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authorCatalin Marinas <catalin.marinas@arm.com>2011-11-22 12:30:28 -0500
committerCatalin Marinas <catalin.marinas@arm.com>2011-12-08 05:30:37 -0500
commit8d2cd3a38fd663bd341507f5ac29002ffd81d986 (patch)
tree9205cf509841c64af8de8bbedceece8524e80d36
parent136848d4ca9cf6f08edf6e50cb9bbe19de55c32a (diff)
ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S
This patch modifies the proc-v7.S file so that it only contains code shared between classic MMU and LPAE. The non-common code is factored out into a separate file. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat
-rw-r--r--arch/arm/mm/proc-v7-2level.S171
-rw-r--r--arch/arm/mm/proc-v7.S152
2 files changed, 174 insertions, 149 deletions
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
new file mode 100644
index 000000000000..3a4b3e7b888c
--- /dev/null
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -0,0 +1,171 @@
1/*
2 * arch/arm/mm/proc-v7-2level.S
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define TTB_S (1 << 1)
12#define TTB_RGN_NC (0 << 3)
13#define TTB_RGN_OC_WBWA (1 << 3)
14#define TTB_RGN_OC_WT (2 << 3)
15#define TTB_RGN_OC_WB (3 << 3)
16#define TTB_NOS (1 << 5)
17#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
18#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
19#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
20#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
21
22/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
23#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
24#define PMD_FLAGS_UP PMD_SECT_WB
25
26/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
27#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
28#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
29
30/*
31 * cpu_v7_switch_mm(pgd_phys, tsk)
32 *
33 * Set the translation table base pointer to be pgd_phys
34 *
35 * - pgd_phys - physical address of new TTB
36 *
37 * It is assumed that:
38 * - we are not using split page tables
39 */
40ENTRY(cpu_v7_switch_mm)
41#ifdef CONFIG_MMU
42 mov r2, #0
43 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
44 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
45 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
46#ifdef CONFIG_ARM_ERRATA_430973
47 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
48#endif
49#ifdef CONFIG_ARM_ERRATA_754322
50 dsb
51#endif
52 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
53 isb
541: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
55 isb
56#ifdef CONFIG_ARM_ERRATA_754322
57 dsb
58#endif
59 mcr p15, 0, r1, c13, c0, 1 @ set context ID
60 isb
61#endif
62 mov pc, lr
63ENDPROC(cpu_v7_switch_mm)
64
65/*
66 * cpu_v7_set_pte_ext(ptep, pte)
67 *
68 * Set a level 2 translation table entry.
69 *
70 * - ptep - pointer to level 2 translation table entry
71 * (hardware version is stored at +2048 bytes)
72 * - pte - PTE value to store
73 * - ext - value for extended PTE bits
74 */
75ENTRY(cpu_v7_set_pte_ext)
76#ifdef CONFIG_MMU
77 str r1, [r0] @ linux version
78
79 bic r3, r1, #0x000003f0
80 bic r3, r3, #PTE_TYPE_MASK
81 orr r3, r3, r2
82 orr r3, r3, #PTE_EXT_AP0 | 2
83
84 tst r1, #1 << 4
85 orrne r3, r3, #PTE_EXT_TEX(1)
86
87 eor r1, r1, #L_PTE_DIRTY
88 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
89 orrne r3, r3, #PTE_EXT_APX
90
91 tst r1, #L_PTE_USER
92 orrne r3, r3, #PTE_EXT_AP1
93#ifdef CONFIG_CPU_USE_DOMAINS
94 @ allow kernel read/write access to read-only user pages
95 tstne r3, #PTE_EXT_APX
96 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
97#endif
98
99 tst r1, #L_PTE_XN
100 orrne r3, r3, #PTE_EXT_XN
101
102 tst r1, #L_PTE_YOUNG
103 tstne r1, #L_PTE_PRESENT
104 moveq r3, #0
105
106 ARM( str r3, [r0, #2048]! )
107 THUMB( add r0, r0, #2048 )
108 THUMB( str r3, [r0] )
109 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
110#endif
111 mov pc, lr
112ENDPROC(cpu_v7_set_pte_ext)
113
114 /*
115 * Memory region attributes with SCTLR.TRE=1
116 *
117 * n = TEX[0],C,B
118 * TR = PRRR[2n+1:2n] - memory type
119 * IR = NMRR[2n+1:2n] - inner cacheable property
120 * OR = NMRR[2n+17:2n+16] - outer cacheable property
121 *
122 * n TR IR OR
123 * UNCACHED 000 00
124 * BUFFERABLE 001 10 00 00
125 * WRITETHROUGH 010 10 10 10
126 * WRITEBACK 011 10 11 11
127 * reserved 110
128 * WRITEALLOC 111 10 01 01
129 * DEV_SHARED 100 01
130 * DEV_NONSHARED 100 01
131 * DEV_WC 001 10
132 * DEV_CACHED 011 10
133 *
134 * Other attributes:
135 *
136 * DS0 = PRRR[16] = 0 - device shareable property
137 * DS1 = PRRR[17] = 1 - device shareable property
138 * NS0 = PRRR[18] = 0 - normal shareable property
139 * NS1 = PRRR[19] = 1 - normal shareable property
140 * NOS = PRRR[24+n] = 1 - not outer shareable
141 */
142.equ PRRR, 0xff0a81a8
143.equ NMRR, 0x40e040e0
144
145 /*
146 * Macro for setting up the TTBRx and TTBCR registers.
147 * - \ttb0 and \ttb1 updated with the corresponding flags.
148 */
149 .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp
150 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
151 ALT_SMP(orr \ttbr0, \ttbr0, #TTB_FLAGS_SMP)
152 ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP)
153 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
154 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
155 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
156 .endm
157
158 __CPUINIT
159
160 /* AT
161 * TFR EV X F I D LR S
162 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
163 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
164 * 1 0 110 0011 1100 .111 1101 < we want
165 */
166 .align 2
167 .type v7_crval, #object
168v7_crval:
169 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
170
171 .previous
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 66a185f018a0..ed1a4d115331 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -19,24 +19,7 @@
19 19
20#include "proc-macros.S" 20#include "proc-macros.S"
21 21
22#define TTB_S (1 << 1) 22#include "proc-v7-2level.S"
23#define TTB_RGN_NC (0 << 3)
24#define TTB_RGN_OC_WBWA (1 << 3)
25#define TTB_RGN_OC_WT (2 << 3)
26#define TTB_RGN_OC_WB (3 << 3)
27#define TTB_NOS (1 << 5)
28#define TTB_IRGN_NC ((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32
33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
35#define PMD_FLAGS_UP PMD_SECT_WB
36
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
40 23
41ENTRY(cpu_v7_proc_init) 24ENTRY(cpu_v7_proc_init)
42 mov pc, lr 25 mov pc, lr
@@ -99,124 +82,9 @@ ENTRY(cpu_v7_dcache_clean_area)
99 mov pc, lr 82 mov pc, lr
100ENDPROC(cpu_v7_dcache_clean_area) 83ENDPROC(cpu_v7_dcache_clean_area)
101 84
102/*
103 * cpu_v7_switch_mm(pgd_phys, tsk)
104 *
105 * Set the translation table base pointer to be pgd_phys
106 *
107 * - pgd_phys - physical address of new TTB
108 *
109 * It is assumed that:
110 * - we are not using split page tables
111 */
112ENTRY(cpu_v7_switch_mm)
113#ifdef CONFIG_MMU
114 mov r2, #0
115 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
116 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
117 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
118#ifdef CONFIG_ARM_ERRATA_430973
119 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
120#endif
121#ifdef CONFIG_ARM_ERRATA_754322
122 dsb
123#endif
124 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
125 isb
1261: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
127 isb
128#ifdef CONFIG_ARM_ERRATA_754322
129 dsb
130#endif
131 mcr p15, 0, r1, c13, c0, 1 @ set context ID
132 isb
133#endif
134 mov pc, lr
135ENDPROC(cpu_v7_switch_mm)
136
137/*
138 * cpu_v7_set_pte_ext(ptep, pte)
139 *
140 * Set a level 2 translation table entry.
141 *
142 * - ptep - pointer to level 2 translation table entry
143 * (hardware version is stored at +2048 bytes)
144 * - pte - PTE value to store
145 * - ext - value for extended PTE bits
146 */
147ENTRY(cpu_v7_set_pte_ext)
148#ifdef CONFIG_MMU
149 str r1, [r0] @ linux version
150
151 bic r3, r1, #0x000003f0
152 bic r3, r3, #PTE_TYPE_MASK
153 orr r3, r3, r2
154 orr r3, r3, #PTE_EXT_AP0 | 2
155
156 tst r1, #1 << 4
157 orrne r3, r3, #PTE_EXT_TEX(1)
158
159 eor r1, r1, #L_PTE_DIRTY
160 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY
161 orrne r3, r3, #PTE_EXT_APX
162
163 tst r1, #L_PTE_USER
164 orrne r3, r3, #PTE_EXT_AP1
165#ifdef CONFIG_CPU_USE_DOMAINS
166 @ allow kernel read/write access to read-only user pages
167 tstne r3, #PTE_EXT_APX
168 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
169#endif
170
171 tst r1, #L_PTE_XN
172 orrne r3, r3, #PTE_EXT_XN
173
174 tst r1, #L_PTE_YOUNG
175 tstne r1, #L_PTE_PRESENT
176 moveq r3, #0
177
178 ARM( str r3, [r0, #2048]! )
179 THUMB( add r0, r0, #2048 )
180 THUMB( str r3, [r0] )
181 mcr p15, 0, r0, c7, c10, 1 @ flush_pte
182#endif
183 mov pc, lr
184ENDPROC(cpu_v7_set_pte_ext)
185
186 string cpu_v7_name, "ARMv7 Processor" 85 string cpu_v7_name, "ARMv7 Processor"
187 .align 86 .align
188 87
189 /*
190 * Memory region attributes with SCTLR.TRE=1
191 *
192 * n = TEX[0],C,B
193 * TR = PRRR[2n+1:2n] - memory type
194 * IR = NMRR[2n+1:2n] - inner cacheable property
195 * OR = NMRR[2n+17:2n+16] - outer cacheable property
196 *
197 * n TR IR OR
198 * UNCACHED 000 00
199 * BUFFERABLE 001 10 00 00
200 * WRITETHROUGH 010 10 10 10
201 * WRITEBACK 011 10 11 11
202 * reserved 110
203 * WRITEALLOC 111 10 01 01
204 * DEV_SHARED 100 01
205 * DEV_NONSHARED 100 01
206 * DEV_WC 001 10
207 * DEV_CACHED 011 10
208 *
209 * Other attributes:
210 *
211 * DS0 = PRRR[16] = 0 - device shareable property
212 * DS1 = PRRR[17] = 1 - device shareable property
213 * NS0 = PRRR[18] = 0 - normal shareable property
214 * NS1 = PRRR[19] = 1 - normal shareable property
215 * NOS = PRRR[24+n] = 1 - not outer shareable
216 */
217.equ PRRR, 0xff0a81a8
218.equ NMRR, 0x40e040e0
219
220/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 88/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
221.globl cpu_v7_suspend_size 89.globl cpu_v7_suspend_size
222.equ cpu_v7_suspend_size, 4 * 7 90.equ cpu_v7_suspend_size, 4 * 7
@@ -379,12 +247,7 @@ __v7_setup:
379 dsb 247 dsb
380#ifdef CONFIG_MMU 248#ifdef CONFIG_MMU
381 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 249 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
382 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 250 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
383 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
384 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
385 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
386 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
387 mcr p15, 0, r8, c2, c0, 1 @ load TTB1
388 ldr r5, =PRRR @ PRRR 251 ldr r5, =PRRR @ PRRR
389 ldr r6, =NMRR @ NMRR 252 ldr r6, =NMRR @ NMRR
390 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 253 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
@@ -406,16 +269,7 @@ __v7_setup:
406 mov pc, lr @ return to head.S:__ret 269 mov pc, lr @ return to head.S:__ret
407ENDPROC(__v7_setup) 270ENDPROC(__v7_setup)
408 271
409 /* AT 272 .align 2
410 * TFR EV X F I D LR S
411 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
412 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
413 * 1 0 110 0011 1100 .111 1101 < we want
414 */
415 .type v7_crval, #object
416v7_crval:
417 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
418
419__v7_setup_stack: 273__v7_setup_stack:
420 .space 4 * 11 @ 11 registers 274 .space 4 * 11 @ 11 registers
421 275
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