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authorMarek Vasut <marex@denx.de>2012-08-03 11:26:06 -0400
committerMark Brown <broonie@opensource.wolfsonmicro.com>2012-08-17 17:52:14 -0400
commit8be3d3b2ac87955455c7ce852e0d489cb04fff59 (patch)
tree6c4f0004758832fc795ec8cbc4db4859d8eb061f
parentd9875690d9b89a866022ff49e3fcea892345ad92 (diff)
mmc: spi: Move SSP register definitions into separate file
Move the definitions into separate file so separate SPI driver can be implemented. The SSP controller in MXS can act both as a MMC host and as a SPI host. Based on previous attempt by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Chris Ball <cjb@laptop.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat
-rw-r--r--drivers/mmc/host/mxs-mmc.c87
-rw-r--r--include/linux/spi/mxs-spi.h109
2 files changed, 112 insertions, 84 deletions
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c
index a51f9309ffbb..26c95dc87cb2 100644
--- a/drivers/mmc/host/mxs-mmc.c
+++ b/drivers/mmc/host/mxs-mmc.c
@@ -45,87 +45,10 @@
45#include <linux/pinctrl/consumer.h> 45#include <linux/pinctrl/consumer.h>
46#include <linux/stmp_device.h> 46#include <linux/stmp_device.h>
47#include <linux/mmc/mxs-mmc.h> 47#include <linux/mmc/mxs-mmc.h>
48#include <linux/spi/mxs-spi.h>
48 49
49#define DRIVER_NAME "mxs-mmc" 50#define DRIVER_NAME "mxs-mmc"
50 51
51/* card detect polling timeout */
52#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
53
54#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
55
56/* SSP registers */
57#define HW_SSP_CTRL0 0x000
58#define BM_SSP_CTRL0_RUN (1 << 29)
59#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
60#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
61#define BM_SSP_CTRL0_READ (1 << 25)
62#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
63#define BP_SSP_CTRL0_BUS_WIDTH (22)
64#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
65#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
66#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
67#define BM_SSP_CTRL0_GET_RESP (1 << 17)
68#define BM_SSP_CTRL0_ENABLE (1 << 16)
69#define BP_SSP_CTRL0_XFER_COUNT (0)
70#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
71#define HW_SSP_CMD0 0x010
72#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
73#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
74#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
75#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
76#define BP_SSP_CMD0_BLOCK_SIZE (16)
77#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
78#define BP_SSP_CMD0_BLOCK_COUNT (8)
79#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
80#define BP_SSP_CMD0_CMD (0)
81#define BM_SSP_CMD0_CMD (0xff)
82#define HW_SSP_CMD1 0x020
83#define HW_SSP_XFER_SIZE 0x030
84#define HW_SSP_BLOCK_SIZE 0x040
85#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
86#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
87#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
88#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
89#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
90#define BP_SSP_TIMING_TIMEOUT (16)
91#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
92#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
93#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
94#define BP_SSP_TIMING_CLOCK_RATE (0)
95#define BM_SSP_TIMING_CLOCK_RATE (0xff)
96#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
97#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
98#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
99#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
100#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
101#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
102#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
103#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
104#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
105#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
106#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
107#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
108#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
109#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
110#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
111#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
112#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
113#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
114#define BM_SSP_CTRL1_POLARITY (1 << 9)
115#define BP_SSP_CTRL1_WORD_LENGTH (4)
116#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
117#define BP_SSP_CTRL1_SSP_MODE (0)
118#define BM_SSP_CTRL1_SSP_MODE (0xf)
119#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
120#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
121#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
122#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
123#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
124#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
125#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
126
127#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
128
129#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \ 52#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
130 BM_SSP_CTRL1_RESP_ERR_IRQ | \ 53 BM_SSP_CTRL1_RESP_ERR_IRQ | \
131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \ 54 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
@@ -135,12 +58,8 @@
135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \ 58 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ) 59 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
137 60
138#define SSP_PIO_NUM 3 61/* card detect polling timeout */
139 62#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
140enum mxs_mmc_id {
141 IMX23_MMC,
142 IMX28_MMC,
143};
144 63
145struct mxs_mmc_host { 64struct mxs_mmc_host {
146 struct mmc_host *mmc; 65 struct mmc_host *mmc;
diff --git a/include/linux/spi/mxs-spi.h b/include/linux/spi/mxs-spi.h
new file mode 100644
index 000000000000..b7ccd577f758
--- /dev/null
+++ b/include/linux/spi/mxs-spi.h
@@ -0,0 +1,109 @@
1/*
2 * include/linux/spi/mxs-spi.h
3 *
4 * Freescale i.MX233/i.MX28 SPI controller register definition
5 *
6 * Copyright 2008 Embedded Alley Solutions, Inc.
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 */
23
24#ifndef __LINUX_SPI_MXS_SPI_H__
25#define __LINUX_SPI_MXS_SPI_H__
26
27#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
28
29/* SSP registers */
30#define HW_SSP_CTRL0 0x000
31#define BM_SSP_CTRL0_RUN (1 << 29)
32#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
33#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
34#define BM_SSP_CTRL0_READ (1 << 25)
35#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
36#define BP_SSP_CTRL0_BUS_WIDTH 22
37#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
38#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
39#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
40#define BM_SSP_CTRL0_GET_RESP (1 << 17)
41#define BM_SSP_CTRL0_ENABLE (1 << 16)
42#define BP_SSP_CTRL0_XFER_COUNT 0
43#define BM_SSP_CTRL0_XFER_COUNT 0xffff
44#define HW_SSP_CMD0 0x010
45#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
46#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
47#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
48#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
49#define BP_SSP_CMD0_BLOCK_SIZE 16
50#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
51#define BP_SSP_CMD0_BLOCK_COUNT 8
52#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
53#define BP_SSP_CMD0_CMD 0
54#define BM_SSP_CMD0_CMD 0xff
55#define HW_SSP_CMD1 0x020
56#define HW_SSP_XFER_SIZE 0x030
57#define HW_SSP_BLOCK_SIZE 0x040
58#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
59#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
60#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
61#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
62#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
63#define BP_SSP_TIMING_TIMEOUT 16
64#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
65#define BP_SSP_TIMING_CLOCK_DIVIDE 8
66#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
67#define BP_SSP_TIMING_CLOCK_RATE 0
68#define BM_SSP_TIMING_CLOCK_RATE 0xff
69#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
70#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
71#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
72#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
73#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
74#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
75#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
76#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
77#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
78#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
79#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
80#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
81#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
82#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
83#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
84#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
85#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
86#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
87#define BM_SSP_CTRL1_POLARITY (1 << 9)
88#define BP_SSP_CTRL1_WORD_LENGTH 4
89#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
90#define BP_SSP_CTRL1_SSP_MODE 0
91#define BM_SSP_CTRL1_SSP_MODE 0xf
92#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
93#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
94#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
95#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
96#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
97#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
98#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
99
100#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
101
102#define SSP_PIO_NUM 3
103
104enum mxs_mmc_id {
105 IMX23_MMC,
106 IMX28_MMC,
107};
108
109#endif /* __LINUX_SPI_MXS_SPI_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 04:25:07 -0500