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authorSantosh Yaraganavi <santoshsy@gmail.com>2012-02-29 01:41:50 -0500
committerJames Bottomley <JBottomley@Parallels.com>2012-03-27 03:26:28 -0400
commit7a3e97b0dc4bbac2ba7803564ab0057722689921 (patch)
treeace32dfcc94a0994b123cc1e3b3967eccd9a0ef3
parent0bd7f84211ad244607e28e9e8fbad0244d54e6f5 (diff)
[SCSI] ufshcd: UFS Host controller driver
This patch adds support for Universal Flash Storage(UFS) host controllers. The UFS host controller driver includes host controller initialization method. The Initialization process involves following steps: - Initiate UFS Host Controller initialization process by writing to Host controller enable register - Configure UFS Host controller registers with host memory space datastructure offsets. - Unipro link startup procedure - Check for connected device - Configure UFS host controller to process requests - Enable required interrupts - Configure interrupt aggregation [jejb: fix warnings in 32 bit compile] Signed-off-by: Santosh Yaraganavi <santoshsy@gmail.com> Signed-off-by: Vinayak Holikatti <vinholikatti@gmail.com> Reviewed-by: Arnd Bergmann <arnd@linaro.org> Reviewed-by: Vishak G <vishak.g@samsung.com> Reviewed-by: Girish K S <girish.shivananjappa@linaro.org> Reviewed-by: Namjae Jeon <linkinjeon@gmail.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Diffstat
-rw-r--r--Documentation/scsi/00-INDEX2
-rw-r--r--Documentation/scsi/ufs.txt133
-rw-r--r--drivers/scsi/Kconfig1
-rw-r--r--drivers/scsi/Makefile1
-rw-r--r--drivers/scsi/ufs/Kconfig49
-rw-r--r--drivers/scsi/ufs/Makefile2
-rw-r--r--drivers/scsi/ufs/ufs.h207
-rw-r--r--drivers/scsi/ufs/ufshcd.c1978
-rw-r--r--drivers/scsi/ufs/ufshci.h376
9 files changed, 2749 insertions, 0 deletions
diff --git a/Documentation/scsi/00-INDEX b/Documentation/scsi/00-INDEX
index b48ded55b555..b7dd6502bec5 100644
--- a/Documentation/scsi/00-INDEX
+++ b/Documentation/scsi/00-INDEX
@@ -94,3 +94,5 @@ sym53c8xx_2.txt
94 - info on second generation driver for sym53c8xx based adapters 94 - info on second generation driver for sym53c8xx based adapters
95tmscsim.txt 95tmscsim.txt
96 - info on driver for AM53c974 based adapters 96 - info on driver for AM53c974 based adapters
97ufs.txt
98 - info on Universal Flash Storage(UFS) and UFS host controller driver.
diff --git a/Documentation/scsi/ufs.txt b/Documentation/scsi/ufs.txt
new file mode 100644
index 000000000000..41a6164592aa
--- /dev/null
+++ b/Documentation/scsi/ufs.txt
@@ -0,0 +1,133 @@
1 Universal Flash Storage
2 =======================
3
4
5Contents
6--------
7
81. Overview
92. UFS Architecture Overview
10 2.1 Application Layer
11 2.2 UFS Transport Protocol(UTP) layer
12 2.3 UFS Interconnect(UIC) Layer
133. UFSHCD Overview
14 3.1 UFS controller initialization
15 3.2 UTP Transfer requests
16 3.3 UFS error handling
17 3.4 SCSI Error handling
18
19
201. Overview
21-----------
22
23Universal Flash Storage(UFS) is a storage specification for flash devices.
24It is aimed to provide a universal storage interface for both
25embedded and removable flash memory based storage in mobile
26devices such as smart phones and tablet computers. The specification
27is defined by JEDEC Solid State Technology Association. UFS is based
28on MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the
29physical layer and MIPI Unipro as the link layer.
30
31The main goals of UFS is to provide,
32 * Optimized performance:
33 For UFS version 1.0 and 1.1 the target performance is as follows,
34 Support for Gear1 is mandatory (rate A: 1248Mbps, rate B: 1457.6Mbps)
35 Support for Gear2 is optional (rate A: 2496Mbps, rate B: 2915.2Mbps)
36 Future version of the standard,
37 Gear3 (rate A: 4992Mbps, rate B: 5830.4Mbps)
38 * Low power consumption
39 * High random IOPs and low latency
40
41
422. UFS Architecture Overview
43----------------------------
44
45UFS has a layered communication architecture which is based on SCSI
46SAM-5 architectural model.
47
48UFS communication architecture consists of following layers,
49
502.1 Application Layer
51
52 The Application layer is composed of UFS command set layer(UCS),
53 Task Manager and Device manager. The UFS interface is designed to be
54 protocol agnostic, however SCSI has been selected as a baseline
55 protocol for versions 1.0 and 1.1 of UFS protocol layer.
56 UFS supports subset of SCSI commands defined by SPC-4 and SBC-3.
57 * UCS: It handles SCSI commands supported by UFS specification.
58 * Task manager: It handles task management functions defined by the
59 UFS which are meant for command queue control.
60 * Device manager: It handles device level operations and device
61 configuration operations. Device level operations mainly involve
62 device power management operations and commands to Interconnect
63 layers. Device level configurations involve handling of query
64 requests which are used to modify and retrieve configuration
65 information of the device.
66
672.2 UFS Transport Protocol(UTP) layer
68
69 UTP layer provides services for
70 the higher layers through Service Access Points. UTP defines 3
71 service access points for higher layers.
72 * UDM_SAP: Device manager service access point is exposed to device
73 manager for device level operations. These device level operations
74 are done through query requests.
75 * UTP_CMD_SAP: Command service access point is exposed to UFS command
76 set layer(UCS) to transport commands.
77 * UTP_TM_SAP: Task management service access point is exposed to task
78 manager to transport task management functions.
79 UTP transports messages through UFS protocol information unit(UPIU).
80
812.3 UFS Interconnect(UIC) Layer
82
83 UIC is the lowest layer of UFS layered architecture. It handles
84 connection between UFS host and UFS device. UIC consists of
85 MIPI UniPro and MIPI M-PHY. UIC provides 2 service access points
86 to upper layer,
87 * UIC_SAP: To transport UPIU between UFS host and UFS device.
88 * UIO_SAP: To issue commands to Unipro layers.
89
90
913. UFSHCD Overview
92------------------
93
94The UFS host controller driver is based on Linux SCSI Framework.
95UFSHCD is a low level device driver which acts as an interface between
96SCSI Midlayer and PCIe based UFS host controllers.
97
98The current UFSHCD implementation supports following functionality,
99
1003.1 UFS controller initialization
101
102 The initialization module brings UFS host controller to active state
103 and prepares the controller to transfer commands/response between
104 UFSHCD and UFS device.
105
1063.2 UTP Transfer requests
107
108 Transfer request handling module of UFSHCD receives SCSI commands
109 from SCSI Midlayer, forms UPIUs and issues the UPIUs to UFS Host
110 controller. Also, the module decodes, responses received from UFS
111 host controller in the form of UPIUs and intimates the SCSI Midlayer
112 of the status of the command.
113
1143.3 UFS error handling
115
116 Error handling module handles Host controller fatal errors,
117 Device fatal errors and UIC interconnect layer related errors.
118
1193.4 SCSI Error handling
120
121 This is done through UFSHCD SCSI error handling routines registered
122 with SCSI Midlayer. Examples of some of the error handling commands
123 issues by SCSI Midlayer are Abort task, Lun reset and host reset.
124 UFSHCD Routines to perform these tasks are registered with
125 SCSI Midlayer through .eh_abort_handler, .eh_device_reset_handler and
126 .eh_host_reset_handler.
127
128In this version of UFSHCD Query requests and power management
129functionality are not implemented.
130
131UFS Specifications can be found at,
132UFS - http://www.jedec.org/sites/default/files/docs/JESD220.pdf
133UFSHCI - http://www.jedec.org/sites/default/files/docs/JESD223.pdf
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 827ebaf4a4a2..af479aa4f494 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -619,6 +619,7 @@ config SCSI_ARCMSR
619 619
620source "drivers/scsi/megaraid/Kconfig.megaraid" 620source "drivers/scsi/megaraid/Kconfig.megaraid"
621source "drivers/scsi/mpt2sas/Kconfig" 621source "drivers/scsi/mpt2sas/Kconfig"
622source "drivers/scsi/ufs/Kconfig"
622 623
623config SCSI_HPTIOP 624config SCSI_HPTIOP
624 tristate "HighPoint RocketRAID 3xxx/4xxx Controller support" 625 tristate "HighPoint RocketRAID 3xxx/4xxx Controller support"
diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile
index 351b28b3d7df..d469816942f4 100644
--- a/drivers/scsi/Makefile
+++ b/drivers/scsi/Makefile
@@ -108,6 +108,7 @@ obj-$(CONFIG_MEGARAID_LEGACY) += megaraid.o
108obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/ 108obj-$(CONFIG_MEGARAID_NEWGEN) += megaraid/
109obj-$(CONFIG_MEGARAID_SAS) += megaraid/ 109obj-$(CONFIG_MEGARAID_SAS) += megaraid/
110obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas/ 110obj-$(CONFIG_SCSI_MPT2SAS) += mpt2sas/
111obj-$(CONFIG_SCSI_UFSHCD) += ufs/
111obj-$(CONFIG_SCSI_ACARD) += atp870u.o 112obj-$(CONFIG_SCSI_ACARD) += atp870u.o
112obj-$(CONFIG_SCSI_SUNESP) += esp_scsi.o sun_esp.o 113obj-$(CONFIG_SCSI_SUNESP) += esp_scsi.o sun_esp.o
113obj-$(CONFIG_SCSI_GDTH) += gdth.o 114obj-$(CONFIG_SCSI_GDTH) += gdth.o
diff --git a/drivers/scsi/ufs/Kconfig b/drivers/scsi/ufs/Kconfig
new file mode 100644
index 000000000000..8f27f9d6f91d
--- /dev/null
+++ b/drivers/scsi/ufs/Kconfig
@@ -0,0 +1,49 @@
1#
2# Kernel configuration file for the UFS Host Controller
3#
4# This code is based on drivers/scsi/ufs/Kconfig
5# Copyright (C) 2011 Samsung Samsung India Software Operations
6#
7# Santosh Yaraganavi <santosh.sy@samsung.com>
8# Vinayak Holikatti <h.vinayak@samsung.com>
9
10# This program is free software; you can redistribute it and/or
11# modify it under the terms of the GNU General Public License
12# as published by the Free Software Foundation; either version 2
13# of the License, or (at your option) any later version.
14
15# This program is distributed in the hope that it will be useful,
16# but WITHOUT ANY WARRANTY; without even the implied warranty of
17# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18# GNU General Public License for more details.
19
20# NO WARRANTY
21# THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23# LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24# MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25# solely responsible for determining the appropriateness of using and
26# distributing the Program and assumes all risks associated with its
27# exercise of rights under this Agreement, including but not limited to
28# the risks and costs of program errors, damage to or loss of data,
29# programs or equipment, and unavailability or interruption of operations.
30
31# DISCLAIMER OF LIABILITY
32# NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34# DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37# USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38# HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40# You should have received a copy of the GNU General Public License
41# along with this program; if not, write to the Free Software
42# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43# USA.
44
45config SCSI_UFSHCD
46 tristate "Universal Flash Storage host controller driver"
47 depends on PCI && SCSI
48 ---help---
49 This is a generic driver which supports PCIe UFS Host controllers.
diff --git a/drivers/scsi/ufs/Makefile b/drivers/scsi/ufs/Makefile
new file mode 100644
index 000000000000..adf7895a6a91
--- /dev/null
+++ b/drivers/scsi/ufs/Makefile
@@ -0,0 +1,2 @@
1# UFSHCD makefile
2obj-$(CONFIG_SCSI_UFSHCD) += ufshcd.o
diff --git a/drivers/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
new file mode 100644
index 000000000000..b207529f8d54
--- /dev/null
+++ b/drivers/scsi/ufs/ufs.h
@@ -0,0 +1,207 @@
1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufs.h
5 * Copyright (C) 2011-2012 Samsung India Software Operations
6 *
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
46#ifndef _UFS_H
47#define _UFS_H
48
49#define MAX_CDB_SIZE 16
50
51#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
52 ((byte3 << 24) | (byte2 << 16) |\
53 (byte1 << 8) | (byte0))
54
55/*
56 * UFS Protocol Information Unit related definitions
57 */
58
59/* Task management functions */
60enum {
61 UFS_ABORT_TASK = 0x01,
62 UFS_ABORT_TASK_SET = 0x02,
63 UFS_CLEAR_TASK_SET = 0x04,
64 UFS_LOGICAL_RESET = 0x08,
65 UFS_QUERY_TASK = 0x80,
66 UFS_QUERY_TASK_SET = 0x81,
67};
68
69/* UTP UPIU Transaction Codes Initiator to Target */
70enum {
71 UPIU_TRANSACTION_NOP_OUT = 0x00,
72 UPIU_TRANSACTION_COMMAND = 0x01,
73 UPIU_TRANSACTION_DATA_OUT = 0x02,
74 UPIU_TRANSACTION_TASK_REQ = 0x04,
75 UPIU_TRANSACTION_QUERY_REQ = 0x26,
76};
77
78/* UTP UPIU Transaction Codes Target to Initiator */
79enum {
80 UPIU_TRANSACTION_NOP_IN = 0x20,
81 UPIU_TRANSACTION_RESPONSE = 0x21,
82 UPIU_TRANSACTION_DATA_IN = 0x22,
83 UPIU_TRANSACTION_TASK_RSP = 0x24,
84 UPIU_TRANSACTION_READY_XFER = 0x31,
85 UPIU_TRANSACTION_QUERY_RSP = 0x36,
86};
87
88/* UPIU Read/Write flags */
89enum {
90 UPIU_CMD_FLAGS_NONE = 0x00,
91 UPIU_CMD_FLAGS_WRITE = 0x20,
92 UPIU_CMD_FLAGS_READ = 0x40,
93};
94
95/* UPIU Task Attributes */
96enum {
97 UPIU_TASK_ATTR_SIMPLE = 0x00,
98 UPIU_TASK_ATTR_ORDERED = 0x01,
99 UPIU_TASK_ATTR_HEADQ = 0x02,
100 UPIU_TASK_ATTR_ACA = 0x03,
101};
102
103/* UTP QUERY Transaction Specific Fields OpCode */
104enum {
105 UPIU_QUERY_OPCODE_NOP = 0x0,
106 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
107 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
108 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
109 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
110 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
111 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
112 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
113 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
114};
115
116/* UTP Transfer Request Command Type (CT) */
117enum {
118 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
119 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
120 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
121};
122
123enum {
124 MASK_SCSI_STATUS = 0xFF,
125 MASK_TASK_RESPONSE = 0xFF00,
126 MASK_RSP_UPIU_RESULT = 0xFFFF,
127};
128
129/* Task management service response */
130enum {
131 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
132 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
133 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
134 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
135 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
136};
137/**
138 * struct utp_upiu_header - UPIU header structure
139 * @dword_0: UPIU header DW-0
140 * @dword_1: UPIU header DW-1
141 * @dword_2: UPIU header DW-2
142 */
143struct utp_upiu_header {
144 u32 dword_0;
145 u32 dword_1;
146 u32 dword_2;
147};
148
149/**
150 * struct utp_upiu_cmd - Command UPIU structure
151 * @header: UPIU header structure DW-0 to DW-2
152 * @data_transfer_len: Data Transfer Length DW-3
153 * @cdb: Command Descriptor Block CDB DW-4 to DW-7
154 */
155struct utp_upiu_cmd {
156 struct utp_upiu_header header;
157 u32 exp_data_transfer_len;
158 u8 cdb[MAX_CDB_SIZE];
159};
160
161/**
162 * struct utp_upiu_rsp - Response UPIU structure
163 * @header: UPIU header DW-0 to DW-2
164 * @residual_transfer_count: Residual transfer count DW-3
165 * @reserved: Reserved double words DW-4 to DW-7
166 * @sense_data_len: Sense data length DW-8 U16
167 * @sense_data: Sense data field DW-8 to DW-12
168 */
169struct utp_upiu_rsp {
170 struct utp_upiu_header header;
171 u32 residual_transfer_count;
172 u32 reserved[4];
173 u16 sense_data_len;
174 u8 sense_data[18];
175};
176
177/**
178 * struct utp_upiu_task_req - Task request UPIU structure
179 * @header - UPIU header structure DW0 to DW-2
180 * @input_param1: Input parameter 1 DW-3
181 * @input_param2: Input parameter 2 DW-4
182 * @input_param3: Input parameter 3 DW-5
183 * @reserved: Reserved double words DW-6 to DW-7
184 */
185struct utp_upiu_task_req {
186 struct utp_upiu_header header;
187 u32 input_param1;
188 u32 input_param2;
189 u32 input_param3;
190 u32 reserved[2];
191};
192
193/**
194 * struct utp_upiu_task_rsp - Task Management Response UPIU structure
195 * @header: UPIU header structure DW0-DW-2
196 * @output_param1: Ouput parameter 1 DW3
197 * @output_param2: Output parameter 2 DW4
198 * @reserved: Reserved double words DW-5 to DW-7
199 */
200struct utp_upiu_task_rsp {
201 struct utp_upiu_header header;
202 u32 output_param1;
203 u32 output_param2;
204 u32 reserved[3];
205};
206
207#endif /* End of Header */
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
new file mode 100644
index 000000000000..52b96e8bf92e
--- /dev/null
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -0,0 +1,1978 @@
1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshcd.c
5 * Copyright (C) 2011-2012 Samsung India Software Operations
6 *
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
46#include <linux/module.h>
47#include <linux/kernel.h>
48#include <linux/init.h>
49#include <linux/pci.h>
50#include <linux/interrupt.h>
51#include <linux/io.h>
52#include <linux/delay.h>
53#include <linux/slab.h>
54#include <linux/spinlock.h>
55#include <linux/workqueue.h>
56#include <linux/errno.h>
57#include <linux/types.h>
58#include <linux/wait.h>
59#include <linux/bitops.h>
60
61#include <asm/irq.h>
62#include <asm/byteorder.h>
63#include <scsi/scsi.h>
64#include <scsi/scsi_cmnd.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi_tcq.h>
67#include <scsi/scsi_dbg.h>
68#include <scsi/scsi_eh.h>
69
70#include "ufs.h"
71#include "ufshci.h"
72
73#define UFSHCD "ufshcd"
74#define UFSHCD_DRIVER_VERSION "0.1"
75
76enum {
77 UFSHCD_MAX_CHANNEL = 0,
78 UFSHCD_MAX_ID = 1,
79 UFSHCD_MAX_LUNS = 8,
80 UFSHCD_CMD_PER_LUN = 32,
81 UFSHCD_CAN_QUEUE = 32,
82};
83
84/* UFSHCD states */
85enum {
86 UFSHCD_STATE_OPERATIONAL,
87 UFSHCD_STATE_RESET,
88 UFSHCD_STATE_ERROR,
89};
90
91/* Interrupt configuration options */
92enum {
93 UFSHCD_INT_DISABLE,
94 UFSHCD_INT_ENABLE,
95 UFSHCD_INT_CLEAR,
96};
97
98/* Interrupt aggregation options */
99enum {
100 INT_AGGR_RESET,
101 INT_AGGR_CONFIG,
102};
103
104/**
105 * struct uic_command - UIC command structure
106 * @command: UIC command
107 * @argument1: UIC command argument 1
108 * @argument2: UIC command argument 2
109 * @argument3: UIC command argument 3
110 * @cmd_active: Indicate if UIC command is outstanding
111 * @result: UIC command result
112 */
113struct uic_command {
114 u32 command;
115 u32 argument1;
116 u32 argument2;
117 u32 argument3;
118 int cmd_active;
119 int result;
120};
121
122/**
123 * struct ufs_hba - per adapter private structure
124 * @mmio_base: UFSHCI base register address
125 * @ucdl_base_addr: UFS Command Descriptor base address
126 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
127 * @utmrdl_base_addr: UTP Task Management Descriptor base address
128 * @ucdl_dma_addr: UFS Command Descriptor DMA address
129 * @utrdl_dma_addr: UTRDL DMA address
130 * @utmrdl_dma_addr: UTMRDL DMA address
131 * @host: Scsi_Host instance of the driver
132 * @pdev: PCI device handle
133 * @lrb: local reference block
134 * @outstanding_tasks: Bits representing outstanding task requests
135 * @outstanding_reqs: Bits representing outstanding transfer requests
136 * @capabilities: UFS Controller Capabilities
137 * @nutrs: Transfer Request Queue depth supported by controller
138 * @nutmrs: Task Management Queue depth supported by controller
139 * @active_uic_cmd: handle of active UIC command
140 * @ufshcd_tm_wait_queue: wait queue for task management
141 * @tm_condition: condition variable for task management
142 * @ufshcd_state: UFSHCD states
143 * @int_enable_mask: Interrupt Mask Bits
144 * @uic_workq: Work queue for UIC completion handling
145 * @feh_workq: Work queue for fatal controller error handling
146 * @errors: HBA errors
147 */
148struct ufs_hba {
149 void __iomem *mmio_base;
150
151 /* Virtual memory reference */
152 struct utp_transfer_cmd_desc *ucdl_base_addr;
153 struct utp_transfer_req_desc *utrdl_base_addr;
154 struct utp_task_req_desc *utmrdl_base_addr;
155
156 /* DMA memory reference */
157 dma_addr_t ucdl_dma_addr;
158 dma_addr_t utrdl_dma_addr;
159 dma_addr_t utmrdl_dma_addr;
160
161 struct Scsi_Host *host;
162 struct pci_dev *pdev;
163
164 struct ufshcd_lrb *lrb;
165
166 unsigned long outstanding_tasks;
167 unsigned long outstanding_reqs;
168
169 u32 capabilities;
170 int nutrs;
171 int nutmrs;
172 u32 ufs_version;
173
174 struct uic_command active_uic_cmd;
175 wait_queue_head_t ufshcd_tm_wait_queue;
176 unsigned long tm_condition;
177
178 u32 ufshcd_state;
179 u32 int_enable_mask;
180
181 /* Work Queues */
182 struct work_struct uic_workq;
183 struct work_struct feh_workq;
184
185 /* HBA Errors */
186 u32 errors;
187};
188
189/**
190 * struct ufshcd_lrb - local reference block
191 * @utr_descriptor_ptr: UTRD address of the command
192 * @ucd_cmd_ptr: UCD address of the command
193 * @ucd_rsp_ptr: Response UPIU address for this command
194 * @ucd_prdt_ptr: PRDT address of the command
195 * @cmd: pointer to SCSI command
196 * @sense_buffer: pointer to sense buffer address of the SCSI command
197 * @sense_bufflen: Length of the sense buffer
198 * @scsi_status: SCSI status of the command
199 * @command_type: SCSI, UFS, Query.
200 * @task_tag: Task tag of the command
201 * @lun: LUN of the command
202 */
203struct ufshcd_lrb {
204 struct utp_transfer_req_desc *utr_descriptor_ptr;
205 struct utp_upiu_cmd *ucd_cmd_ptr;
206 struct utp_upiu_rsp *ucd_rsp_ptr;
207 struct ufshcd_sg_entry *ucd_prdt_ptr;
208
209 struct scsi_cmnd *cmd;
210 u8 *sense_buffer;
211 unsigned int sense_bufflen;
212 int scsi_status;
213
214 int command_type;
215 int task_tag;
216 unsigned int lun;
217};
218
219/**
220 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
221 * @hba - Pointer to adapter instance
222 *
223 * Returns UFSHCI version supported by the controller
224 */
225static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
226{
227 return readl(hba->mmio_base + REG_UFS_VERSION);
228}
229
230/**
231 * ufshcd_is_device_present - Check if any device connected to
232 * the host controller
233 * @reg_hcs - host controller status register value
234 *
235 * Returns 0 if device present, non-zero if no device detected
236 */
237static inline int ufshcd_is_device_present(u32 reg_hcs)
238{
239 return (DEVICE_PRESENT & reg_hcs) ? 0 : -1;
240}
241
242/**
243 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
244 * @lrb: pointer to local command reference block
245 *
246 * This function is used to get the OCS field from UTRD
247 * Returns the OCS field in the UTRD
248 */
249static inline int ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp)
250{
251 return lrbp->utr_descriptor_ptr->header.dword_2 & MASK_OCS;
252}
253
254/**
255 * ufshcd_get_tmr_ocs - Get the UTMRD Overall Command Status
256 * @task_req_descp: pointer to utp_task_req_desc structure
257 *
258 * This function is used to get the OCS field from UTMRD
259 * Returns the OCS field in the UTMRD
260 */
261static inline int
262ufshcd_get_tmr_ocs(struct utp_task_req_desc *task_req_descp)
263{
264 return task_req_descp->header.dword_2 & MASK_OCS;
265}
266
267/**
268 * ufshcd_get_tm_free_slot - get a free slot for task management request
269 * @hba: per adapter instance
270 *
271 * Returns maximum number of task management request slots in case of
272 * task management queue full or returns the free slot number
273 */
274static inline int ufshcd_get_tm_free_slot(struct ufs_hba *hba)
275{
276 return find_first_zero_bit(&hba->outstanding_tasks, hba->nutmrs);
277}
278
279/**
280 * ufshcd_utrl_clear - Clear a bit in UTRLCLR register
281 * @hba: per adapter instance
282 * @pos: position of the bit to be cleared
283 */
284static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 pos)
285{
286 writel(~(1 << pos),
287 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_CLEAR));
288}
289
290/**
291 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
292 * @reg: Register value of host controller status
293 *
294 * Returns integer, 0 on Success and positive value if failed
295 */
296static inline int ufshcd_get_lists_status(u32 reg)
297{
298 /*
299 * The mask 0xFF is for the following HCS register bits
300 * Bit Description
301 * 0 Device Present
302 * 1 UTRLRDY
303 * 2 UTMRLRDY
304 * 3 UCRDY
305 * 4 HEI
306 * 5 DEI
307 * 6-7 reserved
308 */
309 return (((reg) & (0xFF)) >> 1) ^ (0x07);
310}
311
312/**
313 * ufshcd_get_uic_cmd_result - Get the UIC command result
314 * @hba: Pointer to adapter instance
315 *
316 * This function gets the result of UIC command completion
317 * Returns 0 on success, non zero value on error
318 */
319static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
320{
321 return readl(hba->mmio_base + REG_UIC_COMMAND_ARG_2) &
322 MASK_UIC_COMMAND_RESULT;
323}
324
325/**
326 * ufshcd_free_hba_memory - Free allocated memory for LRB, request
327 * and task lists
328 * @hba: Pointer to adapter instance
329 */
330static inline void ufshcd_free_hba_memory(struct ufs_hba *hba)
331{
332 size_t utmrdl_size, utrdl_size, ucdl_size;
333
334 kfree(hba->lrb);
335
336 if (hba->utmrdl_base_addr) {
337 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
338 dma_free_coherent(&hba->pdev->dev, utmrdl_size,
339 hba->utmrdl_base_addr, hba->utmrdl_dma_addr);
340 }
341
342 if (hba->utrdl_base_addr) {
343 utrdl_size =
344 (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
345 dma_free_coherent(&hba->pdev->dev, utrdl_size,
346 hba->utrdl_base_addr, hba->utrdl_dma_addr);
347 }
348
349 if (hba->ucdl_base_addr) {
350 ucdl_size =
351 (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
352 dma_free_coherent(&hba->pdev->dev, ucdl_size,
353 hba->ucdl_base_addr, hba->ucdl_dma_addr);
354 }
355}
356
357/**
358 * ufshcd_is_valid_req_rsp - checks if controller TR response is valid
359 * @ucd_rsp_ptr: pointer to response UPIU
360 *
361 * This function checks the response UPIU for valid transaction type in
362 * response field
363 * Returns 0 on success, non-zero on failure
364 */
365static inline int
366ufshcd_is_valid_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
367{
368 return ((be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24) ==
369 UPIU_TRANSACTION_RESPONSE) ? 0 : DID_ERROR << 16;
370}
371
372/**
373 * ufshcd_get_rsp_upiu_result - Get the result from response UPIU
374 * @ucd_rsp_ptr: pointer to response UPIU
375 *
376 * This function gets the response status and scsi_status from response UPIU
377 * Returns the response result code.
378 */
379static inline int
380ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
381{
382 return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
383}
384
385/**
386 * ufshcd_config_int_aggr - Configure interrupt aggregation values.
387 * Currently there is no use case where we want to configure
388 * interrupt aggregation dynamically. So to configure interrupt
389 * aggregation, #define INT_AGGR_COUNTER_THRESHOLD_VALUE and
390 * INT_AGGR_TIMEOUT_VALUE are used.
391 * @hba: per adapter instance
392 * @option: Interrupt aggregation option
393 */
394static inline void
395ufshcd_config_int_aggr(struct ufs_hba *hba, int option)
396{
397 switch (option) {
398 case INT_AGGR_RESET:
399 writel((INT_AGGR_ENABLE |
400 INT_AGGR_COUNTER_AND_TIMER_RESET),
401 (hba->mmio_base +
402 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
403 break;
404 case INT_AGGR_CONFIG:
405 writel((INT_AGGR_ENABLE |
406 INT_AGGR_PARAM_WRITE |
407 INT_AGGR_COUNTER_THRESHOLD_VALUE |
408 INT_AGGR_TIMEOUT_VALUE),
409 (hba->mmio_base +
410 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL));
411 break;
412 }
413}
414
415/**
416 * ufshcd_enable_run_stop_reg - Enable run-stop registers,
417 * When run-stop registers are set to 1, it indicates the
418 * host controller that it can process the requests
419 * @hba: per adapter instance
420 */
421static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
422{
423 writel(UTP_TASK_REQ_LIST_RUN_STOP_BIT,
424 (hba->mmio_base +
425 REG_UTP_TASK_REQ_LIST_RUN_STOP));
426 writel(UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
427 (hba->mmio_base +
428 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP));
429}
430
431/**
432 * ufshcd_hba_stop - Send controller to reset state
433 * @hba: per adapter instance
434 */
435static inline void ufshcd_hba_stop(struct ufs_hba *hba)
436{
437 writel(CONTROLLER_DISABLE, (hba->mmio_base + REG_CONTROLLER_ENABLE));
438}
439
440/**
441 * ufshcd_hba_start - Start controller initialization sequence
442 * @hba: per adapter instance
443 */
444static inline void ufshcd_hba_start(struct ufs_hba *hba)
445{
446 writel(CONTROLLER_ENABLE , (hba->mmio_base + REG_CONTROLLER_ENABLE));
447}
448
449/**
450 * ufshcd_is_hba_active - Get controller state
451 * @hba: per adapter instance
452 *
453 * Returns zero if controller is active, 1 otherwise
454 */
455static inline int ufshcd_is_hba_active(struct ufs_hba *hba)
456{
457 return (readl(hba->mmio_base + REG_CONTROLLER_ENABLE) & 0x1) ? 0 : 1;
458}
459
460/**
461 * ufshcd_send_command - Send SCSI or device management commands
462 * @hba: per adapter instance
463 * @task_tag: Task tag of the command
464 */
465static inline
466void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
467{
468 __set_bit(task_tag, &hba->outstanding_reqs);
469 writel((1 << task_tag),
470 (hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL));
471}
472
473/**
474 * ufshcd_copy_sense_data - Copy sense data in case of check condition
475 * @lrb - pointer to local reference block
476 */
477static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp)
478{
479 int len;
480 if (lrbp->sense_buffer) {
481 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sense_data_len);
482 memcpy(lrbp->sense_buffer,
483 lrbp->ucd_rsp_ptr->sense_data,
484 min_t(int, len, SCSI_SENSE_BUFFERSIZE));
485 }
486}
487
488/**
489 * ufshcd_hba_capabilities - Read controller capabilities
490 * @hba: per adapter instance
491 */
492static inline void ufshcd_hba_capabilities(struct ufs_hba *hba)
493{
494 hba->capabilities =
495 readl(hba->mmio_base + REG_CONTROLLER_CAPABILITIES);
496
497 /* nutrs and nutmrs are 0 based values */
498 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1;
499 hba->nutmrs =
500 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1;
501}
502
503/**
504 * ufshcd_send_uic_command - Send UIC commands to unipro layers
505 * @hba: per adapter instance
506 * @uic_command: UIC command
507 */
508static inline void
509ufshcd_send_uic_command(struct ufs_hba *hba, struct uic_command *uic_cmnd)
510{
511 /* Write Args */
512 writel(uic_cmnd->argument1,
513 (hba->mmio_base + REG_UIC_COMMAND_ARG_1));
514 writel(uic_cmnd->argument2,
515 (hba->mmio_base + REG_UIC_COMMAND_ARG_2));
516 writel(uic_cmnd->argument3,
517 (hba->mmio_base + REG_UIC_COMMAND_ARG_3));
518
519 /* Write UIC Cmd */
520 writel((uic_cmnd->command & COMMAND_OPCODE_MASK),
521 (hba->mmio_base + REG_UIC_COMMAND));
522}
523
524/**
525 * ufshcd_map_sg - Map scatter-gather list to prdt
526 * @lrbp - pointer to local reference block
527 *
528 * Returns 0 in case of success, non-zero value in case of failure
529 */
530static int ufshcd_map_sg(struct ufshcd_lrb *lrbp)
531{
532 struct ufshcd_sg_entry *prd_table;
533 struct scatterlist *sg;
534 struct scsi_cmnd *cmd;
535 int sg_segments;
536 int i;
537
538 cmd = lrbp->cmd;
539 sg_segments = scsi_dma_map(cmd);
540 if (sg_segments < 0)
541 return sg_segments;
542
543 if (sg_segments) {
544 lrbp->utr_descriptor_ptr->prd_table_length =
545 cpu_to_le16((u16) (sg_segments));
546
547 prd_table = (struct ufshcd_sg_entry *)lrbp->ucd_prdt_ptr;
548
549 scsi_for_each_sg(cmd, sg, sg_segments, i) {
550 prd_table[i].size =
551 cpu_to_le32(((u32) sg_dma_len(sg))-1);
552 prd_table[i].base_addr =
553 cpu_to_le32(lower_32_bits(sg->dma_address));
554 prd_table[i].upper_addr =
555 cpu_to_le32(upper_32_bits(sg->dma_address));
556 }
557 } else {
558 lrbp->utr_descriptor_ptr->prd_table_length = 0;
559 }
560
561 return 0;
562}
563
564/**
565 * ufshcd_int_config - enable/disable interrupts
566 * @hba: per adapter instance
567 * @option: interrupt option
568 */
569static void ufshcd_int_config(struct ufs_hba *hba, u32 option)
570{
571 switch (option) {
572 case UFSHCD_INT_ENABLE:
573 writel(hba->int_enable_mask,
574 (hba->mmio_base + REG_INTERRUPT_ENABLE));
575 break;
576 case UFSHCD_INT_DISABLE:
577 if (hba->ufs_version == UFSHCI_VERSION_10)
578 writel(INTERRUPT_DISABLE_MASK_10,
579 (hba->mmio_base + REG_INTERRUPT_ENABLE));
580 else
581 writel(INTERRUPT_DISABLE_MASK_11,
582 (hba->mmio_base + REG_INTERRUPT_ENABLE));
583 break;
584 }
585}
586
587/**
588 * ufshcd_compose_upiu - form UFS Protocol Information Unit(UPIU)
589 * @lrb - pointer to local reference block
590 */
591static void ufshcd_compose_upiu(struct ufshcd_lrb *lrbp)
592{
593 struct utp_transfer_req_desc *req_desc;
594 struct utp_upiu_cmd *ucd_cmd_ptr;
595 u32 data_direction;
596 u32 upiu_flags;
597
598 ucd_cmd_ptr = lrbp->ucd_cmd_ptr;
599 req_desc = lrbp->utr_descriptor_ptr;
600
601 switch (lrbp->command_type) {
602 case UTP_CMD_TYPE_SCSI:
603 if (lrbp->cmd->sc_data_direction == DMA_FROM_DEVICE) {
604 data_direction = UTP_DEVICE_TO_HOST;
605 upiu_flags = UPIU_CMD_FLAGS_READ;
606 } else if (lrbp->cmd->sc_data_direction == DMA_TO_DEVICE) {
607 data_direction = UTP_HOST_TO_DEVICE;
608 upiu_flags = UPIU_CMD_FLAGS_WRITE;
609 } else {
610 data_direction = UTP_NO_DATA_TRANSFER;
611 upiu_flags = UPIU_CMD_FLAGS_NONE;
612 }
613
614 /* Transfer request descriptor header fields */
615 req_desc->header.dword_0 =
616 cpu_to_le32(data_direction | UTP_SCSI_COMMAND);
617
618 /*
619 * assigning invalid value for command status. Controller
620 * updates OCS on command completion, with the command
621 * status
622 */
623 req_desc->header.dword_2 =
624 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
625
626 /* command descriptor fields */
627 ucd_cmd_ptr->header.dword_0 =
628 cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND,
629 upiu_flags,
630 lrbp->lun,
631 lrbp->task_tag));
632 ucd_cmd_ptr->header.dword_1 =
633 cpu_to_be32(
634 UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI,
635 0,
636 0,
637 0));
638
639 /* Total EHS length and Data segment length will be zero */
640 ucd_cmd_ptr->header.dword_2 = 0;
641
642 ucd_cmd_ptr->exp_data_transfer_len =
643 cpu_to_be32(lrbp->cmd->transfersize);
644
645 memcpy(ucd_cmd_ptr->cdb,
646 lrbp->cmd->cmnd,
647 (min_t(unsigned short,
648 lrbp->cmd->cmd_len,
649 MAX_CDB_SIZE)));
650 break;
651 case UTP_CMD_TYPE_DEV_MANAGE:
652 /* For query function implementation */
653 break;
654 case UTP_CMD_TYPE_UFS:
655 /* For UFS native command implementation */
656 break;
657 } /* end of switch */
658}
659
660/**
661 * ufshcd_queuecommand - main entry point for SCSI requests
662 * @cmd: command from SCSI Midlayer
663 * @done: call back function
664 *
665 * Returns 0 for success, non-zero in case of failure
666 */
667static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
668{
669 struct ufshcd_lrb *lrbp;
670 struct ufs_hba *hba;
671 unsigned long flags;
672 int tag;
673 int err = 0;
674
675 hba = shost_priv(host);
676
677 tag = cmd->request->tag;
678
679 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) {
680 err = SCSI_MLQUEUE_HOST_BUSY;
681 goto out;
682 }
683
684 lrbp = &hba->lrb[tag];
685
686 lrbp->cmd = cmd;
687 lrbp->sense_bufflen = SCSI_SENSE_BUFFERSIZE;
688 lrbp->sense_buffer = cmd->sense_buffer;
689 lrbp->task_tag = tag;
690 lrbp->lun = cmd->device->lun;
691
692 lrbp->command_type = UTP_CMD_TYPE_SCSI;
693
694 /* form UPIU before issuing the command */
695 ufshcd_compose_upiu(lrbp);
696 err = ufshcd_map_sg(lrbp);
697 if (err)
698 goto out;
699
700 /* issue command to the controller */
701 spin_lock_irqsave(hba->host->host_lock, flags);
702 ufshcd_send_command(hba, tag);
703 spin_unlock_irqrestore(hba->host->host_lock, flags);
704out:
705 return err;
706}
707
708/**
709 * ufshcd_memory_alloc - allocate memory for host memory space data structures
710 * @hba: per adapter instance
711 *
712 * 1. Allocate DMA memory for Command Descriptor array
713 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT
714 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL).
715 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List
716 * (UTMRDL)
717 * 4. Allocate memory for local reference block(lrb).
718 *
719 * Returns 0 for success, non-zero in case of failure
720 */
721static int ufshcd_memory_alloc(struct ufs_hba *hba)
722{
723 size_t utmrdl_size, utrdl_size, ucdl_size;
724
725 /* Allocate memory for UTP command descriptors */
726 ucdl_size = (sizeof(struct utp_transfer_cmd_desc) * hba->nutrs);
727 hba->ucdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
728 ucdl_size,
729 &hba->ucdl_dma_addr,
730 GFP_KERNEL);
731
732 /*
733 * UFSHCI requires UTP command descriptor to be 128 byte aligned.
734 * make sure hba->ucdl_dma_addr is aligned to PAGE_SIZE
735 * if hba->ucdl_dma_addr is aligned to PAGE_SIZE, then it will
736 * be aligned to 128 bytes as well
737 */
738 if (!hba->ucdl_base_addr ||
739 WARN_ON(hba->ucdl_dma_addr & (PAGE_SIZE - 1))) {
740 dev_err(&hba->pdev->dev,
741 "Command Descriptor Memory allocation failed\n");
742 goto out;
743 }
744
745 /*
746 * Allocate memory for UTP Transfer descriptors
747 * UFSHCI requires 1024 byte alignment of UTRD
748 */
749 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs);
750 hba->utrdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
751 utrdl_size,
752 &hba->utrdl_dma_addr,
753 GFP_KERNEL);
754 if (!hba->utrdl_base_addr ||
755 WARN_ON(hba->utrdl_dma_addr & (PAGE_SIZE - 1))) {
756 dev_err(&hba->pdev->dev,
757 "Transfer Descriptor Memory allocation failed\n");
758 goto out;
759 }
760
761 /*
762 * Allocate memory for UTP Task Management descriptors
763 * UFSHCI requires 1024 byte alignment of UTMRD
764 */
765 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs;
766 hba->utmrdl_base_addr = dma_alloc_coherent(&hba->pdev->dev,
767 utmrdl_size,
768 &hba->utmrdl_dma_addr,
769 GFP_KERNEL);
770 if (!hba->utmrdl_base_addr ||
771 WARN_ON(hba->utmrdl_dma_addr & (PAGE_SIZE - 1))) {
772 dev_err(&hba->pdev->dev,
773 "Task Management Descriptor Memory allocation failed\n");
774 goto out;
775 }
776
777 /* Allocate memory for local reference block */
778 hba->lrb = kcalloc(hba->nutrs, sizeof(struct ufshcd_lrb), GFP_KERNEL);
779 if (!hba->lrb) {
780 dev_err(&hba->pdev->dev, "LRB Memory allocation failed\n");
781 goto out;
782 }
783 return 0;
784out:
785 ufshcd_free_hba_memory(hba);
786 return -ENOMEM;
787}
788
789/**
790 * ufshcd_host_memory_configure - configure local reference block with
791 * memory offsets
792 * @hba: per adapter instance
793 *
794 * Configure Host memory space
795 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA
796 * address.
797 * 2. Update each UTRD with Response UPIU offset, Response UPIU length
798 * and PRDT offset.
799 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT
800 * into local reference block.
801 */
802static void ufshcd_host_memory_configure(struct ufs_hba *hba)
803{
804 struct utp_transfer_cmd_desc *cmd_descp;
805 struct utp_transfer_req_desc *utrdlp;
806 dma_addr_t cmd_desc_dma_addr;
807 dma_addr_t cmd_desc_element_addr;
808 u16 response_offset;
809 u16 prdt_offset;
810 int cmd_desc_size;
811 int i;
812
813 utrdlp = hba->utrdl_base_addr;
814 cmd_descp = hba->ucdl_base_addr;
815
816 response_offset =
817 offsetof(struct utp_transfer_cmd_desc, response_upiu);
818 prdt_offset =
819 offsetof(struct utp_transfer_cmd_desc, prd_table);
820
821 cmd_desc_size = sizeof(struct utp_transfer_cmd_desc);
822 cmd_desc_dma_addr = hba->ucdl_dma_addr;
823
824 for (i = 0; i < hba->nutrs; i++) {
825 /* Configure UTRD with command descriptor base address */
826 cmd_desc_element_addr =
827 (cmd_desc_dma_addr + (cmd_desc_size * i));
828 utrdlp[i].command_desc_base_addr_lo =
829 cpu_to_le32(lower_32_bits(cmd_desc_element_addr));
830 utrdlp[i].command_desc_base_addr_hi =
831 cpu_to_le32(upper_32_bits(cmd_desc_element_addr));
832
833 /* Response upiu and prdt offset should be in double words */
834 utrdlp[i].response_upiu_offset =
835 cpu_to_le16((response_offset >> 2));
836 utrdlp[i].prd_table_offset =
837 cpu_to_le16((prdt_offset >> 2));
838 utrdlp[i].response_upiu_length =
839 cpu_to_le16(ALIGNED_UPIU_SIZE);
840
841 hba->lrb[i].utr_descriptor_ptr = (utrdlp + i);
842 hba->lrb[i].ucd_cmd_ptr =
843 (struct utp_upiu_cmd *)(cmd_descp + i);
844 hba->lrb[i].ucd_rsp_ptr =
845 (struct utp_upiu_rsp *)cmd_descp[i].response_upiu;
846 hba->lrb[i].ucd_prdt_ptr =
847 (struct ufshcd_sg_entry *)cmd_descp[i].prd_table;
848 }
849}
850
851/**
852 * ufshcd_dme_link_startup - Notify Unipro to perform link startup
853 * @hba: per adapter instance
854 *
855 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer,
856 * in order to initialize the Unipro link startup procedure.
857 * Once the Unipro links are up, the device connected to the controller
858 * is detected.
859 *
860 * Returns 0 on success, non-zero value on failure
861 */
862static int ufshcd_dme_link_startup(struct ufs_hba *hba)
863{
864 struct uic_command *uic_cmd;
865 unsigned long flags;
866
867 /* check if controller is ready to accept UIC commands */
868 if (((readl(hba->mmio_base + REG_CONTROLLER_STATUS)) &
869 UIC_COMMAND_READY) == 0x0) {
870 dev_err(&hba->pdev->dev,
871 "Controller not ready"
872 " to accept UIC commands\n");
873 return -EIO;
874 }
875
876 spin_lock_irqsave(hba->host->host_lock, flags);
877
878 /* form UIC command */
879 uic_cmd = &hba->active_uic_cmd;
880 uic_cmd->command = UIC_CMD_DME_LINK_STARTUP;
881 uic_cmd->argument1 = 0;
882 uic_cmd->argument2 = 0;
883 uic_cmd->argument3 = 0;
884
885 /* enable UIC related interrupts */
886 hba->int_enable_mask |= UIC_COMMAND_COMPL;
887 ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
888
889 /* sending UIC commands to controller */
890 ufshcd_send_uic_command(hba, uic_cmd);
891 spin_unlock_irqrestore(hba->host->host_lock, flags);
892 return 0;
893}
894
895/**
896 * ufshcd_make_hba_operational - Make UFS controller operational
897 * @hba: per adapter instance
898 *
899 * To bring UFS host controller to operational state,
900 * 1. Check if device is present
901 * 2. Configure run-stop-registers
902 * 3. Enable required interrupts
903 * 4. Configure interrupt aggregation
904 *
905 * Returns 0 on success, non-zero value on failure
906 */
907static int ufshcd_make_hba_operational(struct ufs_hba *hba)
908{
909 int err = 0;
910 u32 reg;
911
912 /* check if device present */
913 reg = readl((hba->mmio_base + REG_CONTROLLER_STATUS));
914 if (ufshcd_is_device_present(reg)) {
915 dev_err(&hba->pdev->dev, "cc: Device not present\n");
916 err = -ENXIO;
917 goto out;
918 }
919
920 /*
921 * UCRDY, UTMRLDY and UTRLRDY bits must be 1
922 * DEI, HEI bits must be 0
923 */
924 if (!(ufshcd_get_lists_status(reg))) {
925 ufshcd_enable_run_stop_reg(hba);
926 } else {
927 dev_err(&hba->pdev->dev,
928 "Host controller not ready to process requests");
929 err = -EIO;
930 goto out;
931 }
932
933 /* Enable required interrupts */
934 hba->int_enable_mask |= (UTP_TRANSFER_REQ_COMPL |
935 UIC_ERROR |
936 UTP_TASK_REQ_COMPL |
937 DEVICE_FATAL_ERROR |
938 CONTROLLER_FATAL_ERROR |
939 SYSTEM_BUS_FATAL_ERROR);
940 ufshcd_int_config(hba, UFSHCD_INT_ENABLE);
941
942 /* Configure interrupt aggregation */
943 ufshcd_config_int_aggr(hba, INT_AGGR_CONFIG);
944
945 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
946 scsi_unblock_requests(hba->host);
947
948 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL;
949 scsi_scan_host(hba->host);
950out:
951 return err;
952}
953
954/**
955 * ufshcd_hba_enable - initialize the controller
956 * @hba: per adapter instance
957 *
958 * The controller resets itself and controller firmware initialization
959 * sequence kicks off. When controller is ready it will set
960 * the Host Controller Enable bit to 1.
961 *
962 * Returns 0 on success, non-zero value on failure
963 */
964static int ufshcd_hba_enable(struct ufs_hba *hba)
965{
966 int retry;
967
968 /*
969 * msleep of 1 and 5 used in this function might result in msleep(20),
970 * but it was necessary to send the UFS FPGA to reset mode during
971 * development and testing of this driver. msleep can be changed to
972 * mdelay and retry count can be reduced based on the controller.
973 */
974 if (!ufshcd_is_hba_active(hba)) {
975
976 /* change controller state to "reset state" */
977 ufshcd_hba_stop(hba);
978
979 /*
980 * This delay is based on the testing done with UFS host
981 * controller FPGA. The delay can be changed based on the
982 * host controller used.
983 */
984 msleep(5);
985 }
986
987 /* start controller initialization sequence */
988 ufshcd_hba_start(hba);
989
990 /*
991 * To initialize a UFS host controller HCE bit must be set to 1.
992 * During initialization the HCE bit value changes from 1->0->1.
993 * When the host controller completes initialization sequence
994 * it sets the value of HCE bit to 1. The same HCE bit is read back
995 * to check if the controller has completed initialization sequence.
996 * So without this delay the value HCE = 1, set in the previous
997 * instruction might be read back.
998 * This delay can be changed based on the controller.
999 */
1000 msleep(1);
1001
1002 /* wait for the host controller to complete initialization */
1003 retry = 10;
1004 while (ufshcd_is_hba_active(hba)) {
1005 if (retry) {
1006 retry--;
1007 } else {
1008 dev_err(&hba->pdev->dev,
1009 "Controller enable failed\n");
1010 return -EIO;
1011 }
1012 msleep(5);
1013 }
1014 return 0;
1015}
1016
1017/**
1018 * ufshcd_initialize_hba - start the initialization process
1019 * @hba: per adapter instance
1020 *
1021 * 1. Enable the controller via ufshcd_hba_enable.
1022 * 2. Program the Transfer Request List Address with the starting address of
1023 * UTRDL.
1024 * 3. Program the Task Management Request List Address with starting address
1025 * of UTMRDL.
1026 *
1027 * Returns 0 on success, non-zero value on failure.
1028 */
1029static int ufshcd_initialize_hba(struct ufs_hba *hba)
1030{
1031 if (ufshcd_hba_enable(hba))
1032 return -EIO;
1033
1034 /* Configure UTRL and UTMRL base address registers */
1035 writel(hba->utrdl_dma_addr,
1036 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_L));
1037 writel(lower_32_bits(hba->utrdl_dma_addr),
1038 (hba->mmio_base + REG_UTP_TRANSFER_REQ_LIST_BASE_H));
1039 writel(hba->utmrdl_dma_addr,
1040 (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_L));
1041 writel(upper_32_bits(hba->utmrdl_dma_addr),
1042 (hba->mmio_base + REG_UTP_TASK_REQ_LIST_BASE_H));
1043
1044 /* Initialize unipro link startup procedure */
1045 return ufshcd_dme_link_startup(hba);
1046}
1047
1048/**
1049 * ufshcd_do_reset - reset the host controller
1050 * @hba: per adapter instance
1051 *
1052 * Returns SUCCESS/FAILED
1053 */
1054static int ufshcd_do_reset(struct ufs_hba *hba)
1055{
1056 struct ufshcd_lrb *lrbp;
1057 unsigned long flags;
1058 int tag;
1059
1060 /* block commands from midlayer */
1061 scsi_block_requests(hba->host);
1062
1063 spin_lock_irqsave(hba->host->host_lock, flags);
1064 hba->ufshcd_state = UFSHCD_STATE_RESET;
1065
1066 /* send controller to reset state */
1067 ufshcd_hba_stop(hba);
1068 spin_unlock_irqrestore(hba->host->host_lock, flags);
1069
1070 /* abort outstanding commands */
1071 for (tag = 0; tag < hba->nutrs; tag++) {
1072 if (test_bit(tag, &hba->outstanding_reqs)) {
1073 lrbp = &hba->lrb[tag];
1074 scsi_dma_unmap(lrbp->cmd);
1075 lrbp->cmd->result = DID_RESET << 16;
1076 lrbp->cmd->scsi_done(lrbp->cmd);
1077 lrbp->cmd = NULL;
1078 }
1079 }
1080
1081 /* clear outstanding request/task bit maps */
1082 hba->outstanding_reqs = 0;
1083 hba->outstanding_tasks = 0;
1084
1085 /* start the initialization process */
1086 if (ufshcd_initialize_hba(hba)) {
1087 dev_err(&hba->pdev->dev,
1088 "Reset: Controller initialization failed\n");
1089 return FAILED;
1090 }
1091 return SUCCESS;
1092}
1093
1094/**
1095 * ufshcd_slave_alloc - handle initial SCSI device configurations
1096 * @sdev: pointer to SCSI device
1097 *
1098 * Returns success
1099 */
1100static int ufshcd_slave_alloc(struct scsi_device *sdev)
1101{
1102 struct ufs_hba *hba;
1103
1104 hba = shost_priv(sdev->host);
1105 sdev->tagged_supported = 1;
1106
1107 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */
1108 sdev->use_10_for_ms = 1;
1109 scsi_set_tag_type(sdev, MSG_SIMPLE_TAG);
1110
1111 /*
1112 * Inform SCSI Midlayer that the LUN queue depth is same as the
1113 * controller queue depth. If a LUN queue depth is less than the
1114 * controller queue depth and if the LUN reports
1115 * SAM_STAT_TASK_SET_FULL, the LUN queue depth will be adjusted
1116 * with scsi_adjust_queue_depth.
1117 */
1118 scsi_activate_tcq(sdev, hba->nutrs);
1119 return 0;
1120}
1121
1122/**
1123 * ufshcd_slave_destroy - remove SCSI device configurations
1124 * @sdev: pointer to SCSI device
1125 */
1126static void ufshcd_slave_destroy(struct scsi_device *sdev)
1127{
1128 struct ufs_hba *hba;
1129
1130 hba = shost_priv(sdev->host);
1131 scsi_deactivate_tcq(sdev, hba->nutrs);
1132}
1133
1134/**
1135 * ufshcd_task_req_compl - handle task management request completion
1136 * @hba: per adapter instance
1137 * @index: index of the completed request
1138 *
1139 * Returns SUCCESS/FAILED
1140 */
1141static int ufshcd_task_req_compl(struct ufs_hba *hba, u32 index)
1142{
1143 struct utp_task_req_desc *task_req_descp;
1144 struct utp_upiu_task_rsp *task_rsp_upiup;
1145 unsigned long flags;
1146 int ocs_value;
1147 int task_result;
1148
1149 spin_lock_irqsave(hba->host->host_lock, flags);
1150
1151 /* Clear completed tasks from outstanding_tasks */
1152 __clear_bit(index, &hba->outstanding_tasks);
1153
1154 task_req_descp = hba->utmrdl_base_addr;
1155 ocs_value = ufshcd_get_tmr_ocs(&task_req_descp[index]);
1156
1157 if (ocs_value == OCS_SUCCESS) {
1158 task_rsp_upiup = (struct utp_upiu_task_rsp *)
1159 task_req_descp[index].task_rsp_upiu;
1160 task_result = be32_to_cpu(task_rsp_upiup->header.dword_1);
1161 task_result = ((task_result & MASK_TASK_RESPONSE) >> 8);
1162
1163 if (task_result != UPIU_TASK_MANAGEMENT_FUNC_COMPL ||
1164 task_result != UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED)
1165 task_result = FAILED;
1166 } else {
1167 task_result = FAILED;
1168 dev_err(&hba->pdev->dev,
1169 "trc: Invalid ocs = %x\n", ocs_value);
1170 }
1171 spin_unlock_irqrestore(hba->host->host_lock, flags);
1172 return task_result;
1173}
1174
1175/**
1176 * ufshcd_adjust_lun_qdepth - Update LUN queue depth if device responds with
1177 * SAM_STAT_TASK_SET_FULL SCSI command status.
1178 * @cmd: pointer to SCSI command
1179 */
1180static void ufshcd_adjust_lun_qdepth(struct scsi_cmnd *cmd)
1181{
1182 struct ufs_hba *hba;
1183 int i;
1184 int lun_qdepth = 0;
1185
1186 hba = shost_priv(cmd->device->host);
1187
1188 /*
1189 * LUN queue depth can be obtained by counting outstanding commands
1190 * on the LUN.
1191 */
1192 for (i = 0; i < hba->nutrs; i++) {
1193 if (test_bit(i, &hba->outstanding_reqs)) {
1194
1195 /*
1196 * Check if the outstanding command belongs
1197 * to the LUN which reported SAM_STAT_TASK_SET_FULL.
1198 */
1199 if (cmd->device->lun == hba->lrb[i].lun)
1200 lun_qdepth++;
1201 }
1202 }
1203
1204 /*
1205 * LUN queue depth will be total outstanding commands, except the
1206 * command for which the LUN reported SAM_STAT_TASK_SET_FULL.
1207 */
1208 scsi_adjust_queue_depth(cmd->device, MSG_SIMPLE_TAG, lun_qdepth - 1);
1209}
1210
1211/**
1212 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status
1213 * @lrb: pointer to local reference block of completed command
1214 * @scsi_status: SCSI command status
1215 *
1216 * Returns value base on SCSI command status
1217 */
1218static inline int
1219ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status)
1220{
1221 int result = 0;
1222
1223 switch (scsi_status) {
1224 case SAM_STAT_GOOD:
1225 result |= DID_OK << 16 |
1226 COMMAND_COMPLETE << 8 |
1227 SAM_STAT_GOOD;
1228 break;
1229 case SAM_STAT_CHECK_CONDITION:
1230 result |= DID_OK << 16 |
1231 COMMAND_COMPLETE << 8 |
1232 SAM_STAT_CHECK_CONDITION;
1233 ufshcd_copy_sense_data(lrbp);
1234 break;
1235 case SAM_STAT_BUSY:
1236 result |= SAM_STAT_BUSY;
1237 break;
1238 case SAM_STAT_TASK_SET_FULL:
1239
1240 /*
1241 * If a LUN reports SAM_STAT_TASK_SET_FULL, then the LUN queue
1242 * depth needs to be adjusted to the exact number of
1243 * outstanding commands the LUN can handle at any given time.
1244 */
1245 ufshcd_adjust_lun_qdepth(lrbp->cmd);
1246 result |= SAM_STAT_TASK_SET_FULL;
1247 break;
1248 case SAM_STAT_TASK_ABORTED:
1249 result |= SAM_STAT_TASK_ABORTED;
1250 break;
1251 default:
1252 result |= DID_ERROR << 16;
1253 break;
1254 } /* end of switch */
1255
1256 return result;
1257}
1258
1259/**
1260 * ufshcd_transfer_rsp_status - Get overall status of the response
1261 * @hba: per adapter instance
1262 * @lrb: pointer to local reference block of completed command
1263 *
1264 * Returns result of the command to notify SCSI midlayer
1265 */
1266static inline int
1267ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp)
1268{
1269 int result = 0;
1270 int scsi_status;
1271 int ocs;
1272
1273 /* overall command status of utrd */
1274 ocs = ufshcd_get_tr_ocs(lrbp);
1275
1276 switch (ocs) {
1277 case OCS_SUCCESS:
1278
1279 /* check if the returned transfer response is valid */
1280 result = ufshcd_is_valid_req_rsp(lrbp->ucd_rsp_ptr);
1281 if (result) {
1282 dev_err(&hba->pdev->dev,
1283 "Invalid response = %x\n", result);
1284 break;
1285 }
1286
1287 /*
1288 * get the response UPIU result to extract
1289 * the SCSI command status
1290 */
1291 result = ufshcd_get_rsp_upiu_result(lrbp->ucd_rsp_ptr);
1292
1293 /*
1294 * get the result based on SCSI status response
1295 * to notify the SCSI midlayer of the command status
1296 */
1297 scsi_status = result & MASK_SCSI_STATUS;
1298 result = ufshcd_scsi_cmd_status(lrbp, scsi_status);
1299 break;
1300 case OCS_ABORTED:
1301 result |= DID_ABORT << 16;
1302 break;
1303 case OCS_INVALID_CMD_TABLE_ATTR:
1304 case OCS_INVALID_PRDT_ATTR:
1305 case OCS_MISMATCH_DATA_BUF_SIZE:
1306 case OCS_MISMATCH_RESP_UPIU_SIZE:
1307 case OCS_PEER_COMM_FAILURE:
1308 case OCS_FATAL_ERROR:
1309 default:
1310 result |= DID_ERROR << 16;
1311 dev_err(&hba->pdev->dev,
1312 "OCS error from controller = %x\n", ocs);
1313 break;
1314 } /* end of switch */
1315
1316 return result;
1317}
1318
1319/**
1320 * ufshcd_transfer_req_compl - handle SCSI and query command completion
1321 * @hba: per adapter instance
1322 */
1323static void ufshcd_transfer_req_compl(struct ufs_hba *hba)
1324{
1325 struct ufshcd_lrb *lrb;
1326 unsigned long completed_reqs;
1327 u32 tr_doorbell;
1328 int result;
1329 int index;
1330
1331 lrb = hba->lrb;
1332 tr_doorbell =
1333 readl(hba->mmio_base + REG_UTP_TRANSFER_REQ_DOOR_BELL);
1334 completed_reqs = tr_doorbell ^ hba->outstanding_reqs;
1335
1336 for (index = 0; index < hba->nutrs; index++) {
1337 if (test_bit(index, &completed_reqs)) {
1338
1339 result = ufshcd_transfer_rsp_status(hba, &lrb[index]);
1340
1341 if (lrb[index].cmd) {
1342 scsi_dma_unmap(lrb[index].cmd);
1343 lrb[index].cmd->result = result;
1344 lrb[index].cmd->scsi_done(lrb[index].cmd);
1345
1346 /* Mark completed command as NULL in LRB */
1347 lrb[index].cmd = NULL;
1348 }
1349 } /* end of if */
1350 } /* end of for */
1351
1352 /* clear corresponding bits of completed commands */
1353 hba->outstanding_reqs ^= completed_reqs;
1354
1355 /* Reset interrupt aggregation counters */
1356 ufshcd_config_int_aggr(hba, INT_AGGR_RESET);
1357}
1358
1359/**
1360 * ufshcd_uic_cc_handler - handle UIC command completion
1361 * @work: pointer to a work queue structure
1362 *
1363 * Returns 0 on success, non-zero value on failure
1364 */
1365static void ufshcd_uic_cc_handler (struct work_struct *work)
1366{
1367 struct ufs_hba *hba;
1368
1369 hba = container_of(work, struct ufs_hba, uic_workq);
1370
1371 if ((hba->active_uic_cmd.command == UIC_CMD_DME_LINK_STARTUP) &&
1372 !(ufshcd_get_uic_cmd_result(hba))) {
1373
1374 if (ufshcd_make_hba_operational(hba))
1375 dev_err(&hba->pdev->dev,
1376 "cc: hba not operational state\n");
1377 return;
1378 }
1379}
1380
1381/**
1382 * ufshcd_fatal_err_handler - handle fatal errors
1383 * @hba: per adapter instance
1384 */
1385static void ufshcd_fatal_err_handler(struct work_struct *work)
1386{
1387 struct ufs_hba *hba;
1388 hba = container_of(work, struct ufs_hba, feh_workq);
1389
1390 /* check if reset is already in progress */
1391 if (hba->ufshcd_state != UFSHCD_STATE_RESET)
1392 ufshcd_do_reset(hba);
1393}
1394
1395/**
1396 * ufshcd_err_handler - Check for fatal errors
1397 * @work: pointer to a work queue structure
1398 */
1399static void ufshcd_err_handler(struct ufs_hba *hba)
1400{
1401 u32 reg;
1402
1403 if (hba->errors & INT_FATAL_ERRORS)
1404 goto fatal_eh;
1405
1406 if (hba->errors & UIC_ERROR) {
1407
1408 reg = readl(hba->mmio_base +
1409 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER);
1410 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
1411 goto fatal_eh;
1412 }
1413 return;
1414fatal_eh:
1415 hba->ufshcd_state = UFSHCD_STATE_ERROR;
1416 schedule_work(&hba->feh_workq);
1417}
1418
1419/**
1420 * ufshcd_tmc_handler - handle task management function completion
1421 * @hba: per adapter instance
1422 */
1423static void ufshcd_tmc_handler(struct ufs_hba *hba)
1424{
1425 u32 tm_doorbell;
1426
1427 tm_doorbell = readl(hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL);
1428 hba->tm_condition = tm_doorbell ^ hba->outstanding_tasks;
1429 wake_up_interruptible(&hba->ufshcd_tm_wait_queue);
1430}
1431
1432/**
1433 * ufshcd_sl_intr - Interrupt service routine
1434 * @hba: per adapter instance
1435 * @intr_status: contains interrupts generated by the controller
1436 */
1437static void ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status)
1438{
1439 hba->errors = UFSHCD_ERROR_MASK & intr_status;
1440 if (hba->errors)
1441 ufshcd_err_handler(hba);
1442
1443 if (intr_status & UIC_COMMAND_COMPL)
1444 schedule_work(&hba->uic_workq);
1445
1446 if (intr_status & UTP_TASK_REQ_COMPL)
1447 ufshcd_tmc_handler(hba);
1448
1449 if (intr_status & UTP_TRANSFER_REQ_COMPL)
1450 ufshcd_transfer_req_compl(hba);
1451}
1452
1453/**
1454 * ufshcd_intr - Main interrupt service routine
1455 * @irq: irq number
1456 * @__hba: pointer to adapter instance
1457 *
1458 * Returns IRQ_HANDLED - If interrupt is valid
1459 * IRQ_NONE - If invalid interrupt
1460 */
1461static irqreturn_t ufshcd_intr(int irq, void *__hba)
1462{
1463 u32 intr_status;
1464 irqreturn_t retval = IRQ_NONE;
1465 struct ufs_hba *hba = __hba;
1466
1467 spin_lock(hba->host->host_lock);
1468 intr_status = readl(hba->mmio_base + REG_INTERRUPT_STATUS);
1469
1470 if (intr_status) {
1471 ufshcd_sl_intr(hba, intr_status);
1472
1473 /* If UFSHCI 1.0 then clear interrupt status register */
1474 if (hba->ufs_version == UFSHCI_VERSION_10)
1475 writel(intr_status,
1476 (hba->mmio_base + REG_INTERRUPT_STATUS));
1477 retval = IRQ_HANDLED;
1478 }
1479 spin_unlock(hba->host->host_lock);
1480 return retval;
1481}
1482
1483/**
1484 * ufshcd_issue_tm_cmd - issues task management commands to controller
1485 * @hba: per adapter instance
1486 * @lrbp: pointer to local reference block
1487 *
1488 * Returns SUCCESS/FAILED
1489 */
1490static int
1491ufshcd_issue_tm_cmd(struct ufs_hba *hba,
1492 struct ufshcd_lrb *lrbp,
1493 u8 tm_function)
1494{
1495 struct utp_task_req_desc *task_req_descp;
1496 struct utp_upiu_task_req *task_req_upiup;
1497 struct Scsi_Host *host;
1498 unsigned long flags;
1499 int free_slot = 0;
1500 int err;
1501
1502 host = hba->host;
1503
1504 spin_lock_irqsave(host->host_lock, flags);
1505
1506 /* If task management queue is full */
1507 free_slot = ufshcd_get_tm_free_slot(hba);
1508 if (free_slot >= hba->nutmrs) {
1509 spin_unlock_irqrestore(host->host_lock, flags);
1510 dev_err(&hba->pdev->dev, "Task management queue full\n");
1511 err = FAILED;
1512 goto out;
1513 }
1514
1515 task_req_descp = hba->utmrdl_base_addr;
1516 task_req_descp += free_slot;
1517
1518 /* Configure task request descriptor */
1519 task_req_descp->header.dword_0 = cpu_to_le32(UTP_REQ_DESC_INT_CMD);
1520 task_req_descp->header.dword_2 =
1521 cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
1522
1523 /* Configure task request UPIU */
1524 task_req_upiup =
1525 (struct utp_upiu_task_req *) task_req_descp->task_req_upiu;
1526 task_req_upiup->header.dword_0 =
1527 cpu_to_be32(UPIU_HEADER_DWORD(UPIU_TRANSACTION_TASK_REQ, 0,
1528 lrbp->lun, lrbp->task_tag));
1529 task_req_upiup->header.dword_1 =
1530 cpu_to_be32(UPIU_HEADER_DWORD(0, tm_function, 0, 0));
1531
1532 task_req_upiup->input_param1 = lrbp->lun;
1533 task_req_upiup->input_param1 =
1534 cpu_to_be32(task_req_upiup->input_param1);
1535 task_req_upiup->input_param2 = lrbp->task_tag;
1536 task_req_upiup->input_param2 =
1537 cpu_to_be32(task_req_upiup->input_param2);
1538
1539 /* send command to the controller */
1540 __set_bit(free_slot, &hba->outstanding_tasks);
1541 writel((1 << free_slot),
1542 (hba->mmio_base + REG_UTP_TASK_REQ_DOOR_BELL));
1543
1544 spin_unlock_irqrestore(host->host_lock, flags);
1545
1546 /* wait until the task management command is completed */
1547 err =
1548 wait_event_interruptible_timeout(hba->ufshcd_tm_wait_queue,
1549 (test_bit(free_slot,
1550 &hba->tm_condition) != 0),
1551 60 * HZ);
1552 if (!err) {
1553 dev_err(&hba->pdev->dev,
1554 "Task management command timed-out\n");
1555 err = FAILED;
1556 goto out;
1557 }
1558 clear_bit(free_slot, &hba->tm_condition);
1559 return ufshcd_task_req_compl(hba, free_slot);
1560out:
1561 return err;
1562}
1563
1564/**
1565 * ufshcd_device_reset - reset device and abort all the pending commands
1566 * @cmd: SCSI command pointer
1567 *
1568 * Returns SUCCESS/FAILED
1569 */
1570static int ufshcd_device_reset(struct scsi_cmnd *cmd)
1571{
1572 struct Scsi_Host *host;
1573 struct ufs_hba *hba;
1574 unsigned int tag;
1575 u32 pos;
1576 int err;
1577
1578 host = cmd->device->host;
1579 hba = shost_priv(host);
1580 tag = cmd->request->tag;
1581
1582 err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_LOGICAL_RESET);
1583 if (err)
1584 goto out;
1585
1586 for (pos = 0; pos < hba->nutrs; pos++) {
1587 if (test_bit(pos, &hba->outstanding_reqs) &&
1588 (hba->lrb[tag].lun == hba->lrb[pos].lun)) {
1589
1590 /* clear the respective UTRLCLR register bit */
1591 ufshcd_utrl_clear(hba, pos);
1592
1593 clear_bit(pos, &hba->outstanding_reqs);
1594
1595 if (hba->lrb[pos].cmd) {
1596 scsi_dma_unmap(hba->lrb[pos].cmd);
1597 hba->lrb[pos].cmd->result =
1598 DID_ABORT << 16;
1599 hba->lrb[pos].cmd->scsi_done(cmd);
1600 hba->lrb[pos].cmd = NULL;
1601 }
1602 }
1603 } /* end of for */
1604out:
1605 return err;
1606}
1607
1608/**
1609 * ufshcd_host_reset - Main reset function registered with scsi layer
1610 * @cmd: SCSI command pointer
1611 *
1612 * Returns SUCCESS/FAILED
1613 */
1614static int ufshcd_host_reset(struct scsi_cmnd *cmd)
1615{
1616 struct ufs_hba *hba;
1617
1618 hba = shost_priv(cmd->device->host);
1619
1620 if (hba->ufshcd_state == UFSHCD_STATE_RESET)
1621 return SUCCESS;
1622
1623 return (ufshcd_do_reset(hba) == SUCCESS) ? SUCCESS : FAILED;
1624}
1625
1626/**
1627 * ufshcd_abort - abort a specific command
1628 * @cmd: SCSI command pointer
1629 *
1630 * Returns SUCCESS/FAILED
1631 */
1632static int ufshcd_abort(struct scsi_cmnd *cmd)
1633{
1634 struct Scsi_Host *host;
1635 struct ufs_hba *hba;
1636 unsigned long flags;
1637 unsigned int tag;
1638 int err;
1639
1640 host = cmd->device->host;
1641 hba = shost_priv(host);
1642 tag = cmd->request->tag;
1643
1644 spin_lock_irqsave(host->host_lock, flags);
1645
1646 /* check if command is still pending */
1647 if (!(test_bit(tag, &hba->outstanding_reqs))) {
1648 err = FAILED;
1649 spin_unlock_irqrestore(host->host_lock, flags);
1650 goto out;
1651 }
1652 spin_unlock_irqrestore(host->host_lock, flags);
1653
1654 err = ufshcd_issue_tm_cmd(hba, &hba->lrb[tag], UFS_ABORT_TASK);
1655 if (err)
1656 goto out;
1657
1658 scsi_dma_unmap(cmd);
1659
1660 spin_lock_irqsave(host->host_lock, flags);
1661
1662 /* clear the respective UTRLCLR register bit */
1663 ufshcd_utrl_clear(hba, tag);
1664
1665 __clear_bit(tag, &hba->outstanding_reqs);
1666 hba->lrb[tag].cmd = NULL;
1667 spin_unlock_irqrestore(host->host_lock, flags);
1668out:
1669 return err;
1670}
1671
1672static struct scsi_host_template ufshcd_driver_template = {
1673 .module = THIS_MODULE,
1674 .name = UFSHCD,
1675 .proc_name = UFSHCD,
1676 .queuecommand = ufshcd_queuecommand,
1677 .slave_alloc = ufshcd_slave_alloc,
1678 .slave_destroy = ufshcd_slave_destroy,
1679 .eh_abort_handler = ufshcd_abort,
1680 .eh_device_reset_handler = ufshcd_device_reset,
1681 .eh_host_reset_handler = ufshcd_host_reset,
1682 .this_id = -1,
1683 .sg_tablesize = SG_ALL,
1684 .cmd_per_lun = UFSHCD_CMD_PER_LUN,
1685 .can_queue = UFSHCD_CAN_QUEUE,
1686};
1687
1688/**
1689 * ufshcd_shutdown - main function to put the controller in reset state
1690 * @pdev: pointer to PCI device handle
1691 */
1692static void ufshcd_shutdown(struct pci_dev *pdev)
1693{
1694 ufshcd_hba_stop((struct ufs_hba *)pci_get_drvdata(pdev));
1695}
1696
1697#ifdef CONFIG_PM
1698/**
1699 * ufshcd_suspend - suspend power management function
1700 * @pdev: pointer to PCI device handle
1701 * @state: power state
1702 *
1703 * Returns -ENOSYS
1704 */
1705static int ufshcd_suspend(struct pci_dev *pdev, pm_message_t state)
1706{
1707 /*
1708 * TODO:
1709 * 1. Block SCSI requests from SCSI midlayer
1710 * 2. Change the internal driver state to non operational
1711 * 3. Set UTRLRSR and UTMRLRSR bits to zero
1712 * 4. Wait until outstanding commands are completed
1713 * 5. Set HCE to zero to send the UFS host controller to reset state
1714 */
1715
1716 return -ENOSYS;
1717}
1718
1719/**
1720 * ufshcd_resume - resume power management function
1721 * @pdev: pointer to PCI device handle
1722 *
1723 * Returns -ENOSYS
1724 */
1725static int ufshcd_resume(struct pci_dev *pdev)
1726{
1727 /*
1728 * TODO:
1729 * 1. Set HCE to 1, to start the UFS host controller
1730 * initialization process
1731 * 2. Set UTRLRSR and UTMRLRSR bits to 1
1732 * 3. Change the internal driver state to operational
1733 * 4. Unblock SCSI requests from SCSI midlayer
1734 */
1735
1736 return -ENOSYS;
1737}
1738#endif /* CONFIG_PM */
1739
1740/**
1741 * ufshcd_hba_free - free allocated memory for
1742 * host memory space data structures
1743 * @hba: per adapter instance
1744 */
1745static void ufshcd_hba_free(struct ufs_hba *hba)
1746{
1747 iounmap(hba->mmio_base);
1748 ufshcd_free_hba_memory(hba);
1749 pci_release_regions(hba->pdev);
1750}
1751
1752/**
1753 * ufshcd_remove - de-allocate PCI/SCSI host and host memory space
1754 * data structure memory
1755 * @pdev - pointer to PCI handle
1756 */
1757static void ufshcd_remove(struct pci_dev *pdev)
1758{
1759 struct ufs_hba *hba = pci_get_drvdata(pdev);
1760
1761 /* disable interrupts */
1762 ufshcd_int_config(hba, UFSHCD_INT_DISABLE);
1763 free_irq(pdev->irq, hba);
1764
1765 ufshcd_hba_stop(hba);
1766 ufshcd_hba_free(hba);
1767
1768 scsi_remove_host(hba->host);
1769 scsi_host_put(hba->host);
1770 pci_set_drvdata(pdev, NULL);
1771 pci_clear_master(pdev);
1772 pci_disable_device(pdev);
1773}
1774
1775/**
1776 * ufshcd_set_dma_mask - Set dma mask based on the controller
1777 * addressing capability
1778 * @pdev: PCI device structure
1779 *
1780 * Returns 0 for success, non-zero for failure
1781 */
1782static int ufshcd_set_dma_mask(struct ufs_hba *hba)
1783{
1784 int err;
1785 u64 dma_mask;
1786
1787 /*
1788 * If controller supports 64 bit addressing mode, then set the DMA
1789 * mask to 64-bit, else set the DMA mask to 32-bit
1790 */
1791 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT)
1792 dma_mask = DMA_BIT_MASK(64);
1793 else
1794 dma_mask = DMA_BIT_MASK(32);
1795
1796 err = pci_set_dma_mask(hba->pdev, dma_mask);
1797 if (err)
1798 return err;
1799
1800 err = pci_set_consistent_dma_mask(hba->pdev, dma_mask);
1801
1802 return err;
1803}
1804
1805/**
1806 * ufshcd_probe - probe routine of the driver
1807 * @pdev: pointer to PCI device handle
1808 * @id: PCI device id
1809 *
1810 * Returns 0 on success, non-zero value on failure
1811 */
1812static int __devinit
1813ufshcd_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1814{
1815 struct Scsi_Host *host;
1816 struct ufs_hba *hba;
1817 int err;
1818
1819 err = pci_enable_device(pdev);
1820 if (err) {
1821 dev_err(&pdev->dev, "pci_enable_device failed\n");
1822 goto out_error;
1823 }
1824
1825 pci_set_master(pdev);
1826
1827 host = scsi_host_alloc(&ufshcd_driver_template,
1828 sizeof(struct ufs_hba));
1829 if (!host) {
1830 dev_err(&pdev->dev, "scsi_host_alloc failed\n");
1831 err = -ENOMEM;
1832 goto out_disable;
1833 }
1834 hba = shost_priv(host);
1835
1836 err = pci_request_regions(pdev, UFSHCD);
1837 if (err < 0) {
1838 dev_err(&pdev->dev, "request regions failed\n");
1839 goto out_disable;
1840 }
1841
1842 hba->mmio_base = pci_ioremap_bar(pdev, 0);
1843 if (!hba->mmio_base) {
1844 dev_err(&pdev->dev, "memory map failed\n");
1845 err = -ENOMEM;
1846 goto out_release_regions;
1847 }
1848
1849 hba->host = host;
1850 hba->pdev = pdev;
1851
1852 /* Read capabilities registers */
1853 ufshcd_hba_capabilities(hba);
1854
1855 /* Get UFS version supported by the controller */
1856 hba->ufs_version = ufshcd_get_ufs_version(hba);
1857
1858 err = ufshcd_set_dma_mask(hba);
1859 if (err) {
1860 dev_err(&pdev->dev, "set dma mask failed\n");
1861 goto out_iounmap;
1862 }
1863
1864 /* Allocate memory for host memory space */
1865 err = ufshcd_memory_alloc(hba);
1866 if (err) {
1867 dev_err(&pdev->dev, "Memory allocation failed\n");
1868 goto out_iounmap;
1869 }
1870
1871 /* Configure LRB */
1872 ufshcd_host_memory_configure(hba);
1873
1874 host->can_queue = hba->nutrs;
1875 host->cmd_per_lun = hba->nutrs;
1876 host->max_id = UFSHCD_MAX_ID;
1877 host->max_lun = UFSHCD_MAX_LUNS;
1878 host->max_channel = UFSHCD_MAX_CHANNEL;
1879 host->unique_id = host->host_no;
1880 host->max_cmd_len = MAX_CDB_SIZE;
1881
1882 /* Initailize wait queue for task management */
1883 init_waitqueue_head(&hba->ufshcd_tm_wait_queue);
1884
1885 /* Initialize work queues */
1886 INIT_WORK(&hba->uic_workq, ufshcd_uic_cc_handler);
1887 INIT_WORK(&hba->feh_workq, ufshcd_fatal_err_handler);
1888
1889 /* IRQ registration */
1890 err = request_irq(pdev->irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba);
1891 if (err) {
1892 dev_err(&pdev->dev, "request irq failed\n");
1893 goto out_lrb_free;
1894 }
1895
1896 /* Enable SCSI tag mapping */
1897 err = scsi_init_shared_tag_map(host, host->can_queue);
1898 if (err) {
1899 dev_err(&pdev->dev, "init shared queue failed\n");
1900 goto out_free_irq;
1901 }
1902
1903 pci_set_drvdata(pdev, hba);
1904
1905 err = scsi_add_host(host, &pdev->dev);
1906 if (err) {
1907 dev_err(&pdev->dev, "scsi_add_host failed\n");
1908 goto out_free_irq;
1909 }
1910
1911 /* Initialization routine */
1912 err = ufshcd_initialize_hba(hba);
1913 if (err) {
1914 dev_err(&pdev->dev, "Initialization failed\n");
1915 goto out_free_irq;
1916 }
1917
1918 return 0;
1919
1920out_free_irq:
1921 free_irq(pdev->irq, hba);
1922out_lrb_free:
1923 ufshcd_free_hba_memory(hba);
1924out_iounmap:
1925 iounmap(hba->mmio_base);
1926out_release_regions:
1927 pci_release_regions(pdev);
1928out_disable:
1929 scsi_host_put(host);
1930 pci_clear_master(pdev);
1931 pci_disable_device(pdev);
1932out_error:
1933 return err;
1934}
1935
1936static DEFINE_PCI_DEVICE_TABLE(ufshcd_pci_tbl) = {
1937 { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1938 { } /* terminate list */
1939};
1940
1941MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl);
1942
1943static struct pci_driver ufshcd_pci_driver = {
1944 .name = UFSHCD,
1945 .id_table = ufshcd_pci_tbl,
1946 .probe = ufshcd_probe,
1947 .remove = __devexit_p(ufshcd_remove),
1948 .shutdown = ufshcd_shutdown,
1949#ifdef CONFIG_PM
1950 .suspend = ufshcd_suspend,
1951 .resume = ufshcd_resume,
1952#endif
1953};
1954
1955/**
1956 * ufshcd_init - Driver registration routine
1957 */
1958static int __init ufshcd_init(void)
1959{
1960 return pci_register_driver(&ufshcd_pci_driver);
1961}
1962module_init(ufshcd_init);
1963
1964/**
1965 * ufshcd_exit - Driver exit clean-up routine
1966 */
1967static void __exit ufshcd_exit(void)
1968{
1969 pci_unregister_driver(&ufshcd_pci_driver);
1970}
1971module_exit(ufshcd_exit);
1972
1973
1974MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>, "
1975 "Vinayak Holikatti <h.vinayak@samsung.com>");
1976MODULE_DESCRIPTION("Generic UFS host controller driver");
1977MODULE_LICENSE("GPL");
1978MODULE_VERSION(UFSHCD_DRIVER_VERSION);
diff --git a/drivers/scsi/ufs/ufshci.h b/drivers/scsi/ufs/ufshci.h
new file mode 100644
index 000000000000..6e3510f71167
--- /dev/null
+++ b/drivers/scsi/ufs/ufshci.h
@@ -0,0 +1,376 @@
1/*
2 * Universal Flash Storage Host controller driver
3 *
4 * This code is based on drivers/scsi/ufs/ufshci.h
5 * Copyright (C) 2011-2012 Samsung India Software Operations
6 *
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * NO WARRANTY
21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
25 * solely responsible for determining the appropriateness of using and
26 * distributing the Program and assumes all risks associated with its
27 * exercise of rights under this Agreement, including but not limited to
28 * the risks and costs of program errors, damage to or loss of data,
29 * programs or equipment, and unavailability or interruption of operations.
30
31 * DISCLAIMER OF LIABILITY
32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
39
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
43 * USA.
44 */
45
46#ifndef _UFSHCI_H
47#define _UFSHCI_H
48
49enum {
50 TASK_REQ_UPIU_SIZE_DWORDS = 8,
51 TASK_RSP_UPIU_SIZE_DWORDS = 8,
52 ALIGNED_UPIU_SIZE = 128,
53};
54
55/* UFSHCI Registers */
56enum {
57 REG_CONTROLLER_CAPABILITIES = 0x00,
58 REG_UFS_VERSION = 0x08,
59 REG_CONTROLLER_DEV_ID = 0x10,
60 REG_CONTROLLER_PROD_ID = 0x14,
61 REG_INTERRUPT_STATUS = 0x20,
62 REG_INTERRUPT_ENABLE = 0x24,
63 REG_CONTROLLER_STATUS = 0x30,
64 REG_CONTROLLER_ENABLE = 0x34,
65 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
66 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
67 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
68 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
69 REG_UIC_ERROR_CODE_DME = 0x48,
70 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
71 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
72 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
73 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
74 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
75 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
76 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
77 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
78 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
79 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
80 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
81 REG_UIC_COMMAND = 0x90,
82 REG_UIC_COMMAND_ARG_1 = 0x94,
83 REG_UIC_COMMAND_ARG_2 = 0x98,
84 REG_UIC_COMMAND_ARG_3 = 0x9C,
85};
86
87/* Controller capability masks */
88enum {
89 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
90 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
91 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
92 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
93 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
94};
95
96/* UFS Version 08h */
97#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
98#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
99
100/* Controller UFSHCI version */
101enum {
102 UFSHCI_VERSION_10 = 0x00010000,
103 UFSHCI_VERSION_11 = 0x00010100,
104};
105
106/*
107 * HCDDID - Host Controller Identification Descriptor
108 * - Device ID and Device Class 10h
109 */
110#define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
111#define DEVICE_ID UFS_MASK(0xFF, 24)
112
113/*
114 * HCPMID - Host Controller Identification Descriptor
115 * - Product/Manufacturer ID 14h
116 */
117#define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
118#define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
119
120#define UFS_BIT(x) (1L << (x))
121
122#define UTP_TRANSFER_REQ_COMPL UFS_BIT(0)
123#define UIC_DME_END_PT_RESET UFS_BIT(1)
124#define UIC_ERROR UFS_BIT(2)
125#define UIC_TEST_MODE UFS_BIT(3)
126#define UIC_POWER_MODE UFS_BIT(4)
127#define UIC_HIBERNATE_EXIT UFS_BIT(5)
128#define UIC_HIBERNATE_ENTER UFS_BIT(6)
129#define UIC_LINK_LOST UFS_BIT(7)
130#define UIC_LINK_STARTUP UFS_BIT(8)
131#define UTP_TASK_REQ_COMPL UFS_BIT(9)
132#define UIC_COMMAND_COMPL UFS_BIT(10)
133#define DEVICE_FATAL_ERROR UFS_BIT(11)
134#define CONTROLLER_FATAL_ERROR UFS_BIT(16)
135#define SYSTEM_BUS_FATAL_ERROR UFS_BIT(17)
136
137#define UFSHCD_ERROR_MASK (UIC_ERROR |\
138 DEVICE_FATAL_ERROR |\
139 CONTROLLER_FATAL_ERROR |\
140 SYSTEM_BUS_FATAL_ERROR)
141
142#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
143 CONTROLLER_FATAL_ERROR |\
144 SYSTEM_BUS_FATAL_ERROR)
145
146/* HCS - Host Controller Status 30h */
147#define DEVICE_PRESENT UFS_BIT(0)
148#define UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1)
149#define UTP_TASK_REQ_LIST_READY UFS_BIT(2)
150#define UIC_COMMAND_READY UFS_BIT(3)
151#define HOST_ERROR_INDICATOR UFS_BIT(4)
152#define DEVICE_ERROR_INDICATOR UFS_BIT(5)
153#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
154
155/* HCE - Host Controller Enable 34h */
156#define CONTROLLER_ENABLE UFS_BIT(0)
157#define CONTROLLER_DISABLE 0x0
158
159/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
160#define UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31)
161#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
162
163/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
164#define UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31)
165#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF
166#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
167
168/* UECN - Host UIC Error Code Network Layer 40h */
169#define UIC_NETWORK_LAYER_ERROR UFS_BIT(31)
170#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
171
172/* UECT - Host UIC Error Code Transport Layer 44h */
173#define UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31)
174#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
175
176/* UECDME - Host UIC Error Code DME 48h */
177#define UIC_DME_ERROR UFS_BIT(31)
178#define UIC_DME_ERROR_CODE_MASK 0x1
179
180#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
181#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
182#define INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16)
183#define INT_AGGR_STATUS_BIT UFS_BIT(20)
184#define INT_AGGR_PARAM_WRITE UFS_BIT(24)
185#define INT_AGGR_ENABLE UFS_BIT(31)
186
187/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
188#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
189
190/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
191#define UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0)
192
193/* UICCMD - UIC Command */
194#define COMMAND_OPCODE_MASK 0xFF
195#define GEN_SELECTOR_INDEX_MASK 0xFFFF
196
197#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
198#define RESET_LEVEL 0xFF
199
200#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
201#define CONFIG_RESULT_CODE_MASK 0xFF
202#define GENERIC_ERROR_CODE_MASK 0xFF
203
204/* UIC Commands */
205enum {
206 UIC_CMD_DME_GET = 0x01,
207 UIC_CMD_DME_SET = 0x02,
208 UIC_CMD_DME_PEER_GET = 0x03,
209 UIC_CMD_DME_PEER_SET = 0x04,
210 UIC_CMD_DME_POWERON = 0x10,
211 UIC_CMD_DME_POWEROFF = 0x11,
212 UIC_CMD_DME_ENABLE = 0x12,
213 UIC_CMD_DME_RESET = 0x14,
214 UIC_CMD_DME_END_PT_RST = 0x15,
215 UIC_CMD_DME_LINK_STARTUP = 0x16,
216 UIC_CMD_DME_HIBER_ENTER = 0x17,
217 UIC_CMD_DME_HIBER_EXIT = 0x18,
218 UIC_CMD_DME_TEST_MODE = 0x1A,
219};
220
221/* UIC Config result code / Generic error code */
222enum {
223 UIC_CMD_RESULT_SUCCESS = 0x00,
224 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
225 UIC_CMD_RESULT_FAILURE = 0x01,
226 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
227 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
228 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
229 UIC_CMD_RESULT_BAD_INDEX = 0x05,
230 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
231 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
232 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
233 UIC_CMD_RESULT_BUSY = 0x09,
234 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
235};
236
237#define MASK_UIC_COMMAND_RESULT 0xFF
238
239#define INT_AGGR_COUNTER_THRESHOLD_VALUE (0x1F << 8)
240#define INT_AGGR_TIMEOUT_VALUE (0x02)
241
242/* Interrupt disable masks */
243enum {
244 /* Interrupt disable mask for UFSHCI v1.0 */
245 INTERRUPT_DISABLE_MASK_10 = 0xFFFF,
246
247 /* Interrupt disable mask for UFSHCI v1.1 */
248 INTERRUPT_DISABLE_MASK_11 = 0x0,
249};
250
251/*
252 * Request Descriptor Definitions
253 */
254
255/* Transfer request command type */
256enum {
257 UTP_CMD_TYPE_SCSI = 0x0,
258 UTP_CMD_TYPE_UFS = 0x1,
259 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
260};
261
262enum {
263 UTP_SCSI_COMMAND = 0x00000000,
264 UTP_NATIVE_UFS_COMMAND = 0x10000000,
265 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
266 UTP_REQ_DESC_INT_CMD = 0x01000000,
267};
268
269/* UTP Transfer Request Data Direction (DD) */
270enum {
271 UTP_NO_DATA_TRANSFER = 0x00000000,
272 UTP_HOST_TO_DEVICE = 0x02000000,
273 UTP_DEVICE_TO_HOST = 0x04000000,
274};
275
276/* Overall command status values */
277enum {
278 OCS_SUCCESS = 0x0,
279 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
280 OCS_INVALID_PRDT_ATTR = 0x2,
281 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
282 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
283 OCS_PEER_COMM_FAILURE = 0x5,
284 OCS_ABORTED = 0x6,
285 OCS_FATAL_ERROR = 0x7,
286 OCS_INVALID_COMMAND_STATUS = 0x0F,
287 MASK_OCS = 0x0F,
288};
289
290/**
291 * struct ufshcd_sg_entry - UFSHCI PRD Entry
292 * @base_addr: Lower 32bit physical address DW-0
293 * @upper_addr: Upper 32bit physical address DW-1
294 * @reserved: Reserved for future use DW-2
295 * @size: size of physical segment DW-3
296 */
297struct ufshcd_sg_entry {
298 u32 base_addr;
299 u32 upper_addr;
300 u32 reserved;
301 u32 size;
302};
303
304/**
305 * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
306 * @command_upiu: Command UPIU Frame address
307 * @response_upiu: Response UPIU Frame address
308 * @prd_table: Physical Region Descriptor
309 */
310struct utp_transfer_cmd_desc {
311 u8 command_upiu[ALIGNED_UPIU_SIZE];
312 u8 response_upiu[ALIGNED_UPIU_SIZE];
313 struct ufshcd_sg_entry prd_table[SG_ALL];
314};
315
316/**
317 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
318 * @dword0: Descriptor Header DW0
319 * @dword1: Descriptor Header DW1
320 * @dword2: Descriptor Header DW2
321 * @dword3: Descriptor Header DW3
322 */
323struct request_desc_header {
324 u32 dword_0;
325 u32 dword_1;
326 u32 dword_2;
327 u32 dword_3;
328};
329
330/**
331 * struct utp_transfer_req_desc - UTRD structure
332 * @header: UTRD header DW-0 to DW-3
333 * @command_desc_base_addr_lo: UCD base address low DW-4
334 * @command_desc_base_addr_hi: UCD base address high DW-5
335 * @response_upiu_length: response UPIU length DW-6
336 * @response_upiu_offset: response UPIU offset DW-6
337 * @prd_table_length: Physical region descriptor length DW-7
338 * @prd_table_offset: Physical region descriptor offset DW-7
339 */
340struct utp_transfer_req_desc {
341
342 /* DW 0-3 */
343 struct request_desc_header header;
344
345 /* DW 4-5*/
346 u32 command_desc_base_addr_lo;
347 u32 command_desc_base_addr_hi;
348
349 /* DW 6 */
350 u16 response_upiu_length;
351 u16 response_upiu_offset;
352
353 /* DW 7 */
354 u16 prd_table_length;
355 u16 prd_table_offset;
356};
357
358/**
359 * struct utp_task_req_desc - UTMRD structure
360 * @header: UTMRD header DW-0 to DW-3
361 * @task_req_upiu: Pointer to task request UPIU DW-4 to DW-11
362 * @task_rsp_upiu: Pointer to task response UPIU DW12 to DW-19
363 */
364struct utp_task_req_desc {
365
366 /* DW 0-3 */
367 struct request_desc_header header;
368
369 /* DW 4-11 */
370 u32 task_req_upiu[TASK_REQ_UPIU_SIZE_DWORDS];
371
372 /* DW 12-19 */
373 u32 task_rsp_upiu[TASK_RSP_UPIU_SIZE_DWORDS];
374};
375
376#endif /* End of Header */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 16:05:41 -0500