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authorMaciej W. Rozycki <macro@linux-mips.org>2005-06-22 16:58:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:30 -0400
commit69c75fb458cd81bb29e1d9580469110b00316748 (patch)
tree6e33ce1ecfb30a83b1b842810ff39a5ba99c4783
parent64dac503e8265007ea5c53b4d6bf42488a8a8d7a (diff)
Actual handlers for bus errors for Pmax and 3min.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c new file mode 100644
Diffstat
-rw-r--r--arch/mips/dec/kn01-berr.c200
-rw-r--r--arch/mips/dec/kn02xa-berr.c138
2 files changed, 338 insertions, 0 deletions
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
new file mode 100644
index 000000000000..8ec7b30a90c1
--- /dev/null
+++ b/arch/mips/dec/kn01-berr.c
@@ -0,0 +1,200 @@
1/*
2 * linux/arch/mips/dec/kn01-berr.c
3 *
4 * Bus error event handling code for DECstation/DECsystem 3100
5 * and 2100 (KN01) systems equipped with parity error detection
6 * logic.
7 *
8 * Copyright (c) 2005 Maciej W. Rozycki
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/spinlock.h>
20#include <linux/types.h>
21
22#include <asm/inst.h>
23#include <asm/mipsregs.h>
24#include <asm/page.h>
25#include <asm/system.h>
26#include <asm/traps.h>
27#include <asm/uaccess.h>
28
29#include <asm/dec/kn01.h>
30
31
32/* CP0 hazard avoidance. */
33#define BARRIER \
34 __asm__ __volatile__( \
35 ".set push\n\t" \
36 ".set noreorder\n\t" \
37 "nop\n\t" \
38 ".set pop\n\t")
39
40/*
41 * Bits 7:0 of the Control Register are write-only -- the
42 * corresponding bits of the Status Register have a different
43 * meaning. Hence we use a cache. It speeds up things a bit
44 * as well.
45 *
46 * There is no default value -- it has to be initialized.
47 */
48u16 cached_kn01_csr;
49DEFINE_SPINLOCK(kn01_lock);
50
51
52static inline void dec_kn01_be_ack(void)
53{
54 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
55 unsigned long flags;
56
57 spin_lock_irqsave(&kn01_lock, flags);
58
59 *csr = cached_kn01_csr | KN01_CSR_MEMERR; /* Clear bus IRQ. */
60 iob();
61
62 spin_unlock_irqrestore(&kn01_lock, flags);
63}
64
65static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
66{
67 volatile u32 *kn01_erraddr = (void *)(KN01_SLOT_BASE + KN01_ERRADDR);
68
69 static const char excstr[] = "exception";
70 static const char intstr[] = "interrupt";
71 static const char cpustr[] = "CPU";
72 static const char mreadstr[] = "memory read";
73 static const char readstr[] = "read";
74 static const char writestr[] = "write";
75 static const char timestr[] = "timeout";
76 static const char paritystr[] = "parity error";
77
78 int data = regs->cp0_cause & 4;
79 unsigned int __user *pc = (unsigned int __user *)regs->cp0_epc +
80 ((regs->cp0_cause & CAUSEF_BD) != 0);
81 union mips_instruction insn;
82 unsigned long entrylo, offset;
83 long asid, entryhi, vaddr;
84
85 const char *kind, *agent, *cycle, *event;
86 unsigned long address;
87
88 u32 erraddr = *kn01_erraddr;
89 int action = MIPS_BE_FATAL;
90
91 /* Ack ASAP, so that any subsequent errors get caught. */
92 dec_kn01_be_ack();
93
94 kind = invoker ? intstr : excstr;
95
96 agent = cpustr;
97
98 if (invoker)
99 address = erraddr;
100 else {
101 /* Bloody hardware doesn't record the address for reads... */
102 if (data) {
103 /* This never faults. */
104 __get_user(insn.word, pc);
105 vaddr = regs->regs[insn.i_format.rs] +
106 insn.i_format.simmediate;
107 } else
108 vaddr = (long)pc;
109 if (KSEGX(vaddr) == CKSEG0 || KSEGX(vaddr) == CKSEG1)
110 address = CPHYSADDR(vaddr);
111 else {
112 /* Peek at what physical address the CPU used. */
113 asid = read_c0_entryhi();
114 entryhi = asid & (PAGE_SIZE - 1);
115 entryhi |= vaddr & ~(PAGE_SIZE - 1);
116 write_c0_entryhi(entryhi);
117 BARRIER;
118 tlb_probe();
119 /* No need to check for presence. */
120 tlb_read();
121 entrylo = read_c0_entrylo0();
122 write_c0_entryhi(asid);
123 offset = vaddr & (PAGE_SIZE - 1);
124 address = (entrylo & ~(PAGE_SIZE - 1)) | offset;
125 }
126 }
127
128 /* Treat low 256MB as memory, high -- as I/O. */
129 if (address < 0x10000000) {
130 cycle = mreadstr;
131 event = paritystr;
132 } else {
133 cycle = invoker ? writestr : readstr;
134 event = timestr;
135 }
136
137 if (is_fixup)
138 action = MIPS_BE_FIXUP;
139
140 if (action != MIPS_BE_FIXUP)
141 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
142 kind, agent, cycle, event, address);
143
144 return action;
145}
146
147int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup)
148{
149 return dec_kn01_be_backend(regs, is_fixup, 0);
150}
151
152irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id,
153 struct pt_regs *regs)
154{
155 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
156 int action;
157
158 if (!(*csr & KN01_CSR_MEMERR))
159 return IRQ_NONE; /* Must have been video. */
160
161 action = dec_kn01_be_backend(regs, 0, 1);
162
163 if (action == MIPS_BE_DISCARD)
164 return IRQ_HANDLED;
165
166 /*
167 * FIXME: Find the affected processes and kill them, otherwise
168 * we must die.
169 *
170 * The interrupt is asynchronously delivered thus EPC and RA
171 * may be irrelevant, but are printed for a reference.
172 */
173 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
174 regs->cp0_epc, regs->regs[31]);
175 die("Unrecoverable bus error", regs);
176}
177
178
179void __init dec_kn01_be_init(void)
180{
181 volatile u16 *csr = (void *)(KN01_SLOT_BASE + KN01_CSR);
182 unsigned long flags;
183
184 spin_lock_irqsave(&kn01_lock, flags);
185
186 /* Preset write-only bits of the Control Register cache. */
187 cached_kn01_csr = *csr;
188 cached_kn01_csr &= KN01_CSR_STATUS | KN01_CSR_PARDIS | KN01_CSR_TXDIS;
189 cached_kn01_csr |= KN01_CSR_LEDS;
190
191 /* Enable parity error detection. */
192 cached_kn01_csr &= ~KN01_CSR_PARDIS;
193 *csr = cached_kn01_csr;
194 iob();
195
196 spin_unlock_irqrestore(&kn01_lock, flags);
197
198 /* Clear any leftover errors from the firmware. */
199 dec_kn01_be_ack();
200}
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
new file mode 100644
index 000000000000..c29909566628
--- /dev/null
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -0,0 +1,138 @@
1/*
2 * linux/arch/mips/dec/kn02xa-berr.c
3 *
4 * Bus error event handling code for 5000-series systems equipped
5 * with parity error detection logic, i.e. DECstation/DECsystem
6 * 5000/120, /125, /133 (KN02-BA), 5000/150 (KN04-BA) and Personal
7 * DECstation/DECsystem 5000/20, /25, /33 (KN02-CA), 5000/50
8 * (KN04-CA) systems.
9 *
10 * Copyright (c) 2005 Maciej W. Rozycki
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/kernel.h>
21#include <linux/types.h>
22
23#include <asm/system.h>
24#include <asm/traps.h>
25
26#include <asm/dec/kn02ca.h>
27#include <asm/dec/kn02xa.h>
28#include <asm/dec/kn05.h>
29
30static inline void dec_kn02xa_be_ack(void)
31{
32 volatile u32 *mer = (void *)KN02XA_MER;
33 volatile u32 *mem_intr = (void *)KN02XA_MEM_INTR;
34
35 *mer = KN02CA_MER_INTR; /* Clear errors; keep the ARC IRQ. */
36 *mem_intr = 0; /* Any write clears the bus IRQ. */
37 iob();
38}
39
40static int dec_kn02xa_be_backend(struct pt_regs *regs, int is_fixup,
41 int invoker)
42{
43 volatile u32 *kn02xa_mer = (void *)KN02XA_MER;
44 volatile u32 *kn02xa_ear = (void *)KN02XA_EAR;
45
46 static const char excstr[] = "exception";
47 static const char intstr[] = "interrupt";
48 static const char cpustr[] = "CPU";
49 static const char mreadstr[] = "memory read";
50 static const char readstr[] = "read";
51 static const char writestr[] = "write";
52 static const char timestr[] = "timeout";
53 static const char paritystr[] = "parity error";
54 static const char lanestat[][4] = { " OK", "BAD" };
55
56 const char *kind, *agent, *cycle, *event;
57 unsigned long address;
58
59 u32 mer = *kn02xa_mer;
60 u32 ear = *kn02xa_ear;
61 int action = MIPS_BE_FATAL;
62
63 /* Ack ASAP, so that any subsequent errors get caught. */
64 dec_kn02xa_be_ack();
65
66 kind = invoker ? intstr : excstr;
67
68 /* No DMA errors? */
69 agent = cpustr;
70
71 address = ear & KN02XA_EAR_ADDRESS;
72
73 /* Low 256MB is decoded as memory, high -- as TC. */
74 if (address < 0x10000000) {
75 cycle = mreadstr;
76 event = paritystr;
77 } else {
78 cycle = invoker ? writestr : readstr;
79 event = timestr;
80 }
81
82 if (is_fixup)
83 action = MIPS_BE_FIXUP;
84
85 if (action != MIPS_BE_FIXUP)
86 printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
87 kind, agent, cycle, event, address);
88
89 if (action != MIPS_BE_FIXUP && address < 0x10000000)
90 printk(KERN_ALERT " Byte lane status %#3x -- "
91 "#3: %s, #2: %s, #1: %s, #0: %s\n",
92 (mer & KN02XA_MER_BYTERR) >> 8,
93 lanestat[(mer & KN02XA_MER_BYTERR_3) != 0],
94 lanestat[(mer & KN02XA_MER_BYTERR_2) != 0],
95 lanestat[(mer & KN02XA_MER_BYTERR_1) != 0],
96 lanestat[(mer & KN02XA_MER_BYTERR_0) != 0]);
97
98 return action;
99}
100
101int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup)
102{
103 return dec_kn02xa_be_backend(regs, is_fixup, 0);
104}
105
106irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id,
107 struct pt_regs *regs)
108{
109 int action = dec_kn02xa_be_backend(regs, 0, 1);
110
111 if (action == MIPS_BE_DISCARD)
112 return IRQ_HANDLED;
113
114 /*
115 * FIXME: Find the affected processes and kill them, otherwise
116 * we must die.
117 *
118 * The interrupt is asynchronously delivered thus EPC and RA
119 * may be irrelevant, but are printed for a reference.
120 */
121 printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
122 regs->cp0_epc, regs->regs[31]);
123 die("Unrecoverable bus error", regs);
124}
125
126
127void __init dec_kn02xa_be_init(void)
128{
129 volatile u32 *mbcs = (void *)(KN4K_SLOT_BASE + KN4K_MB_CSR);
130
131 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
132 if (current_cpu_data.cputype == CPU_R4000SC)
133 *mbcs |= KN4K_MB_CSR_EE;
134 fast_iob();
135
136 /* Clear any leftover errors from the firmware. */
137 dec_kn02xa_be_ack();
138}
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