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authorVasanthakumar Thiagarajan <vasanth@atheros.com>2010-12-06 07:27:53 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-12-07 16:34:59 -0500
commit5f139eba4174d9a3343efc7cfb8a0a9cb184c647 (patch)
tree8b276842e0e2c0ad1490b3212afa63d5be30cefc
parentdd040f76cef0cc977b83e905a16b68d41322b735 (diff)
ath9k_hw: Configure power control only for the supported chains
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_eeprom.c28
1 files changed, 16 insertions, 12 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index 76508f82f859..1f5aa51b9cef 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -4260,23 +4260,27 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
4260 REG_RMW(ah, AR_PHY_TPC_11_B0, 4260 REG_RMW(ah, AR_PHY_TPC_11_B0,
4261 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4261 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4262 AR_PHY_TPC_OLPC_GAIN_DELTA); 4262 AR_PHY_TPC_OLPC_GAIN_DELTA);
4263 REG_RMW(ah, AR_PHY_TPC_11_B1, 4263 if (ah->caps.tx_chainmask & BIT(1))
4264 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4264 REG_RMW(ah, AR_PHY_TPC_11_B1,
4265 AR_PHY_TPC_OLPC_GAIN_DELTA); 4265 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4266 REG_RMW(ah, AR_PHY_TPC_11_B2, 4266 AR_PHY_TPC_OLPC_GAIN_DELTA);
4267 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 4267 if (ah->caps.tx_chainmask & BIT(2))
4268 AR_PHY_TPC_OLPC_GAIN_DELTA); 4268 REG_RMW(ah, AR_PHY_TPC_11_B2,
4269 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4270 AR_PHY_TPC_OLPC_GAIN_DELTA);
4269 4271
4270 /* enable open loop power control on chip */ 4272 /* enable open loop power control on chip */
4271 REG_RMW(ah, AR_PHY_TPC_6_B0, 4273 REG_RMW(ah, AR_PHY_TPC_6_B0,
4272 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4274 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4273 AR_PHY_TPC_6_ERROR_EST_MODE); 4275 AR_PHY_TPC_6_ERROR_EST_MODE);
4274 REG_RMW(ah, AR_PHY_TPC_6_B1, 4276 if (ah->caps.tx_chainmask & BIT(1))
4275 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4277 REG_RMW(ah, AR_PHY_TPC_6_B1,
4276 AR_PHY_TPC_6_ERROR_EST_MODE); 4278 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4277 REG_RMW(ah, AR_PHY_TPC_6_B2, 4279 AR_PHY_TPC_6_ERROR_EST_MODE);
4278 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S), 4280 if (ah->caps.tx_chainmask & BIT(2))
4279 AR_PHY_TPC_6_ERROR_EST_MODE); 4281 REG_RMW(ah, AR_PHY_TPC_6_B2,
4282 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4283 AR_PHY_TPC_6_ERROR_EST_MODE);
4280 4284
4281 /* 4285 /*
4282 * enable temperature compensation 4286 * enable temperature compensation