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authorGavin Shan <shangw@linux.vnet.ibm.com>2012-09-11 18:59:46 -0400
committerBjorn Helgaas <bhelgaas@google.com>2012-09-11 18:59:46 -0400
commit4c2245bb5c9c6e9950ee8919b4462dfa77f7a28f (patch)
tree40294aad43963b4e4e3ccd6d008aab9628465c7b
parentc121504e899c19f7e25b4894f616475073876361 (diff)
powerpc/PCI: Override pcibios_window_alignment()
This patch implements pcibios_window_alignment() so powerpc platforms can force P2P bridge windows to be at larger alignments than the PCI spec requires. [bhelgaas: changelog] Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--arch/powerpc/include/asm/machdep.h3
-rw-r--r--arch/powerpc/kernel/pci-common.c20
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 42ce570812c1..f7706d722b39 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -214,6 +214,9 @@ struct machdep_calls {
214 /* Called after scan and before resource survey */ 214 /* Called after scan and before resource survey */
215 void (*pcibios_fixup_phb)(struct pci_controller *hose); 215 void (*pcibios_fixup_phb)(struct pci_controller *hose);
216 216
217 /* Called during PCI resource reassignment */
218 resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
219
217 /* Called to shutdown machine specific hardware not already controlled 220 /* Called to shutdown machine specific hardware not already controlled
218 * by other drivers. 221 * by other drivers.
219 */ 222 */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2aa04f29e1de..43fea543d686 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -99,6 +99,26 @@ void pcibios_free_controller(struct pci_controller *phb)
99 kfree(phb); 99 kfree(phb);
100} 100}
101 101
102/*
103 * The function is used to return the minimal alignment
104 * for memory or I/O windows of the associated P2P bridge.
105 * By default, 4KiB alignment for I/O windows and 1MiB for
106 * memory windows.
107 */
108resource_size_t pcibios_window_alignment(struct pci_bus *bus,
109 unsigned long type)
110{
111 if (ppc_md.pcibios_window_alignment)
112 return ppc_md.pcibios_window_alignment(bus, type);
113
114 /*
115 * PCI core will figure out the default
116 * alignment: 4KiB for I/O and 1MiB for
117 * memory window.
118 */
119 return 1;
120}
121
102static resource_size_t pcibios_io_size(const struct pci_controller *hose) 122static resource_size_t pcibios_io_size(const struct pci_controller *hose)
103{ 123{
104#ifdef CONFIG_PPC64 124#ifdef CONFIG_PPC64