diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-12-02 00:35:38 -0500 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2010-12-29 19:36:52 -0500 |
commit | 3c9169753b42c34c9c5ed96a0e55f417a2f65d77 (patch) | |
tree | 2bb6c93f8b3d6b89c45c87dbb2ba64fc4f87628c | |
parent | c35cd6ec36a619dfd72d95d719ac926511d3f0e4 (diff) |
ARM: S3C64XX: Use chip_data to store the shift for EINTs
This makes all the functions that use the shift slightly smaller, one
instruction in most cases but more for ack() and maskack().
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
-rw-r--r-- | arch/arm/mach-s3c64xx/irq-eint.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c index 169ee29d37d7..2ead8189da74 100644 --- a/arch/arm/mach-s3c64xx/irq-eint.c +++ b/arch/arm/mach-s3c64xx/irq-eint.c | |||
@@ -30,14 +30,14 @@ | |||
30 | #include <plat/pm.h> | 30 | #include <plat/pm.h> |
31 | 31 | ||
32 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | 32 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) |
33 | #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) | 33 | #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq))) |
34 | 34 | ||
35 | static inline void s3c_irq_eint_mask(struct irq_data *data) | 35 | static inline void s3c_irq_eint_mask(struct irq_data *data) |
36 | { | 36 | { |
37 | u32 mask; | 37 | u32 mask; |
38 | 38 | ||
39 | mask = __raw_readl(S3C64XX_EINT0MASK); | 39 | mask = __raw_readl(S3C64XX_EINT0MASK); |
40 | mask |= eint_irq_to_bit(data->irq); | 40 | mask |= (u32)data->chip_data; |
41 | __raw_writel(mask, S3C64XX_EINT0MASK); | 41 | __raw_writel(mask, S3C64XX_EINT0MASK); |
42 | } | 42 | } |
43 | 43 | ||
@@ -46,13 +46,13 @@ static void s3c_irq_eint_unmask(struct irq_data *data) | |||
46 | u32 mask; | 46 | u32 mask; |
47 | 47 | ||
48 | mask = __raw_readl(S3C64XX_EINT0MASK); | 48 | mask = __raw_readl(S3C64XX_EINT0MASK); |
49 | mask &= ~eint_irq_to_bit(data->irq); | 49 | mask &= ~((u32)data->chip_data); |
50 | __raw_writel(mask, S3C64XX_EINT0MASK); | 50 | __raw_writel(mask, S3C64XX_EINT0MASK); |
51 | } | 51 | } |
52 | 52 | ||
53 | static inline void s3c_irq_eint_ack(struct irq_data *data) | 53 | static inline void s3c_irq_eint_ack(struct irq_data *data) |
54 | { | 54 | { |
55 | __raw_writel(eint_irq_to_bit(data->irq), S3C64XX_EINT0PEND); | 55 | __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); |
56 | } | 56 | } |
57 | 57 | ||
58 | static void s3c_irq_eint_maskack(struct irq_data *data) | 58 | static void s3c_irq_eint_maskack(struct irq_data *data) |
@@ -198,6 +198,7 @@ static int __init s3c64xx_init_irq_eint(void) | |||
198 | 198 | ||
199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { | 199 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { |
200 | set_irq_chip(irq, &s3c_irq_eint); | 200 | set_irq_chip(irq, &s3c_irq_eint); |
201 | set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq)); | ||
201 | set_irq_handler(irq, handle_level_irq); | 202 | set_irq_handler(irq, handle_level_irq); |
202 | set_irq_flags(irq, IRQF_VALID); | 203 | set_irq_flags(irq, IRQF_VALID); |
203 | } | 204 | } |