aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2011-05-16 18:06:49 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-16 18:06:49 -0400
commit1e87347c2f6e124d73b4921c4580adad4ac534d6 (patch)
tree9c548931dced2383c7eb8978b4fb2696a46d1a49
parentf29251ff532ca1124d14a03b040ba097edc6e9c0 (diff)
parent3cff484d4b264ff467a3b45c544cbbbab69f0bf8 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable
Diffstat
-rw-r--r--arch/arm/mach-dove/common.c616
-rw-r--r--arch/arm/mach-dove/mpp.c134
-rw-r--r--arch/arm/mach-dove/mpp.h362
-rw-r--r--arch/arm/mach-kirkwood/common.c601
-rw-r--r--arch/arm/mach-kirkwood/include/mach/irqs.h1
-rw-r--r--arch/arm/mach-kirkwood/mpp.c58
-rw-r--r--arch/arm/mach-kirkwood/mpp.h6
-rw-r--r--arch/arm/mach-loki/common.c190
-rw-r--r--arch/arm/mach-mv78xx0/common.c570
-rw-r--r--arch/arm/mach-mv78xx0/mpp.c58
-rw-r--r--arch/arm/mach-mv78xx0/mpp.h6
-rw-r--r--arch/arm/mach-orion5x/common.c478
-rw-r--r--arch/arm/mach-orion5x/d2net-setup.c44
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c44
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c132
-rw-r--r--arch/arm/mach-orion5x/edmini_v2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ls-chl-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ls_hgl-setup.c44
-rw-r--r--arch/arm/mach-orion5x/lsmini-setup.c44
-rw-r--r--arch/arm/mach-orion5x/mpp.c150
-rw-r--r--arch/arm/mach-orion5x/mpp.h191
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/mv2120-setup.c44
-rw-r--r--arch/arm/mach-orion5x/net2big-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c44
-rw-r--r--arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c1
-rw-r--r--arch/arm/mach-orion5x/terastation_pro2-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c44
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c44
-rw-r--r--arch/arm/mach-orion5x/wnr854t-setup.c44
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c44
-rw-r--r--arch/arm/plat-orion/Makefile2
-rw-r--r--arch/arm/plat-orion/common.c957
-rw-r--r--arch/arm/plat-orion/gpio.c112
-rw-r--r--arch/arm/plat-orion/include/plat/common.h117
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h1
-rw-r--r--arch/arm/plat-orion/include/plat/mpp.h34
-rw-r--r--arch/arm/plat-orion/irq.c49
-rw-r--r--arch/arm/plat-orion/mpp.c78
43 files changed, 2219 insertions, 3521 deletions
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f1f81d..5ed51b84c1b2 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17#include <linux/clk.h> 17#include <linux/clk.h>
18#include <linux/mbus.h> 18#include <linux/mbus.h>
19#include <linux/mv643xx_eth.h>
20#include <linux/mv643xx_i2c.h>
21#include <linux/ata_platform.h> 19#include <linux/ata_platform.h>
22#include <linux/spi/orion_spi.h> 20#include <linux/serial_8250.h>
23#include <linux/gpio.h> 21#include <linux/gpio.h>
24#include <asm/page.h> 22#include <asm/page.h>
25#include <asm/setup.h> 23#include <asm/setup.h>
@@ -32,11 +30,12 @@
32#include <mach/bridge-regs.h> 30#include <mach/bridge-regs.h>
33#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
34#include <linux/irq.h> 32#include <linux/irq.h>
35#include <plat/mv_xor.h>
36#include <plat/ehci-orion.h>
37#include <plat/time.h> 33#include <plat/time.h>
34#include <plat/common.h>
38#include "common.h" 35#include "common.h"
39 36
37static int get_tclk(void);
38
40/***************************************************************************** 39/*****************************************************************************
41 * I/O Address Mapping 40 * I/O Address Mapping
42 ****************************************************************************/ 41 ****************************************************************************/
@@ -70,463 +69,106 @@ void __init dove_map_io(void)
70} 69}
71 70
72/***************************************************************************** 71/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data dove_ehci_data = {
76 .dram = &dove_mbus_dram_info,
77 .phy_version = EHCI_PHY_NA,
78};
79
80static u64 ehci_dmamask = DMA_BIT_MASK(32);
81
82/*****************************************************************************
83 * EHCI0 72 * EHCI0
84 ****************************************************************************/ 73 ****************************************************************************/
85static struct resource dove_ehci0_resources[] = {
86 {
87 .start = DOVE_USB0_PHYS_BASE,
88 .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = IRQ_DOVE_USB0,
92 .end = IRQ_DOVE_USB0,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device dove_ehci0 = {
98 .name = "orion-ehci",
99 .id = 0,
100 .dev = {
101 .dma_mask = &ehci_dmamask,
102 .coherent_dma_mask = DMA_BIT_MASK(32),
103 .platform_data = &dove_ehci_data,
104 },
105 .resource = dove_ehci0_resources,
106 .num_resources = ARRAY_SIZE(dove_ehci0_resources),
107};
108
109void __init dove_ehci0_init(void) 74void __init dove_ehci0_init(void)
110{ 75{
111 platform_device_register(&dove_ehci0); 76 orion_ehci_init(&dove_mbus_dram_info,
77 DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
112} 78}
113 79
114/***************************************************************************** 80/*****************************************************************************
115 * EHCI1 81 * EHCI1
116 ****************************************************************************/ 82 ****************************************************************************/
117static struct resource dove_ehci1_resources[] = {
118 {
119 .start = DOVE_USB1_PHYS_BASE,
120 .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
122 }, {
123 .start = IRQ_DOVE_USB1,
124 .end = IRQ_DOVE_USB1,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device dove_ehci1 = {
130 .name = "orion-ehci",
131 .id = 1,
132 .dev = {
133 .dma_mask = &ehci_dmamask,
134 .coherent_dma_mask = DMA_BIT_MASK(32),
135 .platform_data = &dove_ehci_data,
136 },
137 .resource = dove_ehci1_resources,
138 .num_resources = ARRAY_SIZE(dove_ehci1_resources),
139};
140
141void __init dove_ehci1_init(void) 83void __init dove_ehci1_init(void)
142{ 84{
143 platform_device_register(&dove_ehci1); 85 orion_ehci_1_init(&dove_mbus_dram_info,
86 DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
144} 87}
145 88
146/***************************************************************************** 89/*****************************************************************************
147 * GE00 90 * GE00
148 ****************************************************************************/ 91 ****************************************************************************/
149struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
150 .t_clk = 0,
151 .dram = &dove_mbus_dram_info,
152};
153
154static struct resource dove_ge00_shared_resources[] = {
155 {
156 .name = "ge00 base",
157 .start = DOVE_GE00_PHYS_BASE + 0x2000,
158 .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
159 .flags = IORESOURCE_MEM,
160 },
161};
162
163static struct platform_device dove_ge00_shared = {
164 .name = MV643XX_ETH_SHARED_NAME,
165 .id = 0,
166 .dev = {
167 .platform_data = &dove_ge00_shared_data,
168 },
169 .num_resources = 1,
170 .resource = dove_ge00_shared_resources,
171};
172
173static struct resource dove_ge00_resources[] = {
174 {
175 .name = "ge00 irq",
176 .start = IRQ_DOVE_GE00_SUM,
177 .end = IRQ_DOVE_GE00_SUM,
178 .flags = IORESOURCE_IRQ,
179 },
180};
181
182static struct platform_device dove_ge00 = {
183 .name = MV643XX_ETH_NAME,
184 .id = 0,
185 .num_resources = 1,
186 .resource = dove_ge00_resources,
187 .dev = {
188 .coherent_dma_mask = 0xffffffff,
189 },
190};
191
192void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) 92void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
193{ 93{
194 eth_data->shared = &dove_ge00_shared; 94 orion_ge00_init(eth_data, &dove_mbus_dram_info,
195 dove_ge00.dev.platform_data = eth_data; 95 DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
196 96 0, get_tclk());
197 platform_device_register(&dove_ge00_shared);
198 platform_device_register(&dove_ge00);
199} 97}
200 98
201/***************************************************************************** 99/*****************************************************************************
202 * SoC RTC 100 * SoC RTC
203 ****************************************************************************/ 101 ****************************************************************************/
204static struct resource dove_rtc_resource[] = {
205 {
206 .start = DOVE_RTC_PHYS_BASE,
207 .end = DOVE_RTC_PHYS_BASE + 32 - 1,
208 .flags = IORESOURCE_MEM,
209 }, {
210 .start = IRQ_DOVE_RTC,
211 .flags = IORESOURCE_IRQ,
212 }
213};
214
215void __init dove_rtc_init(void) 102void __init dove_rtc_init(void)
216{ 103{
217 platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); 104 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
218} 105}
219 106
220/***************************************************************************** 107/*****************************************************************************
221 * SATA 108 * SATA
222 ****************************************************************************/ 109 ****************************************************************************/
223static struct resource dove_sata_resources[] = {
224 {
225 .name = "sata base",
226 .start = DOVE_SATA_PHYS_BASE,
227 .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .name = "sata irq",
231 .start = IRQ_DOVE_SATA,
232 .end = IRQ_DOVE_SATA,
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237static struct platform_device dove_sata = {
238 .name = "sata_mv",
239 .id = 0,
240 .dev = {
241 .coherent_dma_mask = DMA_BIT_MASK(32),
242 },
243 .num_resources = ARRAY_SIZE(dove_sata_resources),
244 .resource = dove_sata_resources,
245};
246
247void __init dove_sata_init(struct mv_sata_platform_data *sata_data) 110void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
248{ 111{
249 sata_data->dram = &dove_mbus_dram_info; 112 orion_sata_init(sata_data, &dove_mbus_dram_info,
250 dove_sata.dev.platform_data = sata_data; 113 DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
251 platform_device_register(&dove_sata); 114
252} 115}
253 116
254/***************************************************************************** 117/*****************************************************************************
255 * UART0 118 * UART0
256 ****************************************************************************/ 119 ****************************************************************************/
257static struct plat_serial8250_port dove_uart0_data[] = {
258 {
259 .mapbase = DOVE_UART0_PHYS_BASE,
260 .membase = (char *)DOVE_UART0_VIRT_BASE,
261 .irq = IRQ_DOVE_UART_0,
262 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
263 .iotype = UPIO_MEM,
264 .regshift = 2,
265 .uartclk = 0,
266 }, {
267 },
268};
269
270static struct resource dove_uart0_resources[] = {
271 {
272 .start = DOVE_UART0_PHYS_BASE,
273 .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
274 .flags = IORESOURCE_MEM,
275 }, {
276 .start = IRQ_DOVE_UART_0,
277 .end = IRQ_DOVE_UART_0,
278 .flags = IORESOURCE_IRQ,
279 },
280};
281
282static struct platform_device dove_uart0 = {
283 .name = "serial8250",
284 .id = 0,
285 .dev = {
286 .platform_data = dove_uart0_data,
287 },
288 .resource = dove_uart0_resources,
289 .num_resources = ARRAY_SIZE(dove_uart0_resources),
290};
291
292void __init dove_uart0_init(void) 120void __init dove_uart0_init(void)
293{ 121{
294 platform_device_register(&dove_uart0); 122 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
123 IRQ_DOVE_UART_0, get_tclk());
295} 124}
296 125
297/***************************************************************************** 126/*****************************************************************************
298 * UART1 127 * UART1
299 ****************************************************************************/ 128 ****************************************************************************/
300static struct plat_serial8250_port dove_uart1_data[] = {
301 {
302 .mapbase = DOVE_UART1_PHYS_BASE,
303 .membase = (char *)DOVE_UART1_VIRT_BASE,
304 .irq = IRQ_DOVE_UART_1,
305 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
306 .iotype = UPIO_MEM,
307 .regshift = 2,
308 .uartclk = 0,
309 }, {
310 },
311};
312
313static struct resource dove_uart1_resources[] = {
314 {
315 .start = DOVE_UART1_PHYS_BASE,
316 .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
317 .flags = IORESOURCE_MEM,
318 }, {
319 .start = IRQ_DOVE_UART_1,
320 .end = IRQ_DOVE_UART_1,
321 .flags = IORESOURCE_IRQ,
322 },
323};
324
325static struct platform_device dove_uart1 = {
326 .name = "serial8250",
327 .id = 1,
328 .dev = {
329 .platform_data = dove_uart1_data,
330 },
331 .resource = dove_uart1_resources,
332 .num_resources = ARRAY_SIZE(dove_uart1_resources),
333};
334
335void __init dove_uart1_init(void) 129void __init dove_uart1_init(void)
336{ 130{
337 platform_device_register(&dove_uart1); 131 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
132 IRQ_DOVE_UART_1, get_tclk());
338} 133}
339 134
340/***************************************************************************** 135/*****************************************************************************
341 * UART2 136 * UART2
342 ****************************************************************************/ 137 ****************************************************************************/
343static struct plat_serial8250_port dove_uart2_data[] = {
344 {
345 .mapbase = DOVE_UART2_PHYS_BASE,
346 .membase = (char *)DOVE_UART2_VIRT_BASE,
347 .irq = IRQ_DOVE_UART_2,
348 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
349 .iotype = UPIO_MEM,
350 .regshift = 2,
351 .uartclk = 0,
352 }, {
353 },
354};
355
356static struct resource dove_uart2_resources[] = {
357 {
358 .start = DOVE_UART2_PHYS_BASE,
359 .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
360 .flags = IORESOURCE_MEM,
361 }, {
362 .start = IRQ_DOVE_UART_2,
363 .end = IRQ_DOVE_UART_2,
364 .flags = IORESOURCE_IRQ,
365 },
366};
367
368static struct platform_device dove_uart2 = {
369 .name = "serial8250",
370 .id = 2,
371 .dev = {
372 .platform_data = dove_uart2_data,
373 },
374 .resource = dove_uart2_resources,
375 .num_resources = ARRAY_SIZE(dove_uart2_resources),
376};
377
378void __init dove_uart2_init(void) 138void __init dove_uart2_init(void)
379{ 139{
380 platform_device_register(&dove_uart2); 140 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
141 IRQ_DOVE_UART_2, get_tclk());
381} 142}
382 143
383/***************************************************************************** 144/*****************************************************************************
384 * UART3 145 * UART3
385 ****************************************************************************/ 146 ****************************************************************************/
386static struct plat_serial8250_port dove_uart3_data[] = {
387 {
388 .mapbase = DOVE_UART3_PHYS_BASE,
389 .membase = (char *)DOVE_UART3_VIRT_BASE,
390 .irq = IRQ_DOVE_UART_3,
391 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
392 .iotype = UPIO_MEM,
393 .regshift = 2,
394 .uartclk = 0,
395 }, {
396 },
397};
398
399static struct resource dove_uart3_resources[] = {
400 {
401 .start = DOVE_UART3_PHYS_BASE,
402 .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
403 .flags = IORESOURCE_MEM,
404 }, {
405 .start = IRQ_DOVE_UART_3,
406 .end = IRQ_DOVE_UART_3,
407 .flags = IORESOURCE_IRQ,
408 },
409};
410
411static struct platform_device dove_uart3 = {
412 .name = "serial8250",
413 .id = 3,
414 .dev = {
415 .platform_data = dove_uart3_data,
416 },
417 .resource = dove_uart3_resources,
418 .num_resources = ARRAY_SIZE(dove_uart3_resources),
419};
420
421void __init dove_uart3_init(void) 147void __init dove_uart3_init(void)
422{ 148{
423 platform_device_register(&dove_uart3); 149 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
150 IRQ_DOVE_UART_3, get_tclk());
424} 151}
425 152
426/***************************************************************************** 153/*****************************************************************************
427 * SPI0 154 * SPI
428 ****************************************************************************/ 155 ****************************************************************************/
429static struct orion_spi_info dove_spi0_data = {
430 .tclk = 0,
431};
432
433static struct resource dove_spi0_resources[] = {
434 {
435 .start = DOVE_SPI0_PHYS_BASE,
436 .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
437 .flags = IORESOURCE_MEM,
438 }, {
439 .start = IRQ_DOVE_SPI0,
440 .end = IRQ_DOVE_SPI0,
441 .flags = IORESOURCE_IRQ,
442 },
443};
444
445static struct platform_device dove_spi0 = {
446 .name = "orion_spi",
447 .id = 0,
448 .resource = dove_spi0_resources,
449 .dev = {
450 .platform_data = &dove_spi0_data,
451 },
452 .num_resources = ARRAY_SIZE(dove_spi0_resources),
453};
454
455void __init dove_spi0_init(void) 156void __init dove_spi0_init(void)
456{ 157{
457 platform_device_register(&dove_spi0); 158 orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
458} 159}
459 160
460/*****************************************************************************
461 * SPI1
462 ****************************************************************************/
463static struct orion_spi_info dove_spi1_data = {
464 .tclk = 0,
465};
466
467static struct resource dove_spi1_resources[] = {
468 {
469 .start = DOVE_SPI1_PHYS_BASE,
470 .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
471 .flags = IORESOURCE_MEM,
472 }, {
473 .start = IRQ_DOVE_SPI1,
474 .end = IRQ_DOVE_SPI1,
475 .flags = IORESOURCE_IRQ,
476 },
477};
478
479static struct platform_device dove_spi1 = {
480 .name = "orion_spi",
481 .id = 1,
482 .resource = dove_spi1_resources,
483 .dev = {
484 .platform_data = &dove_spi1_data,
485 },
486 .num_resources = ARRAY_SIZE(dove_spi1_resources),
487};
488
489void __init dove_spi1_init(void) 161void __init dove_spi1_init(void)
490{ 162{
491 platform_device_register(&dove_spi1); 163 orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
492} 164}
493 165
494/***************************************************************************** 166/*****************************************************************************
495 * I2C 167 * I2C
496 ****************************************************************************/ 168 ****************************************************************************/
497static struct mv64xxx_i2c_pdata dove_i2c_data = {
498 .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
499 .freq_n = 3,
500 .timeout = 1000, /* Default timeout of 1 second */
501};
502
503static struct resource dove_i2c_resources[] = {
504 {
505 .name = "i2c base",
506 .start = DOVE_I2C_PHYS_BASE,
507 .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
508 .flags = IORESOURCE_MEM,
509 }, {
510 .name = "i2c irq",
511 .start = IRQ_DOVE_I2C,
512 .end = IRQ_DOVE_I2C,
513 .flags = IORESOURCE_IRQ,
514 },
515};
516
517static struct platform_device dove_i2c = {
518 .name = MV64XXX_I2C_CTLR_NAME,
519 .id = 0,
520 .num_resources = ARRAY_SIZE(dove_i2c_resources),
521 .resource = dove_i2c_resources,
522 .dev = {
523 .platform_data = &dove_i2c_data,
524 },
525};
526
527void __init dove_i2c_init(void) 169void __init dove_i2c_init(void)
528{ 170{
529 platform_device_register(&dove_i2c); 171 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
530} 172}
531 173
532/***************************************************************************** 174/*****************************************************************************
@@ -554,208 +196,22 @@ struct sys_timer dove_timer = {
554}; 196};
555 197
556/***************************************************************************** 198/*****************************************************************************
557 * XOR
558 ****************************************************************************/
559static struct mv_xor_platform_shared_data dove_xor_shared_data = {
560 .dram = &dove_mbus_dram_info,
561};
562
563/*****************************************************************************
564 * XOR 0 199 * XOR 0
565 ****************************************************************************/ 200 ****************************************************************************/
566static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
567
568static struct resource dove_xor0_shared_resources[] = {
569 {
570 .name = "xor 0 low",
571 .start = DOVE_XOR0_PHYS_BASE,
572 .end = DOVE_XOR0_PHYS_BASE + 0xff,
573 .flags = IORESOURCE_MEM,
574 }, {
575 .name = "xor 0 high",
576 .start = DOVE_XOR0_HIGH_PHYS_BASE,
577 .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
578 .flags = IORESOURCE_MEM,
579 },
580};
581
582static struct platform_device dove_xor0_shared = {
583 .name = MV_XOR_SHARED_NAME,
584 .id = 0,
585 .dev = {
586 .platform_data = &dove_xor_shared_data,
587 },
588 .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
589 .resource = dove_xor0_shared_resources,
590};
591
592static struct resource dove_xor00_resources[] = {
593 [0] = {
594 .start = IRQ_DOVE_XOR_00,
595 .end = IRQ_DOVE_XOR_00,
596 .flags = IORESOURCE_IRQ,
597 },
598};
599
600static struct mv_xor_platform_data dove_xor00_data = {
601 .shared = &dove_xor0_shared,
602 .hw_id = 0,
603 .pool_size = PAGE_SIZE,
604};
605
606static struct platform_device dove_xor00_channel = {
607 .name = MV_XOR_NAME,
608 .id = 0,
609 .num_resources = ARRAY_SIZE(dove_xor00_resources),
610 .resource = dove_xor00_resources,
611 .dev = {
612 .dma_mask = &dove_xor0_dmamask,
613 .coherent_dma_mask = DMA_BIT_MASK(64),
614 .platform_data = &dove_xor00_data,
615 },
616};
617
618static struct resource dove_xor01_resources[] = {
619 [0] = {
620 .start = IRQ_DOVE_XOR_01,
621 .end = IRQ_DOVE_XOR_01,
622 .flags = IORESOURCE_IRQ,
623 },
624};
625
626static struct mv_xor_platform_data dove_xor01_data = {
627 .shared = &dove_xor0_shared,
628 .hw_id = 1,
629 .pool_size = PAGE_SIZE,
630};
631
632static struct platform_device dove_xor01_channel = {
633 .name = MV_XOR_NAME,
634 .id = 1,
635 .num_resources = ARRAY_SIZE(dove_xor01_resources),
636 .resource = dove_xor01_resources,
637 .dev = {
638 .dma_mask = &dove_xor0_dmamask,
639 .coherent_dma_mask = DMA_BIT_MASK(64),
640 .platform_data = &dove_xor01_data,
641 },
642};
643
644void __init dove_xor0_init(void) 201void __init dove_xor0_init(void)
645{ 202{
646 platform_device_register(&dove_xor0_shared); 203 orion_xor0_init(&dove_mbus_dram_info,
647 204 DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
648 /* 205 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
649 * two engines can't do memset simultaneously, this limitation
650 * satisfied by removing memset support from one of the engines.
651 */
652 dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
653 dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
654 platform_device_register(&dove_xor00_channel);
655
656 dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
657 dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
658 dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
659 platform_device_register(&dove_xor01_channel);
660} 206}
661 207
662/***************************************************************************** 208/*****************************************************************************
663 * XOR 1 209 * XOR 1
664 ****************************************************************************/ 210 ****************************************************************************/
665static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
666
667static struct resource dove_xor1_shared_resources[] = {
668 {
669 .name = "xor 0 low",
670 .start = DOVE_XOR1_PHYS_BASE,
671 .end = DOVE_XOR1_PHYS_BASE + 0xff,
672 .flags = IORESOURCE_MEM,
673 }, {
674 .name = "xor 0 high",
675 .start = DOVE_XOR1_HIGH_PHYS_BASE,
676 .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
677 .flags = IORESOURCE_MEM,
678 },
679};
680
681static struct platform_device dove_xor1_shared = {
682 .name = MV_XOR_SHARED_NAME,
683 .id = 1,
684 .dev = {
685 .platform_data = &dove_xor_shared_data,
686 },
687 .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
688 .resource = dove_xor1_shared_resources,
689};
690
691static struct resource dove_xor10_resources[] = {
692 [0] = {
693 .start = IRQ_DOVE_XOR_10,
694 .end = IRQ_DOVE_XOR_10,
695 .flags = IORESOURCE_IRQ,
696 },
697};
698
699static struct mv_xor_platform_data dove_xor10_data = {
700 .shared = &dove_xor1_shared,
701 .hw_id = 0,
702 .pool_size = PAGE_SIZE,
703};
704
705static struct platform_device dove_xor10_channel = {
706 .name = MV_XOR_NAME,
707 .id = 2,
708 .num_resources = ARRAY_SIZE(dove_xor10_resources),
709 .resource = dove_xor10_resources,
710 .dev = {
711 .dma_mask = &dove_xor1_dmamask,
712 .coherent_dma_mask = DMA_BIT_MASK(64),
713 .platform_data = &dove_xor10_data,
714 },
715};
716
717static struct resource dove_xor11_resources[] = {
718 [0] = {
719 .start = IRQ_DOVE_XOR_11,
720 .end = IRQ_DOVE_XOR_11,
721 .flags = IORESOURCE_IRQ,
722 },
723};
724
725static struct mv_xor_platform_data dove_xor11_data = {
726 .shared = &dove_xor1_shared,
727 .hw_id = 1,
728 .pool_size = PAGE_SIZE,
729};
730
731static struct platform_device dove_xor11_channel = {
732 .name = MV_XOR_NAME,
733 .id = 3,
734 .num_resources = ARRAY_SIZE(dove_xor11_resources),
735 .resource = dove_xor11_resources,
736 .dev = {
737 .dma_mask = &dove_xor1_dmamask,
738 .coherent_dma_mask = DMA_BIT_MASK(64),
739 .platform_data = &dove_xor11_data,
740 },
741};
742
743void __init dove_xor1_init(void) 211void __init dove_xor1_init(void)
744{ 212{
745 platform_device_register(&dove_xor1_shared); 213 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
746 214 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
747 /*
748 * two engines can't do memset simultaneously, this limitation
749 * satisfied by removing memset support from one of the engines.
750 */
751 dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
752 dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
753 platform_device_register(&dove_xor10_channel);
754
755 dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
756 dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
757 dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
758 platform_device_register(&dove_xor11_channel);
759} 215}
760 216
761/***************************************************************************** 217/*****************************************************************************
@@ -833,14 +289,6 @@ void __init dove_init(void)
833#endif 289#endif
834 dove_setup_cpu_mbus(); 290 dove_setup_cpu_mbus();
835 291
836 dove_ge00_shared_data.t_clk = tclk;
837 dove_uart0_data[0].uartclk = tclk;
838 dove_uart1_data[0].uartclk = tclk;
839 dove_uart2_data[0].uartclk = tclk;
840 dove_uart3_data[0].uartclk = tclk;
841 dove_spi0_data.tclk = tclk;
842 dove_spi1_data.tclk = tclk;
843
844 /* internal devices that every board has */ 292 /* internal devices that every board has */
845 dove_rtc_init(); 293 dove_rtc_init();
846 dove_xor0_init(); 294 dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c76346904..51e0e411c9cb 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/io.h> 13#include <linux/io.h>
14 14#include <plat/mpp.h>
15#include <mach/dove.h> 15#include <mach/dove.h>
16
17#include "mpp.h" 16#include "mpp.h"
18 17
19#define MPP_NR_REGS 4
20#define MPP_CTRL(i) ((i) == 3 ? \
21 DOVE_MPP_CTRL4_VIRT_BASE : \
22 DOVE_MPP_VIRT_BASE + (i) * 4)
23#define PMU_SIG_REGS 2
24#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
25
26struct dove_mpp_grp { 18struct dove_mpp_grp {
27 int start; 19 int start;
28 int end; 20 int end;
29}; 21};
30 22
31static struct dove_mpp_grp dove_mpp_grp[] = { 23/* Map a group to a range of GPIO pins in that group */
24static const struct dove_mpp_grp dove_mpp_grp[] = {
32 [MPP_24_39] = { 25 [MPP_24_39] = {
33 .start = 24, 26 .start = 24,
34 .end = 39, 27 .end = 39,
@@ -38,8 +31,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
38 .end = 45, 31 .end = 45,
39 }, 32 },
40 [MPP_46_51] = { 33 [MPP_46_51] = {
41 .start = 40, 34 .start = 46,
42 .end = 45, 35 .end = 51,
43 }, 36 },
44 [MPP_58_61] = { 37 [MPP_58_61] = {
45 .start = 58, 38 .start = 58,
@@ -51,6 +44,8 @@ static struct dove_mpp_grp dove_mpp_grp[] = {
51 }, 44 },
52}; 45};
53 46
47/* Enable gpio for a range of pins. mode should be a combination of
48 GPIO_OUTPUT_OK | GPIO_INPUT_OK */
54static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) 49static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
55{ 50{
56 int i; 51 int i;
@@ -59,24 +54,17 @@ static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
59 orion_gpio_set_valid(i, gpio_mode); 54 orion_gpio_set_valid(i, gpio_mode);
60} 55}
61 56
57/* Dump all the extra MPP registers. The platform code will dump the
58 registers for pins 0-23. */
62static void dove_mpp_dump_regs(void) 59static void dove_mpp_dump_regs(void)
63{ 60{
64#ifdef DEBUG 61 pr_debug("PMU_CTRL4_CTRL: %08x\n",
65 int i; 62 readl(DOVE_MPP_CTRL4_VIRT_BASE));
66 63
67 pr_debug("MPP_CTRL regs:"); 64 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
68 for (i = 0; i < MPP_NR_REGS; i++) 65 readl(DOVE_PMU_MPP_GENERAL_CTRL));
69 printk(" %08x", readl(MPP_CTRL(i)));
70 printk("\n");
71 66
72 pr_debug("PMU_SIG_CTRL regs:");
73 for (i = 0; i < PMU_SIG_REGS; i++)
74 printk(" %08x", readl(PMU_SIG_CTRL(i)));
75 printk("\n");
76
77 pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
78 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 67 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
79#endif
80} 68}
81 69
82static void dove_mpp_cfg_nfc(int sel) 70static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@ static void dove_mpp_cfg_nfc(int sel)
92 80
93static void dove_mpp_cfg_au1(int sel) 81static void dove_mpp_cfg_au1(int sel)
94{ 82{
95 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 83 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
96 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 84 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
97 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); 85 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
98 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); 86 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@ static void dove_mpp_cfg_au1(int sel)
128 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); 116 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
129} 117}
130 118
131static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl) 119/* Configure the group registers, enabling GPIO if sel indicates the
132{ 120 pin is to be used for GPIO */
133 int start = dove_mpp_grp[num].start; 121static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
134 int end = dove_mpp_grp[num].end;
135 int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
136
137 *mpp_ctrl &= ~(0x1 << num);
138 *mpp_ctrl |= sel << num;
139
140 dove_mpp_gpio_mode(start, end, gpio_mode);
141}
142
143void __init dove_mpp_conf(unsigned int *mpp_list)
144{ 122{
145 u32 mpp_ctrl[MPP_NR_REGS]; 123 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
146 u32 pmu_mpp_ctrl = 0; 124 int gpio_mode;
147 u32 pmu_sig_ctrl[PMU_SIG_REGS];
148 int i;
149
150 for (i = 0; i < MPP_NR_REGS; i++)
151 mpp_ctrl[i] = readl(MPP_CTRL(i));
152
153 for (i = 0; i < PMU_SIG_REGS; i++)
154 pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
155
156 pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
157 125
158 dove_mpp_dump_regs(); 126 for ( ; *mpp_grp_list; mpp_grp_list++) {
159 127 unsigned int num = MPP_NUM(*mpp_grp_list);
160 for ( ; *mpp_list != MPP_END; mpp_list++) { 128 unsigned int sel = MPP_SEL(*mpp_grp_list);
161 unsigned int num = MPP_NUM(*mpp_list);
162 unsigned int sel = MPP_SEL(*mpp_list);
163 int shift, gpio_mode;
164
165 if (num > MPP_MAX) {
166 pr_err("dove: invalid MPP number (%u)\n", num);
167 continue;
168 }
169
170 if (*mpp_list & MPP_NFC_MASK) {
171 dove_mpp_cfg_nfc(sel);
172 continue;
173 }
174 129
175 if (*mpp_list & MPP_AU1_MASK) { 130 if (num > MPP_GRP_MAX) {
176 dove_mpp_cfg_au1(sel); 131 pr_err("dove: invalid MPP GRP number (%u)\n", num);
177 continue; 132 continue;
178 } 133 }
179 134
180 if (*mpp_list & MPP_GRP_MASK) { 135 mpp_ctrl4 &= ~(0x1 << num);
181 dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]); 136 mpp_ctrl4 |= sel << num;
182 continue;
183 }
184
185 shift = (num & 7) << 2;
186 if (*mpp_list & MPP_PMU_MASK) {
187 pmu_mpp_ctrl |= (0x1 << num);
188 pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
189 pmu_sig_ctrl[num / 8] |= 0xf << shift;
190 gpio_mode = 0;
191 } else {
192 mpp_ctrl[num / 8] &= ~(0xf << shift);
193 mpp_ctrl[num / 8] |= sel << shift;
194 gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
195 }
196 137
197 orion_gpio_set_valid(num, gpio_mode); 138 gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
139 dove_mpp_gpio_mode(dove_mpp_grp[num].start,
140 dove_mpp_grp[num].end, gpio_mode);
198 } 141 }
142 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
143}
199 144
200 for (i = 0; i < MPP_NR_REGS; i++) 145/* Configure the various MPP pins on Dove */
201 writel(mpp_ctrl[i], MPP_CTRL(i)); 146void __init dove_mpp_conf(unsigned int *mpp_list,
147 unsigned int *mpp_grp_list,
148 unsigned int grp_au1_52_57,
149 unsigned int grp_nfc_64_71)
150{
151 dove_mpp_dump_regs();
202 152
203 for (i = 0; i < PMU_SIG_REGS; i++) 153 /* Use platform code for pins 0-23 */
204 writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i)); 154 orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
205 155
206 writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL); 156 dove_mpp_conf_grp(mpp_grp_list);
157 dove_mpp_cfg_au1(grp_au1_52_57);
158 dove_mpp_cfg_nfc(grp_nfc_64_71);
207 159
208 dove_mpp_dump_regs(); 160 dove_mpp_dump_regs();
209} 161}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce413b15..fbec7c52bfac 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
1#ifndef __ARCH_DOVE_MPP_CODED_H 1#ifndef __ARCH_DOVE_MPP_CODED_H
2#define __ARCH_DOVE_MPP_CODED_H 2#define __ARCH_DOVE_MPP_CODED_H
3 3
4#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \ 4#define MPP(_num, _sel, _in, _out) ( \
5/* MPP/group number */ ((_num) & 0xff) | \ 5 /* MPP number */ ((_num) & 0xff) | \
6/* MPP select value */ (((_mode) & 0xf) << 8) | \ 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7/* MPP PMU */ ((!!(_pmu)) << 12) | \ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8/* group flag */ ((!!(_grp)) << 13) | \ 8 /* may be output signal */ ((!!(_out)) << 13))
9/* AU1 flag */ ((!!(_au1)) << 14) | \ 9
10/* NFCE flag */ ((!!(_nfc)) << 15)) 10#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
11 11#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
12#define MPP_MAX 71 12#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
13 13#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
14#define MPP_NUM(x) ((x) & 0xff) 14
15#define MPP_SEL(x) (((x) >> 8) & 0xf) 15#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
16 16#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
17#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0) 17#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
18#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0) 18#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
19#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0) 19
20#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1) 20#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
21 21#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
22#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1) 22#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
23 23#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
24#define MPP_PMU_DRIVE_0 0x1 24#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
25#define MPP_PMU_DRIVE_1 0x2 25
26#define MPP_PMU_SDI 0x3 26#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
27#define MPP_PMU_CPU_PWRDWN 0x4 27#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
28#define MPP_PMU_STBY_PWRDWN 0x5 28#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
29#define MPP_PMU_CORE_PWR_GOOD 0x8 29#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
30#define MPP_PMU_BAT_FAULT 0xa 30#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
31#define MPP_PMU_EXT0_WU 0xb 31#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
32#define MPP_PMU_EXT1_WU 0xc 32
33#define MPP_PMU_EXT2_WU 0xd 33#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
34#define MPP_PMU_BLINK 0xe 34#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
35#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0) 35#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
36 36#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
37#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0) 37
38#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0) 38#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
39#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0) 39#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
40#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1) 40#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
41 41#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
42#define MPP0_GPIO0 MPP_PIN(0, 0x0) 42
43#define MPP0_UA2_RTSn MPP_PIN(0, 0x2) 43#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
44#define MPP0_SDIO0_CD MPP_PIN(0, 0x3) 44#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
45#define MPP0_LCD0_PWM MPP_PIN(0, 0xf) 45#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
46 46#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
47#define MPP1_GPIO1 MPP_PIN(1, 0x0) 47
48#define MPP1_UA2_CTSn MPP_PIN(1, 0x2) 48#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
49#define MPP1_SDIO0_WP MPP_PIN(1, 0x3) 49#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
50#define MPP1_LCD1_PWM MPP_PIN(1, 0xf) 50#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
51 51#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
52#define MPP2_GPIO2 MPP_PIN(2, 0x0) 52
53#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1) 53#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
54#define MPP2_UA2_TXD MPP_PIN(2, 0x2) 54#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
55#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3) 55
56#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4) 56#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
57 57#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
58#define MPP3_GPIO3 MPP_PIN(3, 0x0) 58
59#define MPP3_SATA_ACT MPP_PIN(3, 0x1) 59#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
60#define MPP3_UA2_RXD MPP_PIN(3, 0x2) 60#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
61#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3) 61
62#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4) 62#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
63#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf) 63#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
64 64#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
65#define MPP4_GPIO4 MPP_PIN(4, 0x0) 65#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
66#define MPP4_UA3_RTSn MPP_PIN(4, 0x2) 66#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
67#define MPP4_SDIO1_CD MPP_PIN(4, 0x3) 67#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
68#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4) 68
69 69#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
70#define MPP5_GPIO5 MPP_PIN(5, 0x0) 70#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
71#define MPP5_UA3_CTSn MPP_PIN(5, 0x2) 71#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
72#define MPP5_SDIO1_WP MPP_PIN(5, 0x3) 72#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
73#define MPP5_SPI_1_CS MPP_PIN(5, 0x4) 73#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
74 74
75#define MPP6_GPIO6 MPP_PIN(6, 0x0) 75#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
76#define MPP6_UA3_TXD MPP_PIN(6, 0x2) 76#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
77#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3) 77#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
78#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4) 78#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
79 79#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
80#define MPP7_GPIO7 MPP_PIN(7, 0x0) 80
81#define MPP7_UA3_RXD MPP_PIN(7, 0x2) 81#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
82#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3) 82#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
83#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4) 83#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
84 84#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
85#define MPP8_GPIO8 MPP_PIN(8, 0x0) 85
86#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1) 86#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
87 87#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
88#define MPP9_GPIO9 MPP_PIN(9, 0x0) 88#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
89#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5) 89#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
90 90
91#define MPP10_GPIO10 MPP_PIN(10, 0x0) 91#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
92#define MPP10_SSP_SCLK MPP_PIN(10, 0x5) 92#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
93 93#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
94#define MPP11_GPIO11 MPP_PIN(11, 0x0) 94#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
95#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1) 95#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
96#define MPP11_SATA_ACT MPP_PIN(11, 0x2) 96
97#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3) 97#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
98#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4) 98#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
99#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5) 99#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
100 100#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
101#define MPP12_GPIO12 MPP_PIN(12, 0x0) 101#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
102#define MPP12_SATA_ACT MPP_PIN(12, 0x1) 102#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
103#define MPP12_UA2_RTSn MPP_PIN(12, 0x2) 103
104#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3) 104#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
105#define MPP12_SDIO1_CD MPP_PIN(12, 0x4) 105#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
106 106#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
107#define MPP13_GPIO13 MPP_PIN(13, 0x0) 107#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
108#define MPP13_UA2_CTSn MPP_PIN(13, 0x2) 108#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
109#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3) 109
110#define MPP13_SDIO1WP MPP_PIN(13, 0x4) 110#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
111#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5) 111#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
112 112#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
113#define MPP14_GPIO14 MPP_PIN(14, 0x0) 113#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
114#define MPP14_UA2_TXD MPP_PIN(14, 0x2) 114
115#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4) 115#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
116#define MPP14_SSP_RXD MPP_PIN(14, 0x5) 116#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
117 117#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
118#define MPP15_GPIO15 MPP_PIN(15, 0x0) 118#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
119#define MPP15_UA2_RXD MPP_PIN(15, 0x2) 119#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
120#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4) 120#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
121#define MPP15_SSP_SFRM MPP_PIN(15, 0x5) 121
122 122#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
123#define MPP16_GPIO16 MPP_PIN(16, 0x0) 123#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
124#define MPP16_UA3_RTSn MPP_PIN(16, 0x2) 124#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
125#define MPP16_SDIO0_CD MPP_PIN(16, 0x3) 125#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
126#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4) 126#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
127#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5) 127#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
128 128#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
129#define MPP17_GPIO17 MPP_PIN(17, 0x0) 129
130#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1) 130#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
131#define MPP17_UA3_CTSn MPP_PIN(17, 0x2) 131#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
132#define MPP17_SDIO0_WP MPP_PIN(17, 0x3) 132#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
133#define MPP17_TW_SDA2 MPP_PIN(17, 0x4) 133#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
134#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5) 134#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
135 135#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
136#define MPP18_GPIO18 MPP_PIN(18, 0x0) 136#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
137#define MPP18_UA3_TXD MPP_PIN(18, 0x2) 137
138#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3) 138#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
139#define MPP18_LCD0_PWM MPP_PIN(18, 0x4) 139#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
140#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5) 140#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
141 141#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
142#define MPP19_GPIO19 MPP_PIN(19, 0x0) 142#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
143#define MPP19_UA3_RXD MPP_PIN(19, 0x2) 143#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
144#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3) 144
145#define MPP19_TW_SCK2 MPP_PIN(19, 0x4) 145#define MPP_MAX 23
146 146
147#define MPP20_GPIO20 MPP_PIN(20, 0x0) 147#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
148#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
149#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
150#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
151#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
152#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
153
154#define MPP21_GPIO21 MPP_PIN(21, 0x0)
155#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
156#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
157#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
158#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
159#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
160#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
161
162#define MPP22_GPIO22 MPP_PIN(22, 0x0)
163#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
164#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
165#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
166#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
167#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
168#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
169
170#define MPP23_GPIO23 MPP_PIN(23, 0x0)
171#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
172#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
173#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
174#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
175#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
176 148
177/* for MPP groups _num is a group index */ 149/* for MPP groups _num is a group index */
178enum dove_mpp_grp_idx { 150enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@ enum dove_mpp_grp_idx {
181 MPP_46_51 = 1, 153 MPP_46_51 = 1,
182 MPP_58_61 = 5, 154 MPP_58_61 = 5,
183 MPP_62_63 = 4, 155 MPP_62_63 = 4,
156 MPP_GRP_MAX = 5,
184}; 157};
185 158
186#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1) 159#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
187#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0) 160#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
188 161
189#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1) 162#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
190#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0) 163#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
191 164
192#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1) 165#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
193#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0) 166#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
194 167
195#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1) 168#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
196#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0) 169#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
197 170
198#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1) 171#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
199#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0) 172#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
200 173
201/* The MPP[64:71] control differs from other groups */ 174/* The MPP[64:71] control differs from other groups */
202#define MPP64_71_GPO MPP_GRP_NFC(0x1) 175#define MPP_GRP_NFC_64_71_GPO 0x1
203#define MPP64_71_NFC MPP_GRP_NFC(0x0) 176#define MPP_GRP_NFC_64_71_NFC 0x0
204 177
205/* 178/*
206 * The MPP[52:57] functionality is encoded by 4 bits in different 179 * The MPP[52:57] functionality is encoded by 4 bits in different
207 * registers. The _num field in this case encodes those bits in 180 * registers. The _num field in this case encodes those bits in
208 * correspodence with Table 135 of 88AP510 Functional specification 181 * correspodence with Table 135 of 88AP510 Functional specification
209 */ 182 */
210#define MPP52_57_AU1 MPP_GRP_AU1(0x0) 183#define MPP_GRP_AU1_52_57_AU1 0x0
211#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2) 184#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
212#define MPP52_57_GPIO MPP_GRP_AU1(0xa) 185#define MPP_GRP_AU1_52_57_GPIO 0xa
213#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb) 186#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
214#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc) 187#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
215#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe) 188#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
216#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf) 189#define MPP_GRP_AU1_52_57_SSP_TW 0xf
217 190
218void dove_mpp_conf(unsigned int *mpp_list); 191void dove_mpp_conf(unsigned int *mpp_list,
192 unsigned int *mpp_grp_list,
193 unsigned int grp_au1_52_57,
194 unsigned int grp_nfc_64_71);
219 195
220#endif /* __ARCH_DOVE_MPP_CODED_H */ 196#endif /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 20e71df3e3bb..f3248cfbe51d 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -13,11 +13,9 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/mv643xx_i2c.h>
18#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
19#include <linux/mtd/nand.h> 17#include <linux/mtd/nand.h>
20#include <linux/spi/orion_spi.h> 18#include <linux/dma-mapping.h>
21#include <net/dsa.h> 19#include <net/dsa.h>
22#include <asm/page.h> 20#include <asm/page.h>
23#include <asm/timex.h> 21#include <asm/timex.h>
@@ -28,11 +26,9 @@
28#include <mach/bridge-regs.h> 26#include <mach/bridge-regs.h>
29#include <plat/audio.h> 27#include <plat/audio.h>
30#include <plat/cache-feroceon-l2.h> 28#include <plat/cache-feroceon-l2.h>
31#include <plat/ehci-orion.h>
32#include <plat/mvsdio.h> 29#include <plat/mvsdio.h>
33#include <plat/mv_xor.h>
34#include <plat/orion_nand.h> 30#include <plat/orion_nand.h>
35#include <plat/orion_wdt.h> 31#include <plat/common.h>
36#include <plat/time.h> 32#include <plat/time.h>
37#include "common.h" 33#include "common.h"
38 34
@@ -69,210 +65,52 @@ void __init kirkwood_map_io(void)
69 * registered. Some reserved bits must be set to 1. 65 * registered. Some reserved bits must be set to 1.
70 */ 66 */
71unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; 67unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
72
73
74/*****************************************************************************
75 * EHCI
76 ****************************************************************************/
77static struct orion_ehci_data kirkwood_ehci_data = {
78 .dram = &kirkwood_mbus_dram_info,
79 .phy_version = EHCI_PHY_NA,
80};
81
82static u64 ehci_dmamask = 0xffffffffUL;
83 68
84 69
85/***************************************************************************** 70/*****************************************************************************
86 * EHCI0 71 * EHCI0
87 ****************************************************************************/ 72 ****************************************************************************/
88static struct resource kirkwood_ehci_resources[] = {
89 {
90 .start = USB_PHYS_BASE,
91 .end = USB_PHYS_BASE + 0x0fff,
92 .flags = IORESOURCE_MEM,
93 }, {
94 .start = IRQ_KIRKWOOD_USB,
95 .end = IRQ_KIRKWOOD_USB,
96 .flags = IORESOURCE_IRQ,
97 },
98};
99
100static struct platform_device kirkwood_ehci = {
101 .name = "orion-ehci",
102 .id = 0,
103 .dev = {
104 .dma_mask = &ehci_dmamask,
105 .coherent_dma_mask = 0xffffffff,
106 .platform_data = &kirkwood_ehci_data,
107 },
108 .resource = kirkwood_ehci_resources,
109 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
110};
111
112void __init kirkwood_ehci_init(void) 73void __init kirkwood_ehci_init(void)
113{ 74{
114 kirkwood_clk_ctrl |= CGC_USB0; 75 kirkwood_clk_ctrl |= CGC_USB0;
115 platform_device_register(&kirkwood_ehci); 76 orion_ehci_init(&kirkwood_mbus_dram_info,
77 USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
116} 78}
117 79
118 80
119/***************************************************************************** 81/*****************************************************************************
120 * GE00 82 * GE00
121 ****************************************************************************/ 83 ****************************************************************************/
122struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
123 .dram = &kirkwood_mbus_dram_info,
124};
125
126static struct resource kirkwood_ge00_shared_resources[] = {
127 {
128 .name = "ge00 base",
129 .start = GE00_PHYS_BASE + 0x2000,
130 .end = GE00_PHYS_BASE + 0x3fff,
131 .flags = IORESOURCE_MEM,
132 }, {
133 .name = "ge00 err irq",
134 .start = IRQ_KIRKWOOD_GE00_ERR,
135 .end = IRQ_KIRKWOOD_GE00_ERR,
136 .flags = IORESOURCE_IRQ,
137 },
138};
139
140static struct platform_device kirkwood_ge00_shared = {
141 .name = MV643XX_ETH_SHARED_NAME,
142 .id = 0,
143 .dev = {
144 .platform_data = &kirkwood_ge00_shared_data,
145 },
146 .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
147 .resource = kirkwood_ge00_shared_resources,
148};
149
150static struct resource kirkwood_ge00_resources[] = {
151 {
152 .name = "ge00 irq",
153 .start = IRQ_KIRKWOOD_GE00_SUM,
154 .end = IRQ_KIRKWOOD_GE00_SUM,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device kirkwood_ge00 = {
160 .name = MV643XX_ETH_NAME,
161 .id = 0,
162 .num_resources = 1,
163 .resource = kirkwood_ge00_resources,
164 .dev = {
165 .coherent_dma_mask = 0xffffffff,
166 },
167};
168
169void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) 84void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
170{ 85{
171 kirkwood_clk_ctrl |= CGC_GE0; 86 kirkwood_clk_ctrl |= CGC_GE0;
172 eth_data->shared = &kirkwood_ge00_shared;
173 kirkwood_ge00.dev.platform_data = eth_data;
174 87
175 platform_device_register(&kirkwood_ge00_shared); 88 orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
176 platform_device_register(&kirkwood_ge00); 89 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
90 IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
177} 91}
178 92
179 93
180/***************************************************************************** 94/*****************************************************************************
181 * GE01 95 * GE01
182 ****************************************************************************/ 96 ****************************************************************************/
183struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
184 .dram = &kirkwood_mbus_dram_info,
185 .shared_smi = &kirkwood_ge00_shared,
186};
187
188static struct resource kirkwood_ge01_shared_resources[] = {
189 {
190 .name = "ge01 base",
191 .start = GE01_PHYS_BASE + 0x2000,
192 .end = GE01_PHYS_BASE + 0x3fff,
193 .flags = IORESOURCE_MEM,
194 }, {
195 .name = "ge01 err irq",
196 .start = IRQ_KIRKWOOD_GE01_ERR,
197 .end = IRQ_KIRKWOOD_GE01_ERR,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device kirkwood_ge01_shared = {
203 .name = MV643XX_ETH_SHARED_NAME,
204 .id = 1,
205 .dev = {
206 .platform_data = &kirkwood_ge01_shared_data,
207 },
208 .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
209 .resource = kirkwood_ge01_shared_resources,
210};
211
212static struct resource kirkwood_ge01_resources[] = {
213 {
214 .name = "ge01 irq",
215 .start = IRQ_KIRKWOOD_GE01_SUM,
216 .end = IRQ_KIRKWOOD_GE01_SUM,
217 .flags = IORESOURCE_IRQ,
218 },
219};
220
221static struct platform_device kirkwood_ge01 = {
222 .name = MV643XX_ETH_NAME,
223 .id = 1,
224 .num_resources = 1,
225 .resource = kirkwood_ge01_resources,
226 .dev = {
227 .coherent_dma_mask = 0xffffffff,
228 },
229};
230
231void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) 97void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
232{ 98{
99
233 kirkwood_clk_ctrl |= CGC_GE1; 100 kirkwood_clk_ctrl |= CGC_GE1;
234 eth_data->shared = &kirkwood_ge01_shared;
235 kirkwood_ge01.dev.platform_data = eth_data;
236 101
237 platform_device_register(&kirkwood_ge01_shared); 102 orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
238 platform_device_register(&kirkwood_ge01); 103 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
104 IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
239} 105}
240 106
241 107
242/***************************************************************************** 108/*****************************************************************************
243 * Ethernet switch 109 * Ethernet switch
244 ****************************************************************************/ 110 ****************************************************************************/
245static struct resource kirkwood_switch_resources[] = {
246 {
247 .start = 0,
248 .end = 0,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device kirkwood_switch_device = {
254 .name = "dsa",
255 .id = 0,
256 .num_resources = 0,
257 .resource = kirkwood_switch_resources,
258};
259
260void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq) 111void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
261{ 112{
262 int i; 113 orion_ge00_switch_init(d, irq);
263
264 if (irq != NO_IRQ) {
265 kirkwood_switch_resources[0].start = irq;
266 kirkwood_switch_resources[0].end = irq;
267 kirkwood_switch_device.num_resources = 1;
268 }
269
270 d->netdev = &kirkwood_ge00.dev;
271 for (i = 0; i < d->nr_chips; i++)
272 d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
273 kirkwood_switch_device.dev.platform_data = d;
274
275 platform_device_register(&kirkwood_switch_device);
276} 114}
277 115
278 116
@@ -325,53 +163,23 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
325/***************************************************************************** 163/*****************************************************************************
326 * SoC RTC 164 * SoC RTC
327 ****************************************************************************/ 165 ****************************************************************************/
328static struct resource kirkwood_rtc_resource = {
329 .start = RTC_PHYS_BASE,
330 .end = RTC_PHYS_BASE + SZ_16 - 1,
331 .flags = IORESOURCE_MEM,
332};
333
334static void __init kirkwood_rtc_init(void) 166static void __init kirkwood_rtc_init(void)
335{ 167{
336 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); 168 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
337} 169}
338 170
339 171
340/***************************************************************************** 172/*****************************************************************************
341 * SATA 173 * SATA
342 ****************************************************************************/ 174 ****************************************************************************/
343static struct resource kirkwood_sata_resources[] = {
344 {
345 .name = "sata base",
346 .start = SATA_PHYS_BASE,
347 .end = SATA_PHYS_BASE + 0x5000 - 1,
348 .flags = IORESOURCE_MEM,
349 }, {
350 .name = "sata irq",
351 .start = IRQ_KIRKWOOD_SATA,
352 .end = IRQ_KIRKWOOD_SATA,
353 .flags = IORESOURCE_IRQ,
354 },
355};
356
357static struct platform_device kirkwood_sata = {
358 .name = "sata_mv",
359 .id = 0,
360 .dev = {
361 .coherent_dma_mask = 0xffffffff,
362 },
363 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
364 .resource = kirkwood_sata_resources,
365};
366
367void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) 175void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
368{ 176{
369 kirkwood_clk_ctrl |= CGC_SATA0; 177 kirkwood_clk_ctrl |= CGC_SATA0;
370 if (sata_data->n_ports > 1) 178 if (sata_data->n_ports > 1)
371 kirkwood_clk_ctrl |= CGC_SATA1; 179 kirkwood_clk_ctrl |= CGC_SATA1;
372 sata_data->dram = &kirkwood_mbus_dram_info; 180
373 kirkwood_sata.dev.platform_data = sata_data; 181 orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
374 platform_device_register(&kirkwood_sata); 182 SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
375} 183}
376 184
377 185
@@ -391,14 +199,14 @@ static struct resource mvsdio_resources[] = {
391 }, 199 },
392}; 200};
393 201
394static u64 mvsdio_dmamask = 0xffffffffUL; 202static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
395 203
396static struct platform_device kirkwood_sdio = { 204static struct platform_device kirkwood_sdio = {
397 .name = "mvsdio", 205 .name = "mvsdio",
398 .id = -1, 206 .id = -1,
399 .dev = { 207 .dev = {
400 .dma_mask = &mvsdio_dmamask, 208 .dma_mask = &mvsdio_dmamask,
401 .coherent_dma_mask = 0xffffffff, 209 .coherent_dma_mask = DMA_BIT_MASK(32),
402 }, 210 },
403 .num_resources = ARRAY_SIZE(mvsdio_resources), 211 .num_resources = ARRAY_SIZE(mvsdio_resources),
404 .resource = mvsdio_resources, 212 .resource = mvsdio_resources,
@@ -423,424 +231,84 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
423/***************************************************************************** 231/*****************************************************************************
424 * SPI 232 * SPI
425 ****************************************************************************/ 233 ****************************************************************************/
426static struct orion_spi_info kirkwood_spi_plat_data = {
427};
428
429static struct resource kirkwood_spi_resources[] = {
430 {
431 .start = SPI_PHYS_BASE,
432 .end = SPI_PHYS_BASE + SZ_512 - 1,
433 .flags = IORESOURCE_MEM,
434 },
435};
436
437static struct platform_device kirkwood_spi = {
438 .name = "orion_spi",
439 .id = 0,
440 .resource = kirkwood_spi_resources,
441 .dev = {
442 .platform_data = &kirkwood_spi_plat_data,
443 },
444 .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
445};
446
447void __init kirkwood_spi_init() 234void __init kirkwood_spi_init()
448{ 235{
449 kirkwood_clk_ctrl |= CGC_RUNIT; 236 kirkwood_clk_ctrl |= CGC_RUNIT;
450 platform_device_register(&kirkwood_spi); 237 orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
451} 238}
452 239
453 240
454/***************************************************************************** 241/*****************************************************************************
455 * I2C 242 * I2C
456 ****************************************************************************/ 243 ****************************************************************************/
457static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
458 .freq_m = 8, /* assumes 166 MHz TCLK */
459 .freq_n = 3,
460 .timeout = 1000, /* Default timeout of 1 second */
461};
462
463static struct resource kirkwood_i2c_resources[] = {
464 {
465 .start = I2C_PHYS_BASE,
466 .end = I2C_PHYS_BASE + 0x1f,
467 .flags = IORESOURCE_MEM,
468 }, {
469 .start = IRQ_KIRKWOOD_TWSI,
470 .end = IRQ_KIRKWOOD_TWSI,
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device kirkwood_i2c = {
476 .name = MV64XXX_I2C_CTLR_NAME,
477 .id = 0,
478 .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
479 .resource = kirkwood_i2c_resources,
480 .dev = {
481 .platform_data = &kirkwood_i2c_pdata,
482 },
483};
484
485void __init kirkwood_i2c_init(void) 244void __init kirkwood_i2c_init(void)
486{ 245{
487 platform_device_register(&kirkwood_i2c); 246 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
488} 247}
489 248
490 249
491/***************************************************************************** 250/*****************************************************************************
492 * UART0 251 * UART0
493 ****************************************************************************/ 252 ****************************************************************************/
494static struct plat_serial8250_port kirkwood_uart0_data[] = {
495 {
496 .mapbase = UART0_PHYS_BASE,
497 .membase = (char *)UART0_VIRT_BASE,
498 .irq = IRQ_KIRKWOOD_UART_0,
499 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
500 .iotype = UPIO_MEM,
501 .regshift = 2,
502 .uartclk = 0,
503 }, {
504 },
505};
506
507static struct resource kirkwood_uart0_resources[] = {
508 {
509 .start = UART0_PHYS_BASE,
510 .end = UART0_PHYS_BASE + 0xff,
511 .flags = IORESOURCE_MEM,
512 }, {
513 .start = IRQ_KIRKWOOD_UART_0,
514 .end = IRQ_KIRKWOOD_UART_0,
515 .flags = IORESOURCE_IRQ,
516 },
517};
518
519static struct platform_device kirkwood_uart0 = {
520 .name = "serial8250",
521 .id = 0,
522 .dev = {
523 .platform_data = kirkwood_uart0_data,
524 },
525 .resource = kirkwood_uart0_resources,
526 .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
527};
528 253
529void __init kirkwood_uart0_init(void) 254void __init kirkwood_uart0_init(void)
530{ 255{
531 platform_device_register(&kirkwood_uart0); 256 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
257 IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
532} 258}
533 259
534 260
535/***************************************************************************** 261/*****************************************************************************
536 * UART1 262 * UART1
537 ****************************************************************************/ 263 ****************************************************************************/
538static struct plat_serial8250_port kirkwood_uart1_data[] = {
539 {
540 .mapbase = UART1_PHYS_BASE,
541 .membase = (char *)UART1_VIRT_BASE,
542 .irq = IRQ_KIRKWOOD_UART_1,
543 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
544 .iotype = UPIO_MEM,
545 .regshift = 2,
546 .uartclk = 0,
547 }, {
548 },
549};
550
551static struct resource kirkwood_uart1_resources[] = {
552 {
553 .start = UART1_PHYS_BASE,
554 .end = UART1_PHYS_BASE + 0xff,
555 .flags = IORESOURCE_MEM,
556 }, {
557 .start = IRQ_KIRKWOOD_UART_1,
558 .end = IRQ_KIRKWOOD_UART_1,
559 .flags = IORESOURCE_IRQ,
560 },
561};
562
563static struct platform_device kirkwood_uart1 = {
564 .name = "serial8250",
565 .id = 1,
566 .dev = {
567 .platform_data = kirkwood_uart1_data,
568 },
569 .resource = kirkwood_uart1_resources,
570 .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
571};
572
573void __init kirkwood_uart1_init(void) 264void __init kirkwood_uart1_init(void)
574{ 265{
575 platform_device_register(&kirkwood_uart1); 266 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
267 IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
576} 268}
577 269
578
579/***************************************************************************** 270/*****************************************************************************
580 * Cryptographic Engines and Security Accelerator (CESA) 271 * Cryptographic Engines and Security Accelerator (CESA)
581 ****************************************************************************/ 272 ****************************************************************************/
582
583static struct resource kirkwood_crypto_res[] = {
584 {
585 .name = "regs",
586 .start = CRYPTO_PHYS_BASE,
587 .end = CRYPTO_PHYS_BASE + 0xffff,
588 .flags = IORESOURCE_MEM,
589 }, {
590 .name = "sram",
591 .start = KIRKWOOD_SRAM_PHYS_BASE,
592 .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
593 .flags = IORESOURCE_MEM,
594 }, {
595 .name = "crypto interrupt",
596 .start = IRQ_KIRKWOOD_CRYPTO,
597 .end = IRQ_KIRKWOOD_CRYPTO,
598 .flags = IORESOURCE_IRQ,
599 },
600};
601
602static struct platform_device kirkwood_crypto_device = {
603 .name = "mv_crypto",
604 .id = -1,
605 .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
606 .resource = kirkwood_crypto_res,
607};
608
609void __init kirkwood_crypto_init(void) 273void __init kirkwood_crypto_init(void)
610{ 274{
611 kirkwood_clk_ctrl |= CGC_CRYPTO; 275 kirkwood_clk_ctrl |= CGC_CRYPTO;
612 platform_device_register(&kirkwood_crypto_device); 276 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
277 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
613} 278}
614 279
615 280
616/***************************************************************************** 281/*****************************************************************************
617 * XOR
618 ****************************************************************************/
619static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
620 .dram = &kirkwood_mbus_dram_info,
621};
622
623static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
624
625
626/*****************************************************************************
627 * XOR0 282 * XOR0
628 ****************************************************************************/ 283 ****************************************************************************/
629static struct resource kirkwood_xor0_shared_resources[] = {
630 {
631 .name = "xor 0 low",
632 .start = XOR0_PHYS_BASE,
633 .end = XOR0_PHYS_BASE + 0xff,
634 .flags = IORESOURCE_MEM,
635 }, {
636 .name = "xor 0 high",
637 .start = XOR0_HIGH_PHYS_BASE,
638 .end = XOR0_HIGH_PHYS_BASE + 0xff,
639 .flags = IORESOURCE_MEM,
640 },
641};
642
643static struct platform_device kirkwood_xor0_shared = {
644 .name = MV_XOR_SHARED_NAME,
645 .id = 0,
646 .dev = {
647 .platform_data = &kirkwood_xor_shared_data,
648 },
649 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
650 .resource = kirkwood_xor0_shared_resources,
651};
652
653static struct resource kirkwood_xor00_resources[] = {
654 [0] = {
655 .start = IRQ_KIRKWOOD_XOR_00,
656 .end = IRQ_KIRKWOOD_XOR_00,
657 .flags = IORESOURCE_IRQ,
658 },
659};
660
661static struct mv_xor_platform_data kirkwood_xor00_data = {
662 .shared = &kirkwood_xor0_shared,
663 .hw_id = 0,
664 .pool_size = PAGE_SIZE,
665};
666
667static struct platform_device kirkwood_xor00_channel = {
668 .name = MV_XOR_NAME,
669 .id = 0,
670 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
671 .resource = kirkwood_xor00_resources,
672 .dev = {
673 .dma_mask = &kirkwood_xor_dmamask,
674 .coherent_dma_mask = DMA_BIT_MASK(64),
675 .platform_data = &kirkwood_xor00_data,
676 },
677};
678
679static struct resource kirkwood_xor01_resources[] = {
680 [0] = {
681 .start = IRQ_KIRKWOOD_XOR_01,
682 .end = IRQ_KIRKWOOD_XOR_01,
683 .flags = IORESOURCE_IRQ,
684 },
685};
686
687static struct mv_xor_platform_data kirkwood_xor01_data = {
688 .shared = &kirkwood_xor0_shared,
689 .hw_id = 1,
690 .pool_size = PAGE_SIZE,
691};
692
693static struct platform_device kirkwood_xor01_channel = {
694 .name = MV_XOR_NAME,
695 .id = 1,
696 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
697 .resource = kirkwood_xor01_resources,
698 .dev = {
699 .dma_mask = &kirkwood_xor_dmamask,
700 .coherent_dma_mask = DMA_BIT_MASK(64),
701 .platform_data = &kirkwood_xor01_data,
702 },
703};
704
705static void __init kirkwood_xor0_init(void) 284static void __init kirkwood_xor0_init(void)
706{ 285{
707 kirkwood_clk_ctrl |= CGC_XOR0; 286 kirkwood_clk_ctrl |= CGC_XOR0;
708 platform_device_register(&kirkwood_xor0_shared);
709 287
710 /* 288 orion_xor0_init(&kirkwood_mbus_dram_info,
711 * two engines can't do memset simultaneously, this limitation 289 XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
712 * satisfied by removing memset support from one of the engines. 290 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
713 */
714 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
715 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
716 platform_device_register(&kirkwood_xor00_channel);
717
718 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
719 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
720 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
721 platform_device_register(&kirkwood_xor01_channel);
722} 291}
723 292
724 293
725/***************************************************************************** 294/*****************************************************************************
726 * XOR1 295 * XOR1
727 ****************************************************************************/ 296 ****************************************************************************/
728static struct resource kirkwood_xor1_shared_resources[] = {
729 {
730 .name = "xor 1 low",
731 .start = XOR1_PHYS_BASE,
732 .end = XOR1_PHYS_BASE + 0xff,
733 .flags = IORESOURCE_MEM,
734 }, {
735 .name = "xor 1 high",
736 .start = XOR1_HIGH_PHYS_BASE,
737 .end = XOR1_HIGH_PHYS_BASE + 0xff,
738 .flags = IORESOURCE_MEM,
739 },
740};
741
742static struct platform_device kirkwood_xor1_shared = {
743 .name = MV_XOR_SHARED_NAME,
744 .id = 1,
745 .dev = {
746 .platform_data = &kirkwood_xor_shared_data,
747 },
748 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
749 .resource = kirkwood_xor1_shared_resources,
750};
751
752static struct resource kirkwood_xor10_resources[] = {
753 [0] = {
754 .start = IRQ_KIRKWOOD_XOR_10,
755 .end = IRQ_KIRKWOOD_XOR_10,
756 .flags = IORESOURCE_IRQ,
757 },
758};
759
760static struct mv_xor_platform_data kirkwood_xor10_data = {
761 .shared = &kirkwood_xor1_shared,
762 .hw_id = 0,
763 .pool_size = PAGE_SIZE,
764};
765
766static struct platform_device kirkwood_xor10_channel = {
767 .name = MV_XOR_NAME,
768 .id = 2,
769 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
770 .resource = kirkwood_xor10_resources,
771 .dev = {
772 .dma_mask = &kirkwood_xor_dmamask,
773 .coherent_dma_mask = DMA_BIT_MASK(64),
774 .platform_data = &kirkwood_xor10_data,
775 },
776};
777
778static struct resource kirkwood_xor11_resources[] = {
779 [0] = {
780 .start = IRQ_KIRKWOOD_XOR_11,
781 .end = IRQ_KIRKWOOD_XOR_11,
782 .flags = IORESOURCE_IRQ,
783 },
784};
785
786static struct mv_xor_platform_data kirkwood_xor11_data = {
787 .shared = &kirkwood_xor1_shared,
788 .hw_id = 1,
789 .pool_size = PAGE_SIZE,
790};
791
792static struct platform_device kirkwood_xor11_channel = {
793 .name = MV_XOR_NAME,
794 .id = 3,
795 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
796 .resource = kirkwood_xor11_resources,
797 .dev = {
798 .dma_mask = &kirkwood_xor_dmamask,
799 .coherent_dma_mask = DMA_BIT_MASK(64),
800 .platform_data = &kirkwood_xor11_data,
801 },
802};
803
804static void __init kirkwood_xor1_init(void) 297static void __init kirkwood_xor1_init(void)
805{ 298{
806 kirkwood_clk_ctrl |= CGC_XOR1; 299 kirkwood_clk_ctrl |= CGC_XOR1;
807 platform_device_register(&kirkwood_xor1_shared);
808 300
809 /* 301 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
810 * two engines can't do memset simultaneously, this limitation 302 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
811 * satisfied by removing memset support from one of the engines.
812 */
813 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
814 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
815 platform_device_register(&kirkwood_xor10_channel);
816
817 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
818 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
819 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
820 platform_device_register(&kirkwood_xor11_channel);
821} 303}
822 304
823 305
824/***************************************************************************** 306/*****************************************************************************
825 * Watchdog 307 * Watchdog
826 ****************************************************************************/ 308 ****************************************************************************/
827static struct orion_wdt_platform_data kirkwood_wdt_data = {
828 .tclk = 0,
829};
830
831static struct platform_device kirkwood_wdt_device = {
832 .name = "orion_wdt",
833 .id = -1,
834 .dev = {
835 .platform_data = &kirkwood_wdt_data,
836 },
837 .num_resources = 0,
838};
839
840static void __init kirkwood_wdt_init(void) 309static void __init kirkwood_wdt_init(void)
841{ 310{
842 kirkwood_wdt_data.tclk = kirkwood_tclk; 311 orion_wdt_init(kirkwood_tclk);
843 platform_device_register(&kirkwood_wdt_device);
844} 312}
845 313
846 314
@@ -984,11 +452,6 @@ void __init kirkwood_init(void)
984{ 452{
985 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n", 453 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
986 kirkwood_id(), kirkwood_tclk); 454 kirkwood_id(), kirkwood_tclk);
987 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
988 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
989 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
990 kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
991 kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
992 kirkwood_i2s_data.tclk = kirkwood_tclk; 455 kirkwood_i2s_data.tclk = kirkwood_tclk;
993 456
994 /* 457 /*
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb59180b..2bf8161e3b51 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -51,6 +51,7 @@
51#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41 51#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
52#define IRQ_KIRKWOOD_GE00_ERR 46 52#define IRQ_KIRKWOOD_GE00_ERR 46
53#define IRQ_KIRKWOOD_GE01_ERR 47 53#define IRQ_KIRKWOOD_GE01_ERR 47
54#define IRQ_KIRKWOOD_RTC 53
54 55
55/* 56/*
56 * KIRKWOOD General Purpose Pins 57 * KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7ce201848067..b0a7d979a8ed 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -14,6 +14,7 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/gpio.h> 15#include <asm/gpio.h>
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/mpp.h>
17#include "common.h" 18#include "common.h"
18#include "mpp.h" 19#include "mpp.h"
19 20
@@ -36,61 +37,8 @@ static unsigned int __init kirkwood_variant(void)
36 return 0; 37 return 0;
37} 38}
38 39
39#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
40#define MPP_NR_REGS (1 + MPP_MAX/8)
41
42void __init kirkwood_mpp_conf(unsigned int *mpp_list) 40void __init kirkwood_mpp_conf(unsigned int *mpp_list)
43{ 41{
44 u32 mpp_ctrl[MPP_NR_REGS]; 42 orion_mpp_conf(mpp_list, kirkwood_variant(),
45 unsigned int variant_mask; 43 MPP_MAX, DEV_BUS_VIRT_BASE);
46 int i;
47
48 variant_mask = kirkwood_variant();
49 if (!variant_mask)
50 return;
51
52 printk(KERN_DEBUG "initial MPP regs:");
53 for (i = 0; i < MPP_NR_REGS; i++) {
54 mpp_ctrl[i] = readl(MPP_CTRL(i));
55 printk(" %08x", mpp_ctrl[i]);
56 }
57 printk("\n");
58
59 for ( ; *mpp_list; mpp_list++) {
60 unsigned int num = MPP_NUM(*mpp_list);
61 unsigned int sel = MPP_SEL(*mpp_list);
62 int shift, gpio_mode;
63
64 if (num > MPP_MAX) {
65 printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
66 "number (%u)\n", num);
67 continue;
68 }
69 if (!(*mpp_list & variant_mask)) {
70 printk(KERN_WARNING
71 "kirkwood_mpp_conf: requested MPP%u config "
72 "unavailable on this hardware\n", num);
73 continue;
74 }
75
76 shift = (num & 7) << 2;
77 mpp_ctrl[num / 8] &= ~(0xf << shift);
78 mpp_ctrl[num / 8] |= sel << shift;
79
80 gpio_mode = 0;
81 if (*mpp_list & MPP_INPUT_MASK)
82 gpio_mode |= GPIO_INPUT_OK;
83 if (*mpp_list & MPP_OUTPUT_MASK)
84 gpio_mode |= GPIO_OUTPUT_OK;
85 if (sel != 0)
86 gpio_mode = 0;
87 orion_gpio_set_valid(num, gpio_mode);
88 }
89
90 printk(KERN_DEBUG " final MPP regs:");
91 for (i = 0; i < MPP_NR_REGS; i++) {
92 writel(mpp_ctrl[i], MPP_CTRL(i));
93 printk(" %08x", mpp_ctrl[i]);
94 }
95 printk("\n");
96} 44}
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index 9b0a94d85c3e..ac787957e2d9 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -22,14 +22,8 @@
22 /* available on F6281 */ ((!!(_F6281)) << 17) | \ 22 /* available on F6281 */ ((!!(_F6281)) << 17) | \
23 /* available on F6282 */ ((!!(_F6282)) << 18)) 23 /* available on F6282 */ ((!!(_F6282)) << 18))
24 24
25#define MPP_NUM(x) ((x) & 0xff)
26#define MPP_SEL(x) (((x) >> 8) & 0xf)
27
28 /* num sel i o 6180 6190 6192 6281 6282 */ 25 /* num sel i o 6180 6190 6192 6281 6282 */
29 26
30#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
31#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
32
33#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 ) 27#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
34#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 ) 28#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
35#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 ) 29#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index e41e909cf8f4..5f02664db812 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -13,7 +13,7 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h> 16#include <linux/dma-mapping.h>
17#include <asm/page.h> 17#include <asm/page.h>
18#include <asm/timex.h> 18#include <asm/timex.h>
19#include <asm/mach/map.h> 19#include <asm/mach/map.h>
@@ -22,6 +22,7 @@
22#include <mach/loki.h> 22#include <mach/loki.h>
23#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
24#include <plat/time.h> 24#include <plat/time.h>
25#include <plat/common.h>
25#include "common.h" 26#include "common.h"
26 27
27/***************************************************************************** 28/*****************************************************************************
@@ -43,116 +44,28 @@ void __init loki_map_io(void)
43 44
44 45
45/***************************************************************************** 46/*****************************************************************************
46 * GE0 47 * GE00
47 ****************************************************************************/ 48 ****************************************************************************/
48struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
49 .t_clk = LOKI_TCLK,
50 .dram = &loki_mbus_dram_info,
51};
52
53static struct resource loki_ge0_shared_resources[] = {
54 {
55 .name = "ge0 base",
56 .start = GE0_PHYS_BASE + 0x2000,
57 .end = GE0_PHYS_BASE + 0x3fff,
58 .flags = IORESOURCE_MEM,
59 },
60};
61
62static struct platform_device loki_ge0_shared = {
63 .name = MV643XX_ETH_SHARED_NAME,
64 .id = 0,
65 .dev = {
66 .platform_data = &loki_ge0_shared_data,
67 },
68 .num_resources = 1,
69 .resource = loki_ge0_shared_resources,
70};
71
72static struct resource loki_ge0_resources[] = {
73 {
74 .name = "ge0 irq",
75 .start = IRQ_LOKI_GBE_A_INT,
76 .end = IRQ_LOKI_GBE_A_INT,
77 .flags = IORESOURCE_IRQ,
78 },
79};
80
81static struct platform_device loki_ge0 = {
82 .name = MV643XX_ETH_NAME,
83 .id = 0,
84 .num_resources = 1,
85 .resource = loki_ge0_resources,
86 .dev = {
87 .coherent_dma_mask = 0xffffffff,
88 },
89};
90
91void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data) 49void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
92{ 50{
93 eth_data->shared = &loki_ge0_shared;
94 loki_ge0.dev.platform_data = eth_data;
95
96 writel(0x00079220, GE0_VIRT_BASE + 0x20b0); 51 writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
97 platform_device_register(&loki_ge0_shared); 52
98 platform_device_register(&loki_ge0); 53 orion_ge00_init(eth_data, &loki_mbus_dram_info,
54 GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
55 0, LOKI_TCLK);
99} 56}
100 57
101 58
102/***************************************************************************** 59/*****************************************************************************
103 * GE1 60 * GE01
104 ****************************************************************************/ 61 ****************************************************************************/
105struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
106 .t_clk = LOKI_TCLK,
107 .dram = &loki_mbus_dram_info,
108};
109
110static struct resource loki_ge1_shared_resources[] = {
111 {
112 .name = "ge1 base",
113 .start = GE1_PHYS_BASE + 0x2000,
114 .end = GE1_PHYS_BASE + 0x3fff,
115 .flags = IORESOURCE_MEM,
116 },
117};
118
119static struct platform_device loki_ge1_shared = {
120 .name = MV643XX_ETH_SHARED_NAME,
121 .id = 1,
122 .dev = {
123 .platform_data = &loki_ge1_shared_data,
124 },
125 .num_resources = 1,
126 .resource = loki_ge1_shared_resources,
127};
128
129static struct resource loki_ge1_resources[] = {
130 {
131 .name = "ge1 irq",
132 .start = IRQ_LOKI_GBE_B_INT,
133 .end = IRQ_LOKI_GBE_B_INT,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device loki_ge1 = {
139 .name = MV643XX_ETH_NAME,
140 .id = 1,
141 .num_resources = 1,
142 .resource = loki_ge1_resources,
143 .dev = {
144 .coherent_dma_mask = 0xffffffff,
145 },
146};
147
148void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data) 62void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
149{ 63{
150 eth_data->shared = &loki_ge1_shared;
151 loki_ge1.dev.platform_data = eth_data;
152
153 writel(0x00079220, GE1_VIRT_BASE + 0x20b0); 64 writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
154 platform_device_register(&loki_ge1_shared); 65
155 platform_device_register(&loki_ge1); 66 orion_ge01_init(eth_data, &loki_mbus_dram_info,
67 GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
68 0, LOKI_TCLK);
156} 69}
157 70
158 71
@@ -187,7 +100,7 @@ static struct platform_device loki_sas = {
187 .name = "mvsas", 100 .name = "mvsas",
188 .id = 0, 101 .id = 0,
189 .dev = { 102 .dev = {
190 .coherent_dma_mask = 0xffffffff, 103 .coherent_dma_mask = DMA_BIT_MASK(32),
191 }, 104 },
192 .num_resources = ARRAY_SIZE(loki_sas_resources), 105 .num_resources = ARRAY_SIZE(loki_sas_resources),
193 .resource = loki_sas_resources, 106 .resource = loki_sas_resources,
@@ -203,88 +116,19 @@ void __init loki_sas_init(void)
203/***************************************************************************** 116/*****************************************************************************
204 * UART0 117 * UART0
205 ****************************************************************************/ 118 ****************************************************************************/
206static struct plat_serial8250_port loki_uart0_data[] = {
207 {
208 .mapbase = UART0_PHYS_BASE,
209 .membase = (char *)UART0_VIRT_BASE,
210 .irq = IRQ_LOKI_UART0,
211 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
212 .iotype = UPIO_MEM,
213 .regshift = 2,
214 .uartclk = LOKI_TCLK,
215 }, {
216 },
217};
218
219static struct resource loki_uart0_resources[] = {
220 {
221 .start = UART0_PHYS_BASE,
222 .end = UART0_PHYS_BASE + 0xff,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = IRQ_LOKI_UART0,
226 .end = IRQ_LOKI_UART0,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231static struct platform_device loki_uart0 = {
232 .name = "serial8250",
233 .id = 0,
234 .dev = {
235 .platform_data = loki_uart0_data,
236 },
237 .resource = loki_uart0_resources,
238 .num_resources = ARRAY_SIZE(loki_uart0_resources),
239};
240
241void __init loki_uart0_init(void) 119void __init loki_uart0_init(void)
242{ 120{
243 platform_device_register(&loki_uart0); 121 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
122 IRQ_LOKI_UART0, LOKI_TCLK);
244} 123}
245 124
246
247/***************************************************************************** 125/*****************************************************************************
248 * UART1 126 * UART1
249 ****************************************************************************/ 127 ****************************************************************************/
250static struct plat_serial8250_port loki_uart1_data[] = {
251 {
252 .mapbase = UART1_PHYS_BASE,
253 .membase = (char *)UART1_VIRT_BASE,
254 .irq = IRQ_LOKI_UART1,
255 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
256 .iotype = UPIO_MEM,
257 .regshift = 2,
258 .uartclk = LOKI_TCLK,
259 }, {
260 },
261};
262
263static struct resource loki_uart1_resources[] = {
264 {
265 .start = UART1_PHYS_BASE,
266 .end = UART1_PHYS_BASE + 0xff,
267 .flags = IORESOURCE_MEM,
268 }, {
269 .start = IRQ_LOKI_UART1,
270 .end = IRQ_LOKI_UART1,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device loki_uart1 = {
276 .name = "serial8250",
277 .id = 1,
278 .dev = {
279 .platform_data = loki_uart1_data,
280 },
281 .resource = loki_uart1_resources,
282 .num_resources = ARRAY_SIZE(loki_uart1_resources),
283};
284
285void __init loki_uart1_init(void) 128void __init loki_uart1_init(void)
286{ 129{
287 platform_device_register(&loki_uart1); 130 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
131 IRQ_LOKI_UART1, LOKI_TCLK);
288} 132}
289 133
290 134
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 44fb4e55be0d..23d3980ef59d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,8 +13,6 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/serial_8250.h> 14#include <linux/serial_8250.h>
15#include <linux/mbus.h> 15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/mv643xx_i2c.h>
18#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
19#include <linux/ethtool.h> 17#include <linux/ethtool.h>
20#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -22,11 +20,12 @@
22#include <mach/mv78xx0.h> 20#include <mach/mv78xx0.h>
23#include <mach/bridge-regs.h> 21#include <mach/bridge-regs.h>
24#include <plat/cache-feroceon-l2.h> 22#include <plat/cache-feroceon-l2.h>
25#include <plat/ehci-orion.h>
26#include <plat/orion_nand.h> 23#include <plat/orion_nand.h>
27#include <plat/time.h> 24#include <plat/time.h>
25#include <plat/common.h>
28#include "common.h" 26#include "common.h"
29 27
28static int get_tclk(void);
30 29
31/***************************************************************************** 30/*****************************************************************************
32 * Common bits 31 * Common bits
@@ -168,285 +167,62 @@ void __init mv78xx0_map_io(void)
168/***************************************************************************** 167/*****************************************************************************
169 * EHCI 168 * EHCI
170 ****************************************************************************/ 169 ****************************************************************************/
171static struct orion_ehci_data mv78xx0_ehci_data = {
172 .dram = &mv78xx0_mbus_dram_info,
173 .phy_version = EHCI_PHY_NA,
174};
175
176static u64 ehci_dmamask = 0xffffffffUL;
177
178
179/*****************************************************************************
180 * EHCI0
181 ****************************************************************************/
182static struct resource mv78xx0_ehci0_resources[] = {
183 {
184 .start = USB0_PHYS_BASE,
185 .end = USB0_PHYS_BASE + 0x0fff,
186 .flags = IORESOURCE_MEM,
187 }, {
188 .start = IRQ_MV78XX0_USB_0,
189 .end = IRQ_MV78XX0_USB_0,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device mv78xx0_ehci0 = {
195 .name = "orion-ehci",
196 .id = 0,
197 .dev = {
198 .dma_mask = &ehci_dmamask,
199 .coherent_dma_mask = 0xffffffff,
200 .platform_data = &mv78xx0_ehci_data,
201 },
202 .resource = mv78xx0_ehci0_resources,
203 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
204};
205
206void __init mv78xx0_ehci0_init(void) 170void __init mv78xx0_ehci0_init(void)
207{ 171{
208 platform_device_register(&mv78xx0_ehci0); 172 orion_ehci_init(&mv78xx0_mbus_dram_info,
173 USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
209} 174}
210 175
211 176
212/***************************************************************************** 177/*****************************************************************************
213 * EHCI1 178 * EHCI1
214 ****************************************************************************/ 179 ****************************************************************************/
215static struct resource mv78xx0_ehci1_resources[] = {
216 {
217 .start = USB1_PHYS_BASE,
218 .end = USB1_PHYS_BASE + 0x0fff,
219 .flags = IORESOURCE_MEM,
220 }, {
221 .start = IRQ_MV78XX0_USB_1,
222 .end = IRQ_MV78XX0_USB_1,
223 .flags = IORESOURCE_IRQ,
224 },
225};
226
227static struct platform_device mv78xx0_ehci1 = {
228 .name = "orion-ehci",
229 .id = 1,
230 .dev = {
231 .dma_mask = &ehci_dmamask,
232 .coherent_dma_mask = 0xffffffff,
233 .platform_data = &mv78xx0_ehci_data,
234 },
235 .resource = mv78xx0_ehci1_resources,
236 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
237};
238
239void __init mv78xx0_ehci1_init(void) 180void __init mv78xx0_ehci1_init(void)
240{ 181{
241 platform_device_register(&mv78xx0_ehci1); 182 orion_ehci_1_init(&mv78xx0_mbus_dram_info,
183 USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
242} 184}
243 185
244 186
245/***************************************************************************** 187/*****************************************************************************
246 * EHCI2 188 * EHCI2
247 ****************************************************************************/ 189 ****************************************************************************/
248static struct resource mv78xx0_ehci2_resources[] = {
249 {
250 .start = USB2_PHYS_BASE,
251 .end = USB2_PHYS_BASE + 0x0fff,
252 .flags = IORESOURCE_MEM,
253 }, {
254 .start = IRQ_MV78XX0_USB_2,
255 .end = IRQ_MV78XX0_USB_2,
256 .flags = IORESOURCE_IRQ,
257 },
258};
259
260static struct platform_device mv78xx0_ehci2 = {
261 .name = "orion-ehci",
262 .id = 2,
263 .dev = {
264 .dma_mask = &ehci_dmamask,
265 .coherent_dma_mask = 0xffffffff,
266 .platform_data = &mv78xx0_ehci_data,
267 },
268 .resource = mv78xx0_ehci2_resources,
269 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
270};
271
272void __init mv78xx0_ehci2_init(void) 190void __init mv78xx0_ehci2_init(void)
273{ 191{
274 platform_device_register(&mv78xx0_ehci2); 192 orion_ehci_2_init(&mv78xx0_mbus_dram_info,
193 USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
275} 194}
276 195
277 196
278/***************************************************************************** 197/*****************************************************************************
279 * GE00 198 * GE00
280 ****************************************************************************/ 199 ****************************************************************************/
281struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
282 .t_clk = 0,
283 .dram = &mv78xx0_mbus_dram_info,
284};
285
286static struct resource mv78xx0_ge00_shared_resources[] = {
287 {
288 .name = "ge00 base",
289 .start = GE00_PHYS_BASE + 0x2000,
290 .end = GE00_PHYS_BASE + 0x3fff,
291 .flags = IORESOURCE_MEM,
292 }, {
293 .name = "ge err irq",
294 .start = IRQ_MV78XX0_GE_ERR,
295 .end = IRQ_MV78XX0_GE_ERR,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device mv78xx0_ge00_shared = {
301 .name = MV643XX_ETH_SHARED_NAME,
302 .id = 0,
303 .dev = {
304 .platform_data = &mv78xx0_ge00_shared_data,
305 },
306 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
307 .resource = mv78xx0_ge00_shared_resources,
308};
309
310static struct resource mv78xx0_ge00_resources[] = {
311 {
312 .name = "ge00 irq",
313 .start = IRQ_MV78XX0_GE00_SUM,
314 .end = IRQ_MV78XX0_GE00_SUM,
315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device mv78xx0_ge00 = {
320 .name = MV643XX_ETH_NAME,
321 .id = 0,
322 .num_resources = 1,
323 .resource = mv78xx0_ge00_resources,
324 .dev = {
325 .coherent_dma_mask = 0xffffffff,
326 },
327};
328
329void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) 200void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
330{ 201{
331 eth_data->shared = &mv78xx0_ge00_shared; 202 orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
332 mv78xx0_ge00.dev.platform_data = eth_data; 203 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
333 204 IRQ_MV78XX0_GE_ERR, get_tclk());
334 platform_device_register(&mv78xx0_ge00_shared);
335 platform_device_register(&mv78xx0_ge00);
336} 205}
337 206
338 207
339/***************************************************************************** 208/*****************************************************************************
340 * GE01 209 * GE01
341 ****************************************************************************/ 210 ****************************************************************************/
342struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
343 .t_clk = 0,
344 .dram = &mv78xx0_mbus_dram_info,
345 .shared_smi = &mv78xx0_ge00_shared,
346};
347
348static struct resource mv78xx0_ge01_shared_resources[] = {
349 {
350 .name = "ge01 base",
351 .start = GE01_PHYS_BASE + 0x2000,
352 .end = GE01_PHYS_BASE + 0x3fff,
353 .flags = IORESOURCE_MEM,
354 },
355};
356
357static struct platform_device mv78xx0_ge01_shared = {
358 .name = MV643XX_ETH_SHARED_NAME,
359 .id = 1,
360 .dev = {
361 .platform_data = &mv78xx0_ge01_shared_data,
362 },
363 .num_resources = 1,
364 .resource = mv78xx0_ge01_shared_resources,
365};
366
367static struct resource mv78xx0_ge01_resources[] = {
368 {
369 .name = "ge01 irq",
370 .start = IRQ_MV78XX0_GE01_SUM,
371 .end = IRQ_MV78XX0_GE01_SUM,
372 .flags = IORESOURCE_IRQ,
373 },
374};
375
376static struct platform_device mv78xx0_ge01 = {
377 .name = MV643XX_ETH_NAME,
378 .id = 1,
379 .num_resources = 1,
380 .resource = mv78xx0_ge01_resources,
381 .dev = {
382 .coherent_dma_mask = 0xffffffff,
383 },
384};
385
386void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) 211void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
387{ 212{
388 eth_data->shared = &mv78xx0_ge01_shared; 213 orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
389 mv78xx0_ge01.dev.platform_data = eth_data; 214 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
390 215 NO_IRQ, get_tclk());
391 platform_device_register(&mv78xx0_ge01_shared);
392 platform_device_register(&mv78xx0_ge01);
393} 216}
394 217
395 218
396/***************************************************************************** 219/*****************************************************************************
397 * GE10 220 * GE10
398 ****************************************************************************/ 221 ****************************************************************************/
399struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
400 .t_clk = 0,
401 .dram = &mv78xx0_mbus_dram_info,
402 .shared_smi = &mv78xx0_ge00_shared,
403};
404
405static struct resource mv78xx0_ge10_shared_resources[] = {
406 {
407 .name = "ge10 base",
408 .start = GE10_PHYS_BASE + 0x2000,
409 .end = GE10_PHYS_BASE + 0x3fff,
410 .flags = IORESOURCE_MEM,
411 },
412};
413
414static struct platform_device mv78xx0_ge10_shared = {
415 .name = MV643XX_ETH_SHARED_NAME,
416 .id = 2,
417 .dev = {
418 .platform_data = &mv78xx0_ge10_shared_data,
419 },
420 .num_resources = 1,
421 .resource = mv78xx0_ge10_shared_resources,
422};
423
424static struct resource mv78xx0_ge10_resources[] = {
425 {
426 .name = "ge10 irq",
427 .start = IRQ_MV78XX0_GE10_SUM,
428 .end = IRQ_MV78XX0_GE10_SUM,
429 .flags = IORESOURCE_IRQ,
430 },
431};
432
433static struct platform_device mv78xx0_ge10 = {
434 .name = MV643XX_ETH_NAME,
435 .id = 2,
436 .num_resources = 1,
437 .resource = mv78xx0_ge10_resources,
438 .dev = {
439 .coherent_dma_mask = 0xffffffff,
440 },
441};
442
443void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) 222void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
444{ 223{
445 u32 dev, rev; 224 u32 dev, rev;
446 225
447 eth_data->shared = &mv78xx0_ge10_shared;
448 mv78xx0_ge10.dev.platform_data = eth_data;
449
450 /* 226 /*
451 * On the Z0, ge10 and ge11 are internally connected back 227 * On the Z0, ge10 and ge11 are internally connected back
452 * to back, and not brought out. 228 * to back, and not brought out.
@@ -458,65 +234,19 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
458 eth_data->duplex = DUPLEX_FULL; 234 eth_data->duplex = DUPLEX_FULL;
459 } 235 }
460 236
461 platform_device_register(&mv78xx0_ge10_shared); 237 orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
462 platform_device_register(&mv78xx0_ge10); 238 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
239 NO_IRQ, get_tclk());
463} 240}
464 241
465 242
466/***************************************************************************** 243/*****************************************************************************
467 * GE11 244 * GE11
468 ****************************************************************************/ 245 ****************************************************************************/
469struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
470 .t_clk = 0,
471 .dram = &mv78xx0_mbus_dram_info,
472 .shared_smi = &mv78xx0_ge00_shared,
473};
474
475static struct resource mv78xx0_ge11_shared_resources[] = {
476 {
477 .name = "ge11 base",
478 .start = GE11_PHYS_BASE + 0x2000,
479 .end = GE11_PHYS_BASE + 0x3fff,
480 .flags = IORESOURCE_MEM,
481 },
482};
483
484static struct platform_device mv78xx0_ge11_shared = {
485 .name = MV643XX_ETH_SHARED_NAME,
486 .id = 3,
487 .dev = {
488 .platform_data = &mv78xx0_ge11_shared_data,
489 },
490 .num_resources = 1,
491 .resource = mv78xx0_ge11_shared_resources,
492};
493
494static struct resource mv78xx0_ge11_resources[] = {
495 {
496 .name = "ge11 irq",
497 .start = IRQ_MV78XX0_GE11_SUM,
498 .end = IRQ_MV78XX0_GE11_SUM,
499 .flags = IORESOURCE_IRQ,
500 },
501};
502
503static struct platform_device mv78xx0_ge11 = {
504 .name = MV643XX_ETH_NAME,
505 .id = 3,
506 .num_resources = 1,
507 .resource = mv78xx0_ge11_resources,
508 .dev = {
509 .coherent_dma_mask = 0xffffffff,
510 },
511};
512
513void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) 246void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
514{ 247{
515 u32 dev, rev; 248 u32 dev, rev;
516 249
517 eth_data->shared = &mv78xx0_ge11_shared;
518 mv78xx0_ge11.dev.platform_data = eth_data;
519
520 /* 250 /*
521 * On the Z0, ge10 and ge11 are internally connected back 251 * On the Z0, ge10 and ge11 are internally connected back
522 * to back, and not brought out. 252 * to back, and not brought out.
@@ -528,293 +258,68 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
528 eth_data->duplex = DUPLEX_FULL; 258 eth_data->duplex = DUPLEX_FULL;
529 } 259 }
530 260
531 platform_device_register(&mv78xx0_ge11_shared); 261 orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
532 platform_device_register(&mv78xx0_ge11); 262 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
263 NO_IRQ, get_tclk());
533} 264}
534 265
535/***************************************************************************** 266/*****************************************************************************
536 * I2C bus 0 267 * I2C
537 ****************************************************************************/
538
539static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
540 .freq_m = 8, /* assumes 166 MHz TCLK */
541 .freq_n = 3,
542 .timeout = 1000, /* Default timeout of 1 second */
543};
544
545static struct resource mv78xx0_i2c_0_resources[] = {
546 {
547 .start = I2C_0_PHYS_BASE,
548 .end = I2C_0_PHYS_BASE + 0x1f,
549 .flags = IORESOURCE_MEM,
550 }, {
551 .start = IRQ_MV78XX0_I2C_0,
552 .end = IRQ_MV78XX0_I2C_0,
553 .flags = IORESOURCE_IRQ,
554 },
555};
556
557
558static struct platform_device mv78xx0_i2c_0 = {
559 .name = MV64XXX_I2C_CTLR_NAME,
560 .id = 0,
561 .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
562 .resource = mv78xx0_i2c_0_resources,
563 .dev = {
564 .platform_data = &mv78xx0_i2c_0_pdata,
565 },
566};
567
568/*****************************************************************************
569 * I2C bus 1
570 ****************************************************************************/ 268 ****************************************************************************/
571
572static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
573 .freq_m = 8, /* assumes 166 MHz TCLK */
574 .freq_n = 3,
575 .timeout = 1000, /* Default timeout of 1 second */
576};
577
578static struct resource mv78xx0_i2c_1_resources[] = {
579 {
580 .start = I2C_1_PHYS_BASE,
581 .end = I2C_1_PHYS_BASE + 0x1f,
582 .flags = IORESOURCE_MEM,
583 }, {
584 .start = IRQ_MV78XX0_I2C_1,
585 .end = IRQ_MV78XX0_I2C_1,
586 .flags = IORESOURCE_IRQ,
587 },
588};
589
590
591static struct platform_device mv78xx0_i2c_1 = {
592 .name = MV64XXX_I2C_CTLR_NAME,
593 .id = 1,
594 .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
595 .resource = mv78xx0_i2c_1_resources,
596 .dev = {
597 .platform_data = &mv78xx0_i2c_1_pdata,
598 },
599};
600
601void __init mv78xx0_i2c_init(void) 269void __init mv78xx0_i2c_init(void)
602{ 270{
603 platform_device_register(&mv78xx0_i2c_0); 271 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
604 platform_device_register(&mv78xx0_i2c_1); 272 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
605} 273}
606 274
607/***************************************************************************** 275/*****************************************************************************
608 * SATA 276 * SATA
609 ****************************************************************************/ 277 ****************************************************************************/
610static struct resource mv78xx0_sata_resources[] = {
611 {
612 .name = "sata base",
613 .start = SATA_PHYS_BASE,
614 .end = SATA_PHYS_BASE + 0x5000 - 1,
615 .flags = IORESOURCE_MEM,
616 }, {
617 .name = "sata irq",
618 .start = IRQ_MV78XX0_SATA,
619 .end = IRQ_MV78XX0_SATA,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
624static struct platform_device mv78xx0_sata = {
625 .name = "sata_mv",
626 .id = 0,
627 .dev = {
628 .coherent_dma_mask = 0xffffffff,
629 },
630 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
631 .resource = mv78xx0_sata_resources,
632};
633
634void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data) 278void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
635{ 279{
636 sata_data->dram = &mv78xx0_mbus_dram_info; 280 orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
637 mv78xx0_sata.dev.platform_data = sata_data; 281 SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
638 platform_device_register(&mv78xx0_sata);
639} 282}
640 283
641 284
642/***************************************************************************** 285/*****************************************************************************
643 * UART0 286 * UART0
644 ****************************************************************************/ 287 ****************************************************************************/
645static struct plat_serial8250_port mv78xx0_uart0_data[] = {
646 {
647 .mapbase = UART0_PHYS_BASE,
648 .membase = (char *)UART0_VIRT_BASE,
649 .irq = IRQ_MV78XX0_UART_0,
650 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
651 .iotype = UPIO_MEM,
652 .regshift = 2,
653 .uartclk = 0,
654 }, {
655 },
656};
657
658static struct resource mv78xx0_uart0_resources[] = {
659 {
660 .start = UART0_PHYS_BASE,
661 .end = UART0_PHYS_BASE + 0xff,
662 .flags = IORESOURCE_MEM,
663 }, {
664 .start = IRQ_MV78XX0_UART_0,
665 .end = IRQ_MV78XX0_UART_0,
666 .flags = IORESOURCE_IRQ,
667 },
668};
669
670static struct platform_device mv78xx0_uart0 = {
671 .name = "serial8250",
672 .id = 0,
673 .dev = {
674 .platform_data = mv78xx0_uart0_data,
675 },
676 .resource = mv78xx0_uart0_resources,
677 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
678};
679
680void __init mv78xx0_uart0_init(void) 288void __init mv78xx0_uart0_init(void)
681{ 289{
682 platform_device_register(&mv78xx0_uart0); 290 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
291 IRQ_MV78XX0_UART_0, get_tclk());
683} 292}
684 293
685 294
686/***************************************************************************** 295/*****************************************************************************
687 * UART1 296 * UART1
688 ****************************************************************************/ 297 ****************************************************************************/
689static struct plat_serial8250_port mv78xx0_uart1_data[] = {
690 {
691 .mapbase = UART1_PHYS_BASE,
692 .membase = (char *)UART1_VIRT_BASE,
693 .irq = IRQ_MV78XX0_UART_1,
694 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
695 .iotype = UPIO_MEM,
696 .regshift = 2,
697 .uartclk = 0,
698 }, {
699 },
700};
701
702static struct resource mv78xx0_uart1_resources[] = {
703 {
704 .start = UART1_PHYS_BASE,
705 .end = UART1_PHYS_BASE + 0xff,
706 .flags = IORESOURCE_MEM,
707 }, {
708 .start = IRQ_MV78XX0_UART_1,
709 .end = IRQ_MV78XX0_UART_1,
710 .flags = IORESOURCE_IRQ,
711 },
712};
713
714static struct platform_device mv78xx0_uart1 = {
715 .name = "serial8250",
716 .id = 1,
717 .dev = {
718 .platform_data = mv78xx0_uart1_data,
719 },
720 .resource = mv78xx0_uart1_resources,
721 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
722};
723
724void __init mv78xx0_uart1_init(void) 298void __init mv78xx0_uart1_init(void)
725{ 299{
726 platform_device_register(&mv78xx0_uart1); 300 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
301 IRQ_MV78XX0_UART_1, get_tclk());
727} 302}
728 303
729 304
730/***************************************************************************** 305/*****************************************************************************
731 * UART2 306 * UART2
732 ****************************************************************************/ 307 ****************************************************************************/
733static struct plat_serial8250_port mv78xx0_uart2_data[] = {
734 {
735 .mapbase = UART2_PHYS_BASE,
736 .membase = (char *)UART2_VIRT_BASE,
737 .irq = IRQ_MV78XX0_UART_2,
738 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
739 .iotype = UPIO_MEM,
740 .regshift = 2,
741 .uartclk = 0,
742 }, {
743 },
744};
745
746static struct resource mv78xx0_uart2_resources[] = {
747 {
748 .start = UART2_PHYS_BASE,
749 .end = UART2_PHYS_BASE + 0xff,
750 .flags = IORESOURCE_MEM,
751 }, {
752 .start = IRQ_MV78XX0_UART_2,
753 .end = IRQ_MV78XX0_UART_2,
754 .flags = IORESOURCE_IRQ,
755 },
756};
757
758static struct platform_device mv78xx0_uart2 = {
759 .name = "serial8250",
760 .id = 2,
761 .dev = {
762 .platform_data = mv78xx0_uart2_data,
763 },
764 .resource = mv78xx0_uart2_resources,
765 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
766};
767
768void __init mv78xx0_uart2_init(void) 308void __init mv78xx0_uart2_init(void)
769{ 309{
770 platform_device_register(&mv78xx0_uart2); 310 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
311 IRQ_MV78XX0_UART_2, get_tclk());
771} 312}
772 313
773
774/***************************************************************************** 314/*****************************************************************************
775 * UART3 315 * UART3
776 ****************************************************************************/ 316 ****************************************************************************/
777static struct plat_serial8250_port mv78xx0_uart3_data[] = {
778 {
779 .mapbase = UART3_PHYS_BASE,
780 .membase = (char *)UART3_VIRT_BASE,
781 .irq = IRQ_MV78XX0_UART_3,
782 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
783 .iotype = UPIO_MEM,
784 .regshift = 2,
785 .uartclk = 0,
786 }, {
787 },
788};
789
790static struct resource mv78xx0_uart3_resources[] = {
791 {
792 .start = UART3_PHYS_BASE,
793 .end = UART3_PHYS_BASE + 0xff,
794 .flags = IORESOURCE_MEM,
795 }, {
796 .start = IRQ_MV78XX0_UART_3,
797 .end = IRQ_MV78XX0_UART_3,
798 .flags = IORESOURCE_IRQ,
799 },
800};
801
802static struct platform_device mv78xx0_uart3 = {
803 .name = "serial8250",
804 .id = 3,
805 .dev = {
806 .platform_data = mv78xx0_uart3_data,
807 },
808 .resource = mv78xx0_uart3_resources,
809 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
810};
811
812void __init mv78xx0_uart3_init(void) 317void __init mv78xx0_uart3_init(void)
813{ 318{
814 platform_device_register(&mv78xx0_uart3); 319 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
320 IRQ_MV78XX0_UART_3, get_tclk());
815} 321}
816 322
817
818/***************************************************************************** 323/*****************************************************************************
819 * Time handling 324 * Time handling
820 ****************************************************************************/ 325 ****************************************************************************/
@@ -895,13 +400,4 @@ void __init mv78xx0_init(void)
895#ifdef CONFIG_CACHE_FEROCEON_L2 400#ifdef CONFIG_CACHE_FEROCEON_L2
896 feroceon_l2_init(is_l2_writethrough()); 401 feroceon_l2_init(is_l2_writethrough());
897#endif 402#endif
898
899 mv78xx0_ge00_shared_data.t_clk = tclk;
900 mv78xx0_ge01_shared_data.t_clk = tclk;
901 mv78xx0_ge10_shared_data.t_clk = tclk;
902 mv78xx0_ge11_shared_data.t_clk = tclk;
903 mv78xx0_uart0_data[0].uartclk = tclk;
904 mv78xx0_uart1_data[0].uartclk = tclk;
905 mv78xx0_uart2_data[0].uartclk = tclk;
906 mv78xx0_uart3_data[0].uartclk = tclk;
907} 403}
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 65b72c454cb0..59b7686b9209 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/mpp.h>
15#include <asm/gpio.h> 16#include <asm/gpio.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include "common.h" 18#include "common.h"
@@ -31,61 +32,8 @@ static unsigned int __init mv78xx0_variant(void)
31 return 0; 32 return 0;
32} 33}
33 34
34#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
35#define MPP_NR_REGS (1 + MPP_MAX/8)
36
37void __init mv78xx0_mpp_conf(unsigned int *mpp_list) 35void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
38{ 36{
39 u32 mpp_ctrl[MPP_NR_REGS]; 37 orion_mpp_conf(mpp_list, mv78xx0_variant(),
40 unsigned int variant_mask; 38 MPP_MAX, DEV_BUS_VIRT_BASE);
41 int i;
42
43 variant_mask = mv78xx0_variant();
44 if (!variant_mask)
45 return;
46
47 printk(KERN_DEBUG "initial MPP regs:");
48 for (i = 0; i < MPP_NR_REGS; i++) {
49 mpp_ctrl[i] = readl(MPP_CTRL(i));
50 printk(" %08x", mpp_ctrl[i]);
51 }
52 printk("\n");
53
54 for ( ; *mpp_list; mpp_list++) {
55 unsigned int num = MPP_NUM(*mpp_list);
56 unsigned int sel = MPP_SEL(*mpp_list);
57 int shift, gpio_mode;
58
59 if (num > MPP_MAX) {
60 printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
61 "number (%u)\n", num);
62 continue;
63 }
64 if (!(*mpp_list & variant_mask)) {
65 printk(KERN_WARNING
66 "mv78xx0_mpp_conf: requested MPP%u config "
67 "unavailable on this hardware\n", num);
68 continue;
69 }
70
71 shift = (num & 7) << 2;
72 mpp_ctrl[num / 8] &= ~(0xf << shift);
73 mpp_ctrl[num / 8] |= sel << shift;
74
75 gpio_mode = 0;
76 if (*mpp_list & MPP_INPUT_MASK)
77 gpio_mode |= GPIO_INPUT_OK;
78 if (*mpp_list & MPP_OUTPUT_MASK)
79 gpio_mode |= GPIO_OUTPUT_OK;
80 if (sel != 0)
81 gpio_mode = 0;
82 orion_gpio_set_valid(num, gpio_mode);
83 }
84
85 printk(KERN_DEBUG " final MPP regs:");
86 for (i = 0; i < MPP_NR_REGS; i++) {
87 writel(mpp_ctrl[i], MPP_CTRL(i));
88 printk(" %08x", mpp_ctrl[i]);
89 }
90 printk("\n");
91} 39}
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 80840b781eaa..b61b50927123 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -19,14 +19,8 @@
19 /* may be output signal */ ((!!(_out)) << 13) | \ 19 /* may be output signal */ ((!!(_out)) << 13) | \
20 /* available on A0 */ ((!!(_78100_A0)) << 14)) 20 /* available on A0 */ ((!!(_78100_A0)) << 14))
21 21
22#define MPP_NUM(x) ((x) & 0xff)
23#define MPP_SEL(x) (((x) >> 8) & 0xf)
24
25 /* num sel i o 78100_A0 */ 22 /* num sel i o 78100_A0 */
26 23
27#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0)
28#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0)
29
30#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) 24#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
31 25
32#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) 26#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 986c3bf4e6b8..0ab531d047fc 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,12 +13,11 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
16#include <linux/serial_8250.h> 17#include <linux/serial_8250.h>
17#include <linux/mbus.h> 18#include <linux/mbus.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h> 19#include <linux/mv643xx_i2c.h>
20#include <linux/ata_platform.h> 20#include <linux/ata_platform.h>
21#include <linux/spi/orion_spi.h>
22#include <net/dsa.h> 21#include <net/dsa.h>
23#include <asm/page.h> 22#include <asm/page.h>
24#include <asm/setup.h> 23#include <asm/setup.h>
@@ -29,11 +28,9 @@
29#include <mach/bridge-regs.h> 28#include <mach/bridge-regs.h>
30#include <mach/hardware.h> 29#include <mach/hardware.h>
31#include <mach/orion5x.h> 30#include <mach/orion5x.h>
32#include <plat/ehci-orion.h>
33#include <plat/mv_xor.h>
34#include <plat/orion_nand.h> 31#include <plat/orion_nand.h>
35#include <plat/orion_wdt.h>
36#include <plat/time.h> 32#include <plat/time.h>
33#include <plat/common.h>
37#include "common.h" 34#include "common.h"
38 35
39/***************************************************************************** 36/*****************************************************************************
@@ -70,530 +67,124 @@ void __init orion5x_map_io(void)
70 67
71 68
72/***************************************************************************** 69/*****************************************************************************
73 * EHCI
74 ****************************************************************************/
75static struct orion_ehci_data orion5x_ehci_data = {
76 .dram = &orion5x_mbus_dram_info,
77 .phy_version = EHCI_PHY_ORION,
78};
79
80static u64 ehci_dmamask = 0xffffffffUL;
81
82
83/*****************************************************************************
84 * EHCI0 70 * EHCI0
85 ****************************************************************************/ 71 ****************************************************************************/
86static struct resource orion5x_ehci0_resources[] = {
87 {
88 .start = ORION5X_USB0_PHYS_BASE,
89 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
90 .flags = IORESOURCE_MEM,
91 }, {
92 .start = IRQ_ORION5X_USB0_CTRL,
93 .end = IRQ_ORION5X_USB0_CTRL,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct platform_device orion5x_ehci0 = {
99 .name = "orion-ehci",
100 .id = 0,
101 .dev = {
102 .dma_mask = &ehci_dmamask,
103 .coherent_dma_mask = 0xffffffff,
104 .platform_data = &orion5x_ehci_data,
105 },
106 .resource = orion5x_ehci0_resources,
107 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
108};
109
110void __init orion5x_ehci0_init(void) 72void __init orion5x_ehci0_init(void)
111{ 73{
112 platform_device_register(&orion5x_ehci0); 74 orion_ehci_init(&orion5x_mbus_dram_info,
75 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
113} 76}
114 77
115 78
116/***************************************************************************** 79/*****************************************************************************
117 * EHCI1 80 * EHCI1
118 ****************************************************************************/ 81 ****************************************************************************/
119static struct resource orion5x_ehci1_resources[] = {
120 {
121 .start = ORION5X_USB1_PHYS_BASE,
122 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
123 .flags = IORESOURCE_MEM,
124 }, {
125 .start = IRQ_ORION5X_USB1_CTRL,
126 .end = IRQ_ORION5X_USB1_CTRL,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct platform_device orion5x_ehci1 = {
132 .name = "orion-ehci",
133 .id = 1,
134 .dev = {
135 .dma_mask = &ehci_dmamask,
136 .coherent_dma_mask = 0xffffffff,
137 .platform_data = &orion5x_ehci_data,
138 },
139 .resource = orion5x_ehci1_resources,
140 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
141};
142
143void __init orion5x_ehci1_init(void) 82void __init orion5x_ehci1_init(void)
144{ 83{
145 platform_device_register(&orion5x_ehci1); 84 orion_ehci_1_init(&orion5x_mbus_dram_info,
85 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
146} 86}
147 87
148 88
149/***************************************************************************** 89/*****************************************************************************
150 * GigE 90 * GE00
151 ****************************************************************************/ 91 ****************************************************************************/
152struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
153 .dram = &orion5x_mbus_dram_info,
154};
155
156static struct resource orion5x_eth_shared_resources[] = {
157 {
158 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
159 .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
160 .flags = IORESOURCE_MEM,
161 }, {
162 .start = IRQ_ORION5X_ETH_ERR,
163 .end = IRQ_ORION5X_ETH_ERR,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device orion5x_eth_shared = {
169 .name = MV643XX_ETH_SHARED_NAME,
170 .id = 0,
171 .dev = {
172 .platform_data = &orion5x_eth_shared_data,
173 },
174 .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
175 .resource = orion5x_eth_shared_resources,
176};
177
178static struct resource orion5x_eth_resources[] = {
179 {
180 .name = "eth irq",
181 .start = IRQ_ORION5X_ETH_SUM,
182 .end = IRQ_ORION5X_ETH_SUM,
183 .flags = IORESOURCE_IRQ,
184 },
185};
186
187static struct platform_device orion5x_eth = {
188 .name = MV643XX_ETH_NAME,
189 .id = 0,
190 .num_resources = 1,
191 .resource = orion5x_eth_resources,
192 .dev = {
193 .coherent_dma_mask = 0xffffffff,
194 },
195};
196
197void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 92void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
198{ 93{
199 eth_data->shared = &orion5x_eth_shared; 94 orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
200 orion5x_eth.dev.platform_data = eth_data; 95 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
201 96 IRQ_ORION5X_ETH_ERR, orion5x_tclk);
202 platform_device_register(&orion5x_eth_shared);
203 platform_device_register(&orion5x_eth);
204} 97}
205 98
206 99
207/***************************************************************************** 100/*****************************************************************************
208 * Ethernet switch 101 * Ethernet switch
209 ****************************************************************************/ 102 ****************************************************************************/
210static struct resource orion5x_switch_resources[] = {
211 {
212 .start = 0,
213 .end = 0,
214 .flags = IORESOURCE_IRQ,
215 },
216};
217
218static struct platform_device orion5x_switch_device = {
219 .name = "dsa",
220 .id = 0,
221 .num_resources = 0,
222 .resource = orion5x_switch_resources,
223};
224
225void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq) 103void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
226{ 104{
227 int i; 105 orion_ge00_switch_init(d, irq);
228
229 if (irq != NO_IRQ) {
230 orion5x_switch_resources[0].start = irq;
231 orion5x_switch_resources[0].end = irq;
232 orion5x_switch_device.num_resources = 1;
233 }
234
235 d->netdev = &orion5x_eth.dev;
236 for (i = 0; i < d->nr_chips; i++)
237 d->chip[i].mii_bus = &orion5x_eth_shared.dev;
238 orion5x_switch_device.dev.platform_data = d;
239
240 platform_device_register(&orion5x_switch_device);
241} 106}
242 107
243 108
244/***************************************************************************** 109/*****************************************************************************
245 * I2C 110 * I2C
246 ****************************************************************************/ 111 ****************************************************************************/
247static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
248 .freq_m = 8, /* assumes 166 MHz TCLK */
249 .freq_n = 3,
250 .timeout = 1000, /* Default timeout of 1 second */
251};
252
253static struct resource orion5x_i2c_resources[] = {
254 {
255 .start = I2C_PHYS_BASE,
256 .end = I2C_PHYS_BASE + 0x1f,
257 .flags = IORESOURCE_MEM,
258 }, {
259 .start = IRQ_ORION5X_I2C,
260 .end = IRQ_ORION5X_I2C,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device orion5x_i2c = {
266 .name = MV64XXX_I2C_CTLR_NAME,
267 .id = 0,
268 .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
269 .resource = orion5x_i2c_resources,
270 .dev = {
271 .platform_data = &orion5x_i2c_pdata,
272 },
273};
274
275void __init orion5x_i2c_init(void) 112void __init orion5x_i2c_init(void)
276{ 113{
277 platform_device_register(&orion5x_i2c); 114 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
115
278} 116}
279 117
280 118
281/***************************************************************************** 119/*****************************************************************************
282 * SATA 120 * SATA
283 ****************************************************************************/ 121 ****************************************************************************/
284static struct resource orion5x_sata_resources[] = {
285 {
286 .name = "sata base",
287 .start = ORION5X_SATA_PHYS_BASE,
288 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
289 .flags = IORESOURCE_MEM,
290 }, {
291 .name = "sata irq",
292 .start = IRQ_ORION5X_SATA,
293 .end = IRQ_ORION5X_SATA,
294 .flags = IORESOURCE_IRQ,
295 },
296};
297
298static struct platform_device orion5x_sata = {
299 .name = "sata_mv",
300 .id = 0,
301 .dev = {
302 .coherent_dma_mask = 0xffffffff,
303 },
304 .num_resources = ARRAY_SIZE(orion5x_sata_resources),
305 .resource = orion5x_sata_resources,
306};
307
308void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 122void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
309{ 123{
310 sata_data->dram = &orion5x_mbus_dram_info; 124 orion_sata_init(sata_data, &orion5x_mbus_dram_info,
311 orion5x_sata.dev.platform_data = sata_data; 125 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
312 platform_device_register(&orion5x_sata);
313} 126}
314 127
315 128
316/***************************************************************************** 129/*****************************************************************************
317 * SPI 130 * SPI
318 ****************************************************************************/ 131 ****************************************************************************/
319static struct orion_spi_info orion5x_spi_plat_data = {
320 .tclk = 0,
321 .enable_clock_fix = 1,
322};
323
324static struct resource orion5x_spi_resources[] = {
325 {
326 .name = "spi base",
327 .start = SPI_PHYS_BASE,
328 .end = SPI_PHYS_BASE + 0x1f,
329 .flags = IORESOURCE_MEM,
330 },
331};
332
333static struct platform_device orion5x_spi = {
334 .name = "orion_spi",
335 .id = 0,
336 .dev = {
337 .platform_data = &orion5x_spi_plat_data,
338 },
339 .num_resources = ARRAY_SIZE(orion5x_spi_resources),
340 .resource = orion5x_spi_resources,
341};
342
343void __init orion5x_spi_init() 132void __init orion5x_spi_init()
344{ 133{
345 platform_device_register(&orion5x_spi); 134 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
346} 135}
347 136
348 137
349/***************************************************************************** 138/*****************************************************************************
350 * UART0 139 * UART0
351 ****************************************************************************/ 140 ****************************************************************************/
352static struct plat_serial8250_port orion5x_uart0_data[] = {
353 {
354 .mapbase = UART0_PHYS_BASE,
355 .membase = (char *)UART0_VIRT_BASE,
356 .irq = IRQ_ORION5X_UART0,
357 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
358 .iotype = UPIO_MEM,
359 .regshift = 2,
360 .uartclk = 0,
361 }, {
362 },
363};
364
365static struct resource orion5x_uart0_resources[] = {
366 {
367 .start = UART0_PHYS_BASE,
368 .end = UART0_PHYS_BASE + 0xff,
369 .flags = IORESOURCE_MEM,
370 }, {
371 .start = IRQ_ORION5X_UART0,
372 .end = IRQ_ORION5X_UART0,
373 .flags = IORESOURCE_IRQ,
374 },
375};
376
377static struct platform_device orion5x_uart0 = {
378 .name = "serial8250",
379 .id = PLAT8250_DEV_PLATFORM,
380 .dev = {
381 .platform_data = orion5x_uart0_data,
382 },
383 .resource = orion5x_uart0_resources,
384 .num_resources = ARRAY_SIZE(orion5x_uart0_resources),
385};
386
387void __init orion5x_uart0_init(void) 141void __init orion5x_uart0_init(void)
388{ 142{
389 platform_device_register(&orion5x_uart0); 143 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
144 IRQ_ORION5X_UART0, orion5x_tclk);
390} 145}
391 146
392
393/***************************************************************************** 147/*****************************************************************************
394 * UART1 148 * UART1
395 ****************************************************************************/ 149 ****************************************************************************/
396static struct plat_serial8250_port orion5x_uart1_data[] = {
397 {
398 .mapbase = UART1_PHYS_BASE,
399 .membase = (char *)UART1_VIRT_BASE,
400 .irq = IRQ_ORION5X_UART1,
401 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
402 .iotype = UPIO_MEM,
403 .regshift = 2,
404 .uartclk = 0,
405 }, {
406 },
407};
408
409static struct resource orion5x_uart1_resources[] = {
410 {
411 .start = UART1_PHYS_BASE,
412 .end = UART1_PHYS_BASE + 0xff,
413 .flags = IORESOURCE_MEM,
414 }, {
415 .start = IRQ_ORION5X_UART1,
416 .end = IRQ_ORION5X_UART1,
417 .flags = IORESOURCE_IRQ,
418 },
419};
420
421static struct platform_device orion5x_uart1 = {
422 .name = "serial8250",
423 .id = PLAT8250_DEV_PLATFORM1,
424 .dev = {
425 .platform_data = orion5x_uart1_data,
426 },
427 .resource = orion5x_uart1_resources,
428 .num_resources = ARRAY_SIZE(orion5x_uart1_resources),
429};
430
431void __init orion5x_uart1_init(void) 150void __init orion5x_uart1_init(void)
432{ 151{
433 platform_device_register(&orion5x_uart1); 152 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
153 IRQ_ORION5X_UART1, orion5x_tclk);
434} 154}
435 155
436
437/***************************************************************************** 156/*****************************************************************************
438 * XOR engine 157 * XOR engine
439 ****************************************************************************/ 158 ****************************************************************************/
440struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
441 .dram = &orion5x_mbus_dram_info,
442};
443
444static struct resource orion5x_xor_shared_resources[] = {
445 {
446 .name = "xor low",
447 .start = ORION5X_XOR_PHYS_BASE,
448 .end = ORION5X_XOR_PHYS_BASE + 0xff,
449 .flags = IORESOURCE_MEM,
450 }, {
451 .name = "xor high",
452 .start = ORION5X_XOR_PHYS_BASE + 0x200,
453 .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
454 .flags = IORESOURCE_MEM,
455 },
456};
457
458static struct platform_device orion5x_xor_shared = {
459 .name = MV_XOR_SHARED_NAME,
460 .id = 0,
461 .dev = {
462 .platform_data = &orion5x_xor_shared_data,
463 },
464 .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
465 .resource = orion5x_xor_shared_resources,
466};
467
468static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
469
470static struct resource orion5x_xor0_resources[] = {
471 [0] = {
472 .start = IRQ_ORION5X_XOR0,
473 .end = IRQ_ORION5X_XOR0,
474 .flags = IORESOURCE_IRQ,
475 },
476};
477
478static struct mv_xor_platform_data orion5x_xor0_data = {
479 .shared = &orion5x_xor_shared,
480 .hw_id = 0,
481 .pool_size = PAGE_SIZE,
482};
483
484static struct platform_device orion5x_xor0_channel = {
485 .name = MV_XOR_NAME,
486 .id = 0,
487 .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
488 .resource = orion5x_xor0_resources,
489 .dev = {
490 .dma_mask = &orion5x_xor_dmamask,
491 .coherent_dma_mask = DMA_BIT_MASK(64),
492 .platform_data = &orion5x_xor0_data,
493 },
494};
495
496static struct resource orion5x_xor1_resources[] = {
497 [0] = {
498 .start = IRQ_ORION5X_XOR1,
499 .end = IRQ_ORION5X_XOR1,
500 .flags = IORESOURCE_IRQ,
501 },
502};
503
504static struct mv_xor_platform_data orion5x_xor1_data = {
505 .shared = &orion5x_xor_shared,
506 .hw_id = 1,
507 .pool_size = PAGE_SIZE,
508};
509
510static struct platform_device orion5x_xor1_channel = {
511 .name = MV_XOR_NAME,
512 .id = 1,
513 .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
514 .resource = orion5x_xor1_resources,
515 .dev = {
516 .dma_mask = &orion5x_xor_dmamask,
517 .coherent_dma_mask = DMA_BIT_MASK(64),
518 .platform_data = &orion5x_xor1_data,
519 },
520};
521
522void __init orion5x_xor_init(void) 159void __init orion5x_xor_init(void)
523{ 160{
524 platform_device_register(&orion5x_xor_shared); 161 orion_xor0_init(&orion5x_mbus_dram_info,
525 162 ORION5X_XOR_PHYS_BASE,
526 /* 163 ORION5X_XOR_PHYS_BASE + 0x200,
527 * two engines can't do memset simultaneously, this limitation 164 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
528 * satisfied by removing memset support from one of the engines.
529 */
530 dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
531 dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
532 platform_device_register(&orion5x_xor0_channel);
533
534 dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
535 dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
536 dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
537 platform_device_register(&orion5x_xor1_channel);
538} 165}
539 166
540static struct resource orion5x_crypto_res[] = { 167/*****************************************************************************
541 { 168 * Cryptographic Engines and Security Accelerator (CESA)
542 .name = "regs", 169 ****************************************************************************/
543 .start = ORION5X_CRYPTO_PHYS_BASE, 170static void __init orion5x_crypto_init(void)
544 .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
545 .flags = IORESOURCE_MEM,
546 }, {
547 .name = "sram",
548 .start = ORION5X_SRAM_PHYS_BASE,
549 .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
550 .flags = IORESOURCE_MEM,
551 }, {
552 .name = "crypto interrupt",
553 .start = IRQ_ORION5X_CESA,
554 .end = IRQ_ORION5X_CESA,
555 .flags = IORESOURCE_IRQ,
556 },
557};
558
559static struct platform_device orion5x_crypto_device = {
560 .name = "mv_crypto",
561 .id = -1,
562 .num_resources = ARRAY_SIZE(orion5x_crypto_res),
563 .resource = orion5x_crypto_res,
564};
565
566static int __init orion5x_crypto_init(void)
567{ 171{
568 int ret; 172 int ret;
569 173
570 ret = orion5x_setup_sram_win(); 174 ret = orion5x_setup_sram_win();
571 if (ret) 175 if (ret)
572 return ret; 176 return;
573 177
574 return platform_device_register(&orion5x_crypto_device); 178 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
179 SZ_8K, IRQ_ORION5X_CESA);
575} 180}
576 181
577/***************************************************************************** 182/*****************************************************************************
578 * Watchdog 183 * Watchdog
579 ****************************************************************************/ 184 ****************************************************************************/
580static struct orion_wdt_platform_data orion5x_wdt_data = {
581 .tclk = 0,
582};
583
584static struct platform_device orion5x_wdt_device = {
585 .name = "orion_wdt",
586 .id = -1,
587 .dev = {
588 .platform_data = &orion5x_wdt_data,
589 },
590 .num_resources = 0,
591};
592
593void __init orion5x_wdt_init(void) 185void __init orion5x_wdt_init(void)
594{ 186{
595 orion5x_wdt_data.tclk = orion5x_tclk; 187 orion_wdt_init(orion5x_tclk);
596 platform_device_register(&orion5x_wdt_device);
597} 188}
598 189
599 190
@@ -685,11 +276,6 @@ void __init orion5x_init(void)
685 orion5x_id(&dev, &rev, &dev_name); 276 orion5x_id(&dev, &rev, &dev_name);
686 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk); 277 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
687 278
688 orion5x_eth_shared_data.t_clk = orion5x_tclk;
689 orion5x_spi_plat_data.tclk = orion5x_tclk;
690 orion5x_uart0_data[0].uartclk = orion5x_tclk;
691 orion5x_uart1_data[0].uartclk = orion5x_tclk;
692
693 /* 279 /*
694 * Setup Orion address map 280 * Setup Orion address map
695 */ 281 */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 425807579303..19cf5bf99f1b 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -267,28 +267,28 @@ static struct platform_device d2net_gpio_buttons = {
267 * General Setup 267 * General Setup
268 ****************************************************************************/ 268 ****************************************************************************/
269 269
270static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = { 270static unsigned int d2net_mpp_modes[] __initdata = {
271 { 0, MPP_GPIO }, /* Board ID (bit 0) */ 271 MPP0_GPIO, /* Board ID (bit 0) */
272 { 1, MPP_GPIO }, /* Board ID (bit 1) */ 272 MPP1_GPIO, /* Board ID (bit 1) */
273 { 2, MPP_GPIO }, /* Board ID (bit 2) */ 273 MPP2_GPIO, /* Board ID (bit 2) */
274 { 3, MPP_GPIO }, /* SATA 0 power */ 274 MPP3_GPIO, /* SATA 0 power */
275 { 4, MPP_UNUSED }, 275 MPP4_UNUSED,
276 { 5, MPP_GPIO }, /* Fan fail detection */ 276 MPP5_GPIO, /* Fan fail detection */
277 { 6, MPP_GPIO }, /* Red front LED */ 277 MPP6_GPIO, /* Red front LED */
278 { 7, MPP_UNUSED }, 278 MPP7_UNUSED,
279 { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ 279 MPP8_GPIO, /* Rear power switch (on|auto) */
280 { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ 280 MPP9_GPIO, /* Rear power switch (auto|off) */
281 { 10, MPP_UNUSED }, 281 MPP10_UNUSED,
282 { 11, MPP_UNUSED }, 282 MPP11_UNUSED,
283 { 12, MPP_GPIO }, /* SATA 1 power */ 283 MPP12_GPIO, /* SATA 1 power */
284 { 13, MPP_UNUSED }, 284 MPP13_UNUSED,
285 { 14, MPP_SATA_LED }, /* SATA 0 active */ 285 MPP14_SATA_LED, /* SATA 0 active */
286 { 15, MPP_SATA_LED }, /* SATA 1 active */ 286 MPP15_SATA_LED, /* SATA 1 active */
287 { 16, MPP_GPIO }, /* Blue front LED blink control */ 287 MPP16_GPIO, /* Blue front LED blink control */
288 { 17, MPP_UNUSED }, 288 MPP17_UNUSED,
289 { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ 289 MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
290 { 19, MPP_UNUSED }, 290 MPP19_UNUSED,
291 { -1 } 291 0,
292 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ 292 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
293 /* 23: Blue front LED off */ 293 /* 23: Blue front LED off */
294 /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */ 294 /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index b7d4591214e0..f95d3cb01cbf 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -298,28 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
298/***************************************************************************** 298/*****************************************************************************
299 * General Setup 299 * General Setup
300 ****************************************************************************/ 300 ****************************************************************************/
301static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = { 301static unsigned int db88f5281_mpp_modes[] __initdata = {
302 { 0, MPP_GPIO }, /* USB Over Current */ 302 MPP0_GPIO, /* USB Over Current */
303 { 1, MPP_GPIO }, /* USB Vbat input */ 303 MPP1_GPIO, /* USB Vbat input */
304 { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */ 304 MPP2_PCI_ARB, /* PCI_REQn[2] */
305 { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */ 305 MPP3_PCI_ARB, /* PCI_GNTn[2] */
306 { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */ 306 MPP4_PCI_ARB, /* PCI_REQn[3] */
307 { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */ 307 MPP5_PCI_ARB, /* PCI_GNTn[3] */
308 { 6, MPP_GPIO }, /* JP0, CON17.2 */ 308 MPP6_GPIO, /* JP0, CON17.2 */
309 { 7, MPP_GPIO }, /* JP1, CON17.1 */ 309 MPP7_GPIO, /* JP1, CON17.1 */
310 { 8, MPP_GPIO }, /* JP2, CON11.2 */ 310 MPP8_GPIO, /* JP2, CON11.2 */
311 { 9, MPP_GPIO }, /* JP3, CON11.3 */ 311 MPP9_GPIO, /* JP3, CON11.3 */
312 { 10, MPP_GPIO }, /* RTC int */ 312 MPP10_GPIO, /* RTC int */
313 { 11, MPP_GPIO }, /* Baud Rate Generator */ 313 MPP11_GPIO, /* Baud Rate Generator */
314 { 12, MPP_GPIO }, /* PCI int 1 */ 314 MPP12_GPIO, /* PCI int 1 */
315 { 13, MPP_GPIO }, /* PCI int 2 */ 315 MPP13_GPIO, /* PCI int 2 */
316 { 14, MPP_NAND }, /* NAND_REn[2] */ 316 MPP14_NAND, /* NAND_REn[2] */
317 { 15, MPP_NAND }, /* NAND_WEn[2] */ 317 MPP15_NAND, /* NAND_WEn[2] */
318 { 16, MPP_UART }, /* UART1_RX */ 318 MPP16_UART, /* UART1_RX */
319 { 17, MPP_UART }, /* UART1_TX */ 319 MPP17_UART, /* UART1_TX */
320 { 18, MPP_UART }, /* UART1_CTSn */ 320 MPP18_UART, /* UART1_CTSn */
321 { 19, MPP_UART }, /* UART1_RTSn */ 321 MPP19_UART, /* UART1_RTSn */
322 { -1 }, 322 0,
323}; 323};
324 324
325static void __init db88f5281_init(void) 325static void __init db88f5281_init(void)
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 90ab022eabeb..855e0e77d563 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -385,76 +385,76 @@ static struct mv_sata_platform_data dns323_sata_data = {
385/**************************************************************************** 385/****************************************************************************
386 * General Setup 386 * General Setup
387 */ 387 */
388static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = { 388static unsigned int dns323a_mpp_modes[] __initdata = {
389 { 0, MPP_PCIE_RST_OUTn }, 389 MPP0_PCIE_RST_OUTn,
390 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 390 MPP1_GPIO, /* right amber LED (sata ch0) */
391 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 391 MPP2_GPIO, /* left amber LED (sata ch1) */
392 { 3, MPP_UNUSED }, 392 MPP3_UNUSED,
393 { 4, MPP_GPIO }, /* power button LED */ 393 MPP4_GPIO, /* power button LED */
394 { 5, MPP_GPIO }, /* power button LED */ 394 MPP5_GPIO, /* power button LED */
395 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ 395 MPP6_GPIO, /* GMT G751-2f overtemp */
396 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ 396 MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
397 { 8, MPP_GPIO }, /* triggers power off */ 397 MPP8_GPIO, /* triggers power off */
398 { 9, MPP_GPIO }, /* power button switch */ 398 MPP9_GPIO, /* power button switch */
399 { 10, MPP_GPIO }, /* reset button switch */ 399 MPP10_GPIO, /* reset button switch */
400 { 11, MPP_UNUSED }, 400 MPP11_UNUSED,
401 { 12, MPP_UNUSED }, 401 MPP12_UNUSED,
402 { 13, MPP_UNUSED }, 402 MPP13_UNUSED,
403 { 14, MPP_UNUSED }, 403 MPP14_UNUSED,
404 { 15, MPP_UNUSED }, 404 MPP15_UNUSED,
405 { 16, MPP_UNUSED }, 405 MPP16_UNUSED,
406 { 17, MPP_UNUSED }, 406 MPP17_UNUSED,
407 { 18, MPP_UNUSED }, 407 MPP18_UNUSED,
408 { 19, MPP_UNUSED }, 408 MPP19_UNUSED,
409 { -1 }, 409 0,
410}; 410};
411 411
412static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = { 412static unsigned int dns323b_mpp_modes[] __initdata = {
413 { 0, MPP_UNUSED }, 413 MPP0_UNUSED,
414 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */ 414 MPP1_GPIO, /* right amber LED (sata ch0) */
415 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */ 415 MPP2_GPIO, /* left amber LED (sata ch1) */
416 { 3, MPP_GPIO }, /* system up flag */ 416 MPP3_GPIO, /* system up flag */
417 { 4, MPP_GPIO }, /* power button LED */ 417 MPP4_GPIO, /* power button LED */
418 { 5, MPP_GPIO }, /* power button LED */ 418 MPP5_GPIO, /* power button LED */
419 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */ 419 MPP6_GPIO, /* GMT G751-2f overtemp */
420 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */ 420 MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
421 { 8, MPP_GPIO }, /* triggers power off */ 421 MPP8_GPIO, /* triggers power off */
422 { 9, MPP_GPIO }, /* power button switch */ 422 MPP9_GPIO, /* power button switch */
423 { 10, MPP_GPIO }, /* reset button switch */ 423 MPP10_GPIO, /* reset button switch */
424 { 11, MPP_UNUSED }, 424 MPP11_UNUSED,
425 { 12, MPP_SATA_LED }, 425 MPP12_SATA_LED,
426 { 13, MPP_SATA_LED }, 426 MPP13_SATA_LED,
427 { 14, MPP_SATA_LED }, 427 MPP14_SATA_LED,
428 { 15, MPP_SATA_LED }, 428 MPP15_SATA_LED,
429 { 16, MPP_UNUSED }, 429 MPP16_UNUSED,
430 { 17, MPP_UNUSED }, 430 MPP17_UNUSED,
431 { 18, MPP_UNUSED }, 431 MPP18_UNUSED,
432 { 19, MPP_UNUSED }, 432 MPP19_UNUSED,
433 { -1 }, 433 0,
434}; 434};
435 435
436static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = { 436static unsigned int dns323c_mpp_modes[] __initdata = {
437 { 0, MPP_GPIO }, /* ? input */ 437 MPP0_GPIO, /* ? input */
438 { 1, MPP_GPIO }, /* input power switch (0 = pressed) */ 438 MPP1_GPIO, /* input power switch (0 = pressed) */
439 { 2, MPP_GPIO }, /* output power off */ 439 MPP2_GPIO, /* output power off */
440 { 3, MPP_UNUSED }, /* ? output */ 440 MPP3_UNUSED, /* ? output */
441 { 4, MPP_UNUSED }, /* ? output */ 441 MPP4_UNUSED, /* ? output */
442 { 5, MPP_UNUSED }, /* ? output */ 442 MPP5_UNUSED, /* ? output */
443 { 6, MPP_UNUSED }, /* ? output */ 443 MPP6_UNUSED, /* ? output */
444 { 7, MPP_UNUSED }, /* ? output */ 444 MPP7_UNUSED, /* ? output */
445 { 8, MPP_GPIO }, /* i/o right amber LED */ 445 MPP8_GPIO, /* i/o right amber LED */
446 { 9, MPP_GPIO }, /* i/o left amber LED */ 446 MPP9_GPIO, /* i/o left amber LED */
447 { 10, MPP_GPIO }, /* input */ 447 MPP10_GPIO, /* input */
448 { 11, MPP_UNUSED }, 448 MPP11_UNUSED,
449 { 12, MPP_SATA_LED }, 449 MPP12_SATA_LED,
450 { 13, MPP_SATA_LED }, 450 MPP13_SATA_LED,
451 { 14, MPP_SATA_LED }, 451 MPP14_SATA_LED,
452 { 15, MPP_SATA_LED }, 452 MPP15_SATA_LED,
453 { 16, MPP_UNUSED }, 453 MPP16_UNUSED,
454 { 17, MPP_GPIO }, /* power button LED */ 454 MPP17_GPIO, /* power button LED */
455 { 18, MPP_GPIO }, /* fan speed bit 0 */ 455 MPP18_GPIO, /* fan speed bit 0 */
456 { 19, MPP_GPIO }, /* fan speed bit 1 */ 456 MPP19_GPIO, /* fan speed bit 1 */
457 { -1 }, 457 0,
458}; 458};
459 459
460/* Rev C1 Fan speed notes: 460/* Rev C1 Fan speed notes:
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d037a90c216c..b67cff0d4cfe 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -180,31 +180,31 @@ static struct platform_device edmini_v2_gpio_buttons = {
180/***************************************************************************** 180/*****************************************************************************
181 * General Setup 181 * General Setup
182 ****************************************************************************/ 182 ****************************************************************************/
183static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = { 183static unsigned int edminiv2_mpp_modes[] __initdata = {
184 { 0, MPP_UNUSED }, 184 MPP0_UNUSED,
185 { 1, MPP_UNUSED }, 185 MPP1_UNUSED,
186 { 2, MPP_UNUSED }, 186 MPP2_UNUSED,
187 { 3, MPP_GPIO }, /* RTC interrupt */ 187 MPP3_GPIO, /* RTC interrupt */
188 { 4, MPP_UNUSED }, 188 MPP4_UNUSED,
189 { 5, MPP_UNUSED }, 189 MPP5_UNUSED,
190 { 6, MPP_UNUSED }, 190 MPP6_UNUSED,
191 { 7, MPP_UNUSED }, 191 MPP7_UNUSED,
192 { 8, MPP_UNUSED }, 192 MPP8_UNUSED,
193 { 9, MPP_UNUSED }, 193 MPP9_UNUSED,
194 { 10, MPP_UNUSED }, 194 MPP10_UNUSED,
195 { 11, MPP_UNUSED }, 195 MPP11_UNUSED,
196 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 196 MPP12_SATA_LED, /* SATA 0 presence */
197 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 197 MPP13_SATA_LED, /* SATA 1 presence */
198 { 14, MPP_SATA_LED }, /* SATA 0 active */ 198 MPP14_SATA_LED, /* SATA 0 active */
199 { 15, MPP_SATA_LED }, /* SATA 1 active */ 199 MPP15_SATA_LED, /* SATA 1 active */
200 /* 16: Power LED control (0 = On, 1 = Off) */ 200 /* 16: Power LED control (0 = On, 1 = Off) */
201 { 16, MPP_GPIO }, 201 MPP16_GPIO,
202 /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */ 202 /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
203 { 17, MPP_GPIO }, 203 MPP17_GPIO,
204 /* 18: Power button status (0 = Released, 1 = Pressed) */ 204 /* 18: Power button status (0 = Released, 1 = Pressed) */
205 { 18, MPP_GPIO }, 205 MPP18_GPIO,
206 { 19, MPP_UNUSED }, 206 MPP19_UNUSED,
207 { -1 } 207 0,
208}; 208};
209 209
210static void __init edmini_v2_init(void) 210static void __init edmini_v2_init(void)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47497c76162a..c0eb6462633f 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -315,28 +315,28 @@ static void kurobox_pro_power_off(void)
315/***************************************************************************** 315/*****************************************************************************
316 * General Setup 316 * General Setup
317 ****************************************************************************/ 317 ****************************************************************************/
318static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = { 318static unsigned int kurobox_pro_mpp_modes[] __initdata = {
319 { 0, MPP_UNUSED }, 319 MPP0_UNUSED,
320 { 1, MPP_UNUSED }, 320 MPP1_UNUSED,
321 { 2, MPP_GPIO }, /* GPIO Micon */ 321 MPP2_GPIO, /* GPIO Micon */
322 { 3, MPP_GPIO }, /* GPIO Rtc */ 322 MPP3_GPIO, /* GPIO Rtc */
323 { 4, MPP_UNUSED }, 323 MPP4_UNUSED,
324 { 5, MPP_UNUSED }, 324 MPP5_UNUSED,
325 { 6, MPP_NAND }, /* NAND Flash REn */ 325 MPP6_NAND, /* NAND Flash REn */
326 { 7, MPP_NAND }, /* NAND Flash WEn */ 326 MPP7_NAND, /* NAND Flash WEn */
327 { 8, MPP_UNUSED }, 327 MPP8_UNUSED,
328 { 9, MPP_UNUSED }, 328 MPP9_UNUSED,
329 { 10, MPP_UNUSED }, 329 MPP10_UNUSED,
330 { 11, MPP_UNUSED }, 330 MPP11_UNUSED,
331 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 331 MPP12_SATA_LED, /* SATA 0 presence */
332 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 332 MPP13_SATA_LED, /* SATA 1 presence */
333 { 14, MPP_SATA_LED }, /* SATA 0 active */ 333 MPP14_SATA_LED, /* SATA 0 active */
334 { 15, MPP_SATA_LED }, /* SATA 1 active */ 334 MPP15_SATA_LED, /* SATA 1 active */
335 { 16, MPP_UART }, /* UART1 RXD */ 335 MPP16_UART, /* UART1 RXD */
336 { 17, MPP_UART }, /* UART1 TXD */ 336 MPP17_UART, /* UART1 TXD */
337 { 18, MPP_UART }, /* UART1 CTSn */ 337 MPP18_UART, /* UART1 CTSn */
338 { 19, MPP_UART }, /* UART1 RTSn */ 338 MPP19_UART, /* UART1 RTSn */
339 { -1 }, 339 0,
340}; 340};
341 341
342static void __init kurobox_pro_init(void) 342static void __init kurobox_pro_init(void)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6ae12aa6d759..5065803ca82a 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -251,28 +251,28 @@ static struct platform_device lschl_fan_device = {
251 * GPIO Data 251 * GPIO Data
252 ****************************************************************************/ 252 ****************************************************************************/
253 253
254static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = { 254static unsigned int lschl_mpp_modes[] __initdata = {
255 { 0, MPP_GPIO }, /* LED POWER */ 255 MPP0_GPIO, /* LED POWER */
256 { 1, MPP_GPIO }, /* HDD POWER */ 256 MPP1_GPIO, /* HDD POWER */
257 { 2, MPP_GPIO }, /* LED ALARM */ 257 MPP2_GPIO, /* LED ALARM */
258 { 3, MPP_GPIO }, /* LED INFO */ 258 MPP3_GPIO, /* LED INFO */
259 { 4, MPP_UNUSED }, 259 MPP4_UNUSED,
260 { 5, MPP_UNUSED }, 260 MPP5_UNUSED,
261 { 6, MPP_GPIO }, /* FAN LOCK */ 261 MPP6_GPIO, /* FAN LOCK */
262 { 7, MPP_GPIO }, /* SW INIT */ 262 MPP7_GPIO, /* SW INIT */
263 { 8, MPP_GPIO }, /* SW POWER */ 263 MPP8_GPIO, /* SW POWER */
264 { 9, MPP_GPIO }, /* USB POWER */ 264 MPP9_GPIO, /* USB POWER */
265 { 10, MPP_GPIO }, /* SW AUTO POWER */ 265 MPP10_GPIO, /* SW AUTO POWER */
266 { 11, MPP_UNUSED }, 266 MPP11_UNUSED,
267 { 12, MPP_UNUSED }, 267 MPP12_UNUSED,
268 { 13, MPP_UNUSED }, 268 MPP13_UNUSED,
269 { 14, MPP_GPIO }, /* FAN HIGH */ 269 MPP14_GPIO, /* FAN HIGH */
270 { 15, MPP_GPIO }, /* SW FUNC */ 270 MPP15_GPIO, /* SW FUNC */
271 { 16, MPP_GPIO }, /* FAN LOW */ 271 MPP16_GPIO, /* FAN LOW */
272 { 17, MPP_GPIO }, /* LED FUNC */ 272 MPP17_GPIO, /* LED FUNC */
273 { 18, MPP_UNUSED }, 273 MPP18_UNUSED,
274 { 19, MPP_UNUSED }, 274 MPP19_UNUSED,
275 { -1 }, 275 0,
276}; 276};
277 277
278static void __init lschl_init(void) 278static void __init lschl_init(void)
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 7adafd79cf98..8503d0a42d41 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -200,28 +200,28 @@ static void ls_hgl_power_off(void)
200 200
201#define LS_HGL_GPIO_HDD_POWER 1 201#define LS_HGL_GPIO_HDD_POWER 1
202 202
203static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = { 203static unsigned int ls_hgl_mpp_modes[] __initdata = {
204 { 0, MPP_GPIO }, /* LED_PWR */ 204 MPP0_GPIO, /* LED_PWR */
205 { 1, MPP_GPIO }, /* HDD_PWR */ 205 MPP1_GPIO, /* HDD_PWR */
206 { 2, MPP_GPIO }, /* LED_ALARM */ 206 MPP2_GPIO, /* LED_ALARM */
207 { 3, MPP_GPIO }, /* LED_INFO */ 207 MPP3_GPIO, /* LED_INFO */
208 { 4, MPP_UNUSED }, 208 MPP4_UNUSED,
209 { 5, MPP_UNUSED }, 209 MPP5_UNUSED,
210 { 6, MPP_GPIO }, /* FAN_LCK */ 210 MPP6_GPIO, /* FAN_LCK */
211 { 7, MPP_GPIO }, /* INIT */ 211 MPP7_GPIO, /* INIT */
212 { 8, MPP_GPIO }, /* POWER */ 212 MPP8_GPIO, /* POWER */
213 { 9, MPP_GPIO }, /* USB_PWR */ 213 MPP9_GPIO, /* USB_PWR */
214 { 10, MPP_GPIO }, /* AUTO_POWER */ 214 MPP10_GPIO, /* AUTO_POWER */
215 { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ 215 MPP11_UNUSED, /* LED_ETH (dummy) */
216 { 12, MPP_UNUSED }, 216 MPP12_UNUSED,
217 { 13, MPP_UNUSED }, 217 MPP13_UNUSED,
218 { 14, MPP_UNUSED }, 218 MPP14_UNUSED,
219 { 15, MPP_GPIO }, /* FUNC */ 219 MPP15_GPIO, /* FUNC */
220 { 16, MPP_UNUSED }, 220 MPP16_UNUSED,
221 { 17, MPP_GPIO }, /* LED_FUNC */ 221 MPP17_GPIO, /* LED_FUNC */
222 { 18, MPP_UNUSED }, 222 MPP18_UNUSED,
223 { 19, MPP_UNUSED }, 223 MPP19_UNUSED,
224 { -1 }, 224 0,
225}; 225};
226 226
227static void __init ls_hgl_init(void) 227static void __init ls_hgl_init(void)
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 869958f5c394..9c82723c05c0 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -201,28 +201,28 @@ static void lsmini_power_off(void)
201#define LSMINI_GPIO_HDD_POWER0 1 201#define LSMINI_GPIO_HDD_POWER0 1
202#define LSMINI_GPIO_HDD_POWER1 19 202#define LSMINI_GPIO_HDD_POWER1 19
203 203
204static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = { 204static unsigned int lsmini_mpp_modes[] __initdata = {
205 { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */ 205 MPP0_UNUSED, /* LED_RESERVE1 (unused) */
206 { 1, MPP_GPIO }, /* HDD_PWR */ 206 MPP1_GPIO, /* HDD_PWR */
207 { 2, MPP_GPIO }, /* LED_ALARM */ 207 MPP2_GPIO, /* LED_ALARM */
208 { 3, MPP_GPIO }, /* LED_INFO */ 208 MPP3_GPIO, /* LED_INFO */
209 { 4, MPP_UNUSED }, 209 MPP4_UNUSED,
210 { 5, MPP_UNUSED }, 210 MPP5_UNUSED,
211 { 6, MPP_UNUSED }, 211 MPP6_UNUSED,
212 { 7, MPP_UNUSED }, 212 MPP7_UNUSED,
213 { 8, MPP_UNUSED }, 213 MPP8_UNUSED,
214 { 9, MPP_GPIO }, /* LED_FUNC */ 214 MPP9_GPIO, /* LED_FUNC */
215 { 10, MPP_UNUSED }, 215 MPP10_UNUSED,
216 { 11, MPP_UNUSED }, /* LED_ETH (dummy) */ 216 MPP11_UNUSED, /* LED_ETH (dummy) */
217 { 12, MPP_UNUSED }, 217 MPP12_UNUSED,
218 { 13, MPP_UNUSED }, 218 MPP13_UNUSED,
219 { 14, MPP_GPIO }, /* LED_PWR */ 219 MPP14_GPIO, /* LED_PWR */
220 { 15, MPP_GPIO }, /* FUNC */ 220 MPP15_GPIO, /* FUNC */
221 { 16, MPP_GPIO }, /* USB_PWR */ 221 MPP16_GPIO, /* USB_PWR */
222 { 17, MPP_GPIO }, /* AUTO_POWER */ 222 MPP17_GPIO, /* AUTO_POWER */
223 { 18, MPP_GPIO }, /* POWER */ 223 MPP18_GPIO, /* POWER */
224 { 19, MPP_GPIO }, /* HDD_PWR1 */ 224 MPP19_GPIO, /* HDD_PWR1 */
225 { -1 }, 225 0,
226}; 226};
227 227
228static void __init lsmini_init(void) 228static void __init lsmini_init(void)
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 2288207726e4..f12c41b98d46 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,154 +12,34 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mbus.h> 13#include <linux/mbus.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/gpio.h>
16#include <mach/hardware.h> 15#include <mach/hardware.h>
17#include "common.h" 16#include <plat/mpp.h>
18#include "mpp.h" 17#include "mpp.h"
18#include "common.h"
19 19
20static int is_5181l(void) 20static unsigned int __init orion5x_variant(void)
21{
22 u32 dev;
23 u32 rev;
24
25 orion5x_pcie_id(&dev, &rev);
26
27 return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
28}
29
30static int is_5182(void)
31{ 21{
32 u32 dev; 22 u32 dev;
33 u32 rev; 23 u32 rev;
34 24
35 orion5x_pcie_id(&dev, &rev); 25 orion5x_pcie_id(&dev, &rev);
36 26
37 return !!(dev == MV88F5182_DEV_ID); 27 if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
38} 28 return MPP_F5181_MASK;
39 29
40static int is_5281(void) 30 if (dev == MV88F5182_DEV_ID)
41{ 31 return MPP_F5182_MASK;
42 u32 dev;
43 u32 rev;
44 32
45 orion5x_pcie_id(&dev, &rev); 33 if (dev == MV88F5281_DEV_ID)
34 return MPP_F5281_MASK;
46 35
47 return !!(dev == MV88F5281_DEV_ID); 36 printk(KERN_ERR "MPP setup: unknown orion5x variant "
37 "(dev %#x rev %#x)\n", dev, rev);
38 return 0;
48} 39}
49 40
50static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type) 41void __init orion5x_mpp_conf(unsigned int *mpp_list)
51{ 42{
52 switch (type) { 43 orion_mpp_conf(mpp_list, orion5x_variant(),
53 case MPP_UNUSED: 44 MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
54 case MPP_GPIO:
55 if (mpp == 0)
56 return 3;
57 if (mpp >= 1 && mpp <= 15)
58 return 0;
59 if (mpp >= 16 && mpp <= 19) {
60 if (is_5182())
61 return 5;
62 if (type == MPP_UNUSED)
63 return 0;
64 }
65 return -1;
66
67 case MPP_PCIE_RST_OUTn:
68 if (mpp == 0)
69 return 0;
70 return -1;
71
72 case MPP_PCI_ARB:
73 if (mpp >= 0 && mpp <= 7)
74 return 2;
75 return -1;
76
77 case MPP_PCI_PMEn:
78 if (mpp == 2)
79 return 3;
80 return -1;
81
82 case MPP_GIGE:
83 if (mpp >= 8 && mpp <= 19)
84 return 1;
85 return -1;
86
87 case MPP_NAND:
88 if (is_5182() || is_5281()) {
89 if (mpp >= 4 && mpp <= 7)
90 return 4;
91 if (mpp >= 12 && mpp <= 17)
92 return 4;
93 }
94 return -1;
95
96 case MPP_PCI_CLK:
97 if (is_5181l() && mpp >= 6 && mpp <= 7)
98 return 5;
99 return -1;
100
101 case MPP_SATA_LED:
102 if (is_5182()) {
103 if (mpp >= 4 && mpp <= 7)
104 return 5;
105 if (mpp >= 12 && mpp <= 15)
106 return 5;
107 }
108 return -1;
109
110 case MPP_UART:
111 if (mpp >= 16 && mpp <= 19)
112 return 0;
113 return -1;
114 }
115
116 printk(KERN_INFO "unknown MPP type %d\n", type);
117
118 return -1;
119}
120
121void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
122{
123 u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
124 u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
125 u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
126
127 for ( ; mode->mpp >= 0; mode++) {
128 u32 *reg;
129 int num_type;
130 int shift;
131
132 if (mode->mpp >= 0 && mode->mpp <= 7)
133 reg = &mpp_0_7_ctrl;
134 else if (mode->mpp >= 8 && mode->mpp <= 15)
135 reg = &mpp_8_15_ctrl;
136 else if (mode->mpp >= 16 && mode->mpp <= 19)
137 reg = &mpp_16_19_ctrl;
138 else {
139 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
140 "(%d)\n", mode->mpp);
141 continue;
142 }
143
144 num_type = determine_type_encoding(mode->mpp, mode->type);
145 if (num_type < 0) {
146 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
147 "combination (%d, %d)\n", mode->mpp,
148 mode->type);
149 continue;
150 }
151
152 shift = (mode->mpp & 7) << 2;
153 *reg &= ~(0xf << shift);
154 *reg |= (num_type & 0xf) << shift;
155
156 if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
157 orion_gpio_set_unused(mode->mpp);
158
159 orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
160 }
161
162 writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
163 writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
164 writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
165} 45}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610dc012..eac68978a2c2 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
1#ifndef __ARCH_ORION5X_MPP_H 1#ifndef __ARCH_ORION5X_MPP_H
2#define __ARCH_ORION5X_MPP_H 2#define __ARCH_ORION5X_MPP_H
3 3
4enum orion5x_mpp_type { 4#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
5 /* 5 /* MPP number */ ((_num) & 0xff) | \
6 * This MPP is unused. 6 /* MPP select value */ (((_sel) & 0xf) << 8) | \
7 */ 7 /* may be input signal */ ((!!(_in)) << 12) | \
8 MPP_UNUSED, 8 /* may be output signal */ ((!!(_out)) << 13) | \
9 9 /* available on F5181l */ ((!!(_F5181l)) << 14) | \
10 /* 10 /* available on F5182 */ ((!!(_F5182)) << 15) | \
11 * This MPP pin is used as a generic GPIO pin. Valid for 11 /* available on F5281 */ ((!!(_F5281)) << 16))
12 * MPPs 0-15 and device bus data pins 16-31. On 5182, also
13 * valid for MPPs 16-19.
14 */
15 MPP_GPIO,
16
17 /*
18 * This MPP is used as PCIe_RST_OUTn pin. Valid for
19 * MPP 0 only.
20 */
21 MPP_PCIE_RST_OUTn,
22
23 /*
24 * This MPP is used as PCI arbiter pin (REQn/GNTn).
25 * Valid for MPPs 0-7 only.
26 */
27 MPP_PCI_ARB,
28
29 /*
30 * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
31 */
32 MPP_PCI_PMEn,
33
34 /*
35 * This MPP is used as GigE half-duplex (COL, CRS) or GMII
36 * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
37 * MPPs 8-19 only.
38 */
39 MPP_GIGE,
40
41 /*
42 * This MPP is used as NAND REn/WEn pin. Valid for MPPs
43 * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
44 */
45 MPP_NAND,
46
47 /*
48 * This MPP is used as a PCI clock output pin. Valid for
49 * MPPs 6-7 only, and only on the 5181l.
50 */
51 MPP_PCI_CLK,
52
53 /*
54 * This MPP is used as a SATA presence/activity LED.
55 * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
56 */
57 MPP_SATA_LED,
58
59 /*
60 * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
61 * Valid for MPPs 16-19 only.
62 */
63 MPP_UART,
64};
65
66struct orion5x_mpp_mode {
67 int mpp;
68 enum orion5x_mpp_type type;
69};
70
71void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
72 12
13 /* num sel i o 5181 5182 5281 */
14
15#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
16#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
17#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
18
19#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
20#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
21#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
22#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
23
24#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
25#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
26#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
27
28#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
29#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
30#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
31#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
32
33#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
34#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
35#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
36
37#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
38#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
39#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
40#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
41#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
42
43#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
44#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
45#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
46#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
47#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
48
49#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
50#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
51#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
52#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
53#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
54#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
55
56#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
57#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
58#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
59#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
60#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
61#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
62
63#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
64#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
65#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
66
67#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
68#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
69#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
70
71#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
72#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
73#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
74
75#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
76#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
77#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
78
79#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
80#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
81#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
82#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
83#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
84
85#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
86#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
87#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
88#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
89#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
90
91#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
92#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
93#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
94#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
95#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
96
97#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
98#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
99#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
100#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
101#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
102
103#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
104#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
105#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
106#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
107#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
108
109#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
110#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
111#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
112#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
113#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
114
115#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
116#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
117#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
118#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
119
120#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
121#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
122#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
123#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
124
125#define MPP_MAX 19
126
127void orion5x_mpp_conf(unsigned int *mpp_list);
73 128
74#endif 129#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index b43b208153cb..59263b73d1e4 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -193,28 +193,28 @@ static void mss2_power_off(void)
193/**************************************************************************** 193/****************************************************************************
194 * General Setup 194 * General Setup
195 ****************************************************************************/ 195 ****************************************************************************/
196static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = { 196static unsigned int mss2_mpp_modes[] __initdata = {
197 { 0, MPP_GPIO }, /* Power LED */ 197 MPP0_GPIO, /* Power LED */
198 { 1, MPP_GPIO }, /* Error LED */ 198 MPP1_GPIO, /* Error LED */
199 { 2, MPP_UNUSED }, 199 MPP2_UNUSED,
200 { 3, MPP_GPIO }, /* RTC interrupt */ 200 MPP3_GPIO, /* RTC interrupt */
201 { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/ 201 MPP4_GPIO, /* HDD ind. (Single/Dual)*/
202 { 5, MPP_GPIO }, /* HD0 5V control */ 202 MPP5_GPIO, /* HD0 5V control */
203 { 6, MPP_GPIO }, /* HD0 12V control */ 203 MPP6_GPIO, /* HD0 12V control */
204 { 7, MPP_GPIO }, /* HD1 5V control */ 204 MPP7_GPIO, /* HD1 5V control */
205 { 8, MPP_GPIO }, /* HD1 12V control */ 205 MPP8_GPIO, /* HD1 12V control */
206 { 9, MPP_UNUSED }, 206 MPP9_UNUSED,
207 { 10, MPP_GPIO }, /* Fan control */ 207 MPP10_GPIO, /* Fan control */
208 { 11, MPP_GPIO }, /* Power button */ 208 MPP11_GPIO, /* Power button */
209 { 12, MPP_GPIO }, /* Reset button */ 209 MPP12_GPIO, /* Reset button */
210 { 13, MPP_UNUSED }, 210 MPP13_UNUSED,
211 { 14, MPP_SATA_LED }, /* SATA 0 active */ 211 MPP14_SATA_LED, /* SATA 0 active */
212 { 15, MPP_SATA_LED }, /* SATA 1 active */ 212 MPP15_SATA_LED, /* SATA 1 active */
213 { 16, MPP_UNUSED }, 213 MPP16_UNUSED,
214 { 17, MPP_UNUSED }, 214 MPP17_UNUSED,
215 { 18, MPP_UNUSED }, 215 MPP18_UNUSED,
216 { 19, MPP_UNUSED }, 216 MPP19_UNUSED,
217 { -1 }, 217 0,
218}; 218};
219 219
220static void __init mss2_init(void) 220static void __init mss2_init(void)
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c55d071707f5..63ff10c3c464 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -108,28 +108,28 @@ static struct platform_device mv2120_button_device = {
108/**************************************************************************** 108/****************************************************************************
109 * General Setup 109 * General Setup
110 ****************************************************************************/ 110 ****************************************************************************/
111static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = { 111static unsigned int mv2120_mpp_modes[] __initdata = {
112 { 0, MPP_GPIO }, /* Sys status LED */ 112 MPP0_GPIO, /* Sys status LED */
113 { 1, MPP_GPIO }, /* Sys error LED */ 113 MPP1_GPIO, /* Sys error LED */
114 { 2, MPP_GPIO }, /* OverTemp interrupt */ 114 MPP2_GPIO, /* OverTemp interrupt */
115 { 3, MPP_GPIO }, /* RTC interrupt */ 115 MPP3_GPIO, /* RTC interrupt */
116 { 4, MPP_GPIO }, /* V_LED 5V */ 116 MPP4_GPIO, /* V_LED 5V */
117 { 5, MPP_GPIO }, /* V_LED 3.3V */ 117 MPP5_GPIO, /* V_LED 3.3V */
118 { 6, MPP_UNUSED }, 118 MPP6_UNUSED,
119 { 7, MPP_UNUSED }, 119 MPP7_UNUSED,
120 { 8, MPP_GPIO }, /* SATA 0 fail LED */ 120 MPP8_GPIO, /* SATA 0 fail LED */
121 { 9, MPP_GPIO }, /* SATA 1 fail LED */ 121 MPP9_GPIO, /* SATA 1 fail LED */
122 { 10, MPP_UNUSED }, 122 MPP10_UNUSED,
123 { 11, MPP_UNUSED }, 123 MPP11_UNUSED,
124 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 124 MPP12_SATA_LED, /* SATA 0 presence */
125 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 125 MPP13_SATA_LED, /* SATA 1 presence */
126 { 14, MPP_SATA_LED }, /* SATA 0 active */ 126 MPP14_SATA_LED, /* SATA 0 active */
127 { 15, MPP_SATA_LED }, /* SATA 1 active */ 127 MPP15_SATA_LED, /* SATA 1 active */
128 { 16, MPP_UNUSED }, 128 MPP16_UNUSED,
129 { 17, MPP_GPIO }, /* Reset button */ 129 MPP17_GPIO, /* Reset button */
130 { 18, MPP_GPIO }, /* Power button */ 130 MPP18_GPIO, /* Power button */
131 { 19, MPP_GPIO }, /* Power off */ 131 MPP19_GPIO, /* Power off */
132 { -1 }, 132 0,
133}; 133};
134 134
135static struct i2c_board_info __initdata mv2120_i2c_rtc = { 135static struct i2c_board_info __initdata mv2120_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index a5930f83958b..e43b39cc7fe9 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -339,28 +339,28 @@ static struct platform_device net2big_gpio_buttons = {
339 * General Setup 339 * General Setup
340 ****************************************************************************/ 340 ****************************************************************************/
341 341
342static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = { 342static unsigned int net2big_mpp_modes[] __initdata = {
343 { 0, MPP_GPIO }, /* Raid mode (bit 0) */ 343 MPP0_GPIO, /* Raid mode (bit 0) */
344 { 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */ 344 MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
345 { 2, MPP_GPIO }, /* Raid mode (bit 1) */ 345 MPP2_GPIO, /* Raid mode (bit 1) */
346 { 3, MPP_GPIO }, /* Board ID (bit 0) */ 346 MPP3_GPIO, /* Board ID (bit 0) */
347 { 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */ 347 MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
348 { 5, MPP_GPIO }, /* Fan fail detection */ 348 MPP5_GPIO, /* Fan fail detection */
349 { 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */ 349 MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
350 { 7, MPP_GPIO }, /* Disable initial blinking on front LED */ 350 MPP7_GPIO, /* Disable initial blinking on front LED */
351 { 8, MPP_GPIO }, /* Rear power switch (on|auto) */ 351 MPP8_GPIO, /* Rear power switch (on|auto) */
352 { 9, MPP_GPIO }, /* Rear power switch (auto|off) */ 352 MPP9_GPIO, /* Rear power switch (auto|off) */
353 { 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */ 353 MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
354 { 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */ 354 MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
355 { 12, MPP_GPIO }, /* Board ID (bit 1) */ 355 MPP12_GPIO, /* Board ID (bit 1) */
356 { 13, MPP_GPIO }, /* SATA 1 blue LED blink control */ 356 MPP13_GPIO, /* SATA 1 blue LED blink control */
357 { 14, MPP_SATA_LED }, 357 MPP14_SATA_LED,
358 { 15, MPP_SATA_LED }, 358 MPP15_SATA_LED,
359 { 16, MPP_GPIO }, /* Blue front LED control */ 359 MPP16_GPIO, /* Blue front LED control */
360 { 17, MPP_GPIO }, /* SATA 0 blue LED blink control */ 360 MPP17_GPIO, /* SATA 0 blue LED blink control */
361 { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */ 361 MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
362 { 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */ 362 MPP19_GPIO, /* SATA{0,1} power On/Off request */
363 { -1 } 363 0,
364 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */ 364 /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
365 /* 23: SATA 0 power status */ 365 /* 23: SATA 0 power status */
366 /* 24: Board power off */ 366 /* 24: Board power off */
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 34310ab56e29..9eec7c2375e9 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -64,28 +64,28 @@ static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
64/***************************************************************************** 64/*****************************************************************************
65 * General Setup 65 * General Setup
66 ****************************************************************************/ 66 ****************************************************************************/
67static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { 67static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
68 { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */ 68 MPP0_GPIO, /* LED1 CardBus LED (front panel) */
69 { 1, MPP_GPIO }, /* PCI_intA */ 69 MPP1_GPIO, /* PCI_intA */
70 { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/ 70 MPP2_GPIO, /* Hard Reset / Factory Init*/
71 { 3, MPP_GPIO }, /* FXS or DAA select */ 71 MPP3_GPIO, /* FXS or DAA select */
72 { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */ 72 MPP4_GPIO, /* LED6 - phone LED (front panel) */
73 { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */ 73 MPP5_GPIO, /* LED5 - phone LED (front panel) */
74 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ 74 MPP6_PCI_CLK, /* CPU PCI refclk */
75 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ 75 MPP7_PCI_CLK, /* PCI/PCIe refclk */
76 { 8, MPP_GPIO }, /* CardBus reset */ 76 MPP8_GPIO, /* CardBus reset */
77 { 9, MPP_GPIO }, /* GE_RXERR */ 77 MPP9_GPIO, /* GE_RXERR */
78 { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */ 78 MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */
79 { 11, MPP_GPIO }, /* Lifeline control */ 79 MPP11_GPIO, /* Lifeline control */
80 { 12, MPP_GIGE }, /* GE_TXD[4] */ 80 MPP12_GIGE, /* GE_TXD[4] */
81 { 13, MPP_GIGE }, /* GE_TXD[5] */ 81 MPP13_GIGE, /* GE_TXD[5] */
82 { 14, MPP_GIGE }, /* GE_TXD[6] */ 82 MPP14_GIGE, /* GE_TXD[6] */
83 { 15, MPP_GIGE }, /* GE_TXD[7] */ 83 MPP15_GIGE, /* GE_TXD[7] */
84 { 16, MPP_GIGE }, /* GE_RXD[4] */ 84 MPP16_GIGE, /* GE_RXD[4] */
85 { 17, MPP_GIGE }, /* GE_RXD[5] */ 85 MPP17_GIGE, /* GE_RXD[5] */
86 { 18, MPP_GIGE }, /* GE_RXD[6] */ 86 MPP18_GIGE, /* GE_RXD[6] */
87 { 19, MPP_GIGE }, /* GE_RXD[7] */ 87 MPP19_GIGE, /* GE_RXD[7] */
88 { -1 }, 88 0,
89}; 89};
90 90
91static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { 91static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c1f79fa014ed..0cc90bbfd326 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -65,28 +65,28 @@ static struct platform_device rd88f5181l_ge_nor_boot_flash = {
65/***************************************************************************** 65/*****************************************************************************
66 * General Setup 66 * General Setup
67 ****************************************************************************/ 67 ****************************************************************************/
68static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = { 68static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
69 { 0, MPP_GPIO }, /* LED1 */ 69 MPP0_GPIO, /* LED1 */
70 { 1, MPP_GPIO }, /* LED5 */ 70 MPP1_GPIO, /* LED5 */
71 { 2, MPP_GPIO }, /* LED4 */ 71 MPP2_GPIO, /* LED4 */
72 { 3, MPP_GPIO }, /* LED3 */ 72 MPP3_GPIO, /* LED3 */
73 { 4, MPP_GPIO }, /* PCI_intA */ 73 MPP4_GPIO, /* PCI_intA */
74 { 5, MPP_GPIO }, /* RTC interrupt */ 74 MPP5_GPIO, /* RTC interrupt */
75 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ 75 MPP6_PCI_CLK, /* CPU PCI refclk */
76 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ 76 MPP7_PCI_CLK, /* PCI/PCIe refclk */
77 { 8, MPP_GPIO }, /* 88e6131 interrupt */ 77 MPP8_GPIO, /* 88e6131 interrupt */
78 { 9, MPP_GPIO }, /* GE_RXERR */ 78 MPP9_GPIO, /* GE_RXERR */
79 { 10, MPP_GPIO }, /* PCI_intB */ 79 MPP10_GPIO, /* PCI_intB */
80 { 11, MPP_GPIO }, /* LED2 */ 80 MPP11_GPIO, /* LED2 */
81 { 12, MPP_GIGE }, /* GE_TXD[4] */ 81 MPP12_GIGE, /* GE_TXD[4] */
82 { 13, MPP_GIGE }, /* GE_TXD[5] */ 82 MPP13_GIGE, /* GE_TXD[5] */
83 { 14, MPP_GIGE }, /* GE_TXD[6] */ 83 MPP14_GIGE, /* GE_TXD[6] */
84 { 15, MPP_GIGE }, /* GE_TXD[7] */ 84 MPP15_GIGE, /* GE_TXD[7] */
85 { 16, MPP_GIGE }, /* GE_RXD[4] */ 85 MPP16_GIGE, /* GE_RXD[4] */
86 { 17, MPP_GIGE }, /* GE_RXD[5] */ 86 MPP17_GIGE, /* GE_RXD[5] */
87 { 18, MPP_GIGE }, /* GE_RXD[6] */ 87 MPP18_GIGE, /* GE_RXD[6] */
88 { 19, MPP_GIGE }, /* GE_RXD[7] */ 88 MPP19_GIGE, /* GE_RXD[7] */
89 { -1 }, 89 0,
90}; 90};
91 91
92static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = { 92static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4fc46772a087..48da39b9bdb0 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -241,28 +241,28 @@ static struct mv_sata_platform_data rd88f5182_sata_data = {
241/***************************************************************************** 241/*****************************************************************************
242 * General Setup 242 * General Setup
243 ****************************************************************************/ 243 ****************************************************************************/
244static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = { 244static unsigned int rd88f5182_mpp_modes[] __initdata = {
245 { 0, MPP_GPIO }, /* Debug Led */ 245 MPP0_GPIO, /* Debug Led */
246 { 1, MPP_GPIO }, /* Reset Switch */ 246 MPP1_GPIO, /* Reset Switch */
247 { 2, MPP_UNUSED }, 247 MPP2_UNUSED,
248 { 3, MPP_GPIO }, /* RTC Int */ 248 MPP3_GPIO, /* RTC Int */
249 { 4, MPP_GPIO }, 249 MPP4_GPIO,
250 { 5, MPP_GPIO }, 250 MPP5_GPIO,
251 { 6, MPP_GPIO }, /* PCI_intA */ 251 MPP6_GPIO, /* PCI_intA */
252 { 7, MPP_GPIO }, /* PCI_intB */ 252 MPP7_GPIO, /* PCI_intB */
253 { 8, MPP_UNUSED }, 253 MPP8_UNUSED,
254 { 9, MPP_UNUSED }, 254 MPP9_UNUSED,
255 { 10, MPP_UNUSED }, 255 MPP10_UNUSED,
256 { 11, MPP_UNUSED }, 256 MPP11_UNUSED,
257 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 257 MPP12_SATA_LED, /* SATA 0 presence */
258 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 258 MPP13_SATA_LED, /* SATA 1 presence */
259 { 14, MPP_SATA_LED }, /* SATA 0 active */ 259 MPP14_SATA_LED, /* SATA 0 active */
260 { 15, MPP_SATA_LED }, /* SATA 1 active */ 260 MPP15_SATA_LED, /* SATA 1 active */
261 { 16, MPP_UNUSED }, 261 MPP16_UNUSED,
262 { 17, MPP_UNUSED }, 262 MPP17_UNUSED,
263 { 18, MPP_UNUSED }, 263 MPP18_UNUSED,
264 { 19, MPP_UNUSED }, 264 MPP19_UNUSED,
265 { -1 }, 265 0,
266}; 266};
267 267
268static void __init rd88f5182_init(void) 268static void __init rd88f5182_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index b080c6966d10..ad2eba9286ad 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -27,7 +27,6 @@
27#include <asm/mach/pci.h> 27#include <asm/mach/pci.h>
28#include <mach/orion5x.h> 28#include <mach/orion5x.h>
29#include "common.h" 29#include "common.h"
30#include "mpp.h"
31 30
32static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = { 31static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
33 .phy_addr = -1, 32 .phy_addr = -1,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 616004143912..29ce826c3c21 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -295,28 +295,28 @@ static void tsp2_power_off(void)
295/***************************************************************************** 295/*****************************************************************************
296 * General Setup 296 * General Setup
297 ****************************************************************************/ 297 ****************************************************************************/
298static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = { 298static unsigned int tsp2_mpp_modes[] __initdata = {
299 { 0, MPP_PCIE_RST_OUTn }, 299 MPP0_PCIE_RST_OUTn,
300 { 1, MPP_UNUSED }, 300 MPP1_UNUSED,
301 { 2, MPP_UNUSED }, 301 MPP2_UNUSED,
302 { 3, MPP_UNUSED }, 302 MPP3_UNUSED,
303 { 4, MPP_NAND }, /* BOOT NAND Flash REn */ 303 MPP4_NAND, /* BOOT NAND Flash REn */
304 { 5, MPP_NAND }, /* BOOT NAND Flash WEn */ 304 MPP5_NAND, /* BOOT NAND Flash WEn */
305 { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */ 305 MPP6_NAND, /* BOOT NAND Flash HREn[0] */
306 { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */ 306 MPP7_NAND, /* BOOT NAND Flash WEn[0] */
307 { 8, MPP_GPIO }, /* MICON int */ 307 MPP8_GPIO, /* MICON int */
308 { 9, MPP_GPIO }, /* RTC int */ 308 MPP9_GPIO, /* RTC int */
309 { 10, MPP_UNUSED }, 309 MPP10_UNUSED,
310 { 11, MPP_GPIO }, /* PCI Int A */ 310 MPP11_GPIO, /* PCI Int A */
311 { 12, MPP_UNUSED }, 311 MPP12_UNUSED,
312 { 13, MPP_GPIO }, /* UPS on UART0 enable */ 312 MPP13_GPIO, /* UPS on UART0 enable */
313 { 14, MPP_GPIO }, /* UPS low battery detection */ 313 MPP14_GPIO, /* UPS low battery detection */
314 { 15, MPP_UNUSED }, 314 MPP15_UNUSED,
315 { 16, MPP_UART }, /* UART1 RXD */ 315 MPP16_UART, /* UART1 RXD */
316 { 17, MPP_UART }, /* UART1 TXD */ 316 MPP17_UART, /* UART1 TXD */
317 { 18, MPP_UART }, /* UART1 CTSn */ 317 MPP18_UART, /* UART1 CTSn */
318 { 19, MPP_UART }, /* UART1 RTSn */ 318 MPP19_UART, /* UART1 RTSn */
319 { -1 }, 319 0,
320}; 320};
321 321
322static void __init tsp2_init(void) 322static void __init tsp2_init(void)
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e6d64494d3de..47162fd5f044 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -244,28 +244,28 @@ static struct mv_sata_platform_data qnap_ts209_sata_data = {
244 244
245 * General Setup 245 * General Setup
246 ****************************************************************************/ 246 ****************************************************************************/
247static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = { 247static unsigned int ts209_mpp_modes[] __initdata = {
248 { 0, MPP_UNUSED }, 248 MPP0_UNUSED,
249 { 1, MPP_GPIO }, /* USB copy button */ 249 MPP1_GPIO, /* USB copy button */
250 { 2, MPP_GPIO }, /* Load defaults button */ 250 MPP2_GPIO, /* Load defaults button */
251 { 3, MPP_GPIO }, /* GPIO RTC */ 251 MPP3_GPIO, /* GPIO RTC */
252 { 4, MPP_UNUSED }, 252 MPP4_UNUSED,
253 { 5, MPP_UNUSED }, 253 MPP5_UNUSED,
254 { 6, MPP_GPIO }, /* PCI Int A */ 254 MPP6_GPIO, /* PCI Int A */
255 { 7, MPP_GPIO }, /* PCI Int B */ 255 MPP7_GPIO, /* PCI Int B */
256 { 8, MPP_UNUSED }, 256 MPP8_UNUSED,
257 { 9, MPP_UNUSED }, 257 MPP9_UNUSED,
258 { 10, MPP_UNUSED }, 258 MPP10_UNUSED,
259 { 11, MPP_UNUSED }, 259 MPP11_UNUSED,
260 { 12, MPP_SATA_LED }, /* SATA 0 presence */ 260 MPP12_SATA_LED, /* SATA 0 presence */
261 { 13, MPP_SATA_LED }, /* SATA 1 presence */ 261 MPP13_SATA_LED, /* SATA 1 presence */
262 { 14, MPP_SATA_LED }, /* SATA 0 active */ 262 MPP14_SATA_LED, /* SATA 0 active */
263 { 15, MPP_SATA_LED }, /* SATA 1 active */ 263 MPP15_SATA_LED, /* SATA 1 active */
264 { 16, MPP_UART }, /* UART1 RXD */ 264 MPP16_UART, /* UART1 RXD */
265 { 17, MPP_UART }, /* UART1 TXD */ 265 MPP17_UART, /* UART1 TXD */
266 { 18, MPP_GPIO }, /* SW_RST */ 266 MPP18_GPIO, /* SW_RST */
267 { 19, MPP_UNUSED }, 267 MPP19_UNUSED,
268 { -1 }, 268 0,
269}; 269};
270 270
271static void __init qnap_ts209_init(void) 271static void __init qnap_ts209_init(void)
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9eac8192d923..5aacc7ac5cf4 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -242,28 +242,28 @@ static struct platform_device qnap_ts409_button_device = {
242/***************************************************************************** 242/*****************************************************************************
243 * General Setup 243 * General Setup
244 ****************************************************************************/ 244 ****************************************************************************/
245static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = { 245static unsigned int ts409_mpp_modes[] __initdata = {
246 { 0, MPP_UNUSED }, 246 MPP0_UNUSED,
247 { 1, MPP_UNUSED }, 247 MPP1_UNUSED,
248 { 2, MPP_UNUSED }, 248 MPP2_UNUSED,
249 { 3, MPP_UNUSED }, 249 MPP3_UNUSED,
250 { 4, MPP_GPIO }, /* HDD 1 status */ 250 MPP4_GPIO, /* HDD 1 status */
251 { 5, MPP_GPIO }, /* HDD 2 status */ 251 MPP5_GPIO, /* HDD 2 status */
252 { 6, MPP_GPIO }, /* HDD 3 status */ 252 MPP6_GPIO, /* HDD 3 status */
253 { 7, MPP_GPIO }, /* HDD 4 status */ 253 MPP7_GPIO, /* HDD 4 status */
254 { 8, MPP_UNUSED }, 254 MPP8_UNUSED,
255 { 9, MPP_UNUSED }, 255 MPP9_UNUSED,
256 { 10, MPP_GPIO }, /* RTC int */ 256 MPP10_GPIO, /* RTC int */
257 { 11, MPP_UNUSED }, 257 MPP11_UNUSED,
258 { 12, MPP_UNUSED }, 258 MPP12_UNUSED,
259 { 13, MPP_UNUSED }, 259 MPP13_UNUSED,
260 { 14, MPP_GPIO }, /* SW_RST */ 260 MPP14_GPIO, /* SW_RST */
261 { 15, MPP_GPIO }, /* USB copy button */ 261 MPP15_GPIO, /* USB copy button */
262 { 16, MPP_UART }, /* UART1 RXD */ 262 MPP16_UART, /* UART1 RXD */
263 { 17, MPP_UART }, /* UART1 TXD */ 263 MPP17_UART, /* UART1 TXD */
264 { 18, MPP_UNUSED }, 264 MPP18_UNUSED,
265 { 19, MPP_UNUSED }, 265 MPP19_UNUSED,
266 { -1 }, 266 0,
267}; 267};
268 268
269static void __init qnap_ts409_init(void) 269static void __init qnap_ts409_init(void)
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index edb1dd2d1611..6b7b54116f30 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -557,27 +557,27 @@ static struct kobj_attribute ts78xx_fpga_attr =
557/***************************************************************************** 557/*****************************************************************************
558 * General Setup 558 * General Setup
559 ****************************************************************************/ 559 ****************************************************************************/
560static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { 560static unsigned int ts78xx_mpp_modes[] __initdata = {
561 { 0, MPP_UNUSED }, 561 MPP0_UNUSED,
562 { 1, MPP_GPIO }, /* JTAG Clock */ 562 MPP1_GPIO, /* JTAG Clock */
563 { 2, MPP_GPIO }, /* JTAG Data In */ 563 MPP2_GPIO, /* JTAG Data In */
564 { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */ 564 MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
565 { 4, MPP_GPIO }, /* JTAG Data Out */ 565 MPP4_GPIO, /* JTAG Data Out */
566 { 5, MPP_GPIO }, /* JTAG TMS */ 566 MPP5_GPIO, /* JTAG TMS */
567 { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */ 567 MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
568 { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */ 568 MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
569 { 8, MPP_UNUSED }, 569 MPP8_UNUSED,
570 { 9, MPP_UNUSED }, 570 MPP9_UNUSED,
571 { 10, MPP_UNUSED }, 571 MPP10_UNUSED,
572 { 11, MPP_UNUSED }, 572 MPP11_UNUSED,
573 { 12, MPP_UNUSED }, 573 MPP12_UNUSED,
574 { 13, MPP_UNUSED }, 574 MPP13_UNUSED,
575 { 14, MPP_UNUSED }, 575 MPP14_UNUSED,
576 { 15, MPP_UNUSED }, 576 MPP15_UNUSED,
577 { 16, MPP_UART }, 577 MPP16_UART,
578 { 17, MPP_UART }, 578 MPP17_UART,
579 { 18, MPP_UART }, 579 MPP18_UART,
580 { 19, MPP_UART }, 580 MPP19_UART,
581 /* 581 /*
582 * MPP[20] PCI Clock Out 1 582 * MPP[20] PCI Clock Out 1
583 * MPP[21] PCI Clock Out 0 583 * MPP[21] PCI Clock Out 0
@@ -586,7 +586,7 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
586 * MPP[24] Unused 586 * MPP[24] Unused
587 * MPP[25] Unused 587 * MPP[25] Unused
588 */ 588 */
589 { -1 }, 589 0,
590}; 590};
591 591
592static void __init ts78xx_init(void) 592static void __init ts78xx_init(void)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 4e5216be0745..444a1c7fdfd6 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -24,28 +24,28 @@
24#include "common.h" 24#include "common.h"
25#include "mpp.h" 25#include "mpp.h"
26 26
27static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = { 27static unsigned int wnr854t_mpp_modes[] __initdata = {
28 { 0, MPP_GPIO }, /* Power LED green (0=on) */ 28 MPP0_GPIO, /* Power LED green (0=on) */
29 { 1, MPP_GPIO }, /* Reset Button (0=off) */ 29 MPP1_GPIO, /* Reset Button (0=off) */
30 { 2, MPP_GPIO }, /* Power LED blink (0=off) */ 30 MPP2_GPIO, /* Power LED blink (0=off) */
31 { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */ 31 MPP3_GPIO, /* WAN Status LED amber (0=off) */
32 { 4, MPP_GPIO }, /* PCI int */ 32 MPP4_GPIO, /* PCI int */
33 { 5, MPP_GPIO }, /* ??? */ 33 MPP5_GPIO, /* ??? */
34 { 6, MPP_GPIO }, /* ??? */ 34 MPP6_GPIO, /* ??? */
35 { 7, MPP_GPIO }, /* ??? */ 35 MPP7_GPIO, /* ??? */
36 { 8, MPP_UNUSED }, /* ??? */ 36 MPP8_UNUSED, /* ??? */
37 { 9, MPP_GIGE }, /* GE_RXERR */ 37 MPP9_GIGE, /* GE_RXERR */
38 { 10, MPP_UNUSED }, /* ??? */ 38 MPP10_UNUSED, /* ??? */
39 { 11, MPP_UNUSED }, /* ??? */ 39 MPP11_UNUSED, /* ??? */
40 { 12, MPP_GIGE }, /* GE_TXD[4] */ 40 MPP12_GIGE, /* GE_TXD[4] */
41 { 13, MPP_GIGE }, /* GE_TXD[5] */ 41 MPP13_GIGE, /* GE_TXD[5] */
42 { 14, MPP_GIGE }, /* GE_TXD[6] */ 42 MPP14_GIGE, /* GE_TXD[6] */
43 { 15, MPP_GIGE }, /* GE_TXD[7] */ 43 MPP15_GIGE, /* GE_TXD[7] */
44 { 16, MPP_GIGE }, /* GE_RXD[4] */ 44 MPP16_GIGE, /* GE_RXD[4] */
45 { 17, MPP_GIGE }, /* GE_RXD[5] */ 45 MPP17_GIGE, /* GE_RXD[5] */
46 { 18, MPP_GIGE }, /* GE_RXD[6] */ 46 MPP18_GIGE, /* GE_RXD[6] */
47 { 19, MPP_GIGE }, /* GE_RXD[7] */ 47 MPP19_GIGE, /* GE_RXD[7] */
48 { -1 }, 48 0,
49}; 49};
50 50
51/* 51/*
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fab79d09cc5c..d1952be0ae1c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -101,28 +101,28 @@ static struct platform_device wrt350n_v2_button_device = {
101/* 101/*
102 * General setup 102 * General setup
103 */ 103 */
104static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = { 104static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
105 { 0, MPP_GPIO }, /* Power LED green (0=on) */ 105 MPP0_GPIO, /* Power LED green (0=on) */
106 { 1, MPP_GPIO }, /* Security LED (0=on) */ 106 MPP1_GPIO, /* Security LED (0=on) */
107 { 2, MPP_GPIO }, /* Internal Button (0=on) */ 107 MPP2_GPIO, /* Internal Button (0=on) */
108 { 3, MPP_GPIO }, /* Reset Button (0=on) */ 108 MPP3_GPIO, /* Reset Button (0=on) */
109 { 4, MPP_GPIO }, /* PCI int */ 109 MPP4_GPIO, /* PCI int */
110 { 5, MPP_GPIO }, /* Power LED orange (0=on) */ 110 MPP5_GPIO, /* Power LED orange (0=on) */
111 { 6, MPP_GPIO }, /* USB LED (0=on) */ 111 MPP6_GPIO, /* USB LED (0=on) */
112 { 7, MPP_GPIO }, /* Wireless LED (0=on) */ 112 MPP7_GPIO, /* Wireless LED (0=on) */
113 { 8, MPP_UNUSED }, /* ??? */ 113 MPP8_UNUSED, /* ??? */
114 { 9, MPP_GIGE }, /* GE_RXERR */ 114 MPP9_GIGE, /* GE_RXERR */
115 { 10, MPP_UNUSED }, /* ??? */ 115 MPP10_UNUSED, /* ??? */
116 { 11, MPP_UNUSED }, /* ??? */ 116 MPP11_UNUSED, /* ??? */
117 { 12, MPP_GIGE }, /* GE_TXD[4] */ 117 MPP12_GIGE, /* GE_TXD[4] */
118 { 13, MPP_GIGE }, /* GE_TXD[5] */ 118 MPP13_GIGE, /* GE_TXD[5] */
119 { 14, MPP_GIGE }, /* GE_TXD[6] */ 119 MPP14_GIGE, /* GE_TXD[6] */
120 { 15, MPP_GIGE }, /* GE_TXD[7] */ 120 MPP15_GIGE, /* GE_TXD[7] */
121 { 16, MPP_GIGE }, /* GE_RXD[4] */ 121 MPP16_GIGE, /* GE_RXD[4] */
122 { 17, MPP_GIGE }, /* GE_RXD[5] */ 122 MPP17_GIGE, /* GE_RXD[5] */
123 { 18, MPP_GIGE }, /* GE_RXD[6] */ 123 MPP18_GIGE, /* GE_RXD[6] */
124 { 19, MPP_GIGE }, /* GE_RXD[7] */ 124 MPP19_GIGE, /* GE_RXD[7] */
125 { -1 }, 125 0,
126}; 126};
127 127
128/* 128/*
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 56021a72e10c..95a5fc53b6db 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o time.o 5obj-y := irq.o pcie.o time.o common.o mpp.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
new file mode 100644
index 000000000000..9e5451b3c8e3
--- /dev/null
+++ b/arch/arm/plat-orion/common.c
@@ -0,0 +1,957 @@
1/*
2 * arch/arm/plat-orion/common.c
3 *
4 * Marvell Orion SoC common setup code used by multiple mach-/common.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/dma-mapping.h>
15#include <linux/serial_8250.h>
16#include <linux/mbus.h>
17#include <linux/ata_platform.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/mv643xx_i2c.h>
20#include <net/dsa.h>
21#include <linux/spi/orion_spi.h>
22#include <plat/orion_wdt.h>
23#include <plat/mv_xor.h>
24#include <plat/ehci-orion.h>
25
26/* Fill in the resources structure and link it into the platform
27 device structure. There is always a memory region, and nearly
28 always an interrupt.*/
29static void fill_resources(struct platform_device *device,
30 struct resource *resources,
31 resource_size_t mapbase,
32 resource_size_t size,
33 unsigned int irq)
34{
35 device->resource = resources;
36 device->num_resources = 1;
37 resources[0].flags = IORESOURCE_MEM;
38 resources[0].start = mapbase;
39 resources[0].end = mapbase + size;
40
41 if (irq != NO_IRQ) {
42 device->num_resources++;
43 resources[1].flags = IORESOURCE_IRQ;
44 resources[1].start = irq;
45 resources[1].end = irq;
46 }
47}
48
49/*****************************************************************************
50 * UART
51 ****************************************************************************/
52static void __init uart_complete(
53 struct platform_device *orion_uart,
54 struct plat_serial8250_port *data,
55 struct resource *resources,
56 unsigned int membase,
57 resource_size_t mapbase,
58 unsigned int irq,
59 unsigned int uartclk)
60{
61 data->mapbase = mapbase;
62 data->membase = (void __iomem *)membase;
63 data->irq = irq;
64 data->uartclk = uartclk;
65 orion_uart->dev.platform_data = data;
66
67 fill_resources(orion_uart, resources, mapbase, 0xff, irq);
68 platform_device_register(orion_uart);
69}
70
71/*****************************************************************************
72 * UART0
73 ****************************************************************************/
74static struct plat_serial8250_port orion_uart0_data[] = {
75 {
76 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
77 .iotype = UPIO_MEM,
78 .regshift = 2,
79 }, {
80 },
81};
82
83static struct resource orion_uart0_resources[2];
84
85static struct platform_device orion_uart0 = {
86 .name = "serial8250",
87 .id = PLAT8250_DEV_PLATFORM,
88};
89
90void __init orion_uart0_init(unsigned int membase,
91 resource_size_t mapbase,
92 unsigned int irq,
93 unsigned int uartclk)
94{
95 uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
96 membase, mapbase, irq, uartclk);
97}
98
99/*****************************************************************************
100 * UART1
101 ****************************************************************************/
102static struct plat_serial8250_port orion_uart1_data[] = {
103 {
104 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
105 .iotype = UPIO_MEM,
106 .regshift = 2,
107 }, {
108 },
109};
110
111static struct resource orion_uart1_resources[2];
112
113static struct platform_device orion_uart1 = {
114 .name = "serial8250",
115 .id = PLAT8250_DEV_PLATFORM1,
116};
117
118void __init orion_uart1_init(unsigned int membase,
119 resource_size_t mapbase,
120 unsigned int irq,
121 unsigned int uartclk)
122{
123 uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
124 membase, mapbase, irq, uartclk);
125}
126
127/*****************************************************************************
128 * UART2
129 ****************************************************************************/
130static struct plat_serial8250_port orion_uart2_data[] = {
131 {
132 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
133 .iotype = UPIO_MEM,
134 .regshift = 2,
135 }, {
136 },
137};
138
139static struct resource orion_uart2_resources[2];
140
141static struct platform_device orion_uart2 = {
142 .name = "serial8250",
143 .id = PLAT8250_DEV_PLATFORM2,
144};
145
146void __init orion_uart2_init(unsigned int membase,
147 resource_size_t mapbase,
148 unsigned int irq,
149 unsigned int uartclk)
150{
151 uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
152 membase, mapbase, irq, uartclk);
153}
154
155/*****************************************************************************
156 * UART3
157 ****************************************************************************/
158static struct plat_serial8250_port orion_uart3_data[] = {
159 {
160 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
161 .iotype = UPIO_MEM,
162 .regshift = 2,
163 }, {
164 },
165};
166
167static struct resource orion_uart3_resources[2];
168
169static struct platform_device orion_uart3 = {
170 .name = "serial8250",
171 .id = 3,
172};
173
174void __init orion_uart3_init(unsigned int membase,
175 resource_size_t mapbase,
176 unsigned int irq,
177 unsigned int uartclk)
178{
179 uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
180 membase, mapbase, irq, uartclk);
181}
182
183/*****************************************************************************
184 * SoC RTC
185 ****************************************************************************/
186static struct resource orion_rtc_resource[2];
187
188void __init orion_rtc_init(unsigned long mapbase,
189 unsigned long irq)
190{
191 orion_rtc_resource[0].start = mapbase;
192 orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
193 orion_rtc_resource[0].flags = IORESOURCE_MEM;
194 orion_rtc_resource[1].start = irq;
195 orion_rtc_resource[1].end = irq;
196 orion_rtc_resource[1].flags = IORESOURCE_IRQ;
197
198 platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
199}
200
201/*****************************************************************************
202 * GE
203 ****************************************************************************/
204static __init void ge_complete(
205 struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
206 struct mbus_dram_target_info *mbus_dram_info, int tclk,
207 struct resource *orion_ge_resource, unsigned long irq,
208 struct platform_device *orion_ge_shared,
209 struct mv643xx_eth_platform_data *eth_data,
210 struct platform_device *orion_ge)
211{
212 orion_ge_shared_data->dram = mbus_dram_info;
213 orion_ge_shared_data->t_clk = tclk;
214 orion_ge_resource->start = irq;
215 orion_ge_resource->end = irq;
216 eth_data->shared = orion_ge_shared;
217 orion_ge->dev.platform_data = eth_data;
218
219 platform_device_register(orion_ge_shared);
220 platform_device_register(orion_ge);
221}
222
223/*****************************************************************************
224 * GE00
225 ****************************************************************************/
226struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
227
228static struct resource orion_ge00_shared_resources[] = {
229 {
230 .name = "ge00 base",
231 }, {
232 .name = "ge00 err irq",
233 },
234};
235
236static struct platform_device orion_ge00_shared = {
237 .name = MV643XX_ETH_SHARED_NAME,
238 .id = 0,
239 .dev = {
240 .platform_data = &orion_ge00_shared_data,
241 },
242};
243
244static struct resource orion_ge00_resources[] = {
245 {
246 .name = "ge00 irq",
247 .flags = IORESOURCE_IRQ,
248 },
249};
250
251static struct platform_device orion_ge00 = {
252 .name = MV643XX_ETH_NAME,
253 .id = 0,
254 .num_resources = 1,
255 .resource = orion_ge00_resources,
256 .dev = {
257 .coherent_dma_mask = DMA_BIT_MASK(32),
258 },
259};
260
261void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
262 struct mbus_dram_target_info *mbus_dram_info,
263 unsigned long mapbase,
264 unsigned long irq,
265 unsigned long irq_err,
266 int tclk)
267{
268 fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
269 mapbase + 0x2000, SZ_16K - 1, irq_err);
270 ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
271 orion_ge00_resources, irq, &orion_ge00_shared,
272 eth_data, &orion_ge00);
273}
274
275/*****************************************************************************
276 * GE01
277 ****************************************************************************/
278struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
279 .shared_smi = &orion_ge00_shared,
280};
281
282static struct resource orion_ge01_shared_resources[] = {
283 {
284 .name = "ge01 base",
285 }, {
286 .name = "ge01 err irq",
287 },
288};
289
290static struct platform_device orion_ge01_shared = {
291 .name = MV643XX_ETH_SHARED_NAME,
292 .id = 1,
293 .dev = {
294 .platform_data = &orion_ge01_shared_data,
295 },
296};
297
298static struct resource orion_ge01_resources[] = {
299 {
300 .name = "ge01 irq",
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct platform_device orion_ge01 = {
306 .name = MV643XX_ETH_NAME,
307 .id = 1,
308 .num_resources = 1,
309 .resource = orion_ge01_resources,
310 .dev = {
311 .coherent_dma_mask = DMA_BIT_MASK(32),
312 },
313};
314
315void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
316 struct mbus_dram_target_info *mbus_dram_info,
317 unsigned long mapbase,
318 unsigned long irq,
319 unsigned long irq_err,
320 int tclk)
321{
322 fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
323 mapbase + 0x2000, SZ_16K - 1, irq_err);
324 ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
325 orion_ge01_resources, irq, &orion_ge01_shared,
326 eth_data, &orion_ge01);
327}
328
329/*****************************************************************************
330 * GE10
331 ****************************************************************************/
332struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
333 .shared_smi = &orion_ge00_shared,
334};
335
336static struct resource orion_ge10_shared_resources[] = {
337 {
338 .name = "ge10 base",
339 }, {
340 .name = "ge10 err irq",
341 },
342};
343
344static struct platform_device orion_ge10_shared = {
345 .name = MV643XX_ETH_SHARED_NAME,
346 .id = 1,
347 .dev = {
348 .platform_data = &orion_ge10_shared_data,
349 },
350};
351
352static struct resource orion_ge10_resources[] = {
353 {
354 .name = "ge10 irq",
355 .flags = IORESOURCE_IRQ,
356 },
357};
358
359static struct platform_device orion_ge10 = {
360 .name = MV643XX_ETH_NAME,
361 .id = 1,
362 .num_resources = 2,
363 .resource = orion_ge10_resources,
364 .dev = {
365 .coherent_dma_mask = DMA_BIT_MASK(32),
366 },
367};
368
369void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
370 struct mbus_dram_target_info *mbus_dram_info,
371 unsigned long mapbase,
372 unsigned long irq,
373 unsigned long irq_err,
374 int tclk)
375{
376 fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
377 mapbase + 0x2000, SZ_16K - 1, irq_err);
378 ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
379 orion_ge10_resources, irq, &orion_ge10_shared,
380 eth_data, &orion_ge10);
381}
382
383/*****************************************************************************
384 * GE11
385 ****************************************************************************/
386struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
387 .shared_smi = &orion_ge00_shared,
388};
389
390static struct resource orion_ge11_shared_resources[] = {
391 {
392 .name = "ge11 base",
393 }, {
394 .name = "ge11 err irq",
395 },
396};
397
398static struct platform_device orion_ge11_shared = {
399 .name = MV643XX_ETH_SHARED_NAME,
400 .id = 1,
401 .dev = {
402 .platform_data = &orion_ge11_shared_data,
403 },
404};
405
406static struct resource orion_ge11_resources[] = {
407 {
408 .name = "ge11 irq",
409 .flags = IORESOURCE_IRQ,
410 },
411};
412
413static struct platform_device orion_ge11 = {
414 .name = MV643XX_ETH_NAME,
415 .id = 1,
416 .num_resources = 2,
417 .resource = orion_ge11_resources,
418 .dev = {
419 .coherent_dma_mask = DMA_BIT_MASK(32),
420 },
421};
422
423void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
424 struct mbus_dram_target_info *mbus_dram_info,
425 unsigned long mapbase,
426 unsigned long irq,
427 unsigned long irq_err,
428 int tclk)
429{
430 fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
431 mapbase + 0x2000, SZ_16K - 1, irq_err);
432 ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
433 orion_ge11_resources, irq, &orion_ge11_shared,
434 eth_data, &orion_ge11);
435}
436
437/*****************************************************************************
438 * Ethernet switch
439 ****************************************************************************/
440static struct resource orion_switch_resources[] = {
441 {
442 .start = 0,
443 .end = 0,
444 .flags = IORESOURCE_IRQ,
445 },
446};
447
448static struct platform_device orion_switch_device = {
449 .name = "dsa",
450 .id = 0,
451 .num_resources = 0,
452 .resource = orion_switch_resources,
453};
454
455void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
456{
457 int i;
458
459 if (irq != NO_IRQ) {
460 orion_switch_resources[0].start = irq;
461 orion_switch_resources[0].end = irq;
462 orion_switch_device.num_resources = 1;
463 }
464
465 d->netdev = &orion_ge00.dev;
466 for (i = 0; i < d->nr_chips; i++)
467 d->chip[i].mii_bus = &orion_ge00_shared.dev;
468 orion_switch_device.dev.platform_data = d;
469
470 platform_device_register(&orion_switch_device);
471}
472
473/*****************************************************************************
474 * I2C
475 ****************************************************************************/
476static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
477 .freq_n = 3,
478 .timeout = 1000, /* Default timeout of 1 second */
479};
480
481static struct resource orion_i2c_resources[2];
482
483static struct platform_device orion_i2c = {
484 .name = MV64XXX_I2C_CTLR_NAME,
485 .id = 0,
486 .dev = {
487 .platform_data = &orion_i2c_pdata,
488 },
489};
490
491static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
492 .freq_n = 3,
493 .timeout = 1000, /* Default timeout of 1 second */
494};
495
496static struct resource orion_i2c_1_resources[2];
497
498static struct platform_device orion_i2c_1 = {
499 .name = MV64XXX_I2C_CTLR_NAME,
500 .id = 1,
501 .dev = {
502 .platform_data = &orion_i2c_1_pdata,
503 },
504};
505
506void __init orion_i2c_init(unsigned long mapbase,
507 unsigned long irq,
508 unsigned long freq_m)
509{
510 orion_i2c_pdata.freq_m = freq_m;
511 fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
512 SZ_32 - 1, irq);
513 platform_device_register(&orion_i2c);
514}
515
516void __init orion_i2c_1_init(unsigned long mapbase,
517 unsigned long irq,
518 unsigned long freq_m)
519{
520 orion_i2c_1_pdata.freq_m = freq_m;
521 fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
522 SZ_32 - 1, irq);
523 platform_device_register(&orion_i2c_1);
524}
525
526/*****************************************************************************
527 * SPI
528 ****************************************************************************/
529static struct orion_spi_info orion_spi_plat_data;
530static struct resource orion_spi_resources;
531
532static struct platform_device orion_spi = {
533 .name = "orion_spi",
534 .id = 0,
535 .dev = {
536 .platform_data = &orion_spi_plat_data,
537 },
538};
539
540static struct orion_spi_info orion_spi_1_plat_data;
541static struct resource orion_spi_1_resources;
542
543static struct platform_device orion_spi_1 = {
544 .name = "orion_spi",
545 .id = 1,
546 .dev = {
547 .platform_data = &orion_spi_1_plat_data,
548 },
549};
550
551/* Note: The SPI silicon core does have interrupts. However the
552 * current Linux software driver does not use interrupts. */
553
554void __init orion_spi_init(unsigned long mapbase,
555 unsigned long tclk)
556{
557 orion_spi_plat_data.tclk = tclk;
558 fill_resources(&orion_spi, &orion_spi_resources,
559 mapbase, SZ_512 - 1, NO_IRQ);
560 platform_device_register(&orion_spi);
561}
562
563void __init orion_spi_1_init(unsigned long mapbase,
564 unsigned long tclk)
565{
566 orion_spi_1_plat_data.tclk = tclk;
567 fill_resources(&orion_spi_1, &orion_spi_1_resources,
568 mapbase, SZ_512 - 1, NO_IRQ);
569 platform_device_register(&orion_spi_1);
570}
571
572/*****************************************************************************
573 * Watchdog
574 ****************************************************************************/
575static struct orion_wdt_platform_data orion_wdt_data;
576
577static struct platform_device orion_wdt_device = {
578 .name = "orion_wdt",
579 .id = -1,
580 .dev = {
581 .platform_data = &orion_wdt_data,
582 },
583 .num_resources = 0,
584};
585
586void __init orion_wdt_init(unsigned long tclk)
587{
588 orion_wdt_data.tclk = tclk;
589 platform_device_register(&orion_wdt_device);
590}
591
592/*****************************************************************************
593 * XOR
594 ****************************************************************************/
595static struct mv_xor_platform_shared_data orion_xor_shared_data;
596
597static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
598
599void __init orion_xor_init_channels(
600 struct mv_xor_platform_data *orion_xor0_data,
601 struct platform_device *orion_xor0_channel,
602 struct mv_xor_platform_data *orion_xor1_data,
603 struct platform_device *orion_xor1_channel)
604{
605 /*
606 * two engines can't do memset simultaneously, this limitation
607 * satisfied by removing memset support from one of the engines.
608 */
609 dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
610 dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
611 platform_device_register(orion_xor0_channel);
612
613 dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
614 dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
615 dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
616 platform_device_register(orion_xor1_channel);
617}
618
619/*****************************************************************************
620 * XOR0
621 ****************************************************************************/
622static struct resource orion_xor0_shared_resources[] = {
623 {
624 .name = "xor 0 low",
625 .flags = IORESOURCE_MEM,
626 }, {
627 .name = "xor 0 high",
628 .flags = IORESOURCE_MEM,
629 },
630};
631
632static struct platform_device orion_xor0_shared = {
633 .name = MV_XOR_SHARED_NAME,
634 .id = 0,
635 .dev = {
636 .platform_data = &orion_xor_shared_data,
637 },
638 .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
639 .resource = orion_xor0_shared_resources,
640};
641
642static struct resource orion_xor00_resources[] = {
643 [0] = {
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct mv_xor_platform_data orion_xor00_data = {
649 .shared = &orion_xor0_shared,
650 .hw_id = 0,
651 .pool_size = PAGE_SIZE,
652};
653
654static struct platform_device orion_xor00_channel = {
655 .name = MV_XOR_NAME,
656 .id = 0,
657 .num_resources = ARRAY_SIZE(orion_xor00_resources),
658 .resource = orion_xor00_resources,
659 .dev = {
660 .dma_mask = &orion_xor_dmamask,
661 .coherent_dma_mask = DMA_BIT_MASK(64),
662 .platform_data = &orion_xor00_data,
663 },
664};
665
666static struct resource orion_xor01_resources[] = {
667 [0] = {
668 .flags = IORESOURCE_IRQ,
669 },
670};
671
672static struct mv_xor_platform_data orion_xor01_data = {
673 .shared = &orion_xor0_shared,
674 .hw_id = 1,
675 .pool_size = PAGE_SIZE,
676};
677
678static struct platform_device orion_xor01_channel = {
679 .name = MV_XOR_NAME,
680 .id = 1,
681 .num_resources = ARRAY_SIZE(orion_xor01_resources),
682 .resource = orion_xor01_resources,
683 .dev = {
684 .dma_mask = &orion_xor_dmamask,
685 .coherent_dma_mask = DMA_BIT_MASK(64),
686 .platform_data = &orion_xor01_data,
687 },
688};
689
690void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
691 unsigned long mapbase_low,
692 unsigned long mapbase_high,
693 unsigned long irq_0,
694 unsigned long irq_1)
695{
696 orion_xor_shared_data.dram = mbus_dram_info;
697
698 orion_xor0_shared_resources[0].start = mapbase_low;
699 orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
700 orion_xor0_shared_resources[1].start = mapbase_high;
701 orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
702
703 orion_xor00_resources[0].start = irq_0;
704 orion_xor00_resources[0].end = irq_0;
705 orion_xor01_resources[0].start = irq_1;
706 orion_xor01_resources[0].end = irq_1;
707
708 platform_device_register(&orion_xor0_shared);
709
710 orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
711 &orion_xor01_data, &orion_xor01_channel);
712}
713
714/*****************************************************************************
715 * XOR1
716 ****************************************************************************/
717static struct resource orion_xor1_shared_resources[] = {
718 {
719 .name = "xor 1 low",
720 .flags = IORESOURCE_MEM,
721 }, {
722 .name = "xor 1 high",
723 .flags = IORESOURCE_MEM,
724 },
725};
726
727static struct platform_device orion_xor1_shared = {
728 .name = MV_XOR_SHARED_NAME,
729 .id = 1,
730 .dev = {
731 .platform_data = &orion_xor_shared_data,
732 },
733 .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
734 .resource = orion_xor1_shared_resources,
735};
736
737static struct resource orion_xor10_resources[] = {
738 [0] = {
739 .flags = IORESOURCE_IRQ,
740 },
741};
742
743static struct mv_xor_platform_data orion_xor10_data = {
744 .shared = &orion_xor1_shared,
745 .hw_id = 0,
746 .pool_size = PAGE_SIZE,
747};
748
749static struct platform_device orion_xor10_channel = {
750 .name = MV_XOR_NAME,
751 .id = 2,
752 .num_resources = ARRAY_SIZE(orion_xor10_resources),
753 .resource = orion_xor10_resources,
754 .dev = {
755 .dma_mask = &orion_xor_dmamask,
756 .coherent_dma_mask = DMA_BIT_MASK(64),
757 .platform_data = &orion_xor10_data,
758 },
759};
760
761static struct resource orion_xor11_resources[] = {
762 [0] = {
763 .flags = IORESOURCE_IRQ,
764 },
765};
766
767static struct mv_xor_platform_data orion_xor11_data = {
768 .shared = &orion_xor1_shared,
769 .hw_id = 1,
770 .pool_size = PAGE_SIZE,
771};
772
773static struct platform_device orion_xor11_channel = {
774 .name = MV_XOR_NAME,
775 .id = 3,
776 .num_resources = ARRAY_SIZE(orion_xor11_resources),
777 .resource = orion_xor11_resources,
778 .dev = {
779 .dma_mask = &orion_xor_dmamask,
780 .coherent_dma_mask = DMA_BIT_MASK(64),
781 .platform_data = &orion_xor11_data,
782 },
783};
784
785void __init orion_xor1_init(unsigned long mapbase_low,
786 unsigned long mapbase_high,
787 unsigned long irq_0,
788 unsigned long irq_1)
789{
790 orion_xor1_shared_resources[0].start = mapbase_low;
791 orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
792 orion_xor1_shared_resources[1].start = mapbase_high;
793 orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
794
795 orion_xor10_resources[0].start = irq_0;
796 orion_xor10_resources[0].end = irq_0;
797 orion_xor11_resources[0].start = irq_1;
798 orion_xor11_resources[0].end = irq_1;
799
800 platform_device_register(&orion_xor1_shared);
801
802 orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
803 &orion_xor11_data, &orion_xor11_channel);
804}
805
806/*****************************************************************************
807 * EHCI
808 ****************************************************************************/
809static struct orion_ehci_data orion_ehci_data = {
810 .phy_version = EHCI_PHY_NA,
811};
812
813static u64 ehci_dmamask = DMA_BIT_MASK(32);
814
815
816/*****************************************************************************
817 * EHCI0
818 ****************************************************************************/
819static struct resource orion_ehci_resources[2];
820
821static struct platform_device orion_ehci = {
822 .name = "orion-ehci",
823 .id = 0,
824 .dev = {
825 .dma_mask = &ehci_dmamask,
826 .coherent_dma_mask = DMA_BIT_MASK(32),
827 .platform_data = &orion_ehci_data,
828 },
829};
830
831void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
832 unsigned long mapbase,
833 unsigned long irq)
834{
835 orion_ehci_data.dram = mbus_dram_info;
836 fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
837 irq);
838
839 platform_device_register(&orion_ehci);
840}
841
842/*****************************************************************************
843 * EHCI1
844 ****************************************************************************/
845static struct resource orion_ehci_1_resources[2];
846
847static struct platform_device orion_ehci_1 = {
848 .name = "orion-ehci",
849 .id = 1,
850 .dev = {
851 .dma_mask = &ehci_dmamask,
852 .coherent_dma_mask = DMA_BIT_MASK(32),
853 .platform_data = &orion_ehci_data,
854 },
855};
856
857void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
858 unsigned long mapbase,
859 unsigned long irq)
860{
861 orion_ehci_data.dram = mbus_dram_info;
862 fill_resources(&orion_ehci_1, orion_ehci_1_resources,
863 mapbase, SZ_4K - 1, irq);
864
865 platform_device_register(&orion_ehci_1);
866}
867
868/*****************************************************************************
869 * EHCI2
870 ****************************************************************************/
871static struct resource orion_ehci_2_resources[2];
872
873static struct platform_device orion_ehci_2 = {
874 .name = "orion-ehci",
875 .id = 2,
876 .dev = {
877 .dma_mask = &ehci_dmamask,
878 .coherent_dma_mask = DMA_BIT_MASK(32),
879 .platform_data = &orion_ehci_data,
880 },
881};
882
883void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
884 unsigned long mapbase,
885 unsigned long irq)
886{
887 orion_ehci_data.dram = mbus_dram_info;
888 fill_resources(&orion_ehci_2, orion_ehci_2_resources,
889 mapbase, SZ_4K - 1, irq);
890
891 platform_device_register(&orion_ehci_2);
892}
893
894/*****************************************************************************
895 * SATA
896 ****************************************************************************/
897static struct resource orion_sata_resources[2] = {
898 {
899 .name = "sata base",
900 }, {
901 .name = "sata irq",
902 },
903};
904
905static struct platform_device orion_sata = {
906 .name = "sata_mv",
907 .id = 0,
908 .dev = {
909 .coherent_dma_mask = DMA_BIT_MASK(32),
910 },
911};
912
913void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
914 struct mbus_dram_target_info *mbus_dram_info,
915 unsigned long mapbase,
916 unsigned long irq)
917{
918 sata_data->dram = mbus_dram_info;
919 orion_sata.dev.platform_data = sata_data;
920 fill_resources(&orion_sata, orion_sata_resources,
921 mapbase, 0x5000 - 1, irq);
922
923 platform_device_register(&orion_sata);
924}
925
926/*****************************************************************************
927 * Cryptographic Engines and Security Accelerator (CESA)
928 ****************************************************************************/
929static struct resource orion_crypto_resources[] = {
930 {
931 .name = "regs",
932 }, {
933 .name = "crypto interrupt",
934 }, {
935 .name = "sram",
936 .flags = IORESOURCE_MEM,
937 },
938};
939
940static struct platform_device orion_crypto = {
941 .name = "mv_crypto",
942 .id = -1,
943};
944
945void __init orion_crypto_init(unsigned long mapbase,
946 unsigned long srambase,
947 unsigned long sram_size,
948 unsigned long irq)
949{
950 fill_resources(&orion_crypto, orion_crypto_resources,
951 mapbase, 0xffff, irq);
952 orion_crypto.num_resources = 3;
953 orion_crypto_resources[2].start = srambase;
954 orion_crypto_resources[2].end = srambase + sram_size - 1;
955
956 platform_device_register(&orion_crypto);
957}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index a431a138f402..5b4fffab1eb4 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -321,59 +321,16 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
321 * polarity LEVEL mask 321 * polarity LEVEL mask
322 * 322 *
323 ****************************************************************************/ 323 ****************************************************************************/
324static void gpio_irq_ack(struct irq_data *d)
325{
326 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
327 int type = irqd_get_trigger_type(d);
328
329 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
330 int pin = d->irq - ochip->secondary_irq_base;
331
332 writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
333 }
334}
335
336static void gpio_irq_mask(struct irq_data *d)
337{
338 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
339 int type = irqd_get_trigger_type(d);
340 void __iomem *reg;
341 int pin;
342
343 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
344 reg = GPIO_EDGE_MASK(ochip);
345 else
346 reg = GPIO_LEVEL_MASK(ochip);
347
348 pin = d->irq - ochip->secondary_irq_base;
349
350 writel(readl(reg) & ~(1 << pin), reg);
351}
352
353static void gpio_irq_unmask(struct irq_data *d)
354{
355 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
356 int type = irqd_get_trigger_type(d);
357 void __iomem *reg;
358 int pin;
359
360 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
361 reg = GPIO_EDGE_MASK(ochip);
362 else
363 reg = GPIO_LEVEL_MASK(ochip);
364
365 pin = d->irq - ochip->secondary_irq_base;
366
367 writel(readl(reg) | (1 << pin), reg);
368}
369 324
370static int gpio_irq_set_type(struct irq_data *d, u32 type) 325static int gpio_irq_set_type(struct irq_data *d, u32 type)
371{ 326{
372 struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d); 327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
328 struct irq_chip_type *ct = irq_data_get_chip_type(d);
329 struct orion_gpio_chip *ochip = gc->private;
373 int pin; 330 int pin;
374 u32 u; 331 u32 u;
375 332
376 pin = d->irq - ochip->secondary_irq_base; 333 pin = d->irq - gc->irq_base;
377 334
378 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); 335 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
379 if (!u) { 336 if (!u) {
@@ -382,18 +339,14 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
382 return -EINVAL; 339 return -EINVAL;
383 } 340 }
384 341
385 /* 342 type &= IRQ_TYPE_SENSE_MASK;
386 * Set edge/level type. 343 if (type == IRQ_TYPE_NONE)
387 */
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
389 __irq_set_handler_locked(d->irq, handle_edge_irq);
390 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
391 __irq_set_handler_locked(d->irq, handle_level_irq);
392 } else {
393 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
394 d->irq, type);
395 return -EINVAL; 344 return -EINVAL;
396 } 345
346 /* Check if we need to change chip and handler */
347 if (!(ct->type & type))
348 if (irq_setup_alt_chip(d, type))
349 return -EINVAL;
397 350
398 /* 351 /*
399 * Configure interrupt polarity. 352 * Configure interrupt polarity.
@@ -425,19 +378,12 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
425 return 0; 378 return 0;
426} 379}
427 380
428struct irq_chip orion_gpio_irq_chip = {
429 .name = "orion_gpio_irq",
430 .irq_ack = gpio_irq_ack,
431 .irq_mask = gpio_irq_mask,
432 .irq_unmask = gpio_irq_unmask,
433 .irq_set_type = gpio_irq_set_type,
434};
435
436void __init orion_gpio_init(int gpio_base, int ngpio, 381void __init orion_gpio_init(int gpio_base, int ngpio,
437 u32 base, int mask_offset, int secondary_irq_base) 382 u32 base, int mask_offset, int secondary_irq_base)
438{ 383{
439 struct orion_gpio_chip *ochip; 384 struct orion_gpio_chip *ochip;
440 int i; 385 struct irq_chip_generic *gc;
386 struct irq_chip_type *ct;
441 387
442 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) 388 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
443 return; 389 return;
@@ -471,15 +417,29 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
471 writel(0, GPIO_EDGE_MASK(ochip)); 417 writel(0, GPIO_EDGE_MASK(ochip));
472 writel(0, GPIO_LEVEL_MASK(ochip)); 418 writel(0, GPIO_LEVEL_MASK(ochip));
473 419
474 for (i = 0; i < ngpio; i++) { 420 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
475 unsigned int irq = secondary_irq_base + i; 421 ochip->base, handle_level_irq);
476 422 gc->private = ochip;
477 irq_set_chip_and_handler(irq, &orion_gpio_irq_chip, 423
478 handle_level_irq); 424 ct = gc->chip_types;
479 irq_set_chip_data(irq, ochip); 425 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
480 irq_set_status_flags(irq, IRQ_LEVEL); 426 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
481 set_irq_flags(irq, IRQF_VALID); 427 ct->chip.irq_mask = irq_gc_mask_clr_bit;
482 } 428 ct->chip.irq_unmask = irq_gc_mask_set_bit;
429 ct->chip.irq_set_type = gpio_irq_set_type;
430
431 ct++;
432 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
433 ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
434 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
435 ct->chip.irq_ack = irq_gc_ack;
436 ct->chip.irq_mask = irq_gc_mask_clr_bit;
437 ct->chip.irq_unmask = irq_gc_mask_set_bit;
438 ct->chip.irq_set_type = gpio_irq_set_type;
439 ct->handler = handle_edge_irq;
440
441 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
442 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
483} 443}
484 444
485void orion_gpio_irq_handler(int pinoff) 445void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
new file mode 100644
index 000000000000..a63c357e2ab1
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -0,0 +1,117 @@
1/*
2 * arch/arm/plat-orion/include/plat/common.h
3 *
4 * Marvell Orion SoC common setup code used by different mach-/common.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_COMMON_H
12#include <linux/mv643xx_eth.h>
13
14struct dsa_platform_data;
15
16void __init orion_uart0_init(unsigned int membase,
17 resource_size_t mapbase,
18 unsigned int irq,
19 unsigned int uartclk);
20
21void __init orion_uart1_init(unsigned int membase,
22 resource_size_t mapbase,
23 unsigned int irq,
24 unsigned int uartclk);
25
26void __init orion_uart2_init(unsigned int membase,
27 resource_size_t mapbase,
28 unsigned int irq,
29 unsigned int uartclk);
30
31void __init orion_uart3_init(unsigned int membase,
32 resource_size_t mapbase,
33 unsigned int irq,
34 unsigned int uartclk);
35
36void __init orion_rtc_init(unsigned long mapbase,
37 unsigned long irq);
38
39void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
40 struct mbus_dram_target_info *mbus_dram_info,
41 unsigned long mapbase,
42 unsigned long irq,
43 unsigned long irq_err,
44 int tclk);
45
46void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
47 struct mbus_dram_target_info *mbus_dram_info,
48 unsigned long mapbase,
49 unsigned long irq,
50 unsigned long irq_err,
51 int tclk);
52
53void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
54 struct mbus_dram_target_info *mbus_dram_info,
55 unsigned long mapbase,
56 unsigned long irq,
57 unsigned long irq_err,
58 int tclk);
59
60void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
61 struct mbus_dram_target_info *mbus_dram_info,
62 unsigned long mapbase,
63 unsigned long irq,
64 unsigned long irq_err,
65 int tclk);
66
67void __init orion_ge00_switch_init(struct dsa_platform_data *d,
68 int irq);
69void __init orion_i2c_init(unsigned long mapbase,
70 unsigned long irq,
71 unsigned long freq_m);
72
73void __init orion_i2c_1_init(unsigned long mapbase,
74 unsigned long irq,
75 unsigned long freq_m);
76
77void __init orion_spi_init(unsigned long mapbase,
78 unsigned long tclk);
79
80void __init orion_spi_1_init(unsigned long mapbase,
81 unsigned long tclk);
82
83void __init orion_wdt_init(unsigned long tclk);
84
85void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
86 unsigned long mapbase_low,
87 unsigned long mapbase_high,
88 unsigned long irq_0,
89 unsigned long irq_1);
90
91void __init orion_xor1_init(unsigned long mapbase_low,
92 unsigned long mapbase_high,
93 unsigned long irq_0,
94 unsigned long irq_1);
95
96void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
97 unsigned long mapbase,
98 unsigned long irq);
99
100void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
101 unsigned long mapbase,
102 unsigned long irq);
103
104void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
105 unsigned long mapbase,
106 unsigned long irq);
107
108void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
109 struct mbus_dram_target_info *mbus_dram_info,
110 unsigned long mapbase,
111 unsigned long irq);
112
113void __init orion_crypto_init(unsigned long mapbase,
114 unsigned long srambase,
115 unsigned long sram_size,
116 unsigned long irq);
117#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 5578b9803fc6..3075b9fdde83 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -39,7 +39,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
39/* 39/*
40 * GPIO interrupt handling. 40 * GPIO interrupt handling.
41 */ 41 */
42extern struct irq_chip orion_gpio_irq_chip;
43void orion_gpio_irq_handler(int irqoff); 42void orion_gpio_irq_handler(int irqoff);
44 43
45 44
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
new file mode 100644
index 000000000000..723adce99f41
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -0,0 +1,34 @@
1/*
2 * arch/arm/plat-orion/include/plat/mpp.h
3 *
4 * Marvell Orion SoC MPP handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __PLAT_MPP_H
12#define __PLAT_MPP_H
13
14#define MPP_NUM(x) ((x) & 0xff)
15#define MPP_SEL(x) (((x) >> 8) & 0xf)
16
17/* This is the generic MPP macro, without any variant information.
18 Each machine architecture is expected to extend this with further
19 bit fields indicating which MPP configurations are valid for a
20 specific variant. */
21
22#define GENERIC_MPP(_num, _sel, _in, _out) ( \
23 /* MPP number */ ((_num) & 0xff) | \
24 /* MPP select value */ (((_sel) & 0xf) << 8) | \
25 /* may be input signal */ ((!!(_in)) << 12) | \
26 /* may be output signal */ ((!!(_out)) << 13))
27
28#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0)
29#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
30
31void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
32 unsigned int mpp_max, unsigned int dev_bus);
33
34#endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d8d638e09f8f..2d5b9c1ef389 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,52 +14,21 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <plat/irq.h> 15#include <plat/irq.h>
16 16
17static void orion_irq_mask(struct irq_data *d)
18{
19 void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
20 u32 mask;
21
22 mask = readl(maskaddr);
23 mask &= ~(1 << (d->irq & 31));
24 writel(mask, maskaddr);
25}
26
27static void orion_irq_unmask(struct irq_data *d)
28{
29 void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
30 u32 mask;
31
32 mask = readl(maskaddr);
33 mask |= 1 << (d->irq & 31);
34 writel(mask, maskaddr);
35}
36
37static struct irq_chip orion_irq_chip = {
38 .name = "orion_irq",
39 .irq_mask = orion_irq_mask,
40 .irq_mask_ack = orion_irq_mask,
41 .irq_unmask = orion_irq_unmask,
42};
43
44void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr) 17void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
45{ 18{
46 unsigned int i; 19 struct irq_chip_generic *gc;
20 struct irq_chip_type *ct;
47 21
48 /* 22 /*
49 * Mask all interrupts initially. 23 * Mask all interrupts initially.
50 */ 24 */
51 writel(0, maskaddr); 25 writel(0, maskaddr);
52 26
53 /* 27 gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
54 * Register IRQ sources. 28 handle_level_irq);
55 */ 29 ct = gc->chip_types;
56 for (i = 0; i < 32; i++) { 30 ct->chip.irq_mask = irq_gc_mask_clr_bit;
57 unsigned int irq = irq_start + i; 31 ct->chip.irq_unmask = irq_gc_mask_set_bit;
58 32 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
59 irq_set_chip_and_handler(irq, &orion_irq_chip, 33 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
60 handle_level_irq);
61 irq_set_chip_data(irq, maskaddr);
62 irq_set_status_flags(irq, IRQ_LEVEL);
63 set_irq_flags(irq, IRQF_VALID);
64 }
65} 34}
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
new file mode 100644
index 000000000000..91553432711d
--- /dev/null
+++ b/arch/arm/plat-orion/mpp.c
@@ -0,0 +1,78 @@
1/*
2 * arch/arm/plat-orion/mpp.c
3 *
4 * MPP functions for Marvell orion SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16#include <mach/hardware.h>
17#include <plat/mpp.h>
18
19/* Address of the ith MPP control register */
20static __init unsigned long mpp_ctrl_addr(unsigned int i,
21 unsigned long dev_bus)
22{
23 return dev_bus + (i) * 4;
24}
25
26
27void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
28 unsigned int mpp_max, unsigned int dev_bus)
29{
30 unsigned int mpp_nr_regs = (1 + mpp_max/8);
31 u32 mpp_ctrl[mpp_nr_regs];
32 int i;
33
34 printk(KERN_DEBUG "initial MPP regs:");
35 for (i = 0; i < mpp_nr_regs; i++) {
36 mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
37 printk(" %08x", mpp_ctrl[i]);
38 }
39 printk("\n");
40
41 for ( ; *mpp_list; mpp_list++) {
42 unsigned int num = MPP_NUM(*mpp_list);
43 unsigned int sel = MPP_SEL(*mpp_list);
44 int shift, gpio_mode;
45
46 if (num > mpp_max) {
47 printk(KERN_ERR "orion_mpp_conf: invalid MPP "
48 "number (%u)\n", num);
49 continue;
50 }
51 if (variant_mask & !(*mpp_list & variant_mask)) {
52 printk(KERN_WARNING
53 "orion_mpp_conf: requested MPP%u config "
54 "unavailable on this hardware\n", num);
55 continue;
56 }
57
58 shift = (num & 7) << 2;
59 mpp_ctrl[num / 8] &= ~(0xf << shift);
60 mpp_ctrl[num / 8] |= sel << shift;
61
62 gpio_mode = 0;
63 if (*mpp_list & MPP_INPUT_MASK)
64 gpio_mode |= GPIO_INPUT_OK;
65 if (*mpp_list & MPP_OUTPUT_MASK)
66 gpio_mode |= GPIO_OUTPUT_OK;
67 if (sel != 0)
68 gpio_mode = 0;
69 orion_gpio_set_valid(num, gpio_mode);
70 }
71
72 printk(KERN_DEBUG " final MPP regs:");
73 for (i = 0; i < mpp_nr_regs; i++) {
74 writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
75 printk(" %08x", mpp_ctrl[i]);
76 }
77 printk("\n");
78}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 17:09:52 -0500