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authorPaul Walmsley <paul@pwsan.com>2012-09-10 16:07:48 -0400
committerPaul Walmsley <paul@pwsan.com>2012-11-12 21:18:50 -0500
commit13a5b6228679456cbc47a8d50e6580063caf8058 (patch)
tree1a81bcdeb2cd2d2937bb4bee7c54f377dbd5b4fc
parent91c5b6d243d957deff3c265b2764e89a65879d69 (diff)
ARM: OMAP44xx: clock: drop obsolete clock data
Drop the now-obsolete OMAP44xx original OMAP clock data. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Mike Turquette <mturquette@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c3390
1 files changed, 0 insertions, 3390 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
deleted file mode 100644
index ef6d09e9a938..000000000000
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ /dev/null
@@ -1,3390 +0,0 @@
1/*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
24 */
25
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30
31#include "soc.h"
32#include "iomap.h"
33#include "clock.h"
34#include "clock44xx.h"
35#include "cm1_44xx.h"
36#include "cm2_44xx.h"
37#include "cm-regbits-44xx.h"
38#include "prm44xx.h"
39#include "prm-regbits-44xx.h"
40#include "control.h"
41#include "scrm44xx.h"
42
43/* OMAP4 modulemode control */
44#define OMAP4430_MODULEMODE_HWCTRL 0
45#define OMAP4430_MODULEMODE_SWCTRL 1
46
47/* Root clocks */
48
49static struct clk extalt_clkin_ck = {
50 .name = "extalt_clkin_ck",
51 .rate = 59000000,
52 .ops = &clkops_null,
53};
54
55static struct clk pad_clks_ck = {
56 .name = "pad_clks_ck",
57 .rate = 12000000,
58 .ops = &clkops_omap2_dflt,
59 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
60 .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
61};
62
63static struct clk pad_slimbus_core_clks_ck = {
64 .name = "pad_slimbus_core_clks_ck",
65 .rate = 12000000,
66 .ops = &clkops_null,
67};
68
69static struct clk secure_32k_clk_src_ck = {
70 .name = "secure_32k_clk_src_ck",
71 .rate = 32768,
72 .ops = &clkops_null,
73};
74
75static struct clk slimbus_clk = {
76 .name = "slimbus_clk",
77 .rate = 12000000,
78 .ops = &clkops_omap2_dflt,
79 .enable_reg = OMAP4430_CM_CLKSEL_ABE,
80 .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
81};
82
83static struct clk sys_32k_ck = {
84 .name = "sys_32k_ck",
85 .clkdm_name = "prm_clkdm",
86 .rate = 32768,
87 .ops = &clkops_null,
88};
89
90static struct clk virt_12000000_ck = {
91 .name = "virt_12000000_ck",
92 .ops = &clkops_null,
93 .rate = 12000000,
94};
95
96static struct clk virt_13000000_ck = {
97 .name = "virt_13000000_ck",
98 .ops = &clkops_null,
99 .rate = 13000000,
100};
101
102static struct clk virt_16800000_ck = {
103 .name = "virt_16800000_ck",
104 .ops = &clkops_null,
105 .rate = 16800000,
106};
107
108static struct clk virt_27000000_ck = {
109 .name = "virt_27000000_ck",
110 .ops = &clkops_null,
111 .rate = 27000000,
112};
113
114static struct clk virt_38400000_ck = {
115 .name = "virt_38400000_ck",
116 .ops = &clkops_null,
117 .rate = 38400000,
118};
119
120static const struct clksel_rate div_1_5_rates[] = {
121 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
122 { .div = 0 },
123};
124
125static const struct clksel_rate div_1_6_rates[] = {
126 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
127 { .div = 0 },
128};
129
130static const struct clksel_rate div_1_7_rates[] = {
131 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
132 { .div = 0 },
133};
134
135static const struct clksel sys_clkin_sel[] = {
136 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
137 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
138 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
139 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
140 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
141 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
142 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
143 { .parent = NULL },
144};
145
146static struct clk sys_clkin_ck = {
147 .name = "sys_clkin_ck",
148 .rate = 38400000,
149 .clksel = sys_clkin_sel,
150 .init = &omap2_init_clksel_parent,
151 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
152 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
153 .ops = &clkops_null,
154 .recalc = &omap2_clksel_recalc,
155};
156
157static struct clk tie_low_clock_ck = {
158 .name = "tie_low_clock_ck",
159 .rate = 0,
160 .ops = &clkops_null,
161};
162
163static struct clk utmi_phy_clkout_ck = {
164 .name = "utmi_phy_clkout_ck",
165 .rate = 60000000,
166 .ops = &clkops_null,
167};
168
169static struct clk xclk60mhsp1_ck = {
170 .name = "xclk60mhsp1_ck",
171 .rate = 60000000,
172 .ops = &clkops_null,
173};
174
175static struct clk xclk60mhsp2_ck = {
176 .name = "xclk60mhsp2_ck",
177 .rate = 60000000,
178 .ops = &clkops_null,
179};
180
181static struct clk xclk60motg_ck = {
182 .name = "xclk60motg_ck",
183 .rate = 60000000,
184 .ops = &clkops_null,
185};
186
187/* Module clocks and DPLL outputs */
188
189static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
190 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
191 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
192 { .parent = NULL },
193};
194
195static struct clk abe_dpll_bypass_clk_mux_ck = {
196 .name = "abe_dpll_bypass_clk_mux_ck",
197 .parent = &sys_clkin_ck,
198 .ops = &clkops_null,
199 .recalc = &followparent_recalc,
200};
201
202static struct clk abe_dpll_refclk_mux_ck = {
203 .name = "abe_dpll_refclk_mux_ck",
204 .parent = &sys_clkin_ck,
205 .clksel = abe_dpll_bypass_clk_mux_sel,
206 .init = &omap2_init_clksel_parent,
207 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
208 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
209 .ops = &clkops_null,
210 .recalc = &omap2_clksel_recalc,
211};
212
213/* DPLL_ABE */
214static struct dpll_data dpll_abe_dd = {
215 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
216 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
217 .clk_ref = &abe_dpll_refclk_mux_ck,
218 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
219 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
220 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
221 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
222 .mult_mask = OMAP4430_DPLL_MULT_MASK,
223 .div1_mask = OMAP4430_DPLL_DIV_MASK,
224 .enable_mask = OMAP4430_DPLL_EN_MASK,
225 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
226 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
227 .max_multiplier = 2047,
228 .max_divider = 128,
229 .min_divider = 1,
230};
231
232
233static struct clk dpll_abe_ck = {
234 .name = "dpll_abe_ck",
235 .parent = &abe_dpll_refclk_mux_ck,
236 .dpll_data = &dpll_abe_dd,
237 .init = &omap2_init_dpll_parent,
238 .ops = &clkops_omap3_noncore_dpll_ops,
239 .recalc = &omap4_dpll_regm4xen_recalc,
240 .round_rate = &omap4_dpll_regm4xen_round_rate,
241 .set_rate = &omap3_noncore_dpll_set_rate,
242};
243
244static struct clk dpll_abe_x2_ck = {
245 .name = "dpll_abe_x2_ck",
246 .parent = &dpll_abe_ck,
247 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
248 .flags = CLOCK_CLKOUTX2,
249 .ops = &clkops_omap4_dpllmx_ops,
250 .recalc = &omap3_clkoutx2_recalc,
251};
252
253static const struct clksel dpll_abe_m2x2_div[] = {
254 { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
255 { .parent = NULL },
256};
257
258static struct clk dpll_abe_m2x2_ck = {
259 .name = "dpll_abe_m2x2_ck",
260 .parent = &dpll_abe_x2_ck,
261 .clksel = dpll_abe_m2x2_div,
262 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
263 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
264 .ops = &clkops_omap4_dpllmx_ops,
265 .recalc = &omap2_clksel_recalc,
266 .round_rate = &omap2_clksel_round_rate,
267 .set_rate = &omap2_clksel_set_rate,
268};
269
270static struct clk abe_24m_fclk = {
271 .name = "abe_24m_fclk",
272 .parent = &dpll_abe_m2x2_ck,
273 .ops = &clkops_null,
274 .fixed_div = 8,
275 .recalc = &omap_fixed_divisor_recalc,
276};
277
278static const struct clksel abe_clk_div[] = {
279 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
280 { .parent = NULL },
281};
282
283static struct clk abe_clk = {
284 .name = "abe_clk",
285 .parent = &dpll_abe_m2x2_ck,
286 .clksel = abe_clk_div,
287 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
288 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
289 .ops = &clkops_null,
290 .recalc = &omap2_clksel_recalc,
291 .round_rate = &omap2_clksel_round_rate,
292 .set_rate = &omap2_clksel_set_rate,
293};
294
295static const struct clksel_rate div2_1to2_rates[] = {
296 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
297 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
298 { .div = 0 },
299};
300
301static const struct clksel aess_fclk_div[] = {
302 { .parent = &abe_clk, .rates = div2_1to2_rates },
303 { .parent = NULL },
304};
305
306static struct clk aess_fclk = {
307 .name = "aess_fclk",
308 .parent = &abe_clk,
309 .clksel = aess_fclk_div,
310 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
311 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
312 .ops = &clkops_null,
313 .recalc = &omap2_clksel_recalc,
314 .round_rate = &omap2_clksel_round_rate,
315 .set_rate = &omap2_clksel_set_rate,
316};
317
318static struct clk dpll_abe_m3x2_ck = {
319 .name = "dpll_abe_m3x2_ck",
320 .parent = &dpll_abe_x2_ck,
321 .clksel = dpll_abe_m2x2_div,
322 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
323 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
324 .ops = &clkops_omap4_dpllmx_ops,
325 .recalc = &omap2_clksel_recalc,
326 .round_rate = &omap2_clksel_round_rate,
327 .set_rate = &omap2_clksel_set_rate,
328};
329
330static const struct clksel core_hsd_byp_clk_mux_sel[] = {
331 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
332 { .parent = &dpll_abe_m3x2_ck, .rates = div_1_1_rates },
333 { .parent = NULL },
334};
335
336static struct clk core_hsd_byp_clk_mux_ck = {
337 .name = "core_hsd_byp_clk_mux_ck",
338 .parent = &sys_clkin_ck,
339 .clksel = core_hsd_byp_clk_mux_sel,
340 .init = &omap2_init_clksel_parent,
341 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
342 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
343 .ops = &clkops_null,
344 .recalc = &omap2_clksel_recalc,
345};
346
347/* DPLL_CORE */
348static struct dpll_data dpll_core_dd = {
349 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
350 .clk_bypass = &core_hsd_byp_clk_mux_ck,
351 .clk_ref = &sys_clkin_ck,
352 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
353 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
354 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
355 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
356 .mult_mask = OMAP4430_DPLL_MULT_MASK,
357 .div1_mask = OMAP4430_DPLL_DIV_MASK,
358 .enable_mask = OMAP4430_DPLL_EN_MASK,
359 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
360 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
361 .max_multiplier = 2047,
362 .max_divider = 128,
363 .min_divider = 1,
364};
365
366
367static struct clk dpll_core_ck = {
368 .name = "dpll_core_ck",
369 .parent = &sys_clkin_ck,
370 .dpll_data = &dpll_core_dd,
371 .init = &omap2_init_dpll_parent,
372 .ops = &clkops_omap3_core_dpll_ops,
373 .recalc = &omap3_dpll_recalc,
374};
375
376static struct clk dpll_core_x2_ck = {
377 .name = "dpll_core_x2_ck",
378 .parent = &dpll_core_ck,
379 .flags = CLOCK_CLKOUTX2,
380 .ops = &clkops_null,
381 .recalc = &omap3_clkoutx2_recalc,
382};
383
384static const struct clksel dpll_core_m6x2_div[] = {
385 { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
386 { .parent = NULL },
387};
388
389static struct clk dpll_core_m6x2_ck = {
390 .name = "dpll_core_m6x2_ck",
391 .parent = &dpll_core_x2_ck,
392 .clksel = dpll_core_m6x2_div,
393 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
394 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
395 .ops = &clkops_omap4_dpllmx_ops,
396 .recalc = &omap2_clksel_recalc,
397 .round_rate = &omap2_clksel_round_rate,
398 .set_rate = &omap2_clksel_set_rate,
399};
400
401static const struct clksel dbgclk_mux_sel[] = {
402 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
403 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
404 { .parent = NULL },
405};
406
407static struct clk dbgclk_mux_ck = {
408 .name = "dbgclk_mux_ck",
409 .parent = &sys_clkin_ck,
410 .ops = &clkops_null,
411 .recalc = &followparent_recalc,
412};
413
414static const struct clksel dpll_core_m2_div[] = {
415 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
416 { .parent = NULL },
417};
418
419static struct clk dpll_core_m2_ck = {
420 .name = "dpll_core_m2_ck",
421 .parent = &dpll_core_ck,
422 .clksel = dpll_core_m2_div,
423 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
424 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
425 .ops = &clkops_omap4_dpllmx_ops,
426 .recalc = &omap2_clksel_recalc,
427 .round_rate = &omap2_clksel_round_rate,
428 .set_rate = &omap2_clksel_set_rate,
429};
430
431static struct clk ddrphy_ck = {
432 .name = "ddrphy_ck",
433 .parent = &dpll_core_m2_ck,
434 .ops = &clkops_null,
435 .clkdm_name = "l3_emif_clkdm",
436 .fixed_div = 2,
437 .recalc = &omap_fixed_divisor_recalc,
438};
439
440static struct clk dpll_core_m5x2_ck = {
441 .name = "dpll_core_m5x2_ck",
442 .parent = &dpll_core_x2_ck,
443 .clksel = dpll_core_m6x2_div,
444 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
445 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
446 .ops = &clkops_omap4_dpllmx_ops,
447 .recalc = &omap2_clksel_recalc,
448 .round_rate = &omap2_clksel_round_rate,
449 .set_rate = &omap2_clksel_set_rate,
450};
451
452static const struct clksel div_core_div[] = {
453 { .parent = &dpll_core_m5x2_ck, .rates = div2_1to2_rates },
454 { .parent = NULL },
455};
456
457static struct clk div_core_ck = {
458 .name = "div_core_ck",
459 .parent = &dpll_core_m5x2_ck,
460 .clksel = div_core_div,
461 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
462 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
463 .ops = &clkops_null,
464 .recalc = &omap2_clksel_recalc,
465 .round_rate = &omap2_clksel_round_rate,
466 .set_rate = &omap2_clksel_set_rate,
467};
468
469static const struct clksel_rate div4_1to8_rates[] = {
470 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
471 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
472 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
473 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
474 { .div = 0 },
475};
476
477static const struct clksel div_iva_hs_clk_div[] = {
478 { .parent = &dpll_core_m5x2_ck, .rates = div4_1to8_rates },
479 { .parent = NULL },
480};
481
482static struct clk div_iva_hs_clk = {
483 .name = "div_iva_hs_clk",
484 .parent = &dpll_core_m5x2_ck,
485 .clksel = div_iva_hs_clk_div,
486 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
487 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
488 .ops = &clkops_null,
489 .recalc = &omap2_clksel_recalc,
490 .round_rate = &omap2_clksel_round_rate,
491 .set_rate = &omap2_clksel_set_rate,
492};
493
494static struct clk div_mpu_hs_clk = {
495 .name = "div_mpu_hs_clk",
496 .parent = &dpll_core_m5x2_ck,
497 .clksel = div_iva_hs_clk_div,
498 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
499 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
500 .ops = &clkops_null,
501 .recalc = &omap2_clksel_recalc,
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap2_clksel_set_rate,
504};
505
506static struct clk dpll_core_m4x2_ck = {
507 .name = "dpll_core_m4x2_ck",
508 .parent = &dpll_core_x2_ck,
509 .clksel = dpll_core_m6x2_div,
510 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
511 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
512 .ops = &clkops_omap4_dpllmx_ops,
513 .recalc = &omap2_clksel_recalc,
514 .round_rate = &omap2_clksel_round_rate,
515 .set_rate = &omap2_clksel_set_rate,
516};
517
518static struct clk dll_clk_div_ck = {
519 .name = "dll_clk_div_ck",
520 .parent = &dpll_core_m4x2_ck,
521 .ops = &clkops_null,
522 .fixed_div = 2,
523 .recalc = &omap_fixed_divisor_recalc,
524};
525
526static const struct clksel dpll_abe_m2_div[] = {
527 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
528 { .parent = NULL },
529};
530
531static struct clk dpll_abe_m2_ck = {
532 .name = "dpll_abe_m2_ck",
533 .parent = &dpll_abe_ck,
534 .clksel = dpll_abe_m2_div,
535 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
536 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
537 .ops = &clkops_omap4_dpllmx_ops,
538 .recalc = &omap2_clksel_recalc,
539 .round_rate = &omap2_clksel_round_rate,
540 .set_rate = &omap2_clksel_set_rate,
541};
542
543static struct clk dpll_core_m3x2_ck = {
544 .name = "dpll_core_m3x2_ck",
545 .parent = &dpll_core_x2_ck,
546 .clksel = dpll_core_m6x2_div,
547 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
548 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
549 .ops = &clkops_omap2_dflt,
550 .recalc = &omap2_clksel_recalc,
551 .round_rate = &omap2_clksel_round_rate,
552 .set_rate = &omap2_clksel_set_rate,
553 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
554 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
555};
556
557static struct clk dpll_core_m7x2_ck = {
558 .name = "dpll_core_m7x2_ck",
559 .parent = &dpll_core_x2_ck,
560 .clksel = dpll_core_m6x2_div,
561 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
562 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
563 .ops = &clkops_omap4_dpllmx_ops,
564 .recalc = &omap2_clksel_recalc,
565 .round_rate = &omap2_clksel_round_rate,
566 .set_rate = &omap2_clksel_set_rate,
567};
568
569static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
570 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
571 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
572 { .parent = NULL },
573};
574
575static struct clk iva_hsd_byp_clk_mux_ck = {
576 .name = "iva_hsd_byp_clk_mux_ck",
577 .parent = &sys_clkin_ck,
578 .clksel = iva_hsd_byp_clk_mux_sel,
579 .init = &omap2_init_clksel_parent,
580 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
581 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
582 .ops = &clkops_null,
583 .recalc = &omap2_clksel_recalc,
584};
585
586/* DPLL_IVA */
587static struct dpll_data dpll_iva_dd = {
588 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
589 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
590 .clk_ref = &sys_clkin_ck,
591 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
592 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
593 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
594 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
595 .mult_mask = OMAP4430_DPLL_MULT_MASK,
596 .div1_mask = OMAP4430_DPLL_DIV_MASK,
597 .enable_mask = OMAP4430_DPLL_EN_MASK,
598 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
599 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
600 .max_multiplier = 2047,
601 .max_divider = 128,
602 .min_divider = 1,
603};
604
605
606static struct clk dpll_iva_ck = {
607 .name = "dpll_iva_ck",
608 .parent = &sys_clkin_ck,
609 .dpll_data = &dpll_iva_dd,
610 .init = &omap2_init_dpll_parent,
611 .ops = &clkops_omap3_noncore_dpll_ops,
612 .recalc = &omap3_dpll_recalc,
613 .round_rate = &omap2_dpll_round_rate,
614 .set_rate = &omap3_noncore_dpll_set_rate,
615};
616
617static struct clk dpll_iva_x2_ck = {
618 .name = "dpll_iva_x2_ck",
619 .parent = &dpll_iva_ck,
620 .flags = CLOCK_CLKOUTX2,
621 .ops = &clkops_null,
622 .recalc = &omap3_clkoutx2_recalc,
623};
624
625static const struct clksel dpll_iva_m4x2_div[] = {
626 { .parent = &dpll_iva_x2_ck, .rates = div31_1to31_rates },
627 { .parent = NULL },
628};
629
630static struct clk dpll_iva_m4x2_ck = {
631 .name = "dpll_iva_m4x2_ck",
632 .parent = &dpll_iva_x2_ck,
633 .clksel = dpll_iva_m4x2_div,
634 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
635 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
636 .ops = &clkops_omap4_dpllmx_ops,
637 .recalc = &omap2_clksel_recalc,
638 .round_rate = &omap2_clksel_round_rate,
639 .set_rate = &omap2_clksel_set_rate,
640};
641
642static struct clk dpll_iva_m5x2_ck = {
643 .name = "dpll_iva_m5x2_ck",
644 .parent = &dpll_iva_x2_ck,
645 .clksel = dpll_iva_m4x2_div,
646 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
647 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
648 .ops = &clkops_omap4_dpllmx_ops,
649 .recalc = &omap2_clksel_recalc,
650 .round_rate = &omap2_clksel_round_rate,
651 .set_rate = &omap2_clksel_set_rate,
652};
653
654/* DPLL_MPU */
655static struct dpll_data dpll_mpu_dd = {
656 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
657 .clk_bypass = &div_mpu_hs_clk,
658 .clk_ref = &sys_clkin_ck,
659 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
660 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
661 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
662 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
663 .mult_mask = OMAP4430_DPLL_MULT_MASK,
664 .div1_mask = OMAP4430_DPLL_DIV_MASK,
665 .enable_mask = OMAP4430_DPLL_EN_MASK,
666 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
667 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
668 .max_multiplier = 2047,
669 .max_divider = 128,
670 .min_divider = 1,
671};
672
673static struct clk dpll_mpu_ck = {
674 .name = "dpll_mpu_ck",
675 .parent = &sys_clkin_ck,
676 .dpll_data = &dpll_mpu_dd,
677 .init = &omap2_init_dpll_parent,
678 .ops = &clkops_omap3_noncore_dpll_ops,
679 .recalc = &omap3_dpll_recalc,
680 .round_rate = &omap2_dpll_round_rate,
681 .set_rate = &omap3_noncore_dpll_set_rate,
682};
683
684static const struct clksel dpll_mpu_m2_div[] = {
685 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
686 { .parent = NULL },
687};
688
689static struct clk dpll_mpu_m2_ck = {
690 .name = "dpll_mpu_m2_ck",
691 .parent = &dpll_mpu_ck,
692 .clkdm_name = "cm_clkdm",
693 .clksel = dpll_mpu_m2_div,
694 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
695 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
696 .ops = &clkops_omap4_dpllmx_ops,
697 .recalc = &omap2_clksel_recalc,
698 .round_rate = &omap2_clksel_round_rate,
699 .set_rate = &omap2_clksel_set_rate,
700};
701
702static struct clk per_hs_clk_div_ck = {
703 .name = "per_hs_clk_div_ck",
704 .parent = &dpll_abe_m3x2_ck,
705 .ops = &clkops_null,
706 .fixed_div = 2,
707 .recalc = &omap_fixed_divisor_recalc,
708};
709
710static const struct clksel per_hsd_byp_clk_mux_sel[] = {
711 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
712 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
713 { .parent = NULL },
714};
715
716static struct clk per_hsd_byp_clk_mux_ck = {
717 .name = "per_hsd_byp_clk_mux_ck",
718 .parent = &sys_clkin_ck,
719 .clksel = per_hsd_byp_clk_mux_sel,
720 .init = &omap2_init_clksel_parent,
721 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
722 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
723 .ops = &clkops_null,
724 .recalc = &omap2_clksel_recalc,
725};
726
727/* DPLL_PER */
728static struct dpll_data dpll_per_dd = {
729 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
730 .clk_bypass = &per_hsd_byp_clk_mux_ck,
731 .clk_ref = &sys_clkin_ck,
732 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
733 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
734 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
735 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
736 .mult_mask = OMAP4430_DPLL_MULT_MASK,
737 .div1_mask = OMAP4430_DPLL_DIV_MASK,
738 .enable_mask = OMAP4430_DPLL_EN_MASK,
739 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
740 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
741 .max_multiplier = 2047,
742 .max_divider = 128,
743 .min_divider = 1,
744};
745
746
747static struct clk dpll_per_ck = {
748 .name = "dpll_per_ck",
749 .parent = &sys_clkin_ck,
750 .dpll_data = &dpll_per_dd,
751 .init = &omap2_init_dpll_parent,
752 .ops = &clkops_omap3_noncore_dpll_ops,
753 .recalc = &omap3_dpll_recalc,
754 .round_rate = &omap2_dpll_round_rate,
755 .set_rate = &omap3_noncore_dpll_set_rate,
756};
757
758static const struct clksel dpll_per_m2_div[] = {
759 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
760 { .parent = NULL },
761};
762
763static struct clk dpll_per_m2_ck = {
764 .name = "dpll_per_m2_ck",
765 .parent = &dpll_per_ck,
766 .clksel = dpll_per_m2_div,
767 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
768 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
769 .ops = &clkops_omap4_dpllmx_ops,
770 .recalc = &omap2_clksel_recalc,
771 .round_rate = &omap2_clksel_round_rate,
772 .set_rate = &omap2_clksel_set_rate,
773};
774
775static struct clk dpll_per_x2_ck = {
776 .name = "dpll_per_x2_ck",
777 .parent = &dpll_per_ck,
778 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
779 .flags = CLOCK_CLKOUTX2,
780 .ops = &clkops_omap4_dpllmx_ops,
781 .recalc = &omap3_clkoutx2_recalc,
782};
783
784static const struct clksel dpll_per_m2x2_div[] = {
785 { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
786 { .parent = NULL },
787};
788
789static struct clk dpll_per_m2x2_ck = {
790 .name = "dpll_per_m2x2_ck",
791 .parent = &dpll_per_x2_ck,
792 .clksel = dpll_per_m2x2_div,
793 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
794 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
795 .ops = &clkops_omap4_dpllmx_ops,
796 .recalc = &omap2_clksel_recalc,
797 .round_rate = &omap2_clksel_round_rate,
798 .set_rate = &omap2_clksel_set_rate,
799};
800
801static struct clk dpll_per_m3x2_ck = {
802 .name = "dpll_per_m3x2_ck",
803 .parent = &dpll_per_x2_ck,
804 .clksel = dpll_per_m2x2_div,
805 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
806 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
807 .ops = &clkops_omap2_dflt,
808 .recalc = &omap2_clksel_recalc,
809 .round_rate = &omap2_clksel_round_rate,
810 .set_rate = &omap2_clksel_set_rate,
811 .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
812 .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
813};
814
815static struct clk dpll_per_m4x2_ck = {
816 .name = "dpll_per_m4x2_ck",
817 .parent = &dpll_per_x2_ck,
818 .clksel = dpll_per_m2x2_div,
819 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
820 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
821 .ops = &clkops_omap4_dpllmx_ops,
822 .recalc = &omap2_clksel_recalc,
823 .round_rate = &omap2_clksel_round_rate,
824 .set_rate = &omap2_clksel_set_rate,
825};
826
827static struct clk dpll_per_m5x2_ck = {
828 .name = "dpll_per_m5x2_ck",
829 .parent = &dpll_per_x2_ck,
830 .clksel = dpll_per_m2x2_div,
831 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
832 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
833 .ops = &clkops_omap4_dpllmx_ops,
834 .recalc = &omap2_clksel_recalc,
835 .round_rate = &omap2_clksel_round_rate,
836 .set_rate = &omap2_clksel_set_rate,
837};
838
839static struct clk dpll_per_m6x2_ck = {
840 .name = "dpll_per_m6x2_ck",
841 .parent = &dpll_per_x2_ck,
842 .clksel = dpll_per_m2x2_div,
843 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
844 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
845 .ops = &clkops_omap4_dpllmx_ops,
846 .recalc = &omap2_clksel_recalc,
847 .round_rate = &omap2_clksel_round_rate,
848 .set_rate = &omap2_clksel_set_rate,
849};
850
851static struct clk dpll_per_m7x2_ck = {
852 .name = "dpll_per_m7x2_ck",
853 .parent = &dpll_per_x2_ck,
854 .clksel = dpll_per_m2x2_div,
855 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
856 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
857 .ops = &clkops_omap4_dpllmx_ops,
858 .recalc = &omap2_clksel_recalc,
859 .round_rate = &omap2_clksel_round_rate,
860 .set_rate = &omap2_clksel_set_rate,
861};
862
863static struct clk usb_hs_clk_div_ck = {
864 .name = "usb_hs_clk_div_ck",
865 .parent = &dpll_abe_m3x2_ck,
866 .ops = &clkops_null,
867 .fixed_div = 3,
868 .recalc = &omap_fixed_divisor_recalc,
869};
870
871/* DPLL_USB */
872static struct dpll_data dpll_usb_dd = {
873 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
874 .clk_bypass = &usb_hs_clk_div_ck,
875 .flags = DPLL_J_TYPE,
876 .clk_ref = &sys_clkin_ck,
877 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
878 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
879 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
880 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
881 .mult_mask = OMAP4430_DPLL_MULT_USB_MASK,
882 .div1_mask = OMAP4430_DPLL_DIV_0_7_MASK,
883 .enable_mask = OMAP4430_DPLL_EN_MASK,
884 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
885 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
886 .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
887 .max_multiplier = 4095,
888 .max_divider = 256,
889 .min_divider = 1,
890};
891
892
893static struct clk dpll_usb_ck = {
894 .name = "dpll_usb_ck",
895 .parent = &sys_clkin_ck,
896 .dpll_data = &dpll_usb_dd,
897 .init = &omap2_init_dpll_parent,
898 .ops = &clkops_omap3_noncore_dpll_ops,
899 .recalc = &omap3_dpll_recalc,
900 .round_rate = &omap2_dpll_round_rate,
901 .set_rate = &omap3_noncore_dpll_set_rate,
902 .clkdm_name = "l3_init_clkdm",
903};
904
905static struct clk dpll_usb_clkdcoldo_ck = {
906 .name = "dpll_usb_clkdcoldo_ck",
907 .parent = &dpll_usb_ck,
908 .clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
909 .ops = &clkops_omap4_dpllmx_ops,
910 .recalc = &followparent_recalc,
911};
912
913static const struct clksel dpll_usb_m2_div[] = {
914 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
915 { .parent = NULL },
916};
917
918static struct clk dpll_usb_m2_ck = {
919 .name = "dpll_usb_m2_ck",
920 .parent = &dpll_usb_ck,
921 .clksel = dpll_usb_m2_div,
922 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
923 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
924 .ops = &clkops_omap4_dpllmx_ops,
925 .recalc = &omap2_clksel_recalc,
926 .round_rate = &omap2_clksel_round_rate,
927 .set_rate = &omap2_clksel_set_rate,
928};
929
930static const struct clksel ducati_clk_mux_sel[] = {
931 { .parent = &div_core_ck, .rates = div_1_0_rates },
932 { .parent = &dpll_per_m6x2_ck, .rates = div_1_1_rates },
933 { .parent = NULL },
934};
935
936static struct clk ducati_clk_mux_ck = {
937 .name = "ducati_clk_mux_ck",
938 .parent = &div_core_ck,
939 .clksel = ducati_clk_mux_sel,
940 .init = &omap2_init_clksel_parent,
941 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
942 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
943 .ops = &clkops_null,
944 .recalc = &omap2_clksel_recalc,
945};
946
947static struct clk func_12m_fclk = {
948 .name = "func_12m_fclk",
949 .parent = &dpll_per_m2x2_ck,
950 .ops = &clkops_null,
951 .fixed_div = 16,
952 .recalc = &omap_fixed_divisor_recalc,
953};
954
955static struct clk func_24m_clk = {
956 .name = "func_24m_clk",
957 .parent = &dpll_per_m2_ck,
958 .ops = &clkops_null,
959 .fixed_div = 4,
960 .recalc = &omap_fixed_divisor_recalc,
961};
962
963static struct clk func_24mc_fclk = {
964 .name = "func_24mc_fclk",
965 .parent = &dpll_per_m2x2_ck,
966 .ops = &clkops_null,
967 .fixed_div = 8,
968 .recalc = &omap_fixed_divisor_recalc,
969};
970
971static const struct clksel_rate div2_4to8_rates[] = {
972 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
973 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
974 { .div = 0 },
975};
976
977static const struct clksel func_48m_fclk_div[] = {
978 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
979 { .parent = NULL },
980};
981
982static struct clk func_48m_fclk = {
983 .name = "func_48m_fclk",
984 .parent = &dpll_per_m2x2_ck,
985 .clksel = func_48m_fclk_div,
986 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
987 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
988 .ops = &clkops_null,
989 .recalc = &omap2_clksel_recalc,
990 .round_rate = &omap2_clksel_round_rate,
991 .set_rate = &omap2_clksel_set_rate,
992};
993
994static struct clk func_48mc_fclk = {
995 .name = "func_48mc_fclk",
996 .parent = &dpll_per_m2x2_ck,
997 .ops = &clkops_null,
998 .fixed_div = 4,
999 .recalc = &omap_fixed_divisor_recalc,
1000};
1001
1002static const struct clksel_rate div2_2to4_rates[] = {
1003 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1004 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1005 { .div = 0 },
1006};
1007
1008static const struct clksel func_64m_fclk_div[] = {
1009 { .parent = &dpll_per_m4x2_ck, .rates = div2_2to4_rates },
1010 { .parent = NULL },
1011};
1012
1013static struct clk func_64m_fclk = {
1014 .name = "func_64m_fclk",
1015 .parent = &dpll_per_m4x2_ck,
1016 .clksel = func_64m_fclk_div,
1017 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1018 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1019 .ops = &clkops_null,
1020 .recalc = &omap2_clksel_recalc,
1021 .round_rate = &omap2_clksel_round_rate,
1022 .set_rate = &omap2_clksel_set_rate,
1023};
1024
1025static const struct clksel func_96m_fclk_div[] = {
1026 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1027 { .parent = NULL },
1028};
1029
1030static struct clk func_96m_fclk = {
1031 .name = "func_96m_fclk",
1032 .parent = &dpll_per_m2x2_ck,
1033 .clksel = func_96m_fclk_div,
1034 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1035 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1036 .ops = &clkops_null,
1037 .recalc = &omap2_clksel_recalc,
1038 .round_rate = &omap2_clksel_round_rate,
1039 .set_rate = &omap2_clksel_set_rate,
1040};
1041
1042static const struct clksel_rate div2_1to8_rates[] = {
1043 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1044 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1045 { .div = 0 },
1046};
1047
1048static const struct clksel init_60m_fclk_div[] = {
1049 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1050 { .parent = NULL },
1051};
1052
1053static struct clk init_60m_fclk = {
1054 .name = "init_60m_fclk",
1055 .parent = &dpll_usb_m2_ck,
1056 .clksel = init_60m_fclk_div,
1057 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1058 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1059 .ops = &clkops_null,
1060 .recalc = &omap2_clksel_recalc,
1061 .round_rate = &omap2_clksel_round_rate,
1062 .set_rate = &omap2_clksel_set_rate,
1063};
1064
1065static const struct clksel l3_div_div[] = {
1066 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1067 { .parent = NULL },
1068};
1069
1070static struct clk l3_div_ck = {
1071 .name = "l3_div_ck",
1072 .parent = &div_core_ck,
1073 .clkdm_name = "cm_clkdm",
1074 .clksel = l3_div_div,
1075 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1076 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1077 .ops = &clkops_null,
1078 .recalc = &omap2_clksel_recalc,
1079 .round_rate = &omap2_clksel_round_rate,
1080 .set_rate = &omap2_clksel_set_rate,
1081};
1082
1083static const struct clksel l4_div_div[] = {
1084 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1085 { .parent = NULL },
1086};
1087
1088static struct clk l4_div_ck = {
1089 .name = "l4_div_ck",
1090 .parent = &l3_div_ck,
1091 .clksel = l4_div_div,
1092 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1093 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1094 .ops = &clkops_null,
1095 .recalc = &omap2_clksel_recalc,
1096 .round_rate = &omap2_clksel_round_rate,
1097 .set_rate = &omap2_clksel_set_rate,
1098};
1099
1100static struct clk lp_clk_div_ck = {
1101 .name = "lp_clk_div_ck",
1102 .parent = &dpll_abe_m2x2_ck,
1103 .ops = &clkops_null,
1104 .fixed_div = 16,
1105 .recalc = &omap_fixed_divisor_recalc,
1106};
1107
1108static const struct clksel l4_wkup_clk_mux_sel[] = {
1109 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1110 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1111 { .parent = NULL },
1112};
1113
1114static struct clk l4_wkup_clk_mux_ck = {
1115 .name = "l4_wkup_clk_mux_ck",
1116 .parent = &sys_clkin_ck,
1117 .clksel = l4_wkup_clk_mux_sel,
1118 .init = &omap2_init_clksel_parent,
1119 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1120 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1121 .ops = &clkops_null,
1122 .recalc = &omap2_clksel_recalc,
1123};
1124
1125static const struct clksel_rate div2_2to1_rates[] = {
1126 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
1127 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1128 { .div = 0 },
1129};
1130
1131static const struct clksel ocp_abe_iclk_div[] = {
1132 { .parent = &aess_fclk, .rates = div2_2to1_rates },
1133 { .parent = NULL },
1134};
1135
1136static struct clk mpu_periphclk = {
1137 .name = "mpu_periphclk",
1138 .parent = &dpll_mpu_ck,
1139 .ops = &clkops_null,
1140 .fixed_div = 2,
1141 .recalc = &omap_fixed_divisor_recalc,
1142};
1143
1144static struct clk ocp_abe_iclk = {
1145 .name = "ocp_abe_iclk",
1146 .parent = &aess_fclk,
1147 .clksel = ocp_abe_iclk_div,
1148 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1149 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
1150 .ops = &clkops_null,
1151 .recalc = &omap2_clksel_recalc,
1152};
1153
1154static struct clk per_abe_24m_fclk = {
1155 .name = "per_abe_24m_fclk",
1156 .parent = &dpll_abe_m2_ck,
1157 .ops = &clkops_null,
1158 .fixed_div = 4,
1159 .recalc = &omap_fixed_divisor_recalc,
1160};
1161
1162static const struct clksel per_abe_nc_fclk_div[] = {
1163 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1164 { .parent = NULL },
1165};
1166
1167static struct clk per_abe_nc_fclk = {
1168 .name = "per_abe_nc_fclk",
1169 .parent = &dpll_abe_m2_ck,
1170 .clksel = per_abe_nc_fclk_div,
1171 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1172 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1173 .ops = &clkops_null,
1174 .recalc = &omap2_clksel_recalc,
1175 .round_rate = &omap2_clksel_round_rate,
1176 .set_rate = &omap2_clksel_set_rate,
1177};
1178
1179static const struct clksel pmd_stm_clock_mux_sel[] = {
1180 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1181 { .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
1182 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1183 { .parent = NULL },
1184};
1185
1186static struct clk pmd_stm_clock_mux_ck = {
1187 .name = "pmd_stm_clock_mux_ck",
1188 .parent = &sys_clkin_ck,
1189 .ops = &clkops_null,
1190 .recalc = &followparent_recalc,
1191};
1192
1193static struct clk pmd_trace_clk_mux_ck = {
1194 .name = "pmd_trace_clk_mux_ck",
1195 .parent = &sys_clkin_ck,
1196 .ops = &clkops_null,
1197 .recalc = &followparent_recalc,
1198};
1199
1200static const struct clksel syc_clk_div_div[] = {
1201 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1202 { .parent = NULL },
1203};
1204
1205static struct clk syc_clk_div_ck = {
1206 .name = "syc_clk_div_ck",
1207 .parent = &sys_clkin_ck,
1208 .clksel = syc_clk_div_div,
1209 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1210 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1211 .ops = &clkops_null,
1212 .recalc = &omap2_clksel_recalc,
1213 .round_rate = &omap2_clksel_round_rate,
1214 .set_rate = &omap2_clksel_set_rate,
1215};
1216
1217/* Leaf clocks controlled by modules */
1218
1219static struct clk aes1_fck = {
1220 .name = "aes1_fck",
1221 .ops = &clkops_omap2_dflt,
1222 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1223 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1224 .clkdm_name = "l4_secure_clkdm",
1225 .parent = &l3_div_ck,
1226 .recalc = &followparent_recalc,
1227};
1228
1229static struct clk aes2_fck = {
1230 .name = "aes2_fck",
1231 .ops = &clkops_omap2_dflt,
1232 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1233 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1234 .clkdm_name = "l4_secure_clkdm",
1235 .parent = &l3_div_ck,
1236 .recalc = &followparent_recalc,
1237};
1238
1239static struct clk aess_fck = {
1240 .name = "aess_fck",
1241 .ops = &clkops_omap2_dflt,
1242 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1243 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1244 .clkdm_name = "abe_clkdm",
1245 .parent = &aess_fclk,
1246 .recalc = &followparent_recalc,
1247};
1248
1249static struct clk bandgap_fclk = {
1250 .name = "bandgap_fclk",
1251 .ops = &clkops_omap2_dflt,
1252 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1253 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1254 .clkdm_name = "l4_wkup_clkdm",
1255 .parent = &sys_32k_ck,
1256 .recalc = &followparent_recalc,
1257};
1258
1259static struct clk des3des_fck = {
1260 .name = "des3des_fck",
1261 .ops = &clkops_omap2_dflt,
1262 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1263 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1264 .clkdm_name = "l4_secure_clkdm",
1265 .parent = &l4_div_ck,
1266 .recalc = &followparent_recalc,
1267};
1268
1269static const struct clksel dmic_sync_mux_sel[] = {
1270 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1271 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1272 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1273 { .parent = NULL },
1274};
1275
1276static struct clk dmic_sync_mux_ck = {
1277 .name = "dmic_sync_mux_ck",
1278 .parent = &abe_24m_fclk,
1279 .clksel = dmic_sync_mux_sel,
1280 .init = &omap2_init_clksel_parent,
1281 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1282 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1283 .ops = &clkops_null,
1284 .recalc = &omap2_clksel_recalc,
1285};
1286
1287static const struct clksel func_dmic_abe_gfclk_sel[] = {
1288 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1289 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1290 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1291 { .parent = NULL },
1292};
1293
1294/* Merged func_dmic_abe_gfclk into dmic */
1295static struct clk dmic_fck = {
1296 .name = "dmic_fck",
1297 .parent = &dmic_sync_mux_ck,
1298 .clksel = func_dmic_abe_gfclk_sel,
1299 .init = &omap2_init_clksel_parent,
1300 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1301 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1302 .ops = &clkops_omap2_dflt,
1303 .recalc = &omap2_clksel_recalc,
1304 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1305 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1306 .clkdm_name = "abe_clkdm",
1307};
1308
1309static struct clk dsp_fck = {
1310 .name = "dsp_fck",
1311 .ops = &clkops_omap2_dflt,
1312 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1313 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1314 .clkdm_name = "tesla_clkdm",
1315 .parent = &dpll_iva_m4x2_ck,
1316 .recalc = &followparent_recalc,
1317};
1318
1319static struct clk dss_sys_clk = {
1320 .name = "dss_sys_clk",
1321 .ops = &clkops_omap2_dflt,
1322 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1323 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1324 .clkdm_name = "l3_dss_clkdm",
1325 .parent = &syc_clk_div_ck,
1326 .recalc = &followparent_recalc,
1327};
1328
1329static struct clk dss_tv_clk = {
1330 .name = "dss_tv_clk",
1331 .ops = &clkops_omap2_dflt,
1332 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1333 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1334 .clkdm_name = "l3_dss_clkdm",
1335 .parent = &extalt_clkin_ck,
1336 .recalc = &followparent_recalc,
1337};
1338
1339static struct clk dss_dss_clk = {
1340 .name = "dss_dss_clk",
1341 .ops = &clkops_omap2_dflt,
1342 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1343 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1344 .clkdm_name = "l3_dss_clkdm",
1345 .parent = &dpll_per_m5x2_ck,
1346 .recalc = &followparent_recalc,
1347};
1348
1349static const struct clksel_rate div3_8to32_rates[] = {
1350 { .div = 8, .val = 0, .flags = RATE_IN_4460 },
1351 { .div = 16, .val = 1, .flags = RATE_IN_4460 },
1352 { .div = 32, .val = 2, .flags = RATE_IN_4460 },
1353 { .div = 0 },
1354};
1355
1356static const struct clksel div_ts_div[] = {
1357 { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
1358 { .parent = NULL },
1359};
1360
1361static struct clk div_ts_ck = {
1362 .name = "div_ts_ck",
1363 .parent = &l4_wkup_clk_mux_ck,
1364 .clksel = div_ts_div,
1365 .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1366 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1367 .ops = &clkops_null,
1368 .recalc = &omap2_clksel_recalc,
1369 .round_rate = &omap2_clksel_round_rate,
1370 .set_rate = &omap2_clksel_set_rate,
1371};
1372
1373static struct clk bandgap_ts_fclk = {
1374 .name = "bandgap_ts_fclk",
1375 .ops = &clkops_omap2_dflt,
1376 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1377 .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
1378 .clkdm_name = "l4_wkup_clkdm",
1379 .parent = &div_ts_ck,
1380 .recalc = &followparent_recalc,
1381};
1382
1383static struct clk dss_48mhz_clk = {
1384 .name = "dss_48mhz_clk",
1385 .ops = &clkops_omap2_dflt,
1386 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1387 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1388 .clkdm_name = "l3_dss_clkdm",
1389 .parent = &func_48mc_fclk,
1390 .recalc = &followparent_recalc,
1391};
1392
1393static struct clk dss_fck = {
1394 .name = "dss_fck",
1395 .ops = &clkops_omap2_dflt,
1396 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1397 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1398 .clkdm_name = "l3_dss_clkdm",
1399 .parent = &l3_div_ck,
1400 .recalc = &followparent_recalc,
1401};
1402
1403static struct clk efuse_ctrl_cust_fck = {
1404 .name = "efuse_ctrl_cust_fck",
1405 .ops = &clkops_omap2_dflt,
1406 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1407 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1408 .clkdm_name = "l4_cefuse_clkdm",
1409 .parent = &sys_clkin_ck,
1410 .recalc = &followparent_recalc,
1411};
1412
1413static struct clk emif1_fck = {
1414 .name = "emif1_fck",
1415 .ops = &clkops_omap2_dflt,
1416 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1417 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1418 .flags = ENABLE_ON_INIT,
1419 .clkdm_name = "l3_emif_clkdm",
1420 .parent = &ddrphy_ck,
1421 .recalc = &followparent_recalc,
1422};
1423
1424static struct clk emif2_fck = {
1425 .name = "emif2_fck",
1426 .ops = &clkops_omap2_dflt,
1427 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1428 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1429 .flags = ENABLE_ON_INIT,
1430 .clkdm_name = "l3_emif_clkdm",
1431 .parent = &ddrphy_ck,
1432 .recalc = &followparent_recalc,
1433};
1434
1435static const struct clksel fdif_fclk_div[] = {
1436 { .parent = &dpll_per_m4x2_ck, .rates = div3_1to4_rates },
1437 { .parent = NULL },
1438};
1439
1440/* Merged fdif_fclk into fdif */
1441static struct clk fdif_fck = {
1442 .name = "fdif_fck",
1443 .parent = &dpll_per_m4x2_ck,
1444 .clksel = fdif_fclk_div,
1445 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1446 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1447 .ops = &clkops_omap2_dflt,
1448 .recalc = &omap2_clksel_recalc,
1449 .round_rate = &omap2_clksel_round_rate,
1450 .set_rate = &omap2_clksel_set_rate,
1451 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1452 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1453 .clkdm_name = "iss_clkdm",
1454};
1455
1456static struct clk fpka_fck = {
1457 .name = "fpka_fck",
1458 .ops = &clkops_omap2_dflt,
1459 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1460 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1461 .clkdm_name = "l4_secure_clkdm",
1462 .parent = &l4_div_ck,
1463 .recalc = &followparent_recalc,
1464};
1465
1466static struct clk gpio1_dbclk = {
1467 .name = "gpio1_dbclk",
1468 .ops = &clkops_omap2_dflt,
1469 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1470 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1471 .clkdm_name = "l4_wkup_clkdm",
1472 .parent = &sys_32k_ck,
1473 .recalc = &followparent_recalc,
1474};
1475
1476static struct clk gpio1_ick = {
1477 .name = "gpio1_ick",
1478 .ops = &clkops_omap2_dflt,
1479 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1480 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1481 .clkdm_name = "l4_wkup_clkdm",
1482 .parent = &l4_wkup_clk_mux_ck,
1483 .recalc = &followparent_recalc,
1484};
1485
1486static struct clk gpio2_dbclk = {
1487 .name = "gpio2_dbclk",
1488 .ops = &clkops_omap2_dflt,
1489 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1490 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1491 .clkdm_name = "l4_per_clkdm",
1492 .parent = &sys_32k_ck,
1493 .recalc = &followparent_recalc,
1494};
1495
1496static struct clk gpio2_ick = {
1497 .name = "gpio2_ick",
1498 .ops = &clkops_omap2_dflt,
1499 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1500 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1501 .clkdm_name = "l4_per_clkdm",
1502 .parent = &l4_div_ck,
1503 .recalc = &followparent_recalc,
1504};
1505
1506static struct clk gpio3_dbclk = {
1507 .name = "gpio3_dbclk",
1508 .ops = &clkops_omap2_dflt,
1509 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1510 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1511 .clkdm_name = "l4_per_clkdm",
1512 .parent = &sys_32k_ck,
1513 .recalc = &followparent_recalc,
1514};
1515
1516static struct clk gpio3_ick = {
1517 .name = "gpio3_ick",
1518 .ops = &clkops_omap2_dflt,
1519 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1520 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1521 .clkdm_name = "l4_per_clkdm",
1522 .parent = &l4_div_ck,
1523 .recalc = &followparent_recalc,
1524};
1525
1526static struct clk gpio4_dbclk = {
1527 .name = "gpio4_dbclk",
1528 .ops = &clkops_omap2_dflt,
1529 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1530 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1531 .clkdm_name = "l4_per_clkdm",
1532 .parent = &sys_32k_ck,
1533 .recalc = &followparent_recalc,
1534};
1535
1536static struct clk gpio4_ick = {
1537 .name = "gpio4_ick",
1538 .ops = &clkops_omap2_dflt,
1539 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1540 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1541 .clkdm_name = "l4_per_clkdm",
1542 .parent = &l4_div_ck,
1543 .recalc = &followparent_recalc,
1544};
1545
1546static struct clk gpio5_dbclk = {
1547 .name = "gpio5_dbclk",
1548 .ops = &clkops_omap2_dflt,
1549 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1550 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1551 .clkdm_name = "l4_per_clkdm",
1552 .parent = &sys_32k_ck,
1553 .recalc = &followparent_recalc,
1554};
1555
1556static struct clk gpio5_ick = {
1557 .name = "gpio5_ick",
1558 .ops = &clkops_omap2_dflt,
1559 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1560 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1561 .clkdm_name = "l4_per_clkdm",
1562 .parent = &l4_div_ck,
1563 .recalc = &followparent_recalc,
1564};
1565
1566static struct clk gpio6_dbclk = {
1567 .name = "gpio6_dbclk",
1568 .ops = &clkops_omap2_dflt,
1569 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1570 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1571 .clkdm_name = "l4_per_clkdm",
1572 .parent = &sys_32k_ck,
1573 .recalc = &followparent_recalc,
1574};
1575
1576static struct clk gpio6_ick = {
1577 .name = "gpio6_ick",
1578 .ops = &clkops_omap2_dflt,
1579 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1580 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1581 .clkdm_name = "l4_per_clkdm",
1582 .parent = &l4_div_ck,
1583 .recalc = &followparent_recalc,
1584};
1585
1586static struct clk gpmc_ick = {
1587 .name = "gpmc_ick",
1588 .ops = &clkops_omap2_dflt,
1589 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1590 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1591 .flags = ENABLE_ON_INIT,
1592 .clkdm_name = "l3_2_clkdm",
1593 .parent = &l3_div_ck,
1594 .recalc = &followparent_recalc,
1595};
1596
1597static const struct clksel sgx_clk_mux_sel[] = {
1598 { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
1599 { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
1600 { .parent = NULL },
1601};
1602
1603/* Merged sgx_clk_mux into gpu */
1604static struct clk gpu_fck = {
1605 .name = "gpu_fck",
1606 .parent = &dpll_core_m7x2_ck,
1607 .clksel = sgx_clk_mux_sel,
1608 .init = &omap2_init_clksel_parent,
1609 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1610 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1611 .ops = &clkops_omap2_dflt,
1612 .recalc = &omap2_clksel_recalc,
1613 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1614 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1615 .clkdm_name = "l3_gfx_clkdm",
1616};
1617
1618static struct clk hdq1w_fck = {
1619 .name = "hdq1w_fck",
1620 .ops = &clkops_omap2_dflt,
1621 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1622 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1623 .clkdm_name = "l4_per_clkdm",
1624 .parent = &func_12m_fclk,
1625 .recalc = &followparent_recalc,
1626};
1627
1628static const struct clksel hsi_fclk_div[] = {
1629 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1630 { .parent = NULL },
1631};
1632
1633/* Merged hsi_fclk into hsi */
1634static struct clk hsi_fck = {
1635 .name = "hsi_fck",
1636 .parent = &dpll_per_m2x2_ck,
1637 .clksel = hsi_fclk_div,
1638 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1639 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1640 .ops = &clkops_omap2_dflt,
1641 .recalc = &omap2_clksel_recalc,
1642 .round_rate = &omap2_clksel_round_rate,
1643 .set_rate = &omap2_clksel_set_rate,
1644 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1645 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1646 .clkdm_name = "l3_init_clkdm",
1647};
1648
1649static struct clk i2c1_fck = {
1650 .name = "i2c1_fck",
1651 .ops = &clkops_omap2_dflt,
1652 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1653 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1654 .clkdm_name = "l4_per_clkdm",
1655 .parent = &func_96m_fclk,
1656 .recalc = &followparent_recalc,
1657};
1658
1659static struct clk i2c2_fck = {
1660 .name = "i2c2_fck",
1661 .ops = &clkops_omap2_dflt,
1662 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1663 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1664 .clkdm_name = "l4_per_clkdm",
1665 .parent = &func_96m_fclk,
1666 .recalc = &followparent_recalc,
1667};
1668
1669static struct clk i2c3_fck = {
1670 .name = "i2c3_fck",
1671 .ops = &clkops_omap2_dflt,
1672 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1673 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1674 .clkdm_name = "l4_per_clkdm",
1675 .parent = &func_96m_fclk,
1676 .recalc = &followparent_recalc,
1677};
1678
1679static struct clk i2c4_fck = {
1680 .name = "i2c4_fck",
1681 .ops = &clkops_omap2_dflt,
1682 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1683 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1684 .clkdm_name = "l4_per_clkdm",
1685 .parent = &func_96m_fclk,
1686 .recalc = &followparent_recalc,
1687};
1688
1689static struct clk ipu_fck = {
1690 .name = "ipu_fck",
1691 .ops = &clkops_omap2_dflt,
1692 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1693 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1694 .clkdm_name = "ducati_clkdm",
1695 .parent = &ducati_clk_mux_ck,
1696 .recalc = &followparent_recalc,
1697};
1698
1699static struct clk iss_ctrlclk = {
1700 .name = "iss_ctrlclk",
1701 .ops = &clkops_omap2_dflt,
1702 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1703 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1704 .clkdm_name = "iss_clkdm",
1705 .parent = &func_96m_fclk,
1706 .recalc = &followparent_recalc,
1707};
1708
1709static struct clk iss_fck = {
1710 .name = "iss_fck",
1711 .ops = &clkops_omap2_dflt,
1712 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1713 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1714 .clkdm_name = "iss_clkdm",
1715 .parent = &ducati_clk_mux_ck,
1716 .recalc = &followparent_recalc,
1717};
1718
1719static struct clk iva_fck = {
1720 .name = "iva_fck",
1721 .ops = &clkops_omap2_dflt,
1722 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1723 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1724 .clkdm_name = "ivahd_clkdm",
1725 .parent = &dpll_iva_m5x2_ck,
1726 .recalc = &followparent_recalc,
1727};
1728
1729static struct clk kbd_fck = {
1730 .name = "kbd_fck",
1731 .ops = &clkops_omap2_dflt,
1732 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1733 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1734 .clkdm_name = "l4_wkup_clkdm",
1735 .parent = &sys_32k_ck,
1736 .recalc = &followparent_recalc,
1737};
1738
1739static struct clk l3_instr_ick = {
1740 .name = "l3_instr_ick",
1741 .ops = &clkops_omap2_dflt,
1742 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1743 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1744 .flags = ENABLE_ON_INIT,
1745 .clkdm_name = "l3_instr_clkdm",
1746 .parent = &l3_div_ck,
1747 .recalc = &followparent_recalc,
1748};
1749
1750static struct clk l3_main_3_ick = {
1751 .name = "l3_main_3_ick",
1752 .ops = &clkops_omap2_dflt,
1753 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1754 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1755 .flags = ENABLE_ON_INIT,
1756 .clkdm_name = "l3_instr_clkdm",
1757 .parent = &l3_div_ck,
1758 .recalc = &followparent_recalc,
1759};
1760
1761static struct clk mcasp_sync_mux_ck = {
1762 .name = "mcasp_sync_mux_ck",
1763 .parent = &abe_24m_fclk,
1764 .clksel = dmic_sync_mux_sel,
1765 .init = &omap2_init_clksel_parent,
1766 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1767 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1768 .ops = &clkops_null,
1769 .recalc = &omap2_clksel_recalc,
1770};
1771
1772static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1773 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1774 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1775 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1776 { .parent = NULL },
1777};
1778
1779/* Merged func_mcasp_abe_gfclk into mcasp */
1780static struct clk mcasp_fck = {
1781 .name = "mcasp_fck",
1782 .parent = &mcasp_sync_mux_ck,
1783 .clksel = func_mcasp_abe_gfclk_sel,
1784 .init = &omap2_init_clksel_parent,
1785 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1786 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1787 .ops = &clkops_omap2_dflt,
1788 .recalc = &omap2_clksel_recalc,
1789 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1790 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1791 .clkdm_name = "abe_clkdm",
1792};
1793
1794static struct clk mcbsp1_sync_mux_ck = {
1795 .name = "mcbsp1_sync_mux_ck",
1796 .parent = &abe_24m_fclk,
1797 .clksel = dmic_sync_mux_sel,
1798 .init = &omap2_init_clksel_parent,
1799 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1800 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1801 .ops = &clkops_null,
1802 .recalc = &omap2_clksel_recalc,
1803};
1804
1805static const struct clksel func_mcbsp1_gfclk_sel[] = {
1806 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1807 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1808 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1809 { .parent = NULL },
1810};
1811
1812/* Merged func_mcbsp1_gfclk into mcbsp1 */
1813static struct clk mcbsp1_fck = {
1814 .name = "mcbsp1_fck",
1815 .parent = &mcbsp1_sync_mux_ck,
1816 .clksel = func_mcbsp1_gfclk_sel,
1817 .init = &omap2_init_clksel_parent,
1818 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1819 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1820 .ops = &clkops_omap2_dflt,
1821 .recalc = &omap2_clksel_recalc,
1822 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1823 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1824 .clkdm_name = "abe_clkdm",
1825};
1826
1827static struct clk mcbsp2_sync_mux_ck = {
1828 .name = "mcbsp2_sync_mux_ck",
1829 .parent = &abe_24m_fclk,
1830 .clksel = dmic_sync_mux_sel,
1831 .init = &omap2_init_clksel_parent,
1832 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1833 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1834 .ops = &clkops_null,
1835 .recalc = &omap2_clksel_recalc,
1836};
1837
1838static const struct clksel func_mcbsp2_gfclk_sel[] = {
1839 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1840 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1841 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1842 { .parent = NULL },
1843};
1844
1845/* Merged func_mcbsp2_gfclk into mcbsp2 */
1846static struct clk mcbsp2_fck = {
1847 .name = "mcbsp2_fck",
1848 .parent = &mcbsp2_sync_mux_ck,
1849 .clksel = func_mcbsp2_gfclk_sel,
1850 .init = &omap2_init_clksel_parent,
1851 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1852 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1853 .ops = &clkops_omap2_dflt,
1854 .recalc = &omap2_clksel_recalc,
1855 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1856 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1857 .clkdm_name = "abe_clkdm",
1858};
1859
1860static struct clk mcbsp3_sync_mux_ck = {
1861 .name = "mcbsp3_sync_mux_ck",
1862 .parent = &abe_24m_fclk,
1863 .clksel = dmic_sync_mux_sel,
1864 .init = &omap2_init_clksel_parent,
1865 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1866 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1867 .ops = &clkops_null,
1868 .recalc = &omap2_clksel_recalc,
1869};
1870
1871static const struct clksel func_mcbsp3_gfclk_sel[] = {
1872 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1873 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1874 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1875 { .parent = NULL },
1876};
1877
1878/* Merged func_mcbsp3_gfclk into mcbsp3 */
1879static struct clk mcbsp3_fck = {
1880 .name = "mcbsp3_fck",
1881 .parent = &mcbsp3_sync_mux_ck,
1882 .clksel = func_mcbsp3_gfclk_sel,
1883 .init = &omap2_init_clksel_parent,
1884 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1885 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1886 .ops = &clkops_omap2_dflt,
1887 .recalc = &omap2_clksel_recalc,
1888 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1889 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1890 .clkdm_name = "abe_clkdm",
1891};
1892
1893static const struct clksel mcbsp4_sync_mux_sel[] = {
1894 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1895 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1896 { .parent = NULL },
1897};
1898
1899static struct clk mcbsp4_sync_mux_ck = {
1900 .name = "mcbsp4_sync_mux_ck",
1901 .parent = &func_96m_fclk,
1902 .clksel = mcbsp4_sync_mux_sel,
1903 .init = &omap2_init_clksel_parent,
1904 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1905 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1906 .ops = &clkops_null,
1907 .recalc = &omap2_clksel_recalc,
1908};
1909
1910static const struct clksel per_mcbsp4_gfclk_sel[] = {
1911 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1912 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1913 { .parent = NULL },
1914};
1915
1916/* Merged per_mcbsp4_gfclk into mcbsp4 */
1917static struct clk mcbsp4_fck = {
1918 .name = "mcbsp4_fck",
1919 .parent = &mcbsp4_sync_mux_ck,
1920 .clksel = per_mcbsp4_gfclk_sel,
1921 .init = &omap2_init_clksel_parent,
1922 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1923 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1924 .ops = &clkops_omap2_dflt,
1925 .recalc = &omap2_clksel_recalc,
1926 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1927 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1928 .clkdm_name = "l4_per_clkdm",
1929};
1930
1931static struct clk mcpdm_fck = {
1932 .name = "mcpdm_fck",
1933 .ops = &clkops_omap2_dflt,
1934 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1935 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1936 .clkdm_name = "abe_clkdm",
1937 .parent = &pad_clks_ck,
1938 .recalc = &followparent_recalc,
1939};
1940
1941static struct clk mcspi1_fck = {
1942 .name = "mcspi1_fck",
1943 .ops = &clkops_omap2_dflt,
1944 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1945 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1946 .clkdm_name = "l4_per_clkdm",
1947 .parent = &func_48m_fclk,
1948 .recalc = &followparent_recalc,
1949};
1950
1951static struct clk mcspi2_fck = {
1952 .name = "mcspi2_fck",
1953 .ops = &clkops_omap2_dflt,
1954 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1955 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1956 .clkdm_name = "l4_per_clkdm",
1957 .parent = &func_48m_fclk,
1958 .recalc = &followparent_recalc,
1959};
1960
1961static struct clk mcspi3_fck = {
1962 .name = "mcspi3_fck",
1963 .ops = &clkops_omap2_dflt,
1964 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1965 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1966 .clkdm_name = "l4_per_clkdm",
1967 .parent = &func_48m_fclk,
1968 .recalc = &followparent_recalc,
1969};
1970
1971static struct clk mcspi4_fck = {
1972 .name = "mcspi4_fck",
1973 .ops = &clkops_omap2_dflt,
1974 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1975 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1976 .clkdm_name = "l4_per_clkdm",
1977 .parent = &func_48m_fclk,
1978 .recalc = &followparent_recalc,
1979};
1980
1981static const struct clksel hsmmc1_fclk_sel[] = {
1982 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1983 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1984 { .parent = NULL },
1985};
1986
1987/* Merged hsmmc1_fclk into mmc1 */
1988static struct clk mmc1_fck = {
1989 .name = "mmc1_fck",
1990 .parent = &func_64m_fclk,
1991 .clksel = hsmmc1_fclk_sel,
1992 .init = &omap2_init_clksel_parent,
1993 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1994 .clksel_mask = OMAP4430_CLKSEL_MASK,
1995 .ops = &clkops_omap2_dflt,
1996 .recalc = &omap2_clksel_recalc,
1997 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1998 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1999 .clkdm_name = "l3_init_clkdm",
2000};
2001
2002/* Merged hsmmc2_fclk into mmc2 */
2003static struct clk mmc2_fck = {
2004 .name = "mmc2_fck",
2005 .parent = &func_64m_fclk,
2006 .clksel = hsmmc1_fclk_sel,
2007 .init = &omap2_init_clksel_parent,
2008 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2009 .clksel_mask = OMAP4430_CLKSEL_MASK,
2010 .ops = &clkops_omap2_dflt,
2011 .recalc = &omap2_clksel_recalc,
2012 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2013 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2014 .clkdm_name = "l3_init_clkdm",
2015};
2016
2017static struct clk mmc3_fck = {
2018 .name = "mmc3_fck",
2019 .ops = &clkops_omap2_dflt,
2020 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2021 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2022 .clkdm_name = "l4_per_clkdm",
2023 .parent = &func_48m_fclk,
2024 .recalc = &followparent_recalc,
2025};
2026
2027static struct clk mmc4_fck = {
2028 .name = "mmc4_fck",
2029 .ops = &clkops_omap2_dflt,
2030 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2031 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2032 .clkdm_name = "l4_per_clkdm",
2033 .parent = &func_48m_fclk,
2034 .recalc = &followparent_recalc,
2035};
2036
2037static struct clk mmc5_fck = {
2038 .name = "mmc5_fck",
2039 .ops = &clkops_omap2_dflt,
2040 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2041 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2042 .clkdm_name = "l4_per_clkdm",
2043 .parent = &func_48m_fclk,
2044 .recalc = &followparent_recalc,
2045};
2046
2047static struct clk ocp2scp_usb_phy_phy_48m = {
2048 .name = "ocp2scp_usb_phy_phy_48m",
2049 .ops = &clkops_omap2_dflt,
2050 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2051 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2052 .clkdm_name = "l3_init_clkdm",
2053 .parent = &func_48m_fclk,
2054 .recalc = &followparent_recalc,
2055};
2056
2057static struct clk ocp2scp_usb_phy_ick = {
2058 .name = "ocp2scp_usb_phy_ick",
2059 .ops = &clkops_omap2_dflt,
2060 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2061 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2062 .clkdm_name = "l3_init_clkdm",
2063 .parent = &l4_div_ck,
2064 .recalc = &followparent_recalc,
2065};
2066
2067static struct clk ocp_wp_noc_ick = {
2068 .name = "ocp_wp_noc_ick",
2069 .ops = &clkops_omap2_dflt,
2070 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2071 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2072 .flags = ENABLE_ON_INIT,
2073 .clkdm_name = "l3_instr_clkdm",
2074 .parent = &l3_div_ck,
2075 .recalc = &followparent_recalc,
2076};
2077
2078static struct clk rng_ick = {
2079 .name = "rng_ick",
2080 .ops = &clkops_omap2_dflt,
2081 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2082 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2083 .clkdm_name = "l4_secure_clkdm",
2084 .parent = &l4_div_ck,
2085 .recalc = &followparent_recalc,
2086};
2087
2088static struct clk sha2md5_fck = {
2089 .name = "sha2md5_fck",
2090 .ops = &clkops_omap2_dflt,
2091 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2092 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2093 .clkdm_name = "l4_secure_clkdm",
2094 .parent = &l3_div_ck,
2095 .recalc = &followparent_recalc,
2096};
2097
2098static struct clk sl2if_ick = {
2099 .name = "sl2if_ick",
2100 .ops = &clkops_omap2_dflt,
2101 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2102 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2103 .clkdm_name = "ivahd_clkdm",
2104 .parent = &dpll_iva_m5x2_ck,
2105 .recalc = &followparent_recalc,
2106};
2107
2108static struct clk slimbus1_fclk_1 = {
2109 .name = "slimbus1_fclk_1",
2110 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2112 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2113 .clkdm_name = "abe_clkdm",
2114 .parent = &func_24m_clk,
2115 .recalc = &followparent_recalc,
2116};
2117
2118static struct clk slimbus1_fclk_0 = {
2119 .name = "slimbus1_fclk_0",
2120 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2122 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2123 .clkdm_name = "abe_clkdm",
2124 .parent = &abe_24m_fclk,
2125 .recalc = &followparent_recalc,
2126};
2127
2128static struct clk slimbus1_fclk_2 = {
2129 .name = "slimbus1_fclk_2",
2130 .ops = &clkops_omap2_dflt,
2131 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2132 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2133 .clkdm_name = "abe_clkdm",
2134 .parent = &pad_clks_ck,
2135 .recalc = &followparent_recalc,
2136};
2137
2138static struct clk slimbus1_slimbus_clk = {
2139 .name = "slimbus1_slimbus_clk",
2140 .ops = &clkops_omap2_dflt,
2141 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2142 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2143 .clkdm_name = "abe_clkdm",
2144 .parent = &slimbus_clk,
2145 .recalc = &followparent_recalc,
2146};
2147
2148static struct clk slimbus1_fck = {
2149 .name = "slimbus1_fck",
2150 .ops = &clkops_omap2_dflt,
2151 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2152 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2153 .clkdm_name = "abe_clkdm",
2154 .parent = &ocp_abe_iclk,
2155 .recalc = &followparent_recalc,
2156};
2157
2158static struct clk slimbus2_fclk_1 = {
2159 .name = "slimbus2_fclk_1",
2160 .ops = &clkops_omap2_dflt,
2161 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2162 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2163 .clkdm_name = "l4_per_clkdm",
2164 .parent = &per_abe_24m_fclk,
2165 .recalc = &followparent_recalc,
2166};
2167
2168static struct clk slimbus2_fclk_0 = {
2169 .name = "slimbus2_fclk_0",
2170 .ops = &clkops_omap2_dflt,
2171 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2172 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2173 .clkdm_name = "l4_per_clkdm",
2174 .parent = &func_24mc_fclk,
2175 .recalc = &followparent_recalc,
2176};
2177
2178static struct clk slimbus2_slimbus_clk = {
2179 .name = "slimbus2_slimbus_clk",
2180 .ops = &clkops_omap2_dflt,
2181 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2182 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2183 .clkdm_name = "l4_per_clkdm",
2184 .parent = &pad_slimbus_core_clks_ck,
2185 .recalc = &followparent_recalc,
2186};
2187
2188static struct clk slimbus2_fck = {
2189 .name = "slimbus2_fck",
2190 .ops = &clkops_omap2_dflt,
2191 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2192 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2193 .clkdm_name = "l4_per_clkdm",
2194 .parent = &l4_div_ck,
2195 .recalc = &followparent_recalc,
2196};
2197
2198static struct clk smartreflex_core_fck = {
2199 .name = "smartreflex_core_fck",
2200 .ops = &clkops_omap2_dflt,
2201 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2202 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2203 .clkdm_name = "l4_ao_clkdm",
2204 .parent = &l4_wkup_clk_mux_ck,
2205 .recalc = &followparent_recalc,
2206};
2207
2208static struct clk smartreflex_iva_fck = {
2209 .name = "smartreflex_iva_fck",
2210 .ops = &clkops_omap2_dflt,
2211 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2212 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2213 .clkdm_name = "l4_ao_clkdm",
2214 .parent = &l4_wkup_clk_mux_ck,
2215 .recalc = &followparent_recalc,
2216};
2217
2218static struct clk smartreflex_mpu_fck = {
2219 .name = "smartreflex_mpu_fck",
2220 .ops = &clkops_omap2_dflt,
2221 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2222 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2223 .clkdm_name = "l4_ao_clkdm",
2224 .parent = &l4_wkup_clk_mux_ck,
2225 .recalc = &followparent_recalc,
2226};
2227
2228/* Merged dmt1_clk_mux into timer1 */
2229static struct clk timer1_fck = {
2230 .name = "timer1_fck",
2231 .parent = &sys_clkin_ck,
2232 .clksel = abe_dpll_bypass_clk_mux_sel,
2233 .init = &omap2_init_clksel_parent,
2234 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2235 .clksel_mask = OMAP4430_CLKSEL_MASK,
2236 .ops = &clkops_omap2_dflt,
2237 .recalc = &omap2_clksel_recalc,
2238 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2239 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2240 .clkdm_name = "l4_wkup_clkdm",
2241};
2242
2243/* Merged cm2_dm10_mux into timer10 */
2244static struct clk timer10_fck = {
2245 .name = "timer10_fck",
2246 .parent = &sys_clkin_ck,
2247 .clksel = abe_dpll_bypass_clk_mux_sel,
2248 .init = &omap2_init_clksel_parent,
2249 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2250 .clksel_mask = OMAP4430_CLKSEL_MASK,
2251 .ops = &clkops_omap2_dflt,
2252 .recalc = &omap2_clksel_recalc,
2253 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2254 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2255 .clkdm_name = "l4_per_clkdm",
2256};
2257
2258/* Merged cm2_dm11_mux into timer11 */
2259static struct clk timer11_fck = {
2260 .name = "timer11_fck",
2261 .parent = &sys_clkin_ck,
2262 .clksel = abe_dpll_bypass_clk_mux_sel,
2263 .init = &omap2_init_clksel_parent,
2264 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2265 .clksel_mask = OMAP4430_CLKSEL_MASK,
2266 .ops = &clkops_omap2_dflt,
2267 .recalc = &omap2_clksel_recalc,
2268 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2269 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2270 .clkdm_name = "l4_per_clkdm",
2271};
2272
2273/* Merged cm2_dm2_mux into timer2 */
2274static struct clk timer2_fck = {
2275 .name = "timer2_fck",
2276 .parent = &sys_clkin_ck,
2277 .clksel = abe_dpll_bypass_clk_mux_sel,
2278 .init = &omap2_init_clksel_parent,
2279 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2280 .clksel_mask = OMAP4430_CLKSEL_MASK,
2281 .ops = &clkops_omap2_dflt,
2282 .recalc = &omap2_clksel_recalc,
2283 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2284 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2285 .clkdm_name = "l4_per_clkdm",
2286};
2287
2288/* Merged cm2_dm3_mux into timer3 */
2289static struct clk timer3_fck = {
2290 .name = "timer3_fck",
2291 .parent = &sys_clkin_ck,
2292 .clksel = abe_dpll_bypass_clk_mux_sel,
2293 .init = &omap2_init_clksel_parent,
2294 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2295 .clksel_mask = OMAP4430_CLKSEL_MASK,
2296 .ops = &clkops_omap2_dflt,
2297 .recalc = &omap2_clksel_recalc,
2298 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2299 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2300 .clkdm_name = "l4_per_clkdm",
2301};
2302
2303/* Merged cm2_dm4_mux into timer4 */
2304static struct clk timer4_fck = {
2305 .name = "timer4_fck",
2306 .parent = &sys_clkin_ck,
2307 .clksel = abe_dpll_bypass_clk_mux_sel,
2308 .init = &omap2_init_clksel_parent,
2309 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2310 .clksel_mask = OMAP4430_CLKSEL_MASK,
2311 .ops = &clkops_omap2_dflt,
2312 .recalc = &omap2_clksel_recalc,
2313 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2314 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2315 .clkdm_name = "l4_per_clkdm",
2316};
2317
2318static const struct clksel timer5_sync_mux_sel[] = {
2319 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2320 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2321 { .parent = NULL },
2322};
2323
2324/* Merged timer5_sync_mux into timer5 */
2325static struct clk timer5_fck = {
2326 .name = "timer5_fck",
2327 .parent = &syc_clk_div_ck,
2328 .clksel = timer5_sync_mux_sel,
2329 .init = &omap2_init_clksel_parent,
2330 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2331 .clksel_mask = OMAP4430_CLKSEL_MASK,
2332 .ops = &clkops_omap2_dflt,
2333 .recalc = &omap2_clksel_recalc,
2334 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2335 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2336 .clkdm_name = "abe_clkdm",
2337};
2338
2339/* Merged timer6_sync_mux into timer6 */
2340static struct clk timer6_fck = {
2341 .name = "timer6_fck",
2342 .parent = &syc_clk_div_ck,
2343 .clksel = timer5_sync_mux_sel,
2344 .init = &omap2_init_clksel_parent,
2345 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2346 .clksel_mask = OMAP4430_CLKSEL_MASK,
2347 .ops = &clkops_omap2_dflt,
2348 .recalc = &omap2_clksel_recalc,
2349 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2350 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2351 .clkdm_name = "abe_clkdm",
2352};
2353
2354/* Merged timer7_sync_mux into timer7 */
2355static struct clk timer7_fck = {
2356 .name = "timer7_fck",
2357 .parent = &syc_clk_div_ck,
2358 .clksel = timer5_sync_mux_sel,
2359 .init = &omap2_init_clksel_parent,
2360 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2361 .clksel_mask = OMAP4430_CLKSEL_MASK,
2362 .ops = &clkops_omap2_dflt,
2363 .recalc = &omap2_clksel_recalc,
2364 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2365 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2366 .clkdm_name = "abe_clkdm",
2367};
2368
2369/* Merged timer8_sync_mux into timer8 */
2370static struct clk timer8_fck = {
2371 .name = "timer8_fck",
2372 .parent = &syc_clk_div_ck,
2373 .clksel = timer5_sync_mux_sel,
2374 .init = &omap2_init_clksel_parent,
2375 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2376 .clksel_mask = OMAP4430_CLKSEL_MASK,
2377 .ops = &clkops_omap2_dflt,
2378 .recalc = &omap2_clksel_recalc,
2379 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2380 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2381 .clkdm_name = "abe_clkdm",
2382};
2383
2384/* Merged cm2_dm9_mux into timer9 */
2385static struct clk timer9_fck = {
2386 .name = "timer9_fck",
2387 .parent = &sys_clkin_ck,
2388 .clksel = abe_dpll_bypass_clk_mux_sel,
2389 .init = &omap2_init_clksel_parent,
2390 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2391 .clksel_mask = OMAP4430_CLKSEL_MASK,
2392 .ops = &clkops_omap2_dflt,
2393 .recalc = &omap2_clksel_recalc,
2394 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2395 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2396 .clkdm_name = "l4_per_clkdm",
2397};
2398
2399static struct clk uart1_fck = {
2400 .name = "uart1_fck",
2401 .ops = &clkops_omap2_dflt,
2402 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2403 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2404 .clkdm_name = "l4_per_clkdm",
2405 .parent = &func_48m_fclk,
2406 .recalc = &followparent_recalc,
2407};
2408
2409static struct clk uart2_fck = {
2410 .name = "uart2_fck",
2411 .ops = &clkops_omap2_dflt,
2412 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2413 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2414 .clkdm_name = "l4_per_clkdm",
2415 .parent = &func_48m_fclk,
2416 .recalc = &followparent_recalc,
2417};
2418
2419static struct clk uart3_fck = {
2420 .name = "uart3_fck",
2421 .ops = &clkops_omap2_dflt,
2422 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2423 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2424 .clkdm_name = "l4_per_clkdm",
2425 .parent = &func_48m_fclk,
2426 .recalc = &followparent_recalc,
2427};
2428
2429static struct clk uart4_fck = {
2430 .name = "uart4_fck",
2431 .ops = &clkops_omap2_dflt,
2432 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2433 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2434 .clkdm_name = "l4_per_clkdm",
2435 .parent = &func_48m_fclk,
2436 .recalc = &followparent_recalc,
2437};
2438
2439static struct clk usb_host_fs_fck = {
2440 .name = "usb_host_fs_fck",
2441 .ops = &clkops_omap2_dflt,
2442 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2443 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2444 .clkdm_name = "l3_init_clkdm",
2445 .parent = &func_48mc_fclk,
2446 .recalc = &followparent_recalc,
2447};
2448
2449static const struct clksel utmi_p1_gfclk_sel[] = {
2450 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2451 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2452 { .parent = NULL },
2453};
2454
2455static struct clk utmi_p1_gfclk = {
2456 .name = "utmi_p1_gfclk",
2457 .parent = &init_60m_fclk,
2458 .clksel = utmi_p1_gfclk_sel,
2459 .init = &omap2_init_clksel_parent,
2460 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2461 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2462 .ops = &clkops_null,
2463 .recalc = &omap2_clksel_recalc,
2464};
2465
2466static struct clk usb_host_hs_utmi_p1_clk = {
2467 .name = "usb_host_hs_utmi_p1_clk",
2468 .ops = &clkops_omap2_dflt,
2469 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2470 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2471 .clkdm_name = "l3_init_clkdm",
2472 .parent = &utmi_p1_gfclk,
2473 .recalc = &followparent_recalc,
2474};
2475
2476static const struct clksel utmi_p2_gfclk_sel[] = {
2477 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2478 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2479 { .parent = NULL },
2480};
2481
2482static struct clk utmi_p2_gfclk = {
2483 .name = "utmi_p2_gfclk",
2484 .parent = &init_60m_fclk,
2485 .clksel = utmi_p2_gfclk_sel,
2486 .init = &omap2_init_clksel_parent,
2487 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2488 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2489 .ops = &clkops_null,
2490 .recalc = &omap2_clksel_recalc,
2491};
2492
2493static struct clk usb_host_hs_utmi_p2_clk = {
2494 .name = "usb_host_hs_utmi_p2_clk",
2495 .ops = &clkops_omap2_dflt,
2496 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2497 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2498 .clkdm_name = "l3_init_clkdm",
2499 .parent = &utmi_p2_gfclk,
2500 .recalc = &followparent_recalc,
2501};
2502
2503static struct clk usb_host_hs_utmi_p3_clk = {
2504 .name = "usb_host_hs_utmi_p3_clk",
2505 .ops = &clkops_omap2_dflt,
2506 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2507 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2508 .clkdm_name = "l3_init_clkdm",
2509 .parent = &init_60m_fclk,
2510 .recalc = &followparent_recalc,
2511};
2512
2513static struct clk usb_host_hs_hsic480m_p1_clk = {
2514 .name = "usb_host_hs_hsic480m_p1_clk",
2515 .ops = &clkops_omap2_dflt,
2516 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2517 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2518 .clkdm_name = "l3_init_clkdm",
2519 .parent = &dpll_usb_m2_ck,
2520 .recalc = &followparent_recalc,
2521};
2522
2523static struct clk usb_host_hs_hsic60m_p1_clk = {
2524 .name = "usb_host_hs_hsic60m_p1_clk",
2525 .ops = &clkops_omap2_dflt,
2526 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2527 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2528 .clkdm_name = "l3_init_clkdm",
2529 .parent = &init_60m_fclk,
2530 .recalc = &followparent_recalc,
2531};
2532
2533static struct clk usb_host_hs_hsic60m_p2_clk = {
2534 .name = "usb_host_hs_hsic60m_p2_clk",
2535 .ops = &clkops_omap2_dflt,
2536 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2537 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2538 .clkdm_name = "l3_init_clkdm",
2539 .parent = &init_60m_fclk,
2540 .recalc = &followparent_recalc,
2541};
2542
2543static struct clk usb_host_hs_hsic480m_p2_clk = {
2544 .name = "usb_host_hs_hsic480m_p2_clk",
2545 .ops = &clkops_omap2_dflt,
2546 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2547 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2548 .clkdm_name = "l3_init_clkdm",
2549 .parent = &dpll_usb_m2_ck,
2550 .recalc = &followparent_recalc,
2551};
2552
2553static struct clk usb_host_hs_func48mclk = {
2554 .name = "usb_host_hs_func48mclk",
2555 .ops = &clkops_omap2_dflt,
2556 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2557 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2558 .clkdm_name = "l3_init_clkdm",
2559 .parent = &func_48mc_fclk,
2560 .recalc = &followparent_recalc,
2561};
2562
2563static struct clk usb_host_hs_fck = {
2564 .name = "usb_host_hs_fck",
2565 .ops = &clkops_omap2_dflt,
2566 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2567 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2568 .clkdm_name = "l3_init_clkdm",
2569 .parent = &init_60m_fclk,
2570 .recalc = &followparent_recalc,
2571};
2572
2573static const struct clksel otg_60m_gfclk_sel[] = {
2574 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2575 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2576 { .parent = NULL },
2577};
2578
2579static struct clk otg_60m_gfclk = {
2580 .name = "otg_60m_gfclk",
2581 .parent = &utmi_phy_clkout_ck,
2582 .clksel = otg_60m_gfclk_sel,
2583 .init = &omap2_init_clksel_parent,
2584 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2585 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2586 .ops = &clkops_null,
2587 .recalc = &omap2_clksel_recalc,
2588};
2589
2590static struct clk usb_otg_hs_xclk = {
2591 .name = "usb_otg_hs_xclk",
2592 .ops = &clkops_omap2_dflt,
2593 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2594 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2595 .clkdm_name = "l3_init_clkdm",
2596 .parent = &otg_60m_gfclk,
2597 .recalc = &followparent_recalc,
2598};
2599
2600static struct clk usb_otg_hs_ick = {
2601 .name = "usb_otg_hs_ick",
2602 .ops = &clkops_omap2_dflt,
2603 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2604 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2605 .clkdm_name = "l3_init_clkdm",
2606 .parent = &l3_div_ck,
2607 .recalc = &followparent_recalc,
2608};
2609
2610static struct clk usb_phy_cm_clk32k = {
2611 .name = "usb_phy_cm_clk32k",
2612 .ops = &clkops_omap2_dflt,
2613 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2614 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2615 .clkdm_name = "l4_ao_clkdm",
2616 .parent = &sys_32k_ck,
2617 .recalc = &followparent_recalc,
2618};
2619
2620static struct clk usb_tll_hs_usb_ch2_clk = {
2621 .name = "usb_tll_hs_usb_ch2_clk",
2622 .ops = &clkops_omap2_dflt,
2623 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2624 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2625 .clkdm_name = "l3_init_clkdm",
2626 .parent = &init_60m_fclk,
2627 .recalc = &followparent_recalc,
2628};
2629
2630static struct clk usb_tll_hs_usb_ch0_clk = {
2631 .name = "usb_tll_hs_usb_ch0_clk",
2632 .ops = &clkops_omap2_dflt,
2633 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2634 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2635 .clkdm_name = "l3_init_clkdm",
2636 .parent = &init_60m_fclk,
2637 .recalc = &followparent_recalc,
2638};
2639
2640static struct clk usb_tll_hs_usb_ch1_clk = {
2641 .name = "usb_tll_hs_usb_ch1_clk",
2642 .ops = &clkops_omap2_dflt,
2643 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2644 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2645 .clkdm_name = "l3_init_clkdm",
2646 .parent = &init_60m_fclk,
2647 .recalc = &followparent_recalc,
2648};
2649
2650static struct clk usb_tll_hs_ick = {
2651 .name = "usb_tll_hs_ick",
2652 .ops = &clkops_omap2_dflt,
2653 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2654 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2655 .clkdm_name = "l3_init_clkdm",
2656 .parent = &l4_div_ck,
2657 .recalc = &followparent_recalc,
2658};
2659
2660static const struct clksel_rate div2_14to18_rates[] = {
2661 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2662 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2663 { .div = 0 },
2664};
2665
2666static const struct clksel usim_fclk_div[] = {
2667 { .parent = &dpll_per_m4x2_ck, .rates = div2_14to18_rates },
2668 { .parent = NULL },
2669};
2670
2671static struct clk usim_ck = {
2672 .name = "usim_ck",
2673 .parent = &dpll_per_m4x2_ck,
2674 .clksel = usim_fclk_div,
2675 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2676 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2677 .ops = &clkops_null,
2678 .recalc = &omap2_clksel_recalc,
2679 .round_rate = &omap2_clksel_round_rate,
2680 .set_rate = &omap2_clksel_set_rate,
2681};
2682
2683static struct clk usim_fclk = {
2684 .name = "usim_fclk",
2685 .ops = &clkops_omap2_dflt,
2686 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2687 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2688 .clkdm_name = "l4_wkup_clkdm",
2689 .parent = &usim_ck,
2690 .recalc = &followparent_recalc,
2691};
2692
2693static struct clk usim_fck = {
2694 .name = "usim_fck",
2695 .ops = &clkops_omap2_dflt,
2696 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2697 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2698 .clkdm_name = "l4_wkup_clkdm",
2699 .parent = &sys_32k_ck,
2700 .recalc = &followparent_recalc,
2701};
2702
2703static struct clk wd_timer2_fck = {
2704 .name = "wd_timer2_fck",
2705 .ops = &clkops_omap2_dflt,
2706 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2707 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2708 .clkdm_name = "l4_wkup_clkdm",
2709 .parent = &sys_32k_ck,
2710 .recalc = &followparent_recalc,
2711};
2712
2713static struct clk wd_timer3_fck = {
2714 .name = "wd_timer3_fck",
2715 .ops = &clkops_omap2_dflt,
2716 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2717 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2718 .clkdm_name = "abe_clkdm",
2719 .parent = &sys_32k_ck,
2720 .recalc = &followparent_recalc,
2721};
2722
2723/* Remaining optional clocks */
2724static const struct clksel stm_clk_div_div[] = {
2725 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2726 { .parent = NULL },
2727};
2728
2729static struct clk stm_clk_div_ck = {
2730 .name = "stm_clk_div_ck",
2731 .parent = &pmd_stm_clock_mux_ck,
2732 .clksel = stm_clk_div_div,
2733 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2734 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2735 .ops = &clkops_null,
2736 .recalc = &omap2_clksel_recalc,
2737 .round_rate = &omap2_clksel_round_rate,
2738 .set_rate = &omap2_clksel_set_rate,
2739};
2740
2741static const struct clksel trace_clk_div_div[] = {
2742 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2743 { .parent = NULL },
2744};
2745
2746static struct clk trace_clk_div_ck = {
2747 .name = "trace_clk_div_ck",
2748 .parent = &pmd_trace_clk_mux_ck,
2749 .clkdm_name = "emu_sys_clkdm",
2750 .clksel = trace_clk_div_div,
2751 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2752 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2753 .ops = &clkops_null,
2754 .recalc = &omap2_clksel_recalc,
2755 .round_rate = &omap2_clksel_round_rate,
2756 .set_rate = &omap2_clksel_set_rate,
2757};
2758
2759/* SCRM aux clk nodes */
2760
2761static const struct clksel auxclk_src_sel[] = {
2762 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
2763 { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
2764 { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
2765 { .parent = NULL },
2766};
2767
2768static const struct clksel_rate div16_1to16_rates[] = {
2769 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
2770 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
2771 { .div = 3, .val = 2, .flags = RATE_IN_4430 },
2772 { .div = 4, .val = 3, .flags = RATE_IN_4430 },
2773 { .div = 5, .val = 4, .flags = RATE_IN_4430 },
2774 { .div = 6, .val = 5, .flags = RATE_IN_4430 },
2775 { .div = 7, .val = 6, .flags = RATE_IN_4430 },
2776 { .div = 8, .val = 7, .flags = RATE_IN_4430 },
2777 { .div = 9, .val = 8, .flags = RATE_IN_4430 },
2778 { .div = 10, .val = 9, .flags = RATE_IN_4430 },
2779 { .div = 11, .val = 10, .flags = RATE_IN_4430 },
2780 { .div = 12, .val = 11, .flags = RATE_IN_4430 },
2781 { .div = 13, .val = 12, .flags = RATE_IN_4430 },
2782 { .div = 14, .val = 13, .flags = RATE_IN_4430 },
2783 { .div = 15, .val = 14, .flags = RATE_IN_4430 },
2784 { .div = 16, .val = 15, .flags = RATE_IN_4430 },
2785 { .div = 0 },
2786};
2787
2788static struct clk auxclk0_src_ck = {
2789 .name = "auxclk0_src_ck",
2790 .parent = &sys_clkin_ck,
2791 .init = &omap2_init_clksel_parent,
2792 .ops = &clkops_omap2_dflt,
2793 .clksel = auxclk_src_sel,
2794 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2795 .clksel_mask = OMAP4_SRCSELECT_MASK,
2796 .recalc = &omap2_clksel_recalc,
2797 .enable_reg = OMAP4_SCRM_AUXCLK0,
2798 .enable_bit = OMAP4_ENABLE_SHIFT,
2799};
2800
2801static const struct clksel auxclk0_sel[] = {
2802 { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
2803 { .parent = NULL },
2804};
2805
2806static struct clk auxclk0_ck = {
2807 .name = "auxclk0_ck",
2808 .parent = &auxclk0_src_ck,
2809 .clksel = auxclk0_sel,
2810 .clksel_reg = OMAP4_SCRM_AUXCLK0,
2811 .clksel_mask = OMAP4_CLKDIV_MASK,
2812 .ops = &clkops_null,
2813 .recalc = &omap2_clksel_recalc,
2814 .round_rate = &omap2_clksel_round_rate,
2815 .set_rate = &omap2_clksel_set_rate,
2816};
2817
2818static struct clk auxclk1_src_ck = {
2819 .name = "auxclk1_src_ck",
2820 .parent = &sys_clkin_ck,
2821 .init = &omap2_init_clksel_parent,
2822 .ops = &clkops_omap2_dflt,
2823 .clksel = auxclk_src_sel,
2824 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2825 .clksel_mask = OMAP4_SRCSELECT_MASK,
2826 .recalc = &omap2_clksel_recalc,
2827 .enable_reg = OMAP4_SCRM_AUXCLK1,
2828 .enable_bit = OMAP4_ENABLE_SHIFT,
2829};
2830
2831static const struct clksel auxclk1_sel[] = {
2832 { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
2833 { .parent = NULL },
2834};
2835
2836static struct clk auxclk1_ck = {
2837 .name = "auxclk1_ck",
2838 .parent = &auxclk1_src_ck,
2839 .clksel = auxclk1_sel,
2840 .clksel_reg = OMAP4_SCRM_AUXCLK1,
2841 .clksel_mask = OMAP4_CLKDIV_MASK,
2842 .ops = &clkops_null,
2843 .recalc = &omap2_clksel_recalc,
2844 .round_rate = &omap2_clksel_round_rate,
2845 .set_rate = &omap2_clksel_set_rate,
2846};
2847
2848static struct clk auxclk2_src_ck = {
2849 .name = "auxclk2_src_ck",
2850 .parent = &sys_clkin_ck,
2851 .init = &omap2_init_clksel_parent,
2852 .ops = &clkops_omap2_dflt,
2853 .clksel = auxclk_src_sel,
2854 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2855 .clksel_mask = OMAP4_SRCSELECT_MASK,
2856 .recalc = &omap2_clksel_recalc,
2857 .enable_reg = OMAP4_SCRM_AUXCLK2,
2858 .enable_bit = OMAP4_ENABLE_SHIFT,
2859};
2860
2861static const struct clksel auxclk2_sel[] = {
2862 { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
2863 { .parent = NULL },
2864};
2865
2866static struct clk auxclk2_ck = {
2867 .name = "auxclk2_ck",
2868 .parent = &auxclk2_src_ck,
2869 .clksel = auxclk2_sel,
2870 .clksel_reg = OMAP4_SCRM_AUXCLK2,
2871 .clksel_mask = OMAP4_CLKDIV_MASK,
2872 .ops = &clkops_null,
2873 .recalc = &omap2_clksel_recalc,
2874 .round_rate = &omap2_clksel_round_rate,
2875 .set_rate = &omap2_clksel_set_rate,
2876};
2877
2878static struct clk auxclk3_src_ck = {
2879 .name = "auxclk3_src_ck",
2880 .parent = &sys_clkin_ck,
2881 .init = &omap2_init_clksel_parent,
2882 .ops = &clkops_omap2_dflt,
2883 .clksel = auxclk_src_sel,
2884 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2885 .clksel_mask = OMAP4_SRCSELECT_MASK,
2886 .recalc = &omap2_clksel_recalc,
2887 .enable_reg = OMAP4_SCRM_AUXCLK3,
2888 .enable_bit = OMAP4_ENABLE_SHIFT,
2889};
2890
2891static const struct clksel auxclk3_sel[] = {
2892 { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
2893 { .parent = NULL },
2894};
2895
2896static struct clk auxclk3_ck = {
2897 .name = "auxclk3_ck",
2898 .parent = &auxclk3_src_ck,
2899 .clksel = auxclk3_sel,
2900 .clksel_reg = OMAP4_SCRM_AUXCLK3,
2901 .clksel_mask = OMAP4_CLKDIV_MASK,
2902 .ops = &clkops_null,
2903 .recalc = &omap2_clksel_recalc,
2904 .round_rate = &omap2_clksel_round_rate,
2905 .set_rate = &omap2_clksel_set_rate,
2906};
2907
2908static struct clk auxclk4_src_ck = {
2909 .name = "auxclk4_src_ck",
2910 .parent = &sys_clkin_ck,
2911 .init = &omap2_init_clksel_parent,
2912 .ops = &clkops_omap2_dflt,
2913 .clksel = auxclk_src_sel,
2914 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2915 .clksel_mask = OMAP4_SRCSELECT_MASK,
2916 .recalc = &omap2_clksel_recalc,
2917 .enable_reg = OMAP4_SCRM_AUXCLK4,
2918 .enable_bit = OMAP4_ENABLE_SHIFT,
2919};
2920
2921static const struct clksel auxclk4_sel[] = {
2922 { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
2923 { .parent = NULL },
2924};
2925
2926static struct clk auxclk4_ck = {
2927 .name = "auxclk4_ck",
2928 .parent = &auxclk4_src_ck,
2929 .clksel = auxclk4_sel,
2930 .clksel_reg = OMAP4_SCRM_AUXCLK4,
2931 .clksel_mask = OMAP4_CLKDIV_MASK,
2932 .ops = &clkops_null,
2933 .recalc = &omap2_clksel_recalc,
2934 .round_rate = &omap2_clksel_round_rate,
2935 .set_rate = &omap2_clksel_set_rate,
2936};
2937
2938static struct clk auxclk5_src_ck = {
2939 .name = "auxclk5_src_ck",
2940 .parent = &sys_clkin_ck,
2941 .init = &omap2_init_clksel_parent,
2942 .ops = &clkops_omap2_dflt,
2943 .clksel = auxclk_src_sel,
2944 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2945 .clksel_mask = OMAP4_SRCSELECT_MASK,
2946 .recalc = &omap2_clksel_recalc,
2947 .enable_reg = OMAP4_SCRM_AUXCLK5,
2948 .enable_bit = OMAP4_ENABLE_SHIFT,
2949};
2950
2951static const struct clksel auxclk5_sel[] = {
2952 { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
2953 { .parent = NULL },
2954};
2955
2956static struct clk auxclk5_ck = {
2957 .name = "auxclk5_ck",
2958 .parent = &auxclk5_src_ck,
2959 .clksel = auxclk5_sel,
2960 .clksel_reg = OMAP4_SCRM_AUXCLK5,
2961 .clksel_mask = OMAP4_CLKDIV_MASK,
2962 .ops = &clkops_null,
2963 .recalc = &omap2_clksel_recalc,
2964 .round_rate = &omap2_clksel_round_rate,
2965 .set_rate = &omap2_clksel_set_rate,
2966};
2967
2968static const struct clksel auxclkreq_sel[] = {
2969 { .parent = &auxclk0_ck, .rates = div_1_0_rates },
2970 { .parent = &auxclk1_ck, .rates = div_1_1_rates },
2971 { .parent = &auxclk2_ck, .rates = div_1_2_rates },
2972 { .parent = &auxclk3_ck, .rates = div_1_3_rates },
2973 { .parent = &auxclk4_ck, .rates = div_1_4_rates },
2974 { .parent = &auxclk5_ck, .rates = div_1_5_rates },
2975 { .parent = NULL },
2976};
2977
2978static struct clk auxclkreq0_ck = {
2979 .name = "auxclkreq0_ck",
2980 .parent = &auxclk0_ck,
2981 .init = &omap2_init_clksel_parent,
2982 .ops = &clkops_null,
2983 .clksel = auxclkreq_sel,
2984 .clksel_reg = OMAP4_SCRM_AUXCLKREQ0,
2985 .clksel_mask = OMAP4_MAPPING_MASK,
2986 .recalc = &omap2_clksel_recalc,
2987};
2988
2989static struct clk auxclkreq1_ck = {
2990 .name = "auxclkreq1_ck",
2991 .parent = &auxclk1_ck,
2992 .init = &omap2_init_clksel_parent,
2993 .ops = &clkops_null,
2994 .clksel = auxclkreq_sel,
2995 .clksel_reg = OMAP4_SCRM_AUXCLKREQ1,
2996 .clksel_mask = OMAP4_MAPPING_MASK,
2997 .recalc = &omap2_clksel_recalc,
2998};
2999
3000static struct clk auxclkreq2_ck = {
3001 .name = "auxclkreq2_ck",
3002 .parent = &auxclk2_ck,
3003 .init = &omap2_init_clksel_parent,
3004 .ops = &clkops_null,
3005 .clksel = auxclkreq_sel,
3006 .clksel_reg = OMAP4_SCRM_AUXCLKREQ2,
3007 .clksel_mask = OMAP4_MAPPING_MASK,
3008 .recalc = &omap2_clksel_recalc,
3009};
3010
3011static struct clk auxclkreq3_ck = {
3012 .name = "auxclkreq3_ck",
3013 .parent = &auxclk3_ck,
3014 .init = &omap2_init_clksel_parent,
3015 .ops = &clkops_null,
3016 .clksel = auxclkreq_sel,
3017 .clksel_reg = OMAP4_SCRM_AUXCLKREQ3,
3018 .clksel_mask = OMAP4_MAPPING_MASK,
3019 .recalc = &omap2_clksel_recalc,
3020};
3021
3022static struct clk auxclkreq4_ck = {
3023 .name = "auxclkreq4_ck",
3024 .parent = &auxclk4_ck,
3025 .init = &omap2_init_clksel_parent,
3026 .ops = &clkops_null,
3027 .clksel = auxclkreq_sel,
3028 .clksel_reg = OMAP4_SCRM_AUXCLKREQ4,
3029 .clksel_mask = OMAP4_MAPPING_MASK,
3030 .recalc = &omap2_clksel_recalc,
3031};
3032
3033static struct clk auxclkreq5_ck = {
3034 .name = "auxclkreq5_ck",
3035 .parent = &auxclk5_ck,
3036 .init = &omap2_init_clksel_parent,
3037 .ops = &clkops_null,
3038 .clksel = auxclkreq_sel,
3039 .clksel_reg = OMAP4_SCRM_AUXCLKREQ5,
3040 .clksel_mask = OMAP4_MAPPING_MASK,
3041 .recalc = &omap2_clksel_recalc,
3042};
3043
3044/*
3045 * clkdev
3046 */
3047
3048static struct omap_clk omap44xx_clks[] = {
3049 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
3050 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
3051 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
3052 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
3053 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
3054 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
3055 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
3056 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
3057 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
3058 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
3059 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
3060 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
3061 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
3062 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
3063 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
3064 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
3065 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
3066 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
3067 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
3068 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
3069 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
3070 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
3071 CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_443X),
3072 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
3073 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
3074 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
3075 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
3076 CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_443X),
3077 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
3078 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
3079 CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_443X),
3080 CLK(NULL, "dpll_core_m6x2_ck", &dpll_core_m6x2_ck, CK_443X),
3081 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
3082 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
3083 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
3084 CLK(NULL, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, CK_443X),
3085 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
3086 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
3087 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
3088 CLK(NULL, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck, CK_443X),
3089 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
3090 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
3091 CLK(NULL, "dpll_core_m3x2_ck", &dpll_core_m3x2_ck, CK_443X),
3092 CLK(NULL, "dpll_core_m7x2_ck", &dpll_core_m7x2_ck, CK_443X),
3093 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
3094 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
3095 CLK(NULL, "dpll_iva_x2_ck", &dpll_iva_x2_ck, CK_443X),
3096 CLK(NULL, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, CK_443X),
3097 CLK(NULL, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, CK_443X),
3098 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
3099 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
3100 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
3101 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
3102 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
3103 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
3104 CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_443X),
3105 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
3106 CLK(NULL, "dpll_per_m3x2_ck", &dpll_per_m3x2_ck, CK_443X),
3107 CLK(NULL, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, CK_443X),
3108 CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
3109 CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
3110 CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
3111 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
3112 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
3113 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
3114 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
3115 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
3116 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
3117 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
3118 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
3119 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
3120 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
3121 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
3122 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
3123 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
3124 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
3125 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
3126 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
3127 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
3128 CLK("smp_twd", NULL, &mpu_periphclk, CK_443X),
3129 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
3130 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
3131 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
3132 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
3133 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
3134 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
3135 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
3136 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
3137 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
3138 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
3139 CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
3140 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
3141 CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
3142 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
3143 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
3144 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
3145 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
3146 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
3147 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
3148 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
3149 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
3150 CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
3151 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
3152 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
3153 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
3154 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
3155 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
3156 CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_443X),
3157 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
3158 CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_443X),
3159 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
3160 CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_443X),
3161 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
3162 CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_443X),
3163 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
3164 CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_443X),
3165 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
3166 CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_443X),
3167 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
3168 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
3169 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
3170 CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
3171 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
3172 CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
3173 CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
3174 CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
3175 CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
3176 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
3177 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
3178 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
3179 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
3180 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
3181 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
3182 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
3183 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
3184 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
3185 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
3186 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
3187 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
3188 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
3189 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
3190 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
3191 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
3192 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
3193 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
3194 CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
3195 CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
3196 CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
3197 CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
3198 CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
3199 CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
3200 CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
3201 CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
3202 CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
3203 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3204 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3205 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
3206 CLK(NULL, "rng_ick", &rng_ick, CK_443X),
3207 CLK("omap_rng", "ick", &rng_ick, CK_443X),
3208 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
3209 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
3210 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
3211 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
3212 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
3213 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
3214 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
3215 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
3216 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
3217 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
3218 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
3219 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
3220 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
3221 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
3222 CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
3223 CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
3224 CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
3225 CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
3226 CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
3227 CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
3228 CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
3229 CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
3230 CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
3231 CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
3232 CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
3233 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
3234 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
3235 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
3236 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
3237 CLK("usbhs_omap", "fs_fck", &usb_host_fs_fck, CK_443X),
3238 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
3239 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
3240 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
3241 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
3242 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
3243 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
3244 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
3245 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
3246 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
3247 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
3248 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
3249 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
3250 CLK("usbhs_omap", "hs_fck", &usb_host_hs_fck, CK_443X),
3251 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
3252 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
3253 CLK(NULL, "usb_otg_hs_ick", &usb_otg_hs_ick, CK_443X),
3254 CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
3255 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
3256 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
3257 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
3258 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
3259 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
3260 CLK("usbhs_omap", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3261 CLK("usbhs_tll", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
3262 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
3263 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
3264 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
3265 CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
3266 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
3267 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
3268 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
3269 CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
3270 CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
3271 CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
3272 CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
3273 CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
3274 CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
3275 CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
3276 CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
3277 CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
3278 CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
3279 CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
3280 CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
3281 CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
3282 CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
3283 CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
3284 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
3285 CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
3286 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
3287 CLK("omap-gpmc", "fck", &dummy_ck, CK_443X),
3288 CLK("omap_i2c.1", "ick", &dummy_ck, CK_443X),
3289 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3290 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3291 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3292 CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
3293 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3294 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3295 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3296 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3297 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3298 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3299 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3300 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
3301 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
3302 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
3303 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
3304 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
3305 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
3306 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
3307 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
3308 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
3309 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
3310 CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_443X),
3311 CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_443X),
3312 CLK("usbhs_tll", "usbtll_fck", &dummy_ck, CK_443X),
3313 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
3314 CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_443X),
3315 /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
3316 CLK("omap_timer.1", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3317 CLK("omap_timer.2", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3318 CLK("omap_timer.3", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3319 CLK("omap_timer.4", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3320 CLK("omap_timer.9", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3321 CLK("omap_timer.10", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3322 CLK("omap_timer.11", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3323 CLK("omap_timer.5", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3324 CLK("omap_timer.6", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3325 CLK("omap_timer.7", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3326 CLK("omap_timer.8", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3327 CLK("4a318000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3328 CLK("48032000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3329 CLK("48034000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3330 CLK("48036000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3331 CLK("4803e000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3332 CLK("48086000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3333 CLK("48088000.timer", "timer_sys_ck", &sys_clkin_ck, CK_443X),
3334 CLK("49038000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3335 CLK("4903a000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3336 CLK("4903c000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3337 CLK("4903e000.timer", "timer_sys_ck", &syc_clk_div_ck, CK_443X),
3338 CLK(NULL, "cpufreq_ck", &dpll_mpu_ck, CK_443X),
3339};
3340
3341int __init omap4xxx_clk_init(void)
3342{
3343 struct omap_clk *c;
3344 u32 cpu_clkflg;
3345
3346 if (cpu_is_omap443x()) {
3347 cpu_mask = RATE_IN_4430;
3348 cpu_clkflg = CK_443X;
3349 } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
3350 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
3351 cpu_clkflg = CK_446X | CK_443X;
3352
3353 if (cpu_is_omap447x())
3354 pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
3355 } else {
3356 return 0;
3357 }
3358
3359 /*
3360 * Must stay commented until all OMAP SoC drivers are
3361 * converted to runtime PM, or drivers may start crashing
3362 *
3363 * omap2_clk_disable_clkdm_control();
3364 */
3365
3366 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3367 c++)
3368 clk_preinit(c->lk.clk);
3369
3370 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
3371 c++)
3372 if (c->cpu & cpu_clkflg) {
3373 clkdev_add(&c->lk);
3374 clk_register(c->lk.clk);
3375 omap2_init_clk_clkdm(c->lk.clk);
3376 }
3377
3378 /* Disable autoidle on all clocks; let the PM code enable it later */
3379 omap_clk_disable_autoidle_all();
3380
3381 recalculate_root_clocks();
3382
3383 /*
3384 * Only enable those clocks we will need, let the drivers
3385 * enable other clocks as necessary
3386 */
3387 clk_enable_init_clocks();
3388
3389 return 0;
3390}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 13:26:50 -0400