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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-20 14:02:10 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-20 14:02:10 -0500
commit10b6339e93244156fac901560117e94bf9dca120 (patch)
tree93a86c1328f0f3b0f37af493907b32d72027c9d1
parentc6699b58f4fe2f968f036a862c09ce44b6968376 (diff)
parentfde8bc59c03c0ad1fa4f655e0ed5cc1f76d11e8b (diff)
Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clock framework update from Michael Turquette: "The common clock framework changes for 3.9 are almost entirely fixes. None are dire enough to be Cc'd to stable which may be interpreted to mean that users of the framework are reaching stability. Lots of new adoption of this framework is via DeviceTree data and that comes through the respective architecture and platform trees instead of through the clk framework tree. Two new features are improved debugfs output and an improvement to how DT clocks are initialized by reusing a common method." * tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (25 commits) clk: sunxi: remove stale Makefile entry clk: vexpress: Use common of_clk_init() function clk: zynq: Use common of_clk_init() function clk: vt8500: Use common of_clk_init() function clk: highbank: Use common of_clk_init() function clk: sunxi: Use common of_clk_init() function clk: add common of_clk_init() function clk: Deduplicate exit code in clk_set_rate clk: beautify Makefile clk-divider: fix macros clk: prima2: enable dt-binding clkdev mapping clk: mxs: Index is always positive clk: max77686: Avoid double free at remove time clk: remove exported function from __init section clk: vt8500: Add support for WM8750/WM8850 PLL clocks clk: vt8500: Fix division-by-0 when requested rate=0 clk: vt8500: Fix device clock divisor calculations clk: vt8500: Fix error in PLL calculations on non-exact match. clk: max77686: Remove unnecessary NULL checking for container_of() clk: JSON debugfs clock tree summary ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/prima2-clock.txt73
-rw-r--r--arch/arm/boot/dts/prima2.dtsi31
-rw-r--r--arch/arm/mach-highbank/core.h1
-rw-r--r--arch/arm/mach-highbank/highbank.c3
-rw-r--r--drivers/clk/Makefile10
-rw-r--r--drivers/clk/clk-divider.c6
-rw-r--r--drivers/clk/clk-fixed-factor.c5
-rw-r--r--drivers/clk/clk-fixed-rate.c3
-rw-r--r--drivers/clk/clk-highbank.c18
-rw-r--r--drivers/clk/clk-max77686.c37
-rw-r--r--drivers/clk/clk-prima2.c205
-rw-r--r--drivers/clk/clk-sunxi.c30
-rw-r--r--drivers/clk/clk-vt8500.c143
-rw-r--r--drivers/clk/clk-zynq.c14
-rw-r--r--drivers/clk/clk.c169
-rw-r--r--drivers/clk/mxs/clk-imx23.c2
-rw-r--r--drivers/clk/mxs/clk-imx28.c2
-rw-r--r--drivers/clk/versatile/clk-vexpress-osc.c1
-rw-r--r--drivers/clk/versatile/clk-vexpress.c8
-rw-r--r--drivers/clocksource/sunxi_timer.c4
-rw-r--r--include/asm-generic/vmlinux.lds.h10
-rw-r--r--include/linux/clk-provider.h6
-rw-r--r--include/linux/clk/sunxi.h22
23 files changed, 527 insertions, 276 deletions
diff --git a/Documentation/devicetree/bindings/clock/prima2-clock.txt b/Documentation/devicetree/bindings/clock/prima2-clock.txt
new file mode 100644
index 000000000000..5016979c0f78
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/prima2-clock.txt
@@ -0,0 +1,73 @@
1* Clock bindings for CSR SiRFprimaII
2
3Required properties:
4- compatible: Should be "sirf,prima2-clkc"
5- reg: Address and length of the register set
6- interrupts: Should contain clock controller interrupt
7- #clock-cells: Should be <1>
8
9The clock consumer should specify the desired clock by having the clock
10ID in its "clocks" phandle cell. The following is a full list of prima2
11clocks and IDs.
12
13 Clock ID
14 ---------------------------
15 rtc 0
16 osc 1
17 pll1 2
18 pll2 3
19 pll3 4
20 mem 5
21 sys 6
22 security 7
23 dsp 8
24 gps 9
25 mf 10
26 io 11
27 cpu 12
28 uart0 13
29 uart1 14
30 uart2 15
31 tsc 16
32 i2c0 17
33 i2c1 18
34 spi0 19
35 spi1 20
36 pwmc 21
37 efuse 22
38 pulse 23
39 dmac0 24
40 dmac1 25
41 nand 26
42 audio 27
43 usp0 28
44 usp1 29
45 usp2 30
46 vip 31
47 gfx 32
48 mm 33
49 lcd 34
50 vpp 35
51 mmc01 36
52 mmc23 37
53 mmc45 38
54 usbpll 39
55 usb0 40
56 usb1 41
57
58Examples:
59
60clks: clock-controller@88000000 {
61 compatible = "sirf,prima2-clkc";
62 reg = <0x88000000 0x1000>;
63 interrupts = <3>;
64 #clock-cells = <1>;
65};
66
67i2c0: i2c@b00e0000 {
68 cell-index = <0>;
69 compatible = "sirf,prima2-i2c";
70 reg = <0xb00e0000 0x10000>;
71 interrupts = <24>;
72 clocks = <&clks 17>;
73};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 055fca542120..3329719a9412 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -58,10 +58,11 @@
58 #size-cells = <1>; 58 #size-cells = <1>;
59 ranges = <0x88000000 0x88000000 0x40000>; 59 ranges = <0x88000000 0x88000000 0x40000>;
60 60
61 clock-controller@88000000 { 61 clks: clock-controller@88000000 {
62 compatible = "sirf,prima2-clkc"; 62 compatible = "sirf,prima2-clkc";
63 reg = <0x88000000 0x1000>; 63 reg = <0x88000000 0x1000>;
64 interrupts = <3>; 64 interrupts = <3>;
65 #clock-cells = <1>;
65 }; 66 };
66 67
67 reset-controller@88010000 { 68 reset-controller@88010000 {
@@ -85,6 +86,7 @@
85 compatible = "sirf,prima2-memc"; 86 compatible = "sirf,prima2-memc";
86 reg = <0x90000000 0x10000>; 87 reg = <0x90000000 0x10000>;
87 interrupts = <27>; 88 interrupts = <27>;
89 clocks = <&clks 5>;
88 }; 90 };
89 }; 91 };
90 92
@@ -104,6 +106,7 @@
104 compatible = "sirf,prima2-vpp"; 106 compatible = "sirf,prima2-vpp";
105 reg = <0x90020000 0x10000>; 107 reg = <0x90020000 0x10000>;
106 interrupts = <31>; 108 interrupts = <31>;
109 clocks = <&clks 35>;
107 }; 110 };
108 }; 111 };
109 112
@@ -117,6 +120,7 @@
117 compatible = "powervr,sgx531"; 120 compatible = "powervr,sgx531";
118 reg = <0x98000000 0x8000000>; 121 reg = <0x98000000 0x8000000>;
119 interrupts = <6>; 122 interrupts = <6>;
123 clocks = <&clks 32>;
120 }; 124 };
121 }; 125 };
122 126
@@ -130,6 +134,7 @@
130 compatible = "sirf,prima2-video-codec"; 134 compatible = "sirf,prima2-video-codec";
131 reg = <0xa0000000 0x8000000>; 135 reg = <0xa0000000 0x8000000>;
132 interrupts = <5>; 136 interrupts = <5>;
137 clocks = <&clks 33>;
133 }; 138 };
134 }; 139 };
135 140
@@ -149,12 +154,14 @@
149 compatible = "sirf,prima2-gps"; 154 compatible = "sirf,prima2-gps";
150 reg = <0xa8010000 0x10000>; 155 reg = <0xa8010000 0x10000>;
151 interrupts = <7>; 156 interrupts = <7>;
157 clocks = <&clks 9>;
152 }; 158 };
153 159
154 dsp@a9000000 { 160 dsp@a9000000 {
155 compatible = "sirf,prima2-dsp"; 161 compatible = "sirf,prima2-dsp";
156 reg = <0xa9000000 0x1000000>; 162 reg = <0xa9000000 0x1000000>;
157 interrupts = <8>; 163 interrupts = <8>;
164 clocks = <&clks 8>;
158 }; 165 };
159 }; 166 };
160 167
@@ -174,12 +181,14 @@
174 compatible = "sirf,prima2-nand"; 181 compatible = "sirf,prima2-nand";
175 reg = <0xb0030000 0x10000>; 182 reg = <0xb0030000 0x10000>;
176 interrupts = <41>; 183 interrupts = <41>;
184 clocks = <&clks 26>;
177 }; 185 };
178 186
179 audio@b0040000 { 187 audio@b0040000 {
180 compatible = "sirf,prima2-audio"; 188 compatible = "sirf,prima2-audio";
181 reg = <0xb0040000 0x10000>; 189 reg = <0xb0040000 0x10000>;
182 interrupts = <35>; 190 interrupts = <35>;
191 clocks = <&clks 27>;
183 }; 192 };
184 193
185 uart0: uart@b0050000 { 194 uart0: uart@b0050000 {
@@ -187,6 +196,7 @@
187 compatible = "sirf,prima2-uart"; 196 compatible = "sirf,prima2-uart";
188 reg = <0xb0050000 0x10000>; 197 reg = <0xb0050000 0x10000>;
189 interrupts = <17>; 198 interrupts = <17>;
199 clocks = <&clks 13>;
190 }; 200 };
191 201
192 uart1: uart@b0060000 { 202 uart1: uart@b0060000 {
@@ -194,6 +204,7 @@
194 compatible = "sirf,prima2-uart"; 204 compatible = "sirf,prima2-uart";
195 reg = <0xb0060000 0x10000>; 205 reg = <0xb0060000 0x10000>;
196 interrupts = <18>; 206 interrupts = <18>;
207 clocks = <&clks 14>;
197 }; 208 };
198 209
199 uart2: uart@b0070000 { 210 uart2: uart@b0070000 {
@@ -201,6 +212,7 @@
201 compatible = "sirf,prima2-uart"; 212 compatible = "sirf,prima2-uart";
202 reg = <0xb0070000 0x10000>; 213 reg = <0xb0070000 0x10000>;
203 interrupts = <19>; 214 interrupts = <19>;
215 clocks = <&clks 15>;
204 }; 216 };
205 217
206 usp0: usp@b0080000 { 218 usp0: usp@b0080000 {
@@ -208,6 +220,7 @@
208 compatible = "sirf,prima2-usp"; 220 compatible = "sirf,prima2-usp";
209 reg = <0xb0080000 0x10000>; 221 reg = <0xb0080000 0x10000>;
210 interrupts = <20>; 222 interrupts = <20>;
223 clocks = <&clks 28>;
211 }; 224 };
212 225
213 usp1: usp@b0090000 { 226 usp1: usp@b0090000 {
@@ -215,6 +228,7 @@
215 compatible = "sirf,prima2-usp"; 228 compatible = "sirf,prima2-usp";
216 reg = <0xb0090000 0x10000>; 229 reg = <0xb0090000 0x10000>;
217 interrupts = <21>; 230 interrupts = <21>;
231 clocks = <&clks 29>;
218 }; 232 };
219 233
220 usp2: usp@b00a0000 { 234 usp2: usp@b00a0000 {
@@ -222,6 +236,7 @@
222 compatible = "sirf,prima2-usp"; 236 compatible = "sirf,prima2-usp";
223 reg = <0xb00a0000 0x10000>; 237 reg = <0xb00a0000 0x10000>;
224 interrupts = <22>; 238 interrupts = <22>;
239 clocks = <&clks 30>;
225 }; 240 };
226 241
227 dmac0: dma-controller@b00b0000 { 242 dmac0: dma-controller@b00b0000 {
@@ -229,6 +244,7 @@
229 compatible = "sirf,prima2-dmac"; 244 compatible = "sirf,prima2-dmac";
230 reg = <0xb00b0000 0x10000>; 245 reg = <0xb00b0000 0x10000>;
231 interrupts = <12>; 246 interrupts = <12>;
247 clocks = <&clks 24>;
232 }; 248 };
233 249
234 dmac1: dma-controller@b0160000 { 250 dmac1: dma-controller@b0160000 {
@@ -236,11 +252,13 @@
236 compatible = "sirf,prima2-dmac"; 252 compatible = "sirf,prima2-dmac";
237 reg = <0xb0160000 0x10000>; 253 reg = <0xb0160000 0x10000>;
238 interrupts = <13>; 254 interrupts = <13>;
255 clocks = <&clks 25>;
239 }; 256 };
240 257
241 vip@b00C0000 { 258 vip@b00C0000 {
242 compatible = "sirf,prima2-vip"; 259 compatible = "sirf,prima2-vip";
243 reg = <0xb00C0000 0x10000>; 260 reg = <0xb00C0000 0x10000>;
261 clocks = <&clks 31>;
244 }; 262 };
245 263
246 spi0: spi@b00d0000 { 264 spi0: spi@b00d0000 {
@@ -248,6 +266,7 @@
248 compatible = "sirf,prima2-spi"; 266 compatible = "sirf,prima2-spi";
249 reg = <0xb00d0000 0x10000>; 267 reg = <0xb00d0000 0x10000>;
250 interrupts = <15>; 268 interrupts = <15>;
269 clocks = <&clks 19>;
251 }; 270 };
252 271
253 spi1: spi@b0170000 { 272 spi1: spi@b0170000 {
@@ -255,6 +274,7 @@
255 compatible = "sirf,prima2-spi"; 274 compatible = "sirf,prima2-spi";
256 reg = <0xb0170000 0x10000>; 275 reg = <0xb0170000 0x10000>;
257 interrupts = <16>; 276 interrupts = <16>;
277 clocks = <&clks 20>;
258 }; 278 };
259 279
260 i2c0: i2c@b00e0000 { 280 i2c0: i2c@b00e0000 {
@@ -262,6 +282,7 @@
262 compatible = "sirf,prima2-i2c"; 282 compatible = "sirf,prima2-i2c";
263 reg = <0xb00e0000 0x10000>; 283 reg = <0xb00e0000 0x10000>;
264 interrupts = <24>; 284 interrupts = <24>;
285 clocks = <&clks 17>;
265 }; 286 };
266 287
267 i2c1: i2c@b00f0000 { 288 i2c1: i2c@b00f0000 {
@@ -269,12 +290,14 @@
269 compatible = "sirf,prima2-i2c"; 290 compatible = "sirf,prima2-i2c";
270 reg = <0xb00f0000 0x10000>; 291 reg = <0xb00f0000 0x10000>;
271 interrupts = <25>; 292 interrupts = <25>;
293 clocks = <&clks 18>;
272 }; 294 };
273 295
274 tsc@b0110000 { 296 tsc@b0110000 {
275 compatible = "sirf,prima2-tsc"; 297 compatible = "sirf,prima2-tsc";
276 reg = <0xb0110000 0x10000>; 298 reg = <0xb0110000 0x10000>;
277 interrupts = <33>; 299 interrupts = <33>;
300 clocks = <&clks 16>;
278 }; 301 };
279 302
280 gpio: pinctrl@b0120000 { 303 gpio: pinctrl@b0120000 {
@@ -507,17 +530,20 @@
507 pwm@b0130000 { 530 pwm@b0130000 {
508 compatible = "sirf,prima2-pwm"; 531 compatible = "sirf,prima2-pwm";
509 reg = <0xb0130000 0x10000>; 532 reg = <0xb0130000 0x10000>;
533 clocks = <&clks 21>;
510 }; 534 };
511 535
512 efusesys@b0140000 { 536 efusesys@b0140000 {
513 compatible = "sirf,prima2-efuse"; 537 compatible = "sirf,prima2-efuse";
514 reg = <0xb0140000 0x10000>; 538 reg = <0xb0140000 0x10000>;
539 clocks = <&clks 22>;
515 }; 540 };
516 541
517 pulsec@b0150000 { 542 pulsec@b0150000 {
518 compatible = "sirf,prima2-pulsec"; 543 compatible = "sirf,prima2-pulsec";
519 reg = <0xb0150000 0x10000>; 544 reg = <0xb0150000 0x10000>;
520 interrupts = <48>; 545 interrupts = <48>;
546 clocks = <&clks 23>;
521 }; 547 };
522 548
523 pci-iobg { 549 pci-iobg {
@@ -616,12 +642,14 @@
616 compatible = "chipidea,ci13611a-prima2"; 642 compatible = "chipidea,ci13611a-prima2";
617 reg = <0xb8000000 0x10000>; 643 reg = <0xb8000000 0x10000>;
618 interrupts = <10>; 644 interrupts = <10>;
645 clocks = <&clks 40>;
619 }; 646 };
620 647
621 usb1: usb@b00f0000 { 648 usb1: usb@b00f0000 {
622 compatible = "chipidea,ci13611a-prima2"; 649 compatible = "chipidea,ci13611a-prima2";
623 reg = <0xb8010000 0x10000>; 650 reg = <0xb8010000 0x10000>;
624 interrupts = <11>; 651 interrupts = <11>;
652 clocks = <&clks 41>;
625 }; 653 };
626 654
627 sata@b00f0000 { 655 sata@b00f0000 {
@@ -634,6 +662,7 @@
634 compatible = "sirf,prima2-security"; 662 compatible = "sirf,prima2-security";
635 reg = <0xb8030000 0x10000>; 663 reg = <0xb8030000 0x10000>;
636 interrupts = <42>; 664 interrupts = <42>;
665 clocks = <&clks 7>;
637 }; 666 };
638 }; 667 };
639 }; 668 };
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 80235b46cb58..3f65206a9b92 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -2,7 +2,6 @@
2#define __HIGHBANK_CORE_H 2#define __HIGHBANK_CORE_H
3 3
4extern void highbank_set_cpu_jump(int cpu, void *jump_addr); 4extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
5extern void highbank_clocks_init(void);
6extern void highbank_restart(char, const char *); 5extern void highbank_restart(char, const char *);
7extern void __iomem *scu_base_addr; 6extern void __iomem *scu_base_addr;
8 7
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index e6c061282939..65656ff0eb33 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -25,6 +25,7 @@
25#include <linux/of_address.h> 25#include <linux/of_address.h>
26#include <linux/smp.h> 26#include <linux/smp.h>
27#include <linux/amba/bus.h> 27#include <linux/amba/bus.h>
28#include <linux/clk-provider.h>
28 29
29#include <asm/arch_timer.h> 30#include <asm/arch_timer.h>
30#include <asm/cacheflush.h> 31#include <asm/cacheflush.h>
@@ -117,7 +118,7 @@ static void __init highbank_timer_init(void)
117 WARN_ON(!timer_base); 118 WARN_ON(!timer_base);
118 irq = irq_of_parse_and_map(np, 0); 119 irq = irq_of_parse_and_map(np, 0);
119 120
120 highbank_clocks_init(); 121 of_clk_init(NULL);
121 lookup.clk = of_clk_get(np, 0); 122 lookup.clk = of_clk_get(np, 0);
122 clkdev_add(&lookup); 123 clkdev_add(&lookup);
123 124
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index ee90e87e7675..0ad642fbe794 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,8 +1,13 @@
1# common clock types 1# common clock types
2obj-$(CONFIG_HAVE_CLK) += clk-devres.o 2obj-$(CONFIG_HAVE_CLK) += clk-devres.o
3obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o 3obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
4obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ 4obj-$(CONFIG_COMMON_CLK) += clk.o
5 clk-mux.o clk-divider.o clk-fixed-factor.o 5obj-$(CONFIG_COMMON_CLK) += clk-divider.o
6obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
7obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
8obj-$(CONFIG_COMMON_CLK) += clk-gate.o
9obj-$(CONFIG_COMMON_CLK) += clk-mux.o
10
6# SoCs specific 11# SoCs specific
7obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o 12obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
8obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o 13obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
@@ -20,7 +25,6 @@ endif
20obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o 25obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
21obj-$(CONFIG_ARCH_U8500) += ux500/ 26obj-$(CONFIG_ARCH_U8500) += ux500/
22obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o 27obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
23obj-$(CONFIG_ARCH_SUNXI) += clk-sunxi.o
24obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o 28obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
25 29
26# Chip specific 30# Chip specific
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index a9204c69148d..68b402101170 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -16,6 +16,7 @@
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/string.h> 18#include <linux/string.h>
19#include <linux/log2.h>
19 20
20/* 21/*
21 * DOC: basic adjustable divider clock that cannot gate 22 * DOC: basic adjustable divider clock that cannot gate
@@ -29,8 +30,7 @@
29 30
30#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) 31#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
31 32
32#define div_mask(d) ((1 << (d->width)) - 1) 33#define div_mask(d) ((1 << ((d)->width)) - 1)
33#define is_power_of_two(i) !(i & ~i)
34 34
35static unsigned int _get_table_maxdiv(const struct clk_div_table *table) 35static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
36{ 36{
@@ -137,7 +137,7 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
137static bool _is_valid_div(struct clk_divider *divider, unsigned int div) 137static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
138{ 138{
139 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 139 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
140 return is_power_of_two(div); 140 return is_power_of_2(div);
141 if (divider->table) 141 if (divider->table)
142 return _is_valid_table_div(divider->table, div); 142 return _is_valid_table_div(divider->table, div);
143 return true; 143 return true;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index a4899855c0f6..1ef271e47594 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -28,8 +28,11 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate) 28 unsigned long parent_rate)
29{ 29{
30 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); 30 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
31 unsigned long long int rate;
31 32
32 return parent_rate * fix->mult / fix->div; 33 rate = (unsigned long long int)parent_rate * fix->mult;
34 do_div(rate, fix->div);
35 return (unsigned long)rate;
33} 36}
34 37
35static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, 38static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index af78ed6b67ef..dc58fbd8516f 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -85,7 +85,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
85/** 85/**
86 * of_fixed_clk_setup() - Setup function for simple fixed rate clock 86 * of_fixed_clk_setup() - Setup function for simple fixed rate clock
87 */ 87 */
88void __init of_fixed_clk_setup(struct device_node *node) 88void of_fixed_clk_setup(struct device_node *node)
89{ 89{
90 struct clk *clk; 90 struct clk *clk;
91 const char *clk_name = node->name; 91 const char *clk_name = node->name;
@@ -101,4 +101,5 @@ void __init of_fixed_clk_setup(struct device_node *node)
101 of_clk_add_provider(node, of_clk_src_simple_get, clk); 101 of_clk_add_provider(node, of_clk_src_simple_get, clk);
102} 102}
103EXPORT_SYMBOL_GPL(of_fixed_clk_setup); 103EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
104CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup);
104#endif 105#endif
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 52fecadf004a..5d1de2e11753 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -314,33 +314,23 @@ static void __init hb_pll_init(struct device_node *node)
314{ 314{
315 hb_clk_init(node, &clk_pll_ops); 315 hb_clk_init(node, &clk_pll_ops);
316} 316}
317CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
317 318
318static void __init hb_a9periph_init(struct device_node *node) 319static void __init hb_a9periph_init(struct device_node *node)
319{ 320{
320 hb_clk_init(node, &a9periphclk_ops); 321 hb_clk_init(node, &a9periphclk_ops);
321} 322}
323CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
322 324
323static void __init hb_a9bus_init(struct device_node *node) 325static void __init hb_a9bus_init(struct device_node *node)
324{ 326{
325 struct clk *clk = hb_clk_init(node, &a9bclk_ops); 327 struct clk *clk = hb_clk_init(node, &a9bclk_ops);
326 clk_prepare_enable(clk); 328 clk_prepare_enable(clk);
327} 329}
330CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
328 331
329static void __init hb_emmc_init(struct device_node *node) 332static void __init hb_emmc_init(struct device_node *node)
330{ 333{
331 hb_clk_init(node, &periclk_ops); 334 hb_clk_init(node, &periclk_ops);
332} 335}
333 336CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
334static const __initconst struct of_device_id clk_match[] = {
335 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
336 { .compatible = "calxeda,hb-pll-clock", .data = hb_pll_init, },
337 { .compatible = "calxeda,hb-a9periph-clock", .data = hb_a9periph_init, },
338 { .compatible = "calxeda,hb-a9bus-clock", .data = hb_a9bus_init, },
339 { .compatible = "calxeda,hb-emmc-clock", .data = hb_emmc_init, },
340 {}
341};
342
343void __init highbank_clocks_init(void)
344{
345 of_clk_init(clk_match);
346}
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index d098f72e1d5f..9f57bc37cd60 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -44,33 +44,23 @@ struct max77686_clk {
44 struct clk_lookup *lookup; 44 struct clk_lookup *lookup;
45}; 45};
46 46
47static struct max77686_clk *get_max77686_clk(struct clk_hw *hw) 47static struct max77686_clk *to_max77686_clk(struct clk_hw *hw)
48{ 48{
49 return container_of(hw, struct max77686_clk, hw); 49 return container_of(hw, struct max77686_clk, hw);
50} 50}
51 51
52static int max77686_clk_prepare(struct clk_hw *hw) 52static int max77686_clk_prepare(struct clk_hw *hw)
53{ 53{
54 struct max77686_clk *max77686; 54 struct max77686_clk *max77686 = to_max77686_clk(hw);
55 int ret;
56
57 max77686 = get_max77686_clk(hw);
58 if (!max77686)
59 return -ENOMEM;
60
61 ret = regmap_update_bits(max77686->iodev->regmap,
62 MAX77686_REG_32KHZ, max77686->mask, max77686->mask);
63 55
64 return ret; 56 return regmap_update_bits(max77686->iodev->regmap,
57 MAX77686_REG_32KHZ, max77686->mask,
58 max77686->mask);
65} 59}
66 60
67static void max77686_clk_unprepare(struct clk_hw *hw) 61static void max77686_clk_unprepare(struct clk_hw *hw)
68{ 62{
69 struct max77686_clk *max77686; 63 struct max77686_clk *max77686 = to_max77686_clk(hw);
70
71 max77686 = get_max77686_clk(hw);
72 if (!max77686)
73 return;
74 64
75 regmap_update_bits(max77686->iodev->regmap, 65 regmap_update_bits(max77686->iodev->regmap,
76 MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask); 66 MAX77686_REG_32KHZ, max77686->mask, ~max77686->mask);
@@ -78,14 +68,10 @@ static void max77686_clk_unprepare(struct clk_hw *hw)
78 68
79static int max77686_clk_is_enabled(struct clk_hw *hw) 69static int max77686_clk_is_enabled(struct clk_hw *hw)
80{ 70{
81 struct max77686_clk *max77686; 71 struct max77686_clk *max77686 = to_max77686_clk(hw);
82 int ret; 72 int ret;
83 u32 val; 73 u32 val;
84 74
85 max77686 = get_max77686_clk(hw);
86 if (!max77686)
87 return -ENOMEM;
88
89 ret = regmap_read(max77686->iodev->regmap, 75 ret = regmap_read(max77686->iodev->regmap,
90 MAX77686_REG_32KHZ, &val); 76 MAX77686_REG_32KHZ, &val);
91 77
@@ -130,9 +116,8 @@ static int max77686_clk_register(struct device *dev,
130 if (IS_ERR(clk)) 116 if (IS_ERR(clk))
131 return -ENOMEM; 117 return -ENOMEM;
132 118
133 max77686->lookup = devm_kzalloc(dev, sizeof(struct clk_lookup), 119 max77686->lookup = kzalloc(sizeof(struct clk_lookup), GFP_KERNEL);
134 GFP_KERNEL); 120 if (!max77686->lookup)
135 if (IS_ERR(max77686->lookup))
136 return -ENOMEM; 121 return -ENOMEM;
137 122
138 max77686->lookup->con_id = hw->init->name; 123 max77686->lookup->con_id = hw->init->name;
@@ -151,13 +136,13 @@ static int max77686_clk_probe(struct platform_device *pdev)
151 136
152 max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *) 137 max77686_clks = devm_kzalloc(&pdev->dev, sizeof(struct max77686_clk *)
153 * MAX77686_CLKS_NUM, GFP_KERNEL); 138 * MAX77686_CLKS_NUM, GFP_KERNEL);
154 if (IS_ERR(max77686_clks)) 139 if (!max77686_clks)
155 return -ENOMEM; 140 return -ENOMEM;
156 141
157 for (i = 0; i < MAX77686_CLKS_NUM; i++) { 142 for (i = 0; i < MAX77686_CLKS_NUM; i++) {
158 max77686_clks[i] = devm_kzalloc(&pdev->dev, 143 max77686_clks[i] = devm_kzalloc(&pdev->dev,
159 sizeof(struct max77686_clk), GFP_KERNEL); 144 sizeof(struct max77686_clk), GFP_KERNEL);
160 if (IS_ERR(max77686_clks[i])) 145 if (!max77686_clks[i])
161 return -ENOMEM; 146 return -ENOMEM;
162 } 147 }
163 148
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
index a203ecccdc4f..f8e9d0c27be2 100644
--- a/drivers/clk/clk-prima2.c
+++ b/drivers/clk/clk-prima2.c
@@ -1025,20 +1025,67 @@ static struct of_device_id rsc_ids[] = {
1025 {}, 1025 {},
1026}; 1026};
1027 1027
1028enum prima2_clk_index {
1029 /* 0 1 2 3 4 5 6 7 8 9 */
1030 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps,
1031 mf, io, cpu, uart0, uart1, uart2, tsc, i2c0, i2c1, spi0,
1032 spi1, pwmc, efuse, pulse, dmac0, dmac1, nand, audio, usp0, usp1,
1033 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll,
1034 usb0, usb1, maxclk,
1035};
1036
1037static __initdata struct clk_hw* prima2_clk_hw_array[maxclk] = {
1038 NULL, /* dummy */
1039 NULL,
1040 &clk_pll1.hw,
1041 &clk_pll2.hw,
1042 &clk_pll3.hw,
1043 &clk_mem.hw,
1044 &clk_sys.hw,
1045 &clk_security.hw,
1046 &clk_dsp.hw,
1047 &clk_gps.hw,
1048 &clk_mf.hw,
1049 &clk_io.hw,
1050 &clk_cpu.hw,
1051 &clk_uart0.hw,
1052 &clk_uart1.hw,
1053 &clk_uart2.hw,
1054 &clk_tsc.hw,
1055 &clk_i2c0.hw,
1056 &clk_i2c1.hw,
1057 &clk_spi0.hw,
1058 &clk_spi1.hw,
1059 &clk_pwmc.hw,
1060 &clk_efuse.hw,
1061 &clk_pulse.hw,
1062 &clk_dmac0.hw,
1063 &clk_dmac1.hw,
1064 &clk_nand.hw,
1065 &clk_audio.hw,
1066 &clk_usp0.hw,
1067 &clk_usp1.hw,
1068 &clk_usp2.hw,
1069 &clk_vip.hw,
1070 &clk_gfx.hw,
1071 &clk_mm.hw,
1072 &clk_lcd.hw,
1073 &clk_vpp.hw,
1074 &clk_mmc01.hw,
1075 &clk_mmc23.hw,
1076 &clk_mmc45.hw,
1077 &usb_pll_clk_hw,
1078 &clk_usb0.hw,
1079 &clk_usb1.hw,
1080};
1081
1082static struct clk *prima2_clks[maxclk];
1083static struct clk_onecell_data clk_data;
1084
1028void __init sirfsoc_of_clk_init(void) 1085void __init sirfsoc_of_clk_init(void)
1029{ 1086{
1030 struct clk *clk;
1031 struct device_node *np; 1087 struct device_node *np;
1032 1088 int i;
1033 np = of_find_matching_node(NULL, clkc_ids);
1034 if (!np)
1035 panic("unable to find compatible clkc node in dtb\n");
1036
1037 sirfsoc_clk_vbase = of_iomap(np, 0);
1038 if (!sirfsoc_clk_vbase)
1039 panic("unable to map clkc registers\n");
1040
1041 of_node_put(np);
1042 1089
1043 np = of_find_matching_node(NULL, rsc_ids); 1090 np = of_find_matching_node(NULL, rsc_ids);
1044 if (!np) 1091 if (!np)
@@ -1050,122 +1097,30 @@ void __init sirfsoc_of_clk_init(void)
1050 1097
1051 of_node_put(np); 1098 of_node_put(np);
1052 1099
1100 np = of_find_matching_node(NULL, clkc_ids);
1101 if (!np)
1102 return;
1103
1104 sirfsoc_clk_vbase = of_iomap(np, 0);
1105 if (!sirfsoc_clk_vbase)
1106 panic("unable to map clkc registers\n");
1053 1107
1054 /* These are always available (RTC and 26MHz OSC)*/ 1108 /* These are always available (RTC and 26MHz OSC)*/
1055 clk = clk_register_fixed_rate(NULL, "rtc", NULL, 1109 prima2_clks[rtc] = clk_register_fixed_rate(NULL, "rtc", NULL,
1056 CLK_IS_ROOT, 32768); 1110 CLK_IS_ROOT, 32768);
1057 BUG_ON(IS_ERR(clk)); 1111 prima2_clks[osc]= clk_register_fixed_rate(NULL, "osc", NULL,
1058 clk = clk_register_fixed_rate(NULL, "osc", NULL,
1059 CLK_IS_ROOT, 26000000); 1112 CLK_IS_ROOT, 26000000);
1060 BUG_ON(IS_ERR(clk)); 1113
1061 1114 for (i = pll1; i < maxclk; i++) {
1062 clk = clk_register(NULL, &clk_pll1.hw); 1115 prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
1063 BUG_ON(IS_ERR(clk)); 1116 BUG_ON(!prima2_clks[i]);
1064 clk = clk_register(NULL, &clk_pll2.hw); 1117 }
1065 BUG_ON(IS_ERR(clk)); 1118 clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
1066 clk = clk_register(NULL, &clk_pll3.hw); 1119 clk_register_clkdev(prima2_clks[io], NULL, "io");
1067 BUG_ON(IS_ERR(clk)); 1120 clk_register_clkdev(prima2_clks[mem], NULL, "mem");
1068 clk = clk_register(NULL, &clk_mem.hw); 1121
1069 BUG_ON(IS_ERR(clk)); 1122 clk_data.clks = prima2_clks;
1070 clk = clk_register(NULL, &clk_sys.hw); 1123 clk_data.clk_num = maxclk;
1071 BUG_ON(IS_ERR(clk)); 1124
1072 clk = clk_register(NULL, &clk_security.hw); 1125 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1073 BUG_ON(IS_ERR(clk));
1074 clk_register_clkdev(clk, NULL, "b8030000.security");
1075 clk = clk_register(NULL, &clk_dsp.hw);
1076 BUG_ON(IS_ERR(clk));
1077 clk = clk_register(NULL, &clk_gps.hw);
1078 BUG_ON(IS_ERR(clk));
1079 clk_register_clkdev(clk, NULL, "a8010000.gps");
1080 clk = clk_register(NULL, &clk_mf.hw);
1081 BUG_ON(IS_ERR(clk));
1082 clk = clk_register(NULL, &clk_io.hw);
1083 BUG_ON(IS_ERR(clk));
1084 clk_register_clkdev(clk, NULL, "io");
1085 clk = clk_register(NULL, &clk_cpu.hw);
1086 BUG_ON(IS_ERR(clk));
1087 clk_register_clkdev(clk, NULL, "cpu");
1088 clk = clk_register(NULL, &clk_uart0.hw);
1089 BUG_ON(IS_ERR(clk));
1090 clk_register_clkdev(clk, NULL, "b0050000.uart");
1091 clk = clk_register(NULL, &clk_uart1.hw);
1092 BUG_ON(IS_ERR(clk));
1093 clk_register_clkdev(clk, NULL, "b0060000.uart");
1094 clk = clk_register(NULL, &clk_uart2.hw);
1095 BUG_ON(IS_ERR(clk));
1096 clk_register_clkdev(clk, NULL, "b0070000.uart");
1097 clk = clk_register(NULL, &clk_tsc.hw);
1098 BUG_ON(IS_ERR(clk));
1099 clk_register_clkdev(clk, NULL, "b0110000.tsc");
1100 clk = clk_register(NULL, &clk_i2c0.hw);
1101 BUG_ON(IS_ERR(clk));
1102 clk_register_clkdev(clk, NULL, "b00e0000.i2c");
1103 clk = clk_register(NULL, &clk_i2c1.hw);
1104 BUG_ON(IS_ERR(clk));
1105 clk_register_clkdev(clk, NULL, "b00f0000.i2c");
1106 clk = clk_register(NULL, &clk_spi0.hw);
1107 BUG_ON(IS_ERR(clk));
1108 clk_register_clkdev(clk, NULL, "b00d0000.spi");
1109 clk = clk_register(NULL, &clk_spi1.hw);
1110 BUG_ON(IS_ERR(clk));
1111 clk_register_clkdev(clk, NULL, "b0170000.spi");
1112 clk = clk_register(NULL, &clk_pwmc.hw);
1113 BUG_ON(IS_ERR(clk));
1114 clk_register_clkdev(clk, NULL, "b0130000.pwm");
1115 clk = clk_register(NULL, &clk_efuse.hw);
1116 BUG_ON(IS_ERR(clk));
1117 clk_register_clkdev(clk, NULL, "b0140000.efusesys");
1118 clk = clk_register(NULL, &clk_pulse.hw);
1119 BUG_ON(IS_ERR(clk));
1120 clk_register_clkdev(clk, NULL, "b0150000.pulsec");
1121 clk = clk_register(NULL, &clk_dmac0.hw);
1122 BUG_ON(IS_ERR(clk));
1123 clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
1124 clk = clk_register(NULL, &clk_dmac1.hw);
1125 BUG_ON(IS_ERR(clk));
1126 clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
1127 clk = clk_register(NULL, &clk_nand.hw);
1128 BUG_ON(IS_ERR(clk));
1129 clk_register_clkdev(clk, NULL, "b0030000.nand");
1130 clk = clk_register(NULL, &clk_audio.hw);
1131 BUG_ON(IS_ERR(clk));
1132 clk_register_clkdev(clk, NULL, "b0040000.audio");
1133 clk = clk_register(NULL, &clk_usp0.hw);
1134 BUG_ON(IS_ERR(clk));
1135 clk_register_clkdev(clk, NULL, "b0080000.usp");
1136 clk = clk_register(NULL, &clk_usp1.hw);
1137 BUG_ON(IS_ERR(clk));
1138 clk_register_clkdev(clk, NULL, "b0090000.usp");
1139 clk = clk_register(NULL, &clk_usp2.hw);
1140 BUG_ON(IS_ERR(clk));
1141 clk_register_clkdev(clk, NULL, "b00a0000.usp");
1142 clk = clk_register(NULL, &clk_vip.hw);
1143 BUG_ON(IS_ERR(clk));
1144 clk_register_clkdev(clk, NULL, "b00c0000.vip");
1145 clk = clk_register(NULL, &clk_gfx.hw);
1146 BUG_ON(IS_ERR(clk));
1147 clk_register_clkdev(clk, NULL, "98000000.graphics");
1148 clk = clk_register(NULL, &clk_mm.hw);
1149 BUG_ON(IS_ERR(clk));
1150 clk_register_clkdev(clk, NULL, "a0000000.multimedia");
1151 clk = clk_register(NULL, &clk_lcd.hw);
1152 BUG_ON(IS_ERR(clk));
1153 clk_register_clkdev(clk, NULL, "90010000.display");
1154 clk = clk_register(NULL, &clk_vpp.hw);
1155 BUG_ON(IS_ERR(clk));
1156 clk_register_clkdev(clk, NULL, "90020000.vpp");
1157 clk = clk_register(NULL, &clk_mmc01.hw);
1158 BUG_ON(IS_ERR(clk));
1159 clk = clk_register(NULL, &clk_mmc23.hw);
1160 BUG_ON(IS_ERR(clk));
1161 clk = clk_register(NULL, &clk_mmc45.hw);
1162 BUG_ON(IS_ERR(clk));
1163 clk = clk_register(NULL, &usb_pll_clk_hw);
1164 BUG_ON(IS_ERR(clk));
1165 clk = clk_register(NULL, &clk_usb0.hw);
1166 BUG_ON(IS_ERR(clk));
1167 clk_register_clkdev(clk, NULL, "b00e0000.usb");
1168 clk = clk_register(NULL, &clk_usb1.hw);
1169 BUG_ON(IS_ERR(clk));
1170 clk_register_clkdev(clk, NULL, "b00f0000.usb");
1171} 1126}
diff --git a/drivers/clk/clk-sunxi.c b/drivers/clk/clk-sunxi.c
deleted file mode 100644
index 0e831b584ba7..000000000000
--- a/drivers/clk/clk-sunxi.c
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/clk/sunxi.h>
20#include <linux/of.h>
21
22static const __initconst struct of_device_id clk_match[] = {
23 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
24 {}
25};
26
27void __init sunxi_init_clocks(void)
28{
29 of_clk_init(clk_match);
30}
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index fe25570874d6..b5538bba7a10 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -41,6 +41,7 @@ struct clk_device {
41 41
42#define PLL_TYPE_VT8500 0 42#define PLL_TYPE_VT8500 0
43#define PLL_TYPE_WM8650 1 43#define PLL_TYPE_WM8650 1
44#define PLL_TYPE_WM8750 2
44 45
45struct clk_pll { 46struct clk_pll {
46 struct clk_hw hw; 47 struct clk_hw hw;
@@ -121,7 +122,16 @@ static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
121 unsigned long *prate) 122 unsigned long *prate)
122{ 123{
123 struct clk_device *cdev = to_clk_device(hw); 124 struct clk_device *cdev = to_clk_device(hw);
124 u32 divisor = *prate / rate; 125 u32 divisor;
126
127 if (rate == 0)
128 return 0;
129
130 divisor = *prate / rate;
131
132 /* If prate / rate would be decimal, incr the divisor */
133 if (rate * divisor < *prate)
134 divisor++;
125 135
126 /* 136 /*
127 * If this is a request for SDMMC we have to adjust the divisor 137 * If this is a request for SDMMC we have to adjust the divisor
@@ -138,9 +148,18 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
138 unsigned long parent_rate) 148 unsigned long parent_rate)
139{ 149{
140 struct clk_device *cdev = to_clk_device(hw); 150 struct clk_device *cdev = to_clk_device(hw);
141 u32 divisor = parent_rate / rate; 151 u32 divisor;
142 unsigned long flags = 0; 152 unsigned long flags = 0;
143 153
154 if (rate == 0)
155 return 0;
156
157 divisor = parent_rate / rate;
158
159 /* If prate / rate would be decimal, incr the divisor */
160 if (rate * divisor < *prate)
161 divisor++;
162
144 if (divisor == cdev->div_mask + 1) 163 if (divisor == cdev->div_mask + 1)
145 divisor = 0; 164 divisor = 0;
146 165
@@ -272,7 +291,7 @@ static __init void vtwm_device_clk_init(struct device_node *node)
272 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 291 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
273 clk_register_clkdev(clk, clk_name, NULL); 292 clk_register_clkdev(clk, clk_name, NULL);
274} 293}
275 294CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
276 295
277/* PLL clock related functions */ 296/* PLL clock related functions */
278 297
@@ -298,6 +317,16 @@ static __init void vtwm_device_clk_init(struct device_node *node)
298#define WM8650_BITS_TO_VAL(m, d1, d2) \ 317#define WM8650_BITS_TO_VAL(m, d1, d2) \
299 ((d2 << 13) | (d1 << 10) | (m & 0x3FF)) 318 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
300 319
320/* Helper macros for PLL_WM8750 */
321#define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
322#define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
323
324#define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
325 (r * (m+1) / ((d1+1) * (1 << d2)))
326
327#define WM8750_BITS_TO_VAL(f, m, d1, d2) \
328 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
329
301 330
302static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, 331static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
303 u32 *multiplier, u32 *prediv) 332 u32 *multiplier, u32 *prediv)
@@ -361,16 +390,87 @@ static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
361 /* if we got here, it wasn't an exact match */ 390 /* if we got here, it wasn't an exact match */
362 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate, 391 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
363 rate - best_err); 392 rate - best_err);
364 *multiplier = mul; 393 *multiplier = best_mul;
365 *divisor1 = div1; 394 *divisor1 = best_div1;
366 *divisor2 = div2; 395 *divisor2 = best_div2;
396}
397
398static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
399{
400 /* calculate frequency (MHz) after pre-divisor */
401 u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
402
403 if ((freq < 10) || (freq > 200))
404 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
405 __func__, freq);
406
407 if (freq >= 166)
408 return 7;
409 else if (freq >= 104)
410 return 6;
411 else if (freq >= 65)
412 return 5;
413 else if (freq >= 42)
414 return 4;
415 else if (freq >= 26)
416 return 3;
417 else if (freq >= 16)
418 return 2;
419 else if (freq >= 10)
420 return 1;
421
422 return 0;
423}
424
425static void wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
426 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
427{
428 u32 mul, div1, div2;
429 u32 best_mul, best_div1, best_div2;
430 unsigned long tclk, rate_err, best_err;
431
432 best_err = (unsigned long)-1;
433
434 /* Find the closest match (lower or equal to requested) */
435 for (div1 = 1; div1 >= 0; div1--)
436 for (div2 = 7; div2 >= 0; div2--)
437 for (mul = 0; mul <= 255; mul++) {
438 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
439 if (tclk > rate)
440 continue;
441 /* error will always be +ve */
442 rate_err = rate - tclk;
443 if (rate_err == 0) {
444 *filter = wm8750_get_filter(parent_rate, div1);
445 *multiplier = mul;
446 *divisor1 = div1;
447 *divisor2 = div2;
448 return;
449 }
450
451 if (rate_err < best_err) {
452 best_err = rate_err;
453 best_mul = mul;
454 best_div1 = div1;
455 best_div2 = div2;
456 }
457 }
458
459 /* if we got here, it wasn't an exact match */
460 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
461 rate - best_err);
462
463 *filter = wm8750_get_filter(parent_rate, best_div1);
464 *multiplier = best_mul;
465 *divisor1 = best_div1;
466 *divisor2 = best_div2;
367} 467}
368 468
369static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, 469static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
370 unsigned long parent_rate) 470 unsigned long parent_rate)
371{ 471{
372 struct clk_pll *pll = to_clk_pll(hw); 472 struct clk_pll *pll = to_clk_pll(hw);
373 u32 mul, div1, div2; 473 u32 filter, mul, div1, div2;
374 u32 pll_val; 474 u32 pll_val;
375 unsigned long flags = 0; 475 unsigned long flags = 0;
376 476
@@ -385,6 +485,9 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
385 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2); 485 wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
386 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); 486 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
387 break; 487 break;
488 case PLL_TYPE_WM8750:
489 wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
490 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
388 default: 491 default:
389 pr_err("%s: invalid pll type\n", __func__); 492 pr_err("%s: invalid pll type\n", __func__);
390 return 0; 493 return 0;
@@ -405,7 +508,7 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
405 unsigned long *prate) 508 unsigned long *prate)
406{ 509{
407 struct clk_pll *pll = to_clk_pll(hw); 510 struct clk_pll *pll = to_clk_pll(hw);
408 u32 mul, div1, div2; 511 u32 filter, mul, div1, div2;
409 long round_rate; 512 long round_rate;
410 513
411 switch (pll->type) { 514 switch (pll->type) {
@@ -417,6 +520,9 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
417 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2); 520 wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
418 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2); 521 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
419 break; 522 break;
523 case PLL_TYPE_WM8750:
524 wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
525 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
420 default: 526 default:
421 round_rate = 0; 527 round_rate = 0;
422 } 528 }
@@ -440,6 +546,10 @@ static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
440 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val); 546 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
441 pll_freq /= WM8650_PLL_DIV(pll_val); 547 pll_freq /= WM8650_PLL_DIV(pll_val);
442 break; 548 break;
549 case PLL_TYPE_WM8750:
550 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
551 pll_freq /= WM8750_PLL_DIV(pll_val);
552 break;
443 default: 553 default:
444 pll_freq = 0; 554 pll_freq = 0;
445 } 555 }
@@ -502,20 +612,19 @@ static void __init vt8500_pll_init(struct device_node *node)
502{ 612{
503 vtwm_pll_clk_init(node, PLL_TYPE_VT8500); 613 vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
504} 614}
615CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
505 616
506static void __init wm8650_pll_init(struct device_node *node) 617static void __init wm8650_pll_init(struct device_node *node)
507{ 618{
508 vtwm_pll_clk_init(node, PLL_TYPE_WM8650); 619 vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
509} 620}
621CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
510 622
511static const __initconst struct of_device_id clk_match[] = { 623static void __init wm8750_pll_init(struct device_node *node)
512 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, 624{
513 { .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, }, 625 vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
514 { .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, }, 626}
515 { .compatible = "via,vt8500-device-clock", 627CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
516 .data = vtwm_device_clk_init, },
517 { /* sentinel */ }
518};
519 628
520void __init vtwm_clk_init(void __iomem *base) 629void __init vtwm_clk_init(void __iomem *base)
521{ 630{
@@ -524,5 +633,5 @@ void __init vtwm_clk_init(void __iomem *base)
524 633
525 pmc_base = base; 634 pmc_base = base;
526 635
527 of_clk_init(clk_match); 636 of_clk_init(NULL);
528} 637}
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
index 37a30514fd66..b14a25f39255 100644
--- a/drivers/clk/clk-zynq.c
+++ b/drivers/clk/clk-zynq.c
@@ -81,6 +81,7 @@ static void __init zynq_pll_clk_setup(struct device_node *np)
81 if (WARN_ON(ret)) 81 if (WARN_ON(ret))
82 return; 82 return;
83} 83}
84CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
84 85
85struct zynq_periph_clk { 86struct zynq_periph_clk {
86 struct clk_hw hw; 87 struct clk_hw hw;
@@ -187,6 +188,7 @@ static void __init zynq_periph_clk_setup(struct device_node *np)
187 if (WARN_ON(err)) 188 if (WARN_ON(err))
188 return; 189 return;
189} 190}
191CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
190 192
191/* CPU Clock domain is modelled as a mux with 4 children subclks, whose 193/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
192 * derivative rates depend on CLK_621_TRUE 194 * derivative rates depend on CLK_621_TRUE
@@ -366,18 +368,10 @@ static void __init zynq_cpu_clk_setup(struct device_node *np)
366 if (WARN_ON(err)) 368 if (WARN_ON(err))
367 return; 369 return;
368} 370}
369 371CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
370static const __initconst struct of_device_id zynq_clk_match[] = {
371 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
372 { .compatible = "xlnx,zynq-pll", .data = zynq_pll_clk_setup, },
373 { .compatible = "xlnx,zynq-periph-clock",
374 .data = zynq_periph_clk_setup, },
375 { .compatible = "xlnx,zynq-cpu-clock", .data = zynq_cpu_clk_setup, },
376 {}
377};
378 372
379void __init xilinx_zynq_clocks_init(void __iomem *slcr) 373void __init xilinx_zynq_clocks_init(void __iomem *slcr)
380{ 374{
381 slcr_base = slcr; 375 slcr_base = slcr;
382 of_clk_init(zynq_clk_match); 376 of_clk_init(NULL);
383} 377}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 251e45d6024d..fabbfe1a9253 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -18,6 +18,7 @@
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/device.h> 20#include <linux/device.h>
21#include <linux/init.h>
21 22
22static DEFINE_SPINLOCK(enable_lock); 23static DEFINE_SPINLOCK(enable_lock);
23static DEFINE_MUTEX(prepare_lock); 24static DEFINE_MUTEX(prepare_lock);
@@ -35,6 +36,137 @@ static struct dentry *rootdir;
35static struct dentry *orphandir; 36static struct dentry *orphandir;
36static int inited = 0; 37static int inited = 0;
37 38
39static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
40{
41 if (!c)
42 return;
43
44 seq_printf(s, "%*s%-*s %-11d %-12d %-10lu",
45 level * 3 + 1, "",
46 30 - level * 3, c->name,
47 c->enable_count, c->prepare_count, c->rate);
48 seq_printf(s, "\n");
49}
50
51static void clk_summary_show_subtree(struct seq_file *s, struct clk *c,
52 int level)
53{
54 struct clk *child;
55 struct hlist_node *tmp;
56
57 if (!c)
58 return;
59
60 clk_summary_show_one(s, c, level);
61
62 hlist_for_each_entry(child, tmp, &c->children, child_node)
63 clk_summary_show_subtree(s, child, level + 1);
64}
65
66static int clk_summary_show(struct seq_file *s, void *data)
67{
68 struct clk *c;
69 struct hlist_node *tmp;
70
71 seq_printf(s, " clock enable_cnt prepare_cnt rate\n");
72 seq_printf(s, "---------------------------------------------------------------------\n");
73
74 mutex_lock(&prepare_lock);
75
76 hlist_for_each_entry(c, tmp, &clk_root_list, child_node)
77 clk_summary_show_subtree(s, c, 0);
78
79 hlist_for_each_entry(c, tmp, &clk_orphan_list, child_node)
80 clk_summary_show_subtree(s, c, 0);
81
82 mutex_unlock(&prepare_lock);
83
84 return 0;
85}
86
87
88static int clk_summary_open(struct inode *inode, struct file *file)
89{
90 return single_open(file, clk_summary_show, inode->i_private);
91}
92
93static const struct file_operations clk_summary_fops = {
94 .open = clk_summary_open,
95 .read = seq_read,
96 .llseek = seq_lseek,
97 .release = single_release,
98};
99
100static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
101{
102 if (!c)
103 return;
104
105 seq_printf(s, "\"%s\": { ", c->name);
106 seq_printf(s, "\"enable_count\": %d,", c->enable_count);
107 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
108 seq_printf(s, "\"rate\": %lu", c->rate);
109}
110
111static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
112{
113 struct clk *child;
114 struct hlist_node *tmp;
115
116 if (!c)
117 return;
118
119 clk_dump_one(s, c, level);
120
121 hlist_for_each_entry(child, tmp, &c->children, child_node) {
122 seq_printf(s, ",");
123 clk_dump_subtree(s, child, level + 1);
124 }
125
126 seq_printf(s, "}");
127}
128
129static int clk_dump(struct seq_file *s, void *data)
130{
131 struct clk *c;
132 struct hlist_node *tmp;
133 bool first_node = true;
134
135 seq_printf(s, "{");
136
137 mutex_lock(&prepare_lock);
138
139 hlist_for_each_entry(c, tmp, &clk_root_list, child_node) {
140 if (!first_node)
141 seq_printf(s, ",");
142 first_node = false;
143 clk_dump_subtree(s, c, 0);
144 }
145
146 hlist_for_each_entry(c, tmp, &clk_orphan_list, child_node) {
147 seq_printf(s, ",");
148 clk_dump_subtree(s, c, 0);
149 }
150
151 mutex_unlock(&prepare_lock);
152
153 seq_printf(s, "}");
154 return 0;
155}
156
157
158static int clk_dump_open(struct inode *inode, struct file *file)
159{
160 return single_open(file, clk_dump, inode->i_private);
161}
162
163static const struct file_operations clk_dump_fops = {
164 .open = clk_dump_open,
165 .read = seq_read,
166 .llseek = seq_lseek,
167 .release = single_release,
168};
169
38/* caller must hold prepare_lock */ 170/* caller must hold prepare_lock */
39static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry) 171static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
40{ 172{
@@ -168,12 +300,23 @@ static int __init clk_debug_init(void)
168{ 300{
169 struct clk *clk; 301 struct clk *clk;
170 struct hlist_node *tmp; 302 struct hlist_node *tmp;
303 struct dentry *d;
171 304
172 rootdir = debugfs_create_dir("clk", NULL); 305 rootdir = debugfs_create_dir("clk", NULL);
173 306
174 if (!rootdir) 307 if (!rootdir)
175 return -ENOMEM; 308 return -ENOMEM;
176 309
310 d = debugfs_create_file("clk_summary", S_IRUGO, rootdir, NULL,
311 &clk_summary_fops);
312 if (!d)
313 return -ENOMEM;
314
315 d = debugfs_create_file("clk_dump", S_IRUGO, rootdir, NULL,
316 &clk_dump_fops);
317 if (!d)
318 return -ENOMEM;
319
177 orphandir = debugfs_create_dir("orphans", rootdir); 320 orphandir = debugfs_create_dir("orphans", rootdir);
178 321
179 if (!orphandir) 322 if (!orphandir)
@@ -259,32 +402,33 @@ late_initcall(clk_disable_unused);
259 402
260/*** helper functions ***/ 403/*** helper functions ***/
261 404
262inline const char *__clk_get_name(struct clk *clk) 405const char *__clk_get_name(struct clk *clk)
263{ 406{
264 return !clk ? NULL : clk->name; 407 return !clk ? NULL : clk->name;
265} 408}
409EXPORT_SYMBOL_GPL(__clk_get_name);
266 410
267inline struct clk_hw *__clk_get_hw(struct clk *clk) 411struct clk_hw *__clk_get_hw(struct clk *clk)
268{ 412{
269 return !clk ? NULL : clk->hw; 413 return !clk ? NULL : clk->hw;
270} 414}
271 415
272inline u8 __clk_get_num_parents(struct clk *clk) 416u8 __clk_get_num_parents(struct clk *clk)
273{ 417{
274 return !clk ? 0 : clk->num_parents; 418 return !clk ? 0 : clk->num_parents;
275} 419}
276 420
277inline struct clk *__clk_get_parent(struct clk *clk) 421struct clk *__clk_get_parent(struct clk *clk)
278{ 422{
279 return !clk ? NULL : clk->parent; 423 return !clk ? NULL : clk->parent;
280} 424}
281 425
282inline unsigned int __clk_get_enable_count(struct clk *clk) 426unsigned int __clk_get_enable_count(struct clk *clk)
283{ 427{
284 return !clk ? 0 : clk->enable_count; 428 return !clk ? 0 : clk->enable_count;
285} 429}
286 430
287inline unsigned int __clk_get_prepare_count(struct clk *clk) 431unsigned int __clk_get_prepare_count(struct clk *clk)
288{ 432{
289 return !clk ? 0 : clk->prepare_count; 433 return !clk ? 0 : clk->prepare_count;
290} 434}
@@ -310,7 +454,7 @@ out:
310 return ret; 454 return ret;
311} 455}
312 456
313inline unsigned long __clk_get_flags(struct clk *clk) 457unsigned long __clk_get_flags(struct clk *clk)
314{ 458{
315 return !clk ? 0 : clk->flags; 459 return !clk ? 0 : clk->flags;
316} 460}
@@ -950,9 +1094,6 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
950 /* change the rates */ 1094 /* change the rates */
951 clk_change_rate(top); 1095 clk_change_rate(top);
952 1096
953 mutex_unlock(&prepare_lock);
954
955 return 0;
956out: 1097out:
957 mutex_unlock(&prepare_lock); 1098 mutex_unlock(&prepare_lock);
958 1099
@@ -1663,6 +1804,11 @@ struct of_clk_provider {
1663 void *data; 1804 void *data;
1664}; 1805};
1665 1806
1807extern struct of_device_id __clk_of_table[];
1808
1809static const struct of_device_id __clk_of_table_sentinel
1810 __used __section(__clk_of_table_end);
1811
1666static LIST_HEAD(of_clk_providers); 1812static LIST_HEAD(of_clk_providers);
1667static DEFINE_MUTEX(of_clk_lock); 1813static DEFINE_MUTEX(of_clk_lock);
1668 1814
@@ -1791,6 +1937,9 @@ void __init of_clk_init(const struct of_device_id *matches)
1791{ 1937{
1792 struct device_node *np; 1938 struct device_node *np;
1793 1939
1940 if (!matches)
1941 matches = __clk_of_table;
1942
1794 for_each_matching_node(np, matches) { 1943 for_each_matching_node(np, matches) {
1795 const struct of_device_id *match = of_match_node(matches, np); 1944 const struct of_device_id *match = of_match_node(matches, np);
1796 of_clk_init_cb_t clk_init_cb = match->data; 1945 of_clk_init_cb_t clk_init_cb = match->data;
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 8dd476e2a9c5..b5c06f9766f6 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -99,7 +99,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
99int __init mx23_clocks_init(void) 99int __init mx23_clocks_init(void)
100{ 100{
101 struct device_node *np; 101 struct device_node *np;
102 int i; 102 u32 i;
103 103
104 clk_misc_init(); 104 clk_misc_init();
105 105
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index db3af0874121..126370a62ce2 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -154,7 +154,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
154int __init mx28_clocks_init(void) 154int __init mx28_clocks_init(void)
155{ 155{
156 struct device_node *np; 156 struct device_node *np;
157 int i; 157 u32 i;
158 158
159 clk_misc_init(); 159 clk_misc_init();
160 160
diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c
index dcb6ae0a0425..256c8be74df8 100644
--- a/drivers/clk/versatile/clk-vexpress-osc.c
+++ b/drivers/clk/versatile/clk-vexpress-osc.c
@@ -144,3 +144,4 @@ error:
144 vexpress_config_func_put(osc->func); 144 vexpress_config_func_put(osc->func);
145 kfree(osc); 145 kfree(osc);
146} 146}
147CLK_OF_DECLARE(vexpress_soc, "arm,vexpress-osc", vexpress_osc_of_setup);
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
index c742ac7c60bb..f889f2f07b37 100644
--- a/drivers/clk/versatile/clk-vexpress.c
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -99,19 +99,13 @@ struct clk *vexpress_sp810_of_get(struct of_phandle_args *clkspec, void *data)
99 return vexpress_sp810_timerclken[clkspec->args[0]]; 99 return vexpress_sp810_timerclken[clkspec->args[0]];
100} 100}
101 101
102static const __initconst struct of_device_id vexpress_fixed_clk_match[] = {
103 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
104 { .compatible = "arm,vexpress-osc", .data = vexpress_osc_of_setup, },
105 {}
106};
107
108void __init vexpress_clk_of_init(void) 102void __init vexpress_clk_of_init(void)
109{ 103{
110 struct device_node *node; 104 struct device_node *node;
111 struct clk *clk; 105 struct clk *clk;
112 struct clk *refclk, *timclk; 106 struct clk *refclk, *timclk;
113 107
114 of_clk_init(vexpress_fixed_clk_match); 108 of_clk_init(NULL);
115 109
116 node = of_find_compatible_node(NULL, NULL, "arm,sp810"); 110 node = of_find_compatible_node(NULL, NULL, "arm,sp810");
117 vexpress_sp810_init(of_iomap(node, 0)); 111 vexpress_sp810_init(of_iomap(node, 0));
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
index 3cd1bd3d7aee..93d09d0e009f 100644
--- a/drivers/clocksource/sunxi_timer.c
+++ b/drivers/clocksource/sunxi_timer.c
@@ -23,7 +23,7 @@
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/of_irq.h> 24#include <linux/of_irq.h>
25#include <linux/sunxi_timer.h> 25#include <linux/sunxi_timer.h>
26#include <linux/clk/sunxi.h> 26#include <linux/clk-provider.h>
27 27
28#define TIMER_CTL_REG 0x00 28#define TIMER_CTL_REG 0x00
29#define TIMER_CTL_ENABLE (1 << 0) 29#define TIMER_CTL_ENABLE (1 << 0)
@@ -124,7 +124,7 @@ static void __init sunxi_timer_init(void)
124 if (irq <= 0) 124 if (irq <= 0)
125 panic("Can't parse IRQ"); 125 panic("Can't parse IRQ");
126 126
127 sunxi_init_clocks(); 127 of_clk_init(NULL);
128 128
129 clk = of_clk_get(node, 0); 129 clk = of_clk_get(node, 0);
130 if (IS_ERR(clk)) 130 if (IS_ERR(clk))
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index d1ea7ce0b4cb..c1fe60ad1540 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -150,6 +150,15 @@
150#endif 150#endif
151 151
152 152
153#ifdef CONFIG_COMMON_CLK
154#define CLK_OF_TABLES() . = ALIGN(8); \
155 VMLINUX_SYMBOL(__clk_of_table) = .; \
156 *(__clk_of_table) \
157 *(__clk_of_table_end)
158#else
159#define CLK_OF_TABLES()
160#endif
161
153#define KERNEL_DTB() \ 162#define KERNEL_DTB() \
154 STRUCT_ALIGN(); \ 163 STRUCT_ALIGN(); \
155 VMLINUX_SYMBOL(__dtb_start) = .; \ 164 VMLINUX_SYMBOL(__dtb_start) = .; \
@@ -493,6 +502,7 @@
493 DEV_DISCARD(init.rodata) \ 502 DEV_DISCARD(init.rodata) \
494 CPU_DISCARD(init.rodata) \ 503 CPU_DISCARD(init.rodata) \
495 MEM_DISCARD(init.rodata) \ 504 MEM_DISCARD(init.rodata) \
505 CLK_OF_TABLES() \
496 KERNEL_DTB() 506 KERNEL_DTB()
497 507
498#define INIT_TEXT \ 508#define INIT_TEXT \
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 4989b8a7bed1..7f197d7addb0 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -379,7 +379,13 @@ struct clk_onecell_data {
379}; 379};
380struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); 380struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
381const char *of_clk_get_parent_name(struct device_node *np, int index); 381const char *of_clk_get_parent_name(struct device_node *np, int index);
382
382void of_clk_init(const struct of_device_id *matches); 383void of_clk_init(const struct of_device_id *matches);
383 384
385#define CLK_OF_DECLARE(name, compat, fn) \
386 static const struct of_device_id __clk_of_table_##name \
387 __used __section(__clk_of_table) \
388 = { .compatible = compat, .data = fn };
389
384#endif /* CONFIG_COMMON_CLK */ 390#endif /* CONFIG_COMMON_CLK */
385#endif /* CLK_PROVIDER_H */ 391#endif /* CLK_PROVIDER_H */
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
deleted file mode 100644
index e074fdd5a236..000000000000
--- a/include/linux/clk/sunxi.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __LINUX_CLK_SUNXI_H_
18#define __LINUX_CLK_SUNXI_H_
19
20void __init sunxi_init_clocks(void);
21
22#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-02 15:28:42 -0500