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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-03-03 11:48:53 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-03-03 11:48:53 -0500
commit07af427606667c304a2e965cd51d2c03642e8cae (patch)
treeb6ae434b49d14aa2fde153e815a8e0e34860a116
parentfab59375b9543f84d1714f7dd00f5d11e531bd3e (diff)
piix/slc90e66: more tuneproc() fixing (take 2)
The tuneproc() method in both these drivers failed to set the drive's own speed. Fix this by renaming the function and "wrapping around it" the new tuneproc() method. Switch back to calling tuneproc() in the PIO fallback code. While at it, also convert the rest of the PIO timing code into proper C. :-) Has been kind of tested on SLC90E66. I'm too lazy to reboot my box and test on ICH4... :-) [ bart: I quickly tested it on ICH4. ] Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
-rw-r--r--drivers/ide/pci/piix.c49
-rw-r--r--drivers/ide/pci/slc90e66.c38
2 files changed, 50 insertions, 37 deletions
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
index 569822f4cf55..061d300ab8be 100644
--- a/drivers/ide/pci/piix.c
+++ b/drivers/ide/pci/piix.c
@@ -1,10 +1,10 @@
1/* 1/*
2 * linux/drivers/ide/pci/piix.c Version 0.46 December 3, 2006 2 * linux/drivers/ide/pci/piix.c Version 0.47 February 8, 2007
3 * 3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer 4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> 6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> 7 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
8 * 8 *
9 * May be copied or modified under the terms of the GNU General Public License 9 * May be copied or modified under the terms of the GNU General Public License
10 * 10 *
@@ -205,14 +205,13 @@ static u8 piix_dma_2_pio (u8 xfer_rate) {
205} 205}
206 206
207/** 207/**
208 * piix_tune_drive - tune a drive attached to a PIIX 208 * piix_tune_pio - tune PIIX for PIO mode
209 * @drive: drive to tune 209 * @drive: drive to tune
210 * @pio: desired PIO mode 210 * @pio: desired PIO mode
211 * 211 *
212 * Set the interface PIO mode based upon the settings done by AMI BIOS 212 * Set the interface PIO mode based upon the settings done by AMI BIOS.
213 * (might be useful if drive is not registered in CMOS for any reason).
214 */ 213 */
215static void piix_tune_drive (ide_drive_t *drive, u8 pio) 214static void piix_tune_pio (ide_drive_t *drive, u8 pio)
216{ 215{
217 ide_hwif_t *hwif = HWIF(drive); 216 ide_hwif_t *hwif = HWIF(drive);
218 struct pci_dev *dev = hwif->pci_dev; 217 struct pci_dev *dev = hwif->pci_dev;
@@ -233,8 +232,6 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
233 { 2, 1 }, 232 { 2, 1 },
234 { 2, 3 }, }; 233 { 2, 3 }, };
235 234
236 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
237
238 /* 235 /*
239 * Master vs slave is synchronized above us but the slave register is 236 * Master vs slave is synchronized above us but the slave register is
240 * shared by the two hwifs so the corner case of two slave timeouts in 237 * shared by the two hwifs so the corner case of two slave timeouts in
@@ -253,19 +250,20 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
253 master_data |= 0x4000; 250 master_data |= 0x4000;
254 master_data &= ~0x0070; 251 master_data &= ~0x0070;
255 if (pio > 1) { 252 if (pio > 1) {
256 /* enable PPE, IE and TIME */ 253 /* Set PPE, IE and TIME */
257 master_data = master_data | (control << 4); 254 master_data |= control << 4;
258 } 255 }
259 pci_read_config_byte(dev, slave_port, &slave_data); 256 pci_read_config_byte(dev, slave_port, &slave_data);
260 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); 257 slave_data &= hwif->channel ? 0x0f : 0xf0;
261 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); 258 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
259 (hwif->channel ? 4 : 0);
262 } else { 260 } else {
263 master_data &= ~0x3307; 261 master_data &= ~0x3307;
264 if (pio > 1) { 262 if (pio > 1) {
265 /* enable PPE, IE and TIME */ 263 /* enable PPE, IE and TIME */
266 master_data = master_data | control; 264 master_data |= control;
267 } 265 }
268 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); 266 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
269 } 267 }
270 pci_write_config_word(dev, master_port, master_data); 268 pci_write_config_word(dev, master_port, master_data);
271 if (is_slave) 269 if (is_slave)
@@ -274,6 +272,21 @@ static void piix_tune_drive (ide_drive_t *drive, u8 pio)
274} 272}
275 273
276/** 274/**
275 * piix_tune_drive - tune a drive attached to PIIX
276 * @drive: drive to tune
277 * @pio: desired PIO mode
278 *
279 * Set the drive's PIO mode (might be useful if drive is not registered
280 * in CMOS for any reason).
281 */
282static void piix_tune_drive (ide_drive_t *drive, u8 pio)
283{
284 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
285 piix_tune_pio(drive, pio);
286 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
287}
288
289/**
277 * piix_tune_chipset - tune a PIIX interface 290 * piix_tune_chipset - tune a PIIX interface
278 * @drive: IDE drive to tune 291 * @drive: IDE drive to tune
279 * @xferspeed: speed to configure 292 * @xferspeed: speed to configure
@@ -348,8 +361,8 @@ static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
348 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag); 361 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
349 } 362 }
350 363
351 piix_tune_drive(drive, piix_dma_2_pio(speed)); 364 piix_tune_pio(drive, piix_dma_2_pio(speed));
352 return (ide_config_drive_speed(drive, speed)); 365 return ide_config_drive_speed(drive, speed);
353} 366}
354 367
355/** 368/**
@@ -392,9 +405,7 @@ static int piix_config_drive_xfer_rate (ide_drive_t *drive)
392 return 0; 405 return 0;
393 406
394 if (ide_use_fast_pio(drive)) 407 if (ide_use_fast_pio(drive))
395 /* Find best PIO mode. */ 408 piix_tune_drive(drive, 255);
396 piix_tune_chipset(drive, XFER_PIO_0 +
397 ide_get_best_pio_mode(drive, 255, 4, NULL));
398 409
399 return -1; 410 return -1;
400} 411}
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
index ae7eb58d961c..852ccb36da1d 100644
--- a/drivers/ide/pci/slc90e66.c
+++ b/drivers/ide/pci/slc90e66.c
@@ -1,8 +1,8 @@
1/* 1/*
2 * linux/drivers/ide/pci/slc90e66.c Version 0.13 December 30, 2006 2 * linux/drivers/ide/pci/slc90e66.c Version 0.14 February 8, 2007
3 * 3 *
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006 MontaVista Software, Inc. <source@mvista.com> 5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
6 * 6 *
7 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66, 7 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
8 * but this keeps the ISA-Bridge and slots alive. 8 * but this keeps the ISA-Bridge and slots alive.
@@ -57,11 +57,7 @@ static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
57 } 57 }
58} 58}
59 59
60/* 60static void slc90e66_tune_pio (ide_drive_t *drive, u8 pio)
61 * Based on settings done by AMI BIOS
62 * (might be useful if drive is not registered in CMOS for any reason).
63 */
64static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
65{ 61{
66 ide_hwif_t *hwif = HWIF(drive); 62 ide_hwif_t *hwif = HWIF(drive);
67 struct pci_dev *dev = hwif->pci_dev; 63 struct pci_dev *dev = hwif->pci_dev;
@@ -80,7 +76,6 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
80 { 2, 1 }, 76 { 2, 1 },
81 { 2, 3 }, }; 77 { 2, 3 }, };
82 78
83 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
84 spin_lock_irqsave(&ide_lock, flags); 79 spin_lock_irqsave(&ide_lock, flags);
85 pci_read_config_word(dev, master_port, &master_data); 80 pci_read_config_word(dev, master_port, &master_data);
86 81
@@ -94,19 +89,20 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
94 master_data |= 0x4000; 89 master_data |= 0x4000;
95 master_data &= ~0x0070; 90 master_data &= ~0x0070;
96 if (pio > 1) { 91 if (pio > 1) {
97 /* enable PPE, IE and TIME */ 92 /* Set PPE, IE and TIME */
98 master_data = master_data | (control << 4); 93 master_data |= control << 4;
99 } 94 }
100 pci_read_config_byte(dev, slave_port, &slave_data); 95 pci_read_config_byte(dev, slave_port, &slave_data);
101 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0); 96 slave_data &= hwif->channel ? 0x0f : 0xf0;
102 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0)); 97 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
98 (hwif->channel ? 4 : 0);
103 } else { 99 } else {
104 master_data &= ~0x3307; 100 master_data &= ~0x3307;
105 if (pio > 1) { 101 if (pio > 1) {
106 /* enable PPE, IE and TIME */ 102 /* enable PPE, IE and TIME */
107 master_data = master_data | control; 103 master_data |= control;
108 } 104 }
109 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8); 105 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
110 } 106 }
111 pci_write_config_word(dev, master_port, master_data); 107 pci_write_config_word(dev, master_port, master_data);
112 if (is_slave) 108 if (is_slave)
@@ -114,6 +110,13 @@ static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
114 spin_unlock_irqrestore(&ide_lock, flags); 110 spin_unlock_irqrestore(&ide_lock, flags);
115} 111}
116 112
113static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
114{
115 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
116 slc90e66_tune_pio(drive, pio);
117 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
118}
119
117static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed) 120static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
118{ 121{
119 ide_hwif_t *hwif = HWIF(drive); 122 ide_hwif_t *hwif = HWIF(drive);
@@ -162,8 +165,8 @@ static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
162 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed); 165 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
163 } 166 }
164 167
165 slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed)); 168 slc90e66_tune_pio(drive, slc90e66_dma_2_pio(speed));
166 return (ide_config_drive_speed(drive, speed)); 169 return ide_config_drive_speed(drive, speed);
167} 170}
168 171
169static int slc90e66_config_drive_for_dma (ide_drive_t *drive) 172static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
@@ -185,8 +188,7 @@ static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
185 return 0; 188 return 0;
186 189
187 if (ide_use_fast_pio(drive)) 190 if (ide_use_fast_pio(drive))
188 (void)slc90e66_tune_chipset(drive, XFER_PIO_0 + 191 slc90e66_tune_drive(drive, 255);
189 ide_get_best_pio_mode(drive, 255, 4, NULL));
190 192
191 return -1; 193 return -1;
192} 194}