diff options
| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-05 05:35:33 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-05 05:35:33 -0500 |
| commit | 0719dc341389882cc834ed18fc9b7fc6006b2b85 (patch) | |
| tree | 794480ac62c07ea8cc4e69c2cb3d2b83bb7f36b7 | |
| parent | e28edb723e64200554194da17617ee6e82de6690 (diff) | |
| parent | 677f4f64e4b2336682f0e15c69b206ade6f6b131 (diff) | |
Merge branch 'devel-stable' into devel
337 files changed, 16393 insertions, 3369 deletions
diff --git a/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt b/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt index 26422f0f9080..b87292e05f2f 100644 --- a/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt +++ b/Documentation/arm/Samsung-S3C24XX/EB2410ITX.txt | |||
| @@ -55,4 +55,4 @@ Maintainers | |||
| 55 | This board is maintained by Simtec Electronics. | 55 | This board is maintained by Simtec Electronics. |
| 56 | 56 | ||
| 57 | 57 | ||
| 58 | (c) 2004 Ben Dooks, Simtec Electronics | 58 | Copyright 2004 Ben Dooks, Simtec Electronics |
diff --git a/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/Documentation/arm/Samsung-S3C24XX/GPIO.txt index 948c8718d967..2af2cf39915f 100644 --- a/Documentation/arm/Samsung-S3C24XX/GPIO.txt +++ b/Documentation/arm/Samsung-S3C24XX/GPIO.txt | |||
| @@ -134,4 +134,4 @@ Authour | |||
| 134 | 134 | ||
| 135 | 135 | ||
| 136 | Ben Dooks, 03 October 2004 | 136 | Ben Dooks, 03 October 2004 |
| 137 | (c) 2004 Ben Dooks, Simtec Electronics | 137 | Copyright 2004 Ben Dooks, Simtec Electronics |
diff --git a/Documentation/arm/Samsung-S3C24XX/Overview.txt b/Documentation/arm/Samsung-S3C24XX/Overview.txt index cff6227b4484..081892df4fda 100644 --- a/Documentation/arm/Samsung-S3C24XX/Overview.txt +++ b/Documentation/arm/Samsung-S3C24XX/Overview.txt | |||
| @@ -299,4 +299,4 @@ Port Contributors | |||
| 299 | Document Author | 299 | Document Author |
| 300 | --------------- | 300 | --------------- |
| 301 | 301 | ||
| 302 | Ben Dooks, (c) 2004-2005,2006 Simtec Electronics | 302 | Ben Dooks, Copyright 2004-2006 Simtec Electronics |
diff --git a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt index 295d971a15ed..f057876b920b 100644 --- a/Documentation/arm/Samsung-S3C24XX/S3C2412.txt +++ b/Documentation/arm/Samsung-S3C24XX/S3C2412.txt | |||
| @@ -117,4 +117,4 @@ ATA | |||
| 117 | Document Author | 117 | Document Author |
| 118 | --------------- | 118 | --------------- |
| 119 | 119 | ||
| 120 | Ben Dooks, (c) 2006 Simtec Electronics | 120 | Ben Dooks, Copyright 2006 Simtec Electronics |
diff --git a/Documentation/arm/Samsung-S3C24XX/S3C2413.txt b/Documentation/arm/Samsung-S3C24XX/S3C2413.txt index ab2a88858f12..909bdc7dd7b5 100644 --- a/Documentation/arm/Samsung-S3C24XX/S3C2413.txt +++ b/Documentation/arm/Samsung-S3C24XX/S3C2413.txt | |||
| @@ -18,4 +18,4 @@ Camera Interface | |||
| 18 | Document Author | 18 | Document Author |
| 19 | --------------- | 19 | --------------- |
| 20 | 20 | ||
| 21 | Ben Dooks, (c) 2006 Simtec Electronics | 21 | Ben Dooks, Copyright 2006 Simtec Electronics |
diff --git a/Documentation/arm/Samsung-S3C24XX/Suspend.txt b/Documentation/arm/Samsung-S3C24XX/Suspend.txt index a30fe510572b..7edd0e2e6c5b 100644 --- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt +++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt | |||
| @@ -133,5 +133,5 @@ Configuration | |||
| 133 | Document Author | 133 | Document Author |
| 134 | --------------- | 134 | --------------- |
| 135 | 135 | ||
| 136 | Ben Dooks, (c) 2004 Simtec Electronics | 136 | Ben Dooks, Copyright 2004 Simtec Electronics |
| 137 | 137 | ||
diff --git a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt index 67671eba4231..f82b1faefad5 100644 --- a/Documentation/arm/Samsung-S3C24XX/USB-Host.txt +++ b/Documentation/arm/Samsung-S3C24XX/USB-Host.txt | |||
| @@ -90,4 +90,4 @@ Platform Data | |||
| 90 | Document Author | 90 | Document Author |
| 91 | --------------- | 91 | --------------- |
| 92 | 92 | ||
| 93 | Ben Dooks, (c) 2005 Simtec Electronics | 93 | Ben Dooks, Copyright 2005 Simtec Electronics |
diff --git a/MAINTAINERS b/MAINTAINERS index 6150c80bccf6..ad59f178586f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -659,6 +659,9 @@ ARM/FREESCALE IMX / MXC ARM ARCHITECTURE | |||
| 659 | M: Sascha Hauer <kernel@pengutronix.de> | 659 | M: Sascha Hauer <kernel@pengutronix.de> |
| 660 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 660 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
| 661 | S: Maintained | 661 | S: Maintained |
| 662 | T: git://git.pengutronix.de/git/imx/linux-2.6.git | ||
| 663 | F: arch/arm/mach-mx*/ | ||
| 664 | F: arch/arm/plat-mxc/ | ||
| 662 | 665 | ||
| 663 | ARM/GLOMATION GESBC9312SX MACHINE SUPPORT | 666 | ARM/GLOMATION GESBC9312SX MACHINE SUPPORT |
| 664 | M: Lennert Buytenhek <kernel@wantstofly.org> | 667 | M: Lennert Buytenhek <kernel@wantstofly.org> |
| @@ -729,6 +732,19 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |||
| 729 | S: Maintained | 732 | S: Maintained |
| 730 | F: arch/arm/mach-ixp4xx/ | 733 | F: arch/arm/mach-ixp4xx/ |
| 731 | 734 | ||
| 735 | ARM/INTEL RESEARCH IMOTE 2 MACHINE SUPPORT | ||
| 736 | M: Jonathan Cameron <jic23@cam.ac.uk> | ||
| 737 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | ||
| 738 | S: Maintained | ||
| 739 | F: arch/arm/mach-pxa/imote2.c | ||
| 740 | |||
| 741 | ARM/INTEL RESEARCH STARGATE 2 MACHINE SUPPORT | ||
| 742 | M: Jonathan Cameron <jic23@cam.ac.uk> | ||
| 743 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | ||
| 744 | S: Maintained | ||
| 745 | F: arch/arm/mach-pxa/stargate2.c | ||
| 746 | F: drivers/pcmcia/pxa2xx_stargate2.c | ||
| 747 | |||
| 732 | ARM/INTEL XSC3 (MANZANO) ARM CORE | 748 | ARM/INTEL XSC3 (MANZANO) ARM CORE |
| 733 | M: Lennert Buytenhek <kernel@wantstofly.org> | 749 | M: Lennert Buytenhek <kernel@wantstofly.org> |
| 734 | M: Dan Williams <dan.j.williams@intel.com> | 750 | M: Dan Williams <dan.j.williams@intel.com> |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1ae18d879e12..cf8a99f19dc4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -433,6 +433,17 @@ config ARCH_L7200 | |||
| 433 | If you have any questions or comments about the Linux kernel port | 433 | If you have any questions or comments about the Linux kernel port |
| 434 | to this board, send e-mail to <sjhill@cotw.com>. | 434 | to this board, send e-mail to <sjhill@cotw.com>. |
| 435 | 435 | ||
| 436 | config ARCH_DOVE | ||
| 437 | bool "Marvell Dove" | ||
| 438 | select PCI | ||
| 439 | select GENERIC_GPIO | ||
| 440 | select ARCH_REQUIRE_GPIOLIB | ||
| 441 | select GENERIC_TIME | ||
| 442 | select GENERIC_CLOCKEVENTS | ||
| 443 | select PLAT_ORION | ||
| 444 | help | ||
| 445 | Support for the Marvell Dove SoC 88AP510 | ||
| 446 | |||
| 436 | config ARCH_KIRKWOOD | 447 | config ARCH_KIRKWOOD |
| 437 | bool "Marvell Kirkwood" | 448 | bool "Marvell Kirkwood" |
| 438 | select CPU_FEROCEON | 449 | select CPU_FEROCEON |
| @@ -757,6 +768,9 @@ source "arch/arm/mach-orion5x/Kconfig" | |||
| 757 | 768 | ||
| 758 | source "arch/arm/mach-kirkwood/Kconfig" | 769 | source "arch/arm/mach-kirkwood/Kconfig" |
| 759 | 770 | ||
| 771 | source "arch/arm/mach-dove/Kconfig" | ||
| 772 | |||
| 773 | source "arch/arm/plat-samsung/Kconfig" | ||
| 760 | source "arch/arm/plat-s3c24xx/Kconfig" | 774 | source "arch/arm/plat-s3c24xx/Kconfig" |
| 761 | source "arch/arm/plat-s3c64xx/Kconfig" | 775 | source "arch/arm/plat-s3c64xx/Kconfig" |
| 762 | source "arch/arm/plat-s3c/Kconfig" | 776 | source "arch/arm/plat-s3c/Kconfig" |
| @@ -823,6 +837,8 @@ config ARCH_ACORN | |||
| 823 | 837 | ||
| 824 | config PLAT_IOP | 838 | config PLAT_IOP |
| 825 | bool | 839 | bool |
| 840 | select GENERIC_CLOCKEVENTS | ||
| 841 | select GENERIC_TIME | ||
| 826 | 842 | ||
| 827 | config PLAT_ORION | 843 | config PLAT_ORION |
| 828 | bool | 844 | bool |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 7603eba7c0cd..fa0cdab2e1d3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -122,6 +122,7 @@ machine-$(CONFIG_ARCH_AT91) := at91 | |||
| 122 | machine-$(CONFIG_ARCH_BCMRING) := bcmring | 122 | machine-$(CONFIG_ARCH_BCMRING) := bcmring |
| 123 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x | 123 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x |
| 124 | machine-$(CONFIG_ARCH_DAVINCI) := davinci | 124 | machine-$(CONFIG_ARCH_DAVINCI) := davinci |
| 125 | machine-$(CONFIG_ARCH_DOVE) := dove | ||
| 125 | machine-$(CONFIG_ARCH_EBSA110) := ebsa110 | 126 | machine-$(CONFIG_ARCH_EBSA110) := ebsa110 |
| 126 | machine-$(CONFIG_ARCH_EP93XX) := ep93xx | 127 | machine-$(CONFIG_ARCH_EP93XX) := ep93xx |
| 127 | machine-$(CONFIG_ARCH_GEMINI) := gemini | 128 | machine-$(CONFIG_ARCH_GEMINI) := gemini |
| @@ -180,9 +181,9 @@ plat-$(CONFIG_PLAT_IOP) := iop | |||
| 180 | plat-$(CONFIG_PLAT_NOMADIK) := nomadik | 181 | plat-$(CONFIG_PLAT_NOMADIK) := nomadik |
| 181 | plat-$(CONFIG_PLAT_ORION) := orion | 182 | plat-$(CONFIG_PLAT_ORION) := orion |
| 182 | plat-$(CONFIG_PLAT_PXA) := pxa | 183 | plat-$(CONFIG_PLAT_PXA) := pxa |
| 183 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c | 184 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c samsung |
| 184 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c | 185 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c samsung |
| 185 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c | 186 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx s3c samsung |
| 186 | plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx | 187 | plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx |
| 187 | 188 | ||
| 188 | ifeq ($(CONFIG_ARCH_EBSA110),y) | 189 | ifeq ($(CONFIG_ARCH_EBSA110),y) |
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fa6fbf45cf3b..d356af7cef82 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -743,6 +743,12 @@ proc_types: | |||
| 743 | W(b) __armv4_mmu_cache_off | 743 | W(b) __armv4_mmu_cache_off |
| 744 | W(b) __armv6_mmu_cache_flush | 744 | W(b) __armv6_mmu_cache_flush |
| 745 | 745 | ||
| 746 | .word 0x560f5810 @ Marvell PJ4 ARMv6 | ||
| 747 | .word 0xff0ffff0 | ||
| 748 | W(b) __armv4_mmu_cache_on | ||
| 749 | W(b) __armv4_mmu_cache_off | ||
| 750 | W(b) __armv6_mmu_cache_flush | ||
| 751 | |||
| 746 | .word 0x000f0000 @ new CPU Id | 752 | .word 0x000f0000 @ new CPU Id |
| 747 | .word 0x000f0000 | 753 | .word 0x000f0000 |
| 748 | W(b) __armv7_mmu_cache_on | 754 | W(b) __armv7_mmu_cache_on |
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig index d18d21bb41e4..a0170867130e 100644 --- a/arch/arm/configs/cm_x300_defconfig +++ b/arch/arm/configs/cm_x300_defconfig | |||
| @@ -1,15 +1,13 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.30-rc8 | 3 | # Linux kernel version: 2.6.32-rc4 |
| 4 | # Thu Jun 4 09:53:21 2009 | 4 | # Tue Oct 13 19:03:13 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | 13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
| @@ -18,14 +16,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | 16 | CONFIG_HARDIRQS_SW_RESEND=y |
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | 17 | CONFIG_GENERIC_IRQ_PROBE=y |
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 19 | CONFIG_ARCH_HAS_CPUFREQ=y |
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | 20 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ARCH_MTD_XIP=y | 22 | CONFIG_ARCH_MTD_XIP=y |
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 26 | CONFIG_CONSTRUCTORS=y | ||
| 29 | 27 | ||
| 30 | # | 28 | # |
| 31 | # General setup | 29 | # General setup |
| @@ -46,11 +44,12 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 46 | # | 44 | # |
| 47 | # RCU Subsystem | 45 | # RCU Subsystem |
| 48 | # | 46 | # |
| 49 | CONFIG_CLASSIC_RCU=y | 47 | CONFIG_TREE_RCU=y |
| 50 | # CONFIG_TREE_RCU is not set | 48 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 51 | # CONFIG_PREEMPT_RCU is not set | 49 | # CONFIG_RCU_TRACE is not set |
| 50 | CONFIG_RCU_FANOUT=32 | ||
| 51 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | 52 | # CONFIG_TREE_RCU_TRACE is not set |
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | CONFIG_IKCONFIG=y | 53 | CONFIG_IKCONFIG=y |
| 55 | CONFIG_IKCONFIG_PROC=y | 54 | CONFIG_IKCONFIG_PROC=y |
| 56 | CONFIG_LOG_BUF_SHIFT=18 | 55 | CONFIG_LOG_BUF_SHIFT=18 |
| @@ -83,7 +82,6 @@ CONFIG_SYSCTL_SYSCALL=y | |||
| 83 | CONFIG_KALLSYMS=y | 82 | CONFIG_KALLSYMS=y |
| 84 | # CONFIG_KALLSYMS_ALL is not set | 83 | # CONFIG_KALLSYMS_ALL is not set |
| 85 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 84 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 86 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 87 | CONFIG_HOTPLUG=y | 85 | CONFIG_HOTPLUG=y |
| 88 | CONFIG_PRINTK=y | 86 | CONFIG_PRINTK=y |
| 89 | CONFIG_BUG=y | 87 | CONFIG_BUG=y |
| @@ -96,6 +94,10 @@ CONFIG_TIMERFD=y | |||
| 96 | CONFIG_EVENTFD=y | 94 | CONFIG_EVENTFD=y |
| 97 | CONFIG_SHMEM=y | 95 | CONFIG_SHMEM=y |
| 98 | CONFIG_AIO=y | 96 | CONFIG_AIO=y |
| 97 | |||
| 98 | # | ||
| 99 | # Kernel Performance Events And Counters | ||
| 100 | # | ||
| 99 | CONFIG_VM_EVENT_COUNTERS=y | 101 | CONFIG_VM_EVENT_COUNTERS=y |
| 100 | CONFIG_SLUB_DEBUG=y | 102 | CONFIG_SLUB_DEBUG=y |
| 101 | CONFIG_COMPAT_BRK=y | 103 | CONFIG_COMPAT_BRK=y |
| @@ -103,13 +105,17 @@ CONFIG_COMPAT_BRK=y | |||
| 103 | CONFIG_SLUB=y | 105 | CONFIG_SLUB=y |
| 104 | # CONFIG_SLOB is not set | 106 | # CONFIG_SLOB is not set |
| 105 | # CONFIG_PROFILING is not set | 107 | # CONFIG_PROFILING is not set |
| 106 | # CONFIG_MARKERS is not set | ||
| 107 | CONFIG_HAVE_OPROFILE=y | 108 | CONFIG_HAVE_OPROFILE=y |
| 108 | # CONFIG_KPROBES is not set | 109 | # CONFIG_KPROBES is not set |
| 109 | CONFIG_HAVE_KPROBES=y | 110 | CONFIG_HAVE_KPROBES=y |
| 110 | CONFIG_HAVE_KRETPROBES=y | 111 | CONFIG_HAVE_KRETPROBES=y |
| 111 | CONFIG_HAVE_CLK=y | 112 | CONFIG_HAVE_CLK=y |
| 112 | # CONFIG_SLOW_WORK is not set | 113 | |
| 114 | # | ||
| 115 | # GCOV-based kernel profiling | ||
| 116 | # | ||
| 117 | # CONFIG_GCOV_KERNEL is not set | ||
| 118 | CONFIG_SLOW_WORK=y | ||
| 113 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 119 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 114 | CONFIG_SLABINFO=y | 120 | CONFIG_SLABINFO=y |
| 115 | CONFIG_RT_MUTEXES=y | 121 | CONFIG_RT_MUTEXES=y |
| @@ -117,11 +123,11 @@ CONFIG_BASE_SMALL=0 | |||
| 117 | CONFIG_MODULES=y | 123 | CONFIG_MODULES=y |
| 118 | # CONFIG_MODULE_FORCE_LOAD is not set | 124 | # CONFIG_MODULE_FORCE_LOAD is not set |
| 119 | CONFIG_MODULE_UNLOAD=y | 125 | CONFIG_MODULE_UNLOAD=y |
| 120 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 126 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 121 | # CONFIG_MODVERSIONS is not set | 127 | # CONFIG_MODVERSIONS is not set |
| 122 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 128 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 123 | CONFIG_BLOCK=y | 129 | CONFIG_BLOCK=y |
| 124 | # CONFIG_LBD is not set | 130 | CONFIG_LBDAF=y |
| 125 | # CONFIG_BLK_DEV_BSG is not set | 131 | # CONFIG_BLK_DEV_BSG is not set |
| 126 | # CONFIG_BLK_DEV_INTEGRITY is not set | 132 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 127 | 133 | ||
| @@ -142,19 +148,22 @@ CONFIG_FREEZER=y | |||
| 142 | # | 148 | # |
| 143 | # System Type | 149 | # System Type |
| 144 | # | 150 | # |
| 151 | CONFIG_MMU=y | ||
| 145 | # CONFIG_ARCH_AAEC2000 is not set | 152 | # CONFIG_ARCH_AAEC2000 is not set |
| 146 | # CONFIG_ARCH_INTEGRATOR is not set | 153 | # CONFIG_ARCH_INTEGRATOR is not set |
| 147 | # CONFIG_ARCH_REALVIEW is not set | 154 | # CONFIG_ARCH_REALVIEW is not set |
| 148 | # CONFIG_ARCH_VERSATILE is not set | 155 | # CONFIG_ARCH_VERSATILE is not set |
| 149 | # CONFIG_ARCH_AT91 is not set | 156 | # CONFIG_ARCH_AT91 is not set |
| 150 | # CONFIG_ARCH_CLPS711X is not set | 157 | # CONFIG_ARCH_CLPS711X is not set |
| 158 | # CONFIG_ARCH_GEMINI is not set | ||
| 151 | # CONFIG_ARCH_EBSA110 is not set | 159 | # CONFIG_ARCH_EBSA110 is not set |
| 152 | # CONFIG_ARCH_EP93XX is not set | 160 | # CONFIG_ARCH_EP93XX is not set |
| 153 | # CONFIG_ARCH_GEMINI is not set | ||
| 154 | # CONFIG_ARCH_FOOTBRIDGE is not set | 161 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 162 | # CONFIG_ARCH_MXC is not set | ||
| 163 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 155 | # CONFIG_ARCH_NETX is not set | 164 | # CONFIG_ARCH_NETX is not set |
| 156 | # CONFIG_ARCH_H720X is not set | 165 | # CONFIG_ARCH_H720X is not set |
| 157 | # CONFIG_ARCH_IMX is not set | 166 | # CONFIG_ARCH_NOMADIK is not set |
| 158 | # CONFIG_ARCH_IOP13XX is not set | 167 | # CONFIG_ARCH_IOP13XX is not set |
| 159 | # CONFIG_ARCH_IOP32X is not set | 168 | # CONFIG_ARCH_IOP32X is not set |
| 160 | # CONFIG_ARCH_IOP33X is not set | 169 | # CONFIG_ARCH_IOP33X is not set |
| @@ -163,25 +172,27 @@ CONFIG_FREEZER=y | |||
| 163 | # CONFIG_ARCH_IXP4XX is not set | 172 | # CONFIG_ARCH_IXP4XX is not set |
| 164 | # CONFIG_ARCH_L7200 is not set | 173 | # CONFIG_ARCH_L7200 is not set |
| 165 | # CONFIG_ARCH_KIRKWOOD is not set | 174 | # CONFIG_ARCH_KIRKWOOD is not set |
| 166 | # CONFIG_ARCH_KS8695 is not set | ||
| 167 | # CONFIG_ARCH_NS9XXX is not set | ||
| 168 | # CONFIG_ARCH_LOKI is not set | 175 | # CONFIG_ARCH_LOKI is not set |
| 169 | # CONFIG_ARCH_MV78XX0 is not set | 176 | # CONFIG_ARCH_MV78XX0 is not set |
| 170 | # CONFIG_ARCH_MXC is not set | ||
| 171 | # CONFIG_ARCH_ORION5X is not set | 177 | # CONFIG_ARCH_ORION5X is not set |
| 178 | # CONFIG_ARCH_MMP is not set | ||
| 179 | # CONFIG_ARCH_KS8695 is not set | ||
| 180 | # CONFIG_ARCH_NS9XXX is not set | ||
| 181 | # CONFIG_ARCH_W90X900 is not set | ||
| 172 | # CONFIG_ARCH_PNX4008 is not set | 182 | # CONFIG_ARCH_PNX4008 is not set |
| 173 | CONFIG_ARCH_PXA=y | 183 | CONFIG_ARCH_PXA=y |
| 174 | # CONFIG_ARCH_MMP is not set | 184 | # CONFIG_ARCH_MSM is not set |
| 175 | # CONFIG_ARCH_RPC is not set | 185 | # CONFIG_ARCH_RPC is not set |
| 176 | # CONFIG_ARCH_SA1100 is not set | 186 | # CONFIG_ARCH_SA1100 is not set |
| 177 | # CONFIG_ARCH_S3C2410 is not set | 187 | # CONFIG_ARCH_S3C2410 is not set |
| 178 | # CONFIG_ARCH_S3C64XX is not set | 188 | # CONFIG_ARCH_S3C64XX is not set |
| 189 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 179 | # CONFIG_ARCH_SHARK is not set | 190 | # CONFIG_ARCH_SHARK is not set |
| 180 | # CONFIG_ARCH_LH7A40X is not set | 191 | # CONFIG_ARCH_LH7A40X is not set |
| 192 | # CONFIG_ARCH_U300 is not set | ||
| 181 | # CONFIG_ARCH_DAVINCI is not set | 193 | # CONFIG_ARCH_DAVINCI is not set |
| 182 | # CONFIG_ARCH_OMAP is not set | 194 | # CONFIG_ARCH_OMAP is not set |
| 183 | # CONFIG_ARCH_MSM is not set | 195 | # CONFIG_ARCH_BCMRING is not set |
| 184 | # CONFIG_ARCH_W90X900 is not set | ||
| 185 | 196 | ||
| 186 | # | 197 | # |
| 187 | # Intel PXA2xx/PXA3xx Implementations | 198 | # Intel PXA2xx/PXA3xx Implementations |
| @@ -191,16 +202,19 @@ CONFIG_ARCH_PXA=y | |||
| 191 | # Supported PXA3xx Processor Variants | 202 | # Supported PXA3xx Processor Variants |
| 192 | # | 203 | # |
| 193 | CONFIG_CPU_PXA300=y | 204 | CONFIG_CPU_PXA300=y |
| 194 | # CONFIG_CPU_PXA310 is not set | 205 | CONFIG_CPU_PXA310=y |
| 195 | # CONFIG_CPU_PXA320 is not set | 206 | # CONFIG_CPU_PXA320 is not set |
| 196 | # CONFIG_CPU_PXA930 is not set | 207 | # CONFIG_CPU_PXA930 is not set |
| 197 | # CONFIG_CPU_PXA935 is not set | 208 | # CONFIG_CPU_PXA935 is not set |
| 209 | # CONFIG_CPU_PXA950 is not set | ||
| 198 | # CONFIG_ARCH_GUMSTIX is not set | 210 | # CONFIG_ARCH_GUMSTIX is not set |
| 199 | # CONFIG_MACH_INTELMOTE2 is not set | 211 | # CONFIG_MACH_INTELMOTE2 is not set |
| 212 | # CONFIG_MACH_STARGATE2 is not set | ||
| 200 | # CONFIG_ARCH_LUBBOCK is not set | 213 | # CONFIG_ARCH_LUBBOCK is not set |
| 201 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 214 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 202 | # CONFIG_MACH_MAINSTONE is not set | 215 | # CONFIG_MACH_MAINSTONE is not set |
| 203 | # CONFIG_MACH_MP900C is not set | 216 | # CONFIG_MACH_MP900C is not set |
| 217 | # CONFIG_MACH_BALLOON3 is not set | ||
| 204 | # CONFIG_ARCH_PXA_IDP is not set | 218 | # CONFIG_ARCH_PXA_IDP is not set |
| 205 | # CONFIG_PXA_SHARPSL is not set | 219 | # CONFIG_PXA_SHARPSL is not set |
| 206 | # CONFIG_ARCH_VIPER is not set | 220 | # CONFIG_ARCH_VIPER is not set |
| @@ -218,6 +232,7 @@ CONFIG_CPU_PXA300=y | |||
| 218 | # CONFIG_MACH_SAAR is not set | 232 | # CONFIG_MACH_SAAR is not set |
| 219 | # CONFIG_MACH_ARMCORE is not set | 233 | # CONFIG_MACH_ARMCORE is not set |
| 220 | CONFIG_MACH_CM_X300=y | 234 | CONFIG_MACH_CM_X300=y |
| 235 | # CONFIG_MACH_H4700 is not set | ||
| 221 | # CONFIG_MACH_MAGICIAN is not set | 236 | # CONFIG_MACH_MAGICIAN is not set |
| 222 | # CONFIG_MACH_HIMALAYA is not set | 237 | # CONFIG_MACH_HIMALAYA is not set |
| 223 | # CONFIG_MACH_MIOA701 is not set | 238 | # CONFIG_MACH_MIOA701 is not set |
| @@ -225,8 +240,8 @@ CONFIG_MACH_CM_X300=y | |||
| 225 | # CONFIG_ARCH_PXA_PALM is not set | 240 | # CONFIG_ARCH_PXA_PALM is not set |
| 226 | # CONFIG_MACH_CSB726 is not set | 241 | # CONFIG_MACH_CSB726 is not set |
| 227 | # CONFIG_PXA_EZX is not set | 242 | # CONFIG_PXA_EZX is not set |
| 243 | # CONFIG_MACH_XCEP is not set | ||
| 228 | CONFIG_PXA3xx=y | 244 | CONFIG_PXA3xx=y |
| 229 | # CONFIG_PXA_PWM is not set | ||
| 230 | CONFIG_PLAT_PXA=y | 245 | CONFIG_PLAT_PXA=y |
| 231 | 246 | ||
| 232 | # | 247 | # |
| @@ -236,7 +251,7 @@ CONFIG_CPU_32=y | |||
| 236 | CONFIG_CPU_XSC3=y | 251 | CONFIG_CPU_XSC3=y |
| 237 | CONFIG_CPU_32v5=y | 252 | CONFIG_CPU_32v5=y |
| 238 | CONFIG_CPU_ABRT_EV5T=y | 253 | CONFIG_CPU_ABRT_EV5T=y |
| 239 | CONFIG_CPU_PABRT_NOIFAR=y | 254 | CONFIG_CPU_PABRT_LEGACY=y |
| 240 | CONFIG_CPU_CACHE_VIVT=y | 255 | CONFIG_CPU_CACHE_VIVT=y |
| 241 | CONFIG_CPU_TLB_V4WBI=y | 256 | CONFIG_CPU_TLB_V4WBI=y |
| 242 | CONFIG_CPU_CP15=y | 257 | CONFIG_CPU_CP15=y |
| @@ -246,11 +261,12 @@ CONFIG_IO_36=y | |||
| 246 | # | 261 | # |
| 247 | # Processor Features | 262 | # Processor Features |
| 248 | # | 263 | # |
| 249 | # CONFIG_ARM_THUMB is not set | 264 | CONFIG_ARM_THUMB=y |
| 250 | # CONFIG_CPU_DCACHE_DISABLE is not set | 265 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 251 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 266 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 252 | CONFIG_OUTER_CACHE=y | 267 | CONFIG_OUTER_CACHE=y |
| 253 | CONFIG_CACHE_XSC3L2=y | 268 | CONFIG_CACHE_XSC3L2=y |
| 269 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
| 254 | CONFIG_IWMMXT=y | 270 | CONFIG_IWMMXT=y |
| 255 | CONFIG_COMMON_CLKDEV=y | 271 | CONFIG_COMMON_CLKDEV=y |
| 256 | 272 | ||
| @@ -272,11 +288,12 @@ CONFIG_VMSPLIT_3G=y | |||
| 272 | # CONFIG_VMSPLIT_2G is not set | 288 | # CONFIG_VMSPLIT_2G is not set |
| 273 | # CONFIG_VMSPLIT_1G is not set | 289 | # CONFIG_VMSPLIT_1G is not set |
| 274 | CONFIG_PAGE_OFFSET=0xC0000000 | 290 | CONFIG_PAGE_OFFSET=0xC0000000 |
| 291 | CONFIG_PREEMPT_NONE=y | ||
| 292 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 275 | # CONFIG_PREEMPT is not set | 293 | # CONFIG_PREEMPT is not set |
| 276 | CONFIG_HZ=100 | 294 | CONFIG_HZ=100 |
| 277 | CONFIG_AEABI=y | 295 | CONFIG_AEABI=y |
| 278 | CONFIG_OABI_COMPAT=y | 296 | CONFIG_OABI_COMPAT=y |
| 279 | # CONFIG_ARCH_HAS_HOLES_MEMORYMODEL is not set | ||
| 280 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 297 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 281 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 298 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
| 282 | CONFIG_HIGHMEM=y | 299 | CONFIG_HIGHMEM=y |
| @@ -292,17 +309,19 @@ CONFIG_SPLIT_PTLOCK_CPUS=4096 | |||
| 292 | CONFIG_ZONE_DMA_FLAG=0 | 309 | CONFIG_ZONE_DMA_FLAG=0 |
| 293 | CONFIG_BOUNCE=y | 310 | CONFIG_BOUNCE=y |
| 294 | CONFIG_VIRT_TO_BUS=y | 311 | CONFIG_VIRT_TO_BUS=y |
| 295 | CONFIG_UNEVICTABLE_LRU=y | ||
| 296 | CONFIG_HAVE_MLOCK=y | 312 | CONFIG_HAVE_MLOCK=y |
| 297 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | 313 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y |
| 314 | # CONFIG_KSM is not set | ||
| 315 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 298 | CONFIG_ALIGNMENT_TRAP=y | 316 | CONFIG_ALIGNMENT_TRAP=y |
| 317 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 299 | 318 | ||
| 300 | # | 319 | # |
| 301 | # Boot options | 320 | # Boot options |
| 302 | # | 321 | # |
| 303 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 322 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 304 | CONFIG_ZBOOT_ROM_BSS=0x0 | 323 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 305 | CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=jffs2 console=ttyS2,38400" | 324 | CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400" |
| 306 | # CONFIG_XIP_KERNEL is not set | 325 | # CONFIG_XIP_KERNEL is not set |
| 307 | # CONFIG_KEXEC is not set | 326 | # CONFIG_KEXEC is not set |
| 308 | 327 | ||
| @@ -355,6 +374,7 @@ CONFIG_PM_SLEEP=y | |||
| 355 | CONFIG_SUSPEND=y | 374 | CONFIG_SUSPEND=y |
| 356 | CONFIG_SUSPEND_FREEZER=y | 375 | CONFIG_SUSPEND_FREEZER=y |
| 357 | CONFIG_APM_EMULATION=y | 376 | CONFIG_APM_EMULATION=y |
| 377 | # CONFIG_PM_RUNTIME is not set | ||
| 358 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 378 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 359 | CONFIG_NET=y | 379 | CONFIG_NET=y |
| 360 | 380 | ||
| @@ -396,6 +416,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 396 | # CONFIG_NETFILTER is not set | 416 | # CONFIG_NETFILTER is not set |
| 397 | # CONFIG_IP_DCCP is not set | 417 | # CONFIG_IP_DCCP is not set |
| 398 | # CONFIG_IP_SCTP is not set | 418 | # CONFIG_IP_SCTP is not set |
| 419 | # CONFIG_RDS is not set | ||
| 399 | # CONFIG_TIPC is not set | 420 | # CONFIG_TIPC is not set |
| 400 | # CONFIG_ATM is not set | 421 | # CONFIG_ATM is not set |
| 401 | # CONFIG_BRIDGE is not set | 422 | # CONFIG_BRIDGE is not set |
| @@ -410,6 +431,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 410 | # CONFIG_ECONET is not set | 431 | # CONFIG_ECONET is not set |
| 411 | # CONFIG_WAN_ROUTER is not set | 432 | # CONFIG_WAN_ROUTER is not set |
| 412 | # CONFIG_PHONET is not set | 433 | # CONFIG_PHONET is not set |
| 434 | # CONFIG_IEEE802154 is not set | ||
| 413 | # CONFIG_NET_SCHED is not set | 435 | # CONFIG_NET_SCHED is not set |
| 414 | # CONFIG_DCB is not set | 436 | # CONFIG_DCB is not set |
| 415 | 437 | ||
| @@ -433,22 +455,27 @@ CONFIG_BT_HIDP=m | |||
| 433 | # | 455 | # |
| 434 | # Bluetooth device drivers | 456 | # Bluetooth device drivers |
| 435 | # | 457 | # |
| 436 | # CONFIG_BT_HCIBTUSB is not set | 458 | CONFIG_BT_HCIBTUSB=m |
| 437 | # CONFIG_BT_HCIBTSDIO is not set | 459 | # CONFIG_BT_HCIBTSDIO is not set |
| 438 | # CONFIG_BT_HCIUART is not set | 460 | # CONFIG_BT_HCIUART is not set |
| 439 | # CONFIG_BT_HCIBCM203X is not set | 461 | # CONFIG_BT_HCIBCM203X is not set |
| 440 | # CONFIG_BT_HCIBPA10X is not set | 462 | # CONFIG_BT_HCIBPA10X is not set |
| 441 | # CONFIG_BT_HCIBFUSB is not set | 463 | # CONFIG_BT_HCIBFUSB is not set |
| 442 | # CONFIG_BT_HCIVHCI is not set | 464 | # CONFIG_BT_HCIVHCI is not set |
| 465 | # CONFIG_BT_MRVL is not set | ||
| 443 | # CONFIG_AF_RXRPC is not set | 466 | # CONFIG_AF_RXRPC is not set |
| 444 | CONFIG_WIRELESS=y | 467 | CONFIG_WIRELESS=y |
| 445 | # CONFIG_CFG80211 is not set | 468 | # CONFIG_CFG80211 is not set |
| 469 | CONFIG_CFG80211_DEFAULT_PS_VALUE=0 | ||
| 446 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | 470 | # CONFIG_WIRELESS_OLD_REGULATORY is not set |
| 447 | CONFIG_WIRELESS_EXT=y | 471 | CONFIG_WIRELESS_EXT=y |
| 448 | CONFIG_WIRELESS_EXT_SYSFS=y | 472 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 449 | CONFIG_LIB80211=m | 473 | CONFIG_LIB80211=m |
| 450 | # CONFIG_LIB80211_DEBUG is not set | 474 | # CONFIG_LIB80211_DEBUG is not set |
| 451 | # CONFIG_MAC80211 is not set | 475 | |
| 476 | # | ||
| 477 | # CFG80211 needs to be enabled for MAC80211 | ||
| 478 | # | ||
| 452 | # CONFIG_WIMAX is not set | 479 | # CONFIG_WIMAX is not set |
| 453 | # CONFIG_RFKILL is not set | 480 | # CONFIG_RFKILL is not set |
| 454 | # CONFIG_NET_9P is not set | 481 | # CONFIG_NET_9P is not set |
| @@ -461,6 +488,7 @@ CONFIG_LIB80211=m | |||
| 461 | # Generic Driver Options | 488 | # Generic Driver Options |
| 462 | # | 489 | # |
| 463 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 490 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 491 | # CONFIG_DEVTMPFS is not set | ||
| 464 | CONFIG_STANDALONE=y | 492 | CONFIG_STANDALONE=y |
| 465 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 493 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 466 | CONFIG_FW_LOADER=y | 494 | CONFIG_FW_LOADER=y |
| @@ -472,9 +500,9 @@ CONFIG_EXTRA_FIRMWARE="" | |||
| 472 | # CONFIG_CONNECTOR is not set | 500 | # CONFIG_CONNECTOR is not set |
| 473 | CONFIG_MTD=y | 501 | CONFIG_MTD=y |
| 474 | # CONFIG_MTD_DEBUG is not set | 502 | # CONFIG_MTD_DEBUG is not set |
| 503 | # CONFIG_MTD_TESTS is not set | ||
| 475 | # CONFIG_MTD_CONCAT is not set | 504 | # CONFIG_MTD_CONCAT is not set |
| 476 | CONFIG_MTD_PARTITIONS=y | 505 | CONFIG_MTD_PARTITIONS=y |
| 477 | # CONFIG_MTD_TESTS is not set | ||
| 478 | # CONFIG_MTD_REDBOOT_PARTS is not set | 506 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 479 | # CONFIG_MTD_CMDLINE_PARTS is not set | 507 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 480 | # CONFIG_MTD_AFS_PARTS is not set | 508 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -521,6 +549,9 @@ CONFIG_MTD_CFI_I2=y | |||
| 521 | # | 549 | # |
| 522 | # Self-contained MTD device drivers | 550 | # Self-contained MTD device drivers |
| 523 | # | 551 | # |
| 552 | # CONFIG_MTD_DATAFLASH is not set | ||
| 553 | # CONFIG_MTD_M25P80 is not set | ||
| 554 | # CONFIG_MTD_SST25L is not set | ||
| 524 | # CONFIG_MTD_SLRAM is not set | 555 | # CONFIG_MTD_SLRAM is not set |
| 525 | # CONFIG_MTD_PHRAM is not set | 556 | # CONFIG_MTD_PHRAM is not set |
| 526 | # CONFIG_MTD_MTDRAM is not set | 557 | # CONFIG_MTD_MTDRAM is not set |
| @@ -556,7 +587,15 @@ CONFIG_MTD_NAND_PXA3xx=y | |||
| 556 | # | 587 | # |
| 557 | # UBI - Unsorted block images | 588 | # UBI - Unsorted block images |
| 558 | # | 589 | # |
| 559 | # CONFIG_MTD_UBI is not set | 590 | CONFIG_MTD_UBI=y |
| 591 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 592 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 593 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 594 | |||
| 595 | # | ||
| 596 | # UBI debugging options | ||
| 597 | # | ||
| 598 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 560 | # CONFIG_PARPORT is not set | 599 | # CONFIG_PARPORT is not set |
| 561 | CONFIG_BLK_DEV=y | 600 | CONFIG_BLK_DEV=y |
| 562 | # CONFIG_BLK_DEV_COW_COMMON is not set | 601 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| @@ -570,6 +609,7 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 | |||
| 570 | # CONFIG_BLK_DEV_XIP is not set | 609 | # CONFIG_BLK_DEV_XIP is not set |
| 571 | # CONFIG_CDROM_PKTCDVD is not set | 610 | # CONFIG_CDROM_PKTCDVD is not set |
| 572 | # CONFIG_ATA_OVER_ETH is not set | 611 | # CONFIG_ATA_OVER_ETH is not set |
| 612 | # CONFIG_MG_DISK is not set | ||
| 573 | # CONFIG_MISC_DEVICES is not set | 613 | # CONFIG_MISC_DEVICES is not set |
| 574 | CONFIG_HAVE_IDE=y | 614 | CONFIG_HAVE_IDE=y |
| 575 | # CONFIG_IDE is not set | 615 | # CONFIG_IDE is not set |
| @@ -593,10 +633,6 @@ CONFIG_BLK_DEV_SD=y | |||
| 593 | # CONFIG_BLK_DEV_SR is not set | 633 | # CONFIG_BLK_DEV_SR is not set |
| 594 | # CONFIG_CHR_DEV_SG is not set | 634 | # CONFIG_CHR_DEV_SG is not set |
| 595 | # CONFIG_CHR_DEV_SCH is not set | 635 | # CONFIG_CHR_DEV_SCH is not set |
| 596 | |||
| 597 | # | ||
| 598 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 599 | # | ||
| 600 | # CONFIG_SCSI_MULTI_LUN is not set | 636 | # CONFIG_SCSI_MULTI_LUN is not set |
| 601 | # CONFIG_SCSI_CONSTANTS is not set | 637 | # CONFIG_SCSI_CONSTANTS is not set |
| 602 | # CONFIG_SCSI_LOGGING is not set | 638 | # CONFIG_SCSI_LOGGING is not set |
| @@ -621,7 +657,6 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 621 | # CONFIG_ATA is not set | 657 | # CONFIG_ATA is not set |
| 622 | # CONFIG_MD is not set | 658 | # CONFIG_MD is not set |
| 623 | CONFIG_NETDEVICES=y | 659 | CONFIG_NETDEVICES=y |
| 624 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 625 | # CONFIG_DUMMY is not set | 660 | # CONFIG_DUMMY is not set |
| 626 | # CONFIG_BONDING is not set | 661 | # CONFIG_BONDING is not set |
| 627 | # CONFIG_MACVLAN is not set | 662 | # CONFIG_MACVLAN is not set |
| @@ -636,6 +671,7 @@ CONFIG_MII=y | |||
| 636 | CONFIG_DM9000=y | 671 | CONFIG_DM9000=y |
| 637 | CONFIG_DM9000_DEBUGLEVEL=0 | 672 | CONFIG_DM9000_DEBUGLEVEL=0 |
| 638 | CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y | 673 | CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y |
| 674 | # CONFIG_ENC28J60 is not set | ||
| 639 | # CONFIG_ETHOC is not set | 675 | # CONFIG_ETHOC is not set |
| 640 | # CONFIG_SMC911X is not set | 676 | # CONFIG_SMC911X is not set |
| 641 | # CONFIG_SMSC911X is not set | 677 | # CONFIG_SMSC911X is not set |
| @@ -648,20 +684,20 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y | |||
| 648 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | 684 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set |
| 649 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | 685 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set |
| 650 | # CONFIG_B44 is not set | 686 | # CONFIG_B44 is not set |
| 687 | # CONFIG_KS8842 is not set | ||
| 688 | # CONFIG_KS8851 is not set | ||
| 689 | # CONFIG_KS8851_MLL is not set | ||
| 651 | # CONFIG_NETDEV_1000 is not set | 690 | # CONFIG_NETDEV_1000 is not set |
| 652 | # CONFIG_NETDEV_10000 is not set | 691 | # CONFIG_NETDEV_10000 is not set |
| 653 | 692 | CONFIG_WLAN=y | |
| 654 | # | ||
| 655 | # Wireless LAN | ||
| 656 | # | ||
| 657 | # CONFIG_WLAN_PRE80211 is not set | 693 | # CONFIG_WLAN_PRE80211 is not set |
| 658 | CONFIG_WLAN_80211=y | 694 | CONFIG_WLAN_80211=y |
| 659 | CONFIG_LIBERTAS=m | 695 | CONFIG_LIBERTAS=m |
| 660 | # CONFIG_LIBERTAS_USB is not set | 696 | # CONFIG_LIBERTAS_USB is not set |
| 661 | CONFIG_LIBERTAS_SDIO=m | 697 | CONFIG_LIBERTAS_SDIO=m |
| 698 | # CONFIG_LIBERTAS_SPI is not set | ||
| 662 | # CONFIG_LIBERTAS_DEBUG is not set | 699 | # CONFIG_LIBERTAS_DEBUG is not set |
| 663 | # CONFIG_USB_ZD1201 is not set | 700 | # CONFIG_USB_ZD1201 is not set |
| 664 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 665 | # CONFIG_HOSTAP is not set | 701 | # CONFIG_HOSTAP is not set |
| 666 | 702 | ||
| 667 | # | 703 | # |
| @@ -683,6 +719,7 @@ CONFIG_LIBERTAS_SDIO=m | |||
| 683 | # CONFIG_NETPOLL is not set | 719 | # CONFIG_NETPOLL is not set |
| 684 | # CONFIG_NET_POLL_CONTROLLER is not set | 720 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 685 | # CONFIG_ISDN is not set | 721 | # CONFIG_ISDN is not set |
| 722 | # CONFIG_PHONE is not set | ||
| 686 | 723 | ||
| 687 | # | 724 | # |
| 688 | # Input device support | 725 | # Input device support |
| @@ -706,33 +743,51 @@ CONFIG_INPUT_EVDEV=y | |||
| 706 | # Input Device Drivers | 743 | # Input Device Drivers |
| 707 | # | 744 | # |
| 708 | CONFIG_INPUT_KEYBOARD=y | 745 | CONFIG_INPUT_KEYBOARD=y |
| 746 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 709 | # CONFIG_KEYBOARD_ATKBD is not set | 747 | # CONFIG_KEYBOARD_ATKBD is not set |
| 710 | # CONFIG_KEYBOARD_SUNKBD is not set | 748 | # CONFIG_QT2160 is not set |
| 711 | # CONFIG_KEYBOARD_LKKBD is not set | 749 | # CONFIG_KEYBOARD_LKKBD is not set |
| 712 | # CONFIG_KEYBOARD_XTKBD is not set | 750 | # CONFIG_KEYBOARD_GPIO is not set |
| 751 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 752 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 753 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 713 | # CONFIG_KEYBOARD_NEWTON is not set | 754 | # CONFIG_KEYBOARD_NEWTON is not set |
| 714 | # CONFIG_KEYBOARD_STOWAWAY is not set | 755 | # CONFIG_KEYBOARD_OPENCORES is not set |
| 715 | CONFIG_KEYBOARD_PXA27x=m | 756 | CONFIG_KEYBOARD_PXA27x=m |
| 716 | # CONFIG_KEYBOARD_GPIO is not set | 757 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 758 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 759 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 717 | # CONFIG_INPUT_MOUSE is not set | 760 | # CONFIG_INPUT_MOUSE is not set |
| 718 | # CONFIG_INPUT_JOYSTICK is not set | 761 | # CONFIG_INPUT_JOYSTICK is not set |
| 719 | # CONFIG_INPUT_TABLET is not set | 762 | # CONFIG_INPUT_TABLET is not set |
| 720 | CONFIG_INPUT_TOUCHSCREEN=y | 763 | CONFIG_INPUT_TOUCHSCREEN=y |
| 764 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 765 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 721 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 766 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 767 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 722 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 768 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 769 | # CONFIG_TOUCHSCREEN_DA9034 is not set | ||
| 770 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 723 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 771 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 724 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 772 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 725 | # CONFIG_TOUCHSCREEN_ELO is not set | 773 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 726 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | 774 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set |
| 775 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 727 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 776 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 728 | # CONFIG_TOUCHSCREEN_INEXIO is not set | 777 | # CONFIG_TOUCHSCREEN_INEXIO is not set |
| 729 | # CONFIG_TOUCHSCREEN_MK712 is not set | 778 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 730 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 779 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 731 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 780 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 732 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 781 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 782 | CONFIG_TOUCHSCREEN_WM97XX=m | ||
| 783 | # CONFIG_TOUCHSCREEN_WM9705 is not set | ||
| 784 | CONFIG_TOUCHSCREEN_WM9712=y | ||
| 785 | # CONFIG_TOUCHSCREEN_WM9713 is not set | ||
| 786 | # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set | ||
| 733 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 787 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 734 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 788 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 735 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | 789 | # CONFIG_TOUCHSCREEN_TSC2007 is not set |
| 790 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 736 | # CONFIG_INPUT_MISC is not set | 791 | # CONFIG_INPUT_MISC is not set |
| 737 | 792 | ||
| 738 | # | 793 | # |
| @@ -760,6 +815,7 @@ CONFIG_DEVKMEM=y | |||
| 760 | # | 815 | # |
| 761 | # Non-8250 serial port support | 816 | # Non-8250 serial port support |
| 762 | # | 817 | # |
| 818 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 763 | CONFIG_SERIAL_PXA=y | 819 | CONFIG_SERIAL_PXA=y |
| 764 | CONFIG_SERIAL_PXA_CONSOLE=y | 820 | CONFIG_SERIAL_PXA_CONSOLE=y |
| 765 | CONFIG_SERIAL_CORE=y | 821 | CONFIG_SERIAL_CORE=y |
| @@ -774,6 +830,7 @@ CONFIG_UNIX98_PTYS=y | |||
| 774 | # CONFIG_TCG_TPM is not set | 830 | # CONFIG_TCG_TPM is not set |
| 775 | CONFIG_I2C=y | 831 | CONFIG_I2C=y |
| 776 | CONFIG_I2C_BOARDINFO=y | 832 | CONFIG_I2C_BOARDINFO=y |
| 833 | CONFIG_I2C_COMPAT=y | ||
| 777 | # CONFIG_I2C_CHARDEV is not set | 834 | # CONFIG_I2C_CHARDEV is not set |
| 778 | CONFIG_I2C_HELPER_AUTO=y | 835 | CONFIG_I2C_HELPER_AUTO=y |
| 779 | 836 | ||
| @@ -784,6 +841,7 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 784 | # | 841 | # |
| 785 | # I2C system bus drivers (mostly embedded / system-on-chip) | 842 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 786 | # | 843 | # |
| 844 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 787 | # CONFIG_I2C_GPIO is not set | 845 | # CONFIG_I2C_GPIO is not set |
| 788 | # CONFIG_I2C_OCORES is not set | 846 | # CONFIG_I2C_OCORES is not set |
| 789 | CONFIG_I2C_PXA=y | 847 | CONFIG_I2C_PXA=y |
| @@ -807,19 +865,36 @@ CONFIG_I2C_PXA=y | |||
| 807 | # Miscellaneous I2C Chip support | 865 | # Miscellaneous I2C Chip support |
| 808 | # | 866 | # |
| 809 | # CONFIG_DS1682 is not set | 867 | # CONFIG_DS1682 is not set |
| 810 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 811 | # CONFIG_PCF8575 is not set | ||
| 812 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 813 | # CONFIG_SENSORS_TSL2550 is not set | 868 | # CONFIG_SENSORS_TSL2550 is not set |
| 814 | # CONFIG_I2C_DEBUG_CORE is not set | 869 | # CONFIG_I2C_DEBUG_CORE is not set |
| 815 | # CONFIG_I2C_DEBUG_ALGO is not set | 870 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 816 | # CONFIG_I2C_DEBUG_BUS is not set | 871 | # CONFIG_I2C_DEBUG_BUS is not set |
| 817 | # CONFIG_I2C_DEBUG_CHIP is not set | 872 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 818 | # CONFIG_SPI is not set | 873 | CONFIG_SPI=y |
| 874 | # CONFIG_SPI_DEBUG is not set | ||
| 875 | CONFIG_SPI_MASTER=y | ||
| 876 | |||
| 877 | # | ||
| 878 | # SPI Master Controller Drivers | ||
| 879 | # | ||
| 880 | CONFIG_SPI_BITBANG=y | ||
| 881 | CONFIG_SPI_GPIO=y | ||
| 882 | # CONFIG_SPI_PXA2XX is not set | ||
| 883 | |||
| 884 | # | ||
| 885 | # SPI Protocol Masters | ||
| 886 | # | ||
| 887 | # CONFIG_SPI_SPIDEV is not set | ||
| 888 | # CONFIG_SPI_TLE62X0 is not set | ||
| 889 | |||
| 890 | # | ||
| 891 | # PPS support | ||
| 892 | # | ||
| 893 | # CONFIG_PPS is not set | ||
| 819 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 894 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 820 | CONFIG_GPIOLIB=y | 895 | CONFIG_GPIOLIB=y |
| 821 | # CONFIG_DEBUG_GPIO is not set | 896 | # CONFIG_DEBUG_GPIO is not set |
| 822 | # CONFIG_GPIO_SYSFS is not set | 897 | CONFIG_GPIO_SYSFS=y |
| 823 | 898 | ||
| 824 | # | 899 | # |
| 825 | # Memory mapped GPIO expanders: | 900 | # Memory mapped GPIO expanders: |
| @@ -839,11 +914,17 @@ CONFIG_GPIO_PCA953X=y | |||
| 839 | # | 914 | # |
| 840 | # SPI GPIO expanders: | 915 | # SPI GPIO expanders: |
| 841 | # | 916 | # |
| 917 | # CONFIG_GPIO_MAX7301 is not set | ||
| 918 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 919 | # CONFIG_GPIO_MC33880 is not set | ||
| 920 | |||
| 921 | # | ||
| 922 | # AC97 GPIO expanders: | ||
| 923 | # | ||
| 842 | # CONFIG_W1 is not set | 924 | # CONFIG_W1 is not set |
| 843 | # CONFIG_POWER_SUPPLY is not set | 925 | # CONFIG_POWER_SUPPLY is not set |
| 844 | # CONFIG_HWMON is not set | 926 | # CONFIG_HWMON is not set |
| 845 | # CONFIG_THERMAL is not set | 927 | # CONFIG_THERMAL is not set |
| 846 | # CONFIG_THERMAL_HWMON is not set | ||
| 847 | # CONFIG_WATCHDOG is not set | 928 | # CONFIG_WATCHDOG is not set |
| 848 | CONFIG_SSB_POSSIBLE=y | 929 | CONFIG_SSB_POSSIBLE=y |
| 849 | 930 | ||
| @@ -860,32 +941,33 @@ CONFIG_SSB_POSSIBLE=y | |||
| 860 | # CONFIG_MFD_ASIC3 is not set | 941 | # CONFIG_MFD_ASIC3 is not set |
| 861 | # CONFIG_HTC_EGPIO is not set | 942 | # CONFIG_HTC_EGPIO is not set |
| 862 | # CONFIG_HTC_PASIC3 is not set | 943 | # CONFIG_HTC_PASIC3 is not set |
| 944 | # CONFIG_UCB1400_CORE is not set | ||
| 863 | # CONFIG_TPS65010 is not set | 945 | # CONFIG_TPS65010 is not set |
| 864 | # CONFIG_TWL4030_CORE is not set | 946 | # CONFIG_TWL4030_CORE is not set |
| 865 | # CONFIG_MFD_TMIO is not set | 947 | # CONFIG_MFD_TMIO is not set |
| 866 | # CONFIG_MFD_T7L66XB is not set | 948 | # CONFIG_MFD_T7L66XB is not set |
| 867 | # CONFIG_MFD_TC6387XB is not set | 949 | # CONFIG_MFD_TC6387XB is not set |
| 868 | # CONFIG_MFD_TC6393XB is not set | 950 | # CONFIG_MFD_TC6393XB is not set |
| 869 | # CONFIG_PMIC_DA903X is not set | 951 | CONFIG_PMIC_DA903X=y |
| 870 | # CONFIG_MFD_WM8400 is not set | 952 | # CONFIG_MFD_WM8400 is not set |
| 953 | # CONFIG_MFD_WM831X is not set | ||
| 871 | # CONFIG_MFD_WM8350_I2C is not set | 954 | # CONFIG_MFD_WM8350_I2C is not set |
| 872 | # CONFIG_MFD_PCF50633 is not set | 955 | # CONFIG_MFD_PCF50633 is not set |
| 873 | 956 | # CONFIG_MFD_MC13783 is not set | |
| 874 | # | 957 | # CONFIG_AB3100_CORE is not set |
| 875 | # Multimedia devices | 958 | # CONFIG_EZX_PCAP is not set |
| 876 | # | 959 | CONFIG_REGULATOR=y |
| 877 | 960 | # CONFIG_REGULATOR_DEBUG is not set | |
| 878 | # | 961 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set |
| 879 | # Multimedia core support | 962 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set |
| 880 | # | 963 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set |
| 881 | # CONFIG_VIDEO_DEV is not set | 964 | # CONFIG_REGULATOR_BQ24022 is not set |
| 882 | # CONFIG_DVB_CORE is not set | 965 | # CONFIG_REGULATOR_MAX1586 is not set |
| 883 | # CONFIG_VIDEO_MEDIA is not set | 966 | CONFIG_REGULATOR_DA903X=y |
| 884 | 967 | # CONFIG_REGULATOR_LP3971 is not set | |
| 885 | # | 968 | # CONFIG_REGULATOR_TPS65023 is not set |
| 886 | # Multimedia drivers | 969 | # CONFIG_REGULATOR_TPS6507X is not set |
| 887 | # | 970 | # CONFIG_MEDIA_SUPPORT is not set |
| 888 | # CONFIG_DAB is not set | ||
| 889 | 971 | ||
| 890 | # | 972 | # |
| 891 | # Graphics support | 973 | # Graphics support |
| @@ -925,7 +1007,17 @@ CONFIG_FB_PXA=y | |||
| 925 | # CONFIG_FB_METRONOME is not set | 1007 | # CONFIG_FB_METRONOME is not set |
| 926 | # CONFIG_FB_MB862XX is not set | 1008 | # CONFIG_FB_MB862XX is not set |
| 927 | # CONFIG_FB_BROADSHEET is not set | 1009 | # CONFIG_FB_BROADSHEET is not set |
| 928 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 1010 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 1011 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 1012 | # CONFIG_LCD_LMS283GF05 is not set | ||
| 1013 | # CONFIG_LCD_LTV350QV is not set | ||
| 1014 | # CONFIG_LCD_ILI9320 is not set | ||
| 1015 | CONFIG_LCD_TDO24M=y | ||
| 1016 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 1017 | # CONFIG_LCD_PLATFORM is not set | ||
| 1018 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | ||
| 1019 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 1020 | CONFIG_BACKLIGHT_DA903X=m | ||
| 929 | 1021 | ||
| 930 | # | 1022 | # |
| 931 | # Display device support | 1023 | # Display device support |
| @@ -956,38 +1048,48 @@ CONFIG_LOGO_LINUX_MONO=y | |||
| 956 | CONFIG_LOGO_LINUX_VGA16=y | 1048 | CONFIG_LOGO_LINUX_VGA16=y |
| 957 | CONFIG_LOGO_LINUX_CLUT224=y | 1049 | CONFIG_LOGO_LINUX_CLUT224=y |
| 958 | CONFIG_SOUND=m | 1050 | CONFIG_SOUND=m |
| 959 | # CONFIG_SOUND_OSS_CORE is not set | 1051 | CONFIG_SOUND_OSS_CORE=y |
| 1052 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | ||
| 960 | CONFIG_SND=m | 1053 | CONFIG_SND=m |
| 961 | CONFIG_SND_TIMER=m | 1054 | CONFIG_SND_TIMER=m |
| 962 | CONFIG_SND_PCM=m | 1055 | CONFIG_SND_PCM=m |
| 963 | CONFIG_SND_JACK=y | 1056 | CONFIG_SND_JACK=y |
| 964 | # CONFIG_SND_SEQUENCER is not set | 1057 | # CONFIG_SND_SEQUENCER is not set |
| 965 | # CONFIG_SND_MIXER_OSS is not set | 1058 | CONFIG_SND_OSSEMUL=y |
| 966 | # CONFIG_SND_PCM_OSS is not set | 1059 | CONFIG_SND_MIXER_OSS=m |
| 1060 | CONFIG_SND_PCM_OSS=m | ||
| 1061 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 967 | # CONFIG_SND_DYNAMIC_MINORS is not set | 1062 | # CONFIG_SND_DYNAMIC_MINORS is not set |
| 968 | CONFIG_SND_SUPPORT_OLD_API=y | 1063 | CONFIG_SND_SUPPORT_OLD_API=y |
| 969 | CONFIG_SND_VERBOSE_PROCFS=y | 1064 | CONFIG_SND_VERBOSE_PROCFS=y |
| 970 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1065 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 971 | # CONFIG_SND_DEBUG is not set | 1066 | # CONFIG_SND_DEBUG is not set |
| 972 | CONFIG_SND_DRIVERS=y | 1067 | CONFIG_SND_VMASTER=y |
| 973 | # CONFIG_SND_DUMMY is not set | 1068 | # CONFIG_SND_RAWMIDI_SEQ is not set |
| 974 | # CONFIG_SND_MTPAV is not set | 1069 | # CONFIG_SND_OPL3_LIB_SEQ is not set |
| 975 | # CONFIG_SND_SERIAL_U16550 is not set | 1070 | # CONFIG_SND_OPL4_LIB_SEQ is not set |
| 976 | # CONFIG_SND_MPU401 is not set | 1071 | # CONFIG_SND_SBAWE_SEQ is not set |
| 1072 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 1073 | CONFIG_SND_AC97_CODEC=m | ||
| 1074 | # CONFIG_SND_DRIVERS is not set | ||
| 977 | CONFIG_SND_ARM=y | 1075 | CONFIG_SND_ARM=y |
| 978 | CONFIG_SND_PXA2XX_LIB=m | 1076 | CONFIG_SND_PXA2XX_LIB=m |
| 1077 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
| 979 | # CONFIG_SND_PXA2XX_AC97 is not set | 1078 | # CONFIG_SND_PXA2XX_AC97 is not set |
| 980 | CONFIG_SND_USB=y | 1079 | # CONFIG_SND_SPI is not set |
| 981 | # CONFIG_SND_USB_AUDIO is not set | 1080 | # CONFIG_SND_USB is not set |
| 982 | # CONFIG_SND_USB_CAIAQ is not set | ||
| 983 | CONFIG_SND_SOC=m | 1081 | CONFIG_SND_SOC=m |
| 1082 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 984 | CONFIG_SND_PXA2XX_SOC=m | 1083 | CONFIG_SND_PXA2XX_SOC=m |
| 1084 | CONFIG_SND_PXA2XX_SOC_AC97=m | ||
| 1085 | CONFIG_SND_PXA2XX_SOC_EM_X270=m | ||
| 985 | CONFIG_SND_SOC_I2C_AND_SPI=m | 1086 | CONFIG_SND_SOC_I2C_AND_SPI=m |
| 986 | # CONFIG_SND_SOC_ALL_CODECS is not set | 1087 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 1088 | CONFIG_SND_SOC_WM9712=m | ||
| 987 | # CONFIG_SOUND_PRIME is not set | 1089 | # CONFIG_SOUND_PRIME is not set |
| 1090 | CONFIG_AC97_BUS=m | ||
| 988 | CONFIG_HID_SUPPORT=y | 1091 | CONFIG_HID_SUPPORT=y |
| 989 | CONFIG_HID=y | 1092 | CONFIG_HID=y |
| 990 | CONFIG_HID_DEBUG=y | ||
| 991 | # CONFIG_HIDRAW is not set | 1093 | # CONFIG_HIDRAW is not set |
| 992 | 1094 | ||
| 993 | # | 1095 | # |
| @@ -1006,10 +1108,12 @@ CONFIG_HID_BELKIN=y | |||
| 1006 | CONFIG_HID_CHERRY=y | 1108 | CONFIG_HID_CHERRY=y |
| 1007 | CONFIG_HID_CHICONY=y | 1109 | CONFIG_HID_CHICONY=y |
| 1008 | CONFIG_HID_CYPRESS=y | 1110 | CONFIG_HID_CYPRESS=y |
| 1111 | CONFIG_HID_DRAGONRISE=y | ||
| 1009 | # CONFIG_DRAGONRISE_FF is not set | 1112 | # CONFIG_DRAGONRISE_FF is not set |
| 1010 | CONFIG_HID_EZKEY=y | 1113 | CONFIG_HID_EZKEY=y |
| 1011 | CONFIG_HID_KYE=y | 1114 | CONFIG_HID_KYE=y |
| 1012 | CONFIG_HID_GYRATION=y | 1115 | CONFIG_HID_GYRATION=y |
| 1116 | CONFIG_HID_TWINHAN=y | ||
| 1013 | CONFIG_HID_KENSINGTON=y | 1117 | CONFIG_HID_KENSINGTON=y |
| 1014 | CONFIG_HID_LOGITECH=y | 1118 | CONFIG_HID_LOGITECH=y |
| 1015 | # CONFIG_LOGITECH_FF is not set | 1119 | # CONFIG_LOGITECH_FF is not set |
| @@ -1023,9 +1127,15 @@ CONFIG_HID_PETALYNX=y | |||
| 1023 | CONFIG_HID_SAMSUNG=y | 1127 | CONFIG_HID_SAMSUNG=y |
| 1024 | CONFIG_HID_SONY=y | 1128 | CONFIG_HID_SONY=y |
| 1025 | CONFIG_HID_SUNPLUS=y | 1129 | CONFIG_HID_SUNPLUS=y |
| 1130 | CONFIG_HID_GREENASIA=y | ||
| 1026 | # CONFIG_GREENASIA_FF is not set | 1131 | # CONFIG_GREENASIA_FF is not set |
| 1132 | CONFIG_HID_SMARTJOYPLUS=y | ||
| 1133 | # CONFIG_SMARTJOYPLUS_FF is not set | ||
| 1027 | CONFIG_HID_TOPSEED=y | 1134 | CONFIG_HID_TOPSEED=y |
| 1135 | CONFIG_HID_THRUSTMASTER=y | ||
| 1028 | # CONFIG_THRUSTMASTER_FF is not set | 1136 | # CONFIG_THRUSTMASTER_FF is not set |
| 1137 | CONFIG_HID_WACOM=m | ||
| 1138 | CONFIG_HID_ZEROPLUS=y | ||
| 1029 | # CONFIG_ZEROPLUS_FF is not set | 1139 | # CONFIG_ZEROPLUS_FF is not set |
| 1030 | CONFIG_USB_SUPPORT=y | 1140 | CONFIG_USB_SUPPORT=y |
| 1031 | CONFIG_USB_ARCH_HAS_HCD=y | 1141 | CONFIG_USB_ARCH_HAS_HCD=y |
| @@ -1054,6 +1164,7 @@ CONFIG_USB_MON=y | |||
| 1054 | # CONFIG_USB_OXU210HP_HCD is not set | 1164 | # CONFIG_USB_OXU210HP_HCD is not set |
| 1055 | # CONFIG_USB_ISP116X_HCD is not set | 1165 | # CONFIG_USB_ISP116X_HCD is not set |
| 1056 | # CONFIG_USB_ISP1760_HCD is not set | 1166 | # CONFIG_USB_ISP1760_HCD is not set |
| 1167 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1057 | CONFIG_USB_OHCI_HCD=y | 1168 | CONFIG_USB_OHCI_HCD=y |
| 1058 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1169 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 1059 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1170 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| @@ -1151,8 +1262,9 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 1151 | # | 1262 | # |
| 1152 | CONFIG_MMC_PXA=m | 1263 | CONFIG_MMC_PXA=m |
| 1153 | # CONFIG_MMC_SDHCI is not set | 1264 | # CONFIG_MMC_SDHCI is not set |
| 1265 | # CONFIG_MMC_AT91 is not set | ||
| 1266 | # CONFIG_MMC_ATMELMCI is not set | ||
| 1154 | # CONFIG_MEMSTICK is not set | 1267 | # CONFIG_MEMSTICK is not set |
| 1155 | # CONFIG_ACCESSIBILITY is not set | ||
| 1156 | CONFIG_NEW_LEDS=y | 1268 | CONFIG_NEW_LEDS=y |
| 1157 | CONFIG_LEDS_CLASS=y | 1269 | CONFIG_LEDS_CLASS=y |
| 1158 | 1270 | ||
| @@ -1162,8 +1274,10 @@ CONFIG_LEDS_CLASS=y | |||
| 1162 | # CONFIG_LEDS_PCA9532 is not set | 1274 | # CONFIG_LEDS_PCA9532 is not set |
| 1163 | CONFIG_LEDS_GPIO=y | 1275 | CONFIG_LEDS_GPIO=y |
| 1164 | CONFIG_LEDS_GPIO_PLATFORM=y | 1276 | CONFIG_LEDS_GPIO_PLATFORM=y |
| 1165 | # CONFIG_LEDS_LP5521 is not set | 1277 | # CONFIG_LEDS_LP3944 is not set |
| 1166 | # CONFIG_LEDS_PCA955X is not set | 1278 | # CONFIG_LEDS_PCA955X is not set |
| 1279 | # CONFIG_LEDS_DA903X is not set | ||
| 1280 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1167 | # CONFIG_LEDS_BD2802 is not set | 1281 | # CONFIG_LEDS_BD2802 is not set |
| 1168 | 1282 | ||
| 1169 | # | 1283 | # |
| @@ -1179,6 +1293,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y | |||
| 1179 | # | 1293 | # |
| 1180 | # iptables trigger is under Netfilter config (LED target) | 1294 | # iptables trigger is under Netfilter config (LED target) |
| 1181 | # | 1295 | # |
| 1296 | # CONFIG_ACCESSIBILITY is not set | ||
| 1182 | CONFIG_RTC_LIB=y | 1297 | CONFIG_RTC_LIB=y |
| 1183 | CONFIG_RTC_CLASS=y | 1298 | CONFIG_RTC_CLASS=y |
| 1184 | CONFIG_RTC_HCTOSYS=y | 1299 | CONFIG_RTC_HCTOSYS=y |
| @@ -1210,10 +1325,19 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1210 | # CONFIG_RTC_DRV_S35390A is not set | 1325 | # CONFIG_RTC_DRV_S35390A is not set |
| 1211 | # CONFIG_RTC_DRV_FM3130 is not set | 1326 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1212 | # CONFIG_RTC_DRV_RX8581 is not set | 1327 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1328 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1213 | 1329 | ||
| 1214 | # | 1330 | # |
| 1215 | # SPI RTC drivers | 1331 | # SPI RTC drivers |
| 1216 | # | 1332 | # |
| 1333 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1334 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1335 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1336 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1337 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1338 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1339 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1340 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1217 | 1341 | ||
| 1218 | # | 1342 | # |
| 1219 | # Platform RTC drivers | 1343 | # Platform RTC drivers |
| @@ -1233,12 +1357,15 @@ CONFIG_RTC_DRV_V3020=y | |||
| 1233 | # | 1357 | # |
| 1234 | # on-CPU RTC drivers | 1358 | # on-CPU RTC drivers |
| 1235 | # | 1359 | # |
| 1236 | CONFIG_RTC_DRV_SA1100=y | 1360 | # CONFIG_RTC_DRV_SA1100 is not set |
| 1237 | # CONFIG_RTC_DRV_PXA is not set | 1361 | CONFIG_RTC_DRV_PXA=y |
| 1238 | # CONFIG_DMADEVICES is not set | 1362 | # CONFIG_DMADEVICES is not set |
| 1239 | # CONFIG_AUXDISPLAY is not set | 1363 | # CONFIG_AUXDISPLAY is not set |
| 1240 | # CONFIG_REGULATOR is not set | ||
| 1241 | # CONFIG_UIO is not set | 1364 | # CONFIG_UIO is not set |
| 1365 | |||
| 1366 | # | ||
| 1367 | # TI VLYNQ | ||
| 1368 | # | ||
| 1242 | # CONFIG_STAGING is not set | 1369 | # CONFIG_STAGING is not set |
| 1243 | 1370 | ||
| 1244 | # | 1371 | # |
| @@ -1256,10 +1383,13 @@ CONFIG_JBD=y | |||
| 1256 | # CONFIG_REISERFS_FS is not set | 1383 | # CONFIG_REISERFS_FS is not set |
| 1257 | # CONFIG_JFS_FS is not set | 1384 | # CONFIG_JFS_FS is not set |
| 1258 | CONFIG_FS_POSIX_ACL=y | 1385 | CONFIG_FS_POSIX_ACL=y |
| 1259 | CONFIG_FILE_LOCKING=y | ||
| 1260 | # CONFIG_XFS_FS is not set | 1386 | # CONFIG_XFS_FS is not set |
| 1387 | # CONFIG_GFS2_FS is not set | ||
| 1261 | # CONFIG_OCFS2_FS is not set | 1388 | # CONFIG_OCFS2_FS is not set |
| 1262 | # CONFIG_BTRFS_FS is not set | 1389 | # CONFIG_BTRFS_FS is not set |
| 1390 | # CONFIG_NILFS2_FS is not set | ||
| 1391 | CONFIG_FILE_LOCKING=y | ||
| 1392 | CONFIG_FSNOTIFY=y | ||
| 1263 | CONFIG_DNOTIFY=y | 1393 | CONFIG_DNOTIFY=y |
| 1264 | CONFIG_INOTIFY=y | 1394 | CONFIG_INOTIFY=y |
| 1265 | CONFIG_INOTIFY_USER=y | 1395 | CONFIG_INOTIFY_USER=y |
| @@ -1319,6 +1449,12 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1319 | # CONFIG_JFFS2_LZO is not set | 1449 | # CONFIG_JFFS2_LZO is not set |
| 1320 | CONFIG_JFFS2_RTIME=y | 1450 | CONFIG_JFFS2_RTIME=y |
| 1321 | # CONFIG_JFFS2_RUBIN is not set | 1451 | # CONFIG_JFFS2_RUBIN is not set |
| 1452 | CONFIG_UBIFS_FS=y | ||
| 1453 | # CONFIG_UBIFS_FS_XATTR is not set | ||
| 1454 | # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | ||
| 1455 | CONFIG_UBIFS_FS_LZO=y | ||
| 1456 | CONFIG_UBIFS_FS_ZLIB=y | ||
| 1457 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
| 1322 | # CONFIG_CRAMFS is not set | 1458 | # CONFIG_CRAMFS is not set |
| 1323 | # CONFIG_SQUASHFS is not set | 1459 | # CONFIG_SQUASHFS is not set |
| 1324 | # CONFIG_VXFS_FS is not set | 1460 | # CONFIG_VXFS_FS is not set |
| @@ -1329,12 +1465,12 @@ CONFIG_JFFS2_RTIME=y | |||
| 1329 | # CONFIG_ROMFS_FS is not set | 1465 | # CONFIG_ROMFS_FS is not set |
| 1330 | # CONFIG_SYSV_FS is not set | 1466 | # CONFIG_SYSV_FS is not set |
| 1331 | # CONFIG_UFS_FS is not set | 1467 | # CONFIG_UFS_FS is not set |
| 1332 | # CONFIG_NILFS2_FS is not set | ||
| 1333 | CONFIG_NETWORK_FILESYSTEMS=y | 1468 | CONFIG_NETWORK_FILESYSTEMS=y |
| 1334 | CONFIG_NFS_FS=y | 1469 | CONFIG_NFS_FS=y |
| 1335 | CONFIG_NFS_V3=y | 1470 | CONFIG_NFS_V3=y |
| 1336 | CONFIG_NFS_V3_ACL=y | 1471 | CONFIG_NFS_V3_ACL=y |
| 1337 | CONFIG_NFS_V4=y | 1472 | CONFIG_NFS_V4=y |
| 1473 | # CONFIG_NFS_V4_1 is not set | ||
| 1338 | CONFIG_ROOT_NFS=y | 1474 | CONFIG_ROOT_NFS=y |
| 1339 | # CONFIG_NFSD is not set | 1475 | # CONFIG_NFSD is not set |
| 1340 | CONFIG_LOCKD=y | 1476 | CONFIG_LOCKD=y |
| @@ -1378,7 +1514,7 @@ CONFIG_MSDOS_PARTITION=y | |||
| 1378 | # CONFIG_KARMA_PARTITION is not set | 1514 | # CONFIG_KARMA_PARTITION is not set |
| 1379 | # CONFIG_EFI_PARTITION is not set | 1515 | # CONFIG_EFI_PARTITION is not set |
| 1380 | # CONFIG_SYSV68_PARTITION is not set | 1516 | # CONFIG_SYSV68_PARTITION is not set |
| 1381 | CONFIG_NLS=m | 1517 | CONFIG_NLS=y |
| 1382 | CONFIG_NLS_DEFAULT="iso8859-1" | 1518 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1383 | CONFIG_NLS_CODEPAGE_437=m | 1519 | CONFIG_NLS_CODEPAGE_437=m |
| 1384 | # CONFIG_NLS_CODEPAGE_737 is not set | 1520 | # CONFIG_NLS_CODEPAGE_737 is not set |
| @@ -1428,6 +1564,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y | |||
| 1428 | CONFIG_ENABLE_MUST_CHECK=y | 1564 | CONFIG_ENABLE_MUST_CHECK=y |
| 1429 | CONFIG_FRAME_WARN=1024 | 1565 | CONFIG_FRAME_WARN=1024 |
| 1430 | # CONFIG_MAGIC_SYSRQ is not set | 1566 | # CONFIG_MAGIC_SYSRQ is not set |
| 1567 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1431 | # CONFIG_UNUSED_SYMBOLS is not set | 1568 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1432 | CONFIG_DEBUG_FS=y | 1569 | CONFIG_DEBUG_FS=y |
| 1433 | # CONFIG_HEADERS_CHECK is not set | 1570 | # CONFIG_HEADERS_CHECK is not set |
| @@ -1441,6 +1578,7 @@ CONFIG_DEBUG_KERNEL=y | |||
| 1441 | # CONFIG_DEBUG_OBJECTS is not set | 1578 | # CONFIG_DEBUG_OBJECTS is not set |
| 1442 | # CONFIG_SLUB_DEBUG_ON is not set | 1579 | # CONFIG_SLUB_DEBUG_ON is not set |
| 1443 | # CONFIG_SLUB_STATS is not set | 1580 | # CONFIG_SLUB_STATS is not set |
| 1581 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1444 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1582 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1445 | # CONFIG_RT_MUTEX_TESTER is not set | 1583 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1446 | # CONFIG_DEBUG_SPINLOCK is not set | 1584 | # CONFIG_DEBUG_SPINLOCK is not set |
| @@ -1460,32 +1598,20 @@ CONFIG_DEBUG_MEMORY_INIT=y | |||
| 1460 | # CONFIG_DEBUG_LIST is not set | 1598 | # CONFIG_DEBUG_LIST is not set |
| 1461 | # CONFIG_DEBUG_SG is not set | 1599 | # CONFIG_DEBUG_SG is not set |
| 1462 | # CONFIG_DEBUG_NOTIFIERS is not set | 1600 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 1601 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1463 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1602 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1464 | # CONFIG_RCU_TORTURE_TEST is not set | 1603 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1465 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 1604 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 1466 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1605 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1467 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1606 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1607 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1468 | # CONFIG_FAULT_INJECTION is not set | 1608 | # CONFIG_FAULT_INJECTION is not set |
| 1469 | # CONFIG_LATENCYTOP is not set | 1609 | # CONFIG_LATENCYTOP is not set |
| 1470 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1610 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1471 | # CONFIG_PAGE_POISONING is not set | 1611 | # CONFIG_PAGE_POISONING is not set |
| 1472 | CONFIG_HAVE_FUNCTION_TRACER=y | 1612 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1473 | CONFIG_TRACING_SUPPORT=y | 1613 | CONFIG_TRACING_SUPPORT=y |
| 1474 | 1614 | # CONFIG_FTRACE is not set | |
| 1475 | # | ||
| 1476 | # Tracers | ||
| 1477 | # | ||
| 1478 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1479 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1480 | # CONFIG_SCHED_TRACER is not set | ||
| 1481 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1482 | # CONFIG_EVENT_TRACER is not set | ||
| 1483 | # CONFIG_BOOT_TRACER is not set | ||
| 1484 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1485 | # CONFIG_STACK_TRACER is not set | ||
| 1486 | # CONFIG_KMEMTRACE is not set | ||
| 1487 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1488 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1489 | # CONFIG_DYNAMIC_DEBUG is not set | 1615 | # CONFIG_DYNAMIC_DEBUG is not set |
| 1490 | # CONFIG_SAMPLES is not set | 1616 | # CONFIG_SAMPLES is not set |
| 1491 | CONFIG_HAVE_ARCH_KGDB=y | 1617 | CONFIG_HAVE_ARCH_KGDB=y |
| @@ -1509,7 +1635,6 @@ CONFIG_CRYPTO=y | |||
| 1509 | # | 1635 | # |
| 1510 | # Crypto core or helper | 1636 | # Crypto core or helper |
| 1511 | # | 1637 | # |
| 1512 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1513 | CONFIG_CRYPTO_ALGAPI=y | 1638 | CONFIG_CRYPTO_ALGAPI=y |
| 1514 | CONFIG_CRYPTO_ALGAPI2=y | 1639 | CONFIG_CRYPTO_ALGAPI2=y |
| 1515 | CONFIG_CRYPTO_AEAD2=y | 1640 | CONFIG_CRYPTO_AEAD2=y |
| @@ -1551,11 +1676,13 @@ CONFIG_CRYPTO_ECB=m | |||
| 1551 | # | 1676 | # |
| 1552 | # CONFIG_CRYPTO_HMAC is not set | 1677 | # CONFIG_CRYPTO_HMAC is not set |
| 1553 | # CONFIG_CRYPTO_XCBC is not set | 1678 | # CONFIG_CRYPTO_XCBC is not set |
| 1679 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1554 | 1680 | ||
| 1555 | # | 1681 | # |
| 1556 | # Digest | 1682 | # Digest |
| 1557 | # | 1683 | # |
| 1558 | # CONFIG_CRYPTO_CRC32C is not set | 1684 | # CONFIG_CRYPTO_CRC32C is not set |
| 1685 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1559 | # CONFIG_CRYPTO_MD4 is not set | 1686 | # CONFIG_CRYPTO_MD4 is not set |
| 1560 | CONFIG_CRYPTO_MD5=y | 1687 | CONFIG_CRYPTO_MD5=y |
| 1561 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1688 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| @@ -1591,9 +1718,9 @@ CONFIG_CRYPTO_DES=y | |||
| 1591 | # | 1718 | # |
| 1592 | # Compression | 1719 | # Compression |
| 1593 | # | 1720 | # |
| 1594 | # CONFIG_CRYPTO_DEFLATE is not set | 1721 | CONFIG_CRYPTO_DEFLATE=y |
| 1595 | # CONFIG_CRYPTO_ZLIB is not set | 1722 | # CONFIG_CRYPTO_ZLIB is not set |
| 1596 | # CONFIG_CRYPTO_LZO is not set | 1723 | CONFIG_CRYPTO_LZO=y |
| 1597 | 1724 | ||
| 1598 | # | 1725 | # |
| 1599 | # Random Number Generation | 1726 | # Random Number Generation |
| @@ -1608,7 +1735,7 @@ CONFIG_CRYPTO_DES=y | |||
| 1608 | CONFIG_BITREVERSE=y | 1735 | CONFIG_BITREVERSE=y |
| 1609 | CONFIG_GENERIC_FIND_LAST_BIT=y | 1736 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 1610 | # CONFIG_CRC_CCITT is not set | 1737 | # CONFIG_CRC_CCITT is not set |
| 1611 | # CONFIG_CRC16 is not set | 1738 | CONFIG_CRC16=y |
| 1612 | CONFIG_CRC_T10DIF=y | 1739 | CONFIG_CRC_T10DIF=y |
| 1613 | # CONFIG_CRC_ITU_T is not set | 1740 | # CONFIG_CRC_ITU_T is not set |
| 1614 | CONFIG_CRC32=y | 1741 | CONFIG_CRC32=y |
| @@ -1616,6 +1743,8 @@ CONFIG_CRC32=y | |||
| 1616 | # CONFIG_LIBCRC32C is not set | 1743 | # CONFIG_LIBCRC32C is not set |
| 1617 | CONFIG_ZLIB_INFLATE=y | 1744 | CONFIG_ZLIB_INFLATE=y |
| 1618 | CONFIG_ZLIB_DEFLATE=y | 1745 | CONFIG_ZLIB_DEFLATE=y |
| 1746 | CONFIG_LZO_COMPRESS=y | ||
| 1747 | CONFIG_LZO_DECOMPRESS=y | ||
| 1619 | CONFIG_DECOMPRESS_GZIP=y | 1748 | CONFIG_DECOMPRESS_GZIP=y |
| 1620 | CONFIG_DECOMPRESS_BZIP2=y | 1749 | CONFIG_DECOMPRESS_BZIP2=y |
| 1621 | CONFIG_DECOMPRESS_LZMA=y | 1750 | CONFIG_DECOMPRESS_LZMA=y |
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig new file mode 100644 index 000000000000..b3a491675d59 --- /dev/null +++ b/arch/arm/configs/dove_defconfig | |||
| @@ -0,0 +1,1620 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.32-rc6 | ||
| 4 | # Tue Nov 24 13:53:37 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_GENERIC_HARDIRQS=y | ||
| 12 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 14 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 19 | CONFIG_GENERIC_HWEIGHT=y | ||
| 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 21 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 22 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 24 | CONFIG_CONSTRUCTORS=y | ||
| 25 | |||
| 26 | # | ||
| 27 | # General setup | ||
| 28 | # | ||
| 29 | CONFIG_EXPERIMENTAL=y | ||
| 30 | CONFIG_BROKEN_ON_SMP=y | ||
| 31 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 32 | CONFIG_LOCALVERSION="" | ||
| 33 | CONFIG_LOCALVERSION_AUTO=y | ||
| 34 | CONFIG_SWAP=y | ||
| 35 | CONFIG_SYSVIPC=y | ||
| 36 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 37 | # CONFIG_POSIX_MQUEUE is not set | ||
| 38 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 39 | # CONFIG_TASKSTATS is not set | ||
| 40 | # CONFIG_AUDIT is not set | ||
| 41 | |||
| 42 | # | ||
| 43 | # RCU Subsystem | ||
| 44 | # | ||
| 45 | CONFIG_TREE_RCU=y | ||
| 46 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 47 | # CONFIG_RCU_TRACE is not set | ||
| 48 | CONFIG_RCU_FANOUT=32 | ||
| 49 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 50 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 51 | # CONFIG_IKCONFIG is not set | ||
| 52 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 53 | # CONFIG_GROUP_SCHED is not set | ||
| 54 | # CONFIG_CGROUPS is not set | ||
| 55 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 56 | # CONFIG_RELAY is not set | ||
| 57 | # CONFIG_NAMESPACES is not set | ||
| 58 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 60 | CONFIG_SYSCTL=y | ||
| 61 | CONFIG_ANON_INODES=y | ||
| 62 | CONFIG_EMBEDDED=y | ||
| 63 | CONFIG_UID16=y | ||
| 64 | CONFIG_SYSCTL_SYSCALL=y | ||
| 65 | CONFIG_KALLSYMS=y | ||
| 66 | # CONFIG_KALLSYMS_ALL is not set | ||
| 67 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 68 | CONFIG_HOTPLUG=y | ||
| 69 | CONFIG_PRINTK=y | ||
| 70 | CONFIG_BUG=y | ||
| 71 | CONFIG_ELF_CORE=y | ||
| 72 | CONFIG_BASE_FULL=y | ||
| 73 | CONFIG_FUTEX=y | ||
| 74 | CONFIG_EPOLL=y | ||
| 75 | CONFIG_SIGNALFD=y | ||
| 76 | CONFIG_TIMERFD=y | ||
| 77 | CONFIG_EVENTFD=y | ||
| 78 | CONFIG_SHMEM=y | ||
| 79 | CONFIG_AIO=y | ||
| 80 | |||
| 81 | # | ||
| 82 | # Kernel Performance Events And Counters | ||
| 83 | # | ||
| 84 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 85 | CONFIG_PCI_QUIRKS=y | ||
| 86 | CONFIG_COMPAT_BRK=y | ||
| 87 | CONFIG_SLAB=y | ||
| 88 | # CONFIG_SLUB is not set | ||
| 89 | # CONFIG_SLOB is not set | ||
| 90 | # CONFIG_PROFILING is not set | ||
| 91 | CONFIG_HAVE_OPROFILE=y | ||
| 92 | # CONFIG_KPROBES is not set | ||
| 93 | CONFIG_HAVE_KPROBES=y | ||
| 94 | CONFIG_HAVE_KRETPROBES=y | ||
| 95 | |||
| 96 | # | ||
| 97 | # GCOV-based kernel profiling | ||
| 98 | # | ||
| 99 | # CONFIG_GCOV_KERNEL is not set | ||
| 100 | # CONFIG_SLOW_WORK is not set | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 109 | # CONFIG_MODVERSIONS is not set | ||
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | CONFIG_LBDAF=y | ||
| 113 | # CONFIG_BLK_DEV_BSG is not set | ||
| 114 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 115 | |||
| 116 | # | ||
| 117 | # IO Schedulers | ||
| 118 | # | ||
| 119 | CONFIG_IOSCHED_NOOP=y | ||
| 120 | CONFIG_IOSCHED_AS=y | ||
| 121 | CONFIG_IOSCHED_DEADLINE=y | ||
| 122 | CONFIG_IOSCHED_CFQ=y | ||
| 123 | # CONFIG_DEFAULT_AS is not set | ||
| 124 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 125 | CONFIG_DEFAULT_CFQ=y | ||
| 126 | # CONFIG_DEFAULT_NOOP is not set | ||
| 127 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 128 | # CONFIG_FREEZER is not set | ||
| 129 | |||
| 130 | # | ||
| 131 | # System Type | ||
| 132 | # | ||
| 133 | CONFIG_MMU=y | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_GEMINI is not set | ||
| 141 | # CONFIG_ARCH_EBSA110 is not set | ||
| 142 | # CONFIG_ARCH_EP93XX is not set | ||
| 143 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 144 | # CONFIG_ARCH_MXC is not set | ||
| 145 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 146 | # CONFIG_ARCH_NETX is not set | ||
| 147 | # CONFIG_ARCH_H720X is not set | ||
| 148 | # CONFIG_ARCH_NOMADIK is not set | ||
| 149 | # CONFIG_ARCH_IOP13XX is not set | ||
| 150 | # CONFIG_ARCH_IOP32X is not set | ||
| 151 | # CONFIG_ARCH_IOP33X is not set | ||
| 152 | # CONFIG_ARCH_IXP23XX is not set | ||
| 153 | # CONFIG_ARCH_IXP2000 is not set | ||
| 154 | # CONFIG_ARCH_IXP4XX is not set | ||
| 155 | # CONFIG_ARCH_L7200 is not set | ||
| 156 | CONFIG_ARCH_DOVE=y | ||
| 157 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 158 | # CONFIG_ARCH_LOKI is not set | ||
| 159 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 160 | # CONFIG_ARCH_ORION5X is not set | ||
| 161 | # CONFIG_ARCH_MMP is not set | ||
| 162 | # CONFIG_ARCH_KS8695 is not set | ||
| 163 | # CONFIG_ARCH_NS9XXX is not set | ||
| 164 | # CONFIG_ARCH_W90X900 is not set | ||
| 165 | # CONFIG_ARCH_PNX4008 is not set | ||
| 166 | # CONFIG_ARCH_PXA is not set | ||
| 167 | # CONFIG_ARCH_MSM is not set | ||
| 168 | # CONFIG_ARCH_RPC is not set | ||
| 169 | # CONFIG_ARCH_SA1100 is not set | ||
| 170 | # CONFIG_ARCH_S3C2410 is not set | ||
| 171 | # CONFIG_ARCH_S3C64XX is not set | ||
| 172 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 173 | # CONFIG_ARCH_SHARK is not set | ||
| 174 | # CONFIG_ARCH_LH7A40X is not set | ||
| 175 | # CONFIG_ARCH_U300 is not set | ||
| 176 | # CONFIG_ARCH_DAVINCI is not set | ||
| 177 | # CONFIG_ARCH_OMAP is not set | ||
| 178 | # CONFIG_ARCH_BCMRING is not set | ||
| 179 | |||
| 180 | # | ||
| 181 | # Marvell Dove Implementations | ||
| 182 | # | ||
| 183 | CONFIG_MACH_DOVE_DB=y | ||
| 184 | CONFIG_PLAT_ORION=y | ||
| 185 | |||
| 186 | # | ||
| 187 | # Processor Type | ||
| 188 | # | ||
| 189 | CONFIG_CPU_32=y | ||
| 190 | CONFIG_CPU_V6=y | ||
| 191 | CONFIG_CPU_32v6K=y | ||
| 192 | CONFIG_CPU_32v6=y | ||
| 193 | CONFIG_CPU_ABRT_EV6=y | ||
| 194 | CONFIG_CPU_PABRT_V6=y | ||
| 195 | CONFIG_CPU_CACHE_V6=y | ||
| 196 | CONFIG_CPU_CACHE_VIPT=y | ||
| 197 | CONFIG_CPU_COPY_V6=y | ||
| 198 | CONFIG_CPU_TLB_V6=y | ||
| 199 | CONFIG_CPU_HAS_ASID=y | ||
| 200 | CONFIG_CPU_CP15=y | ||
| 201 | CONFIG_CPU_CP15_MMU=y | ||
| 202 | |||
| 203 | # | ||
| 204 | # Processor Features | ||
| 205 | # | ||
| 206 | CONFIG_ARM_THUMB=y | ||
| 207 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 208 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 209 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 210 | CONFIG_OUTER_CACHE=y | ||
| 211 | CONFIG_CACHE_TAUROS2=y | ||
| 212 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
| 213 | # CONFIG_ARM_ERRATA_411920 is not set | ||
| 214 | |||
| 215 | # | ||
| 216 | # Bus support | ||
| 217 | # | ||
| 218 | CONFIG_PCI=y | ||
| 219 | CONFIG_PCI_SYSCALL=y | ||
| 220 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 221 | CONFIG_PCI_LEGACY=y | ||
| 222 | # CONFIG_PCI_DEBUG is not set | ||
| 223 | # CONFIG_PCI_STUB is not set | ||
| 224 | # CONFIG_PCI_IOV is not set | ||
| 225 | # CONFIG_PCCARD is not set | ||
| 226 | |||
| 227 | # | ||
| 228 | # Kernel Features | ||
| 229 | # | ||
| 230 | CONFIG_TICK_ONESHOT=y | ||
| 231 | CONFIG_NO_HZ=y | ||
| 232 | CONFIG_HIGH_RES_TIMERS=y | ||
| 233 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 234 | CONFIG_VMSPLIT_3G=y | ||
| 235 | # CONFIG_VMSPLIT_2G is not set | ||
| 236 | # CONFIG_VMSPLIT_1G is not set | ||
| 237 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 238 | CONFIG_PREEMPT_NONE=y | ||
| 239 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 240 | # CONFIG_PREEMPT is not set | ||
| 241 | CONFIG_HZ=100 | ||
| 242 | CONFIG_AEABI=y | ||
| 243 | CONFIG_OABI_COMPAT=y | ||
| 244 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 245 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 246 | # CONFIG_HIGHMEM is not set | ||
| 247 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 248 | CONFIG_FLATMEM_MANUAL=y | ||
| 249 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 250 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 251 | CONFIG_FLATMEM=y | ||
| 252 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 253 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 254 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 255 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 256 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 257 | CONFIG_VIRT_TO_BUS=y | ||
| 258 | CONFIG_HAVE_MLOCK=y | ||
| 259 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 260 | # CONFIG_KSM is not set | ||
| 261 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 262 | CONFIG_ALIGNMENT_TRAP=y | ||
| 263 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 264 | |||
| 265 | # | ||
| 266 | # Boot options | ||
| 267 | # | ||
| 268 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 269 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 270 | CONFIG_CMDLINE="" | ||
| 271 | # CONFIG_XIP_KERNEL is not set | ||
| 272 | # CONFIG_KEXEC is not set | ||
| 273 | |||
| 274 | # | ||
| 275 | # CPU Power Management | ||
| 276 | # | ||
| 277 | # CONFIG_CPU_IDLE is not set | ||
| 278 | |||
| 279 | # | ||
| 280 | # Floating point emulation | ||
| 281 | # | ||
| 282 | |||
| 283 | # | ||
| 284 | # At least one emulation must be selected | ||
| 285 | # | ||
| 286 | # CONFIG_FPE_NWFPE is not set | ||
| 287 | # CONFIG_FPE_FASTFPE is not set | ||
| 288 | CONFIG_VFP=y | ||
| 289 | |||
| 290 | # | ||
| 291 | # Userspace binary formats | ||
| 292 | # | ||
| 293 | CONFIG_BINFMT_ELF=y | ||
| 294 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 295 | CONFIG_HAVE_AOUT=y | ||
| 296 | # CONFIG_BINFMT_AOUT is not set | ||
| 297 | # CONFIG_BINFMT_MISC is not set | ||
| 298 | |||
| 299 | # | ||
| 300 | # Power management options | ||
| 301 | # | ||
| 302 | # CONFIG_PM is not set | ||
| 303 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 304 | CONFIG_NET=y | ||
| 305 | |||
| 306 | # | ||
| 307 | # Networking options | ||
| 308 | # | ||
| 309 | CONFIG_PACKET=y | ||
| 310 | CONFIG_PACKET_MMAP=y | ||
| 311 | CONFIG_UNIX=y | ||
| 312 | CONFIG_XFRM=y | ||
| 313 | # CONFIG_XFRM_USER is not set | ||
| 314 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 315 | # CONFIG_XFRM_MIGRATE is not set | ||
| 316 | # CONFIG_XFRM_STATISTICS is not set | ||
| 317 | # CONFIG_NET_KEY is not set | ||
| 318 | CONFIG_INET=y | ||
| 319 | CONFIG_IP_MULTICAST=y | ||
| 320 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 321 | CONFIG_IP_FIB_HASH=y | ||
| 322 | CONFIG_IP_PNP=y | ||
| 323 | CONFIG_IP_PNP_DHCP=y | ||
| 324 | CONFIG_IP_PNP_BOOTP=y | ||
| 325 | # CONFIG_IP_PNP_RARP is not set | ||
| 326 | # CONFIG_NET_IPIP is not set | ||
| 327 | # CONFIG_NET_IPGRE is not set | ||
| 328 | # CONFIG_IP_MROUTE is not set | ||
| 329 | # CONFIG_ARPD is not set | ||
| 330 | # CONFIG_SYN_COOKIES is not set | ||
| 331 | # CONFIG_INET_AH is not set | ||
| 332 | # CONFIG_INET_ESP is not set | ||
| 333 | # CONFIG_INET_IPCOMP is not set | ||
| 334 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 335 | # CONFIG_INET_TUNNEL is not set | ||
| 336 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 337 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 338 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 339 | CONFIG_INET_LRO=y | ||
| 340 | CONFIG_INET_DIAG=y | ||
| 341 | CONFIG_INET_TCP_DIAG=y | ||
| 342 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 343 | CONFIG_TCP_CONG_CUBIC=y | ||
| 344 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 345 | # CONFIG_TCP_MD5SIG is not set | ||
| 346 | # CONFIG_IPV6 is not set | ||
| 347 | # CONFIG_NETWORK_SECMARK is not set | ||
| 348 | # CONFIG_NETFILTER is not set | ||
| 349 | # CONFIG_IP_DCCP is not set | ||
| 350 | # CONFIG_IP_SCTP is not set | ||
| 351 | # CONFIG_RDS is not set | ||
| 352 | # CONFIG_TIPC is not set | ||
| 353 | # CONFIG_ATM is not set | ||
| 354 | # CONFIG_BRIDGE is not set | ||
| 355 | # CONFIG_NET_DSA is not set | ||
| 356 | # CONFIG_VLAN_8021Q is not set | ||
| 357 | # CONFIG_DECNET is not set | ||
| 358 | # CONFIG_LLC2 is not set | ||
| 359 | # CONFIG_IPX is not set | ||
| 360 | # CONFIG_ATALK is not set | ||
| 361 | # CONFIG_X25 is not set | ||
| 362 | # CONFIG_LAPB is not set | ||
| 363 | # CONFIG_ECONET is not set | ||
| 364 | # CONFIG_WAN_ROUTER is not set | ||
| 365 | # CONFIG_PHONET is not set | ||
| 366 | # CONFIG_IEEE802154 is not set | ||
| 367 | # CONFIG_NET_SCHED is not set | ||
| 368 | # CONFIG_DCB is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Network testing | ||
| 372 | # | ||
| 373 | # CONFIG_NET_PKTGEN is not set | ||
| 374 | # CONFIG_HAMRADIO is not set | ||
| 375 | # CONFIG_CAN is not set | ||
| 376 | # CONFIG_IRDA is not set | ||
| 377 | # CONFIG_BT is not set | ||
| 378 | # CONFIG_AF_RXRPC is not set | ||
| 379 | # CONFIG_WIRELESS is not set | ||
| 380 | # CONFIG_WIMAX is not set | ||
| 381 | # CONFIG_RFKILL is not set | ||
| 382 | # CONFIG_NET_9P is not set | ||
| 383 | |||
| 384 | # | ||
| 385 | # Device Drivers | ||
| 386 | # | ||
| 387 | |||
| 388 | # | ||
| 389 | # Generic Driver Options | ||
| 390 | # | ||
| 391 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 392 | # CONFIG_DEVTMPFS is not set | ||
| 393 | CONFIG_STANDALONE=y | ||
| 394 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 395 | CONFIG_FW_LOADER=y | ||
| 396 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 397 | CONFIG_EXTRA_FIRMWARE="" | ||
| 398 | # CONFIG_DEBUG_DRIVER is not set | ||
| 399 | # CONFIG_DEBUG_DEVRES is not set | ||
| 400 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 401 | # CONFIG_CONNECTOR is not set | ||
| 402 | CONFIG_MTD=y | ||
| 403 | # CONFIG_MTD_DEBUG is not set | ||
| 404 | # CONFIG_MTD_TESTS is not set | ||
| 405 | # CONFIG_MTD_CONCAT is not set | ||
| 406 | CONFIG_MTD_PARTITIONS=y | ||
| 407 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 408 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 409 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 410 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 411 | |||
| 412 | # | ||
| 413 | # User Modules And Translation Layers | ||
| 414 | # | ||
| 415 | CONFIG_MTD_CHAR=y | ||
| 416 | CONFIG_MTD_BLKDEVS=y | ||
| 417 | CONFIG_MTD_BLOCK=y | ||
| 418 | # CONFIG_FTL is not set | ||
| 419 | # CONFIG_NFTL is not set | ||
| 420 | # CONFIG_INFTL is not set | ||
| 421 | # CONFIG_RFD_FTL is not set | ||
| 422 | # CONFIG_SSFDC is not set | ||
| 423 | # CONFIG_MTD_OOPS is not set | ||
| 424 | |||
| 425 | # | ||
| 426 | # RAM/ROM/Flash chip drivers | ||
| 427 | # | ||
| 428 | CONFIG_MTD_CFI=y | ||
| 429 | CONFIG_MTD_JEDECPROBE=y | ||
| 430 | CONFIG_MTD_GEN_PROBE=y | ||
| 431 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 432 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 433 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 434 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 435 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 436 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 437 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 438 | # CONFIG_MTD_MAP_BANK_WIDTH_4 is not set | ||
| 439 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 440 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 441 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 442 | CONFIG_MTD_CFI_I1=y | ||
| 443 | CONFIG_MTD_CFI_I2=y | ||
| 444 | # CONFIG_MTD_CFI_I4 is not set | ||
| 445 | # CONFIG_MTD_CFI_I8 is not set | ||
| 446 | # CONFIG_MTD_OTP is not set | ||
| 447 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 448 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 449 | CONFIG_MTD_CFI_STAA=y | ||
| 450 | CONFIG_MTD_CFI_UTIL=y | ||
| 451 | # CONFIG_MTD_RAM is not set | ||
| 452 | # CONFIG_MTD_ROM is not set | ||
| 453 | # CONFIG_MTD_ABSENT is not set | ||
| 454 | |||
| 455 | # | ||
| 456 | # Mapping drivers for chip access | ||
| 457 | # | ||
| 458 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 459 | CONFIG_MTD_PHYSMAP=y | ||
| 460 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 461 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 462 | # CONFIG_MTD_IMPA7 is not set | ||
| 463 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 464 | # CONFIG_MTD_PLATRAM is not set | ||
| 465 | |||
| 466 | # | ||
| 467 | # Self-contained MTD device drivers | ||
| 468 | # | ||
| 469 | # CONFIG_MTD_PMC551 is not set | ||
| 470 | # CONFIG_MTD_DATAFLASH is not set | ||
| 471 | CONFIG_MTD_M25P80=y | ||
| 472 | CONFIG_M25PXX_USE_FAST_READ=y | ||
| 473 | # CONFIG_MTD_SST25L is not set | ||
| 474 | # CONFIG_MTD_SLRAM is not set | ||
| 475 | # CONFIG_MTD_PHRAM is not set | ||
| 476 | # CONFIG_MTD_MTDRAM is not set | ||
| 477 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 478 | |||
| 479 | # | ||
| 480 | # Disk-On-Chip Device Drivers | ||
| 481 | # | ||
| 482 | # CONFIG_MTD_DOC2000 is not set | ||
| 483 | # CONFIG_MTD_DOC2001 is not set | ||
| 484 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 485 | # CONFIG_MTD_NAND is not set | ||
| 486 | # CONFIG_MTD_ONENAND is not set | ||
| 487 | |||
| 488 | # | ||
| 489 | # LPDDR flash memory drivers | ||
| 490 | # | ||
| 491 | # CONFIG_MTD_LPDDR is not set | ||
| 492 | |||
| 493 | # | ||
| 494 | # UBI - Unsorted block images | ||
| 495 | # | ||
| 496 | CONFIG_MTD_UBI=y | ||
| 497 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 498 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 499 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 500 | |||
| 501 | # | ||
| 502 | # UBI debugging options | ||
| 503 | # | ||
| 504 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 505 | # CONFIG_PARPORT is not set | ||
| 506 | CONFIG_BLK_DEV=y | ||
| 507 | # CONFIG_BLK_CPQ_DA is not set | ||
| 508 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
| 509 | # CONFIG_BLK_DEV_DAC960 is not set | ||
| 510 | # CONFIG_BLK_DEV_UMEM is not set | ||
| 511 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 512 | CONFIG_BLK_DEV_LOOP=y | ||
| 513 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 514 | # CONFIG_BLK_DEV_NBD is not set | ||
| 515 | # CONFIG_BLK_DEV_SX8 is not set | ||
| 516 | # CONFIG_BLK_DEV_UB is not set | ||
| 517 | CONFIG_BLK_DEV_RAM=y | ||
| 518 | CONFIG_BLK_DEV_RAM_COUNT=1 | ||
| 519 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 520 | # CONFIG_BLK_DEV_XIP is not set | ||
| 521 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 522 | # CONFIG_ATA_OVER_ETH is not set | ||
| 523 | # CONFIG_MG_DISK is not set | ||
| 524 | # CONFIG_MISC_DEVICES is not set | ||
| 525 | CONFIG_HAVE_IDE=y | ||
| 526 | # CONFIG_IDE is not set | ||
| 527 | |||
| 528 | # | ||
| 529 | # SCSI device support | ||
| 530 | # | ||
| 531 | # CONFIG_RAID_ATTRS is not set | ||
| 532 | CONFIG_SCSI=y | ||
| 533 | CONFIG_SCSI_DMA=y | ||
| 534 | # CONFIG_SCSI_TGT is not set | ||
| 535 | # CONFIG_SCSI_NETLINK is not set | ||
| 536 | # CONFIG_SCSI_PROC_FS is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # SCSI support type (disk, tape, CD-ROM) | ||
| 540 | # | ||
| 541 | CONFIG_BLK_DEV_SD=y | ||
| 542 | # CONFIG_CHR_DEV_ST is not set | ||
| 543 | # CONFIG_CHR_DEV_OSST is not set | ||
| 544 | # CONFIG_BLK_DEV_SR is not set | ||
| 545 | # CONFIG_CHR_DEV_SG is not set | ||
| 546 | # CONFIG_CHR_DEV_SCH is not set | ||
| 547 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 548 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 549 | # CONFIG_SCSI_LOGGING is not set | ||
| 550 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 551 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 552 | |||
| 553 | # | ||
| 554 | # SCSI Transports | ||
| 555 | # | ||
| 556 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 557 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 558 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 559 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 560 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 561 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 562 | # CONFIG_SCSI_DH is not set | ||
| 563 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 564 | CONFIG_ATA=y | ||
| 565 | # CONFIG_ATA_NONSTANDARD is not set | ||
| 566 | CONFIG_ATA_VERBOSE_ERROR=y | ||
| 567 | CONFIG_SATA_PMP=y | ||
| 568 | # CONFIG_SATA_AHCI is not set | ||
| 569 | # CONFIG_SATA_SIL24 is not set | ||
| 570 | CONFIG_ATA_SFF=y | ||
| 571 | # CONFIG_SATA_SVW is not set | ||
| 572 | # CONFIG_ATA_PIIX is not set | ||
| 573 | CONFIG_SATA_MV=y | ||
| 574 | # CONFIG_SATA_NV is not set | ||
| 575 | # CONFIG_PDC_ADMA is not set | ||
| 576 | # CONFIG_SATA_QSTOR is not set | ||
| 577 | # CONFIG_SATA_PROMISE is not set | ||
| 578 | # CONFIG_SATA_SX4 is not set | ||
| 579 | # CONFIG_SATA_SIL is not set | ||
| 580 | # CONFIG_SATA_SIS is not set | ||
| 581 | # CONFIG_SATA_ULI is not set | ||
| 582 | # CONFIG_SATA_VIA is not set | ||
| 583 | # CONFIG_SATA_VITESSE is not set | ||
| 584 | # CONFIG_SATA_INIC162X is not set | ||
| 585 | # CONFIG_PATA_ALI is not set | ||
| 586 | # CONFIG_PATA_AMD is not set | ||
| 587 | # CONFIG_PATA_ARTOP is not set | ||
| 588 | # CONFIG_PATA_ATP867X is not set | ||
| 589 | # CONFIG_PATA_ATIIXP is not set | ||
| 590 | # CONFIG_PATA_CMD640_PCI is not set | ||
| 591 | # CONFIG_PATA_CMD64X is not set | ||
| 592 | # CONFIG_PATA_CS5520 is not set | ||
| 593 | # CONFIG_PATA_CS5530 is not set | ||
| 594 | # CONFIG_PATA_CYPRESS is not set | ||
| 595 | # CONFIG_PATA_EFAR is not set | ||
| 596 | # CONFIG_ATA_GENERIC is not set | ||
| 597 | # CONFIG_PATA_HPT366 is not set | ||
| 598 | # CONFIG_PATA_HPT37X is not set | ||
| 599 | # CONFIG_PATA_HPT3X2N is not set | ||
| 600 | # CONFIG_PATA_HPT3X3 is not set | ||
| 601 | # CONFIG_PATA_IT821X is not set | ||
| 602 | # CONFIG_PATA_IT8213 is not set | ||
| 603 | # CONFIG_PATA_JMICRON is not set | ||
| 604 | # CONFIG_PATA_TRIFLEX is not set | ||
| 605 | # CONFIG_PATA_MARVELL is not set | ||
| 606 | # CONFIG_PATA_MPIIX is not set | ||
| 607 | # CONFIG_PATA_OLDPIIX is not set | ||
| 608 | # CONFIG_PATA_NETCELL is not set | ||
| 609 | # CONFIG_PATA_NINJA32 is not set | ||
| 610 | # CONFIG_PATA_NS87410 is not set | ||
| 611 | # CONFIG_PATA_NS87415 is not set | ||
| 612 | # CONFIG_PATA_OPTI is not set | ||
| 613 | # CONFIG_PATA_OPTIDMA is not set | ||
| 614 | # CONFIG_PATA_PDC_OLD is not set | ||
| 615 | # CONFIG_PATA_RADISYS is not set | ||
| 616 | # CONFIG_PATA_RDC is not set | ||
| 617 | # CONFIG_PATA_RZ1000 is not set | ||
| 618 | # CONFIG_PATA_SC1200 is not set | ||
| 619 | # CONFIG_PATA_SERVERWORKS is not set | ||
| 620 | # CONFIG_PATA_PDC2027X is not set | ||
| 621 | # CONFIG_PATA_SIL680 is not set | ||
| 622 | # CONFIG_PATA_SIS is not set | ||
| 623 | # CONFIG_PATA_VIA is not set | ||
| 624 | # CONFIG_PATA_WINBOND is not set | ||
| 625 | # CONFIG_PATA_PLATFORM is not set | ||
| 626 | # CONFIG_PATA_SCH is not set | ||
| 627 | # CONFIG_MD is not set | ||
| 628 | # CONFIG_FUSION is not set | ||
| 629 | |||
| 630 | # | ||
| 631 | # IEEE 1394 (FireWire) support | ||
| 632 | # | ||
| 633 | |||
| 634 | # | ||
| 635 | # You can enable one or both FireWire driver stacks. | ||
| 636 | # | ||
| 637 | |||
| 638 | # | ||
| 639 | # See the help texts for more information. | ||
| 640 | # | ||
| 641 | # CONFIG_FIREWIRE is not set | ||
| 642 | # CONFIG_IEEE1394 is not set | ||
| 643 | # CONFIG_I2O is not set | ||
| 644 | CONFIG_NETDEVICES=y | ||
| 645 | # CONFIG_DUMMY is not set | ||
| 646 | # CONFIG_BONDING is not set | ||
| 647 | # CONFIG_MACVLAN is not set | ||
| 648 | # CONFIG_EQUALIZER is not set | ||
| 649 | # CONFIG_TUN is not set | ||
| 650 | # CONFIG_VETH is not set | ||
| 651 | # CONFIG_ARCNET is not set | ||
| 652 | CONFIG_PHYLIB=y | ||
| 653 | |||
| 654 | # | ||
| 655 | # MII PHY device drivers | ||
| 656 | # | ||
| 657 | # CONFIG_MARVELL_PHY is not set | ||
| 658 | # CONFIG_DAVICOM_PHY is not set | ||
| 659 | # CONFIG_QSEMI_PHY is not set | ||
| 660 | # CONFIG_LXT_PHY is not set | ||
| 661 | # CONFIG_CICADA_PHY is not set | ||
| 662 | # CONFIG_VITESSE_PHY is not set | ||
| 663 | # CONFIG_SMSC_PHY is not set | ||
| 664 | # CONFIG_BROADCOM_PHY is not set | ||
| 665 | # CONFIG_ICPLUS_PHY is not set | ||
| 666 | # CONFIG_REALTEK_PHY is not set | ||
| 667 | # CONFIG_NATIONAL_PHY is not set | ||
| 668 | # CONFIG_STE10XP is not set | ||
| 669 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 670 | # CONFIG_FIXED_PHY is not set | ||
| 671 | # CONFIG_MDIO_BITBANG is not set | ||
| 672 | # CONFIG_NET_ETHERNET is not set | ||
| 673 | CONFIG_NETDEV_1000=y | ||
| 674 | # CONFIG_ACENIC is not set | ||
| 675 | # CONFIG_DL2K is not set | ||
| 676 | # CONFIG_E1000 is not set | ||
| 677 | # CONFIG_E1000E is not set | ||
| 678 | # CONFIG_IP1000 is not set | ||
| 679 | # CONFIG_IGB is not set | ||
| 680 | # CONFIG_IGBVF is not set | ||
| 681 | # CONFIG_NS83820 is not set | ||
| 682 | # CONFIG_HAMACHI is not set | ||
| 683 | # CONFIG_YELLOWFIN is not set | ||
| 684 | # CONFIG_R8169 is not set | ||
| 685 | # CONFIG_SIS190 is not set | ||
| 686 | # CONFIG_SKGE is not set | ||
| 687 | # CONFIG_SKY2 is not set | ||
| 688 | # CONFIG_VIA_VELOCITY is not set | ||
| 689 | # CONFIG_TIGON3 is not set | ||
| 690 | # CONFIG_BNX2 is not set | ||
| 691 | # CONFIG_CNIC is not set | ||
| 692 | CONFIG_MV643XX_ETH=y | ||
| 693 | # CONFIG_QLA3XXX is not set | ||
| 694 | # CONFIG_ATL1 is not set | ||
| 695 | # CONFIG_ATL1E is not set | ||
| 696 | # CONFIG_ATL1C is not set | ||
| 697 | # CONFIG_JME is not set | ||
| 698 | # CONFIG_NETDEV_10000 is not set | ||
| 699 | # CONFIG_TR is not set | ||
| 700 | CONFIG_WLAN=y | ||
| 701 | # CONFIG_WLAN_PRE80211 is not set | ||
| 702 | # CONFIG_WLAN_80211 is not set | ||
| 703 | |||
| 704 | # | ||
| 705 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 706 | # | ||
| 707 | |||
| 708 | # | ||
| 709 | # USB Network Adapters | ||
| 710 | # | ||
| 711 | # CONFIG_USB_CATC is not set | ||
| 712 | # CONFIG_USB_KAWETH is not set | ||
| 713 | # CONFIG_USB_PEGASUS is not set | ||
| 714 | # CONFIG_USB_RTL8150 is not set | ||
| 715 | # CONFIG_USB_USBNET is not set | ||
| 716 | # CONFIG_WAN is not set | ||
| 717 | # CONFIG_FDDI is not set | ||
| 718 | # CONFIG_HIPPI is not set | ||
| 719 | # CONFIG_PPP is not set | ||
| 720 | # CONFIG_SLIP is not set | ||
| 721 | # CONFIG_NET_FC is not set | ||
| 722 | # CONFIG_NETCONSOLE is not set | ||
| 723 | # CONFIG_NETPOLL is not set | ||
| 724 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 725 | # CONFIG_ISDN is not set | ||
| 726 | # CONFIG_PHONE is not set | ||
| 727 | |||
| 728 | # | ||
| 729 | # Input device support | ||
| 730 | # | ||
| 731 | CONFIG_INPUT=y | ||
| 732 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 733 | CONFIG_INPUT_POLLDEV=y | ||
| 734 | |||
| 735 | # | ||
| 736 | # Userland interfaces | ||
| 737 | # | ||
| 738 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 739 | # CONFIG_INPUT_JOYDEV is not set | ||
| 740 | CONFIG_INPUT_EVDEV=y | ||
| 741 | # CONFIG_INPUT_EVBUG is not set | ||
| 742 | |||
| 743 | # | ||
| 744 | # Input Device Drivers | ||
| 745 | # | ||
| 746 | CONFIG_INPUT_KEYBOARD=y | ||
| 747 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 748 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 749 | # CONFIG_QT2160 is not set | ||
| 750 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 751 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 752 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 753 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 754 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 755 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 756 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 757 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 758 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 759 | CONFIG_INPUT_MOUSE=y | ||
| 760 | # CONFIG_MOUSE_PS2 is not set | ||
| 761 | # CONFIG_MOUSE_SERIAL is not set | ||
| 762 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 763 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 764 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 765 | # CONFIG_MOUSE_GPIO is not set | ||
| 766 | # CONFIG_MOUSE_SYNAPTICS_I2C is not set | ||
| 767 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 768 | # CONFIG_INPUT_TABLET is not set | ||
| 769 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 770 | # CONFIG_INPUT_MISC is not set | ||
| 771 | |||
| 772 | # | ||
| 773 | # Hardware I/O ports | ||
| 774 | # | ||
| 775 | # CONFIG_SERIO is not set | ||
| 776 | # CONFIG_GAMEPORT is not set | ||
| 777 | |||
| 778 | # | ||
| 779 | # Character devices | ||
| 780 | # | ||
| 781 | CONFIG_VT=y | ||
| 782 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 783 | CONFIG_VT_CONSOLE=y | ||
| 784 | CONFIG_HW_CONSOLE=y | ||
| 785 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 786 | # CONFIG_DEVKMEM is not set | ||
| 787 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 788 | # CONFIG_NOZOMI is not set | ||
| 789 | |||
| 790 | # | ||
| 791 | # Serial drivers | ||
| 792 | # | ||
| 793 | CONFIG_SERIAL_8250=y | ||
| 794 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 795 | # CONFIG_SERIAL_8250_PCI is not set | ||
| 796 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 797 | CONFIG_SERIAL_8250_RUNTIME_UARTS=2 | ||
| 798 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 799 | |||
| 800 | # | ||
| 801 | # Non-8250 serial port support | ||
| 802 | # | ||
| 803 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 804 | CONFIG_SERIAL_CORE=y | ||
| 805 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 806 | # CONFIG_SERIAL_JSM is not set | ||
| 807 | CONFIG_UNIX98_PTYS=y | ||
| 808 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 809 | CONFIG_LEGACY_PTYS=y | ||
| 810 | CONFIG_LEGACY_PTY_COUNT=16 | ||
| 811 | # CONFIG_IPMI_HANDLER is not set | ||
| 812 | # CONFIG_HW_RANDOM is not set | ||
| 813 | # CONFIG_R3964 is not set | ||
| 814 | # CONFIG_APPLICOM is not set | ||
| 815 | # CONFIG_RAW_DRIVER is not set | ||
| 816 | # CONFIG_TCG_TPM is not set | ||
| 817 | CONFIG_DEVPORT=y | ||
| 818 | CONFIG_I2C=y | ||
| 819 | CONFIG_I2C_BOARDINFO=y | ||
| 820 | CONFIG_I2C_COMPAT=y | ||
| 821 | CONFIG_I2C_CHARDEV=y | ||
| 822 | CONFIG_I2C_HELPER_AUTO=y | ||
| 823 | |||
| 824 | # | ||
| 825 | # I2C Hardware Bus support | ||
| 826 | # | ||
| 827 | |||
| 828 | # | ||
| 829 | # PC SMBus host controller drivers | ||
| 830 | # | ||
| 831 | # CONFIG_I2C_ALI1535 is not set | ||
| 832 | # CONFIG_I2C_ALI1563 is not set | ||
| 833 | # CONFIG_I2C_ALI15X3 is not set | ||
| 834 | # CONFIG_I2C_AMD756 is not set | ||
| 835 | # CONFIG_I2C_AMD8111 is not set | ||
| 836 | # CONFIG_I2C_I801 is not set | ||
| 837 | # CONFIG_I2C_ISCH is not set | ||
| 838 | # CONFIG_I2C_PIIX4 is not set | ||
| 839 | # CONFIG_I2C_NFORCE2 is not set | ||
| 840 | # CONFIG_I2C_SIS5595 is not set | ||
| 841 | # CONFIG_I2C_SIS630 is not set | ||
| 842 | # CONFIG_I2C_SIS96X is not set | ||
| 843 | # CONFIG_I2C_VIA is not set | ||
| 844 | # CONFIG_I2C_VIAPRO is not set | ||
| 845 | |||
| 846 | # | ||
| 847 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 848 | # | ||
| 849 | # CONFIG_I2C_GPIO is not set | ||
| 850 | CONFIG_I2C_MV64XXX=y | ||
| 851 | # CONFIG_I2C_OCORES is not set | ||
| 852 | # CONFIG_I2C_SIMTEC is not set | ||
| 853 | |||
| 854 | # | ||
| 855 | # External I2C/SMBus adapter drivers | ||
| 856 | # | ||
| 857 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 858 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 859 | # CONFIG_I2C_TINY_USB is not set | ||
| 860 | |||
| 861 | # | ||
| 862 | # Graphics adapter I2C/DDC channel drivers | ||
| 863 | # | ||
| 864 | # CONFIG_I2C_VOODOO3 is not set | ||
| 865 | |||
| 866 | # | ||
| 867 | # Other I2C/SMBus bus drivers | ||
| 868 | # | ||
| 869 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 870 | # CONFIG_I2C_STUB is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # Miscellaneous I2C Chip support | ||
| 874 | # | ||
| 875 | # CONFIG_DS1682 is not set | ||
| 876 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 877 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 878 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 879 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 880 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 881 | CONFIG_SPI=y | ||
| 882 | # CONFIG_SPI_DEBUG is not set | ||
| 883 | CONFIG_SPI_MASTER=y | ||
| 884 | |||
| 885 | # | ||
| 886 | # SPI Master Controller Drivers | ||
| 887 | # | ||
| 888 | # CONFIG_SPI_BITBANG is not set | ||
| 889 | # CONFIG_SPI_GPIO is not set | ||
| 890 | CONFIG_SPI_ORION=y | ||
| 891 | |||
| 892 | # | ||
| 893 | # SPI Protocol Masters | ||
| 894 | # | ||
| 895 | # CONFIG_SPI_SPIDEV is not set | ||
| 896 | # CONFIG_SPI_TLE62X0 is not set | ||
| 897 | |||
| 898 | # | ||
| 899 | # PPS support | ||
| 900 | # | ||
| 901 | # CONFIG_PPS is not set | ||
| 902 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 903 | CONFIG_GPIOLIB=y | ||
| 904 | # CONFIG_DEBUG_GPIO is not set | ||
| 905 | # CONFIG_GPIO_SYSFS is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # Memory mapped GPIO expanders: | ||
| 909 | # | ||
| 910 | |||
| 911 | # | ||
| 912 | # I2C GPIO expanders: | ||
| 913 | # | ||
| 914 | # CONFIG_GPIO_MAX732X is not set | ||
| 915 | # CONFIG_GPIO_PCA953X is not set | ||
| 916 | # CONFIG_GPIO_PCF857X is not set | ||
| 917 | |||
| 918 | # | ||
| 919 | # PCI GPIO expanders: | ||
| 920 | # | ||
| 921 | # CONFIG_GPIO_BT8XX is not set | ||
| 922 | # CONFIG_GPIO_LANGWELL is not set | ||
| 923 | |||
| 924 | # | ||
| 925 | # SPI GPIO expanders: | ||
| 926 | # | ||
| 927 | # CONFIG_GPIO_MAX7301 is not set | ||
| 928 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 929 | # CONFIG_GPIO_MC33880 is not set | ||
| 930 | |||
| 931 | # | ||
| 932 | # AC97 GPIO expanders: | ||
| 933 | # | ||
| 934 | # CONFIG_W1 is not set | ||
| 935 | # CONFIG_POWER_SUPPLY is not set | ||
| 936 | # CONFIG_HWMON is not set | ||
| 937 | # CONFIG_THERMAL is not set | ||
| 938 | # CONFIG_WATCHDOG is not set | ||
| 939 | CONFIG_SSB_POSSIBLE=y | ||
| 940 | |||
| 941 | # | ||
| 942 | # Sonics Silicon Backplane | ||
| 943 | # | ||
| 944 | # CONFIG_SSB is not set | ||
| 945 | |||
| 946 | # | ||
| 947 | # Multifunction device drivers | ||
| 948 | # | ||
| 949 | # CONFIG_MFD_CORE is not set | ||
| 950 | # CONFIG_MFD_SM501 is not set | ||
| 951 | # CONFIG_MFD_ASIC3 is not set | ||
| 952 | # CONFIG_HTC_EGPIO is not set | ||
| 953 | # CONFIG_HTC_PASIC3 is not set | ||
| 954 | # CONFIG_TPS65010 is not set | ||
| 955 | # CONFIG_TWL4030_CORE is not set | ||
| 956 | # CONFIG_MFD_TMIO is not set | ||
| 957 | # CONFIG_MFD_TC6393XB is not set | ||
| 958 | # CONFIG_PMIC_DA903X is not set | ||
| 959 | # CONFIG_MFD_WM8400 is not set | ||
| 960 | # CONFIG_MFD_WM831X is not set | ||
| 961 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 962 | # CONFIG_MFD_PCF50633 is not set | ||
| 963 | # CONFIG_MFD_MC13783 is not set | ||
| 964 | # CONFIG_AB3100_CORE is not set | ||
| 965 | # CONFIG_EZX_PCAP is not set | ||
| 966 | # CONFIG_REGULATOR is not set | ||
| 967 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 968 | |||
| 969 | # | ||
| 970 | # Graphics support | ||
| 971 | # | ||
| 972 | CONFIG_VGA_ARB=y | ||
| 973 | # CONFIG_DRM is not set | ||
| 974 | # CONFIG_VGASTATE is not set | ||
| 975 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 976 | # CONFIG_FB is not set | ||
| 977 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 978 | |||
| 979 | # | ||
| 980 | # Display device support | ||
| 981 | # | ||
| 982 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 983 | |||
| 984 | # | ||
| 985 | # Console display driver support | ||
| 986 | # | ||
| 987 | # CONFIG_VGA_CONSOLE is not set | ||
| 988 | CONFIG_DUMMY_CONSOLE=y | ||
| 989 | # CONFIG_SOUND is not set | ||
| 990 | CONFIG_HID_SUPPORT=y | ||
| 991 | CONFIG_HID=y | ||
| 992 | # CONFIG_HIDRAW is not set | ||
| 993 | |||
| 994 | # | ||
| 995 | # USB Input Devices | ||
| 996 | # | ||
| 997 | CONFIG_USB_HID=y | ||
| 998 | # CONFIG_HID_PID is not set | ||
| 999 | # CONFIG_USB_HIDDEV is not set | ||
| 1000 | |||
| 1001 | # | ||
| 1002 | # Special HID drivers | ||
| 1003 | # | ||
| 1004 | # CONFIG_HID_A4TECH is not set | ||
| 1005 | # CONFIG_HID_APPLE is not set | ||
| 1006 | # CONFIG_HID_BELKIN is not set | ||
| 1007 | # CONFIG_HID_CHERRY is not set | ||
| 1008 | # CONFIG_HID_CHICONY is not set | ||
| 1009 | # CONFIG_HID_CYPRESS is not set | ||
| 1010 | # CONFIG_HID_DRAGONRISE is not set | ||
| 1011 | # CONFIG_HID_EZKEY is not set | ||
| 1012 | # CONFIG_HID_KYE is not set | ||
| 1013 | # CONFIG_HID_GYRATION is not set | ||
| 1014 | # CONFIG_HID_TWINHAN is not set | ||
| 1015 | # CONFIG_HID_KENSINGTON is not set | ||
| 1016 | # CONFIG_HID_LOGITECH is not set | ||
| 1017 | # CONFIG_HID_MICROSOFT is not set | ||
| 1018 | # CONFIG_HID_MONTEREY is not set | ||
| 1019 | # CONFIG_HID_NTRIG is not set | ||
| 1020 | # CONFIG_HID_PANTHERLORD is not set | ||
| 1021 | # CONFIG_HID_PETALYNX is not set | ||
| 1022 | # CONFIG_HID_SAMSUNG is not set | ||
| 1023 | # CONFIG_HID_SONY is not set | ||
| 1024 | # CONFIG_HID_SUNPLUS is not set | ||
| 1025 | # CONFIG_HID_GREENASIA is not set | ||
| 1026 | # CONFIG_HID_SMARTJOYPLUS is not set | ||
| 1027 | # CONFIG_HID_TOPSEED is not set | ||
| 1028 | # CONFIG_HID_THRUSTMASTER is not set | ||
| 1029 | # CONFIG_HID_ZEROPLUS is not set | ||
| 1030 | CONFIG_USB_SUPPORT=y | ||
| 1031 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1032 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1033 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 1034 | CONFIG_USB=y | ||
| 1035 | # CONFIG_USB_DEBUG is not set | ||
| 1036 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1037 | |||
| 1038 | # | ||
| 1039 | # Miscellaneous USB options | ||
| 1040 | # | ||
| 1041 | CONFIG_USB_DEVICEFS=y | ||
| 1042 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1043 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1044 | # CONFIG_USB_OTG is not set | ||
| 1045 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1046 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1047 | # CONFIG_USB_MON is not set | ||
| 1048 | # CONFIG_USB_WUSB is not set | ||
| 1049 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # USB Host Controller Drivers | ||
| 1053 | # | ||
| 1054 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1055 | # CONFIG_USB_XHCI_HCD is not set | ||
| 1056 | CONFIG_USB_EHCI_HCD=y | ||
| 1057 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 1058 | CONFIG_USB_EHCI_TT_NEWSCHED=y | ||
| 1059 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1060 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1061 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1062 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1063 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1064 | # CONFIG_USB_UHCI_HCD is not set | ||
| 1065 | # CONFIG_USB_SL811_HCD is not set | ||
| 1066 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1067 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1068 | # CONFIG_USB_HWA_HCD is not set | ||
| 1069 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1070 | |||
| 1071 | # | ||
| 1072 | # USB Device Class drivers | ||
| 1073 | # | ||
| 1074 | # CONFIG_USB_ACM is not set | ||
| 1075 | # CONFIG_USB_PRINTER is not set | ||
| 1076 | # CONFIG_USB_WDM is not set | ||
| 1077 | # CONFIG_USB_TMC is not set | ||
| 1078 | |||
| 1079 | # | ||
| 1080 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 1081 | # | ||
| 1082 | |||
| 1083 | # | ||
| 1084 | # also be needed; see USB_STORAGE Help for more info | ||
| 1085 | # | ||
| 1086 | CONFIG_USB_STORAGE=y | ||
| 1087 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1088 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1089 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1090 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1091 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1092 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1093 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1094 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1095 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1096 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1097 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1098 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1099 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1100 | |||
| 1101 | # | ||
| 1102 | # USB Imaging devices | ||
| 1103 | # | ||
| 1104 | # CONFIG_USB_MDC800 is not set | ||
| 1105 | # CONFIG_USB_MICROTEK is not set | ||
| 1106 | |||
| 1107 | # | ||
| 1108 | # USB port drivers | ||
| 1109 | # | ||
| 1110 | # CONFIG_USB_SERIAL is not set | ||
| 1111 | |||
| 1112 | # | ||
| 1113 | # USB Miscellaneous drivers | ||
| 1114 | # | ||
| 1115 | # CONFIG_USB_EMI62 is not set | ||
| 1116 | # CONFIG_USB_EMI26 is not set | ||
| 1117 | # CONFIG_USB_ADUTUX is not set | ||
| 1118 | # CONFIG_USB_SEVSEG is not set | ||
| 1119 | # CONFIG_USB_RIO500 is not set | ||
| 1120 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1121 | # CONFIG_USB_LCD is not set | ||
| 1122 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1123 | # CONFIG_USB_LED is not set | ||
| 1124 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1125 | # CONFIG_USB_CYTHERM is not set | ||
| 1126 | # CONFIG_USB_IDMOUSE is not set | ||
| 1127 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1128 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1129 | # CONFIG_USB_SISUSBVGA is not set | ||
| 1130 | # CONFIG_USB_LD is not set | ||
| 1131 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1132 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1133 | # CONFIG_USB_TEST is not set | ||
| 1134 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1135 | # CONFIG_USB_VST is not set | ||
| 1136 | # CONFIG_USB_GADGET is not set | ||
| 1137 | |||
| 1138 | # | ||
| 1139 | # OTG and related infrastructure | ||
| 1140 | # | ||
| 1141 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1142 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1143 | # CONFIG_UWB is not set | ||
| 1144 | # CONFIG_MMC is not set | ||
| 1145 | # CONFIG_MEMSTICK is not set | ||
| 1146 | # CONFIG_NEW_LEDS is not set | ||
| 1147 | # CONFIG_ACCESSIBILITY is not set | ||
| 1148 | # CONFIG_INFINIBAND is not set | ||
| 1149 | CONFIG_RTC_LIB=y | ||
| 1150 | CONFIG_RTC_CLASS=y | ||
| 1151 | CONFIG_RTC_HCTOSYS=y | ||
| 1152 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1153 | # CONFIG_RTC_DEBUG is not set | ||
| 1154 | |||
| 1155 | # | ||
| 1156 | # RTC interfaces | ||
| 1157 | # | ||
| 1158 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1159 | CONFIG_RTC_INTF_PROC=y | ||
| 1160 | CONFIG_RTC_INTF_DEV=y | ||
| 1161 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1162 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1163 | |||
| 1164 | # | ||
| 1165 | # I2C RTC drivers | ||
| 1166 | # | ||
| 1167 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1168 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1169 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1170 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1171 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1172 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1173 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1174 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1175 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1176 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1177 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1178 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1179 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1180 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1181 | |||
| 1182 | # | ||
| 1183 | # SPI RTC drivers | ||
| 1184 | # | ||
| 1185 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1186 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1187 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1188 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1189 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1190 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1191 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1192 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1193 | |||
| 1194 | # | ||
| 1195 | # Platform RTC drivers | ||
| 1196 | # | ||
| 1197 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1198 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1199 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1200 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1201 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1202 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1203 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1204 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1205 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1206 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1207 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1208 | |||
| 1209 | # | ||
| 1210 | # on-CPU RTC drivers | ||
| 1211 | # | ||
| 1212 | CONFIG_RTC_DRV_MV=y | ||
| 1213 | CONFIG_DMADEVICES=y | ||
| 1214 | |||
| 1215 | # | ||
| 1216 | # DMA Devices | ||
| 1217 | # | ||
| 1218 | CONFIG_MV_XOR=y | ||
| 1219 | CONFIG_DMA_ENGINE=y | ||
| 1220 | |||
| 1221 | # | ||
| 1222 | # DMA Clients | ||
| 1223 | # | ||
| 1224 | # CONFIG_NET_DMA is not set | ||
| 1225 | # CONFIG_ASYNC_TX_DMA is not set | ||
| 1226 | # CONFIG_DMATEST is not set | ||
| 1227 | # CONFIG_AUXDISPLAY is not set | ||
| 1228 | # CONFIG_UIO is not set | ||
| 1229 | |||
| 1230 | # | ||
| 1231 | # TI VLYNQ | ||
| 1232 | # | ||
| 1233 | # CONFIG_STAGING is not set | ||
| 1234 | |||
| 1235 | # | ||
| 1236 | # File systems | ||
| 1237 | # | ||
| 1238 | CONFIG_EXT2_FS=y | ||
| 1239 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1240 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1241 | CONFIG_EXT3_FS=y | ||
| 1242 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1243 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1244 | # CONFIG_EXT4_FS is not set | ||
| 1245 | CONFIG_JBD=y | ||
| 1246 | # CONFIG_JBD_DEBUG is not set | ||
| 1247 | # CONFIG_REISERFS_FS is not set | ||
| 1248 | # CONFIG_JFS_FS is not set | ||
| 1249 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1250 | # CONFIG_XFS_FS is not set | ||
| 1251 | # CONFIG_GFS2_FS is not set | ||
| 1252 | # CONFIG_OCFS2_FS is not set | ||
| 1253 | # CONFIG_BTRFS_FS is not set | ||
| 1254 | # CONFIG_NILFS2_FS is not set | ||
| 1255 | CONFIG_FILE_LOCKING=y | ||
| 1256 | CONFIG_FSNOTIFY=y | ||
| 1257 | CONFIG_DNOTIFY=y | ||
| 1258 | CONFIG_INOTIFY=y | ||
| 1259 | CONFIG_INOTIFY_USER=y | ||
| 1260 | # CONFIG_QUOTA is not set | ||
| 1261 | # CONFIG_AUTOFS_FS is not set | ||
| 1262 | # CONFIG_AUTOFS4_FS is not set | ||
| 1263 | # CONFIG_FUSE_FS is not set | ||
| 1264 | |||
| 1265 | # | ||
| 1266 | # Caches | ||
| 1267 | # | ||
| 1268 | # CONFIG_FSCACHE is not set | ||
| 1269 | |||
| 1270 | # | ||
| 1271 | # CD-ROM/DVD Filesystems | ||
| 1272 | # | ||
| 1273 | CONFIG_ISO9660_FS=y | ||
| 1274 | CONFIG_JOLIET=y | ||
| 1275 | # CONFIG_ZISOFS is not set | ||
| 1276 | CONFIG_UDF_FS=m | ||
| 1277 | CONFIG_UDF_NLS=y | ||
| 1278 | |||
| 1279 | # | ||
| 1280 | # DOS/FAT/NT Filesystems | ||
| 1281 | # | ||
| 1282 | CONFIG_FAT_FS=y | ||
| 1283 | CONFIG_MSDOS_FS=y | ||
| 1284 | CONFIG_VFAT_FS=y | ||
| 1285 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1286 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1287 | # CONFIG_NTFS_FS is not set | ||
| 1288 | |||
| 1289 | # | ||
| 1290 | # Pseudo filesystems | ||
| 1291 | # | ||
| 1292 | CONFIG_PROC_FS=y | ||
| 1293 | CONFIG_PROC_SYSCTL=y | ||
| 1294 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1295 | CONFIG_SYSFS=y | ||
| 1296 | CONFIG_TMPFS=y | ||
| 1297 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1298 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1299 | # CONFIG_CONFIGFS_FS is not set | ||
| 1300 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1301 | # CONFIG_ADFS_FS is not set | ||
| 1302 | # CONFIG_AFFS_FS is not set | ||
| 1303 | # CONFIG_HFS_FS is not set | ||
| 1304 | # CONFIG_HFSPLUS_FS is not set | ||
| 1305 | # CONFIG_BEFS_FS is not set | ||
| 1306 | # CONFIG_BFS_FS is not set | ||
| 1307 | # CONFIG_EFS_FS is not set | ||
| 1308 | CONFIG_JFFS2_FS=y | ||
| 1309 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1310 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1311 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1312 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 1313 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1314 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1315 | CONFIG_JFFS2_ZLIB=y | ||
| 1316 | # CONFIG_JFFS2_LZO is not set | ||
| 1317 | CONFIG_JFFS2_RTIME=y | ||
| 1318 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1319 | # CONFIG_UBIFS_FS is not set | ||
| 1320 | # CONFIG_CRAMFS is not set | ||
| 1321 | # CONFIG_SQUASHFS is not set | ||
| 1322 | # CONFIG_VXFS_FS is not set | ||
| 1323 | # CONFIG_MINIX_FS is not set | ||
| 1324 | # CONFIG_OMFS_FS is not set | ||
| 1325 | # CONFIG_HPFS_FS is not set | ||
| 1326 | # CONFIG_QNX4FS_FS is not set | ||
| 1327 | # CONFIG_ROMFS_FS is not set | ||
| 1328 | # CONFIG_SYSV_FS is not set | ||
| 1329 | # CONFIG_UFS_FS is not set | ||
| 1330 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1331 | CONFIG_NFS_FS=y | ||
| 1332 | CONFIG_NFS_V3=y | ||
| 1333 | # CONFIG_NFS_V3_ACL is not set | ||
| 1334 | # CONFIG_NFS_V4 is not set | ||
| 1335 | CONFIG_ROOT_NFS=y | ||
| 1336 | # CONFIG_NFSD is not set | ||
| 1337 | CONFIG_LOCKD=y | ||
| 1338 | CONFIG_LOCKD_V4=y | ||
| 1339 | CONFIG_NFS_COMMON=y | ||
| 1340 | CONFIG_SUNRPC=y | ||
| 1341 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1342 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1343 | # CONFIG_SMB_FS is not set | ||
| 1344 | # CONFIG_CIFS is not set | ||
| 1345 | # CONFIG_NCP_FS is not set | ||
| 1346 | # CONFIG_CODA_FS is not set | ||
| 1347 | # CONFIG_AFS_FS is not set | ||
| 1348 | |||
| 1349 | # | ||
| 1350 | # Partition Types | ||
| 1351 | # | ||
| 1352 | CONFIG_PARTITION_ADVANCED=y | ||
| 1353 | # CONFIG_ACORN_PARTITION is not set | ||
| 1354 | # CONFIG_OSF_PARTITION is not set | ||
| 1355 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1356 | # CONFIG_ATARI_PARTITION is not set | ||
| 1357 | # CONFIG_MAC_PARTITION is not set | ||
| 1358 | CONFIG_MSDOS_PARTITION=y | ||
| 1359 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1360 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1361 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1362 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1363 | # CONFIG_LDM_PARTITION is not set | ||
| 1364 | # CONFIG_SGI_PARTITION is not set | ||
| 1365 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1366 | # CONFIG_SUN_PARTITION is not set | ||
| 1367 | # CONFIG_KARMA_PARTITION is not set | ||
| 1368 | # CONFIG_EFI_PARTITION is not set | ||
| 1369 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1370 | CONFIG_NLS=y | ||
| 1371 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1372 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1373 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1374 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1375 | CONFIG_NLS_CODEPAGE_850=y | ||
| 1376 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1377 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1378 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1379 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1380 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1381 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1382 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1383 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1384 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1385 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1386 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1387 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1388 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1389 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1390 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1391 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1392 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1393 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1394 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1395 | # CONFIG_NLS_ASCII is not set | ||
| 1396 | CONFIG_NLS_ISO8859_1=y | ||
| 1397 | CONFIG_NLS_ISO8859_2=y | ||
| 1398 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1399 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1400 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1401 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1402 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1403 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1404 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1405 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1406 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1407 | # CONFIG_NLS_KOI8_R is not set | ||
| 1408 | # CONFIG_NLS_KOI8_U is not set | ||
| 1409 | CONFIG_NLS_UTF8=y | ||
| 1410 | # CONFIG_DLM is not set | ||
| 1411 | |||
| 1412 | # | ||
| 1413 | # Kernel hacking | ||
| 1414 | # | ||
| 1415 | # CONFIG_PRINTK_TIME is not set | ||
| 1416 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1417 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1418 | CONFIG_FRAME_WARN=1024 | ||
| 1419 | CONFIG_MAGIC_SYSRQ=y | ||
| 1420 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1421 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1422 | CONFIG_DEBUG_FS=y | ||
| 1423 | # CONFIG_HEADERS_CHECK is not set | ||
| 1424 | CONFIG_DEBUG_KERNEL=y | ||
| 1425 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1426 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1427 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1428 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1429 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1430 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1431 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1432 | # CONFIG_SCHED_DEBUG is not set | ||
| 1433 | # CONFIG_SCHEDSTATS is not set | ||
| 1434 | CONFIG_TIMER_STATS=y | ||
| 1435 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1436 | # CONFIG_DEBUG_SLAB is not set | ||
| 1437 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1438 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1439 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1440 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1441 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1442 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1443 | # CONFIG_PROVE_LOCKING is not set | ||
| 1444 | # CONFIG_LOCK_STAT is not set | ||
| 1445 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1446 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1447 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1448 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1449 | CONFIG_DEBUG_INFO=y | ||
| 1450 | # CONFIG_DEBUG_VM is not set | ||
| 1451 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1452 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1453 | # CONFIG_DEBUG_LIST is not set | ||
| 1454 | # CONFIG_DEBUG_SG is not set | ||
| 1455 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1456 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1457 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1458 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1459 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1460 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1461 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1462 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1463 | # CONFIG_FAULT_INJECTION is not set | ||
| 1464 | # CONFIG_LATENCYTOP is not set | ||
| 1465 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1466 | # CONFIG_PAGE_POISONING is not set | ||
| 1467 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1468 | CONFIG_TRACING_SUPPORT=y | ||
| 1469 | CONFIG_FTRACE=y | ||
| 1470 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1471 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1472 | # CONFIG_SCHED_TRACER is not set | ||
| 1473 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set | ||
| 1474 | # CONFIG_BOOT_TRACER is not set | ||
| 1475 | CONFIG_BRANCH_PROFILE_NONE=y | ||
| 1476 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 1477 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 1478 | # CONFIG_STACK_TRACER is not set | ||
| 1479 | # CONFIG_KMEMTRACE is not set | ||
| 1480 | # CONFIG_WORKQUEUE_TRACER is not set | ||
| 1481 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 1482 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 1483 | # CONFIG_SAMPLES is not set | ||
| 1484 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1485 | # CONFIG_KGDB is not set | ||
| 1486 | CONFIG_ARM_UNWIND=y | ||
| 1487 | CONFIG_DEBUG_USER=y | ||
| 1488 | CONFIG_DEBUG_ERRORS=y | ||
| 1489 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1490 | # CONFIG_DEBUG_LL is not set | ||
| 1491 | |||
| 1492 | # | ||
| 1493 | # Security options | ||
| 1494 | # | ||
| 1495 | # CONFIG_KEYS is not set | ||
| 1496 | # CONFIG_SECURITY is not set | ||
| 1497 | # CONFIG_SECURITYFS is not set | ||
| 1498 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1499 | CONFIG_CRYPTO=y | ||
| 1500 | |||
| 1501 | # | ||
| 1502 | # Crypto core or helper | ||
| 1503 | # | ||
| 1504 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1505 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1506 | CONFIG_CRYPTO_AEAD2=y | ||
| 1507 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1508 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1509 | CONFIG_CRYPTO_HASH=y | ||
| 1510 | CONFIG_CRYPTO_HASH2=y | ||
| 1511 | CONFIG_CRYPTO_RNG2=y | ||
| 1512 | CONFIG_CRYPTO_PCOMP=y | ||
| 1513 | CONFIG_CRYPTO_MANAGER=y | ||
| 1514 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1515 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1516 | CONFIG_CRYPTO_NULL=y | ||
| 1517 | CONFIG_CRYPTO_WORKQUEUE=y | ||
| 1518 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1519 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1520 | # CONFIG_CRYPTO_TEST is not set | ||
| 1521 | |||
| 1522 | # | ||
| 1523 | # Authenticated Encryption with Associated Data | ||
| 1524 | # | ||
| 1525 | # CONFIG_CRYPTO_CCM is not set | ||
| 1526 | # CONFIG_CRYPTO_GCM is not set | ||
| 1527 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1528 | |||
| 1529 | # | ||
| 1530 | # Block modes | ||
| 1531 | # | ||
| 1532 | CONFIG_CRYPTO_CBC=y | ||
| 1533 | # CONFIG_CRYPTO_CTR is not set | ||
| 1534 | # CONFIG_CRYPTO_CTS is not set | ||
| 1535 | CONFIG_CRYPTO_ECB=m | ||
| 1536 | # CONFIG_CRYPTO_LRW is not set | ||
| 1537 | CONFIG_CRYPTO_PCBC=m | ||
| 1538 | # CONFIG_CRYPTO_XTS is not set | ||
| 1539 | |||
| 1540 | # | ||
| 1541 | # Hash modes | ||
| 1542 | # | ||
| 1543 | CONFIG_CRYPTO_HMAC=y | ||
| 1544 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1545 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1546 | |||
| 1547 | # | ||
| 1548 | # Digest | ||
| 1549 | # | ||
| 1550 | CONFIG_CRYPTO_CRC32C=y | ||
| 1551 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1552 | CONFIG_CRYPTO_MD4=y | ||
| 1553 | CONFIG_CRYPTO_MD5=y | ||
| 1554 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1555 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1556 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1557 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1558 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1559 | CONFIG_CRYPTO_SHA1=y | ||
| 1560 | CONFIG_CRYPTO_SHA256=y | ||
| 1561 | CONFIG_CRYPTO_SHA512=y | ||
| 1562 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1563 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1564 | |||
| 1565 | # | ||
| 1566 | # Ciphers | ||
| 1567 | # | ||
| 1568 | CONFIG_CRYPTO_AES=y | ||
| 1569 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1570 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1571 | CONFIG_CRYPTO_BLOWFISH=y | ||
| 1572 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1573 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1574 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1575 | CONFIG_CRYPTO_DES=y | ||
| 1576 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1577 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1578 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1579 | # CONFIG_CRYPTO_SEED is not set | ||
| 1580 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1581 | CONFIG_CRYPTO_TEA=y | ||
| 1582 | CONFIG_CRYPTO_TWOFISH=y | ||
| 1583 | CONFIG_CRYPTO_TWOFISH_COMMON=y | ||
| 1584 | |||
| 1585 | # | ||
| 1586 | # Compression | ||
| 1587 | # | ||
| 1588 | CONFIG_CRYPTO_DEFLATE=y | ||
| 1589 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1590 | CONFIG_CRYPTO_LZO=y | ||
| 1591 | |||
| 1592 | # | ||
| 1593 | # Random Number Generation | ||
| 1594 | # | ||
| 1595 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1596 | CONFIG_CRYPTO_HW=y | ||
| 1597 | # CONFIG_CRYPTO_DEV_MV_CESA is not set | ||
| 1598 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
| 1599 | # CONFIG_BINARY_PRINTF is not set | ||
| 1600 | |||
| 1601 | # | ||
| 1602 | # Library routines | ||
| 1603 | # | ||
| 1604 | CONFIG_BITREVERSE=y | ||
| 1605 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1606 | CONFIG_CRC_CCITT=y | ||
| 1607 | CONFIG_CRC16=y | ||
| 1608 | # CONFIG_CRC_T10DIF is not set | ||
| 1609 | CONFIG_CRC_ITU_T=m | ||
| 1610 | CONFIG_CRC32=y | ||
| 1611 | # CONFIG_CRC7 is not set | ||
| 1612 | CONFIG_LIBCRC32C=y | ||
| 1613 | CONFIG_ZLIB_INFLATE=y | ||
| 1614 | CONFIG_ZLIB_DEFLATE=y | ||
| 1615 | CONFIG_LZO_COMPRESS=y | ||
| 1616 | CONFIG_LZO_DECOMPRESS=y | ||
| 1617 | CONFIG_HAS_IOMEM=y | ||
| 1618 | CONFIG_HAS_IOPORT=y | ||
| 1619 | CONFIG_HAS_DMA=y | ||
| 1620 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig index d5ee16e6abf3..492f29aba332 100644 --- a/arch/arm/configs/ezx_defconfig +++ b/arch/arm/configs/ezx_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.26-rc3 | 3 | # Linux kernel version: 2.6.32-rc5 |
| 4 | # Mon Jul 7 17:52:21 2008 | 4 | # Mon Nov 2 13:18:50 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_HAVE_PWM=y | 7 | CONFIG_HAVE_PWM=y |
| @@ -9,24 +9,22 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y | |||
| 9 | CONFIG_GENERIC_GPIO=y | 9 | CONFIG_GENERIC_GPIO=y |
| 10 | CONFIG_GENERIC_TIME=y | 10 | CONFIG_GENERIC_TIME=y |
| 11 | CONFIG_GENERIC_CLOCKEVENTS=y | 11 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 12 | CONFIG_MMU=y | ||
| 13 | # CONFIG_NO_IOPORT is not set | ||
| 14 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
| 15 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
| 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | 15 | CONFIG_LOCKDEP_SUPPORT=y |
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 20 | CONFIG_ARCH_HAS_CPUFREQ=y |
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | 21 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 22 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | ||
| 27 | CONFIG_ARCH_MTD_XIP=y | 23 | CONFIG_ARCH_MTD_XIP=y |
| 24 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 28 | CONFIG_VECTORS_BASE=0xffff0000 | 25 | CONFIG_VECTORS_BASE=0xffff0000 |
| 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 27 | CONFIG_CONSTRUCTORS=y | ||
| 30 | 28 | ||
| 31 | # | 29 | # |
| 32 | # General setup | 30 | # General setup |
| @@ -35,7 +33,7 @@ CONFIG_EXPERIMENTAL=y | |||
| 35 | CONFIG_BROKEN_ON_SMP=y | 33 | CONFIG_BROKEN_ON_SMP=y |
| 36 | CONFIG_LOCK_KERNEL=y | 34 | CONFIG_LOCK_KERNEL=y |
| 37 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 38 | CONFIG_LOCALVERSION="-ezxdev" | 36 | CONFIG_LOCALVERSION="-ezx200910312315" |
| 39 | # CONFIG_LOCALVERSION_AUTO is not set | 37 | # CONFIG_LOCALVERSION_AUTO is not set |
| 40 | CONFIG_SWAP=y | 38 | CONFIG_SWAP=y |
| 41 | CONFIG_SYSVIPC=y | 39 | CONFIG_SYSVIPC=y |
| @@ -44,56 +42,78 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 44 | # CONFIG_BSD_PROCESS_ACCT is not set | 42 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 45 | # CONFIG_TASKSTATS is not set | 43 | # CONFIG_TASKSTATS is not set |
| 46 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 47 | CONFIG_IKCONFIG=y | 45 | |
| 48 | CONFIG_IKCONFIG_PROC=y | 46 | # |
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_TREE_RCU=y | ||
| 50 | # CONFIG_TREE_PREEMPT_RCU is not set | ||
| 51 | # CONFIG_RCU_TRACE is not set | ||
| 52 | CONFIG_RCU_FANOUT=32 | ||
| 53 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_IKCONFIG is not set | ||
| 49 | CONFIG_LOG_BUF_SHIFT=14 | 56 | CONFIG_LOG_BUF_SHIFT=14 |
| 50 | # CONFIG_CGROUPS is not set | ||
| 51 | CONFIG_GROUP_SCHED=y | 57 | CONFIG_GROUP_SCHED=y |
| 52 | CONFIG_FAIR_GROUP_SCHED=y | 58 | CONFIG_FAIR_GROUP_SCHED=y |
| 53 | # CONFIG_RT_GROUP_SCHED is not set | 59 | # CONFIG_RT_GROUP_SCHED is not set |
| 54 | CONFIG_USER_SCHED=y | 60 | CONFIG_USER_SCHED=y |
| 55 | # CONFIG_CGROUP_SCHED is not set | 61 | # CONFIG_CGROUP_SCHED is not set |
| 62 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | 63 | CONFIG_SYSFS_DEPRECATED=y |
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | 64 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 58 | # CONFIG_RELAY is not set | 65 | # CONFIG_RELAY is not set |
| 59 | # CONFIG_NAMESPACES is not set | 66 | # CONFIG_NAMESPACES is not set |
| 60 | # CONFIG_BLK_DEV_INITRD is not set | 67 | CONFIG_BLK_DEV_INITRD=y |
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_RD_GZIP=y | ||
| 70 | CONFIG_RD_BZIP2=y | ||
| 71 | CONFIG_RD_LZMA=y | ||
| 61 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 72 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 62 | CONFIG_SYSCTL=y | 73 | CONFIG_SYSCTL=y |
| 74 | CONFIG_ANON_INODES=y | ||
| 63 | CONFIG_EMBEDDED=y | 75 | CONFIG_EMBEDDED=y |
| 64 | CONFIG_UID16=y | 76 | CONFIG_UID16=y |
| 65 | CONFIG_SYSCTL_SYSCALL=y | 77 | CONFIG_SYSCTL_SYSCALL=y |
| 66 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 67 | CONFIG_KALLSYMS=y | 78 | CONFIG_KALLSYMS=y |
| 79 | CONFIG_KALLSYMS_ALL=y | ||
| 68 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 80 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 69 | CONFIG_HOTPLUG=y | 81 | CONFIG_HOTPLUG=y |
| 70 | CONFIG_PRINTK=y | 82 | CONFIG_PRINTK=y |
| 71 | CONFIG_BUG=y | 83 | CONFIG_BUG=y |
| 72 | CONFIG_ELF_CORE=y | 84 | CONFIG_ELF_CORE=y |
| 73 | # CONFIG_COMPAT_BRK is not set | ||
| 74 | CONFIG_BASE_FULL=y | 85 | CONFIG_BASE_FULL=y |
| 75 | CONFIG_FUTEX=y | 86 | CONFIG_FUTEX=y |
| 76 | CONFIG_ANON_INODES=y | ||
| 77 | CONFIG_EPOLL=y | 87 | CONFIG_EPOLL=y |
| 78 | CONFIG_SIGNALFD=y | 88 | CONFIG_SIGNALFD=y |
| 79 | CONFIG_TIMERFD=y | 89 | CONFIG_TIMERFD=y |
| 80 | CONFIG_EVENTFD=y | 90 | CONFIG_EVENTFD=y |
| 81 | CONFIG_SHMEM=y | 91 | CONFIG_SHMEM=y |
| 92 | CONFIG_AIO=y | ||
| 93 | |||
| 94 | # | ||
| 95 | # Kernel Performance Events And Counters | ||
| 96 | # | ||
| 82 | CONFIG_VM_EVENT_COUNTERS=y | 97 | CONFIG_VM_EVENT_COUNTERS=y |
| 98 | # CONFIG_COMPAT_BRK is not set | ||
| 83 | CONFIG_SLAB=y | 99 | CONFIG_SLAB=y |
| 84 | # CONFIG_SLUB is not set | 100 | # CONFIG_SLUB is not set |
| 85 | # CONFIG_SLOB is not set | 101 | # CONFIG_SLOB is not set |
| 86 | # CONFIG_PROFILING is not set | 102 | # CONFIG_PROFILING is not set |
| 87 | # CONFIG_MARKERS is not set | ||
| 88 | CONFIG_HAVE_OPROFILE=y | 103 | CONFIG_HAVE_OPROFILE=y |
| 89 | # CONFIG_KPROBES is not set | 104 | # CONFIG_KPROBES is not set |
| 90 | CONFIG_HAVE_KPROBES=y | 105 | CONFIG_HAVE_KPROBES=y |
| 91 | CONFIG_HAVE_KRETPROBES=y | 106 | CONFIG_HAVE_KRETPROBES=y |
| 92 | # CONFIG_HAVE_DMA_ATTRS is not set | 107 | CONFIG_HAVE_CLK=y |
| 93 | CONFIG_PROC_PAGE_MONITOR=y | 108 | |
| 109 | # | ||
| 110 | # GCOV-based kernel profiling | ||
| 111 | # | ||
| 112 | # CONFIG_GCOV_KERNEL is not set | ||
| 113 | CONFIG_SLOW_WORK=y | ||
| 114 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 94 | CONFIG_SLABINFO=y | 115 | CONFIG_SLABINFO=y |
| 95 | CONFIG_RT_MUTEXES=y | 116 | CONFIG_RT_MUTEXES=y |
| 96 | # CONFIG_TINY_SHMEM is not set | ||
| 97 | CONFIG_BASE_SMALL=0 | 117 | CONFIG_BASE_SMALL=0 |
| 98 | CONFIG_MODULES=y | 118 | CONFIG_MODULES=y |
| 99 | # CONFIG_MODULE_FORCE_LOAD is not set | 119 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -101,12 +121,10 @@ CONFIG_MODULE_UNLOAD=y | |||
| 101 | CONFIG_MODULE_FORCE_UNLOAD=y | 121 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 102 | CONFIG_MODVERSIONS=y | 122 | CONFIG_MODVERSIONS=y |
| 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 123 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 104 | CONFIG_KMOD=y | ||
| 105 | CONFIG_BLOCK=y | 124 | CONFIG_BLOCK=y |
| 106 | # CONFIG_LBD is not set | 125 | # CONFIG_LBDAF is not set |
| 107 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 108 | # CONFIG_LSF is not set | ||
| 109 | # CONFIG_BLK_DEV_BSG is not set | 126 | # CONFIG_BLK_DEV_BSG is not set |
| 127 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 110 | 128 | ||
| 111 | # | 129 | # |
| 112 | # IO Schedulers | 130 | # IO Schedulers |
| @@ -120,25 +138,27 @@ CONFIG_DEFAULT_DEADLINE=y | |||
| 120 | # CONFIG_DEFAULT_CFQ is not set | 138 | # CONFIG_DEFAULT_CFQ is not set |
| 121 | # CONFIG_DEFAULT_NOOP is not set | 139 | # CONFIG_DEFAULT_NOOP is not set |
| 122 | CONFIG_DEFAULT_IOSCHED="deadline" | 140 | CONFIG_DEFAULT_IOSCHED="deadline" |
| 123 | CONFIG_CLASSIC_RCU=y | 141 | CONFIG_FREEZER=y |
| 124 | 142 | ||
| 125 | # | 143 | # |
| 126 | # System Type | 144 | # System Type |
| 127 | # | 145 | # |
| 146 | CONFIG_MMU=y | ||
| 128 | # CONFIG_ARCH_AAEC2000 is not set | 147 | # CONFIG_ARCH_AAEC2000 is not set |
| 129 | # CONFIG_ARCH_INTEGRATOR is not set | 148 | # CONFIG_ARCH_INTEGRATOR is not set |
| 130 | # CONFIG_ARCH_REALVIEW is not set | 149 | # CONFIG_ARCH_REALVIEW is not set |
| 131 | # CONFIG_ARCH_VERSATILE is not set | 150 | # CONFIG_ARCH_VERSATILE is not set |
| 132 | # CONFIG_ARCH_AT91 is not set | 151 | # CONFIG_ARCH_AT91 is not set |
| 133 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 134 | # CONFIG_ARCH_CLPS711X is not set | 152 | # CONFIG_ARCH_CLPS711X is not set |
| 135 | # CONFIG_ARCH_CO285 is not set | 153 | # CONFIG_ARCH_GEMINI is not set |
| 136 | # CONFIG_ARCH_EBSA110 is not set | 154 | # CONFIG_ARCH_EBSA110 is not set |
| 137 | # CONFIG_ARCH_EP93XX is not set | 155 | # CONFIG_ARCH_EP93XX is not set |
| 138 | # CONFIG_ARCH_FOOTBRIDGE is not set | 156 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 157 | # CONFIG_ARCH_MXC is not set | ||
| 158 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 139 | # CONFIG_ARCH_NETX is not set | 159 | # CONFIG_ARCH_NETX is not set |
| 140 | # CONFIG_ARCH_H720X is not set | 160 | # CONFIG_ARCH_H720X is not set |
| 141 | # CONFIG_ARCH_IMX is not set | 161 | # CONFIG_ARCH_NOMADIK is not set |
| 142 | # CONFIG_ARCH_IOP13XX is not set | 162 | # CONFIG_ARCH_IOP13XX is not set |
| 143 | # CONFIG_ARCH_IOP32X is not set | 163 | # CONFIG_ARCH_IOP32X is not set |
| 144 | # CONFIG_ARCH_IOP33X is not set | 164 | # CONFIG_ARCH_IOP33X is not set |
| @@ -146,39 +166,64 @@ CONFIG_CLASSIC_RCU=y | |||
| 146 | # CONFIG_ARCH_IXP2000 is not set | 166 | # CONFIG_ARCH_IXP2000 is not set |
| 147 | # CONFIG_ARCH_IXP4XX is not set | 167 | # CONFIG_ARCH_IXP4XX is not set |
| 148 | # CONFIG_ARCH_L7200 is not set | 168 | # CONFIG_ARCH_L7200 is not set |
| 169 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 170 | # CONFIG_ARCH_LOKI is not set | ||
| 171 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 172 | # CONFIG_ARCH_ORION5X is not set | ||
| 173 | # CONFIG_ARCH_MMP is not set | ||
| 149 | # CONFIG_ARCH_KS8695 is not set | 174 | # CONFIG_ARCH_KS8695 is not set |
| 150 | # CONFIG_ARCH_NS9XXX is not set | 175 | # CONFIG_ARCH_NS9XXX is not set |
| 151 | # CONFIG_ARCH_MXC is not set | 176 | # CONFIG_ARCH_W90X900 is not set |
| 152 | # CONFIG_ARCH_ORION5X is not set | ||
| 153 | # CONFIG_ARCH_PNX4008 is not set | 177 | # CONFIG_ARCH_PNX4008 is not set |
| 154 | CONFIG_ARCH_PXA=y | 178 | CONFIG_ARCH_PXA=y |
| 179 | # CONFIG_ARCH_MSM is not set | ||
| 155 | # CONFIG_ARCH_RPC is not set | 180 | # CONFIG_ARCH_RPC is not set |
| 156 | # CONFIG_ARCH_SA1100 is not set | 181 | # CONFIG_ARCH_SA1100 is not set |
| 157 | # CONFIG_ARCH_S3C2410 is not set | 182 | # CONFIG_ARCH_S3C2410 is not set |
| 183 | # CONFIG_ARCH_S3C64XX is not set | ||
| 184 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 158 | # CONFIG_ARCH_SHARK is not set | 185 | # CONFIG_ARCH_SHARK is not set |
| 159 | # CONFIG_ARCH_LH7A40X is not set | 186 | # CONFIG_ARCH_LH7A40X is not set |
| 187 | # CONFIG_ARCH_U300 is not set | ||
| 160 | # CONFIG_ARCH_DAVINCI is not set | 188 | # CONFIG_ARCH_DAVINCI is not set |
| 161 | # CONFIG_ARCH_OMAP is not set | 189 | # CONFIG_ARCH_OMAP is not set |
| 162 | # CONFIG_ARCH_MSM7X00A is not set | 190 | # CONFIG_ARCH_BCMRING is not set |
| 163 | 191 | ||
| 164 | # | 192 | # |
| 165 | # Intel PXA2xx/PXA3xx Implementations | 193 | # Intel PXA2xx/PXA3xx Implementations |
| 166 | # | 194 | # |
| 167 | # CONFIG_ARCH_GUMSTIX is not set | 195 | # CONFIG_ARCH_GUMSTIX is not set |
| 196 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 197 | # CONFIG_MACH_STARGATE2 is not set | ||
| 168 | # CONFIG_ARCH_LUBBOCK is not set | 198 | # CONFIG_ARCH_LUBBOCK is not set |
| 169 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 199 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 170 | # CONFIG_MACH_MAINSTONE is not set | 200 | # CONFIG_MACH_MAINSTONE is not set |
| 201 | # CONFIG_MACH_MP900C is not set | ||
| 202 | # CONFIG_MACH_BALLOON3 is not set | ||
| 171 | # CONFIG_ARCH_PXA_IDP is not set | 203 | # CONFIG_ARCH_PXA_IDP is not set |
| 172 | # CONFIG_PXA_SHARPSL is not set | 204 | # CONFIG_PXA_SHARPSL is not set |
| 205 | # CONFIG_ARCH_VIPER is not set | ||
| 173 | # CONFIG_ARCH_PXA_ESERIES is not set | 206 | # CONFIG_ARCH_PXA_ESERIES is not set |
| 174 | # CONFIG_MACH_TRIZEPS4 is not set | 207 | # CONFIG_TRIZEPS_PXA is not set |
| 208 | # CONFIG_MACH_H5000 is not set | ||
| 175 | # CONFIG_MACH_EM_X270 is not set | 209 | # CONFIG_MACH_EM_X270 is not set |
| 210 | # CONFIG_MACH_EXEDA is not set | ||
| 176 | # CONFIG_MACH_COLIBRI is not set | 211 | # CONFIG_MACH_COLIBRI is not set |
| 212 | # CONFIG_MACH_COLIBRI300 is not set | ||
| 213 | # CONFIG_MACH_COLIBRI320 is not set | ||
| 177 | # CONFIG_MACH_ZYLONITE is not set | 214 | # CONFIG_MACH_ZYLONITE is not set |
| 178 | # CONFIG_MACH_LITTLETON is not set | 215 | # CONFIG_MACH_LITTLETON is not set |
| 216 | # CONFIG_MACH_TAVOREVB is not set | ||
| 217 | # CONFIG_MACH_SAAR is not set | ||
| 179 | # CONFIG_MACH_ARMCORE is not set | 218 | # CONFIG_MACH_ARMCORE is not set |
| 219 | # CONFIG_MACH_CM_X300 is not set | ||
| 220 | # CONFIG_MACH_H4700 is not set | ||
| 180 | # CONFIG_MACH_MAGICIAN is not set | 221 | # CONFIG_MACH_MAGICIAN is not set |
| 222 | # CONFIG_MACH_HIMALAYA is not set | ||
| 223 | # CONFIG_MACH_MIOA701 is not set | ||
| 181 | # CONFIG_MACH_PCM027 is not set | 224 | # CONFIG_MACH_PCM027 is not set |
| 225 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 226 | # CONFIG_MACH_CSB726 is not set | ||
| 182 | CONFIG_PXA_EZX=y | 227 | CONFIG_PXA_EZX=y |
| 183 | CONFIG_MACH_EZX_A780=y | 228 | CONFIG_MACH_EZX_A780=y |
| 184 | CONFIG_MACH_EZX_E680=y | 229 | CONFIG_MACH_EZX_E680=y |
| @@ -186,17 +231,11 @@ CONFIG_MACH_EZX_A1200=y | |||
| 186 | CONFIG_MACH_EZX_A910=y | 231 | CONFIG_MACH_EZX_A910=y |
| 187 | CONFIG_MACH_EZX_E6=y | 232 | CONFIG_MACH_EZX_E6=y |
| 188 | CONFIG_MACH_EZX_E2=y | 233 | CONFIG_MACH_EZX_E2=y |
| 234 | # CONFIG_MACH_XCEP is not set | ||
| 189 | CONFIG_PXA27x=y | 235 | CONFIG_PXA27x=y |
| 190 | CONFIG_PXA_SSP=y | 236 | CONFIG_PXA_SSP=y |
| 191 | CONFIG_PXA_PWM=y | 237 | CONFIG_PXA_HAVE_BOARD_IRQS=y |
| 192 | 238 | CONFIG_PLAT_PXA=y | |
| 193 | # | ||
| 194 | # Boot options | ||
| 195 | # | ||
| 196 | |||
| 197 | # | ||
| 198 | # Power management | ||
| 199 | # | ||
| 200 | 239 | ||
| 201 | # | 240 | # |
| 202 | # Processor Type | 241 | # Processor Type |
| @@ -205,7 +244,7 @@ CONFIG_CPU_32=y | |||
| 205 | CONFIG_CPU_XSCALE=y | 244 | CONFIG_CPU_XSCALE=y |
| 206 | CONFIG_CPU_32v5=y | 245 | CONFIG_CPU_32v5=y |
| 207 | CONFIG_CPU_ABRT_EV5T=y | 246 | CONFIG_CPU_ABRT_EV5T=y |
| 208 | CONFIG_CPU_PABRT_NOIFAR=y | 247 | CONFIG_CPU_PABRT_LEGACY=y |
| 209 | CONFIG_CPU_CACHE_VIVT=y | 248 | CONFIG_CPU_CACHE_VIVT=y |
| 210 | CONFIG_CPU_TLB_V4WBI=y | 249 | CONFIG_CPU_TLB_V4WBI=y |
| 211 | CONFIG_CPU_CP15=y | 250 | CONFIG_CPU_CP15=y |
| @@ -216,9 +255,10 @@ CONFIG_CPU_CP15_MMU=y | |||
| 216 | # | 255 | # |
| 217 | CONFIG_ARM_THUMB=y | 256 | CONFIG_ARM_THUMB=y |
| 218 | # CONFIG_CPU_DCACHE_DISABLE is not set | 257 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 219 | # CONFIG_OUTER_CACHE is not set | 258 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
| 220 | CONFIG_IWMMXT=y | 259 | CONFIG_IWMMXT=y |
| 221 | CONFIG_XSCALE_PMU=y | 260 | CONFIG_XSCALE_PMU=y |
| 261 | CONFIG_COMMON_CLKDEV=y | ||
| 222 | 262 | ||
| 223 | # | 263 | # |
| 224 | # Bus support | 264 | # Bus support |
| @@ -231,44 +271,71 @@ CONFIG_XSCALE_PMU=y | |||
| 231 | # Kernel Features | 271 | # Kernel Features |
| 232 | # | 272 | # |
| 233 | CONFIG_TICK_ONESHOT=y | 273 | CONFIG_TICK_ONESHOT=y |
| 234 | # CONFIG_NO_HZ is not set | 274 | CONFIG_NO_HZ=y |
| 235 | CONFIG_HIGH_RES_TIMERS=y | 275 | CONFIG_HIGH_RES_TIMERS=y |
| 236 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 276 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 277 | CONFIG_VMSPLIT_3G=y | ||
| 278 | # CONFIG_VMSPLIT_2G is not set | ||
| 279 | # CONFIG_VMSPLIT_1G is not set | ||
| 280 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 281 | # CONFIG_PREEMPT_NONE is not set | ||
| 282 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 237 | CONFIG_PREEMPT=y | 283 | CONFIG_PREEMPT=y |
| 238 | CONFIG_HZ=100 | 284 | CONFIG_HZ=100 |
| 239 | CONFIG_AEABI=y | 285 | CONFIG_AEABI=y |
| 240 | CONFIG_OABI_COMPAT=y | 286 | CONFIG_OABI_COMPAT=y |
| 241 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 287 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 288 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 289 | # CONFIG_HIGHMEM is not set | ||
| 242 | CONFIG_SELECT_MEMORY_MODEL=y | 290 | CONFIG_SELECT_MEMORY_MODEL=y |
| 243 | CONFIG_FLATMEM_MANUAL=y | 291 | CONFIG_FLATMEM_MANUAL=y |
| 244 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 292 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 245 | # CONFIG_SPARSEMEM_MANUAL is not set | 293 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 246 | CONFIG_FLATMEM=y | 294 | CONFIG_FLATMEM=y |
| 247 | CONFIG_FLAT_NODE_MEM_MAP=y | 295 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 248 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 249 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 250 | CONFIG_PAGEFLAGS_EXTENDED=y | 296 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 251 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 297 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 252 | # CONFIG_RESOURCES_64BIT is not set | 298 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 253 | CONFIG_ZONE_DMA_FLAG=1 | 299 | CONFIG_ZONE_DMA_FLAG=0 |
| 254 | CONFIG_BOUNCE=y | ||
| 255 | CONFIG_VIRT_TO_BUS=y | 300 | CONFIG_VIRT_TO_BUS=y |
| 301 | CONFIG_HAVE_MLOCK=y | ||
| 302 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 303 | # CONFIG_KSM is not set | ||
| 304 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 256 | CONFIG_ALIGNMENT_TRAP=y | 305 | CONFIG_ALIGNMENT_TRAP=y |
| 306 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 257 | 307 | ||
| 258 | # | 308 | # |
| 259 | # Boot options | 309 | # Boot options |
| 260 | # | 310 | # |
| 261 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 311 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
| 262 | CONFIG_ZBOOT_ROM_BSS=0x0 | 312 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 263 | CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=1 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" | 313 | CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" |
| 264 | # CONFIG_XIP_KERNEL is not set | 314 | # CONFIG_XIP_KERNEL is not set |
| 265 | CONFIG_KEXEC=y | 315 | CONFIG_KEXEC=y |
| 266 | CONFIG_ATAGS_PROC=y | 316 | CONFIG_ATAGS_PROC=y |
| 267 | 317 | ||
| 268 | # | 318 | # |
| 269 | # CPU Frequency scaling | 319 | # CPU Power Management |
| 270 | # | 320 | # |
| 271 | # CONFIG_CPU_FREQ is not set | 321 | CONFIG_CPU_FREQ=y |
| 322 | CONFIG_CPU_FREQ_TABLE=y | ||
| 323 | CONFIG_CPU_FREQ_DEBUG=y | ||
| 324 | CONFIG_CPU_FREQ_STAT=y | ||
| 325 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
| 326 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 327 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 328 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 329 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 330 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 331 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 332 | CONFIG_CPU_FREQ_GOV_POWERSAVE=m | ||
| 333 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | ||
| 334 | CONFIG_CPU_FREQ_GOV_ONDEMAND=m | ||
| 335 | CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m | ||
| 336 | CONFIG_CPU_IDLE=y | ||
| 337 | CONFIG_CPU_IDLE_GOV_LADDER=y | ||
| 338 | CONFIG_CPU_IDLE_GOV_MENU=y | ||
| 272 | 339 | ||
| 273 | # | 340 | # |
| 274 | # Floating point emulation | 341 | # Floating point emulation |
| @@ -285,6 +352,8 @@ CONFIG_FPE_NWFPE=y | |||
| 285 | # Userspace binary formats | 352 | # Userspace binary formats |
| 286 | # | 353 | # |
| 287 | CONFIG_BINFMT_ELF=y | 354 | CONFIG_BINFMT_ELF=y |
| 355 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 356 | CONFIG_HAVE_AOUT=y | ||
| 288 | CONFIG_BINFMT_AOUT=m | 357 | CONFIG_BINFMT_AOUT=m |
| 289 | CONFIG_BINFMT_MISC=m | 358 | CONFIG_BINFMT_MISC=m |
| 290 | 359 | ||
| @@ -297,11 +366,8 @@ CONFIG_PM_SLEEP=y | |||
| 297 | CONFIG_SUSPEND=y | 366 | CONFIG_SUSPEND=y |
| 298 | CONFIG_SUSPEND_FREEZER=y | 367 | CONFIG_SUSPEND_FREEZER=y |
| 299 | CONFIG_APM_EMULATION=y | 368 | CONFIG_APM_EMULATION=y |
| 369 | CONFIG_PM_RUNTIME=y | ||
| 300 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 370 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 301 | |||
| 302 | # | ||
| 303 | # Networking | ||
| 304 | # | ||
| 305 | CONFIG_NET=y | 371 | CONFIG_NET=y |
| 306 | 372 | ||
| 307 | # | 373 | # |
| @@ -315,6 +381,7 @@ CONFIG_XFRM=y | |||
| 315 | # CONFIG_XFRM_SUB_POLICY is not set | 381 | # CONFIG_XFRM_SUB_POLICY is not set |
| 316 | # CONFIG_XFRM_MIGRATE is not set | 382 | # CONFIG_XFRM_MIGRATE is not set |
| 317 | # CONFIG_XFRM_STATISTICS is not set | 383 | # CONFIG_XFRM_STATISTICS is not set |
| 384 | CONFIG_XFRM_IPCOMP=m | ||
| 318 | # CONFIG_NET_KEY is not set | 385 | # CONFIG_NET_KEY is not set |
| 319 | CONFIG_INET=y | 386 | CONFIG_INET=y |
| 320 | # CONFIG_IP_MULTICAST is not set | 387 | # CONFIG_IP_MULTICAST is not set |
| @@ -342,7 +409,6 @@ CONFIG_INET_TUNNEL=m | |||
| 342 | CONFIG_TCP_CONG_CUBIC=y | 409 | CONFIG_TCP_CONG_CUBIC=y |
| 343 | CONFIG_DEFAULT_TCP_CONG="cubic" | 410 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 344 | # CONFIG_TCP_MD5SIG is not set | 411 | # CONFIG_TCP_MD5SIG is not set |
| 345 | # CONFIG_IP_VS is not set | ||
| 346 | CONFIG_IPV6=m | 412 | CONFIG_IPV6=m |
| 347 | # CONFIG_IPV6_PRIVACY is not set | 413 | # CONFIG_IPV6_PRIVACY is not set |
| 348 | # CONFIG_IPV6_ROUTER_PREF is not set | 414 | # CONFIG_IPV6_ROUTER_PREF is not set |
| @@ -393,18 +459,22 @@ CONFIG_NF_CONNTRACK_SANE=m | |||
| 393 | CONFIG_NF_CONNTRACK_SIP=m | 459 | CONFIG_NF_CONNTRACK_SIP=m |
| 394 | CONFIG_NF_CONNTRACK_TFTP=m | 460 | CONFIG_NF_CONNTRACK_TFTP=m |
| 395 | CONFIG_NF_CT_NETLINK=m | 461 | CONFIG_NF_CT_NETLINK=m |
| 462 | # CONFIG_NETFILTER_TPROXY is not set | ||
| 396 | CONFIG_NETFILTER_XTABLES=m | 463 | CONFIG_NETFILTER_XTABLES=m |
| 397 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 464 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 398 | # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set | 465 | # CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set |
| 399 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set | 466 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set |
| 467 | CONFIG_NETFILTER_XT_TARGET_HL=m | ||
| 468 | CONFIG_NETFILTER_XT_TARGET_LED=m | ||
| 400 | CONFIG_NETFILTER_XT_TARGET_MARK=m | 469 | CONFIG_NETFILTER_XT_TARGET_MARK=m |
| 401 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | ||
| 402 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m | 470 | CONFIG_NETFILTER_XT_TARGET_NFLOG=m |
| 471 | CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m | ||
| 403 | # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set | 472 | # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set |
| 404 | # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | 473 | # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set |
| 405 | # CONFIG_NETFILTER_XT_TARGET_TRACE is not set | 474 | # CONFIG_NETFILTER_XT_TARGET_TRACE is not set |
| 406 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m | 475 | CONFIG_NETFILTER_XT_TARGET_TCPMSS=m |
| 407 | # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set | 476 | # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set |
| 477 | # CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set | ||
| 408 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m | 478 | CONFIG_NETFILTER_XT_MATCH_COMMENT=m |
| 409 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m | 479 | CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m |
| 410 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m | 480 | CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m |
| @@ -413,20 +483,23 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m | |||
| 413 | CONFIG_NETFILTER_XT_MATCH_DCCP=m | 483 | CONFIG_NETFILTER_XT_MATCH_DCCP=m |
| 414 | CONFIG_NETFILTER_XT_MATCH_DSCP=m | 484 | CONFIG_NETFILTER_XT_MATCH_DSCP=m |
| 415 | CONFIG_NETFILTER_XT_MATCH_ESP=m | 485 | CONFIG_NETFILTER_XT_MATCH_ESP=m |
| 486 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | ||
| 416 | CONFIG_NETFILTER_XT_MATCH_HELPER=m | 487 | CONFIG_NETFILTER_XT_MATCH_HELPER=m |
| 488 | CONFIG_NETFILTER_XT_MATCH_HL=m | ||
| 417 | # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | 489 | # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set |
| 418 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m | 490 | CONFIG_NETFILTER_XT_MATCH_LENGTH=m |
| 419 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m | 491 | CONFIG_NETFILTER_XT_MATCH_LIMIT=m |
| 420 | CONFIG_NETFILTER_XT_MATCH_MAC=m | 492 | CONFIG_NETFILTER_XT_MATCH_MAC=m |
| 421 | CONFIG_NETFILTER_XT_MATCH_MARK=m | 493 | CONFIG_NETFILTER_XT_MATCH_MARK=m |
| 494 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | ||
| 422 | # CONFIG_NETFILTER_XT_MATCH_OWNER is not set | 495 | # CONFIG_NETFILTER_XT_MATCH_OWNER is not set |
| 423 | CONFIG_NETFILTER_XT_MATCH_POLICY=m | 496 | CONFIG_NETFILTER_XT_MATCH_POLICY=m |
| 424 | CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m | ||
| 425 | # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set | 497 | # CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set |
| 426 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m | 498 | CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m |
| 427 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m | 499 | CONFIG_NETFILTER_XT_MATCH_QUOTA=m |
| 428 | # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | 500 | # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set |
| 429 | CONFIG_NETFILTER_XT_MATCH_REALM=m | 501 | CONFIG_NETFILTER_XT_MATCH_REALM=m |
| 502 | # CONFIG_NETFILTER_XT_MATCH_RECENT is not set | ||
| 430 | CONFIG_NETFILTER_XT_MATCH_SCTP=m | 503 | CONFIG_NETFILTER_XT_MATCH_SCTP=m |
| 431 | CONFIG_NETFILTER_XT_MATCH_STATE=m | 504 | CONFIG_NETFILTER_XT_MATCH_STATE=m |
| 432 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m | 505 | CONFIG_NETFILTER_XT_MATCH_STATISTIC=m |
| @@ -434,20 +507,21 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m | |||
| 434 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 507 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 435 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 508 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 436 | CONFIG_NETFILTER_XT_MATCH_U32=m | 509 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 437 | CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m | 510 | # CONFIG_NETFILTER_XT_MATCH_OSF is not set |
| 511 | # CONFIG_IP_VS is not set | ||
| 438 | 512 | ||
| 439 | # | 513 | # |
| 440 | # IP: Netfilter Configuration | 514 | # IP: Netfilter Configuration |
| 441 | # | 515 | # |
| 516 | CONFIG_NF_DEFRAG_IPV4=m | ||
| 442 | CONFIG_NF_CONNTRACK_IPV4=m | 517 | CONFIG_NF_CONNTRACK_IPV4=m |
| 443 | CONFIG_NF_CONNTRACK_PROC_COMPAT=y | 518 | CONFIG_NF_CONNTRACK_PROC_COMPAT=y |
| 444 | CONFIG_IP_NF_QUEUE=m | 519 | CONFIG_IP_NF_QUEUE=m |
| 445 | CONFIG_IP_NF_IPTABLES=m | 520 | CONFIG_IP_NF_IPTABLES=m |
| 446 | CONFIG_IP_NF_MATCH_RECENT=m | 521 | CONFIG_IP_NF_MATCH_ADDRTYPE=m |
| 447 | CONFIG_IP_NF_MATCH_ECN=m | ||
| 448 | CONFIG_IP_NF_MATCH_AH=m | 522 | CONFIG_IP_NF_MATCH_AH=m |
| 523 | CONFIG_IP_NF_MATCH_ECN=m | ||
| 449 | CONFIG_IP_NF_MATCH_TTL=m | 524 | CONFIG_IP_NF_MATCH_TTL=m |
| 450 | CONFIG_IP_NF_MATCH_ADDRTYPE=m | ||
| 451 | CONFIG_IP_NF_FILTER=m | 525 | CONFIG_IP_NF_FILTER=m |
| 452 | CONFIG_IP_NF_TARGET_REJECT=m | 526 | CONFIG_IP_NF_TARGET_REJECT=m |
| 453 | CONFIG_IP_NF_TARGET_LOG=m | 527 | CONFIG_IP_NF_TARGET_LOG=m |
| @@ -455,8 +529,8 @@ CONFIG_IP_NF_TARGET_ULOG=m | |||
| 455 | CONFIG_NF_NAT=m | 529 | CONFIG_NF_NAT=m |
| 456 | CONFIG_NF_NAT_NEEDED=y | 530 | CONFIG_NF_NAT_NEEDED=y |
| 457 | CONFIG_IP_NF_TARGET_MASQUERADE=m | 531 | CONFIG_IP_NF_TARGET_MASQUERADE=m |
| 458 | CONFIG_IP_NF_TARGET_REDIRECT=m | ||
| 459 | CONFIG_IP_NF_TARGET_NETMAP=m | 532 | CONFIG_IP_NF_TARGET_NETMAP=m |
| 533 | CONFIG_IP_NF_TARGET_REDIRECT=m | ||
| 460 | CONFIG_NF_NAT_SNMP_BASIC=m | 534 | CONFIG_NF_NAT_SNMP_BASIC=m |
| 461 | CONFIG_NF_NAT_PROTO_GRE=m | 535 | CONFIG_NF_NAT_PROTO_GRE=m |
| 462 | CONFIG_NF_NAT_PROTO_UDPLITE=m | 536 | CONFIG_NF_NAT_PROTO_UDPLITE=m |
| @@ -469,9 +543,9 @@ CONFIG_NF_NAT_PPTP=m | |||
| 469 | CONFIG_NF_NAT_H323=m | 543 | CONFIG_NF_NAT_H323=m |
| 470 | CONFIG_NF_NAT_SIP=m | 544 | CONFIG_NF_NAT_SIP=m |
| 471 | CONFIG_IP_NF_MANGLE=m | 545 | CONFIG_IP_NF_MANGLE=m |
| 546 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | ||
| 472 | CONFIG_IP_NF_TARGET_ECN=m | 547 | CONFIG_IP_NF_TARGET_ECN=m |
| 473 | CONFIG_IP_NF_TARGET_TTL=m | 548 | CONFIG_IP_NF_TARGET_TTL=m |
| 474 | CONFIG_IP_NF_TARGET_CLUSTERIP=m | ||
| 475 | CONFIG_IP_NF_RAW=m | 549 | CONFIG_IP_NF_RAW=m |
| 476 | CONFIG_IP_NF_ARPTABLES=m | 550 | CONFIG_IP_NF_ARPTABLES=m |
| 477 | CONFIG_IP_NF_ARPFILTER=m | 551 | CONFIG_IP_NF_ARPFILTER=m |
| @@ -483,30 +557,29 @@ CONFIG_IP_NF_ARP_MANGLE=m | |||
| 483 | CONFIG_NF_CONNTRACK_IPV6=m | 557 | CONFIG_NF_CONNTRACK_IPV6=m |
| 484 | CONFIG_IP6_NF_QUEUE=m | 558 | CONFIG_IP6_NF_QUEUE=m |
| 485 | CONFIG_IP6_NF_IPTABLES=m | 559 | CONFIG_IP6_NF_IPTABLES=m |
| 486 | CONFIG_IP6_NF_MATCH_RT=m | 560 | CONFIG_IP6_NF_MATCH_AH=m |
| 487 | CONFIG_IP6_NF_MATCH_OPTS=m | 561 | CONFIG_IP6_NF_MATCH_EUI64=m |
| 488 | CONFIG_IP6_NF_MATCH_FRAG=m | 562 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 563 | CONFIG_IP6_NF_MATCH_OPTS=m | ||
| 489 | CONFIG_IP6_NF_MATCH_HL=m | 564 | CONFIG_IP6_NF_MATCH_HL=m |
| 490 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 565 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 491 | CONFIG_IP6_NF_MATCH_AH=m | ||
| 492 | CONFIG_IP6_NF_MATCH_MH=m | 566 | CONFIG_IP6_NF_MATCH_MH=m |
| 493 | CONFIG_IP6_NF_MATCH_EUI64=m | 567 | CONFIG_IP6_NF_MATCH_RT=m |
| 494 | CONFIG_IP6_NF_FILTER=m | 568 | CONFIG_IP6_NF_TARGET_HL=m |
| 495 | CONFIG_IP6_NF_TARGET_LOG=m | 569 | CONFIG_IP6_NF_TARGET_LOG=m |
| 570 | CONFIG_IP6_NF_FILTER=m | ||
| 496 | CONFIG_IP6_NF_TARGET_REJECT=m | 571 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 497 | CONFIG_IP6_NF_MANGLE=m | 572 | CONFIG_IP6_NF_MANGLE=m |
| 498 | CONFIG_IP6_NF_TARGET_HL=m | ||
| 499 | CONFIG_IP6_NF_RAW=m | 573 | CONFIG_IP6_NF_RAW=m |
| 500 | |||
| 501 | # | ||
| 502 | # Bridge: Netfilter Configuration | ||
| 503 | # | ||
| 504 | # CONFIG_BRIDGE_NF_EBTABLES is not set | 574 | # CONFIG_BRIDGE_NF_EBTABLES is not set |
| 505 | # CONFIG_IP_DCCP is not set | 575 | # CONFIG_IP_DCCP is not set |
| 506 | # CONFIG_IP_SCTP is not set | 576 | # CONFIG_IP_SCTP is not set |
| 577 | # CONFIG_RDS is not set | ||
| 507 | # CONFIG_TIPC is not set | 578 | # CONFIG_TIPC is not set |
| 508 | # CONFIG_ATM is not set | 579 | # CONFIG_ATM is not set |
| 580 | CONFIG_STP=m | ||
| 509 | CONFIG_BRIDGE=m | 581 | CONFIG_BRIDGE=m |
| 582 | # CONFIG_NET_DSA is not set | ||
| 510 | # CONFIG_VLAN_8021Q is not set | 583 | # CONFIG_VLAN_8021Q is not set |
| 511 | # CONFIG_DECNET is not set | 584 | # CONFIG_DECNET is not set |
| 512 | CONFIG_LLC=m | 585 | CONFIG_LLC=m |
| @@ -517,9 +590,11 @@ CONFIG_LLC=m | |||
| 517 | # CONFIG_LAPB is not set | 590 | # CONFIG_LAPB is not set |
| 518 | # CONFIG_ECONET is not set | 591 | # CONFIG_ECONET is not set |
| 519 | # CONFIG_WAN_ROUTER is not set | 592 | # CONFIG_WAN_ROUTER is not set |
| 593 | # CONFIG_PHONET is not set | ||
| 594 | # CONFIG_IEEE802154 is not set | ||
| 520 | # CONFIG_NET_SCHED is not set | 595 | # CONFIG_NET_SCHED is not set |
| 521 | CONFIG_NET_CLS_ROUTE=y | 596 | CONFIG_NET_CLS_ROUTE=y |
| 522 | CONFIG_NET_SCH_FIFO=y | 597 | # CONFIG_DCB is not set |
| 523 | 598 | ||
| 524 | # | 599 | # |
| 525 | # Network testing | 600 | # Network testing |
| @@ -529,64 +604,34 @@ CONFIG_NET_SCH_FIFO=y | |||
| 529 | # CONFIG_CAN is not set | 604 | # CONFIG_CAN is not set |
| 530 | # CONFIG_IRDA is not set | 605 | # CONFIG_IRDA is not set |
| 531 | CONFIG_BT=y | 606 | CONFIG_BT=y |
| 532 | CONFIG_BT_L2CAP=m | 607 | CONFIG_BT_L2CAP=y |
| 533 | CONFIG_BT_SCO=y | 608 | CONFIG_BT_SCO=y |
| 534 | CONFIG_BT_RFCOMM=m | 609 | CONFIG_BT_RFCOMM=y |
| 535 | CONFIG_BT_RFCOMM_TTY=y | 610 | CONFIG_BT_RFCOMM_TTY=y |
| 536 | CONFIG_BT_BNEP=m | 611 | CONFIG_BT_BNEP=y |
| 537 | CONFIG_BT_BNEP_MC_FILTER=y | 612 | CONFIG_BT_BNEP_MC_FILTER=y |
| 538 | CONFIG_BT_BNEP_PROTO_FILTER=y | 613 | CONFIG_BT_BNEP_PROTO_FILTER=y |
| 539 | CONFIG_BT_HIDP=m | 614 | CONFIG_BT_HIDP=y |
| 540 | 615 | ||
| 541 | # | 616 | # |
| 542 | # Bluetooth device drivers | 617 | # Bluetooth device drivers |
| 543 | # | 618 | # |
| 544 | # CONFIG_BT_HCIUSB is not set | 619 | CONFIG_BT_HCIBTUSB=m |
| 545 | # CONFIG_BT_HCIBTUSB is not set | 620 | CONFIG_BT_HCIBTSDIO=m |
| 546 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 547 | CONFIG_BT_HCIUART=y | 621 | CONFIG_BT_HCIUART=y |
| 548 | CONFIG_BT_HCIUART_H4=y | 622 | CONFIG_BT_HCIUART_H4=y |
| 549 | # CONFIG_BT_HCIUART_BCSP is not set | 623 | # CONFIG_BT_HCIUART_BCSP is not set |
| 550 | # CONFIG_BT_HCIUART_LL is not set | 624 | # CONFIG_BT_HCIUART_LL is not set |
| 551 | # CONFIG_BT_HCIBCM203X is not set | 625 | CONFIG_BT_HCIBCM203X=m |
| 552 | # CONFIG_BT_HCIBPA10X is not set | 626 | CONFIG_BT_HCIBPA10X=m |
| 553 | # CONFIG_BT_HCIBFUSB is not set | 627 | CONFIG_BT_HCIBFUSB=m |
| 554 | # CONFIG_BT_HCIVHCI is not set | 628 | CONFIG_BT_HCIVHCI=m |
| 629 | CONFIG_BT_MRVL=m | ||
| 630 | CONFIG_BT_MRVL_SDIO=m | ||
| 555 | # CONFIG_AF_RXRPC is not set | 631 | # CONFIG_AF_RXRPC is not set |
| 556 | CONFIG_FIB_RULES=y | 632 | CONFIG_FIB_RULES=y |
| 557 | 633 | # CONFIG_WIRELESS is not set | |
| 558 | # | 634 | # CONFIG_WIMAX is not set |
| 559 | # Wireless | ||
| 560 | # | ||
| 561 | CONFIG_CFG80211=m | ||
| 562 | CONFIG_NL80211=y | ||
| 563 | CONFIG_WIRELESS_EXT=y | ||
| 564 | CONFIG_MAC80211=m | ||
| 565 | |||
| 566 | # | ||
| 567 | # Rate control algorithm selection | ||
| 568 | # | ||
| 569 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 570 | # CONFIG_MAC80211_RC_DEFAULT_NONE is not set | ||
| 571 | |||
| 572 | # | ||
| 573 | # Selecting 'y' for an algorithm will | ||
| 574 | # | ||
| 575 | |||
| 576 | # | ||
| 577 | # build the algorithm into mac80211. | ||
| 578 | # | ||
| 579 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
| 580 | CONFIG_MAC80211_RC_PID=y | ||
| 581 | # CONFIG_MAC80211_MESH is not set | ||
| 582 | CONFIG_MAC80211_LEDS=y | ||
| 583 | # CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set | ||
| 584 | # CONFIG_MAC80211_DEBUG is not set | ||
| 585 | CONFIG_IEEE80211=m | ||
| 586 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 587 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
| 588 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
| 589 | CONFIG_IEEE80211_CRYPT_TKIP=m | ||
| 590 | # CONFIG_RFKILL is not set | 635 | # CONFIG_RFKILL is not set |
| 591 | # CONFIG_NET_9P is not set | 636 | # CONFIG_NET_9P is not set |
| 592 | 637 | ||
| @@ -598,13 +643,19 @@ CONFIG_IEEE80211_CRYPT_TKIP=m | |||
| 598 | # Generic Driver Options | 643 | # Generic Driver Options |
| 599 | # | 644 | # |
| 600 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 645 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 646 | # CONFIG_DEVTMPFS is not set | ||
| 601 | CONFIG_STANDALONE=y | 647 | CONFIG_STANDALONE=y |
| 602 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 648 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 603 | CONFIG_FW_LOADER=m | 649 | CONFIG_FW_LOADER=m |
| 650 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 651 | CONFIG_EXTRA_FIRMWARE="" | ||
| 652 | # CONFIG_DEBUG_DRIVER is not set | ||
| 653 | # CONFIG_DEBUG_DEVRES is not set | ||
| 604 | # CONFIG_SYS_HYPERVISOR is not set | 654 | # CONFIG_SYS_HYPERVISOR is not set |
| 605 | CONFIG_CONNECTOR=m | 655 | CONFIG_CONNECTOR=m |
| 606 | CONFIG_MTD=y | 656 | CONFIG_MTD=y |
| 607 | # CONFIG_MTD_DEBUG is not set | 657 | # CONFIG_MTD_DEBUG is not set |
| 658 | # CONFIG_MTD_TESTS is not set | ||
| 608 | # CONFIG_MTD_CONCAT is not set | 659 | # CONFIG_MTD_CONCAT is not set |
| 609 | CONFIG_MTD_PARTITIONS=y | 660 | CONFIG_MTD_PARTITIONS=y |
| 610 | # CONFIG_MTD_REDBOOT_PARTS is not set | 661 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| @@ -616,9 +667,9 @@ CONFIG_MTD_PARTITIONS=y | |||
| 616 | # User Modules And Translation Layers | 667 | # User Modules And Translation Layers |
| 617 | # | 668 | # |
| 618 | CONFIG_MTD_CHAR=y | 669 | CONFIG_MTD_CHAR=y |
| 619 | # CONFIG_MTD_BLKDEVS is not set | 670 | CONFIG_HAVE_MTD_OTP=y |
| 620 | # CONFIG_MTD_BLOCK is not set | 671 | CONFIG_MTD_BLKDEVS=y |
| 621 | # CONFIG_MTD_BLOCK_RO is not set | 672 | CONFIG_MTD_BLOCK=y |
| 622 | # CONFIG_FTL is not set | 673 | # CONFIG_FTL is not set |
| 623 | # CONFIG_NFTL is not set | 674 | # CONFIG_NFTL is not set |
| 624 | # CONFIG_INFTL is not set | 675 | # CONFIG_INFTL is not set |
| @@ -647,7 +698,7 @@ CONFIG_MTD_CFI_I1=y | |||
| 647 | # CONFIG_MTD_CFI_I2 is not set | 698 | # CONFIG_MTD_CFI_I2 is not set |
| 648 | # CONFIG_MTD_CFI_I4 is not set | 699 | # CONFIG_MTD_CFI_I4 is not set |
| 649 | # CONFIG_MTD_CFI_I8 is not set | 700 | # CONFIG_MTD_CFI_I8 is not set |
| 650 | # CONFIG_MTD_OTP is not set | 701 | CONFIG_MTD_OTP=y |
| 651 | CONFIG_MTD_CFI_INTELEXT=y | 702 | CONFIG_MTD_CFI_INTELEXT=y |
| 652 | # CONFIG_MTD_CFI_AMDSTD is not set | 703 | # CONFIG_MTD_CFI_AMDSTD is not set |
| 653 | # CONFIG_MTD_CFI_STAA is not set | 704 | # CONFIG_MTD_CFI_STAA is not set |
| @@ -655,19 +706,15 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 655 | # CONFIG_MTD_RAM is not set | 706 | # CONFIG_MTD_RAM is not set |
| 656 | # CONFIG_MTD_ROM is not set | 707 | # CONFIG_MTD_ROM is not set |
| 657 | # CONFIG_MTD_ABSENT is not set | 708 | # CONFIG_MTD_ABSENT is not set |
| 658 | CONFIG_MTD_XIP=y | 709 | # CONFIG_MTD_XIP is not set |
| 659 | 710 | ||
| 660 | # | 711 | # |
| 661 | # Mapping drivers for chip access | 712 | # Mapping drivers for chip access |
| 662 | # | 713 | # |
| 663 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 714 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 664 | CONFIG_MTD_PHYSMAP=y | 715 | # CONFIG_MTD_PHYSMAP is not set |
| 665 | CONFIG_MTD_PHYSMAP_START=0x0 | 716 | CONFIG_MTD_PXA2XX=y |
| 666 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 667 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 668 | # CONFIG_MTD_PXA2XX is not set | ||
| 669 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 717 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 670 | # CONFIG_MTD_SHARP_SL is not set | ||
| 671 | # CONFIG_MTD_PLATRAM is not set | 718 | # CONFIG_MTD_PLATRAM is not set |
| 672 | 719 | ||
| 673 | # | 720 | # |
| @@ -675,6 +722,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | |||
| 675 | # | 722 | # |
| 676 | # CONFIG_MTD_DATAFLASH is not set | 723 | # CONFIG_MTD_DATAFLASH is not set |
| 677 | # CONFIG_MTD_M25P80 is not set | 724 | # CONFIG_MTD_M25P80 is not set |
| 725 | # CONFIG_MTD_SST25L is not set | ||
| 678 | # CONFIG_MTD_SLRAM is not set | 726 | # CONFIG_MTD_SLRAM is not set |
| 679 | # CONFIG_MTD_PHRAM is not set | 727 | # CONFIG_MTD_PHRAM is not set |
| 680 | # CONFIG_MTD_MTDRAM is not set | 728 | # CONFIG_MTD_MTDRAM is not set |
| @@ -690,6 +738,11 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | |||
| 690 | # CONFIG_MTD_ONENAND is not set | 738 | # CONFIG_MTD_ONENAND is not set |
| 691 | 739 | ||
| 692 | # | 740 | # |
| 741 | # LPDDR flash memory drivers | ||
| 742 | # | ||
| 743 | # CONFIG_MTD_LPDDR is not set | ||
| 744 | |||
| 745 | # | ||
| 693 | # UBI - Unsorted block images | 746 | # UBI - Unsorted block images |
| 694 | # | 747 | # |
| 695 | # CONFIG_MTD_UBI is not set | 748 | # CONFIG_MTD_UBI is not set |
| @@ -700,15 +753,14 @@ CONFIG_BLK_DEV_LOOP=m | |||
| 700 | CONFIG_BLK_DEV_CRYPTOLOOP=m | 753 | CONFIG_BLK_DEV_CRYPTOLOOP=m |
| 701 | CONFIG_BLK_DEV_NBD=m | 754 | CONFIG_BLK_DEV_NBD=m |
| 702 | # CONFIG_BLK_DEV_UB is not set | 755 | # CONFIG_BLK_DEV_UB is not set |
| 703 | CONFIG_BLK_DEV_RAM=m | 756 | CONFIG_BLK_DEV_RAM=y |
| 704 | CONFIG_BLK_DEV_RAM_COUNT=16 | 757 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 705 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 758 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 706 | # CONFIG_BLK_DEV_XIP is not set | 759 | # CONFIG_BLK_DEV_XIP is not set |
| 707 | # CONFIG_CDROM_PKTCDVD is not set | 760 | # CONFIG_CDROM_PKTCDVD is not set |
| 708 | # CONFIG_ATA_OVER_ETH is not set | 761 | # CONFIG_ATA_OVER_ETH is not set |
| 709 | CONFIG_MISC_DEVICES=y | 762 | # CONFIG_MG_DISK is not set |
| 710 | # CONFIG_EEPROM_93CX6 is not set | 763 | # CONFIG_MISC_DEVICES is not set |
| 711 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 712 | CONFIG_HAVE_IDE=y | 764 | CONFIG_HAVE_IDE=y |
| 713 | # CONFIG_IDE is not set | 765 | # CONFIG_IDE is not set |
| 714 | 766 | ||
| @@ -722,7 +774,6 @@ CONFIG_HAVE_IDE=y | |||
| 722 | # CONFIG_ATA is not set | 774 | # CONFIG_ATA is not set |
| 723 | # CONFIG_MD is not set | 775 | # CONFIG_MD is not set |
| 724 | CONFIG_NETDEVICES=y | 776 | CONFIG_NETDEVICES=y |
| 725 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 726 | CONFIG_DUMMY=y | 777 | CONFIG_DUMMY=y |
| 727 | # CONFIG_BONDING is not set | 778 | # CONFIG_BONDING is not set |
| 728 | # CONFIG_MACVLAN is not set | 779 | # CONFIG_MACVLAN is not set |
| @@ -732,13 +783,11 @@ CONFIG_DUMMY=y | |||
| 732 | # CONFIG_NET_ETHERNET is not set | 783 | # CONFIG_NET_ETHERNET is not set |
| 733 | # CONFIG_NETDEV_1000 is not set | 784 | # CONFIG_NETDEV_1000 is not set |
| 734 | # CONFIG_NETDEV_10000 is not set | 785 | # CONFIG_NETDEV_10000 is not set |
| 786 | # CONFIG_WLAN is not set | ||
| 735 | 787 | ||
| 736 | # | 788 | # |
| 737 | # Wireless LAN | 789 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| 738 | # | 790 | # |
| 739 | # CONFIG_WLAN_PRE80211 is not set | ||
| 740 | # CONFIG_WLAN_80211 is not set | ||
| 741 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 742 | 791 | ||
| 743 | # | 792 | # |
| 744 | # USB Network Adapters | 793 | # USB Network Adapters |
| @@ -765,6 +814,7 @@ CONFIG_SLHC=m | |||
| 765 | # CONFIG_NETPOLL is not set | 814 | # CONFIG_NETPOLL is not set |
| 766 | # CONFIG_NET_POLL_CONTROLLER is not set | 815 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 767 | # CONFIG_ISDN is not set | 816 | # CONFIG_ISDN is not set |
| 817 | # CONFIG_PHONE is not set | ||
| 768 | 818 | ||
| 769 | # | 819 | # |
| 770 | # Input device support | 820 | # Input device support |
| @@ -786,29 +836,45 @@ CONFIG_INPUT_EVDEV=y | |||
| 786 | # Input Device Drivers | 836 | # Input Device Drivers |
| 787 | # | 837 | # |
| 788 | CONFIG_INPUT_KEYBOARD=y | 838 | CONFIG_INPUT_KEYBOARD=y |
| 839 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 789 | # CONFIG_KEYBOARD_ATKBD is not set | 840 | # CONFIG_KEYBOARD_ATKBD is not set |
| 790 | # CONFIG_KEYBOARD_SUNKBD is not set | 841 | # CONFIG_QT2160 is not set |
| 791 | # CONFIG_KEYBOARD_LKKBD is not set | 842 | # CONFIG_KEYBOARD_LKKBD is not set |
| 792 | # CONFIG_KEYBOARD_XTKBD is not set | 843 | CONFIG_KEYBOARD_GPIO=y |
| 844 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 845 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 846 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 793 | # CONFIG_KEYBOARD_NEWTON is not set | 847 | # CONFIG_KEYBOARD_NEWTON is not set |
| 794 | # CONFIG_KEYBOARD_STOWAWAY is not set | 848 | # CONFIG_KEYBOARD_OPENCORES is not set |
| 795 | CONFIG_KEYBOARD_PXA27x=y | 849 | CONFIG_KEYBOARD_PXA27x=y |
| 796 | CONFIG_KEYBOARD_GPIO=y | 850 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 851 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 852 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 797 | # CONFIG_INPUT_MOUSE is not set | 853 | # CONFIG_INPUT_MOUSE is not set |
| 798 | # CONFIG_INPUT_JOYSTICK is not set | 854 | # CONFIG_INPUT_JOYSTICK is not set |
| 799 | # CONFIG_INPUT_TABLET is not set | 855 | # CONFIG_INPUT_TABLET is not set |
| 800 | CONFIG_INPUT_TOUCHSCREEN=y | 856 | CONFIG_INPUT_TOUCHSCREEN=y |
| 801 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | 857 | # CONFIG_TOUCHSCREEN_ADS7846 is not set |
| 858 | # CONFIG_TOUCHSCREEN_AD7877 is not set | ||
| 859 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | ||
| 860 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | ||
| 861 | # CONFIG_TOUCHSCREEN_AD7879 is not set | ||
| 862 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 802 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 863 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 803 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 864 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 804 | # CONFIG_TOUCHSCREEN_ELO is not set | 865 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 866 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 867 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 805 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 868 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 869 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 806 | # CONFIG_TOUCHSCREEN_MK712 is not set | 870 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 807 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 871 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 808 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 872 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 809 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 873 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 810 | # CONFIG_TOUCHSCREEN_UCB1400 is not set | ||
| 811 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 874 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 875 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 876 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 877 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 812 | CONFIG_TOUCHSCREEN_PCAP=y | 878 | CONFIG_TOUCHSCREEN_PCAP=y |
| 813 | CONFIG_INPUT_MISC=y | 879 | CONFIG_INPUT_MISC=y |
| 814 | # CONFIG_INPUT_ATI_REMOTE is not set | 880 | # CONFIG_INPUT_ATI_REMOTE is not set |
| @@ -816,7 +882,10 @@ CONFIG_INPUT_MISC=y | |||
| 816 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 882 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 817 | # CONFIG_INPUT_POWERMATE is not set | 883 | # CONFIG_INPUT_POWERMATE is not set |
| 818 | # CONFIG_INPUT_YEALINK is not set | 884 | # CONFIG_INPUT_YEALINK is not set |
| 885 | # CONFIG_INPUT_CM109 is not set | ||
| 819 | CONFIG_INPUT_UINPUT=y | 886 | CONFIG_INPUT_UINPUT=y |
| 887 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
| 888 | CONFIG_INPUT_PCAP=y | ||
| 820 | 889 | ||
| 821 | # | 890 | # |
| 822 | # Hardware I/O ports | 891 | # Hardware I/O ports |
| @@ -828,6 +897,7 @@ CONFIG_INPUT_UINPUT=y | |||
| 828 | # Character devices | 897 | # Character devices |
| 829 | # | 898 | # |
| 830 | CONFIG_VT=y | 899 | CONFIG_VT=y |
| 900 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 831 | CONFIG_VT_CONSOLE=y | 901 | CONFIG_VT_CONSOLE=y |
| 832 | CONFIG_HW_CONSOLE=y | 902 | CONFIG_HW_CONSOLE=y |
| 833 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 903 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| @@ -842,92 +912,130 @@ CONFIG_DEVKMEM=y | |||
| 842 | # | 912 | # |
| 843 | # Non-8250 serial port support | 913 | # Non-8250 serial port support |
| 844 | # | 914 | # |
| 915 | # CONFIG_SERIAL_MAX3100 is not set | ||
| 845 | CONFIG_SERIAL_PXA=y | 916 | CONFIG_SERIAL_PXA=y |
| 846 | CONFIG_SERIAL_PXA_CONSOLE=y | 917 | CONFIG_SERIAL_PXA_CONSOLE=y |
| 847 | CONFIG_SERIAL_CORE=y | 918 | CONFIG_SERIAL_CORE=y |
| 848 | CONFIG_SERIAL_CORE_CONSOLE=y | 919 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 849 | CONFIG_UNIX98_PTYS=y | 920 | CONFIG_UNIX98_PTYS=y |
| 921 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 850 | CONFIG_LEGACY_PTYS=y | 922 | CONFIG_LEGACY_PTYS=y |
| 851 | CONFIG_LEGACY_PTY_COUNT=8 | 923 | CONFIG_LEGACY_PTY_COUNT=8 |
| 852 | # CONFIG_IPMI_HANDLER is not set | 924 | # CONFIG_IPMI_HANDLER is not set |
| 853 | CONFIG_HW_RANDOM=y | 925 | # CONFIG_HW_RANDOM is not set |
| 854 | # CONFIG_NVRAM is not set | ||
| 855 | # CONFIG_R3964 is not set | 926 | # CONFIG_R3964 is not set |
| 856 | # CONFIG_RAW_DRIVER is not set | 927 | # CONFIG_RAW_DRIVER is not set |
| 857 | # CONFIG_TCG_TPM is not set | 928 | # CONFIG_TCG_TPM is not set |
| 858 | CONFIG_I2C=y | 929 | CONFIG_I2C=y |
| 859 | CONFIG_I2C_BOARDINFO=y | 930 | CONFIG_I2C_BOARDINFO=y |
| 931 | CONFIG_I2C_COMPAT=y | ||
| 860 | CONFIG_I2C_CHARDEV=y | 932 | CONFIG_I2C_CHARDEV=y |
| 933 | CONFIG_I2C_HELPER_AUTO=y | ||
| 861 | 934 | ||
| 862 | # | 935 | # |
| 863 | # I2C Hardware Bus support | 936 | # I2C Hardware Bus support |
| 864 | # | 937 | # |
| 938 | |||
| 939 | # | ||
| 940 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 941 | # | ||
| 942 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 865 | # CONFIG_I2C_GPIO is not set | 943 | # CONFIG_I2C_GPIO is not set |
| 944 | # CONFIG_I2C_OCORES is not set | ||
| 866 | CONFIG_I2C_PXA=y | 945 | CONFIG_I2C_PXA=y |
| 867 | # CONFIG_I2C_PXA_SLAVE is not set | 946 | # CONFIG_I2C_PXA_SLAVE is not set |
| 868 | # CONFIG_I2C_OCORES is not set | ||
| 869 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 870 | # CONFIG_I2C_SIMTEC is not set | 947 | # CONFIG_I2C_SIMTEC is not set |
| 948 | |||
| 949 | # | ||
| 950 | # External I2C/SMBus adapter drivers | ||
| 951 | # | ||
| 952 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 871 | # CONFIG_I2C_TAOS_EVM is not set | 953 | # CONFIG_I2C_TAOS_EVM is not set |
| 872 | # CONFIG_I2C_STUB is not set | ||
| 873 | # CONFIG_I2C_TINY_USB is not set | 954 | # CONFIG_I2C_TINY_USB is not set |
| 955 | |||
| 956 | # | ||
| 957 | # Other I2C/SMBus bus drivers | ||
| 958 | # | ||
| 874 | # CONFIG_I2C_PCA_PLATFORM is not set | 959 | # CONFIG_I2C_PCA_PLATFORM is not set |
| 960 | # CONFIG_I2C_STUB is not set | ||
| 875 | 961 | ||
| 876 | # | 962 | # |
| 877 | # Miscellaneous I2C Chip support | 963 | # Miscellaneous I2C Chip support |
| 878 | # | 964 | # |
| 879 | # CONFIG_DS1682 is not set | 965 | # CONFIG_DS1682 is not set |
| 880 | # CONFIG_EEPROM_LEGACY is not set | ||
| 881 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 882 | # CONFIG_PCF8575 is not set | ||
| 883 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 884 | # CONFIG_TPS65010 is not set | ||
| 885 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 886 | # CONFIG_SENSORS_TSL2550 is not set | 966 | # CONFIG_SENSORS_TSL2550 is not set |
| 887 | # CONFIG_I2C_DEBUG_CORE is not set | 967 | # CONFIG_I2C_DEBUG_CORE is not set |
| 888 | # CONFIG_I2C_DEBUG_ALGO is not set | 968 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 889 | # CONFIG_I2C_DEBUG_BUS is not set | 969 | # CONFIG_I2C_DEBUG_BUS is not set |
| 890 | # CONFIG_I2C_DEBUG_CHIP is not set | 970 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 891 | CONFIG_SPI=y | 971 | CONFIG_SPI=y |
| 972 | # CONFIG_SPI_DEBUG is not set | ||
| 892 | CONFIG_SPI_MASTER=y | 973 | CONFIG_SPI_MASTER=y |
| 893 | 974 | ||
| 894 | # | 975 | # |
| 895 | # SPI Master Controller Drivers | 976 | # SPI Master Controller Drivers |
| 896 | # | 977 | # |
| 897 | # CONFIG_SPI_BITBANG is not set | 978 | # CONFIG_SPI_BITBANG is not set |
| 898 | CONFIG_SPI_PXA2XX=m | 979 | # CONFIG_SPI_GPIO is not set |
| 980 | CONFIG_SPI_PXA2XX=y | ||
| 899 | 981 | ||
| 900 | # | 982 | # |
| 901 | # SPI Protocol Masters | 983 | # SPI Protocol Masters |
| 902 | # | 984 | # |
| 903 | # CONFIG_EEPROM_AT25 is not set | ||
| 904 | # CONFIG_SPI_SPIDEV is not set | 985 | # CONFIG_SPI_SPIDEV is not set |
| 905 | # CONFIG_SPI_TLE62X0 is not set | 986 | # CONFIG_SPI_TLE62X0 is not set |
| 906 | CONFIG_HAVE_GPIO_LIB=y | ||
| 907 | 987 | ||
| 908 | # | 988 | # |
| 909 | # GPIO Support | 989 | # PPS support |
| 990 | # | ||
| 991 | # CONFIG_PPS is not set | ||
| 992 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 993 | CONFIG_GPIOLIB=y | ||
| 994 | # CONFIG_DEBUG_GPIO is not set | ||
| 995 | CONFIG_GPIO_SYSFS=y | ||
| 996 | |||
| 997 | # | ||
| 998 | # Memory mapped GPIO expanders: | ||
| 910 | # | 999 | # |
| 911 | 1000 | ||
| 912 | # | 1001 | # |
| 913 | # I2C GPIO expanders: | 1002 | # I2C GPIO expanders: |
| 914 | # | 1003 | # |
| 1004 | # CONFIG_GPIO_MAX732X is not set | ||
| 915 | # CONFIG_GPIO_PCA953X is not set | 1005 | # CONFIG_GPIO_PCA953X is not set |
| 916 | # CONFIG_GPIO_PCF857X is not set | 1006 | # CONFIG_GPIO_PCF857X is not set |
| 917 | 1007 | ||
| 918 | # | 1008 | # |
| 1009 | # PCI GPIO expanders: | ||
| 1010 | # | ||
| 1011 | |||
| 1012 | # | ||
| 919 | # SPI GPIO expanders: | 1013 | # SPI GPIO expanders: |
| 920 | # | 1014 | # |
| 1015 | # CONFIG_GPIO_MAX7301 is not set | ||
| 921 | # CONFIG_GPIO_MCP23S08 is not set | 1016 | # CONFIG_GPIO_MCP23S08 is not set |
| 1017 | # CONFIG_GPIO_MC33880 is not set | ||
| 1018 | |||
| 1019 | # | ||
| 1020 | # AC97 GPIO expanders: | ||
| 1021 | # | ||
| 922 | # CONFIG_W1 is not set | 1022 | # CONFIG_W1 is not set |
| 923 | # CONFIG_POWER_SUPPLY is not set | 1023 | CONFIG_POWER_SUPPLY=y |
| 1024 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 1025 | # CONFIG_PDA_POWER is not set | ||
| 1026 | # CONFIG_APM_POWER is not set | ||
| 1027 | # CONFIG_BATTERY_DS2760 is not set | ||
| 1028 | # CONFIG_BATTERY_DS2782 is not set | ||
| 1029 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 1030 | # CONFIG_BATTERY_MAX17040 is not set | ||
| 924 | # CONFIG_HWMON is not set | 1031 | # CONFIG_HWMON is not set |
| 1032 | # CONFIG_THERMAL is not set | ||
| 925 | # CONFIG_WATCHDOG is not set | 1033 | # CONFIG_WATCHDOG is not set |
| 1034 | CONFIG_SSB_POSSIBLE=y | ||
| 926 | 1035 | ||
| 927 | # | 1036 | # |
| 928 | # Sonics Silicon Backplane | 1037 | # Sonics Silicon Backplane |
| 929 | # | 1038 | # |
| 930 | CONFIG_SSB_POSSIBLE=y | ||
| 931 | # CONFIG_SSB is not set | 1039 | # CONFIG_SSB is not set |
| 932 | 1040 | ||
| 933 | # | 1041 | # |
| @@ -938,54 +1046,170 @@ CONFIG_SSB_POSSIBLE=y | |||
| 938 | # CONFIG_MFD_ASIC3 is not set | 1046 | # CONFIG_MFD_ASIC3 is not set |
| 939 | # CONFIG_HTC_EGPIO is not set | 1047 | # CONFIG_HTC_EGPIO is not set |
| 940 | # CONFIG_HTC_PASIC3 is not set | 1048 | # CONFIG_HTC_PASIC3 is not set |
| 1049 | # CONFIG_TPS65010 is not set | ||
| 1050 | # CONFIG_TWL4030_CORE is not set | ||
| 1051 | # CONFIG_MFD_TMIO is not set | ||
| 1052 | # CONFIG_MFD_T7L66XB is not set | ||
| 1053 | # CONFIG_MFD_TC6387XB is not set | ||
| 941 | # CONFIG_MFD_TC6393XB is not set | 1054 | # CONFIG_MFD_TC6393XB is not set |
| 1055 | # CONFIG_PMIC_DA903X is not set | ||
| 1056 | # CONFIG_MFD_WM8400 is not set | ||
| 1057 | # CONFIG_MFD_WM831X is not set | ||
| 1058 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1059 | # CONFIG_MFD_PCF50633 is not set | ||
| 1060 | # CONFIG_MFD_MC13783 is not set | ||
| 1061 | # CONFIG_AB3100_CORE is not set | ||
| 942 | CONFIG_EZX_PCAP=y | 1062 | CONFIG_EZX_PCAP=y |
| 943 | 1063 | CONFIG_REGULATOR=y | |
| 944 | # | 1064 | CONFIG_REGULATOR_DEBUG=y |
| 945 | # Multimedia devices | 1065 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set |
| 946 | # | 1066 | CONFIG_REGULATOR_VIRTUAL_CONSUMER=y |
| 1067 | CONFIG_REGULATOR_USERSPACE_CONSUMER=y | ||
| 1068 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1069 | # CONFIG_REGULATOR_MAX1586 is not set | ||
| 1070 | # CONFIG_REGULATOR_LP3971 is not set | ||
| 1071 | CONFIG_REGULATOR_PCAP=y | ||
| 1072 | # CONFIG_REGULATOR_TPS65023 is not set | ||
| 1073 | # CONFIG_REGULATOR_TPS6507X is not set | ||
| 1074 | CONFIG_MEDIA_SUPPORT=y | ||
| 947 | 1075 | ||
| 948 | # | 1076 | # |
| 949 | # Multimedia core support | 1077 | # Multimedia core support |
| 950 | # | 1078 | # |
| 951 | CONFIG_VIDEO_DEV=m | 1079 | CONFIG_VIDEO_DEV=y |
| 952 | CONFIG_VIDEO_V4L2_COMMON=m | 1080 | CONFIG_VIDEO_V4L2_COMMON=y |
| 953 | CONFIG_VIDEO_ALLOW_V4L1=y | 1081 | CONFIG_VIDEO_ALLOW_V4L1=y |
| 954 | CONFIG_VIDEO_V4L1_COMPAT=y | 1082 | CONFIG_VIDEO_V4L1_COMPAT=y |
| 955 | # CONFIG_DVB_CORE is not set | 1083 | # CONFIG_DVB_CORE is not set |
| 956 | CONFIG_VIDEO_MEDIA=m | 1084 | CONFIG_VIDEO_MEDIA=y |
| 957 | 1085 | ||
| 958 | # | 1086 | # |
| 959 | # Multimedia drivers | 1087 | # Multimedia drivers |
| 960 | # | 1088 | # |
| 961 | # CONFIG_MEDIA_ATTACH is not set | 1089 | # CONFIG_MEDIA_ATTACH is not set |
| 962 | CONFIG_MEDIA_TUNER=m | 1090 | CONFIG_MEDIA_TUNER=y |
| 963 | # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set | 1091 | CONFIG_MEDIA_TUNER_CUSTOMISE=y |
| 964 | CONFIG_MEDIA_TUNER_SIMPLE=m | 1092 | # CONFIG_MEDIA_TUNER_SIMPLE is not set |
| 965 | CONFIG_MEDIA_TUNER_TDA8290=m | 1093 | # CONFIG_MEDIA_TUNER_TDA8290 is not set |
| 966 | CONFIG_MEDIA_TUNER_TDA9887=m | 1094 | # CONFIG_MEDIA_TUNER_TDA827X is not set |
| 967 | CONFIG_MEDIA_TUNER_TEA5761=m | 1095 | # CONFIG_MEDIA_TUNER_TDA18271 is not set |
| 968 | CONFIG_MEDIA_TUNER_TEA5767=m | 1096 | # CONFIG_MEDIA_TUNER_TDA9887 is not set |
| 969 | CONFIG_MEDIA_TUNER_MT20XX=m | 1097 | # CONFIG_MEDIA_TUNER_TEA5761 is not set |
| 970 | CONFIG_MEDIA_TUNER_XC2028=m | 1098 | # CONFIG_MEDIA_TUNER_TEA5767 is not set |
| 971 | CONFIG_MEDIA_TUNER_XC5000=m | 1099 | # CONFIG_MEDIA_TUNER_MT20XX is not set |
| 972 | CONFIG_VIDEO_V4L2=m | 1100 | # CONFIG_MEDIA_TUNER_MT2060 is not set |
| 973 | CONFIG_VIDEO_V4L1=m | 1101 | # CONFIG_MEDIA_TUNER_MT2266 is not set |
| 1102 | # CONFIG_MEDIA_TUNER_MT2131 is not set | ||
| 1103 | # CONFIG_MEDIA_TUNER_QT1010 is not set | ||
| 1104 | # CONFIG_MEDIA_TUNER_XC2028 is not set | ||
| 1105 | # CONFIG_MEDIA_TUNER_XC5000 is not set | ||
| 1106 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | ||
| 1107 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | ||
| 1108 | # CONFIG_MEDIA_TUNER_MC44S803 is not set | ||
| 1109 | CONFIG_VIDEO_V4L2=y | ||
| 1110 | CONFIG_VIDEO_V4L1=y | ||
| 1111 | CONFIG_VIDEOBUF_GEN=y | ||
| 1112 | CONFIG_VIDEOBUF_DMA_SG=y | ||
| 974 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | 1113 | CONFIG_VIDEO_CAPTURE_DRIVERS=y |
| 975 | # CONFIG_VIDEO_ADV_DEBUG is not set | 1114 | # CONFIG_VIDEO_ADV_DEBUG is not set |
| 976 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | 1115 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set |
| 1116 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | ||
| 1117 | |||
| 1118 | # | ||
| 1119 | # Encoders/decoders and other helper chips | ||
| 1120 | # | ||
| 1121 | |||
| 1122 | # | ||
| 1123 | # Audio decoders | ||
| 1124 | # | ||
| 1125 | # CONFIG_VIDEO_TVAUDIO is not set | ||
| 1126 | # CONFIG_VIDEO_TDA7432 is not set | ||
| 1127 | # CONFIG_VIDEO_TDA9840 is not set | ||
| 1128 | # CONFIG_VIDEO_TDA9875 is not set | ||
| 1129 | # CONFIG_VIDEO_TEA6415C is not set | ||
| 1130 | # CONFIG_VIDEO_TEA6420 is not set | ||
| 1131 | # CONFIG_VIDEO_MSP3400 is not set | ||
| 1132 | # CONFIG_VIDEO_CS5345 is not set | ||
| 1133 | # CONFIG_VIDEO_CS53L32A is not set | ||
| 1134 | # CONFIG_VIDEO_M52790 is not set | ||
| 1135 | # CONFIG_VIDEO_TLV320AIC23B is not set | ||
| 1136 | # CONFIG_VIDEO_WM8775 is not set | ||
| 1137 | # CONFIG_VIDEO_WM8739 is not set | ||
| 1138 | # CONFIG_VIDEO_VP27SMPX is not set | ||
| 1139 | |||
| 1140 | # | ||
| 1141 | # RDS decoders | ||
| 1142 | # | ||
| 1143 | # CONFIG_VIDEO_SAA6588 is not set | ||
| 1144 | |||
| 1145 | # | ||
| 1146 | # Video decoders | ||
| 1147 | # | ||
| 1148 | # CONFIG_VIDEO_ADV7180 is not set | ||
| 1149 | # CONFIG_VIDEO_BT819 is not set | ||
| 1150 | # CONFIG_VIDEO_BT856 is not set | ||
| 1151 | # CONFIG_VIDEO_BT866 is not set | ||
| 1152 | # CONFIG_VIDEO_KS0127 is not set | ||
| 1153 | # CONFIG_VIDEO_OV7670 is not set | ||
| 1154 | # CONFIG_VIDEO_MT9V011 is not set | ||
| 1155 | # CONFIG_VIDEO_TCM825X is not set | ||
| 1156 | # CONFIG_VIDEO_SAA7110 is not set | ||
| 1157 | # CONFIG_VIDEO_SAA711X is not set | ||
| 1158 | # CONFIG_VIDEO_SAA717X is not set | ||
| 1159 | # CONFIG_VIDEO_SAA7191 is not set | ||
| 1160 | # CONFIG_VIDEO_TVP514X is not set | ||
| 1161 | # CONFIG_VIDEO_TVP5150 is not set | ||
| 1162 | # CONFIG_VIDEO_VPX3220 is not set | ||
| 1163 | |||
| 1164 | # | ||
| 1165 | # Video and audio decoders | ||
| 1166 | # | ||
| 1167 | # CONFIG_VIDEO_CX25840 is not set | ||
| 1168 | |||
| 1169 | # | ||
| 1170 | # MPEG video encoders | ||
| 1171 | # | ||
| 1172 | # CONFIG_VIDEO_CX2341X is not set | ||
| 1173 | |||
| 1174 | # | ||
| 1175 | # Video encoders | ||
| 1176 | # | ||
| 1177 | # CONFIG_VIDEO_SAA7127 is not set | ||
| 1178 | # CONFIG_VIDEO_SAA7185 is not set | ||
| 1179 | # CONFIG_VIDEO_ADV7170 is not set | ||
| 1180 | # CONFIG_VIDEO_ADV7175 is not set | ||
| 1181 | # CONFIG_VIDEO_THS7303 is not set | ||
| 1182 | # CONFIG_VIDEO_ADV7343 is not set | ||
| 1183 | |||
| 1184 | # | ||
| 1185 | # Video improvement chips | ||
| 1186 | # | ||
| 1187 | # CONFIG_VIDEO_UPD64031A is not set | ||
| 1188 | # CONFIG_VIDEO_UPD64083 is not set | ||
| 977 | # CONFIG_VIDEO_VIVI is not set | 1189 | # CONFIG_VIDEO_VIVI is not set |
| 978 | # CONFIG_VIDEO_CPIA is not set | 1190 | # CONFIG_VIDEO_CPIA is not set |
| 979 | # CONFIG_VIDEO_CPIA2 is not set | 1191 | # CONFIG_VIDEO_CPIA2 is not set |
| 980 | # CONFIG_VIDEO_SAA5246A is not set | 1192 | # CONFIG_VIDEO_SAA5246A is not set |
| 981 | # CONFIG_VIDEO_SAA5249 is not set | 1193 | # CONFIG_VIDEO_SAA5249 is not set |
| 982 | # CONFIG_TUNER_3036 is not set | 1194 | CONFIG_SOC_CAMERA=y |
| 1195 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1196 | CONFIG_SOC_CAMERA_MT9M111=y | ||
| 1197 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1198 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1199 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1200 | # CONFIG_SOC_CAMERA_PLATFORM is not set | ||
| 1201 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1202 | CONFIG_VIDEO_PXA27x=y | ||
| 1203 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 983 | # CONFIG_V4L_USB_DRIVERS is not set | 1204 | # CONFIG_V4L_USB_DRIVERS is not set |
| 984 | # CONFIG_SOC_CAMERA is not set | ||
| 985 | # CONFIG_VIDEO_PXA27x is not set | ||
| 986 | CONFIG_RADIO_ADAPTERS=y | 1205 | CONFIG_RADIO_ADAPTERS=y |
| 1206 | # CONFIG_I2C_SI4713 is not set | ||
| 1207 | # CONFIG_RADIO_SI4713 is not set | ||
| 987 | # CONFIG_USB_DSBR is not set | 1208 | # CONFIG_USB_DSBR is not set |
| 988 | # CONFIG_USB_SI470X is not set | 1209 | # CONFIG_RADIO_SI470X is not set |
| 1210 | # CONFIG_USB_MR800 is not set | ||
| 1211 | CONFIG_RADIO_TEA5764=y | ||
| 1212 | CONFIG_RADIO_TEA5764_XTAL=y | ||
| 989 | # CONFIG_DAB is not set | 1213 | # CONFIG_DAB is not set |
| 990 | 1214 | ||
| 991 | # | 1215 | # |
| @@ -996,6 +1220,7 @@ CONFIG_RADIO_ADAPTERS=y | |||
| 996 | CONFIG_FB=y | 1220 | CONFIG_FB=y |
| 997 | # CONFIG_FIRMWARE_EDID is not set | 1221 | # CONFIG_FIRMWARE_EDID is not set |
| 998 | # CONFIG_FB_DDC is not set | 1222 | # CONFIG_FB_DDC is not set |
| 1223 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 999 | CONFIG_FB_CFB_FILLRECT=y | 1224 | CONFIG_FB_CFB_FILLRECT=y |
| 1000 | CONFIG_FB_CFB_COPYAREA=y | 1225 | CONFIG_FB_CFB_COPYAREA=y |
| 1001 | CONFIG_FB_CFB_IMAGEBLIT=y | 1226 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -1017,15 +1242,19 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1017 | # CONFIG_FB_UVESA is not set | 1242 | # CONFIG_FB_UVESA is not set |
| 1018 | # CONFIG_FB_S1D13XXX is not set | 1243 | # CONFIG_FB_S1D13XXX is not set |
| 1019 | CONFIG_FB_PXA=y | 1244 | CONFIG_FB_PXA=y |
| 1245 | CONFIG_FB_PXA_OVERLAY=y | ||
| 1020 | # CONFIG_FB_PXA_SMARTPANEL is not set | 1246 | # CONFIG_FB_PXA_SMARTPANEL is not set |
| 1021 | CONFIG_FB_PXA_PARAMETERS=y | 1247 | CONFIG_FB_PXA_PARAMETERS=y |
| 1022 | # CONFIG_FB_MBX is not set | 1248 | # CONFIG_FB_MBX is not set |
| 1023 | # CONFIG_FB_AM200EPD is not set | 1249 | # CONFIG_FB_W100 is not set |
| 1024 | # CONFIG_FB_VIRTUAL is not set | 1250 | # CONFIG_FB_VIRTUAL is not set |
| 1251 | # CONFIG_FB_METRONOME is not set | ||
| 1252 | # CONFIG_FB_MB862XX is not set | ||
| 1253 | # CONFIG_FB_BROADSHEET is not set | ||
| 1025 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1254 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 1026 | # CONFIG_LCD_CLASS_DEVICE is not set | 1255 | # CONFIG_LCD_CLASS_DEVICE is not set |
| 1027 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 1256 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 1028 | # CONFIG_BACKLIGHT_CORGI is not set | 1257 | CONFIG_BACKLIGHT_GENERIC=y |
| 1029 | CONFIG_BACKLIGHT_PWM=y | 1258 | CONFIG_BACKLIGHT_PWM=y |
| 1030 | 1259 | ||
| 1031 | # | 1260 | # |
| @@ -1053,85 +1282,60 @@ CONFIG_FONT_MINI_4x6=y | |||
| 1053 | # CONFIG_FONT_SUN12x22 is not set | 1282 | # CONFIG_FONT_SUN12x22 is not set |
| 1054 | # CONFIG_FONT_10x18 is not set | 1283 | # CONFIG_FONT_10x18 is not set |
| 1055 | # CONFIG_LOGO is not set | 1284 | # CONFIG_LOGO is not set |
| 1056 | |||
| 1057 | # | ||
| 1058 | # Sound | ||
| 1059 | # | ||
| 1060 | CONFIG_SOUND=y | 1285 | CONFIG_SOUND=y |
| 1061 | 1286 | CONFIG_SOUND_OSS_CORE=y | |
| 1062 | # | 1287 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y |
| 1063 | # Advanced Linux Sound Architecture | ||
| 1064 | # | ||
| 1065 | CONFIG_SND=y | 1288 | CONFIG_SND=y |
| 1066 | CONFIG_SND_TIMER=y | 1289 | CONFIG_SND_TIMER=y |
| 1067 | CONFIG_SND_PCM=y | 1290 | CONFIG_SND_PCM=y |
| 1291 | CONFIG_SND_JACK=y | ||
| 1068 | # CONFIG_SND_SEQUENCER is not set | 1292 | # CONFIG_SND_SEQUENCER is not set |
| 1069 | CONFIG_SND_OSSEMUL=y | 1293 | CONFIG_SND_OSSEMUL=y |
| 1070 | CONFIG_SND_MIXER_OSS=y | 1294 | CONFIG_SND_MIXER_OSS=y |
| 1071 | CONFIG_SND_PCM_OSS=y | 1295 | CONFIG_SND_PCM_OSS=y |
| 1072 | CONFIG_SND_PCM_OSS_PLUGINS=y | 1296 | CONFIG_SND_PCM_OSS_PLUGINS=y |
| 1297 | # CONFIG_SND_HRTIMER is not set | ||
| 1073 | # CONFIG_SND_DYNAMIC_MINORS is not set | 1298 | # CONFIG_SND_DYNAMIC_MINORS is not set |
| 1074 | CONFIG_SND_SUPPORT_OLD_API=y | 1299 | CONFIG_SND_SUPPORT_OLD_API=y |
| 1075 | CONFIG_SND_VERBOSE_PROCFS=y | 1300 | CONFIG_SND_VERBOSE_PROCFS=y |
| 1076 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1301 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 1077 | # CONFIG_SND_DEBUG is not set | 1302 | # CONFIG_SND_DEBUG is not set |
| 1078 | 1303 | # CONFIG_SND_RAWMIDI_SEQ is not set | |
| 1079 | # | 1304 | # CONFIG_SND_OPL3_LIB_SEQ is not set |
| 1080 | # Generic devices | 1305 | # CONFIG_SND_OPL4_LIB_SEQ is not set |
| 1081 | # | 1306 | # CONFIG_SND_SBAWE_SEQ is not set |
| 1082 | # CONFIG_SND_DUMMY is not set | 1307 | # CONFIG_SND_EMU10K1_SEQ is not set |
| 1083 | # CONFIG_SND_MTPAV is not set | 1308 | # CONFIG_SND_DRIVERS is not set |
| 1084 | # CONFIG_SND_SERIAL_U16550 is not set | 1309 | # CONFIG_SND_ARM is not set |
| 1085 | # CONFIG_SND_MPU401 is not set | 1310 | CONFIG_SND_PXA2XX_LIB=y |
| 1086 | 1311 | # CONFIG_SND_SPI is not set | |
| 1087 | # | 1312 | # CONFIG_SND_USB is not set |
| 1088 | # ALSA ARM devices | ||
| 1089 | # | ||
| 1090 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 1091 | |||
| 1092 | # | ||
| 1093 | # SPI devices | ||
| 1094 | # | ||
| 1095 | |||
| 1096 | # | ||
| 1097 | # USB devices | ||
| 1098 | # | ||
| 1099 | # CONFIG_SND_USB_AUDIO is not set | ||
| 1100 | # CONFIG_SND_USB_CAIAQ is not set | ||
| 1101 | |||
| 1102 | # | ||
| 1103 | # System on Chip audio support | ||
| 1104 | # | ||
| 1105 | CONFIG_SND_SOC=y | 1313 | CONFIG_SND_SOC=y |
| 1106 | CONFIG_SND_PXA2XX_SOC=y | 1314 | CONFIG_SND_PXA2XX_SOC=y |
| 1107 | 1315 | CONFIG_SND_SOC_I2C_AND_SPI=y | |
| 1108 | # | 1316 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 1109 | # ALSA SoC audio for Freescale SOCs | ||
| 1110 | # | ||
| 1111 | |||
| 1112 | # | ||
| 1113 | # SoC Audio for the Texas Instruments OMAP | ||
| 1114 | # | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Open Sound System | ||
| 1118 | # | ||
| 1119 | # CONFIG_SOUND_PRIME is not set | 1317 | # CONFIG_SOUND_PRIME is not set |
| 1120 | CONFIG_HID_SUPPORT=y | 1318 | CONFIG_HID_SUPPORT=y |
| 1121 | CONFIG_HID=y | 1319 | CONFIG_HID=y |
| 1122 | # CONFIG_HID_DEBUG is not set | ||
| 1123 | # CONFIG_HIDRAW is not set | 1320 | # CONFIG_HIDRAW is not set |
| 1124 | 1321 | ||
| 1125 | # | 1322 | # |
| 1126 | # USB Input Devices | 1323 | # USB Input Devices |
| 1127 | # | 1324 | # |
| 1128 | # CONFIG_USB_HID is not set | 1325 | # CONFIG_USB_HID is not set |
| 1326 | # CONFIG_HID_PID is not set | ||
| 1129 | 1327 | ||
| 1130 | # | 1328 | # |
| 1131 | # USB HID Boot Protocol drivers | 1329 | # USB HID Boot Protocol drivers |
| 1132 | # | 1330 | # |
| 1133 | # CONFIG_USB_KBD is not set | 1331 | # CONFIG_USB_KBD is not set |
| 1134 | # CONFIG_USB_MOUSE is not set | 1332 | # CONFIG_USB_MOUSE is not set |
| 1333 | |||
| 1334 | # | ||
| 1335 | # Special HID drivers | ||
| 1336 | # | ||
| 1337 | CONFIG_HID_APPLE=m | ||
| 1338 | # CONFIG_HID_WACOM is not set | ||
| 1135 | CONFIG_USB_SUPPORT=y | 1339 | CONFIG_USB_SUPPORT=y |
| 1136 | CONFIG_USB_ARCH_HAS_HCD=y | 1340 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1137 | CONFIG_USB_ARCH_HAS_OHCI=y | 1341 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -1150,32 +1354,42 @@ CONFIG_USB=y | |||
| 1150 | # CONFIG_USB_OTG is not set | 1354 | # CONFIG_USB_OTG is not set |
| 1151 | # CONFIG_USB_OTG_WHITELIST is not set | 1355 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1152 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | 1356 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set |
| 1357 | # CONFIG_USB_MON is not set | ||
| 1358 | # CONFIG_USB_WUSB is not set | ||
| 1359 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1153 | 1360 | ||
| 1154 | # | 1361 | # |
| 1155 | # USB Host Controller Drivers | 1362 | # USB Host Controller Drivers |
| 1156 | # | 1363 | # |
| 1157 | # CONFIG_USB_C67X00_HCD is not set | 1364 | # CONFIG_USB_C67X00_HCD is not set |
| 1365 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1158 | # CONFIG_USB_ISP116X_HCD is not set | 1366 | # CONFIG_USB_ISP116X_HCD is not set |
| 1159 | # CONFIG_USB_ISP1760_HCD is not set | 1367 | # CONFIG_USB_ISP1760_HCD is not set |
| 1368 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1160 | CONFIG_USB_OHCI_HCD=y | 1369 | CONFIG_USB_OHCI_HCD=y |
| 1161 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1370 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 1162 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1371 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| 1163 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 1372 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 1164 | # CONFIG_USB_SL811_HCD is not set | 1373 | # CONFIG_USB_SL811_HCD is not set |
| 1165 | # CONFIG_USB_R8A66597_HCD is not set | 1374 | # CONFIG_USB_R8A66597_HCD is not set |
| 1375 | # CONFIG_USB_HWA_HCD is not set | ||
| 1376 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1377 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1166 | 1378 | ||
| 1167 | # | 1379 | # |
| 1168 | # USB Device Class drivers | 1380 | # USB Device Class drivers |
| 1169 | # | 1381 | # |
| 1170 | # CONFIG_USB_ACM is not set | 1382 | # CONFIG_USB_ACM is not set |
| 1171 | # CONFIG_USB_PRINTER is not set | 1383 | # CONFIG_USB_PRINTER is not set |
| 1384 | # CONFIG_USB_WDM is not set | ||
| 1385 | # CONFIG_USB_TMC is not set | ||
| 1172 | 1386 | ||
| 1173 | # | 1387 | # |
| 1174 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1388 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may |
| 1175 | # | 1389 | # |
| 1176 | 1390 | ||
| 1177 | # | 1391 | # |
| 1178 | # may also be needed; see USB_STORAGE Help for more information | 1392 | # also be needed; see USB_STORAGE Help for more info |
| 1179 | # | 1393 | # |
| 1180 | # CONFIG_USB_LIBUSUAL is not set | 1394 | # CONFIG_USB_LIBUSUAL is not set |
| 1181 | 1395 | ||
| @@ -1183,7 +1397,6 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1183 | # USB Imaging devices | 1397 | # USB Imaging devices |
| 1184 | # | 1398 | # |
| 1185 | # CONFIG_USB_MDC800 is not set | 1399 | # CONFIG_USB_MDC800 is not set |
| 1186 | # CONFIG_USB_MON is not set | ||
| 1187 | 1400 | ||
| 1188 | # | 1401 | # |
| 1189 | # USB port drivers | 1402 | # USB port drivers |
| @@ -1196,7 +1409,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1196 | # CONFIG_USB_EMI62 is not set | 1409 | # CONFIG_USB_EMI62 is not set |
| 1197 | # CONFIG_USB_EMI26 is not set | 1410 | # CONFIG_USB_EMI26 is not set |
| 1198 | # CONFIG_USB_ADUTUX is not set | 1411 | # CONFIG_USB_ADUTUX is not set |
| 1199 | # CONFIG_USB_AUERSWALD is not set | 1412 | # CONFIG_USB_SEVSEG is not set |
| 1200 | # CONFIG_USB_RIO500 is not set | 1413 | # CONFIG_USB_RIO500 is not set |
| 1201 | # CONFIG_USB_LEGOTOWER is not set | 1414 | # CONFIG_USB_LEGOTOWER is not set |
| 1202 | # CONFIG_USB_LCD is not set | 1415 | # CONFIG_USB_LCD is not set |
| @@ -1204,62 +1417,94 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1204 | # CONFIG_USB_LED is not set | 1417 | # CONFIG_USB_LED is not set |
| 1205 | # CONFIG_USB_CYPRESS_CY7C63 is not set | 1418 | # CONFIG_USB_CYPRESS_CY7C63 is not set |
| 1206 | # CONFIG_USB_CYTHERM is not set | 1419 | # CONFIG_USB_CYTHERM is not set |
| 1207 | # CONFIG_USB_PHIDGET is not set | ||
| 1208 | # CONFIG_USB_IDMOUSE is not set | 1420 | # CONFIG_USB_IDMOUSE is not set |
| 1209 | # CONFIG_USB_FTDI_ELAN is not set | 1421 | # CONFIG_USB_FTDI_ELAN is not set |
| 1210 | # CONFIG_USB_APPLEDISPLAY is not set | 1422 | # CONFIG_USB_APPLEDISPLAY is not set |
| 1211 | # CONFIG_USB_LD is not set | 1423 | # CONFIG_USB_LD is not set |
| 1212 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1424 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1213 | # CONFIG_USB_IOWARRIOR is not set | 1425 | # CONFIG_USB_IOWARRIOR is not set |
| 1426 | # CONFIG_USB_TEST is not set | ||
| 1427 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1428 | # CONFIG_USB_VST is not set | ||
| 1214 | CONFIG_USB_GADGET=y | 1429 | CONFIG_USB_GADGET=y |
| 1430 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1215 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 1431 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 1432 | # CONFIG_USB_GADGET_DEBUG_FS is not set | ||
| 1433 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1216 | CONFIG_USB_GADGET_SELECTED=y | 1434 | CONFIG_USB_GADGET_SELECTED=y |
| 1217 | # CONFIG_USB_GADGET_AMD5536UDC is not set | 1435 | # CONFIG_USB_GADGET_AT91 is not set |
| 1218 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | 1436 | # CONFIG_USB_GADGET_ATMEL_USBA is not set |
| 1219 | # CONFIG_USB_GADGET_FSL_USB2 is not set | 1437 | # CONFIG_USB_GADGET_FSL_USB2 is not set |
| 1220 | # CONFIG_USB_GADGET_NET2280 is not set | 1438 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 1439 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1221 | # CONFIG_USB_GADGET_PXA25X is not set | 1440 | # CONFIG_USB_GADGET_PXA25X is not set |
| 1222 | # CONFIG_USB_GADGET_M66592 is not set | 1441 | # CONFIG_USB_GADGET_R8A66597 is not set |
| 1223 | CONFIG_USB_GADGET_PXA27X=y | 1442 | CONFIG_USB_GADGET_PXA27X=y |
| 1224 | CONFIG_USB_PXA27X=y | 1443 | CONFIG_USB_PXA27X=y |
| 1225 | # CONFIG_USB_GADGET_GOKU is not set | 1444 | # CONFIG_USB_GADGET_S3C_HSOTG is not set |
| 1226 | # CONFIG_USB_GADGET_LH7A40X is not set | 1445 | # CONFIG_USB_GADGET_IMX is not set |
| 1227 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1228 | # CONFIG_USB_GADGET_S3C2410 is not set | 1446 | # CONFIG_USB_GADGET_S3C2410 is not set |
| 1229 | # CONFIG_USB_GADGET_AT91 is not set | 1447 | # CONFIG_USB_GADGET_M66592 is not set |
| 1448 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1449 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1450 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1451 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1452 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1453 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 1230 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | 1454 | # CONFIG_USB_GADGET_DUMMY_HCD is not set |
| 1231 | # CONFIG_USB_GADGET_DUALSPEED is not set | 1455 | # CONFIG_USB_GADGET_DUALSPEED is not set |
| 1232 | # CONFIG_USB_ZERO is not set | 1456 | # CONFIG_USB_ZERO is not set |
| 1457 | # CONFIG_USB_AUDIO is not set | ||
| 1233 | CONFIG_USB_ETH=y | 1458 | CONFIG_USB_ETH=y |
| 1234 | # CONFIG_USB_ETH_RNDIS is not set | 1459 | # CONFIG_USB_ETH_RNDIS is not set |
| 1460 | # CONFIG_USB_ETH_EEM is not set | ||
| 1235 | # CONFIG_USB_GADGETFS is not set | 1461 | # CONFIG_USB_GADGETFS is not set |
| 1236 | # CONFIG_USB_FILE_STORAGE is not set | 1462 | # CONFIG_USB_FILE_STORAGE is not set |
| 1237 | # CONFIG_USB_G_SERIAL is not set | 1463 | # CONFIG_USB_G_SERIAL is not set |
| 1238 | # CONFIG_USB_MIDI_GADGET is not set | 1464 | # CONFIG_USB_MIDI_GADGET is not set |
| 1239 | # CONFIG_USB_G_PRINTER is not set | 1465 | # CONFIG_USB_G_PRINTER is not set |
| 1466 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1467 | |||
| 1468 | # | ||
| 1469 | # OTG and related infrastructure | ||
| 1470 | # | ||
| 1471 | CONFIG_USB_OTG_UTILS=y | ||
| 1472 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1473 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1240 | CONFIG_MMC=y | 1474 | CONFIG_MMC=y |
| 1241 | # CONFIG_MMC_DEBUG is not set | 1475 | # CONFIG_MMC_DEBUG is not set |
| 1242 | CONFIG_MMC_UNSAFE_RESUME=y | 1476 | CONFIG_MMC_UNSAFE_RESUME=y |
| 1243 | 1477 | ||
| 1244 | # | 1478 | # |
| 1245 | # MMC/SD Card Drivers | 1479 | # MMC/SD/SDIO Card Drivers |
| 1246 | # | 1480 | # |
| 1247 | CONFIG_MMC_BLOCK=y | 1481 | CONFIG_MMC_BLOCK=y |
| 1248 | CONFIG_MMC_BLOCK_BOUNCE=y | 1482 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 1249 | CONFIG_SDIO_UART=y | 1483 | CONFIG_SDIO_UART=m |
| 1484 | # CONFIG_MMC_TEST is not set | ||
| 1250 | 1485 | ||
| 1251 | # | 1486 | # |
| 1252 | # MMC/SD Host Controller Drivers | 1487 | # MMC/SD/SDIO Host Controller Drivers |
| 1253 | # | 1488 | # |
| 1254 | CONFIG_MMC_PXA=y | 1489 | CONFIG_MMC_PXA=y |
| 1255 | # CONFIG_MMC_SPI is not set | 1490 | # CONFIG_MMC_SDHCI is not set |
| 1491 | # CONFIG_MMC_AT91 is not set | ||
| 1492 | # CONFIG_MMC_ATMELMCI is not set | ||
| 1493 | CONFIG_MMC_SPI=y | ||
| 1494 | # CONFIG_MEMSTICK is not set | ||
| 1256 | CONFIG_NEW_LEDS=y | 1495 | CONFIG_NEW_LEDS=y |
| 1257 | CONFIG_LEDS_CLASS=y | 1496 | CONFIG_LEDS_CLASS=y |
| 1258 | 1497 | ||
| 1259 | # | 1498 | # |
| 1260 | # LED drivers | 1499 | # LED drivers |
| 1261 | # | 1500 | # |
| 1501 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1262 | # CONFIG_LEDS_GPIO is not set | 1502 | # CONFIG_LEDS_GPIO is not set |
| 1503 | CONFIG_LEDS_LP3944=y | ||
| 1504 | # CONFIG_LEDS_PCA955X is not set | ||
| 1505 | # CONFIG_LEDS_DAC124S085 is not set | ||
| 1506 | # CONFIG_LEDS_PWM is not set | ||
| 1507 | # CONFIG_LEDS_BD2802 is not set | ||
| 1263 | 1508 | ||
| 1264 | # | 1509 | # |
| 1265 | # LED Triggers | 1510 | # LED Triggers |
| @@ -1267,7 +1512,14 @@ CONFIG_LEDS_CLASS=y | |||
| 1267 | CONFIG_LEDS_TRIGGERS=y | 1512 | CONFIG_LEDS_TRIGGERS=y |
| 1268 | CONFIG_LEDS_TRIGGER_TIMER=y | 1513 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 1269 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 1514 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 1270 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | 1515 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 1516 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1517 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1518 | |||
| 1519 | # | ||
| 1520 | # iptables trigger is under Netfilter config (LED target) | ||
| 1521 | # | ||
| 1522 | # CONFIG_ACCESSIBILITY is not set | ||
| 1271 | CONFIG_RTC_LIB=y | 1523 | CONFIG_RTC_LIB=y |
| 1272 | CONFIG_RTC_CLASS=y | 1524 | CONFIG_RTC_CLASS=y |
| 1273 | CONFIG_RTC_HCTOSYS=y | 1525 | CONFIG_RTC_HCTOSYS=y |
| @@ -1297,45 +1549,67 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1297 | # CONFIG_RTC_DRV_PCF8583 is not set | 1549 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1298 | # CONFIG_RTC_DRV_M41T80 is not set | 1550 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1299 | # CONFIG_RTC_DRV_S35390A is not set | 1551 | # CONFIG_RTC_DRV_S35390A is not set |
| 1552 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1553 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1554 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1300 | 1555 | ||
| 1301 | # | 1556 | # |
| 1302 | # SPI RTC drivers | 1557 | # SPI RTC drivers |
| 1303 | # | 1558 | # |
| 1559 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1560 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1561 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1304 | # CONFIG_RTC_DRV_MAX6902 is not set | 1562 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 1305 | # CONFIG_RTC_DRV_R9701 is not set | 1563 | # CONFIG_RTC_DRV_R9701 is not set |
| 1306 | # CONFIG_RTC_DRV_RS5C348 is not set | 1564 | # CONFIG_RTC_DRV_RS5C348 is not set |
| 1565 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1566 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1307 | 1567 | ||
| 1308 | # | 1568 | # |
| 1309 | # Platform RTC drivers | 1569 | # Platform RTC drivers |
| 1310 | # | 1570 | # |
| 1311 | # CONFIG_RTC_DRV_CMOS is not set | 1571 | # CONFIG_RTC_DRV_CMOS is not set |
| 1572 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1312 | # CONFIG_RTC_DRV_DS1511 is not set | 1573 | # CONFIG_RTC_DRV_DS1511 is not set |
| 1313 | # CONFIG_RTC_DRV_DS1553 is not set | 1574 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1314 | # CONFIG_RTC_DRV_DS1742 is not set | 1575 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1315 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1576 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1316 | # CONFIG_RTC_DRV_M48T86 is not set | 1577 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1578 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1317 | # CONFIG_RTC_DRV_M48T59 is not set | 1579 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1580 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1318 | # CONFIG_RTC_DRV_V3020 is not set | 1581 | # CONFIG_RTC_DRV_V3020 is not set |
| 1319 | 1582 | ||
| 1320 | # | 1583 | # |
| 1321 | # on-CPU RTC drivers | 1584 | # on-CPU RTC drivers |
| 1322 | # | 1585 | # |
| 1323 | CONFIG_RTC_DRV_SA1100=m | 1586 | # CONFIG_RTC_DRV_SA1100 is not set |
| 1587 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1588 | CONFIG_RTC_DRV_PCAP=y | ||
| 1589 | # CONFIG_DMADEVICES is not set | ||
| 1590 | # CONFIG_AUXDISPLAY is not set | ||
| 1324 | # CONFIG_UIO is not set | 1591 | # CONFIG_UIO is not set |
| 1325 | 1592 | ||
| 1326 | # | 1593 | # |
| 1594 | # TI VLYNQ | ||
| 1595 | # | ||
| 1596 | # CONFIG_STAGING is not set | ||
| 1597 | |||
| 1598 | # | ||
| 1327 | # File systems | 1599 | # File systems |
| 1328 | # | 1600 | # |
| 1329 | CONFIG_EXT2_FS=y | 1601 | CONFIG_EXT2_FS=y |
| 1330 | # CONFIG_EXT2_FS_XATTR is not set | 1602 | # CONFIG_EXT2_FS_XATTR is not set |
| 1331 | # CONFIG_EXT2_FS_XIP is not set | 1603 | # CONFIG_EXT2_FS_XIP is not set |
| 1332 | CONFIG_EXT3_FS=m | 1604 | CONFIG_EXT3_FS=m |
| 1605 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1333 | CONFIG_EXT3_FS_XATTR=y | 1606 | CONFIG_EXT3_FS_XATTR=y |
| 1334 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1607 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 1335 | # CONFIG_EXT3_FS_SECURITY is not set | 1608 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1336 | # CONFIG_EXT4DEV_FS is not set | 1609 | # CONFIG_EXT4_FS is not set |
| 1337 | CONFIG_JBD=m | 1610 | CONFIG_JBD=m |
| 1338 | CONFIG_FS_MBCACHE=y | 1611 | # CONFIG_JBD_DEBUG is not set |
| 1612 | CONFIG_FS_MBCACHE=m | ||
| 1339 | CONFIG_REISERFS_FS=m | 1613 | CONFIG_REISERFS_FS=m |
| 1340 | # CONFIG_REISERFS_CHECK is not set | 1614 | # CONFIG_REISERFS_CHECK is not set |
| 1341 | # CONFIG_REISERFS_PROC_INFO is not set | 1615 | # CONFIG_REISERFS_PROC_INFO is not set |
| @@ -1350,6 +1624,10 @@ CONFIG_XFS_FS=m | |||
| 1350 | # CONFIG_XFS_RT is not set | 1624 | # CONFIG_XFS_RT is not set |
| 1351 | # CONFIG_XFS_DEBUG is not set | 1625 | # CONFIG_XFS_DEBUG is not set |
| 1352 | # CONFIG_OCFS2_FS is not set | 1626 | # CONFIG_OCFS2_FS is not set |
| 1627 | # CONFIG_BTRFS_FS is not set | ||
| 1628 | # CONFIG_NILFS2_FS is not set | ||
| 1629 | CONFIG_FILE_LOCKING=y | ||
| 1630 | CONFIG_FSNOTIFY=y | ||
| 1353 | CONFIG_DNOTIFY=y | 1631 | CONFIG_DNOTIFY=y |
| 1354 | CONFIG_INOTIFY=y | 1632 | CONFIG_INOTIFY=y |
| 1355 | CONFIG_INOTIFY_USER=y | 1633 | CONFIG_INOTIFY_USER=y |
| @@ -1357,6 +1635,12 @@ CONFIG_INOTIFY_USER=y | |||
| 1357 | CONFIG_AUTOFS_FS=y | 1635 | CONFIG_AUTOFS_FS=y |
| 1358 | CONFIG_AUTOFS4_FS=y | 1636 | CONFIG_AUTOFS4_FS=y |
| 1359 | CONFIG_FUSE_FS=m | 1637 | CONFIG_FUSE_FS=m |
| 1638 | CONFIG_CUSE=m | ||
| 1639 | |||
| 1640 | # | ||
| 1641 | # Caches | ||
| 1642 | # | ||
| 1643 | # CONFIG_FSCACHE is not set | ||
| 1360 | 1644 | ||
| 1361 | # | 1645 | # |
| 1362 | # CD-ROM/DVD Filesystems | 1646 | # CD-ROM/DVD Filesystems |
| @@ -1381,15 +1665,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1381 | # | 1665 | # |
| 1382 | CONFIG_PROC_FS=y | 1666 | CONFIG_PROC_FS=y |
| 1383 | CONFIG_PROC_SYSCTL=y | 1667 | CONFIG_PROC_SYSCTL=y |
| 1668 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1384 | CONFIG_SYSFS=y | 1669 | CONFIG_SYSFS=y |
| 1385 | CONFIG_TMPFS=y | 1670 | CONFIG_TMPFS=y |
| 1386 | # CONFIG_TMPFS_POSIX_ACL is not set | 1671 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1387 | # CONFIG_HUGETLB_PAGE is not set | 1672 | # CONFIG_HUGETLB_PAGE is not set |
| 1388 | # CONFIG_CONFIGFS_FS is not set | 1673 | # CONFIG_CONFIGFS_FS is not set |
| 1389 | 1674 | CONFIG_MISC_FILESYSTEMS=y | |
| 1390 | # | ||
| 1391 | # Miscellaneous filesystems | ||
| 1392 | # | ||
| 1393 | # CONFIG_ADFS_FS is not set | 1675 | # CONFIG_ADFS_FS is not set |
| 1394 | # CONFIG_AFFS_FS is not set | 1676 | # CONFIG_AFFS_FS is not set |
| 1395 | # CONFIG_HFS_FS is not set | 1677 | # CONFIG_HFS_FS is not set |
| @@ -1397,13 +1679,35 @@ CONFIG_TMPFS=y | |||
| 1397 | # CONFIG_BEFS_FS is not set | 1679 | # CONFIG_BEFS_FS is not set |
| 1398 | # CONFIG_BFS_FS is not set | 1680 | # CONFIG_BFS_FS is not set |
| 1399 | # CONFIG_EFS_FS is not set | 1681 | # CONFIG_EFS_FS is not set |
| 1400 | # CONFIG_JFFS2_FS is not set | 1682 | CONFIG_JFFS2_FS=m |
| 1683 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1684 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1685 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1686 | # CONFIG_JFFS2_SUMMARY is not set | ||
| 1687 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1688 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1689 | CONFIG_JFFS2_ZLIB=y | ||
| 1690 | CONFIG_JFFS2_LZO=y | ||
| 1691 | CONFIG_JFFS2_RTIME=y | ||
| 1692 | CONFIG_JFFS2_RUBIN=y | ||
| 1693 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1694 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1695 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1696 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1401 | CONFIG_CRAMFS=m | 1697 | CONFIG_CRAMFS=m |
| 1698 | CONFIG_SQUASHFS=m | ||
| 1699 | # CONFIG_SQUASHFS_EMBEDDED is not set | ||
| 1700 | CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 | ||
| 1402 | # CONFIG_VXFS_FS is not set | 1701 | # CONFIG_VXFS_FS is not set |
| 1403 | # CONFIG_MINIX_FS is not set | 1702 | # CONFIG_MINIX_FS is not set |
| 1703 | # CONFIG_OMFS_FS is not set | ||
| 1404 | # CONFIG_HPFS_FS is not set | 1704 | # CONFIG_HPFS_FS is not set |
| 1405 | # CONFIG_QNX4FS_FS is not set | 1705 | # CONFIG_QNX4FS_FS is not set |
| 1406 | # CONFIG_ROMFS_FS is not set | 1706 | CONFIG_ROMFS_FS=m |
| 1707 | CONFIG_ROMFS_BACKED_BY_BLOCK=y | ||
| 1708 | # CONFIG_ROMFS_BACKED_BY_MTD is not set | ||
| 1709 | # CONFIG_ROMFS_BACKED_BY_BOTH is not set | ||
| 1710 | CONFIG_ROMFS_ON_BLOCK=y | ||
| 1407 | # CONFIG_SYSV_FS is not set | 1711 | # CONFIG_SYSV_FS is not set |
| 1408 | # CONFIG_UFS_FS is not set | 1712 | # CONFIG_UFS_FS is not set |
| 1409 | CONFIG_NETWORK_FILESYSTEMS=y | 1713 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1411,19 +1715,18 @@ CONFIG_NFS_FS=y | |||
| 1411 | CONFIG_NFS_V3=y | 1715 | CONFIG_NFS_V3=y |
| 1412 | CONFIG_NFS_V3_ACL=y | 1716 | CONFIG_NFS_V3_ACL=y |
| 1413 | # CONFIG_NFS_V4 is not set | 1717 | # CONFIG_NFS_V4 is not set |
| 1718 | # CONFIG_ROOT_NFS is not set | ||
| 1414 | CONFIG_NFSD=m | 1719 | CONFIG_NFSD=m |
| 1415 | CONFIG_NFSD_V2_ACL=y | 1720 | CONFIG_NFSD_V2_ACL=y |
| 1416 | CONFIG_NFSD_V3=y | 1721 | CONFIG_NFSD_V3=y |
| 1417 | CONFIG_NFSD_V3_ACL=y | 1722 | CONFIG_NFSD_V3_ACL=y |
| 1418 | # CONFIG_NFSD_V4 is not set | 1723 | # CONFIG_NFSD_V4 is not set |
| 1419 | # CONFIG_ROOT_NFS is not set | ||
| 1420 | CONFIG_LOCKD=y | 1724 | CONFIG_LOCKD=y |
| 1421 | CONFIG_LOCKD_V4=y | 1725 | CONFIG_LOCKD_V4=y |
| 1422 | CONFIG_EXPORTFS=m | 1726 | CONFIG_EXPORTFS=m |
| 1423 | CONFIG_NFS_ACL_SUPPORT=y | 1727 | CONFIG_NFS_ACL_SUPPORT=y |
| 1424 | CONFIG_NFS_COMMON=y | 1728 | CONFIG_NFS_COMMON=y |
| 1425 | CONFIG_SUNRPC=y | 1729 | CONFIG_SUNRPC=y |
| 1426 | # CONFIG_SUNRPC_BIND34 is not set | ||
| 1427 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1730 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1428 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1731 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1429 | CONFIG_SMB_FS=m | 1732 | CONFIG_SMB_FS=m |
| @@ -1490,25 +1793,83 @@ CONFIG_NLS_UTF8=m | |||
| 1490 | # | 1793 | # |
| 1491 | # Kernel hacking | 1794 | # Kernel hacking |
| 1492 | # | 1795 | # |
| 1493 | # CONFIG_PRINTK_TIME is not set | 1796 | CONFIG_PRINTK_TIME=y |
| 1494 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1797 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1495 | # CONFIG_ENABLE_MUST_CHECK is not set | 1798 | CONFIG_ENABLE_MUST_CHECK=y |
| 1496 | CONFIG_FRAME_WARN=1024 | 1799 | CONFIG_FRAME_WARN=1024 |
| 1497 | # CONFIG_MAGIC_SYSRQ is not set | 1800 | # CONFIG_MAGIC_SYSRQ is not set |
| 1801 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1498 | # CONFIG_UNUSED_SYMBOLS is not set | 1802 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1499 | # CONFIG_DEBUG_FS is not set | 1803 | CONFIG_DEBUG_FS=y |
| 1500 | # CONFIG_HEADERS_CHECK is not set | 1804 | # CONFIG_HEADERS_CHECK is not set |
| 1501 | # CONFIG_DEBUG_KERNEL is not set | 1805 | CONFIG_DEBUG_KERNEL=y |
| 1502 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1806 | # CONFIG_DEBUG_SHIRQ is not set |
| 1503 | CONFIG_FRAME_POINTER=y | 1807 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1808 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1809 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1810 | CONFIG_DETECT_HUNG_TASK=y | ||
| 1811 | # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set | ||
| 1812 | CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 | ||
| 1813 | # CONFIG_SCHED_DEBUG is not set | ||
| 1814 | # CONFIG_SCHEDSTATS is not set | ||
| 1815 | # CONFIG_TIMER_STATS is not set | ||
| 1816 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1817 | # CONFIG_DEBUG_SLAB is not set | ||
| 1818 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 1819 | CONFIG_DEBUG_PREEMPT=y | ||
| 1820 | CONFIG_DEBUG_RT_MUTEXES=y | ||
| 1821 | CONFIG_DEBUG_PI_LIST=y | ||
| 1822 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1823 | CONFIG_DEBUG_SPINLOCK=y | ||
| 1824 | CONFIG_DEBUG_MUTEXES=y | ||
| 1825 | CONFIG_DEBUG_LOCK_ALLOC=y | ||
| 1826 | CONFIG_PROVE_LOCKING=y | ||
| 1827 | CONFIG_LOCKDEP=y | ||
| 1828 | # CONFIG_LOCK_STAT is not set | ||
| 1829 | # CONFIG_DEBUG_LOCKDEP is not set | ||
| 1830 | CONFIG_TRACE_IRQFLAGS=y | ||
| 1831 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1832 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1833 | CONFIG_STACKTRACE=y | ||
| 1834 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1835 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1836 | # CONFIG_DEBUG_INFO is not set | ||
| 1837 | # CONFIG_DEBUG_VM is not set | ||
| 1838 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1839 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1840 | # CONFIG_DEBUG_LIST is not set | ||
| 1841 | # CONFIG_DEBUG_SG is not set | ||
| 1842 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1843 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 1844 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1845 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1846 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1847 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1848 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1849 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 1850 | # CONFIG_FAULT_INJECTION is not set | ||
| 1851 | # CONFIG_LATENCYTOP is not set | ||
| 1852 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1853 | # CONFIG_PAGE_POISONING is not set | ||
| 1854 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1855 | CONFIG_TRACING_SUPPORT=y | ||
| 1856 | # CONFIG_FTRACE is not set | ||
| 1857 | # CONFIG_DYNAMIC_DEBUG is not set | ||
| 1504 | # CONFIG_SAMPLES is not set | 1858 | # CONFIG_SAMPLES is not set |
| 1505 | # CONFIG_DEBUG_USER is not set | 1859 | CONFIG_HAVE_ARCH_KGDB=y |
| 1860 | # CONFIG_KGDB is not set | ||
| 1861 | CONFIG_ARM_UNWIND=y | ||
| 1862 | CONFIG_DEBUG_USER=y | ||
| 1863 | CONFIG_DEBUG_ERRORS=y | ||
| 1864 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1865 | # CONFIG_DEBUG_LL is not set | ||
| 1506 | 1866 | ||
| 1507 | # | 1867 | # |
| 1508 | # Security options | 1868 | # Security options |
| 1509 | # | 1869 | # |
| 1510 | # CONFIG_KEYS is not set | 1870 | # CONFIG_KEYS is not set |
| 1511 | # CONFIG_SECURITY is not set | 1871 | # CONFIG_SECURITY is not set |
| 1872 | # CONFIG_SECURITYFS is not set | ||
| 1512 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1873 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1513 | CONFIG_CRYPTO=y | 1874 | CONFIG_CRYPTO=y |
| 1514 | 1875 | ||
| @@ -1516,12 +1877,20 @@ CONFIG_CRYPTO=y | |||
| 1516 | # Crypto core or helper | 1877 | # Crypto core or helper |
| 1517 | # | 1878 | # |
| 1518 | CONFIG_CRYPTO_ALGAPI=m | 1879 | CONFIG_CRYPTO_ALGAPI=m |
| 1880 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1519 | CONFIG_CRYPTO_AEAD=m | 1881 | CONFIG_CRYPTO_AEAD=m |
| 1882 | CONFIG_CRYPTO_AEAD2=m | ||
| 1520 | CONFIG_CRYPTO_BLKCIPHER=m | 1883 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1884 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1521 | CONFIG_CRYPTO_HASH=m | 1885 | CONFIG_CRYPTO_HASH=m |
| 1886 | CONFIG_CRYPTO_HASH2=m | ||
| 1887 | CONFIG_CRYPTO_RNG2=m | ||
| 1888 | CONFIG_CRYPTO_PCOMP=m | ||
| 1522 | CONFIG_CRYPTO_MANAGER=m | 1889 | CONFIG_CRYPTO_MANAGER=m |
| 1890 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1523 | CONFIG_CRYPTO_GF128MUL=m | 1891 | CONFIG_CRYPTO_GF128MUL=m |
| 1524 | CONFIG_CRYPTO_NULL=m | 1892 | CONFIG_CRYPTO_NULL=m |
| 1893 | CONFIG_CRYPTO_WORKQUEUE=m | ||
| 1525 | CONFIG_CRYPTO_CRYPTD=m | 1894 | CONFIG_CRYPTO_CRYPTD=m |
| 1526 | CONFIG_CRYPTO_AUTHENC=m | 1895 | CONFIG_CRYPTO_AUTHENC=m |
| 1527 | CONFIG_CRYPTO_TEST=m | 1896 | CONFIG_CRYPTO_TEST=m |
| @@ -1549,14 +1918,20 @@ CONFIG_CRYPTO_XTS=m | |||
| 1549 | # | 1918 | # |
| 1550 | CONFIG_CRYPTO_HMAC=m | 1919 | CONFIG_CRYPTO_HMAC=m |
| 1551 | CONFIG_CRYPTO_XCBC=m | 1920 | CONFIG_CRYPTO_XCBC=m |
| 1921 | CONFIG_CRYPTO_VMAC=m | ||
| 1552 | 1922 | ||
| 1553 | # | 1923 | # |
| 1554 | # Digest | 1924 | # Digest |
| 1555 | # | 1925 | # |
| 1556 | CONFIG_CRYPTO_CRC32C=m | 1926 | CONFIG_CRYPTO_CRC32C=m |
| 1927 | CONFIG_CRYPTO_GHASH=m | ||
| 1557 | CONFIG_CRYPTO_MD4=m | 1928 | CONFIG_CRYPTO_MD4=m |
| 1558 | CONFIG_CRYPTO_MD5=m | 1929 | CONFIG_CRYPTO_MD5=m |
| 1559 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1930 | CONFIG_CRYPTO_MICHAEL_MIC=m |
| 1931 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1932 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1933 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1934 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1560 | CONFIG_CRYPTO_SHA1=m | 1935 | CONFIG_CRYPTO_SHA1=m |
| 1561 | CONFIG_CRYPTO_SHA256=m | 1936 | CONFIG_CRYPTO_SHA256=m |
| 1562 | CONFIG_CRYPTO_SHA512=m | 1937 | CONFIG_CRYPTO_SHA512=m |
| @@ -1587,28 +1962,40 @@ CONFIG_CRYPTO_TWOFISH_COMMON=m | |||
| 1587 | # Compression | 1962 | # Compression |
| 1588 | # | 1963 | # |
| 1589 | CONFIG_CRYPTO_DEFLATE=m | 1964 | CONFIG_CRYPTO_DEFLATE=m |
| 1965 | # CONFIG_CRYPTO_ZLIB is not set | ||
| 1590 | # CONFIG_CRYPTO_LZO is not set | 1966 | # CONFIG_CRYPTO_LZO is not set |
| 1967 | |||
| 1968 | # | ||
| 1969 | # Random Number Generation | ||
| 1970 | # | ||
| 1971 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1591 | CONFIG_CRYPTO_HW=y | 1972 | CONFIG_CRYPTO_HW=y |
| 1973 | # CONFIG_BINARY_PRINTF is not set | ||
| 1592 | 1974 | ||
| 1593 | # | 1975 | # |
| 1594 | # Library routines | 1976 | # Library routines |
| 1595 | # | 1977 | # |
| 1596 | CONFIG_BITREVERSE=y | 1978 | CONFIG_BITREVERSE=y |
| 1597 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 1979 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 1598 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 1599 | CONFIG_CRC_CCITT=m | 1980 | CONFIG_CRC_CCITT=m |
| 1600 | CONFIG_CRC16=m | 1981 | CONFIG_CRC16=y |
| 1601 | # CONFIG_CRC_ITU_T is not set | 1982 | # CONFIG_CRC_T10DIF is not set |
| 1983 | CONFIG_CRC_ITU_T=y | ||
| 1602 | CONFIG_CRC32=y | 1984 | CONFIG_CRC32=y |
| 1603 | # CONFIG_CRC7 is not set | 1985 | CONFIG_CRC7=y |
| 1604 | CONFIG_LIBCRC32C=m | 1986 | CONFIG_LIBCRC32C=m |
| 1605 | CONFIG_ZLIB_INFLATE=m | 1987 | CONFIG_ZLIB_INFLATE=y |
| 1606 | CONFIG_ZLIB_DEFLATE=m | 1988 | CONFIG_ZLIB_DEFLATE=m |
| 1989 | CONFIG_LZO_COMPRESS=m | ||
| 1990 | CONFIG_LZO_DECOMPRESS=m | ||
| 1991 | CONFIG_DECOMPRESS_GZIP=y | ||
| 1992 | CONFIG_DECOMPRESS_BZIP2=y | ||
| 1993 | CONFIG_DECOMPRESS_LZMA=y | ||
| 1607 | CONFIG_TEXTSEARCH=y | 1994 | CONFIG_TEXTSEARCH=y |
| 1608 | CONFIG_TEXTSEARCH_KMP=m | 1995 | CONFIG_TEXTSEARCH_KMP=m |
| 1609 | CONFIG_TEXTSEARCH_BM=m | 1996 | CONFIG_TEXTSEARCH_BM=m |
| 1610 | CONFIG_TEXTSEARCH_FSM=m | 1997 | CONFIG_TEXTSEARCH_FSM=m |
| 1611 | CONFIG_PLIST=y | ||
| 1612 | CONFIG_HAS_IOMEM=y | 1998 | CONFIG_HAS_IOMEM=y |
| 1613 | CONFIG_HAS_IOPORT=y | 1999 | CONFIG_HAS_IOPORT=y |
| 1614 | CONFIG_HAS_DMA=y | 2000 | CONFIG_HAS_DMA=y |
| 2001 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig index a4f9a2a8149c..7734ccab2119 100644 --- a/arch/arm/configs/mx3_defconfig +++ b/arch/arm/configs/mx3_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.31-rc4 | 3 | # Linux kernel version: 2.6.32-rc5 |
| 4 | # Tue Jul 28 14:11:34 2009 | 4 | # Sun Nov 1 22:56:24 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_HAVE_PWM=y | 7 | CONFIG_HAVE_PWM=y |
| @@ -9,7 +9,6 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y | |||
| 9 | CONFIG_GENERIC_GPIO=y | 9 | CONFIG_GENERIC_GPIO=y |
| 10 | CONFIG_GENERIC_TIME=y | 10 | CONFIG_GENERIC_TIME=y |
| 11 | CONFIG_GENERIC_CLOCKEVENTS=y | 11 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 12 | CONFIG_MMU=y | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y |
| @@ -46,11 +45,12 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 46 | # | 45 | # |
| 47 | # RCU Subsystem | 46 | # RCU Subsystem |
| 48 | # | 47 | # |
| 49 | CONFIG_CLASSIC_RCU=y | 48 | CONFIG_TREE_RCU=y |
| 50 | # CONFIG_TREE_RCU is not set | 49 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 51 | # CONFIG_PREEMPT_RCU is not set | 50 | # CONFIG_RCU_TRACE is not set |
| 51 | CONFIG_RCU_FANOUT=32 | ||
| 52 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | 53 | # CONFIG_TREE_RCU_TRACE is not set |
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | CONFIG_IKCONFIG=y | 54 | CONFIG_IKCONFIG=y |
| 55 | CONFIG_IKCONFIG_PROC=y | 55 | CONFIG_IKCONFIG_PROC=y |
| 56 | CONFIG_LOG_BUF_SHIFT=14 | 56 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -87,16 +87,14 @@ CONFIG_SHMEM=y | |||
| 87 | CONFIG_AIO=y | 87 | CONFIG_AIO=y |
| 88 | 88 | ||
| 89 | # | 89 | # |
| 90 | # Performance Counters | 90 | # Kernel Performance Events And Counters |
| 91 | # | 91 | # |
| 92 | CONFIG_VM_EVENT_COUNTERS=y | 92 | CONFIG_VM_EVENT_COUNTERS=y |
| 93 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 94 | CONFIG_COMPAT_BRK=y | 93 | CONFIG_COMPAT_BRK=y |
| 95 | CONFIG_SLAB=y | 94 | CONFIG_SLAB=y |
| 96 | # CONFIG_SLUB is not set | 95 | # CONFIG_SLUB is not set |
| 97 | # CONFIG_SLOB is not set | 96 | # CONFIG_SLOB is not set |
| 98 | # CONFIG_PROFILING is not set | 97 | # CONFIG_PROFILING is not set |
| 99 | # CONFIG_MARKERS is not set | ||
| 100 | CONFIG_HAVE_OPROFILE=y | 98 | CONFIG_HAVE_OPROFILE=y |
| 101 | # CONFIG_KPROBES is not set | 99 | # CONFIG_KPROBES is not set |
| 102 | CONFIG_HAVE_KPROBES=y | 100 | CONFIG_HAVE_KPROBES=y |
| @@ -139,6 +137,7 @@ CONFIG_FREEZER=y | |||
| 139 | # | 137 | # |
| 140 | # System Type | 138 | # System Type |
| 141 | # | 139 | # |
| 140 | CONFIG_MMU=y | ||
| 142 | # CONFIG_ARCH_AAEC2000 is not set | 141 | # CONFIG_ARCH_AAEC2000 is not set |
| 143 | # CONFIG_ARCH_INTEGRATOR is not set | 142 | # CONFIG_ARCH_INTEGRATOR is not set |
| 144 | # CONFIG_ARCH_REALVIEW is not set | 143 | # CONFIG_ARCH_REALVIEW is not set |
| @@ -153,6 +152,7 @@ CONFIG_ARCH_MXC=y | |||
| 153 | # CONFIG_ARCH_STMP3XXX is not set | 152 | # CONFIG_ARCH_STMP3XXX is not set |
| 154 | # CONFIG_ARCH_NETX is not set | 153 | # CONFIG_ARCH_NETX is not set |
| 155 | # CONFIG_ARCH_H720X is not set | 154 | # CONFIG_ARCH_H720X is not set |
| 155 | # CONFIG_ARCH_NOMADIK is not set | ||
| 156 | # CONFIG_ARCH_IOP13XX is not set | 156 | # CONFIG_ARCH_IOP13XX is not set |
| 157 | # CONFIG_ARCH_IOP32X is not set | 157 | # CONFIG_ARCH_IOP32X is not set |
| 158 | # CONFIG_ARCH_IOP33X is not set | 158 | # CONFIG_ARCH_IOP33X is not set |
| @@ -175,18 +175,22 @@ CONFIG_ARCH_MXC=y | |||
| 175 | # CONFIG_ARCH_SA1100 is not set | 175 | # CONFIG_ARCH_SA1100 is not set |
| 176 | # CONFIG_ARCH_S3C2410 is not set | 176 | # CONFIG_ARCH_S3C2410 is not set |
| 177 | # CONFIG_ARCH_S3C64XX is not set | 177 | # CONFIG_ARCH_S3C64XX is not set |
| 178 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 178 | # CONFIG_ARCH_SHARK is not set | 179 | # CONFIG_ARCH_SHARK is not set |
| 179 | # CONFIG_ARCH_LH7A40X is not set | 180 | # CONFIG_ARCH_LH7A40X is not set |
| 180 | # CONFIG_ARCH_U300 is not set | 181 | # CONFIG_ARCH_U300 is not set |
| 181 | # CONFIG_ARCH_DAVINCI is not set | 182 | # CONFIG_ARCH_DAVINCI is not set |
| 182 | # CONFIG_ARCH_OMAP is not set | 183 | # CONFIG_ARCH_OMAP is not set |
| 184 | # CONFIG_ARCH_BCMRING is not set | ||
| 183 | 185 | ||
| 184 | # | 186 | # |
| 185 | # Freescale MXC Implementations | 187 | # Freescale MXC Implementations |
| 186 | # | 188 | # |
| 187 | # CONFIG_ARCH_MX1 is not set | 189 | # CONFIG_ARCH_MX1 is not set |
| 188 | # CONFIG_ARCH_MX2 is not set | 190 | # CONFIG_ARCH_MX2 is not set |
| 191 | # CONFIG_ARCH_MX25 is not set | ||
| 189 | CONFIG_ARCH_MX3=y | 192 | CONFIG_ARCH_MX3=y |
| 193 | # CONFIG_ARCH_MXC91231 is not set | ||
| 190 | CONFIG_ARCH_MX31=y | 194 | CONFIG_ARCH_MX31=y |
| 191 | CONFIG_ARCH_MX35=y | 195 | CONFIG_ARCH_MX35=y |
| 192 | 196 | ||
| @@ -205,6 +209,7 @@ CONFIG_MACH_QONG=y | |||
| 205 | CONFIG_MACH_PCM043=y | 209 | CONFIG_MACH_PCM043=y |
| 206 | CONFIG_MACH_ARMADILLO5X0=y | 210 | CONFIG_MACH_ARMADILLO5X0=y |
| 207 | CONFIG_MACH_MX35_3DS=y | 211 | CONFIG_MACH_MX35_3DS=y |
| 212 | CONFIG_MACH_KZM_ARM11_01=y | ||
| 208 | CONFIG_MXC_IRQ_PRIOR=y | 213 | CONFIG_MXC_IRQ_PRIOR=y |
| 209 | CONFIG_MXC_PWM=y | 214 | CONFIG_MXC_PWM=y |
| 210 | CONFIG_ARCH_HAS_RNGA=y | 215 | CONFIG_ARCH_HAS_RNGA=y |
| @@ -218,7 +223,7 @@ CONFIG_CPU_V6=y | |||
| 218 | # CONFIG_CPU_32v6K is not set | 223 | # CONFIG_CPU_32v6K is not set |
| 219 | CONFIG_CPU_32v6=y | 224 | CONFIG_CPU_32v6=y |
| 220 | CONFIG_CPU_ABRT_EV6=y | 225 | CONFIG_CPU_ABRT_EV6=y |
| 221 | CONFIG_CPU_PABRT_NOIFAR=y | 226 | CONFIG_CPU_PABRT_V6=y |
| 222 | CONFIG_CPU_CACHE_V6=y | 227 | CONFIG_CPU_CACHE_V6=y |
| 223 | CONFIG_CPU_CACHE_VIPT=y | 228 | CONFIG_CPU_CACHE_VIPT=y |
| 224 | CONFIG_CPU_COPY_V6=y | 229 | CONFIG_CPU_COPY_V6=y |
| @@ -236,6 +241,7 @@ CONFIG_ARM_THUMB=y | |||
| 236 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 241 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 237 | CONFIG_OUTER_CACHE=y | 242 | CONFIG_OUTER_CACHE=y |
| 238 | CONFIG_CACHE_L2X0=y | 243 | CONFIG_CACHE_L2X0=y |
| 244 | CONFIG_ARM_L1_CACHE_SHIFT=5 | ||
| 239 | # CONFIG_ARM_ERRATA_411920 is not set | 245 | # CONFIG_ARM_ERRATA_411920 is not set |
| 240 | CONFIG_COMMON_CLKDEV=y | 246 | CONFIG_COMMON_CLKDEV=y |
| 241 | 247 | ||
| @@ -257,6 +263,8 @@ CONFIG_VMSPLIT_3G=y | |||
| 257 | # CONFIG_VMSPLIT_2G is not set | 263 | # CONFIG_VMSPLIT_2G is not set |
| 258 | # CONFIG_VMSPLIT_1G is not set | 264 | # CONFIG_VMSPLIT_1G is not set |
| 259 | CONFIG_PAGE_OFFSET=0xC0000000 | 265 | CONFIG_PAGE_OFFSET=0xC0000000 |
| 266 | # CONFIG_PREEMPT_NONE is not set | ||
| 267 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 260 | CONFIG_PREEMPT=y | 268 | CONFIG_PREEMPT=y |
| 261 | CONFIG_HZ=100 | 269 | CONFIG_HZ=100 |
| 262 | CONFIG_AEABI=y | 270 | CONFIG_AEABI=y |
| @@ -277,6 +285,7 @@ CONFIG_ZONE_DMA_FLAG=0 | |||
| 277 | CONFIG_VIRT_TO_BUS=y | 285 | CONFIG_VIRT_TO_BUS=y |
| 278 | CONFIG_HAVE_MLOCK=y | 286 | CONFIG_HAVE_MLOCK=y |
| 279 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | 287 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y |
| 288 | # CONFIG_KSM is not set | ||
| 280 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | 289 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 |
| 281 | CONFIG_ALIGNMENT_TRAP=y | 290 | CONFIG_ALIGNMENT_TRAP=y |
| 282 | # CONFIG_UACCESS_WITH_MEMCPY is not set | 291 | # CONFIG_UACCESS_WITH_MEMCPY is not set |
| @@ -326,6 +335,7 @@ CONFIG_PM_SLEEP=y | |||
| 326 | CONFIG_SUSPEND=y | 335 | CONFIG_SUSPEND=y |
| 327 | CONFIG_SUSPEND_FREEZER=y | 336 | CONFIG_SUSPEND_FREEZER=y |
| 328 | # CONFIG_APM_EMULATION is not set | 337 | # CONFIG_APM_EMULATION is not set |
| 338 | # CONFIG_PM_RUNTIME is not set | ||
| 329 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 339 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 330 | CONFIG_NET=y | 340 | CONFIG_NET=y |
| 331 | 341 | ||
| @@ -367,6 +377,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 367 | # CONFIG_NETFILTER is not set | 377 | # CONFIG_NETFILTER is not set |
| 368 | # CONFIG_IP_DCCP is not set | 378 | # CONFIG_IP_DCCP is not set |
| 369 | # CONFIG_IP_SCTP is not set | 379 | # CONFIG_IP_SCTP is not set |
| 380 | # CONFIG_RDS is not set | ||
| 370 | # CONFIG_TIPC is not set | 381 | # CONFIG_TIPC is not set |
| 371 | # CONFIG_ATM is not set | 382 | # CONFIG_ATM is not set |
| 372 | # CONFIG_BRIDGE is not set | 383 | # CONFIG_BRIDGE is not set |
| @@ -407,6 +418,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 407 | # Generic Driver Options | 418 | # Generic Driver Options |
| 408 | # | 419 | # |
| 409 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 420 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 421 | # CONFIG_DEVTMPFS is not set | ||
| 410 | CONFIG_STANDALONE=y | 422 | CONFIG_STANDALONE=y |
| 411 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 423 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 412 | CONFIG_FW_LOADER=m | 424 | CONFIG_FW_LOADER=m |
| @@ -416,9 +428,9 @@ CONFIG_EXTRA_FIRMWARE="" | |||
| 416 | # CONFIG_CONNECTOR is not set | 428 | # CONFIG_CONNECTOR is not set |
| 417 | CONFIG_MTD=y | 429 | CONFIG_MTD=y |
| 418 | # CONFIG_MTD_DEBUG is not set | 430 | # CONFIG_MTD_DEBUG is not set |
| 431 | # CONFIG_MTD_TESTS is not set | ||
| 419 | # CONFIG_MTD_CONCAT is not set | 432 | # CONFIG_MTD_CONCAT is not set |
| 420 | CONFIG_MTD_PARTITIONS=y | 433 | CONFIG_MTD_PARTITIONS=y |
| 421 | # CONFIG_MTD_TESTS is not set | ||
| 422 | # CONFIG_MTD_REDBOOT_PARTS is not set | 434 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 423 | CONFIG_MTD_CMDLINE_PARTS=y | 435 | CONFIG_MTD_CMDLINE_PARTS=y |
| 424 | # CONFIG_MTD_AFS_PARTS is not set | 436 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -587,14 +599,12 @@ CONFIG_DNET=y | |||
| 587 | # CONFIG_B44 is not set | 599 | # CONFIG_B44 is not set |
| 588 | # CONFIG_CS89x0 is not set | 600 | # CONFIG_CS89x0 is not set |
| 589 | # CONFIG_KS8842 is not set | 601 | # CONFIG_KS8842 is not set |
| 602 | # CONFIG_KS8851_MLL is not set | ||
| 590 | CONFIG_FEC=y | 603 | CONFIG_FEC=y |
| 591 | # CONFIG_FEC2 is not set | 604 | # CONFIG_FEC2 is not set |
| 592 | # CONFIG_NETDEV_1000 is not set | 605 | # CONFIG_NETDEV_1000 is not set |
| 593 | # CONFIG_NETDEV_10000 is not set | 606 | # CONFIG_NETDEV_10000 is not set |
| 594 | 607 | CONFIG_WLAN=y | |
| 595 | # | ||
| 596 | # Wireless LAN | ||
| 597 | # | ||
| 598 | # CONFIG_WLAN_PRE80211 is not set | 608 | # CONFIG_WLAN_PRE80211 is not set |
| 599 | # CONFIG_WLAN_80211 is not set | 609 | # CONFIG_WLAN_80211 is not set |
| 600 | 610 | ||
| @@ -608,6 +618,7 @@ CONFIG_FEC=y | |||
| 608 | # CONFIG_NETPOLL is not set | 618 | # CONFIG_NETPOLL is not set |
| 609 | # CONFIG_NET_POLL_CONTROLLER is not set | 619 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 610 | # CONFIG_ISDN is not set | 620 | # CONFIG_ISDN is not set |
| 621 | # CONFIG_PHONE is not set | ||
| 611 | 622 | ||
| 612 | # | 623 | # |
| 613 | # Input device support | 624 | # Input device support |
| @@ -630,7 +641,14 @@ CONFIG_DEVKMEM=y | |||
| 630 | # | 641 | # |
| 631 | # Serial drivers | 642 | # Serial drivers |
| 632 | # | 643 | # |
| 633 | # CONFIG_SERIAL_8250 is not set | 644 | CONFIG_SERIAL_8250=m |
| 645 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 646 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 647 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 648 | # CONFIG_SERIAL_8250_MANY_PORTS is not set | ||
| 649 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 650 | # CONFIG_SERIAL_8250_DETECT_IRQ is not set | ||
| 651 | # CONFIG_SERIAL_8250_RSA is not set | ||
| 634 | 652 | ||
| 635 | # | 653 | # |
| 636 | # Non-8250 serial port support | 654 | # Non-8250 serial port support |
| @@ -649,6 +667,7 @@ CONFIG_UNIX98_PTYS=y | |||
| 649 | # CONFIG_TCG_TPM is not set | 667 | # CONFIG_TCG_TPM is not set |
| 650 | CONFIG_I2C=y | 668 | CONFIG_I2C=y |
| 651 | CONFIG_I2C_BOARDINFO=y | 669 | CONFIG_I2C_BOARDINFO=y |
| 670 | CONFIG_I2C_COMPAT=y | ||
| 652 | CONFIG_I2C_CHARDEV=y | 671 | CONFIG_I2C_CHARDEV=y |
| 653 | CONFIG_I2C_HELPER_AUTO=y | 672 | CONFIG_I2C_HELPER_AUTO=y |
| 654 | 673 | ||
| @@ -681,15 +700,17 @@ CONFIG_I2C_IMX=y | |||
| 681 | # Miscellaneous I2C Chip support | 700 | # Miscellaneous I2C Chip support |
| 682 | # | 701 | # |
| 683 | # CONFIG_DS1682 is not set | 702 | # CONFIG_DS1682 is not set |
| 684 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 685 | # CONFIG_PCF8575 is not set | ||
| 686 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 687 | # CONFIG_SENSORS_TSL2550 is not set | 703 | # CONFIG_SENSORS_TSL2550 is not set |
| 688 | # CONFIG_I2C_DEBUG_CORE is not set | 704 | # CONFIG_I2C_DEBUG_CORE is not set |
| 689 | # CONFIG_I2C_DEBUG_ALGO is not set | 705 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 690 | # CONFIG_I2C_DEBUG_BUS is not set | 706 | # CONFIG_I2C_DEBUG_BUS is not set |
| 691 | # CONFIG_I2C_DEBUG_CHIP is not set | 707 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 692 | # CONFIG_SPI is not set | 708 | # CONFIG_SPI is not set |
| 709 | |||
| 710 | # | ||
| 711 | # PPS support | ||
| 712 | # | ||
| 713 | # CONFIG_PPS is not set | ||
| 693 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 714 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 694 | CONFIG_GPIOLIB=y | 715 | CONFIG_GPIOLIB=y |
| 695 | # CONFIG_GPIO_SYSFS is not set | 716 | # CONFIG_GPIO_SYSFS is not set |
| @@ -712,6 +733,10 @@ CONFIG_GPIOLIB=y | |||
| 712 | # | 733 | # |
| 713 | # SPI GPIO expanders: | 734 | # SPI GPIO expanders: |
| 714 | # | 735 | # |
| 736 | |||
| 737 | # | ||
| 738 | # AC97 GPIO expanders: | ||
| 739 | # | ||
| 715 | CONFIG_W1=y | 740 | CONFIG_W1=y |
| 716 | 741 | ||
| 717 | # | 742 | # |
| @@ -734,7 +759,6 @@ CONFIG_W1_SLAVE_THERM=y | |||
| 734 | # CONFIG_POWER_SUPPLY is not set | 759 | # CONFIG_POWER_SUPPLY is not set |
| 735 | # CONFIG_HWMON is not set | 760 | # CONFIG_HWMON is not set |
| 736 | # CONFIG_THERMAL is not set | 761 | # CONFIG_THERMAL is not set |
| 737 | # CONFIG_THERMAL_HWMON is not set | ||
| 738 | # CONFIG_WATCHDOG is not set | 762 | # CONFIG_WATCHDOG is not set |
| 739 | CONFIG_SSB_POSSIBLE=y | 763 | CONFIG_SSB_POSSIBLE=y |
| 740 | 764 | ||
| @@ -759,12 +783,24 @@ CONFIG_SSB_POSSIBLE=y | |||
| 759 | # CONFIG_MFD_TC6393XB is not set | 783 | # CONFIG_MFD_TC6393XB is not set |
| 760 | # CONFIG_PMIC_DA903X is not set | 784 | # CONFIG_PMIC_DA903X is not set |
| 761 | # CONFIG_MFD_WM8400 is not set | 785 | # CONFIG_MFD_WM8400 is not set |
| 786 | # CONFIG_MFD_WM831X is not set | ||
| 762 | CONFIG_MFD_WM8350=y | 787 | CONFIG_MFD_WM8350=y |
| 763 | CONFIG_MFD_WM8350_CONFIG_MODE_0=y | 788 | CONFIG_MFD_WM8350_CONFIG_MODE_0=y |
| 764 | CONFIG_MFD_WM8352_CONFIG_MODE_0=y | 789 | CONFIG_MFD_WM8352_CONFIG_MODE_0=y |
| 765 | CONFIG_MFD_WM8350_I2C=y | 790 | CONFIG_MFD_WM8350_I2C=y |
| 766 | # CONFIG_MFD_PCF50633 is not set | 791 | # CONFIG_MFD_PCF50633 is not set |
| 767 | # CONFIG_AB3100_CORE is not set | 792 | # CONFIG_AB3100_CORE is not set |
| 793 | CONFIG_REGULATOR=y | ||
| 794 | # CONFIG_REGULATOR_DEBUG is not set | ||
| 795 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 796 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 797 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | ||
| 798 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 799 | # CONFIG_REGULATOR_MAX1586 is not set | ||
| 800 | CONFIG_REGULATOR_WM8350=y | ||
| 801 | # CONFIG_REGULATOR_LP3971 is not set | ||
| 802 | # CONFIG_REGULATOR_TPS65023 is not set | ||
| 803 | # CONFIG_REGULATOR_TPS6507X is not set | ||
| 768 | CONFIG_MEDIA_SUPPORT=y | 804 | CONFIG_MEDIA_SUPPORT=y |
| 769 | 805 | ||
| 770 | # | 806 | # |
| @@ -874,10 +910,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 874 | # MMC/SD/SDIO Host Controller Drivers | 910 | # MMC/SD/SDIO Host Controller Drivers |
| 875 | # | 911 | # |
| 876 | # CONFIG_MMC_SDHCI is not set | 912 | # CONFIG_MMC_SDHCI is not set |
| 913 | # CONFIG_MMC_AT91 is not set | ||
| 914 | # CONFIG_MMC_ATMELMCI is not set | ||
| 877 | CONFIG_MMC_MXC=y | 915 | CONFIG_MMC_MXC=y |
| 878 | # CONFIG_MEMSTICK is not set | 916 | # CONFIG_MEMSTICK is not set |
| 879 | # CONFIG_ACCESSIBILITY is not set | ||
| 880 | # CONFIG_NEW_LEDS is not set | 917 | # CONFIG_NEW_LEDS is not set |
| 918 | # CONFIG_ACCESSIBILITY is not set | ||
| 881 | CONFIG_RTC_LIB=y | 919 | CONFIG_RTC_LIB=y |
| 882 | # CONFIG_RTC_CLASS is not set | 920 | # CONFIG_RTC_CLASS is not set |
| 883 | CONFIG_DMADEVICES=y | 921 | CONFIG_DMADEVICES=y |
| @@ -896,16 +934,11 @@ CONFIG_DMA_ENGINE=y | |||
| 896 | # CONFIG_ASYNC_TX_DMA is not set | 934 | # CONFIG_ASYNC_TX_DMA is not set |
| 897 | # CONFIG_DMATEST is not set | 935 | # CONFIG_DMATEST is not set |
| 898 | # CONFIG_AUXDISPLAY is not set | 936 | # CONFIG_AUXDISPLAY is not set |
| 899 | CONFIG_REGULATOR=y | ||
| 900 | # CONFIG_REGULATOR_DEBUG is not set | ||
| 901 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 902 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 903 | # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set | ||
| 904 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 905 | # CONFIG_REGULATOR_MAX1586 is not set | ||
| 906 | CONFIG_REGULATOR_WM8350=y | ||
| 907 | # CONFIG_REGULATOR_LP3971 is not set | ||
| 908 | # CONFIG_UIO is not set | 937 | # CONFIG_UIO is not set |
| 938 | |||
| 939 | # | ||
| 940 | # TI VLYNQ | ||
| 941 | # | ||
| 909 | # CONFIG_STAGING is not set | 942 | # CONFIG_STAGING is not set |
| 910 | 943 | ||
| 911 | # | 944 | # |
| @@ -921,6 +954,7 @@ CONFIG_REGULATOR_WM8350=y | |||
| 921 | # CONFIG_GFS2_FS is not set | 954 | # CONFIG_GFS2_FS is not set |
| 922 | # CONFIG_OCFS2_FS is not set | 955 | # CONFIG_OCFS2_FS is not set |
| 923 | # CONFIG_BTRFS_FS is not set | 956 | # CONFIG_BTRFS_FS is not set |
| 957 | # CONFIG_NILFS2_FS is not set | ||
| 924 | CONFIG_FILE_LOCKING=y | 958 | CONFIG_FILE_LOCKING=y |
| 925 | CONFIG_FSNOTIFY=y | 959 | CONFIG_FSNOTIFY=y |
| 926 | # CONFIG_DNOTIFY is not set | 960 | # CONFIG_DNOTIFY is not set |
| @@ -995,7 +1029,6 @@ CONFIG_UBIFS_FS_ZLIB=y | |||
| 995 | # CONFIG_ROMFS_FS is not set | 1029 | # CONFIG_ROMFS_FS is not set |
| 996 | # CONFIG_SYSV_FS is not set | 1030 | # CONFIG_SYSV_FS is not set |
| 997 | # CONFIG_UFS_FS is not set | 1031 | # CONFIG_UFS_FS is not set |
| 998 | # CONFIG_NILFS2_FS is not set | ||
| 999 | CONFIG_NETWORK_FILESYSTEMS=y | 1032 | CONFIG_NETWORK_FILESYSTEMS=y |
| 1000 | CONFIG_NFS_FS=y | 1033 | CONFIG_NFS_FS=y |
| 1001 | CONFIG_NFS_V3=y | 1034 | CONFIG_NFS_V3=y |
| @@ -1033,6 +1066,7 @@ CONFIG_MSDOS_PARTITION=y | |||
| 1033 | # CONFIG_ENABLE_MUST_CHECK is not set | 1066 | # CONFIG_ENABLE_MUST_CHECK is not set |
| 1034 | CONFIG_FRAME_WARN=1024 | 1067 | CONFIG_FRAME_WARN=1024 |
| 1035 | # CONFIG_MAGIC_SYSRQ is not set | 1068 | # CONFIG_MAGIC_SYSRQ is not set |
| 1069 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 1036 | # CONFIG_UNUSED_SYMBOLS is not set | 1070 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1037 | # CONFIG_DEBUG_FS is not set | 1071 | # CONFIG_DEBUG_FS is not set |
| 1038 | # CONFIG_HEADERS_CHECK is not set | 1072 | # CONFIG_HEADERS_CHECK is not set |
| @@ -1062,7 +1096,6 @@ CONFIG_CRYPTO=y | |||
| 1062 | # | 1096 | # |
| 1063 | # Crypto core or helper | 1097 | # Crypto core or helper |
| 1064 | # | 1098 | # |
| 1065 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1066 | CONFIG_CRYPTO_ALGAPI=y | 1099 | CONFIG_CRYPTO_ALGAPI=y |
| 1067 | CONFIG_CRYPTO_ALGAPI2=y | 1100 | CONFIG_CRYPTO_ALGAPI2=y |
| 1068 | CONFIG_CRYPTO_AEAD2=y | 1101 | CONFIG_CRYPTO_AEAD2=y |
| @@ -1104,11 +1137,13 @@ CONFIG_CRYPTO_CBC=y | |||
| 1104 | # | 1137 | # |
| 1105 | # CONFIG_CRYPTO_HMAC is not set | 1138 | # CONFIG_CRYPTO_HMAC is not set |
| 1106 | # CONFIG_CRYPTO_XCBC is not set | 1139 | # CONFIG_CRYPTO_XCBC is not set |
| 1140 | # CONFIG_CRYPTO_VMAC is not set | ||
| 1107 | 1141 | ||
| 1108 | # | 1142 | # |
| 1109 | # Digest | 1143 | # Digest |
| 1110 | # | 1144 | # |
| 1111 | # CONFIG_CRYPTO_CRC32C is not set | 1145 | # CONFIG_CRYPTO_CRC32C is not set |
| 1146 | # CONFIG_CRYPTO_GHASH is not set | ||
| 1112 | # CONFIG_CRYPTO_MD4 is not set | 1147 | # CONFIG_CRYPTO_MD4 is not set |
| 1113 | CONFIG_CRYPTO_MD5=y | 1148 | CONFIG_CRYPTO_MD5=y |
| 1114 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1149 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h new file mode 100644 index 000000000000..538f17ca905b --- /dev/null +++ b/arch/arm/include/asm/hardware/cache-tauros2.h | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/include/asm/hardware/cache-tauros2.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Marvell Semiconductor | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | extern void __init tauros2_init(void); | ||
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h index 8d60ad267e3a..5daea2961d48 100644 --- a/arch/arm/include/asm/hardware/iop3xx.h +++ b/arch/arm/include/asm/hardware/iop3xx.h | |||
| @@ -234,7 +234,13 @@ extern int iop3xx_get_init_atu(void); | |||
| 234 | void iop3xx_map_io(void); | 234 | void iop3xx_map_io(void); |
| 235 | void iop_init_cp6_handler(void); | 235 | void iop_init_cp6_handler(void); |
| 236 | void iop_init_time(unsigned long tickrate); | 236 | void iop_init_time(unsigned long tickrate); |
| 237 | unsigned long iop_gettimeoffset(void); | 237 | |
| 238 | static inline u32 read_tmr0(void) | ||
| 239 | { | ||
| 240 | u32 val; | ||
| 241 | asm volatile("mrc p6, 0, %0, c0, c1, 0" : "=r" (val)); | ||
| 242 | return val; | ||
| 243 | } | ||
| 238 | 244 | ||
| 239 | static inline void write_tmr0(u32 val) | 245 | static inline void write_tmr0(u32 val) |
| 240 | { | 246 | { |
| @@ -253,6 +259,11 @@ static inline u32 read_tcr0(void) | |||
| 253 | return val; | 259 | return val; |
| 254 | } | 260 | } |
| 255 | 261 | ||
| 262 | static inline void write_tcr0(u32 val) | ||
| 263 | { | ||
| 264 | asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); | ||
| 265 | } | ||
| 266 | |||
| 256 | static inline u32 read_tcr1(void) | 267 | static inline u32 read_tcr1(void) |
| 257 | { | 268 | { |
| 258 | u32 val; | 269 | u32 val; |
| @@ -260,6 +271,11 @@ static inline u32 read_tcr1(void) | |||
| 260 | return val; | 271 | return val; |
| 261 | } | 272 | } |
| 262 | 273 | ||
| 274 | static inline void write_tcr1(u32 val) | ||
| 275 | { | ||
| 276 | asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); | ||
| 277 | } | ||
| 278 | |||
| 263 | static inline void write_trr0(u32 val) | 279 | static inline void write_trr0(u32 val) |
| 264 | { | 280 | { |
| 265 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); | 281 | asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); |
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index e5dfc2895e24..573b803dc6bf 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | * numbers for r1. | 32 | * numbers for r1. |
| 33 | * | 33 | * |
| 34 | */ | 34 | */ |
| 35 | .section ".text.head", "ax" | 35 | __HEAD |
| 36 | ENTRY(stext) | 36 | ENTRY(stext) |
| 37 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode | 37 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
| 38 | @ and irqs disabled | 38 | @ and irqs disabled |
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 38ccbe1d3b2c..eb62bf947212 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
| @@ -74,7 +74,7 @@ | |||
| 74 | * crap here - that's what the boot loader (or in extreme, well justified | 74 | * crap here - that's what the boot loader (or in extreme, well justified |
| 75 | * circumstances, zImage) is for. | 75 | * circumstances, zImage) is for. |
| 76 | */ | 76 | */ |
| 77 | .section ".text.head", "ax" | 77 | __HEAD |
| 78 | ENTRY(stext) | 78 | ENTRY(stext) |
| 79 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode | 79 | setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode |
| 80 | @ and irqs disabled | 80 | @ and irqs disabled |
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index aecf87dfbaec..71151bd87a36 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
| @@ -24,13 +24,11 @@ SECTIONS | |||
| 24 | #else | 24 | #else |
| 25 | . = PAGE_OFFSET + TEXT_OFFSET; | 25 | . = PAGE_OFFSET + TEXT_OFFSET; |
| 26 | #endif | 26 | #endif |
| 27 | .text.head : { | ||
| 28 | _stext = .; | ||
| 29 | _sinittext = .; | ||
| 30 | *(.text.head) | ||
| 31 | } | ||
| 32 | 27 | ||
| 33 | .init : { /* Init code and data */ | 28 | .init : { /* Init code and data */ |
| 29 | _stext = .; | ||
| 30 | _sinittext = .; | ||
| 31 | HEAD_TEXT | ||
| 34 | INIT_TEXT | 32 | INIT_TEXT |
| 35 | _einittext = .; | 33 | _einittext = .; |
| 36 | __proc_info_begin = .; | 34 | __proc_info_begin = .; |
| @@ -42,43 +40,31 @@ SECTIONS | |||
| 42 | __tagtable_begin = .; | 40 | __tagtable_begin = .; |
| 43 | *(.taglist.init) | 41 | *(.taglist.init) |
| 44 | __tagtable_end = .; | 42 | __tagtable_end = .; |
| 45 | . = ALIGN(16); | 43 | |
| 46 | __setup_start = .; | 44 | INIT_SETUP(16) |
| 47 | *(.init.setup) | 45 | |
| 48 | __setup_end = .; | ||
| 49 | __early_begin = .; | 46 | __early_begin = .; |
| 50 | *(.early_param.init) | 47 | *(.early_param.init) |
| 51 | __early_end = .; | 48 | __early_end = .; |
| 52 | __initcall_start = .; | 49 | |
| 53 | INITCALLS | 50 | INIT_CALLS |
| 54 | __initcall_end = .; | 51 | CON_INITCALL |
| 55 | __con_initcall_start = .; | 52 | SECURITY_INITCALL |
| 56 | *(.con_initcall.init) | 53 | INIT_RAM_FS |
| 57 | __con_initcall_end = .; | 54 | |
| 58 | __security_initcall_start = .; | ||
| 59 | *(.security_initcall.init) | ||
| 60 | __security_initcall_end = .; | ||
| 61 | #ifdef CONFIG_BLK_DEV_INITRD | ||
| 62 | . = ALIGN(32); | ||
| 63 | __initramfs_start = .; | ||
| 64 | usr/built-in.o(.init.ramfs) | ||
| 65 | __initramfs_end = .; | ||
| 66 | #endif | ||
| 67 | . = ALIGN(PAGE_SIZE); | ||
| 68 | __per_cpu_load = .; | ||
| 69 | __per_cpu_start = .; | ||
| 70 | *(.data.percpu.page_aligned) | ||
| 71 | *(.data.percpu) | ||
| 72 | *(.data.percpu.shared_aligned) | ||
| 73 | __per_cpu_end = .; | ||
| 74 | #ifndef CONFIG_XIP_KERNEL | 55 | #ifndef CONFIG_XIP_KERNEL |
| 75 | __init_begin = _stext; | 56 | __init_begin = _stext; |
| 76 | INIT_DATA | 57 | INIT_DATA |
| 77 | . = ALIGN(PAGE_SIZE); | ||
| 78 | __init_end = .; | ||
| 79 | #endif | 58 | #endif |
| 80 | } | 59 | } |
| 81 | 60 | ||
| 61 | PERCPU(PAGE_SIZE) | ||
| 62 | |||
| 63 | #ifndef CONFIG_XIP_KERNEL | ||
| 64 | . = ALIGN(PAGE_SIZE); | ||
| 65 | __init_end = .; | ||
| 66 | #endif | ||
| 67 | |||
| 82 | /DISCARD/ : { /* Exit code and data */ | 68 | /DISCARD/ : { /* Exit code and data */ |
| 83 | EXIT_TEXT | 69 | EXIT_TEXT |
| 84 | EXIT_DATA | 70 | EXIT_DATA |
| @@ -157,7 +143,7 @@ SECTIONS | |||
| 157 | * first, the init task union, aligned | 143 | * first, the init task union, aligned |
| 158 | * to an 8192 byte boundary. | 144 | * to an 8192 byte boundary. |
| 159 | */ | 145 | */ |
| 160 | *(.data.init_task) | 146 | INIT_TASK_DATA(THREAD_SIZE) |
| 161 | 147 | ||
| 162 | #ifdef CONFIG_XIP_KERNEL | 148 | #ifdef CONFIG_XIP_KERNEL |
| 163 | . = ALIGN(PAGE_SIZE); | 149 | . = ALIGN(PAGE_SIZE); |
| @@ -167,17 +153,8 @@ SECTIONS | |||
| 167 | __init_end = .; | 153 | __init_end = .; |
| 168 | #endif | 154 | #endif |
| 169 | 155 | ||
| 170 | . = ALIGN(PAGE_SIZE); | 156 | NOSAVE_DATA |
| 171 | __nosave_begin = .; | 157 | CACHELINE_ALIGNED_DATA(32) |
| 172 | *(.data.nosave) | ||
| 173 | . = ALIGN(PAGE_SIZE); | ||
| 174 | __nosave_end = .; | ||
| 175 | |||
| 176 | /* | ||
| 177 | * then the cacheline aligned data | ||
| 178 | */ | ||
| 179 | . = ALIGN(32); | ||
| 180 | *(.data.cacheline_aligned) | ||
| 181 | 158 | ||
| 182 | /* | 159 | /* |
| 183 | * The exception fixup table (might need resorting at runtime) | 160 | * The exception fixup table (might need resorting at runtime) |
| @@ -256,20 +233,10 @@ SECTIONS | |||
| 256 | } | 233 | } |
| 257 | #endif | 234 | #endif |
| 258 | 235 | ||
| 259 | .bss : { | 236 | BSS_SECTION(0, 0, 0) |
| 260 | __bss_start = .; /* BSS */ | 237 | _end = .; |
| 261 | *(.bss) | 238 | |
| 262 | *(COMMON) | 239 | STABS_DEBUG |
| 263 | __bss_stop = .; | ||
| 264 | _end = .; | ||
| 265 | } | ||
| 266 | /* Stabs debugging sections. */ | ||
| 267 | .stab 0 : { *(.stab) } | ||
| 268 | .stabstr 0 : { *(.stabstr) } | ||
| 269 | .stab.excl 0 : { *(.stab.excl) } | ||
| 270 | .stab.exclstr 0 : { *(.stab.exclstr) } | ||
| 271 | .stab.index 0 : { *(.stab.index) } | ||
| 272 | .stab.indexstr 0 : { *(.stab.indexstr) } | ||
| 273 | .comment 0 : { *(.comment) } | 240 | .comment 0 : { *(.comment) } |
| 274 | } | 241 | } |
| 275 | 242 | ||
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c71e39ed092f..0b2ee953f164 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -1,5 +1,20 @@ | |||
| 1 | if ARCH_AT91 | 1 | if ARCH_AT91 |
| 2 | 2 | ||
| 3 | config HAVE_AT91_DATAFLASH_CARD | ||
| 4 | bool | ||
| 5 | |||
| 6 | config HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 7 | bool | ||
| 8 | |||
| 9 | config HAVE_AT91_USART3 | ||
| 10 | bool | ||
| 11 | |||
| 12 | config HAVE_AT91_USART4 | ||
| 13 | bool | ||
| 14 | |||
| 15 | config HAVE_AT91_USART5 | ||
| 16 | bool | ||
| 17 | |||
| 3 | menu "Atmel AT91 System-on-Chip" | 18 | menu "Atmel AT91 System-on-Chip" |
| 4 | 19 | ||
| 5 | choice | 20 | choice |
| @@ -10,54 +25,69 @@ config ARCH_AT91RM9200 | |||
| 10 | select CPU_ARM920T | 25 | select CPU_ARM920T |
| 11 | select GENERIC_TIME | 26 | select GENERIC_TIME |
| 12 | select GENERIC_CLOCKEVENTS | 27 | select GENERIC_CLOCKEVENTS |
| 28 | select HAVE_AT91_USART3 | ||
| 13 | 29 | ||
| 14 | config ARCH_AT91SAM9260 | 30 | config ARCH_AT91SAM9260 |
| 15 | bool "AT91SAM9260 or AT91SAM9XE" | 31 | bool "AT91SAM9260 or AT91SAM9XE" |
| 16 | select CPU_ARM926T | 32 | select CPU_ARM926T |
| 17 | select GENERIC_TIME | 33 | select GENERIC_TIME |
| 18 | select GENERIC_CLOCKEVENTS | 34 | select GENERIC_CLOCKEVENTS |
| 35 | select HAVE_AT91_USART3 | ||
| 36 | select HAVE_AT91_USART4 | ||
| 37 | select HAVE_AT91_USART5 | ||
| 19 | 38 | ||
| 20 | config ARCH_AT91SAM9261 | 39 | config ARCH_AT91SAM9261 |
| 21 | bool "AT91SAM9261" | 40 | bool "AT91SAM9261" |
| 22 | select CPU_ARM926T | 41 | select CPU_ARM926T |
| 23 | select GENERIC_TIME | 42 | select GENERIC_TIME |
| 24 | select GENERIC_CLOCKEVENTS | 43 | select GENERIC_CLOCKEVENTS |
| 44 | select HAVE_FB_ATMEL | ||
| 25 | 45 | ||
| 26 | config ARCH_AT91SAM9G10 | 46 | config ARCH_AT91SAM9G10 |
| 27 | bool "AT91SAM9G10" | 47 | bool "AT91SAM9G10" |
| 28 | select CPU_ARM926T | 48 | select CPU_ARM926T |
| 29 | select GENERIC_TIME | 49 | select GENERIC_TIME |
| 30 | select GENERIC_CLOCKEVENTS | 50 | select GENERIC_CLOCKEVENTS |
| 51 | select HAVE_FB_ATMEL | ||
| 31 | 52 | ||
| 32 | config ARCH_AT91SAM9263 | 53 | config ARCH_AT91SAM9263 |
| 33 | bool "AT91SAM9263" | 54 | bool "AT91SAM9263" |
| 34 | select CPU_ARM926T | 55 | select CPU_ARM926T |
| 35 | select GENERIC_TIME | 56 | select GENERIC_TIME |
| 36 | select GENERIC_CLOCKEVENTS | 57 | select GENERIC_CLOCKEVENTS |
| 58 | select HAVE_FB_ATMEL | ||
| 37 | 59 | ||
| 38 | config ARCH_AT91SAM9RL | 60 | config ARCH_AT91SAM9RL |
| 39 | bool "AT91SAM9RL" | 61 | bool "AT91SAM9RL" |
| 40 | select CPU_ARM926T | 62 | select CPU_ARM926T |
| 41 | select GENERIC_TIME | 63 | select GENERIC_TIME |
| 42 | select GENERIC_CLOCKEVENTS | 64 | select GENERIC_CLOCKEVENTS |
| 65 | select HAVE_AT91_USART3 | ||
| 66 | select HAVE_FB_ATMEL | ||
| 43 | 67 | ||
| 44 | config ARCH_AT91SAM9G20 | 68 | config ARCH_AT91SAM9G20 |
| 45 | bool "AT91SAM9G20" | 69 | bool "AT91SAM9G20" |
| 46 | select CPU_ARM926T | 70 | select CPU_ARM926T |
| 47 | select GENERIC_TIME | 71 | select GENERIC_TIME |
| 48 | select GENERIC_CLOCKEVENTS | 72 | select GENERIC_CLOCKEVENTS |
| 73 | select HAVE_AT91_USART3 | ||
| 74 | select HAVE_AT91_USART4 | ||
| 75 | select HAVE_AT91_USART5 | ||
| 49 | 76 | ||
| 50 | config ARCH_AT91SAM9G45 | 77 | config ARCH_AT91SAM9G45 |
| 51 | bool "AT91SAM9G45" | 78 | bool "AT91SAM9G45" |
| 52 | select CPU_ARM926T | 79 | select CPU_ARM926T |
| 53 | select GENERIC_TIME | 80 | select GENERIC_TIME |
| 54 | select GENERIC_CLOCKEVENTS | 81 | select GENERIC_CLOCKEVENTS |
| 82 | select HAVE_AT91_USART3 | ||
| 83 | select HAVE_FB_ATMEL | ||
| 55 | 84 | ||
| 56 | config ARCH_AT91CAP9 | 85 | config ARCH_AT91CAP9 |
| 57 | bool "AT91CAP9" | 86 | bool "AT91CAP9" |
| 58 | select CPU_ARM926T | 87 | select CPU_ARM926T |
| 59 | select GENERIC_TIME | 88 | select GENERIC_TIME |
| 60 | select GENERIC_CLOCKEVENTS | 89 | select GENERIC_CLOCKEVENTS |
| 90 | select HAVE_FB_ATMEL | ||
| 61 | 91 | ||
| 62 | config ARCH_AT91X40 | 92 | config ARCH_AT91X40 |
| 63 | bool "AT91x40" | 93 | bool "AT91x40" |
| @@ -76,89 +106,79 @@ comment "AT91RM9200 Board Type" | |||
| 76 | 106 | ||
| 77 | config MACH_ONEARM | 107 | config MACH_ONEARM |
| 78 | bool "Ajeco 1ARM Single Board Computer" | 108 | bool "Ajeco 1ARM Single Board Computer" |
| 79 | depends on ARCH_AT91RM9200 | ||
| 80 | help | 109 | help |
| 81 | Select this if you are using Ajeco's 1ARM Single Board Computer. | 110 | Select this if you are using Ajeco's 1ARM Single Board Computer. |
| 82 | <http://www.ajeco.fi/products.htm> | 111 | <http://www.ajeco.fi/products.htm> |
| 83 | 112 | ||
| 84 | config ARCH_AT91RM9200DK | 113 | config ARCH_AT91RM9200DK |
| 85 | bool "Atmel AT91RM9200-DK Development board" | 114 | bool "Atmel AT91RM9200-DK Development board" |
| 86 | depends on ARCH_AT91RM9200 | 115 | select HAVE_AT91_DATAFLASH_CARD |
| 87 | help | 116 | help |
| 88 | Select this if you are using Atmel's AT91RM9200-DK Development board. | 117 | Select this if you are using Atmel's AT91RM9200-DK Development board. |
| 89 | (Discontinued) | 118 | (Discontinued) |
| 90 | 119 | ||
| 91 | config MACH_AT91RM9200EK | 120 | config MACH_AT91RM9200EK |
| 92 | bool "Atmel AT91RM9200-EK Evaluation Kit" | 121 | bool "Atmel AT91RM9200-EK Evaluation Kit" |
| 93 | depends on ARCH_AT91RM9200 | 122 | select HAVE_AT91_DATAFLASH_CARD |
| 94 | help | 123 | help |
| 95 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. | 124 | Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. |
| 96 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> | 125 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507> |
| 97 | 126 | ||
| 98 | config MACH_CSB337 | 127 | config MACH_CSB337 |
| 99 | bool "Cogent CSB337" | 128 | bool "Cogent CSB337" |
| 100 | depends on ARCH_AT91RM9200 | ||
| 101 | help | 129 | help |
| 102 | Select this if you are using Cogent's CSB337 board. | 130 | Select this if you are using Cogent's CSB337 board. |
| 103 | <http://www.cogcomp.com/csb_csb337.htm> | 131 | <http://www.cogcomp.com/csb_csb337.htm> |
| 104 | 132 | ||
| 105 | config MACH_CSB637 | 133 | config MACH_CSB637 |
| 106 | bool "Cogent CSB637" | 134 | bool "Cogent CSB637" |
| 107 | depends on ARCH_AT91RM9200 | ||
| 108 | help | 135 | help |
| 109 | Select this if you are using Cogent's CSB637 board. | 136 | Select this if you are using Cogent's CSB637 board. |
| 110 | <http://www.cogcomp.com/csb_csb637.htm> | 137 | <http://www.cogcomp.com/csb_csb637.htm> |
| 111 | 138 | ||
| 112 | config MACH_CARMEVA | 139 | config MACH_CARMEVA |
| 113 | bool "Conitec ARM&EVA" | 140 | bool "Conitec ARM&EVA" |
| 114 | depends on ARCH_AT91RM9200 | ||
| 115 | help | 141 | help |
| 116 | Select this if you are using Conitec's AT91RM9200-MCU-Module. | 142 | Select this if you are using Conitec's AT91RM9200-MCU-Module. |
| 117 | <http://www.conitec.net/english/linuxboard.htm> | 143 | <http://www.conitec.net/english/linuxboard.htm> |
| 118 | 144 | ||
| 119 | config MACH_ATEB9200 | 145 | config MACH_ATEB9200 |
| 120 | bool "Embest ATEB9200" | 146 | bool "Embest ATEB9200" |
| 121 | depends on ARCH_AT91RM9200 | ||
| 122 | help | 147 | help |
| 123 | Select this if you are using Embest's ATEB9200 board. | 148 | Select this if you are using Embest's ATEB9200 board. |
| 124 | <http://www.embedinfo.com/english/product/ATEB9200.asp> | 149 | <http://www.embedinfo.com/english/product/ATEB9200.asp> |
| 125 | 150 | ||
| 126 | config MACH_KB9200 | 151 | config MACH_KB9200 |
| 127 | bool "KwikByte KB920x" | 152 | bool "KwikByte KB920x" |
| 128 | depends on ARCH_AT91RM9200 | ||
| 129 | help | 153 | help |
| 130 | Select this if you are using KwikByte's KB920x board. | 154 | Select this if you are using KwikByte's KB920x board. |
| 131 | <http://kwikbyte.com/KB9202_description_new.htm> | 155 | <http://kwikbyte.com/KB9202_description_new.htm> |
| 132 | 156 | ||
| 133 | config MACH_PICOTUX2XX | 157 | config MACH_PICOTUX2XX |
| 134 | bool "picotux 200" | 158 | bool "picotux 200" |
| 135 | depends on ARCH_AT91RM9200 | ||
| 136 | help | 159 | help |
| 137 | Select this if you are using a picotux 200. | 160 | Select this if you are using a picotux 200. |
| 138 | <http://www.picotux.com/> | 161 | <http://www.picotux.com/> |
| 139 | 162 | ||
| 140 | config MACH_KAFA | 163 | config MACH_KAFA |
| 141 | bool "Sperry-Sun KAFA board" | 164 | bool "Sperry-Sun KAFA board" |
| 142 | depends on ARCH_AT91RM9200 | ||
| 143 | help | 165 | help |
| 144 | Select this if you are using Sperry-Sun's KAFA board. | 166 | Select this if you are using Sperry-Sun's KAFA board. |
| 145 | 167 | ||
| 146 | config MACH_ECBAT91 | 168 | config MACH_ECBAT91 |
| 147 | bool "emQbit ECB_AT91 SBC" | 169 | bool "emQbit ECB_AT91 SBC" |
| 148 | depends on ARCH_AT91RM9200 | 170 | select HAVE_AT91_DATAFLASH_CARD |
| 149 | help | 171 | help |
| 150 | Select this if you are using emQbit's ECB_AT91 board. | 172 | Select this if you are using emQbit's ECB_AT91 board. |
| 151 | <http://wiki.emqbit.com/free-ecb-at91> | 173 | <http://wiki.emqbit.com/free-ecb-at91> |
| 152 | 174 | ||
| 153 | config MACH_YL9200 | 175 | config MACH_YL9200 |
| 154 | bool "ucDragon YL-9200" | 176 | bool "ucDragon YL-9200" |
| 155 | depends on ARCH_AT91RM9200 | ||
| 156 | help | 177 | help |
| 157 | Select this if you are using the ucDragon YL-9200 board. | 178 | Select this if you are using the ucDragon YL-9200 board. |
| 158 | 179 | ||
| 159 | config MACH_CPUAT91 | 180 | config MACH_CPUAT91 |
| 160 | bool "Eukrea CPUAT91" | 181 | bool "Eukrea CPUAT91" |
| 161 | depends on ARCH_AT91RM9200 | ||
| 162 | help | 182 | help |
| 163 | Select this if you are using the Eukrea Electromatique's | 183 | Select this if you are using the Eukrea Electromatique's |
| 164 | CPUAT91 board <http://www.eukrea.com/>. | 184 | CPUAT91 board <http://www.eukrea.com/>. |
| @@ -178,7 +198,6 @@ comment "AT91SAM9260 Variants" | |||
| 178 | 198 | ||
| 179 | config ARCH_AT91SAM9260_SAM9XE | 199 | config ARCH_AT91SAM9260_SAM9XE |
| 180 | bool "AT91SAM9XE" | 200 | bool "AT91SAM9XE" |
| 181 | depends on ARCH_AT91SAM9260 | ||
| 182 | help | 201 | help |
| 183 | Select this if you are using Atmel's AT91SAM9XE System-on-Chip. | 202 | Select this if you are using Atmel's AT91SAM9XE System-on-Chip. |
| 184 | They are basically AT91SAM9260s with various sizes of embedded Flash. | 203 | They are basically AT91SAM9260s with various sizes of embedded Flash. |
| @@ -187,28 +206,27 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type" | |||
| 187 | 206 | ||
| 188 | config MACH_AT91SAM9260EK | 207 | config MACH_AT91SAM9260EK |
| 189 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" | 208 | bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" |
| 190 | depends on ARCH_AT91SAM9260 | 209 | select HAVE_AT91_DATAFLASH_CARD |
| 210 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 191 | help | 211 | help |
| 192 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit | 212 | Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit |
| 193 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> | 213 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933> |
| 194 | 214 | ||
| 195 | config MACH_CAM60 | 215 | config MACH_CAM60 |
| 196 | bool "KwikByte KB9260 (CAM60) board" | 216 | bool "KwikByte KB9260 (CAM60) board" |
| 197 | depends on ARCH_AT91SAM9260 | ||
| 198 | help | 217 | help |
| 199 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. | 218 | Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. |
| 200 | <http://www.kwikbyte.com/KB9260.html> | 219 | <http://www.kwikbyte.com/KB9260.html> |
| 201 | 220 | ||
| 202 | config MACH_SAM9_L9260 | 221 | config MACH_SAM9_L9260 |
| 203 | bool "Olimex SAM9-L9260 board" | 222 | bool "Olimex SAM9-L9260 board" |
| 204 | depends on ARCH_AT91SAM9260 | 223 | select HAVE_AT91_DATAFLASH_CARD |
| 205 | help | 224 | help |
| 206 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. | 225 | Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. |
| 207 | <http://www.olimex.com/dev/sam9-L9260.html> | 226 | <http://www.olimex.com/dev/sam9-L9260.html> |
| 208 | 227 | ||
| 209 | config MACH_AFEB9260 | 228 | config MACH_AFEB9260 |
| 210 | bool "Custom afeb9260 board v1" | 229 | bool "Custom afeb9260 board v1" |
| 211 | depends on ARCH_AT91SAM9260 | ||
| 212 | help | 230 | help |
| 213 | Select this if you are using custom afeb9260 board based on | 231 | Select this if you are using custom afeb9260 board based on |
| 214 | open hardware design. Select this for revision 1 of the board. | 232 | open hardware design. Select this for revision 1 of the board. |
| @@ -217,21 +235,18 @@ config MACH_AFEB9260 | |||
| 217 | 235 | ||
| 218 | config MACH_USB_A9260 | 236 | config MACH_USB_A9260 |
| 219 | bool "CALAO USB-A9260" | 237 | bool "CALAO USB-A9260" |
| 220 | depends on ARCH_AT91SAM9260 | ||
| 221 | help | 238 | help |
| 222 | Select this if you are using a Calao Systems USB-A9260. | 239 | Select this if you are using a Calao Systems USB-A9260. |
| 223 | <http://www.calao-systems.com> | 240 | <http://www.calao-systems.com> |
| 224 | 241 | ||
| 225 | config MACH_QIL_A9260 | 242 | config MACH_QIL_A9260 |
| 226 | bool "CALAO QIL-A9260 board" | 243 | bool "CALAO QIL-A9260 board" |
| 227 | depends on ARCH_AT91SAM9260 | ||
| 228 | help | 244 | help |
| 229 | Select this if you are using a Calao Systems QIL-A9260 Board. | 245 | Select this if you are using a Calao Systems QIL-A9260 Board. |
| 230 | <http://www.calao-systems.com> | 246 | <http://www.calao-systems.com> |
| 231 | 247 | ||
| 232 | config MACH_CPU9260 | 248 | config MACH_CPU9260 |
| 233 | bool "Eukrea CPU9260 board" | 249 | bool "Eukrea CPU9260 board" |
| 234 | depends on ARCH_AT91SAM9260 | ||
| 235 | help | 250 | help |
| 236 | Select this if you are using a Eukrea Electromatique's | 251 | Select this if you are using a Eukrea Electromatique's |
| 237 | CPU9260 Board <http://www.eukrea.com/> | 252 | CPU9260 Board <http://www.eukrea.com/> |
| @@ -246,7 +261,8 @@ comment "AT91SAM9261 Board Type" | |||
| 246 | 261 | ||
| 247 | config MACH_AT91SAM9261EK | 262 | config MACH_AT91SAM9261EK |
| 248 | bool "Atmel AT91SAM9261-EK Evaluation Kit" | 263 | bool "Atmel AT91SAM9261-EK Evaluation Kit" |
| 249 | depends on ARCH_AT91SAM9261 | 264 | select HAVE_AT91_DATAFLASH_CARD |
| 265 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 250 | help | 266 | help |
| 251 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. | 267 | Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. |
| 252 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> | 268 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> |
| @@ -261,7 +277,8 @@ comment "AT91SAM9G10 Board Type" | |||
| 261 | 277 | ||
| 262 | config MACH_AT91SAM9G10EK | 278 | config MACH_AT91SAM9G10EK |
| 263 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | 279 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" |
| 264 | depends on ARCH_AT91SAM9G10 | 280 | select HAVE_AT91_DATAFLASH_CARD |
| 281 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 265 | help | 282 | help |
| 266 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | 283 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. |
| 267 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | 284 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> |
| @@ -276,21 +293,21 @@ comment "AT91SAM9263 Board Type" | |||
| 276 | 293 | ||
| 277 | config MACH_AT91SAM9263EK | 294 | config MACH_AT91SAM9263EK |
| 278 | bool "Atmel AT91SAM9263-EK Evaluation Kit" | 295 | bool "Atmel AT91SAM9263-EK Evaluation Kit" |
| 279 | depends on ARCH_AT91SAM9263 | 296 | select HAVE_AT91_DATAFLASH_CARD |
| 297 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 280 | help | 298 | help |
| 281 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. | 299 | Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. |
| 282 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> | 300 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> |
| 283 | 301 | ||
| 284 | config MACH_USB_A9263 | 302 | config MACH_USB_A9263 |
| 285 | bool "CALAO USB-A9263" | 303 | bool "CALAO USB-A9263" |
| 286 | depends on ARCH_AT91SAM9263 | ||
| 287 | help | 304 | help |
| 288 | Select this if you are using a Calao Systems USB-A9263. | 305 | Select this if you are using a Calao Systems USB-A9263. |
| 289 | <http://www.calao-systems.com> | 306 | <http://www.calao-systems.com> |
| 290 | 307 | ||
| 291 | config MACH_NEOCORE926 | 308 | config MACH_NEOCORE926 |
| 292 | bool "Adeneo NEOCORE926" | 309 | bool "Adeneo NEOCORE926" |
| 293 | depends on ARCH_AT91SAM9263 | 310 | select HAVE_AT91_DATAFLASH_CARD |
| 294 | help | 311 | help |
| 295 | Select this if you are using the Adeneo Neocore 926 board. | 312 | Select this if you are using the Adeneo Neocore 926 board. |
| 296 | 313 | ||
| @@ -304,7 +321,6 @@ comment "AT91SAM9RL Board Type" | |||
| 304 | 321 | ||
| 305 | config MACH_AT91SAM9RLEK | 322 | config MACH_AT91SAM9RLEK |
| 306 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" | 323 | bool "Atmel AT91SAM9RL-EK Evaluation Kit" |
| 307 | depends on ARCH_AT91SAM9RL | ||
| 308 | help | 324 | help |
| 309 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. | 325 | Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. |
| 310 | 326 | ||
| @@ -318,14 +334,15 @@ comment "AT91SAM9G20 Board Type" | |||
| 318 | 334 | ||
| 319 | config MACH_AT91SAM9G20EK | 335 | config MACH_AT91SAM9G20EK |
| 320 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" | 336 | bool "Atmel AT91SAM9G20-EK Evaluation Kit" |
| 321 | depends on ARCH_AT91SAM9G20 | 337 | select HAVE_AT91_DATAFLASH_CARD |
| 338 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 322 | help | 339 | help |
| 323 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit | 340 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit |
| 324 | that embeds only one SD/MMC slot. | 341 | that embeds only one SD/MMC slot. |
| 325 | 342 | ||
| 326 | config MACH_AT91SAM9G20EK_2MMC | 343 | config MACH_AT91SAM9G20EK_2MMC |
| 327 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" | 344 | bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" |
| 328 | depends on ARCH_AT91SAM9G20 | 345 | select HAVE_NAND_ATMEL_BUSWIDTH_16 |
| 329 | help | 346 | help |
| 330 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit | 347 | Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit |
| 331 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and | 348 | with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and |
| @@ -333,7 +350,6 @@ config MACH_AT91SAM9G20EK_2MMC | |||
| 333 | 350 | ||
| 334 | config MACH_CPU9G20 | 351 | config MACH_CPU9G20 |
| 335 | bool "Eukrea CPU9G20 board" | 352 | bool "Eukrea CPU9G20 board" |
| 336 | depends on ARCH_AT91SAM9G20 | ||
| 337 | help | 353 | help |
| 338 | Select this if you are using a Eukrea Electromatique's | 354 | Select this if you are using a Eukrea Electromatique's |
| 339 | CPU9G20 Board <http://www.eukrea.com/> | 355 | CPU9G20 Board <http://www.eukrea.com/> |
| @@ -348,7 +364,7 @@ comment "AT91SAM9G45 Board Type" | |||
| 348 | 364 | ||
| 349 | config MACH_AT91SAM9G45EKES | 365 | config MACH_AT91SAM9G45EKES |
| 350 | bool "Atmel AT91SAM9G45-EKES Evaluation Kit" | 366 | bool "Atmel AT91SAM9G45-EKES Evaluation Kit" |
| 351 | depends on ARCH_AT91SAM9G45 | 367 | select HAVE_NAND_ATMEL_BUSWIDTH_16 |
| 352 | help | 368 | help |
| 353 | Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. | 369 | Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. |
| 354 | "ES" at the end of the name means that this board is an | 370 | "ES" at the end of the name means that this board is an |
| @@ -364,7 +380,8 @@ comment "AT91CAP9 Board Type" | |||
| 364 | 380 | ||
| 365 | config MACH_AT91CAP9ADK | 381 | config MACH_AT91CAP9ADK |
| 366 | bool "Atmel AT91CAP9A-DK Evaluation Kit" | 382 | bool "Atmel AT91CAP9A-DK Evaluation Kit" |
| 367 | depends on ARCH_AT91CAP9 | 383 | select HAVE_AT91_DATAFLASH_CARD |
| 384 | select HAVE_NAND_ATMEL_BUSWIDTH_16 | ||
| 368 | help | 385 | help |
| 369 | Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit. | 386 | Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit. |
| 370 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138> | 387 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138> |
| @@ -393,13 +410,13 @@ comment "AT91 Board Options" | |||
| 393 | 410 | ||
| 394 | config MTD_AT91_DATAFLASH_CARD | 411 | config MTD_AT91_DATAFLASH_CARD |
| 395 | bool "Enable DataFlash Card support" | 412 | bool "Enable DataFlash Card support" |
| 396 | depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) | 413 | depends on HAVE_AT91_DATAFLASH_CARD |
| 397 | help | 414 | help |
| 398 | Enable support for the DataFlash card. | 415 | Enable support for the DataFlash card. |
| 399 | 416 | ||
| 400 | config MTD_NAND_ATMEL_BUSWIDTH_16 | 417 | config MTD_NAND_ATMEL_BUSWIDTH_16 |
| 401 | bool "Enable 16-bit data bus interface to NAND flash" | 418 | bool "Enable 16-bit data bus interface to NAND flash" |
| 402 | depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G20EK_2MMC || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK) | 419 | depends on HAVE_NAND_ATMEL_BUSWIDTH_16 |
| 403 | help | 420 | help |
| 404 | On AT91SAM926x boards both types of NAND flash can be present | 421 | On AT91SAM926x boards both types of NAND flash can be present |
| 405 | (8 and 16 bit data bus width). | 422 | (8 and 16 bit data bus width). |
| @@ -461,15 +478,15 @@ config AT91_EARLY_USART2 | |||
| 461 | 478 | ||
| 462 | config AT91_EARLY_USART3 | 479 | config AT91_EARLY_USART3 |
| 463 | bool "USART3" | 480 | bool "USART3" |
| 464 | depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45) | 481 | depends on HAVE_AT91_USART3 |
| 465 | 482 | ||
| 466 | config AT91_EARLY_USART4 | 483 | config AT91_EARLY_USART4 |
| 467 | bool "USART4" | 484 | bool "USART4" |
| 468 | depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 | 485 | depends on HAVE_AT91_USART4 |
| 469 | 486 | ||
| 470 | config AT91_EARLY_USART5 | 487 | config AT91_EARLY_USART5 |
| 471 | bool "USART5" | 488 | bool "USART5" |
| 472 | depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 | 489 | depends on HAVE_AT91_USART5 |
| 473 | 490 | ||
| 474 | endchoice | 491 | endchoice |
| 475 | 492 | ||
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig new file mode 100644 index 000000000000..3b9a32ace909 --- /dev/null +++ b/arch/arm/mach-dove/Kconfig | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | if ARCH_DOVE | ||
| 2 | |||
| 3 | menu "Marvell Dove Implementations" | ||
| 4 | |||
| 5 | config MACH_DOVE_DB | ||
| 6 | bool "Marvell DB-MV88AP510 Development Board" | ||
| 7 | select I2C_BOARDINFO | ||
| 8 | help | ||
| 9 | Say 'Y' here if you want your kernel to support the | ||
| 10 | Marvell DB-MV88AP510 Development Board. | ||
| 11 | |||
| 12 | endmenu | ||
| 13 | |||
| 14 | endif | ||
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile new file mode 100644 index 000000000000..7ab3be53f642 --- /dev/null +++ b/arch/arm/mach-dove/Makefile | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | ||
| 2 | |||
| 3 | obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o | ||
diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot new file mode 100644 index 000000000000..67039c3e0c48 --- /dev/null +++ b/arch/arm/mach-dove/Makefile.boot | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | zreladdr-y := 0x00008000 | ||
| 2 | params_phys-y := 0x00000100 | ||
| 3 | initrd_phys-y := 0x00800000 | ||
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c new file mode 100644 index 000000000000..00be4fc26dd7 --- /dev/null +++ b/arch/arm/mach-dove/addr-map.c | |||
| @@ -0,0 +1,149 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/addr-map.c | ||
| 3 | * | ||
| 4 | * Address map functions for Marvell Dove 88AP510 SoC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/mach/arch.h> | ||
| 16 | #include <asm/setup.h> | ||
| 17 | #include "common.h" | ||
| 18 | |||
| 19 | /* | ||
| 20 | * Generic Address Decode Windows bit settings | ||
| 21 | */ | ||
| 22 | #define TARGET_DDR 0x0 | ||
| 23 | #define TARGET_BOOTROM 0x1 | ||
| 24 | #define TARGET_CESA 0x3 | ||
| 25 | #define TARGET_PCIE0 0x4 | ||
| 26 | #define TARGET_PCIE1 0x8 | ||
| 27 | #define TARGET_SCRATCHPAD 0xd | ||
| 28 | |||
| 29 | #define ATTR_CESA 0x01 | ||
| 30 | #define ATTR_BOOTROM 0xfd | ||
| 31 | #define ATTR_DEV_SPI0_ROM 0xfe | ||
| 32 | #define ATTR_DEV_SPI1_ROM 0xfb | ||
| 33 | #define ATTR_PCIE_IO 0xe0 | ||
| 34 | #define ATTR_PCIE_MEM 0xe8 | ||
| 35 | #define ATTR_SCRATCHPAD 0x0 | ||
| 36 | |||
| 37 | /* | ||
| 38 | * CPU Address Decode Windows registers | ||
| 39 | */ | ||
| 40 | #define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) | ||
| 41 | #define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) | ||
| 42 | #define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) | ||
| 43 | #define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) | ||
| 44 | |||
| 45 | struct mbus_dram_target_info dove_mbus_dram_info; | ||
| 46 | |||
| 47 | static inline void __iomem *ddr_map_sc(int i) | ||
| 48 | { | ||
| 49 | return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); | ||
| 50 | } | ||
| 51 | |||
| 52 | static int cpu_win_can_remap(int win) | ||
| 53 | { | ||
| 54 | if (win < 4) | ||
| 55 | return 1; | ||
| 56 | |||
| 57 | return 0; | ||
| 58 | } | ||
| 59 | |||
| 60 | static void __init setup_cpu_win(int win, u32 base, u32 size, | ||
| 61 | u8 target, u8 attr, int remap) | ||
| 62 | { | ||
| 63 | u32 ctrl; | ||
| 64 | |||
| 65 | base &= 0xffff0000; | ||
| 66 | ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; | ||
| 67 | |||
| 68 | writel(base, WIN_BASE(win)); | ||
| 69 | writel(ctrl, WIN_CTRL(win)); | ||
| 70 | if (cpu_win_can_remap(win)) { | ||
| 71 | if (remap < 0) | ||
| 72 | remap = base; | ||
| 73 | writel(remap & 0xffff0000, WIN_REMAP_LO(win)); | ||
| 74 | writel(0, WIN_REMAP_HI(win)); | ||
| 75 | } | ||
| 76 | } | ||
| 77 | |||
| 78 | void __init dove_setup_cpu_mbus(void) | ||
| 79 | { | ||
| 80 | int i; | ||
| 81 | int cs; | ||
| 82 | |||
| 83 | /* | ||
| 84 | * First, disable and clear windows. | ||
| 85 | */ | ||
| 86 | for (i = 0; i < 8; i++) { | ||
| 87 | writel(0, WIN_BASE(i)); | ||
| 88 | writel(0, WIN_CTRL(i)); | ||
| 89 | if (cpu_win_can_remap(i)) { | ||
| 90 | writel(0, WIN_REMAP_LO(i)); | ||
| 91 | writel(0, WIN_REMAP_HI(i)); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | /* | ||
| 96 | * Setup windows for PCIe IO+MEM space. | ||
| 97 | */ | ||
| 98 | setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, | ||
| 99 | TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); | ||
| 100 | setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, | ||
| 101 | TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); | ||
| 102 | setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, | ||
| 103 | TARGET_PCIE0, ATTR_PCIE_MEM, -1); | ||
| 104 | setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, | ||
| 105 | TARGET_PCIE1, ATTR_PCIE_MEM, -1); | ||
| 106 | |||
| 107 | /* | ||
| 108 | * Setup window for CESA engine. | ||
| 109 | */ | ||
| 110 | setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, | ||
| 111 | TARGET_CESA, ATTR_CESA, -1); | ||
| 112 | |||
| 113 | /* | ||
| 114 | * Setup the Window to the BootROM for Standby and Sleep Resume | ||
| 115 | */ | ||
| 116 | setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, | ||
| 117 | TARGET_BOOTROM, ATTR_BOOTROM, -1); | ||
| 118 | |||
| 119 | /* | ||
| 120 | * Setup the Window to the PMU Scratch Pad space | ||
| 121 | */ | ||
| 122 | setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, | ||
| 123 | TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); | ||
| 124 | |||
| 125 | /* | ||
| 126 | * Setup MBUS dram target info. | ||
| 127 | */ | ||
| 128 | dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; | ||
| 129 | |||
| 130 | for (i = 0, cs = 0; i < 2; i++) { | ||
| 131 | u32 map = readl(ddr_map_sc(i)); | ||
| 132 | |||
| 133 | /* | ||
| 134 | * Chip select enabled? | ||
| 135 | */ | ||
| 136 | if (map & 1) { | ||
| 137 | struct mbus_dram_window *w; | ||
| 138 | |||
| 139 | w = &dove_mbus_dram_info.cs[cs++]; | ||
| 140 | w->cs_index = i; | ||
| 141 | w->mbus_attr = 0; /* CS address decoding done inside */ | ||
| 142 | /* the DDR controller, no need to */ | ||
| 143 | /* provide attributes */ | ||
| 144 | w->base = map & 0xff800000; | ||
| 145 | w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); | ||
| 146 | } | ||
| 147 | } | ||
| 148 | dove_mbus_dram_info.num_cs = cs; | ||
| 149 | } | ||
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c new file mode 100644 index 000000000000..806972a68c87 --- /dev/null +++ b/arch/arm/mach-dove/common.c | |||
| @@ -0,0 +1,781 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/common.c | ||
| 3 | * | ||
| 4 | * Core functions for Marvell Dove 88AP510 System On Chip | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/delay.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/pci.h> | ||
| 16 | #include <linux/serial_8250.h> | ||
| 17 | #include <linux/clk.h> | ||
| 18 | #include <linux/mbus.h> | ||
| 19 | #include <linux/mv643xx_eth.h> | ||
| 20 | #include <linux/mv643xx_i2c.h> | ||
| 21 | #include <linux/ata_platform.h> | ||
| 22 | #include <linux/spi/orion_spi.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | #include <asm/page.h> | ||
| 25 | #include <asm/setup.h> | ||
| 26 | #include <asm/timex.h> | ||
| 27 | #include <asm/hardware/cache-tauros2.h> | ||
| 28 | #include <asm/mach/map.h> | ||
| 29 | #include <asm/mach/time.h> | ||
| 30 | #include <asm/mach/pci.h> | ||
| 31 | #include <mach/dove.h> | ||
| 32 | #include <mach/bridge-regs.h> | ||
| 33 | #include <asm/mach/arch.h> | ||
| 34 | #include <linux/irq.h> | ||
| 35 | #include <plat/mv_xor.h> | ||
| 36 | #include <plat/ehci-orion.h> | ||
| 37 | #include <plat/time.h> | ||
| 38 | #include "common.h" | ||
| 39 | |||
| 40 | /***************************************************************************** | ||
| 41 | * I/O Address Mapping | ||
| 42 | ****************************************************************************/ | ||
| 43 | static struct map_desc dove_io_desc[] __initdata = { | ||
| 44 | { | ||
| 45 | .virtual = DOVE_SB_REGS_VIRT_BASE, | ||
| 46 | .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), | ||
| 47 | .length = DOVE_SB_REGS_SIZE, | ||
| 48 | .type = MT_DEVICE, | ||
| 49 | }, { | ||
| 50 | .virtual = DOVE_NB_REGS_VIRT_BASE, | ||
| 51 | .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), | ||
| 52 | .length = DOVE_NB_REGS_SIZE, | ||
| 53 | .type = MT_DEVICE, | ||
| 54 | }, { | ||
| 55 | .virtual = DOVE_PCIE0_IO_VIRT_BASE, | ||
| 56 | .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), | ||
| 57 | .length = DOVE_PCIE0_IO_SIZE, | ||
| 58 | .type = MT_DEVICE, | ||
| 59 | }, { | ||
| 60 | .virtual = DOVE_PCIE1_IO_VIRT_BASE, | ||
| 61 | .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), | ||
| 62 | .length = DOVE_PCIE1_IO_SIZE, | ||
| 63 | .type = MT_DEVICE, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | |||
| 67 | void __init dove_map_io(void) | ||
| 68 | { | ||
| 69 | iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); | ||
| 70 | } | ||
| 71 | |||
| 72 | /***************************************************************************** | ||
| 73 | * EHCI | ||
| 74 | ****************************************************************************/ | ||
| 75 | static struct orion_ehci_data dove_ehci_data = { | ||
| 76 | .dram = &dove_mbus_dram_info, | ||
| 77 | .phy_version = EHCI_PHY_NA, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static u64 ehci_dmamask = DMA_BIT_MASK(32); | ||
| 81 | |||
| 82 | /***************************************************************************** | ||
| 83 | * EHCI0 | ||
| 84 | ****************************************************************************/ | ||
| 85 | static struct resource dove_ehci0_resources[] = { | ||
| 86 | { | ||
| 87 | .start = DOVE_USB0_PHYS_BASE, | ||
| 88 | .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, | ||
| 89 | .flags = IORESOURCE_MEM, | ||
| 90 | }, { | ||
| 91 | .start = IRQ_DOVE_USB0, | ||
| 92 | .end = IRQ_DOVE_USB0, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct platform_device dove_ehci0 = { | ||
| 98 | .name = "orion-ehci", | ||
| 99 | .id = 0, | ||
| 100 | .dev = { | ||
| 101 | .dma_mask = &ehci_dmamask, | ||
| 102 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 103 | .platform_data = &dove_ehci_data, | ||
| 104 | }, | ||
| 105 | .resource = dove_ehci0_resources, | ||
| 106 | .num_resources = ARRAY_SIZE(dove_ehci0_resources), | ||
| 107 | }; | ||
| 108 | |||
| 109 | void __init dove_ehci0_init(void) | ||
| 110 | { | ||
| 111 | platform_device_register(&dove_ehci0); | ||
| 112 | } | ||
| 113 | |||
| 114 | /***************************************************************************** | ||
| 115 | * EHCI1 | ||
| 116 | ****************************************************************************/ | ||
| 117 | static struct resource dove_ehci1_resources[] = { | ||
| 118 | { | ||
| 119 | .start = DOVE_USB1_PHYS_BASE, | ||
| 120 | .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, | ||
| 121 | .flags = IORESOURCE_MEM, | ||
| 122 | }, { | ||
| 123 | .start = IRQ_DOVE_USB1, | ||
| 124 | .end = IRQ_DOVE_USB1, | ||
| 125 | .flags = IORESOURCE_IRQ, | ||
| 126 | }, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct platform_device dove_ehci1 = { | ||
| 130 | .name = "orion-ehci", | ||
| 131 | .id = 1, | ||
| 132 | .dev = { | ||
| 133 | .dma_mask = &ehci_dmamask, | ||
| 134 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 135 | .platform_data = &dove_ehci_data, | ||
| 136 | }, | ||
| 137 | .resource = dove_ehci1_resources, | ||
| 138 | .num_resources = ARRAY_SIZE(dove_ehci1_resources), | ||
| 139 | }; | ||
| 140 | |||
| 141 | void __init dove_ehci1_init(void) | ||
| 142 | { | ||
| 143 | platform_device_register(&dove_ehci1); | ||
| 144 | } | ||
| 145 | |||
| 146 | /***************************************************************************** | ||
| 147 | * GE00 | ||
| 148 | ****************************************************************************/ | ||
| 149 | struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { | ||
| 150 | .t_clk = 0, | ||
| 151 | .dram = &dove_mbus_dram_info, | ||
| 152 | }; | ||
| 153 | |||
| 154 | static struct resource dove_ge00_shared_resources[] = { | ||
| 155 | { | ||
| 156 | .name = "ge00 base", | ||
| 157 | .start = DOVE_GE00_PHYS_BASE + 0x2000, | ||
| 158 | .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, | ||
| 159 | .flags = IORESOURCE_MEM, | ||
| 160 | }, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static struct platform_device dove_ge00_shared = { | ||
| 164 | .name = MV643XX_ETH_SHARED_NAME, | ||
| 165 | .id = 0, | ||
| 166 | .dev = { | ||
| 167 | .platform_data = &dove_ge00_shared_data, | ||
| 168 | }, | ||
| 169 | .num_resources = 1, | ||
| 170 | .resource = dove_ge00_shared_resources, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct resource dove_ge00_resources[] = { | ||
| 174 | { | ||
| 175 | .name = "ge00 irq", | ||
| 176 | .start = IRQ_DOVE_GE00_SUM, | ||
| 177 | .end = IRQ_DOVE_GE00_SUM, | ||
| 178 | .flags = IORESOURCE_IRQ, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static struct platform_device dove_ge00 = { | ||
| 183 | .name = MV643XX_ETH_NAME, | ||
| 184 | .id = 0, | ||
| 185 | .num_resources = 1, | ||
| 186 | .resource = dove_ge00_resources, | ||
| 187 | .dev = { | ||
| 188 | .coherent_dma_mask = 0xffffffff, | ||
| 189 | }, | ||
| 190 | }; | ||
| 191 | |||
| 192 | void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) | ||
| 193 | { | ||
| 194 | eth_data->shared = &dove_ge00_shared; | ||
| 195 | dove_ge00.dev.platform_data = eth_data; | ||
| 196 | |||
| 197 | platform_device_register(&dove_ge00_shared); | ||
| 198 | platform_device_register(&dove_ge00); | ||
| 199 | } | ||
| 200 | |||
| 201 | /***************************************************************************** | ||
| 202 | * SoC RTC | ||
| 203 | ****************************************************************************/ | ||
| 204 | static struct resource dove_rtc_resource[] = { | ||
| 205 | { | ||
| 206 | .start = DOVE_RTC_PHYS_BASE, | ||
| 207 | .end = DOVE_RTC_PHYS_BASE + 32 - 1, | ||
| 208 | .flags = IORESOURCE_MEM, | ||
| 209 | }, { | ||
| 210 | .start = IRQ_DOVE_RTC, | ||
| 211 | .flags = IORESOURCE_IRQ, | ||
| 212 | } | ||
| 213 | }; | ||
| 214 | |||
| 215 | void __init dove_rtc_init(void) | ||
| 216 | { | ||
| 217 | platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); | ||
| 218 | } | ||
| 219 | |||
| 220 | /***************************************************************************** | ||
| 221 | * SATA | ||
| 222 | ****************************************************************************/ | ||
| 223 | static struct resource dove_sata_resources[] = { | ||
| 224 | { | ||
| 225 | .name = "sata base", | ||
| 226 | .start = DOVE_SATA_PHYS_BASE, | ||
| 227 | .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, | ||
| 228 | .flags = IORESOURCE_MEM, | ||
| 229 | }, { | ||
| 230 | .name = "sata irq", | ||
| 231 | .start = IRQ_DOVE_SATA, | ||
| 232 | .end = IRQ_DOVE_SATA, | ||
| 233 | .flags = IORESOURCE_IRQ, | ||
| 234 | }, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct platform_device dove_sata = { | ||
| 238 | .name = "sata_mv", | ||
| 239 | .id = 0, | ||
| 240 | .dev = { | ||
| 241 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 242 | }, | ||
| 243 | .num_resources = ARRAY_SIZE(dove_sata_resources), | ||
| 244 | .resource = dove_sata_resources, | ||
| 245 | }; | ||
| 246 | |||
| 247 | void __init dove_sata_init(struct mv_sata_platform_data *sata_data) | ||
| 248 | { | ||
| 249 | sata_data->dram = &dove_mbus_dram_info; | ||
| 250 | dove_sata.dev.platform_data = sata_data; | ||
| 251 | platform_device_register(&dove_sata); | ||
| 252 | } | ||
| 253 | |||
| 254 | /***************************************************************************** | ||
| 255 | * UART0 | ||
| 256 | ****************************************************************************/ | ||
| 257 | static struct plat_serial8250_port dove_uart0_data[] = { | ||
| 258 | { | ||
| 259 | .mapbase = DOVE_UART0_PHYS_BASE, | ||
| 260 | .membase = (char *)DOVE_UART0_VIRT_BASE, | ||
| 261 | .irq = IRQ_DOVE_UART_0, | ||
| 262 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | ||
| 263 | .iotype = UPIO_MEM, | ||
| 264 | .regshift = 2, | ||
| 265 | .uartclk = 0, | ||
| 266 | }, { | ||
| 267 | }, | ||
| 268 | }; | ||
| 269 | |||
| 270 | static struct resource dove_uart0_resources[] = { | ||
| 271 | { | ||
| 272 | .start = DOVE_UART0_PHYS_BASE, | ||
| 273 | .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, | ||
| 274 | .flags = IORESOURCE_MEM, | ||
| 275 | }, { | ||
| 276 | .start = IRQ_DOVE_UART_0, | ||
| 277 | .end = IRQ_DOVE_UART_0, | ||
| 278 | .flags = IORESOURCE_IRQ, | ||
| 279 | }, | ||
| 280 | }; | ||
| 281 | |||
| 282 | static struct platform_device dove_uart0 = { | ||
| 283 | .name = "serial8250", | ||
| 284 | .id = 0, | ||
| 285 | .dev = { | ||
| 286 | .platform_data = dove_uart0_data, | ||
| 287 | }, | ||
| 288 | .resource = dove_uart0_resources, | ||
| 289 | .num_resources = ARRAY_SIZE(dove_uart0_resources), | ||
| 290 | }; | ||
| 291 | |||
| 292 | void __init dove_uart0_init(void) | ||
| 293 | { | ||
| 294 | platform_device_register(&dove_uart0); | ||
| 295 | } | ||
| 296 | |||
| 297 | /***************************************************************************** | ||
| 298 | * UART1 | ||
| 299 | ****************************************************************************/ | ||
| 300 | static struct plat_serial8250_port dove_uart1_data[] = { | ||
| 301 | { | ||
| 302 | .mapbase = DOVE_UART1_PHYS_BASE, | ||
| 303 | .membase = (char *)DOVE_UART1_VIRT_BASE, | ||
| 304 | .irq = IRQ_DOVE_UART_1, | ||
| 305 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | ||
| 306 | .iotype = UPIO_MEM, | ||
| 307 | .regshift = 2, | ||
| 308 | .uartclk = 0, | ||
| 309 | }, { | ||
| 310 | }, | ||
| 311 | }; | ||
| 312 | |||
| 313 | static struct resource dove_uart1_resources[] = { | ||
| 314 | { | ||
| 315 | .start = DOVE_UART1_PHYS_BASE, | ||
| 316 | .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, | ||
| 317 | .flags = IORESOURCE_MEM, | ||
| 318 | }, { | ||
| 319 | .start = IRQ_DOVE_UART_1, | ||
| 320 | .end = IRQ_DOVE_UART_1, | ||
| 321 | .flags = IORESOURCE_IRQ, | ||
| 322 | }, | ||
| 323 | }; | ||
| 324 | |||
| 325 | static struct platform_device dove_uart1 = { | ||
| 326 | .name = "serial8250", | ||
| 327 | .id = 1, | ||
| 328 | .dev = { | ||
| 329 | .platform_data = dove_uart1_data, | ||
| 330 | }, | ||
| 331 | .resource = dove_uart1_resources, | ||
| 332 | .num_resources = ARRAY_SIZE(dove_uart1_resources), | ||
| 333 | }; | ||
| 334 | |||
| 335 | void __init dove_uart1_init(void) | ||
| 336 | { | ||
| 337 | platform_device_register(&dove_uart1); | ||
| 338 | } | ||
| 339 | |||
| 340 | /***************************************************************************** | ||
| 341 | * UART2 | ||
| 342 | ****************************************************************************/ | ||
| 343 | static struct plat_serial8250_port dove_uart2_data[] = { | ||
| 344 | { | ||
| 345 | .mapbase = DOVE_UART2_PHYS_BASE, | ||
| 346 | .membase = (char *)DOVE_UART2_VIRT_BASE, | ||
| 347 | .irq = IRQ_DOVE_UART_2, | ||
| 348 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | ||
| 349 | .iotype = UPIO_MEM, | ||
| 350 | .regshift = 2, | ||
| 351 | .uartclk = 0, | ||
| 352 | }, { | ||
| 353 | }, | ||
| 354 | }; | ||
| 355 | |||
| 356 | static struct resource dove_uart2_resources[] = { | ||
| 357 | { | ||
| 358 | .start = DOVE_UART2_PHYS_BASE, | ||
| 359 | .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, | ||
| 360 | .flags = IORESOURCE_MEM, | ||
| 361 | }, { | ||
| 362 | .start = IRQ_DOVE_UART_2, | ||
| 363 | .end = IRQ_DOVE_UART_2, | ||
| 364 | .flags = IORESOURCE_IRQ, | ||
| 365 | }, | ||
| 366 | }; | ||
| 367 | |||
| 368 | static struct platform_device dove_uart2 = { | ||
| 369 | .name = "serial8250", | ||
| 370 | .id = 2, | ||
| 371 | .dev = { | ||
| 372 | .platform_data = dove_uart2_data, | ||
| 373 | }, | ||
| 374 | .resource = dove_uart2_resources, | ||
| 375 | .num_resources = ARRAY_SIZE(dove_uart2_resources), | ||
| 376 | }; | ||
| 377 | |||
| 378 | void __init dove_uart2_init(void) | ||
| 379 | { | ||
| 380 | platform_device_register(&dove_uart2); | ||
| 381 | } | ||
| 382 | |||
| 383 | /***************************************************************************** | ||
| 384 | * UART3 | ||
| 385 | ****************************************************************************/ | ||
| 386 | static struct plat_serial8250_port dove_uart3_data[] = { | ||
| 387 | { | ||
| 388 | .mapbase = DOVE_UART3_PHYS_BASE, | ||
| 389 | .membase = (char *)DOVE_UART3_VIRT_BASE, | ||
| 390 | .irq = IRQ_DOVE_UART_3, | ||
| 391 | .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, | ||
| 392 | .iotype = UPIO_MEM, | ||
| 393 | .regshift = 2, | ||
| 394 | .uartclk = 0, | ||
| 395 | }, { | ||
| 396 | }, | ||
| 397 | }; | ||
| 398 | |||
| 399 | static struct resource dove_uart3_resources[] = { | ||
| 400 | { | ||
| 401 | .start = DOVE_UART3_PHYS_BASE, | ||
| 402 | .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, | ||
| 403 | .flags = IORESOURCE_MEM, | ||
| 404 | }, { | ||
| 405 | .start = IRQ_DOVE_UART_3, | ||
| 406 | .end = IRQ_DOVE_UART_3, | ||
| 407 | .flags = IORESOURCE_IRQ, | ||
| 408 | }, | ||
| 409 | }; | ||
| 410 | |||
| 411 | static struct platform_device dove_uart3 = { | ||
| 412 | .name = "serial8250", | ||
| 413 | .id = 3, | ||
| 414 | .dev = { | ||
| 415 | .platform_data = dove_uart3_data, | ||
| 416 | }, | ||
| 417 | .resource = dove_uart3_resources, | ||
| 418 | .num_resources = ARRAY_SIZE(dove_uart3_resources), | ||
| 419 | }; | ||
| 420 | |||
| 421 | void __init dove_uart3_init(void) | ||
| 422 | { | ||
| 423 | platform_device_register(&dove_uart3); | ||
| 424 | } | ||
| 425 | |||
| 426 | /***************************************************************************** | ||
| 427 | * SPI0 | ||
| 428 | ****************************************************************************/ | ||
| 429 | static struct orion_spi_info dove_spi0_data = { | ||
| 430 | .tclk = 0, | ||
| 431 | }; | ||
| 432 | |||
| 433 | static struct resource dove_spi0_resources[] = { | ||
| 434 | { | ||
| 435 | .start = DOVE_SPI0_PHYS_BASE, | ||
| 436 | .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, | ||
| 437 | .flags = IORESOURCE_MEM, | ||
| 438 | }, { | ||
| 439 | .start = IRQ_DOVE_SPI0, | ||
| 440 | .end = IRQ_DOVE_SPI0, | ||
| 441 | .flags = IORESOURCE_IRQ, | ||
| 442 | }, | ||
| 443 | }; | ||
| 444 | |||
| 445 | static struct platform_device dove_spi0 = { | ||
| 446 | .name = "orion_spi", | ||
| 447 | .id = 0, | ||
| 448 | .resource = dove_spi0_resources, | ||
| 449 | .dev = { | ||
| 450 | .platform_data = &dove_spi0_data, | ||
| 451 | }, | ||
| 452 | .num_resources = ARRAY_SIZE(dove_spi0_resources), | ||
| 453 | }; | ||
| 454 | |||
| 455 | void __init dove_spi0_init(void) | ||
| 456 | { | ||
| 457 | platform_device_register(&dove_spi0); | ||
| 458 | } | ||
| 459 | |||
| 460 | /***************************************************************************** | ||
| 461 | * SPI1 | ||
| 462 | ****************************************************************************/ | ||
| 463 | static struct orion_spi_info dove_spi1_data = { | ||
| 464 | .tclk = 0, | ||
| 465 | }; | ||
| 466 | |||
| 467 | static struct resource dove_spi1_resources[] = { | ||
| 468 | { | ||
| 469 | .start = DOVE_SPI1_PHYS_BASE, | ||
| 470 | .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, | ||
| 471 | .flags = IORESOURCE_MEM, | ||
| 472 | }, { | ||
| 473 | .start = IRQ_DOVE_SPI1, | ||
| 474 | .end = IRQ_DOVE_SPI1, | ||
| 475 | .flags = IORESOURCE_IRQ, | ||
| 476 | }, | ||
| 477 | }; | ||
| 478 | |||
| 479 | static struct platform_device dove_spi1 = { | ||
| 480 | .name = "orion_spi", | ||
| 481 | .id = 1, | ||
| 482 | .resource = dove_spi1_resources, | ||
| 483 | .dev = { | ||
| 484 | .platform_data = &dove_spi1_data, | ||
| 485 | }, | ||
| 486 | .num_resources = ARRAY_SIZE(dove_spi1_resources), | ||
| 487 | }; | ||
| 488 | |||
| 489 | void __init dove_spi1_init(void) | ||
| 490 | { | ||
| 491 | platform_device_register(&dove_spi1); | ||
| 492 | } | ||
| 493 | |||
| 494 | /***************************************************************************** | ||
| 495 | * I2C | ||
| 496 | ****************************************************************************/ | ||
| 497 | static struct mv64xxx_i2c_pdata dove_i2c_data = { | ||
| 498 | .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ | ||
| 499 | .freq_n = 3, | ||
| 500 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 501 | }; | ||
| 502 | |||
| 503 | static struct resource dove_i2c_resources[] = { | ||
| 504 | { | ||
| 505 | .name = "i2c base", | ||
| 506 | .start = DOVE_I2C_PHYS_BASE, | ||
| 507 | .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, | ||
| 508 | .flags = IORESOURCE_MEM, | ||
| 509 | }, { | ||
| 510 | .name = "i2c irq", | ||
| 511 | .start = IRQ_DOVE_I2C, | ||
| 512 | .end = IRQ_DOVE_I2C, | ||
| 513 | .flags = IORESOURCE_IRQ, | ||
| 514 | }, | ||
| 515 | }; | ||
| 516 | |||
| 517 | static struct platform_device dove_i2c = { | ||
| 518 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 519 | .id = 0, | ||
| 520 | .num_resources = ARRAY_SIZE(dove_i2c_resources), | ||
| 521 | .resource = dove_i2c_resources, | ||
| 522 | .dev = { | ||
| 523 | .platform_data = &dove_i2c_data, | ||
| 524 | }, | ||
| 525 | }; | ||
| 526 | |||
| 527 | void __init dove_i2c_init(void) | ||
| 528 | { | ||
| 529 | platform_device_register(&dove_i2c); | ||
| 530 | } | ||
| 531 | |||
| 532 | /***************************************************************************** | ||
| 533 | * Time handling | ||
| 534 | ****************************************************************************/ | ||
| 535 | static int get_tclk(void) | ||
| 536 | { | ||
| 537 | /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ | ||
| 538 | return 166666667; | ||
| 539 | } | ||
| 540 | |||
| 541 | static void dove_timer_init(void) | ||
| 542 | { | ||
| 543 | orion_time_init(IRQ_DOVE_BRIDGE, get_tclk()); | ||
| 544 | } | ||
| 545 | |||
| 546 | struct sys_timer dove_timer = { | ||
| 547 | .init = dove_timer_init, | ||
| 548 | }; | ||
| 549 | |||
| 550 | /***************************************************************************** | ||
| 551 | * XOR | ||
| 552 | ****************************************************************************/ | ||
| 553 | static struct mv_xor_platform_shared_data dove_xor_shared_data = { | ||
| 554 | .dram = &dove_mbus_dram_info, | ||
| 555 | }; | ||
| 556 | |||
| 557 | /***************************************************************************** | ||
| 558 | * XOR 0 | ||
| 559 | ****************************************************************************/ | ||
| 560 | static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); | ||
| 561 | |||
| 562 | static struct resource dove_xor0_shared_resources[] = { | ||
| 563 | { | ||
| 564 | .name = "xor 0 low", | ||
| 565 | .start = DOVE_XOR0_PHYS_BASE, | ||
| 566 | .end = DOVE_XOR0_PHYS_BASE + 0xff, | ||
| 567 | .flags = IORESOURCE_MEM, | ||
| 568 | }, { | ||
| 569 | .name = "xor 0 high", | ||
| 570 | .start = DOVE_XOR0_HIGH_PHYS_BASE, | ||
| 571 | .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, | ||
| 572 | .flags = IORESOURCE_MEM, | ||
| 573 | }, | ||
| 574 | }; | ||
| 575 | |||
| 576 | static struct platform_device dove_xor0_shared = { | ||
| 577 | .name = MV_XOR_SHARED_NAME, | ||
| 578 | .id = 0, | ||
| 579 | .dev = { | ||
| 580 | .platform_data = &dove_xor_shared_data, | ||
| 581 | }, | ||
| 582 | .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), | ||
| 583 | .resource = dove_xor0_shared_resources, | ||
| 584 | }; | ||
| 585 | |||
| 586 | static struct resource dove_xor00_resources[] = { | ||
| 587 | [0] = { | ||
| 588 | .start = IRQ_DOVE_XOR_00, | ||
| 589 | .end = IRQ_DOVE_XOR_00, | ||
| 590 | .flags = IORESOURCE_IRQ, | ||
| 591 | }, | ||
| 592 | }; | ||
| 593 | |||
| 594 | static struct mv_xor_platform_data dove_xor00_data = { | ||
| 595 | .shared = &dove_xor0_shared, | ||
| 596 | .hw_id = 0, | ||
| 597 | .pool_size = PAGE_SIZE, | ||
| 598 | }; | ||
| 599 | |||
| 600 | static struct platform_device dove_xor00_channel = { | ||
| 601 | .name = MV_XOR_NAME, | ||
| 602 | .id = 0, | ||
| 603 | .num_resources = ARRAY_SIZE(dove_xor00_resources), | ||
| 604 | .resource = dove_xor00_resources, | ||
| 605 | .dev = { | ||
| 606 | .dma_mask = &dove_xor0_dmamask, | ||
| 607 | .coherent_dma_mask = DMA_BIT_MASK(64), | ||
| 608 | .platform_data = (void *)&dove_xor00_data, | ||
| 609 | }, | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct resource dove_xor01_resources[] = { | ||
| 613 | [0] = { | ||
| 614 | .start = IRQ_DOVE_XOR_01, | ||
| 615 | .end = IRQ_DOVE_XOR_01, | ||
| 616 | .flags = IORESOURCE_IRQ, | ||
| 617 | }, | ||
| 618 | }; | ||
| 619 | |||
| 620 | static struct mv_xor_platform_data dove_xor01_data = { | ||
| 621 | .shared = &dove_xor0_shared, | ||
| 622 | .hw_id = 1, | ||
| 623 | .pool_size = PAGE_SIZE, | ||
| 624 | }; | ||
| 625 | |||
| 626 | static struct platform_device dove_xor01_channel = { | ||
| 627 | .name = MV_XOR_NAME, | ||
| 628 | .id = 1, | ||
| 629 | .num_resources = ARRAY_SIZE(dove_xor01_resources), | ||
| 630 | .resource = dove_xor01_resources, | ||
| 631 | .dev = { | ||
| 632 | .dma_mask = &dove_xor0_dmamask, | ||
| 633 | .coherent_dma_mask = DMA_BIT_MASK(64), | ||
| 634 | .platform_data = (void *)&dove_xor01_data, | ||
| 635 | }, | ||
| 636 | }; | ||
| 637 | |||
| 638 | void __init dove_xor0_init(void) | ||
| 639 | { | ||
| 640 | platform_device_register(&dove_xor0_shared); | ||
| 641 | |||
| 642 | /* | ||
| 643 | * two engines can't do memset simultaneously, this limitation | ||
| 644 | * satisfied by removing memset support from one of the engines. | ||
| 645 | */ | ||
| 646 | dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); | ||
| 647 | dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); | ||
| 648 | platform_device_register(&dove_xor00_channel); | ||
| 649 | |||
| 650 | dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); | ||
| 651 | dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); | ||
| 652 | dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); | ||
| 653 | platform_device_register(&dove_xor01_channel); | ||
| 654 | } | ||
| 655 | |||
| 656 | /***************************************************************************** | ||
| 657 | * XOR 1 | ||
| 658 | ****************************************************************************/ | ||
| 659 | static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); | ||
| 660 | |||
| 661 | static struct resource dove_xor1_shared_resources[] = { | ||
| 662 | { | ||
| 663 | .name = "xor 0 low", | ||
| 664 | .start = DOVE_XOR1_PHYS_BASE, | ||
| 665 | .end = DOVE_XOR1_PHYS_BASE + 0xff, | ||
| 666 | .flags = IORESOURCE_MEM, | ||
| 667 | }, { | ||
| 668 | .name = "xor 0 high", | ||
| 669 | .start = DOVE_XOR1_HIGH_PHYS_BASE, | ||
| 670 | .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, | ||
| 671 | .flags = IORESOURCE_MEM, | ||
| 672 | }, | ||
| 673 | }; | ||
| 674 | |||
| 675 | static struct platform_device dove_xor1_shared = { | ||
| 676 | .name = MV_XOR_SHARED_NAME, | ||
| 677 | .id = 1, | ||
| 678 | .dev = { | ||
| 679 | .platform_data = &dove_xor_shared_data, | ||
| 680 | }, | ||
| 681 | .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), | ||
| 682 | .resource = dove_xor1_shared_resources, | ||
| 683 | }; | ||
| 684 | |||
| 685 | static struct resource dove_xor10_resources[] = { | ||
| 686 | [0] = { | ||
| 687 | .start = IRQ_DOVE_XOR_10, | ||
| 688 | .end = IRQ_DOVE_XOR_10, | ||
| 689 | .flags = IORESOURCE_IRQ, | ||
| 690 | }, | ||
| 691 | }; | ||
| 692 | |||
| 693 | static struct mv_xor_platform_data dove_xor10_data = { | ||
| 694 | .shared = &dove_xor1_shared, | ||
| 695 | .hw_id = 0, | ||
| 696 | .pool_size = PAGE_SIZE, | ||
| 697 | }; | ||
| 698 | |||
| 699 | static struct platform_device dove_xor10_channel = { | ||
| 700 | .name = MV_XOR_NAME, | ||
| 701 | .id = 2, | ||
| 702 | .num_resources = ARRAY_SIZE(dove_xor10_resources), | ||
| 703 | .resource = dove_xor10_resources, | ||
| 704 | .dev = { | ||
| 705 | .dma_mask = &dove_xor1_dmamask, | ||
| 706 | .coherent_dma_mask = DMA_BIT_MASK(64), | ||
| 707 | .platform_data = (void *)&dove_xor10_data, | ||
| 708 | }, | ||
| 709 | }; | ||
| 710 | |||
| 711 | static struct resource dove_xor11_resources[] = { | ||
| 712 | [0] = { | ||
| 713 | .start = IRQ_DOVE_XOR_11, | ||
| 714 | .end = IRQ_DOVE_XOR_11, | ||
| 715 | .flags = IORESOURCE_IRQ, | ||
| 716 | }, | ||
| 717 | }; | ||
| 718 | |||
| 719 | static struct mv_xor_platform_data dove_xor11_data = { | ||
| 720 | .shared = &dove_xor1_shared, | ||
| 721 | .hw_id = 1, | ||
| 722 | .pool_size = PAGE_SIZE, | ||
| 723 | }; | ||
| 724 | |||
| 725 | static struct platform_device dove_xor11_channel = { | ||
| 726 | .name = MV_XOR_NAME, | ||
| 727 | .id = 3, | ||
| 728 | .num_resources = ARRAY_SIZE(dove_xor11_resources), | ||
| 729 | .resource = dove_xor11_resources, | ||
| 730 | .dev = { | ||
| 731 | .dma_mask = &dove_xor1_dmamask, | ||
| 732 | .coherent_dma_mask = DMA_BIT_MASK(64), | ||
| 733 | .platform_data = (void *)&dove_xor11_data, | ||
| 734 | }, | ||
| 735 | }; | ||
| 736 | |||
| 737 | void __init dove_xor1_init(void) | ||
| 738 | { | ||
| 739 | platform_device_register(&dove_xor1_shared); | ||
| 740 | |||
| 741 | /* | ||
| 742 | * two engines can't do memset simultaneously, this limitation | ||
| 743 | * satisfied by removing memset support from one of the engines. | ||
| 744 | */ | ||
| 745 | dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); | ||
| 746 | dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); | ||
| 747 | platform_device_register(&dove_xor10_channel); | ||
| 748 | |||
| 749 | dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); | ||
| 750 | dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); | ||
| 751 | dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); | ||
| 752 | platform_device_register(&dove_xor11_channel); | ||
| 753 | } | ||
| 754 | |||
| 755 | void __init dove_init(void) | ||
| 756 | { | ||
| 757 | int tclk; | ||
| 758 | |||
| 759 | tclk = get_tclk(); | ||
| 760 | |||
| 761 | printk(KERN_INFO "Dove 88AP510 SoC, "); | ||
| 762 | printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); | ||
| 763 | |||
| 764 | #ifdef CONFIG_CACHE_TAUROS2 | ||
| 765 | tauros2_init(); | ||
| 766 | #endif | ||
| 767 | dove_setup_cpu_mbus(); | ||
| 768 | |||
| 769 | dove_ge00_shared_data.t_clk = tclk; | ||
| 770 | dove_uart0_data[0].uartclk = tclk; | ||
| 771 | dove_uart1_data[0].uartclk = tclk; | ||
| 772 | dove_uart2_data[0].uartclk = tclk; | ||
| 773 | dove_uart3_data[0].uartclk = tclk; | ||
| 774 | dove_spi0_data.tclk = tclk; | ||
| 775 | dove_spi1_data.tclk = tclk; | ||
| 776 | |||
| 777 | /* internal devices that every board has */ | ||
| 778 | dove_rtc_init(); | ||
| 779 | dove_xor0_init(); | ||
| 780 | dove_xor1_init(); | ||
| 781 | } | ||
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h new file mode 100644 index 000000000000..b29e8937de4f --- /dev/null +++ b/arch/arm/mach-dove/common.h | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/common.h | ||
| 3 | * | ||
| 4 | * Core functions for Marvell Dove 88AP510 System On Chip | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ARCH_DOVE_COMMON_H | ||
| 12 | #define __ARCH_DOVE_COMMON_H | ||
| 13 | |||
| 14 | struct mv643xx_eth_platform_data; | ||
| 15 | struct mv_sata_platform_data; | ||
| 16 | |||
| 17 | extern struct sys_timer dove_timer; | ||
| 18 | extern struct mbus_dram_target_info dove_mbus_dram_info; | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Basic Dove init functions used early by machine-setup. | ||
| 22 | */ | ||
| 23 | void dove_map_io(void); | ||
| 24 | void dove_init(void); | ||
| 25 | void dove_init_irq(void); | ||
| 26 | void dove_setup_cpu_mbus(void); | ||
| 27 | void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data); | ||
| 28 | void dove_sata_init(struct mv_sata_platform_data *sata_data); | ||
| 29 | void dove_pcie_init(int init_port0, int init_port1); | ||
| 30 | void dove_ehci0_init(void); | ||
| 31 | void dove_ehci1_init(void); | ||
| 32 | void dove_uart0_init(void); | ||
| 33 | void dove_uart1_init(void); | ||
| 34 | void dove_uart2_init(void); | ||
| 35 | void dove_uart3_init(void); | ||
| 36 | void dove_spi0_init(void); | ||
| 37 | void dove_spi1_init(void); | ||
| 38 | void dove_i2c_init(void); | ||
| 39 | |||
| 40 | #endif | ||
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c new file mode 100644 index 000000000000..f2971b745224 --- /dev/null +++ b/arch/arm/mach-dove/dove-db-setup.c | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/dove-db-setup.c | ||
| 3 | * | ||
| 4 | * Marvell DB-MV88AP510-BP Development Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/irq.h> | ||
| 15 | #include <linux/mtd/physmap.h> | ||
| 16 | #include <linux/mtd/nand.h> | ||
| 17 | #include <linux/timer.h> | ||
| 18 | #include <linux/ata_platform.h> | ||
| 19 | #include <linux/mv643xx_eth.h> | ||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/pci.h> | ||
| 22 | #include <linux/spi/spi.h> | ||
| 23 | #include <linux/spi/orion_spi.h> | ||
| 24 | #include <linux/spi/flash.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <asm/mach-types.h> | ||
| 27 | #include <asm/mach/arch.h> | ||
| 28 | #include <mach/dove.h> | ||
| 29 | #include "common.h" | ||
| 30 | |||
| 31 | static struct mv643xx_eth_platform_data dove_db_ge00_data = { | ||
| 32 | .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static struct mv_sata_platform_data dove_db_sata_data = { | ||
| 36 | .n_ports = 1, | ||
| 37 | }; | ||
| 38 | |||
| 39 | /***************************************************************************** | ||
| 40 | * SPI Devices: | ||
| 41 | * SPI0: 4M Flash ST-M25P32-VMF6P | ||
| 42 | ****************************************************************************/ | ||
| 43 | static const struct flash_platform_data dove_db_spi_flash_data = { | ||
| 44 | .type = "m25p64", | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct spi_board_info __initdata dove_db_spi_flash_info[] = { | ||
| 48 | { | ||
| 49 | .modalias = "m25p80", | ||
| 50 | .platform_data = &dove_db_spi_flash_data, | ||
| 51 | .irq = -1, | ||
| 52 | .max_speed_hz = 20000000, | ||
| 53 | .bus_num = 0, | ||
| 54 | .chip_select = 0, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | /***************************************************************************** | ||
| 59 | * PCI | ||
| 60 | ****************************************************************************/ | ||
| 61 | static int __init dove_db_pci_init(void) | ||
| 62 | { | ||
| 63 | if (machine_is_dove_db()) | ||
| 64 | dove_pcie_init(1, 1); | ||
| 65 | |||
| 66 | return 0; | ||
| 67 | } | ||
| 68 | |||
| 69 | subsys_initcall(dove_db_pci_init); | ||
| 70 | |||
| 71 | /***************************************************************************** | ||
| 72 | * Board Init | ||
| 73 | ****************************************************************************/ | ||
| 74 | static void __init dove_db_init(void) | ||
| 75 | { | ||
| 76 | /* | ||
| 77 | * Basic Dove setup. Needs to be called early. | ||
| 78 | */ | ||
| 79 | dove_init(); | ||
| 80 | |||
| 81 | dove_ge00_init(&dove_db_ge00_data); | ||
| 82 | dove_ehci0_init(); | ||
| 83 | dove_ehci1_init(); | ||
| 84 | dove_sata_init(&dove_db_sata_data); | ||
| 85 | dove_spi0_init(); | ||
| 86 | dove_spi1_init(); | ||
| 87 | dove_uart0_init(); | ||
| 88 | dove_uart1_init(); | ||
| 89 | dove_i2c_init(); | ||
| 90 | spi_register_board_info(dove_db_spi_flash_info, | ||
| 91 | ARRAY_SIZE(dove_db_spi_flash_info)); | ||
| 92 | } | ||
| 93 | |||
| 94 | MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") | ||
| 95 | .phys_io = DOVE_SB_REGS_PHYS_BASE, | ||
| 96 | .io_pg_offst = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 97 | .boot_params = 0x00000100, | ||
| 98 | .init_machine = dove_db_init, | ||
| 99 | .map_io = dove_map_io, | ||
| 100 | .init_irq = dove_init_irq, | ||
| 101 | .timer = &dove_timer, | ||
| 102 | MACHINE_END | ||
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h new file mode 100644 index 000000000000..214a4c31f069 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/bridge-regs.h | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/bridge-regs.h | ||
| 3 | * | ||
| 4 | * Mbus-L to Mbus Bridge Registers | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_BRIDGE_REGS_H | ||
| 12 | #define __ASM_ARCH_BRIDGE_REGS_H | ||
| 13 | |||
| 14 | #include <mach/dove.h> | ||
| 15 | |||
| 16 | #define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) | ||
| 17 | |||
| 18 | #define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) | ||
| 19 | #define CPU_CTRL_PCIE0_LINK 0x00000001 | ||
| 20 | #define CPU_RESET 0x00000002 | ||
| 21 | #define CPU_CTRL_PCIE1_LINK 0x00000008 | ||
| 22 | |||
| 23 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) | ||
| 24 | #define SOFT_RESET_OUT_EN 0x00000004 | ||
| 25 | |||
| 26 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) | ||
| 27 | #define SOFT_RESET 0x00000001 | ||
| 28 | |||
| 29 | #define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) | ||
| 30 | #define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114) | ||
| 31 | #define BRIDGE_INT_TIMER0 0x0002 | ||
| 32 | #define BRIDGE_INT_TIMER1 0x0004 | ||
| 33 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) | ||
| 34 | |||
| 35 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) | ||
| 36 | #define IRQ_CAUSE_LOW_OFF 0x0000 | ||
| 37 | #define IRQ_MASK_LOW_OFF 0x0004 | ||
| 38 | #define FIQ_MASK_LOW_OFF 0x0008 | ||
| 39 | #define ENDPOINT_MASK_LOW_OFF 0x000c | ||
| 40 | #define IRQ_CAUSE_HIGH_OFF 0x0010 | ||
| 41 | #define IRQ_MASK_HIGH_OFF 0x0014 | ||
| 42 | #define FIQ_MASK_HIGH_OFF 0x0018 | ||
| 43 | #define ENDPOINT_MASK_HIGH_OFF 0x001c | ||
| 44 | #define PCIE_INTERRUPT_MASK_OFF 0x0020 | ||
| 45 | |||
| 46 | #define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) | ||
| 47 | #define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) | ||
| 48 | #define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) | ||
| 49 | #define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) | ||
| 50 | #define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) | ||
| 51 | #define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) | ||
| 52 | #define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) | ||
| 53 | |||
| 54 | #define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) | ||
| 55 | |||
| 56 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | ||
| 57 | |||
| 58 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S new file mode 100644 index 000000000000..9b89ec7d3040 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/debug-macro.S | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/debug-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/bridge-regs.h> | ||
| 10 | |||
| 11 | .macro addruart,rx | ||
| 12 | mrc p15, 0, \rx, c1, c0 | ||
| 13 | tst \rx, #1 @ MMU enabled? | ||
| 14 | ldreq \rx, =DOVE_SB_REGS_PHYS_BASE | ||
| 15 | ldrne \rx, =DOVE_SB_REGS_VIRT_BASE | ||
| 16 | orr \rx, \rx, #0x00012000 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | #define UART_SHIFT 2 | ||
| 20 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h new file mode 100644 index 000000000000..f6a08397f046 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/dove.h | |||
| @@ -0,0 +1,180 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/dove.h | ||
| 3 | * | ||
| 4 | * Generic definitions for Marvell Dove 88AP510 SoC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_DOVE_H | ||
| 12 | #define __ASM_ARCH_DOVE_H | ||
| 13 | |||
| 14 | #include <mach/vmalloc.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * Marvell Dove address maps. | ||
| 18 | * | ||
| 19 | * phys virt size | ||
| 20 | * c8000000 fdb00000 1M Cryptographic SRAM | ||
| 21 | * e0000000 @runtime 128M PCIe-0 Memory space | ||
| 22 | * e8000000 @runtime 128M PCIe-1 Memory space | ||
| 23 | * f1000000 fde00000 8M on-chip south-bridge registers | ||
| 24 | * f1800000 fe600000 8M on-chip north-bridge registers | ||
| 25 | * f2000000 fee00000 1M PCIe-0 I/O space | ||
| 26 | * f2100000 fef00000 1M PCIe-1 I/O space | ||
| 27 | */ | ||
| 28 | |||
| 29 | #define DOVE_CESA_PHYS_BASE 0xc8000000 | ||
| 30 | #define DOVE_CESA_VIRT_BASE 0xfdb00000 | ||
| 31 | #define DOVE_CESA_SIZE SZ_1M | ||
| 32 | |||
| 33 | #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 | ||
| 34 | #define DOVE_PCIE0_MEM_SIZE SZ_128M | ||
| 35 | |||
| 36 | #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 | ||
| 37 | #define DOVE_PCIE1_MEM_SIZE SZ_128M | ||
| 38 | |||
| 39 | #define DOVE_BOOTROM_PHYS_BASE 0xf8000000 | ||
| 40 | #define DOVE_BOOTROM_SIZE SZ_128M | ||
| 41 | |||
| 42 | #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 | ||
| 43 | #define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 | ||
| 44 | #define DOVE_SCRATCHPAD_SIZE SZ_1M | ||
| 45 | |||
| 46 | #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 | ||
| 47 | #define DOVE_SB_REGS_VIRT_BASE 0xfde00000 | ||
| 48 | #define DOVE_SB_REGS_SIZE SZ_8M | ||
| 49 | |||
| 50 | #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 | ||
| 51 | #define DOVE_NB_REGS_VIRT_BASE 0xfe600000 | ||
| 52 | #define DOVE_NB_REGS_SIZE SZ_8M | ||
| 53 | |||
| 54 | #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 | ||
| 55 | #define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 | ||
| 56 | #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 | ||
| 57 | #define DOVE_PCIE0_IO_SIZE SZ_1M | ||
| 58 | |||
| 59 | #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 | ||
| 60 | #define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 | ||
| 61 | #define DOVE_PCIE1_IO_BUS_BASE 0x00100000 | ||
| 62 | #define DOVE_PCIE1_IO_SIZE SZ_1M | ||
| 63 | |||
| 64 | /* | ||
| 65 | * Dove Core Registers Map | ||
| 66 | */ | ||
| 67 | |||
| 68 | /* SPI, I2C, UART */ | ||
| 69 | #define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) | ||
| 70 | #define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) | ||
| 71 | #define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) | ||
| 72 | #define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) | ||
| 73 | #define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) | ||
| 74 | #define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) | ||
| 75 | #define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) | ||
| 76 | #define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) | ||
| 77 | #define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) | ||
| 78 | #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) | ||
| 79 | #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) | ||
| 80 | |||
| 81 | /* North-South Bridge */ | ||
| 82 | #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) | ||
| 83 | |||
| 84 | /* Cryptographic Engine */ | ||
| 85 | #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) | ||
| 86 | |||
| 87 | /* PCIe 0 */ | ||
| 88 | #define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) | ||
| 89 | |||
| 90 | /* USB */ | ||
| 91 | #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) | ||
| 92 | #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) | ||
| 93 | |||
| 94 | /* XOR 0 Engine */ | ||
| 95 | #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) | ||
| 96 | #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) | ||
| 97 | #define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) | ||
| 98 | #define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) | ||
| 99 | |||
| 100 | /* XOR 1 Engine */ | ||
| 101 | #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) | ||
| 102 | #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) | ||
| 103 | #define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) | ||
| 104 | #define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) | ||
| 105 | |||
| 106 | /* Gigabit Ethernet */ | ||
| 107 | #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) | ||
| 108 | |||
| 109 | /* PCIe 1 */ | ||
| 110 | #define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) | ||
| 111 | |||
| 112 | /* CAFE */ | ||
| 113 | #define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) | ||
| 114 | #define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) | ||
| 115 | #define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) | ||
| 116 | #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) | ||
| 117 | |||
| 118 | /* SATA */ | ||
| 119 | #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) | ||
| 120 | |||
| 121 | /* I2S/SPDIF */ | ||
| 122 | #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) | ||
| 123 | #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) | ||
| 124 | |||
| 125 | /* NAND Flash Controller */ | ||
| 126 | #define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) | ||
| 127 | |||
| 128 | /* MPP, GPIO, Reset Sampling */ | ||
| 129 | #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) | ||
| 130 | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) | ||
| 131 | #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) | ||
| 132 | #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) | ||
| 133 | #define DOVE_GPIO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) | ||
| 134 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) | ||
| 135 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) | ||
| 136 | #define DOVE_NAND_GPIO_EN (1 << 0) | ||
| 137 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_VIRT_BASE + 0x40) | ||
| 138 | |||
| 139 | |||
| 140 | /* Power Management */ | ||
| 141 | #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) | ||
| 142 | |||
| 143 | /* Real Time Clock */ | ||
| 144 | #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) | ||
| 145 | |||
| 146 | /* AC97 */ | ||
| 147 | #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) | ||
| 148 | #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) | ||
| 149 | |||
| 150 | /* Peripheral DMA */ | ||
| 151 | #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) | ||
| 152 | #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) | ||
| 153 | |||
| 154 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) | ||
| 155 | #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) | ||
| 156 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) | ||
| 157 | #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) | ||
| 158 | #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) | ||
| 159 | #define DOVE_TWSI_OPTION3_GPIO (1 << 22) | ||
| 160 | #define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) | ||
| 161 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) | ||
| 162 | #define DOVE_SSP_ON_AU1 (1 << 0) | ||
| 163 | #define DOVE_SSP_CLOCK_ENABLE (1 << 1) | ||
| 164 | #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) | ||
| 165 | /* Memory Controller */ | ||
| 166 | #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) | ||
| 167 | |||
| 168 | /* LCD Controller */ | ||
| 169 | #define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) | ||
| 170 | #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) | ||
| 171 | #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) | ||
| 172 | #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) | ||
| 173 | |||
| 174 | /* Graphic Engine */ | ||
| 175 | #define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) | ||
| 176 | |||
| 177 | /* Video Engine */ | ||
| 178 | #define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) | ||
| 179 | |||
| 180 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S new file mode 100644 index 000000000000..e84c78c2a8b7 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/entry-macro.S | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for Marvell Dove platforms | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <mach/bridge-regs.h> | ||
| 12 | |||
| 13 | .macro disable_fiq | ||
| 14 | .endm | ||
| 15 | |||
| 16 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 17 | .endm | ||
| 18 | |||
| 19 | .macro get_irqnr_preamble, base, tmp | ||
| 20 | ldr \base, =IRQ_VIRT_BASE | ||
| 21 | .endm | ||
| 22 | |||
| 23 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 24 | @ check low interrupts | ||
| 25 | ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] | ||
| 26 | ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] | ||
| 27 | mov \irqnr, #31 | ||
| 28 | ands \irqstat, \irqstat, \tmp | ||
| 29 | |||
| 30 | @ if no low interrupts set, check high interrupts | ||
| 31 | ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] | ||
| 32 | ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] | ||
| 33 | moveq \irqnr, #63 | ||
| 34 | andeqs \irqstat, \irqstat, \tmp | ||
| 35 | |||
| 36 | @ find first active interrupt source | ||
| 37 | clzne \irqstat, \irqstat | ||
| 38 | subne \irqnr, \irqnr, \irqstat | ||
| 39 | .endm | ||
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h new file mode 100644 index 000000000000..0ee70ff39e11 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/gpio.h | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/gpio.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_GPIO_H | ||
| 10 | #define __ASM_ARCH_GPIO_H | ||
| 11 | |||
| 12 | #include <asm/errno.h> | ||
| 13 | #include <mach/irqs.h> | ||
| 14 | #include <plat/gpio.h> | ||
| 15 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | ||
| 16 | |||
| 17 | #define GPIO_MAX 64 | ||
| 18 | |||
| 19 | #define GPIO_BASE_LO (DOVE_GPIO_VIRT_BASE + 0x00) | ||
| 20 | #define GPIO_BASE_HI (DOVE_GPIO_VIRT_BASE + 0x20) | ||
| 21 | |||
| 22 | #define GPIO_BASE(pin) ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI) | ||
| 23 | |||
| 24 | #define GPIO_OUT(pin) (GPIO_BASE(pin) + 0x00) | ||
| 25 | #define GPIO_IO_CONF(pin) (GPIO_BASE(pin) + 0x04) | ||
| 26 | #define GPIO_BLINK_EN(pin) (GPIO_BASE(pin) + 0x08) | ||
| 27 | #define GPIO_IN_POL(pin) (GPIO_BASE(pin) + 0x0c) | ||
| 28 | #define GPIO_DATA_IN(pin) (GPIO_BASE(pin) + 0x10) | ||
| 29 | #define GPIO_EDGE_CAUSE(pin) (GPIO_BASE(pin) + 0x14) | ||
| 30 | #define GPIO_EDGE_MASK(pin) (GPIO_BASE(pin) + 0x18) | ||
| 31 | #define GPIO_LEVEL_MASK(pin) (GPIO_BASE(pin) + 0x1c) | ||
| 32 | |||
| 33 | static inline int gpio_to_irq(int pin) | ||
| 34 | { | ||
| 35 | if (pin < NR_GPIO_IRQS) | ||
| 36 | return pin + IRQ_DOVE_GPIO_START; | ||
| 37 | |||
| 38 | return -EINVAL; | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline int irq_to_gpio(int irq) | ||
| 42 | { | ||
| 43 | if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS) | ||
| 44 | return irq - IRQ_DOVE_GPIO_START; | ||
| 45 | |||
| 46 | return -EINVAL; | ||
| 47 | } | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h new file mode 100644 index 000000000000..32b0826e7873 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/hardware.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/hardware.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 10 | #define __ASM_ARCH_HARDWARE_H | ||
| 11 | |||
| 12 | #include "dove.h" | ||
| 13 | |||
| 14 | #define pcibios_assign_all_busses() 1 | ||
| 15 | |||
| 16 | #define PCIBIOS_MIN_IO 0x1000 | ||
| 17 | #define PCIBIOS_MIN_MEM 0x01000000 | ||
| 18 | #define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE | ||
| 19 | |||
| 20 | |||
| 21 | /* Macros below are required for compatibility with PXA AC'97 driver. */ | ||
| 22 | #define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \ | ||
| 23 | DOVE_SB_REGS_VIRT_BASE))) | ||
| 24 | #define __PREG(x) (((u32)&(x)) - DOVE_SB_REGS_VIRT_BASE + \ | ||
| 25 | DOVE_SB_REGS_PHYS_BASE) | ||
| 26 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h new file mode 100644 index 000000000000..3b3e4721ce2e --- /dev/null +++ b/arch/arm/mach-dove/include/mach/io.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/io.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_IO_H | ||
| 10 | #define __ASM_ARCH_IO_H | ||
| 11 | |||
| 12 | #include "dove.h" | ||
| 13 | |||
| 14 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 15 | |||
| 16 | #define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\ | ||
| 17 | DOVE_PCIE0_IO_VIRT_BASE)) | ||
| 18 | #define __mem_pci(a) (a) | ||
| 19 | |||
| 20 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h new file mode 100644 index 000000000000..46681466f92b --- /dev/null +++ b/arch/arm/mach-dove/include/mach/irqs.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/irqs.h | ||
| 3 | * | ||
| 4 | * IRQ definitions for Marvell Dove 88AP510 SoC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_IRQS_H | ||
| 12 | #define __ASM_ARCH_IRQS_H | ||
| 13 | |||
| 14 | /* | ||
| 15 | * Dove Low Interrupt Controller | ||
| 16 | */ | ||
| 17 | #define IRQ_DOVE_BRIDGE 0 | ||
| 18 | #define IRQ_DOVE_H2C 1 | ||
| 19 | #define IRQ_DOVE_C2H 2 | ||
| 20 | #define IRQ_DOVE_NAND 3 | ||
| 21 | #define IRQ_DOVE_PDMA 4 | ||
| 22 | #define IRQ_DOVE_SPI1 5 | ||
| 23 | #define IRQ_DOVE_SPI0 6 | ||
| 24 | #define IRQ_DOVE_UART_0 7 | ||
| 25 | #define IRQ_DOVE_UART_1 8 | ||
| 26 | #define IRQ_DOVE_UART_2 9 | ||
| 27 | #define IRQ_DOVE_UART_3 10 | ||
| 28 | #define IRQ_DOVE_I2C 11 | ||
| 29 | #define IRQ_DOVE_GPIO_0_7 12 | ||
| 30 | #define IRQ_DOVE_GPIO_8_15 13 | ||
| 31 | #define IRQ_DOVE_GPIO_16_23 14 | ||
| 32 | #define IRQ_DOVE_PCIE0_ERR 15 | ||
| 33 | #define IRQ_DOVE_PCIE0 16 | ||
| 34 | #define IRQ_DOVE_PCIE1_ERR 17 | ||
| 35 | #define IRQ_DOVE_PCIE1 18 | ||
| 36 | #define IRQ_DOVE_I2S0 19 | ||
| 37 | #define IRQ_DOVE_I2S0_ERR 20 | ||
| 38 | #define IRQ_DOVE_I2S1 21 | ||
| 39 | #define IRQ_DOVE_I2S1_ERR 22 | ||
| 40 | #define IRQ_DOVE_USB_ERR 23 | ||
| 41 | #define IRQ_DOVE_USB0 24 | ||
| 42 | #define IRQ_DOVE_USB1 25 | ||
| 43 | #define IRQ_DOVE_GE00_RX 26 | ||
| 44 | #define IRQ_DOVE_GE00_TX 27 | ||
| 45 | #define IRQ_DOVE_GE00_MISC 28 | ||
| 46 | #define IRQ_DOVE_GE00_SUM 29 | ||
| 47 | #define IRQ_DOVE_GE00_ERR 30 | ||
| 48 | #define IRQ_DOVE_CRYPTO 31 | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Dove High Interrupt Controller | ||
| 52 | */ | ||
| 53 | #define IRQ_DOVE_AC97 32 | ||
| 54 | #define IRQ_DOVE_PMU 33 | ||
| 55 | #define IRQ_DOVE_CAM 34 | ||
| 56 | #define IRQ_DOVE_SDIO0 35 | ||
| 57 | #define IRQ_DOVE_SDIO1 36 | ||
| 58 | #define IRQ_DOVE_SDIO0_WAKEUP 37 | ||
| 59 | #define IRQ_DOVE_SDIO1_WAKEUP 38 | ||
| 60 | #define IRQ_DOVE_XOR_00 39 | ||
| 61 | #define IRQ_DOVE_XOR_01 40 | ||
| 62 | #define IRQ_DOVE_XOR0_ERR 41 | ||
| 63 | #define IRQ_DOVE_XOR_10 42 | ||
| 64 | #define IRQ_DOVE_XOR_11 43 | ||
| 65 | #define IRQ_DOVE_XOR1_ERR 44 | ||
| 66 | #define IRQ_DOVE_LCD_DCON 45 | ||
| 67 | #define IRQ_DOVE_LCD1 46 | ||
| 68 | #define IRQ_DOVE_LCD0 47 | ||
| 69 | #define IRQ_DOVE_GPU 48 | ||
| 70 | #define IRQ_DOVE_PERFORM_MNTR 49 | ||
| 71 | #define IRQ_DOVE_VPRO_DMA1 51 | ||
| 72 | #define IRQ_DOVE_SSP_TIMER 54 | ||
| 73 | #define IRQ_DOVE_SSP 55 | ||
| 74 | #define IRQ_DOVE_MC_L2_ERR 56 | ||
| 75 | #define IRQ_DOVE_CRYPTO_ERR 59 | ||
| 76 | #define IRQ_DOVE_GPIO_24_31 60 | ||
| 77 | #define IRQ_DOVE_HIGH_GPIO 61 | ||
| 78 | #define IRQ_DOVE_SATA 62 | ||
| 79 | |||
| 80 | /* | ||
| 81 | * DOVE General Purpose Pins | ||
| 82 | */ | ||
| 83 | #define IRQ_DOVE_GPIO_START 64 | ||
| 84 | #define NR_GPIO_IRQS 64 | ||
| 85 | |||
| 86 | /* | ||
| 87 | * PMU interrupts | ||
| 88 | */ | ||
| 89 | #define IRQ_DOVE_PMU_START (IRQ_DOVE_GPIO_START + NR_GPIO_IRQS) | ||
| 90 | #define NR_PMU_IRQS 7 | ||
| 91 | #define IRQ_DOVE_RTC (IRQ_DOVE_PMU_START + 5) | ||
| 92 | |||
| 93 | #define NR_IRQS (IRQ_DOVE_PMU_START + NR_PMU_IRQS) | ||
| 94 | |||
| 95 | /* Required for compatability with PXA AC97 driver. */ | ||
| 96 | #define IRQ_AC97 IRQ_DOVE_AC97 | ||
| 97 | /* Required for compatability with PXA DMA driver. */ | ||
| 98 | #define IRQ_DMA IRQ_DOVE_PDMA | ||
| 99 | /* Required for compatability with PXA NAND driver */ | ||
| 100 | #define IRQ_NAND IRQ_DOVE_NAND | ||
| 101 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h new file mode 100644 index 000000000000..d66872074946 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/memory.h | |||
| @@ -0,0 +1,10 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/memory.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 6 | #define __ASM_ARCH_MEMORY_H | ||
| 7 | |||
| 8 | #define PHYS_OFFSET UL(0x00000000) | ||
| 9 | |||
| 10 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h new file mode 100644 index 000000000000..3ad9f946a9e8 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/pm.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/pm.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_PM_H | ||
| 10 | #define __ASM_ARCH_PM_H | ||
| 11 | |||
| 12 | #include <asm/errno.h> | ||
| 13 | #include <mach/irqs.h> | ||
| 14 | |||
| 15 | #define CLOCK_GATING_CONTROL (DOVE_PMU_VIRT_BASE + 0x38) | ||
| 16 | #define CLOCK_GATING_USB0_MASK (1 << 0) | ||
| 17 | #define CLOCK_GATING_USB1_MASK (1 << 1) | ||
| 18 | #define CLOCK_GATING_GBE_MASK (1 << 2) | ||
| 19 | #define CLOCK_GATING_SATA_MASK (1 << 3) | ||
| 20 | #define CLOCK_GATING_PCIE0_MASK (1 << 4) | ||
| 21 | #define CLOCK_GATING_PCIE1_MASK (1 << 5) | ||
| 22 | #define CLOCK_GATING_SDIO0_MASK (1 << 8) | ||
| 23 | #define CLOCK_GATING_SDIO1_MASK (1 << 9) | ||
| 24 | #define CLOCK_GATING_NAND_MASK (1 << 10) | ||
| 25 | #define CLOCK_GATING_CAMERA_MASK (1 << 11) | ||
| 26 | #define CLOCK_GATING_I2S0_MASK (1 << 12) | ||
| 27 | #define CLOCK_GATING_I2S1_MASK (1 << 13) | ||
| 28 | #define CLOCK_GATING_CRYPTO_MASK (1 << 15) | ||
| 29 | #define CLOCK_GATING_AC97_MASK (1 << 21) | ||
| 30 | #define CLOCK_GATING_PDMA_MASK (1 << 22) | ||
| 31 | #define CLOCK_GATING_XOR0_MASK (1 << 23) | ||
| 32 | #define CLOCK_GATING_XOR1_MASK (1 << 24) | ||
| 33 | #define CLOCK_GATING_GIGA_PHY_MASK (1 << 30) | ||
| 34 | |||
| 35 | #define PMU_INTERRUPT_CAUSE (DOVE_PMU_VIRT_BASE + 0x50) | ||
| 36 | #define PMU_INTERRUPT_MASK (DOVE_PMU_VIRT_BASE + 0x54) | ||
| 37 | |||
| 38 | static inline int pmu_to_irq(int pin) | ||
| 39 | { | ||
| 40 | if (pin < NR_PMU_IRQS) | ||
| 41 | return pin + IRQ_DOVE_PMU_START; | ||
| 42 | |||
| 43 | return -EINVAL; | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline int irq_to_pmu(int irq) | ||
| 47 | { | ||
| 48 | if (IRQ_DOVE_PMU_START < irq && irq < NR_IRQS) | ||
| 49 | return irq - IRQ_DOVE_PMU_START; | ||
| 50 | |||
| 51 | return -EINVAL; | ||
| 52 | } | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h new file mode 100644 index 000000000000..356afda56853 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/system.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/system.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 10 | #define __ASM_ARCH_SYSTEM_H | ||
| 11 | |||
| 12 | #include <mach/bridge-regs.h> | ||
| 13 | |||
| 14 | static inline void arch_idle(void) | ||
| 15 | { | ||
| 16 | cpu_do_idle(); | ||
| 17 | } | ||
| 18 | |||
| 19 | static inline void arch_reset(char mode, const char *cmd) | ||
| 20 | { | ||
| 21 | /* | ||
| 22 | * Enable soft reset to assert RSTOUTn. | ||
| 23 | */ | ||
| 24 | writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK); | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Assert soft reset. | ||
| 28 | */ | ||
| 29 | writel(SOFT_RESET, SYSTEM_SOFT_RESET); | ||
| 30 | |||
| 31 | while (1) | ||
| 32 | ; | ||
| 33 | } | ||
| 34 | |||
| 35 | |||
| 36 | #endif | ||
diff --git a/arch/arm/mach-dove/include/mach/timex.h b/arch/arm/mach-dove/include/mach/timex.h new file mode 100644 index 000000000000..251d538541db --- /dev/null +++ b/arch/arm/mach-dove/include/mach/timex.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE (100 * HZ) | ||
diff --git a/arch/arm/mach-dove/include/mach/uncompress.h b/arch/arm/mach-dove/include/mach/uncompress.h new file mode 100644 index 000000000000..2c5cdd7a3eed --- /dev/null +++ b/arch/arm/mach-dove/include/mach/uncompress.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/dove.h> | ||
| 10 | |||
| 11 | #define UART_THR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x0)) | ||
| 12 | #define UART_LSR ((volatile unsigned char *)(DOVE_UART0_PHYS_BASE + 0x14)) | ||
| 13 | |||
| 14 | #define LSR_THRE 0x20 | ||
| 15 | |||
| 16 | static void putc(const char c) | ||
| 17 | { | ||
| 18 | int i; | ||
| 19 | |||
| 20 | for (i = 0; i < 0x1000; i++) { | ||
| 21 | /* Transmit fifo not full? */ | ||
| 22 | if (*UART_LSR & LSR_THRE) | ||
| 23 | break; | ||
| 24 | } | ||
| 25 | |||
| 26 | *UART_THR = c; | ||
| 27 | } | ||
| 28 | |||
| 29 | static void flush(void) | ||
| 30 | { | ||
| 31 | } | ||
| 32 | |||
| 33 | /* | ||
| 34 | * nothing to do | ||
| 35 | */ | ||
| 36 | #define arch_decomp_setup() | ||
| 37 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h new file mode 100644 index 000000000000..8b2c974755c6 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/vmalloc.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/include/mach/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfd800000 | ||
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c new file mode 100644 index 000000000000..61bfcb3b08c2 --- /dev/null +++ b/arch/arm/mach-dove/irq.c | |||
| @@ -0,0 +1,133 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/irq.c | ||
| 3 | * | ||
| 4 | * Dove IRQ handling. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/irq.h> | ||
| 14 | #include <linux/gpio.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <asm/mach/arch.h> | ||
| 17 | #include <plat/irq.h> | ||
| 18 | #include <asm/mach/irq.h> | ||
| 19 | #include <mach/pm.h> | ||
| 20 | #include <mach/bridge-regs.h> | ||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
| 24 | { | ||
| 25 | int irqoff; | ||
| 26 | BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO); | ||
| 27 | |||
| 28 | irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 : | ||
| 29 | 3 + irq - IRQ_DOVE_GPIO_24_31; | ||
| 30 | |||
| 31 | orion_gpio_irq_handler(irqoff << 3); | ||
| 32 | if (irq == IRQ_DOVE_HIGH_GPIO) { | ||
| 33 | orion_gpio_irq_handler(40); | ||
| 34 | orion_gpio_irq_handler(48); | ||
| 35 | orion_gpio_irq_handler(56); | ||
| 36 | } | ||
| 37 | } | ||
| 38 | |||
| 39 | static void pmu_irq_mask(unsigned int irq) | ||
| 40 | { | ||
| 41 | int pin = irq_to_pmu(irq); | ||
| 42 | u32 u; | ||
| 43 | |||
| 44 | u = readl(PMU_INTERRUPT_MASK); | ||
| 45 | u &= ~(1 << (pin & 31)); | ||
| 46 | writel(u, PMU_INTERRUPT_MASK); | ||
| 47 | } | ||
| 48 | |||
| 49 | static void pmu_irq_unmask(unsigned int irq) | ||
| 50 | { | ||
| 51 | int pin = irq_to_pmu(irq); | ||
| 52 | u32 u; | ||
| 53 | |||
| 54 | u = readl(PMU_INTERRUPT_MASK); | ||
| 55 | u |= 1 << (pin & 31); | ||
| 56 | writel(u, PMU_INTERRUPT_MASK); | ||
| 57 | } | ||
| 58 | |||
| 59 | static void pmu_irq_ack(unsigned int irq) | ||
| 60 | { | ||
| 61 | int pin = irq_to_pmu(irq); | ||
| 62 | u32 u; | ||
| 63 | |||
| 64 | u = ~(1 << (pin & 31)); | ||
| 65 | writel(u, PMU_INTERRUPT_CAUSE); | ||
| 66 | } | ||
| 67 | |||
| 68 | static struct irq_chip pmu_irq_chip = { | ||
| 69 | .name = "pmu_irq", | ||
| 70 | .mask = pmu_irq_mask, | ||
| 71 | .unmask = pmu_irq_unmask, | ||
| 72 | .ack = pmu_irq_ack, | ||
| 73 | }; | ||
| 74 | |||
| 75 | static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc) | ||
| 76 | { | ||
| 77 | unsigned long cause = readl(PMU_INTERRUPT_CAUSE); | ||
| 78 | |||
| 79 | cause &= readl(PMU_INTERRUPT_MASK); | ||
| 80 | if (cause == 0) { | ||
| 81 | do_bad_IRQ(irq, desc); | ||
| 82 | return; | ||
| 83 | } | ||
| 84 | |||
| 85 | for (irq = 0; irq < NR_PMU_IRQS; irq++) { | ||
| 86 | if (!(cause & (1 << irq))) | ||
| 87 | continue; | ||
| 88 | irq = pmu_to_irq(irq); | ||
| 89 | desc = irq_desc + irq; | ||
| 90 | desc_handle_irq(irq, desc); | ||
| 91 | } | ||
| 92 | } | ||
| 93 | |||
| 94 | void __init dove_init_irq(void) | ||
| 95 | { | ||
| 96 | int i; | ||
| 97 | |||
| 98 | orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); | ||
| 99 | orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); | ||
| 100 | |||
| 101 | /* | ||
| 102 | * Mask and clear GPIO IRQ interrupts. | ||
| 103 | */ | ||
| 104 | writel(0, GPIO_LEVEL_MASK(0)); | ||
| 105 | writel(0, GPIO_EDGE_MASK(0)); | ||
| 106 | writel(0, GPIO_EDGE_CAUSE(0)); | ||
| 107 | |||
| 108 | /* | ||
| 109 | * Mask and clear PMU interrupts | ||
| 110 | */ | ||
| 111 | writel(0, PMU_INTERRUPT_MASK); | ||
| 112 | writel(0, PMU_INTERRUPT_CAUSE); | ||
| 113 | |||
| 114 | for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) { | ||
| 115 | set_irq_chip(i, &orion_gpio_irq_chip); | ||
| 116 | set_irq_handler(i, handle_level_irq); | ||
| 117 | irq_desc[i].status |= IRQ_LEVEL; | ||
| 118 | set_irq_flags(i, IRQF_VALID); | ||
| 119 | } | ||
| 120 | set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); | ||
| 121 | set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); | ||
| 122 | set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); | ||
| 123 | set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); | ||
| 124 | set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); | ||
| 125 | |||
| 126 | for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { | ||
| 127 | set_irq_chip(i, &pmu_irq_chip); | ||
| 128 | set_irq_handler(i, handle_level_irq); | ||
| 129 | irq_desc[i].status |= IRQ_LEVEL; | ||
| 130 | set_irq_flags(i, IRQF_VALID); | ||
| 131 | } | ||
| 132 | set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); | ||
| 133 | } | ||
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c new file mode 100644 index 000000000000..502d1ca2f4b7 --- /dev/null +++ b/arch/arm/mach-dove/pcie.c | |||
| @@ -0,0 +1,238 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-dove/pcie.c | ||
| 3 | * | ||
| 4 | * PCIe functions for Marvell Dove 88AP510 SoC | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/pci.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <asm/mach/pci.h> | ||
| 15 | #include <asm/mach/arch.h> | ||
| 16 | #include <asm/setup.h> | ||
| 17 | #include <asm/delay.h> | ||
| 18 | #include <plat/pcie.h> | ||
| 19 | #include <mach/irqs.h> | ||
| 20 | #include <mach/bridge-regs.h> | ||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | struct pcie_port { | ||
| 24 | u8 index; | ||
| 25 | u8 root_bus_nr; | ||
| 26 | void __iomem *base; | ||
| 27 | spinlock_t conf_lock; | ||
| 28 | char io_space_name[16]; | ||
| 29 | char mem_space_name[16]; | ||
| 30 | struct resource res[2]; | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct pcie_port pcie_port[2]; | ||
| 34 | static int num_pcie_ports; | ||
| 35 | |||
| 36 | |||
| 37 | static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) | ||
| 38 | { | ||
| 39 | struct pcie_port *pp; | ||
| 40 | |||
| 41 | if (nr >= num_pcie_ports) | ||
| 42 | return 0; | ||
| 43 | |||
| 44 | pp = &pcie_port[nr]; | ||
| 45 | pp->root_bus_nr = sys->busnr; | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Generic PCIe unit setup. | ||
| 49 | */ | ||
| 50 | orion_pcie_set_local_bus_nr(pp->base, sys->busnr); | ||
| 51 | |||
| 52 | orion_pcie_setup(pp->base, &dove_mbus_dram_info); | ||
| 53 | |||
| 54 | /* | ||
| 55 | * IORESOURCE_IO | ||
| 56 | */ | ||
| 57 | snprintf(pp->io_space_name, sizeof(pp->io_space_name), | ||
| 58 | "PCIe %d I/O", pp->index); | ||
| 59 | pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; | ||
| 60 | pp->res[0].name = pp->io_space_name; | ||
| 61 | if (pp->index == 0) { | ||
| 62 | pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; | ||
| 63 | pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; | ||
| 64 | } else { | ||
| 65 | pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; | ||
| 66 | pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; | ||
| 67 | } | ||
| 68 | pp->res[0].flags = IORESOURCE_IO; | ||
| 69 | if (request_resource(&ioport_resource, &pp->res[0])) | ||
| 70 | panic("Request PCIe IO resource failed\n"); | ||
| 71 | sys->resource[0] = &pp->res[0]; | ||
| 72 | |||
| 73 | /* | ||
| 74 | * IORESOURCE_MEM | ||
| 75 | */ | ||
| 76 | snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), | ||
| 77 | "PCIe %d MEM", pp->index); | ||
| 78 | pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; | ||
| 79 | pp->res[1].name = pp->mem_space_name; | ||
| 80 | if (pp->index == 0) { | ||
| 81 | pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; | ||
| 82 | pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; | ||
| 83 | } else { | ||
| 84 | pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; | ||
| 85 | pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; | ||
| 86 | } | ||
| 87 | pp->res[1].flags = IORESOURCE_MEM; | ||
| 88 | if (request_resource(&iomem_resource, &pp->res[1])) | ||
| 89 | panic("Request PCIe Memory resource failed\n"); | ||
| 90 | sys->resource[1] = &pp->res[1]; | ||
| 91 | |||
| 92 | sys->resource[2] = NULL; | ||
| 93 | |||
| 94 | return 1; | ||
| 95 | } | ||
| 96 | |||
| 97 | static struct pcie_port *bus_to_port(int bus) | ||
| 98 | { | ||
| 99 | int i; | ||
| 100 | |||
| 101 | for (i = num_pcie_ports - 1; i >= 0; i--) { | ||
| 102 | int rbus = pcie_port[i].root_bus_nr; | ||
| 103 | if (rbus != -1 && rbus <= bus) | ||
| 104 | break; | ||
| 105 | } | ||
| 106 | |||
| 107 | return i >= 0 ? pcie_port + i : NULL; | ||
| 108 | } | ||
| 109 | |||
| 110 | static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) | ||
| 111 | { | ||
| 112 | /* | ||
| 113 | * Don't go out when trying to access nonexisting devices | ||
| 114 | * on the local bus. | ||
| 115 | */ | ||
| 116 | if (bus == pp->root_bus_nr && dev > 1) | ||
| 117 | return 0; | ||
| 118 | |||
| 119 | return 1; | ||
| 120 | } | ||
| 121 | |||
| 122 | static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, | ||
| 123 | int size, u32 *val) | ||
| 124 | { | ||
| 125 | struct pcie_port *pp = bus_to_port(bus->number); | ||
| 126 | unsigned long flags; | ||
| 127 | int ret; | ||
| 128 | |||
| 129 | if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { | ||
| 130 | *val = 0xffffffff; | ||
| 131 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 132 | } | ||
| 133 | |||
| 134 | spin_lock_irqsave(&pp->conf_lock, flags); | ||
| 135 | ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); | ||
| 136 | spin_unlock_irqrestore(&pp->conf_lock, flags); | ||
| 137 | |||
| 138 | return ret; | ||
| 139 | } | ||
| 140 | |||
| 141 | static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, | ||
| 142 | int where, int size, u32 val) | ||
| 143 | { | ||
| 144 | struct pcie_port *pp = bus_to_port(bus->number); | ||
| 145 | unsigned long flags; | ||
| 146 | int ret; | ||
| 147 | |||
| 148 | if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) | ||
| 149 | return PCIBIOS_DEVICE_NOT_FOUND; | ||
| 150 | |||
| 151 | spin_lock_irqsave(&pp->conf_lock, flags); | ||
| 152 | ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); | ||
| 153 | spin_unlock_irqrestore(&pp->conf_lock, flags); | ||
| 154 | |||
| 155 | return ret; | ||
| 156 | } | ||
| 157 | |||
| 158 | static struct pci_ops pcie_ops = { | ||
| 159 | .read = pcie_rd_conf, | ||
| 160 | .write = pcie_wr_conf, | ||
| 161 | }; | ||
| 162 | |||
| 163 | static void __devinit rc_pci_fixup(struct pci_dev *dev) | ||
| 164 | { | ||
| 165 | /* | ||
| 166 | * Prevent enumeration of root complex. | ||
| 167 | */ | ||
| 168 | if (dev->bus->parent == NULL && dev->devfn == 0) { | ||
| 169 | int i; | ||
| 170 | |||
| 171 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | ||
| 172 | dev->resource[i].start = 0; | ||
| 173 | dev->resource[i].end = 0; | ||
| 174 | dev->resource[i].flags = 0; | ||
| 175 | } | ||
| 176 | } | ||
| 177 | } | ||
| 178 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); | ||
| 179 | |||
| 180 | static struct pci_bus __init * | ||
| 181 | dove_pcie_scan_bus(int nr, struct pci_sys_data *sys) | ||
| 182 | { | ||
| 183 | struct pci_bus *bus; | ||
| 184 | |||
| 185 | if (nr < num_pcie_ports) { | ||
| 186 | bus = pci_scan_bus(sys->busnr, &pcie_ops, sys); | ||
| 187 | } else { | ||
| 188 | bus = NULL; | ||
| 189 | BUG(); | ||
| 190 | } | ||
| 191 | |||
| 192 | return bus; | ||
| 193 | } | ||
| 194 | |||
| 195 | static int __init dove_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | ||
| 196 | { | ||
| 197 | struct pcie_port *pp = bus_to_port(dev->bus->number); | ||
| 198 | |||
| 199 | return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; | ||
| 200 | } | ||
| 201 | |||
| 202 | static struct hw_pci dove_pci __initdata = { | ||
| 203 | .nr_controllers = 2, | ||
| 204 | .swizzle = pci_std_swizzle, | ||
| 205 | .setup = dove_pcie_setup, | ||
| 206 | .scan = dove_pcie_scan_bus, | ||
| 207 | .map_irq = dove_pcie_map_irq, | ||
| 208 | }; | ||
| 209 | |||
| 210 | static void __init add_pcie_port(int index, unsigned long base) | ||
| 211 | { | ||
| 212 | printk(KERN_INFO "Dove PCIe port %d: ", index); | ||
| 213 | |||
| 214 | if (orion_pcie_link_up((void __iomem *)base)) { | ||
| 215 | struct pcie_port *pp = &pcie_port[num_pcie_ports++]; | ||
| 216 | |||
| 217 | printk(KERN_INFO "link up\n"); | ||
| 218 | |||
| 219 | pp->index = index; | ||
| 220 | pp->root_bus_nr = -1; | ||
| 221 | pp->base = (void __iomem *)base; | ||
| 222 | spin_lock_init(&pp->conf_lock); | ||
| 223 | memset(pp->res, 0, sizeof(pp->res)); | ||
| 224 | } else { | ||
| 225 | printk(KERN_INFO "link down, ignoring\n"); | ||
| 226 | } | ||
| 227 | } | ||
| 228 | |||
| 229 | void __init dove_pcie_init(int init_port0, int init_port1) | ||
| 230 | { | ||
| 231 | if (init_port0) | ||
| 232 | add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); | ||
| 233 | |||
| 234 | if (init_port1) | ||
| 235 | add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); | ||
| 236 | |||
| 237 | pci_common_init(&dove_pci); | ||
| 238 | } | ||
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h index d6d52527589d..f1c00d6d560b 100644 --- a/arch/arm/mach-iop13xx/include/mach/time.h +++ b/arch/arm/mach-iop13xx/include/mach/time.h | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #define IOP13XX_CORE_FREQ_1200 (5 << 16) | 20 | #define IOP13XX_CORE_FREQ_1200 (5 << 16) |
| 21 | 21 | ||
| 22 | void iop_init_time(unsigned long tickrate); | 22 | void iop_init_time(unsigned long tickrate); |
| 23 | unsigned long iop_gettimeoffset(void); | ||
| 24 | 23 | ||
| 25 | static inline unsigned long iop13xx_core_freq(void) | 24 | static inline unsigned long iop13xx_core_freq(void) |
| 26 | { | 25 | { |
| @@ -66,6 +65,13 @@ static inline unsigned long iop13xx_xsi_bus_ratio(void) | |||
| 66 | return 2; | 65 | return 2; |
| 67 | } | 66 | } |
| 68 | 67 | ||
| 68 | static inline u32 read_tmr0(void) | ||
| 69 | { | ||
| 70 | u32 val; | ||
| 71 | asm volatile("mrc p6, 0, %0, c0, c9, 0" : "=r" (val)); | ||
| 72 | return val; | ||
| 73 | } | ||
| 74 | |||
| 69 | static inline void write_tmr0(u32 val) | 75 | static inline void write_tmr0(u32 val) |
| 70 | { | 76 | { |
| 71 | asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); | 77 | asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); |
| @@ -83,6 +89,11 @@ static inline u32 read_tcr0(void) | |||
| 83 | return val; | 89 | return val; |
| 84 | } | 90 | } |
| 85 | 91 | ||
| 92 | static inline void write_tcr0(u32 val) | ||
| 93 | { | ||
| 94 | asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); | ||
| 95 | } | ||
| 96 | |||
| 86 | static inline u32 read_tcr1(void) | 97 | static inline u32 read_tcr1(void) |
| 87 | { | 98 | { |
| 88 | u32 val; | 99 | u32 val; |
| @@ -90,6 +101,11 @@ static inline u32 read_tcr1(void) | |||
| 90 | return val; | 101 | return val; |
| 91 | } | 102 | } |
| 92 | 103 | ||
| 104 | static inline void write_tcr1(u32 val) | ||
| 105 | { | ||
| 106 | asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); | ||
| 107 | } | ||
| 108 | |||
| 93 | static inline void write_trr0(u32 val) | 109 | static inline void write_trr0(u32 val) |
| 94 | { | 110 | { |
| 95 | asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); | 111 | asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); |
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c index 5051c03d437c..f91f3154577d 100644 --- a/arch/arm/mach-iop13xx/iq81340mc.c +++ b/arch/arm/mach-iop13xx/iq81340mc.c | |||
| @@ -87,7 +87,6 @@ static void __init iq81340mc_timer_init(void) | |||
| 87 | 87 | ||
| 88 | static struct sys_timer iq81340mc_timer = { | 88 | static struct sys_timer iq81340mc_timer = { |
| 89 | .init = iq81340mc_timer_init, | 89 | .init = iq81340mc_timer_init, |
| 90 | .offset = iop_gettimeoffset, | ||
| 91 | }; | 90 | }; |
| 92 | 91 | ||
| 93 | MACHINE_START(IQ81340MC, "Intel IQ81340MC") | 92 | MACHINE_START(IQ81340MC, "Intel IQ81340MC") |
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c index bc443073a8e3..ddb7a3435de9 100644 --- a/arch/arm/mach-iop13xx/iq81340sc.c +++ b/arch/arm/mach-iop13xx/iq81340sc.c | |||
| @@ -89,7 +89,6 @@ static void __init iq81340sc_timer_init(void) | |||
| 89 | 89 | ||
| 90 | static struct sys_timer iq81340sc_timer = { | 90 | static struct sys_timer iq81340sc_timer = { |
| 91 | .init = iq81340sc_timer_init, | 91 | .init = iq81340sc_timer_init, |
| 92 | .offset = iop_gettimeoffset, | ||
| 93 | }; | 92 | }; |
| 94 | 93 | ||
| 95 | MACHINE_START(IQ81340SC, "Intel IQ81340SC") | 94 | MACHINE_START(IQ81340SC, "Intel IQ81340SC") |
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c index 3ad4696ade42..2bef9b6e1cc9 100644 --- a/arch/arm/mach-iop32x/em7210.c +++ b/arch/arm/mach-iop32x/em7210.c | |||
| @@ -42,7 +42,6 @@ static void __init em7210_timer_init(void) | |||
| 42 | 42 | ||
| 43 | static struct sys_timer em7210_timer = { | 43 | static struct sys_timer em7210_timer = { |
| 44 | .init = em7210_timer_init, | 44 | .init = em7210_timer_init, |
| 45 | .offset = iop_gettimeoffset, | ||
| 46 | }; | 45 | }; |
| 47 | 46 | ||
| 48 | /* | 47 | /* |
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c index a9c2dfdb2507..93370a46b620 100644 --- a/arch/arm/mach-iop32x/glantank.c +++ b/arch/arm/mach-iop32x/glantank.c | |||
| @@ -47,7 +47,6 @@ static void __init glantank_timer_init(void) | |||
| 47 | 47 | ||
| 48 | static struct sys_timer glantank_timer = { | 48 | static struct sys_timer glantank_timer = { |
| 49 | .init = glantank_timer_init, | 49 | .init = glantank_timer_init, |
| 50 | .offset = iop_gettimeoffset, | ||
| 51 | }; | 50 | }; |
| 52 | 51 | ||
| 53 | 52 | ||
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c index dd1cd9904518..a7a08dda7f33 100644 --- a/arch/arm/mach-iop32x/iq31244.c +++ b/arch/arm/mach-iop32x/iq31244.c | |||
| @@ -78,7 +78,6 @@ static void __init iq31244_timer_init(void) | |||
| 78 | 78 | ||
| 79 | static struct sys_timer iq31244_timer = { | 79 | static struct sys_timer iq31244_timer = { |
| 80 | .init = iq31244_timer_init, | 80 | .init = iq31244_timer_init, |
| 81 | .offset = iop_gettimeoffset, | ||
| 82 | }; | 81 | }; |
| 83 | 82 | ||
| 84 | 83 | ||
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c index fbe27798759d..0200f80c1e17 100644 --- a/arch/arm/mach-iop32x/iq80321.c +++ b/arch/arm/mach-iop32x/iq80321.c | |||
| @@ -46,7 +46,6 @@ static void __init iq80321_timer_init(void) | |||
| 46 | 46 | ||
| 47 | static struct sys_timer iq80321_timer = { | 47 | static struct sys_timer iq80321_timer = { |
| 48 | .init = iq80321_timer_init, | 48 | .init = iq80321_timer_init, |
| 49 | .offset = iop_gettimeoffset, | ||
| 50 | }; | 49 | }; |
| 51 | 50 | ||
| 52 | 51 | ||
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c index d2e427899729..2a5c637639bb 100644 --- a/arch/arm/mach-iop32x/n2100.c +++ b/arch/arm/mach-iop32x/n2100.c | |||
| @@ -53,7 +53,6 @@ static void __init n2100_timer_init(void) | |||
| 53 | 53 | ||
| 54 | static struct sys_timer n2100_timer = { | 54 | static struct sys_timer n2100_timer = { |
| 55 | .init = n2100_timer_init, | 55 | .init = n2100_timer_init, |
| 56 | .offset = iop_gettimeoffset, | ||
| 57 | }; | 56 | }; |
| 58 | 57 | ||
| 59 | 58 | ||
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c index d51e10cddf20..394e95a30b75 100644 --- a/arch/arm/mach-iop33x/iq80331.c +++ b/arch/arm/mach-iop33x/iq80331.c | |||
| @@ -48,7 +48,6 @@ static void __init iq80331_timer_init(void) | |||
| 48 | 48 | ||
| 49 | static struct sys_timer iq80331_timer = { | 49 | static struct sys_timer iq80331_timer = { |
| 50 | .init = iq80331_timer_init, | 50 | .init = iq80331_timer_init, |
| 51 | .offset = iop_gettimeoffset, | ||
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| 54 | 53 | ||
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c index 92fb44cdbcad..a40badf126c2 100644 --- a/arch/arm/mach-iop33x/iq80332.c +++ b/arch/arm/mach-iop33x/iq80332.c | |||
| @@ -48,7 +48,6 @@ static void __init iq80332_timer_init(void) | |||
| 48 | 48 | ||
| 49 | static struct sys_timer iq80332_timer = { | 49 | static struct sys_timer iq80332_timer = { |
| 50 | .init = iq80332_timer_init, | 50 | .init = iq80332_timer_init, |
| 51 | .offset = iop_gettimeoffset, | ||
| 52 | }; | 51 | }; |
| 53 | 52 | ||
| 54 | 53 | ||
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 0aca451b216d..8bf09ae5b347 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig | |||
| @@ -33,10 +33,18 @@ config MACH_SHEEVAPLUG | |||
| 33 | Marvell SheevaPlug Reference Board. | 33 | Marvell SheevaPlug Reference Board. |
| 34 | 34 | ||
| 35 | config MACH_TS219 | 35 | config MACH_TS219 |
| 36 | bool "QNAP TS-119 and TS-219 Turbo NAS" | 36 | bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS" |
| 37 | help | 37 | help |
| 38 | Say 'Y' here if you want your kernel to support the | 38 | Say 'Y' here if you want your kernel to support the |
| 39 | QNAP TS-119 and TS-219 Turbo NAS devices. | 39 | QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS |
| 40 | devices. | ||
| 41 | |||
| 42 | config MACH_TS41X | ||
| 43 | bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS" | ||
| 44 | help | ||
| 45 | Say 'Y' here if you want your kernel to support the | ||
| 46 | QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS | ||
| 47 | devices. | ||
| 40 | 48 | ||
| 41 | config MACH_OPENRD_BASE | 49 | config MACH_OPENRD_BASE |
| 42 | bool "Marvell OpenRD Base Board" | 50 | bool "Marvell OpenRD Base Board" |
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index 80ab0ec90ee1..9f2f67b2b63d 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
| @@ -5,7 +5,8 @@ obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o | |||
| 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o | 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o |
| 6 | obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o | 6 | obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o |
| 7 | obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o | 7 | obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o |
| 8 | obj-$(CONFIG_MACH_TS219) += ts219-setup.o | 8 | obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o |
| 9 | obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o | ||
| 9 | obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o | 10 | obj-$(CONFIG_MACH_OPENRD_BASE) += openrd_base-setup.o |
| 10 | 11 | ||
| 11 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 12 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c index ec1a64f263d2..2830f0fe80e0 100644 --- a/arch/arm/mach-kirkwood/ts219-setup.c +++ b/arch/arm/mach-kirkwood/ts219-setup.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * | 2 | * |
| 3 | * QNAP TS-119/TS-219 Turbo NAS Board Setup | 3 | * QNAP TS-11x/TS-21x Turbo NAS Board Setup |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> | 5 | * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> |
| 6 | * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> | 6 | * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> |
| @@ -14,87 +14,17 @@ | |||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/mtd/physmap.h> | ||
| 18 | #include <linux/spi/flash.h> | ||
| 19 | #include <linux/spi/spi.h> | ||
| 20 | #include <linux/spi/orion_spi.h> | ||
| 21 | #include <linux/i2c.h> | 17 | #include <linux/i2c.h> |
| 22 | #include <linux/mv643xx_eth.h> | 18 | #include <linux/mv643xx_eth.h> |
| 23 | #include <linux/ata_platform.h> | 19 | #include <linux/ata_platform.h> |
| 24 | #include <linux/gpio_keys.h> | 20 | #include <linux/gpio_keys.h> |
| 25 | #include <linux/input.h> | 21 | #include <linux/input.h> |
| 26 | #include <linux/timex.h> | ||
| 27 | #include <linux/serial_reg.h> | ||
| 28 | #include <linux/pci.h> | ||
| 29 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 31 | #include <mach/kirkwood.h> | 24 | #include <mach/kirkwood.h> |
| 32 | #include "common.h" | 25 | #include "common.h" |
| 33 | #include "mpp.h" | 26 | #include "mpp.h" |
| 34 | 27 | #include "tsx1x-common.h" | |
| 35 | /**************************************************************************** | ||
| 36 | * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the | ||
| 37 | * partitions on the device because we want to keep compatability with | ||
| 38 | * the QNAP firmware. | ||
| 39 | * Layout as used by QNAP: | ||
| 40 | * 0x00000000-0x00080000 : "U-Boot" | ||
| 41 | * 0x00200000-0x00400000 : "Kernel" | ||
| 42 | * 0x00400000-0x00d00000 : "RootFS" | ||
| 43 | * 0x00d00000-0x01000000 : "RootFS2" | ||
| 44 | * 0x00080000-0x000c0000 : "U-Boot Config" | ||
| 45 | * 0x000c0000-0x00200000 : "NAS Config" | ||
| 46 | * | ||
| 47 | * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout | ||
| 48 | * used by the QNAP TS-109/TS-209. | ||
| 49 | * | ||
| 50 | ***************************************************************************/ | ||
| 51 | |||
| 52 | static struct mtd_partition qnap_ts219_partitions[] = { | ||
| 53 | { | ||
| 54 | .name = "U-Boot", | ||
| 55 | .size = 0x00080000, | ||
| 56 | .offset = 0, | ||
| 57 | .mask_flags = MTD_WRITEABLE, | ||
| 58 | }, { | ||
| 59 | .name = "Kernel", | ||
| 60 | .size = 0x00200000, | ||
| 61 | .offset = 0x00200000, | ||
| 62 | }, { | ||
| 63 | .name = "RootFS1", | ||
| 64 | .size = 0x00900000, | ||
| 65 | .offset = 0x00400000, | ||
| 66 | }, { | ||
| 67 | .name = "RootFS2", | ||
| 68 | .size = 0x00300000, | ||
| 69 | .offset = 0x00d00000, | ||
| 70 | }, { | ||
| 71 | .name = "U-Boot Config", | ||
| 72 | .size = 0x00040000, | ||
| 73 | .offset = 0x00080000, | ||
| 74 | }, { | ||
| 75 | .name = "NAS Config", | ||
| 76 | .size = 0x00140000, | ||
| 77 | .offset = 0x000c0000, | ||
| 78 | }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static const struct flash_platform_data qnap_ts219_flash = { | ||
| 82 | .type = "m25p128", | ||
| 83 | .name = "spi_flash", | ||
| 84 | .parts = qnap_ts219_partitions, | ||
| 85 | .nr_parts = ARRAY_SIZE(qnap_ts219_partitions), | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = { | ||
| 89 | { | ||
| 90 | .modalias = "m25p80", | ||
| 91 | .platform_data = &qnap_ts219_flash, | ||
| 92 | .irq = -1, | ||
| 93 | .max_speed_hz = 20000000, | ||
| 94 | .bus_num = 0, | ||
| 95 | .chip_select = 0, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | 28 | ||
| 99 | static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { | 29 | static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { |
| 100 | I2C_BOARD_INFO("s35390a", 0x30), | 30 | I2C_BOARD_INFO("s35390a", 0x30), |
| @@ -152,36 +82,10 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = { | |||
| 152 | MPP14_UART1_RXD, /* PIC controller */ | 82 | MPP14_UART1_RXD, /* PIC controller */ |
| 153 | MPP15_GPIO, /* USB Copy button */ | 83 | MPP15_GPIO, /* USB Copy button */ |
| 154 | MPP16_GPIO, /* Reset button */ | 84 | MPP16_GPIO, /* Reset button */ |
| 85 | MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ | ||
| 155 | 0 | 86 | 0 |
| 156 | }; | 87 | }; |
| 157 | 88 | ||
| 158 | |||
| 159 | /***************************************************************************** | ||
| 160 | * QNAP TS-x19 specific power off method via UART1-attached PIC | ||
| 161 | ****************************************************************************/ | ||
| 162 | |||
| 163 | #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) | ||
| 164 | |||
| 165 | void qnap_ts219_power_off(void) | ||
| 166 | { | ||
| 167 | /* 19200 baud divisor */ | ||
| 168 | const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); | ||
| 169 | |||
| 170 | pr_info("%s: triggering power-off...\n", __func__); | ||
| 171 | |||
| 172 | /* hijack UART1 and reset into sane state (19200,8n1) */ | ||
| 173 | writel(0x83, UART1_REG(LCR)); | ||
| 174 | writel(divisor & 0xff, UART1_REG(DLL)); | ||
| 175 | writel((divisor >> 8) & 0xff, UART1_REG(DLM)); | ||
| 176 | writel(0x03, UART1_REG(LCR)); | ||
| 177 | writel(0x00, UART1_REG(IER)); | ||
| 178 | writel(0x00, UART1_REG(FCR)); | ||
| 179 | writel(0x00, UART1_REG(MCR)); | ||
| 180 | |||
| 181 | /* send the power-off command 'A' to PIC */ | ||
| 182 | writel('A', UART1_REG(TX)); | ||
| 183 | } | ||
| 184 | |||
| 185 | static void __init qnap_ts219_init(void) | 89 | static void __init qnap_ts219_init(void) |
| 186 | { | 90 | { |
| 187 | /* | 91 | /* |
| @@ -192,9 +96,7 @@ static void __init qnap_ts219_init(void) | |||
| 192 | 96 | ||
| 193 | kirkwood_uart0_init(); | 97 | kirkwood_uart0_init(); |
| 194 | kirkwood_uart1_init(); /* A PIC controller is connected here. */ | 98 | kirkwood_uart1_init(); /* A PIC controller is connected here. */ |
| 195 | spi_register_board_info(qnap_ts219_spi_slave_info, | 99 | qnap_tsx1x_register_flash(); |
| 196 | ARRAY_SIZE(qnap_ts219_spi_slave_info)); | ||
| 197 | kirkwood_spi_init(); | ||
| 198 | kirkwood_i2c_init(); | 100 | kirkwood_i2c_init(); |
| 199 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); | 101 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); |
| 200 | kirkwood_ge00_init(&qnap_ts219_ge00_data); | 102 | kirkwood_ge00_init(&qnap_ts219_ge00_data); |
| @@ -202,7 +104,7 @@ static void __init qnap_ts219_init(void) | |||
| 202 | kirkwood_ehci_init(); | 104 | kirkwood_ehci_init(); |
| 203 | platform_device_register(&qnap_ts219_button_device); | 105 | platform_device_register(&qnap_ts219_button_device); |
| 204 | 106 | ||
| 205 | pm_power_off = qnap_ts219_power_off; | 107 | pm_power_off = qnap_tsx1x_power_off; |
| 206 | 108 | ||
| 207 | } | 109 | } |
| 208 | 110 | ||
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c new file mode 100644 index 000000000000..de49c2d9e74b --- /dev/null +++ b/arch/arm/mach-kirkwood/ts41x-setup.c | |||
| @@ -0,0 +1,154 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup | ||
| 4 | * | ||
| 5 | * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> | ||
| 6 | * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version | ||
| 11 | * 2 of the License, or (at your option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/i2c.h> | ||
| 18 | #include <linux/mv643xx_eth.h> | ||
| 19 | #include <linux/ata_platform.h> | ||
| 20 | #include <linux/gpio_keys.h> | ||
| 21 | #include <linux/input.h> | ||
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <mach/kirkwood.h> | ||
| 25 | #include "common.h" | ||
| 26 | #include "mpp.h" | ||
| 27 | #include "tsx1x-common.h" | ||
| 28 | |||
| 29 | static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = { | ||
| 30 | I2C_BOARD_INFO("s35390a", 0x30), | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct mv643xx_eth_platform_data qnap_ts41x_ge00_data = { | ||
| 34 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct mv643xx_eth_platform_data qnap_ts41x_ge01_data = { | ||
| 38 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), | ||
| 39 | }; | ||
| 40 | |||
| 41 | static struct mv_sata_platform_data qnap_ts41x_sata_data = { | ||
| 42 | .n_ports = 2, | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct gpio_keys_button qnap_ts41x_buttons[] = { | ||
| 46 | { | ||
| 47 | .code = KEY_COPY, | ||
| 48 | .gpio = 43, | ||
| 49 | .desc = "USB Copy", | ||
| 50 | .active_low = 1, | ||
| 51 | }, | ||
| 52 | { | ||
| 53 | .code = KEY_RESTART, | ||
| 54 | .gpio = 37, | ||
| 55 | .desc = "Reset", | ||
| 56 | .active_low = 1, | ||
| 57 | }, | ||
| 58 | }; | ||
| 59 | |||
| 60 | static struct gpio_keys_platform_data qnap_ts41x_button_data = { | ||
| 61 | .buttons = qnap_ts41x_buttons, | ||
| 62 | .nbuttons = ARRAY_SIZE(qnap_ts41x_buttons), | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct platform_device qnap_ts41x_button_device = { | ||
| 66 | .name = "gpio-keys", | ||
| 67 | .id = -1, | ||
| 68 | .num_resources = 0, | ||
| 69 | .dev = { | ||
| 70 | .platform_data = &qnap_ts41x_button_data, | ||
| 71 | } | ||
| 72 | }; | ||
| 73 | |||
| 74 | static unsigned int qnap_ts41x_mpp_config[] __initdata = { | ||
| 75 | MPP0_SPI_SCn, | ||
| 76 | MPP1_SPI_MOSI, | ||
| 77 | MPP2_SPI_SCK, | ||
| 78 | MPP3_SPI_MISO, | ||
| 79 | MPP6_SYSRST_OUTn, | ||
| 80 | MPP7_PEX_RST_OUTn, | ||
| 81 | MPP8_TW_SDA, | ||
| 82 | MPP9_TW_SCK, | ||
| 83 | MPP10_UART0_TXD, | ||
| 84 | MPP11_UART0_RXD, | ||
| 85 | MPP13_UART1_TXD, /* PIC controller */ | ||
| 86 | MPP14_UART1_RXD, /* PIC controller */ | ||
| 87 | MPP15_SATA0_ACTn, | ||
| 88 | MPP16_SATA1_ACTn, | ||
| 89 | MPP20_GE1_0, | ||
| 90 | MPP21_GE1_1, | ||
| 91 | MPP22_GE1_2, | ||
| 92 | MPP23_GE1_3, | ||
| 93 | MPP24_GE1_4, | ||
| 94 | MPP25_GE1_5, | ||
| 95 | MPP26_GE1_6, | ||
| 96 | MPP27_GE1_7, | ||
| 97 | MPP30_GE1_10, | ||
| 98 | MPP31_GE1_11, | ||
| 99 | MPP32_GE1_12, | ||
| 100 | MPP33_GE1_13, | ||
| 101 | MPP36_GPIO, /* RAM: 0: 256 MB, 1: 512 MB */ | ||
| 102 | MPP37_GPIO, /* Reset button */ | ||
| 103 | MPP43_GPIO, /* USB Copy button */ | ||
| 104 | MPP44_GPIO, /* Board ID: 0: TS-419U, 1: TS-419 */ | ||
| 105 | MPP45_GPIO, /* JP1: 0: console, 1: LCD */ | ||
| 106 | MPP46_GPIO, /* External SATA HDD1 error indicator */ | ||
| 107 | MPP47_GPIO, /* External SATA HDD2 error indicator */ | ||
| 108 | MPP48_GPIO, /* External SATA HDD3 error indicator */ | ||
| 109 | MPP49_GPIO, /* External SATA HDD4 error indicator */ | ||
| 110 | 0 | ||
| 111 | }; | ||
| 112 | |||
| 113 | static void __init qnap_ts41x_init(void) | ||
| 114 | { | ||
| 115 | /* | ||
| 116 | * Basic setup. Needs to be called early. | ||
| 117 | */ | ||
| 118 | kirkwood_init(); | ||
| 119 | kirkwood_mpp_conf(qnap_ts41x_mpp_config); | ||
| 120 | |||
| 121 | kirkwood_uart0_init(); | ||
| 122 | kirkwood_uart1_init(); /* A PIC controller is connected here. */ | ||
| 123 | qnap_tsx1x_register_flash(); | ||
| 124 | kirkwood_i2c_init(); | ||
| 125 | i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1); | ||
| 126 | kirkwood_ge00_init(&qnap_ts41x_ge00_data); | ||
| 127 | kirkwood_ge01_init(&qnap_ts41x_ge01_data); | ||
| 128 | kirkwood_sata_init(&qnap_ts41x_sata_data); | ||
| 129 | kirkwood_ehci_init(); | ||
| 130 | platform_device_register(&qnap_ts41x_button_device); | ||
| 131 | |||
| 132 | pm_power_off = qnap_tsx1x_power_off; | ||
| 133 | |||
| 134 | } | ||
| 135 | |||
| 136 | static int __init ts41x_pci_init(void) | ||
| 137 | { | ||
| 138 | if (machine_is_ts41x()) | ||
| 139 | kirkwood_pcie_init(); | ||
| 140 | |||
| 141 | return 0; | ||
| 142 | } | ||
| 143 | subsys_initcall(ts41x_pci_init); | ||
| 144 | |||
| 145 | MACHINE_START(TS41X, "QNAP TS-41x") | ||
| 146 | /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ | ||
| 147 | .phys_io = KIRKWOOD_REGS_PHYS_BASE, | ||
| 148 | .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 149 | .boot_params = 0x00000100, | ||
| 150 | .init_machine = qnap_ts41x_init, | ||
| 151 | .map_io = kirkwood_map_io, | ||
| 152 | .init_irq = kirkwood_init_irq, | ||
| 153 | .timer = &kirkwood_timer, | ||
| 154 | MACHINE_END | ||
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.c b/arch/arm/mach-kirkwood/tsx1x-common.c new file mode 100644 index 000000000000..7221c20b2afa --- /dev/null +++ b/arch/arm/mach-kirkwood/tsx1x-common.c | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | #include <linux/kernel.h> | ||
| 2 | #include <linux/pci.h> | ||
| 3 | #include <linux/platform_device.h> | ||
| 4 | #include <linux/mtd/physmap.h> | ||
| 5 | #include <linux/spi/flash.h> | ||
| 6 | #include <linux/spi/spi.h> | ||
| 7 | #include <linux/spi/orion_spi.h> | ||
| 8 | #include <linux/serial_reg.h> | ||
| 9 | #include <mach/kirkwood.h> | ||
| 10 | #include "common.h" | ||
| 11 | |||
| 12 | /* | ||
| 13 | * QNAP TS-x1x Boards flash | ||
| 14 | */ | ||
| 15 | |||
| 16 | /**************************************************************************** | ||
| 17 | * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the | ||
| 18 | * partitions on the device because we want to keep compatability with | ||
| 19 | * the QNAP firmware. | ||
| 20 | * Layout as used by QNAP: | ||
| 21 | * 0x00000000-0x00080000 : "U-Boot" | ||
| 22 | * 0x00200000-0x00400000 : "Kernel" | ||
| 23 | * 0x00400000-0x00d00000 : "RootFS" | ||
| 24 | * 0x00d00000-0x01000000 : "RootFS2" | ||
| 25 | * 0x00080000-0x000c0000 : "U-Boot Config" | ||
| 26 | * 0x000c0000-0x00200000 : "NAS Config" | ||
| 27 | * | ||
| 28 | * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout | ||
| 29 | * used by the QNAP TS-109/TS-209. | ||
| 30 | * | ||
| 31 | ***************************************************************************/ | ||
| 32 | |||
| 33 | struct mtd_partition qnap_tsx1x_partitions[] = { | ||
| 34 | { | ||
| 35 | .name = "U-Boot", | ||
| 36 | .size = 0x00080000, | ||
| 37 | .offset = 0, | ||
| 38 | .mask_flags = MTD_WRITEABLE, | ||
| 39 | }, { | ||
| 40 | .name = "Kernel", | ||
| 41 | .size = 0x00200000, | ||
| 42 | .offset = 0x00200000, | ||
| 43 | }, { | ||
| 44 | .name = "RootFS1", | ||
| 45 | .size = 0x00900000, | ||
| 46 | .offset = 0x00400000, | ||
| 47 | }, { | ||
| 48 | .name = "RootFS2", | ||
| 49 | .size = 0x00300000, | ||
| 50 | .offset = 0x00d00000, | ||
| 51 | }, { | ||
| 52 | .name = "U-Boot Config", | ||
| 53 | .size = 0x00040000, | ||
| 54 | .offset = 0x00080000, | ||
| 55 | }, { | ||
| 56 | .name = "NAS Config", | ||
| 57 | .size = 0x00140000, | ||
| 58 | .offset = 0x000c0000, | ||
| 59 | }, | ||
| 60 | }; | ||
| 61 | |||
| 62 | const struct flash_platform_data qnap_tsx1x_flash = { | ||
| 63 | .type = "m25p128", | ||
| 64 | .name = "spi_flash", | ||
| 65 | .parts = qnap_tsx1x_partitions, | ||
| 66 | .nr_parts = ARRAY_SIZE(qnap_tsx1x_partitions), | ||
| 67 | }; | ||
| 68 | |||
| 69 | struct spi_board_info __initdata qnap_tsx1x_spi_slave_info[] = { | ||
| 70 | { | ||
| 71 | .modalias = "m25p80", | ||
| 72 | .platform_data = &qnap_tsx1x_flash, | ||
| 73 | .irq = -1, | ||
| 74 | .max_speed_hz = 20000000, | ||
| 75 | .bus_num = 0, | ||
| 76 | .chip_select = 0, | ||
| 77 | }, | ||
| 78 | }; | ||
| 79 | |||
| 80 | void qnap_tsx1x_register_flash(void) | ||
| 81 | { | ||
| 82 | spi_register_board_info(qnap_tsx1x_spi_slave_info, | ||
| 83 | ARRAY_SIZE(qnap_tsx1x_spi_slave_info)); | ||
| 84 | kirkwood_spi_init(); | ||
| 85 | } | ||
| 86 | |||
| 87 | |||
| 88 | /***************************************************************************** | ||
| 89 | * QNAP TS-x1x specific power off method via UART1-attached PIC | ||
| 90 | ****************************************************************************/ | ||
| 91 | |||
| 92 | #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) | ||
| 93 | |||
| 94 | void qnap_tsx1x_power_off(void) | ||
| 95 | { | ||
| 96 | /* 19200 baud divisor */ | ||
| 97 | const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); | ||
| 98 | |||
| 99 | pr_info("%s: triggering power-off...\n", __func__); | ||
| 100 | |||
| 101 | /* hijack UART1 and reset into sane state (19200,8n1) */ | ||
| 102 | writel(0x83, UART1_REG(LCR)); | ||
| 103 | writel(divisor & 0xff, UART1_REG(DLL)); | ||
| 104 | writel((divisor >> 8) & 0xff, UART1_REG(DLM)); | ||
| 105 | writel(0x03, UART1_REG(LCR)); | ||
| 106 | writel(0x00, UART1_REG(IER)); | ||
| 107 | writel(0x00, UART1_REG(FCR)); | ||
| 108 | writel(0x00, UART1_REG(MCR)); | ||
| 109 | |||
| 110 | /* send the power-off command 'A' to PIC */ | ||
| 111 | writel('A', UART1_REG(TX)); | ||
| 112 | } | ||
| 113 | |||
diff --git a/arch/arm/mach-kirkwood/tsx1x-common.h b/arch/arm/mach-kirkwood/tsx1x-common.h new file mode 100644 index 000000000000..9a592962a6ea --- /dev/null +++ b/arch/arm/mach-kirkwood/tsx1x-common.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ARCH_KIRKWOOD_TSX1X_COMMON_H | ||
| 2 | #define __ARCH_KIRKWOOD_TSX1X_COMMON_H | ||
| 3 | |||
| 4 | extern void qnap_tsx1x_register_flash(void); | ||
| 5 | extern void qnap_tsx1x_power_off(void); | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c index 4562452d4074..a2d307ec0420 100644 --- a/arch/arm/mach-mmp/aspenite.c +++ b/arch/arm/mach-mmp/aspenite.c | |||
| @@ -13,6 +13,9 @@ | |||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/smc91x.h> | 15 | #include <linux/smc91x.h> |
| 16 | #include <linux/mtd/mtd.h> | ||
| 17 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <linux/mtd/nand.h> | ||
| 16 | 19 | ||
| 17 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 18 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| @@ -85,12 +88,48 @@ static struct platform_device smc91x_device = { | |||
| 85 | .resource = smc91x_resources, | 88 | .resource = smc91x_resources, |
| 86 | }; | 89 | }; |
| 87 | 90 | ||
| 91 | static struct mtd_partition aspenite_nand_partitions[] = { | ||
| 92 | { | ||
| 93 | .name = "bootloader", | ||
| 94 | .offset = 0, | ||
| 95 | .size = SZ_1M, | ||
| 96 | .mask_flags = MTD_WRITEABLE, | ||
| 97 | }, { | ||
| 98 | .name = "reserved", | ||
| 99 | .offset = MTDPART_OFS_APPEND, | ||
| 100 | .size = SZ_128K, | ||
| 101 | .mask_flags = MTD_WRITEABLE, | ||
| 102 | }, { | ||
| 103 | .name = "reserved", | ||
| 104 | .offset = MTDPART_OFS_APPEND, | ||
| 105 | .size = SZ_8M, | ||
| 106 | .mask_flags = MTD_WRITEABLE, | ||
| 107 | }, { | ||
| 108 | .name = "kernel", | ||
| 109 | .offset = MTDPART_OFS_APPEND, | ||
| 110 | .size = (SZ_2M + SZ_1M), | ||
| 111 | .mask_flags = 0, | ||
| 112 | }, { | ||
| 113 | .name = "filesystem", | ||
| 114 | .offset = MTDPART_OFS_APPEND, | ||
| 115 | .size = SZ_48M, | ||
| 116 | .mask_flags = 0, | ||
| 117 | } | ||
| 118 | }; | ||
| 119 | |||
| 120 | static struct pxa3xx_nand_platform_data aspenite_nand_info = { | ||
| 121 | .enable_arbiter = 1, | ||
| 122 | .parts = aspenite_nand_partitions, | ||
| 123 | .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), | ||
| 124 | }; | ||
| 125 | |||
| 88 | static void __init common_init(void) | 126 | static void __init common_init(void) |
| 89 | { | 127 | { |
| 90 | mfp_config(ARRAY_AND_SIZE(common_pin_config)); | 128 | mfp_config(ARRAY_AND_SIZE(common_pin_config)); |
| 91 | 129 | ||
| 92 | /* on-chip devices */ | 130 | /* on-chip devices */ |
| 93 | pxa168_add_uart(1); | 131 | pxa168_add_uart(1); |
| 132 | pxa168_add_nand(&aspenite_nand_info); | ||
| 94 | 133 | ||
| 95 | /* off-chip devices */ | 134 | /* off-chip devices */ |
| 96 | platform_device_register(&smc91x_device); | 135 | platform_device_register(&smc91x_device); |
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c index 2d9cc5a7122f..2a46ed5cc2a2 100644 --- a/arch/arm/mach-mmp/clock.c +++ b/arch/arm/mach-mmp/clock.c | |||
| @@ -34,6 +34,21 @@ struct clkops apbc_clk_ops = { | |||
| 34 | .disable = apbc_clk_disable, | 34 | .disable = apbc_clk_disable, |
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | static void apmu_clk_enable(struct clk *clk) | ||
| 38 | { | ||
| 39 | __raw_writel(clk->enable_val, clk->clk_rst); | ||
| 40 | } | ||
| 41 | |||
| 42 | static void apmu_clk_disable(struct clk *clk) | ||
| 43 | { | ||
| 44 | __raw_writel(0, clk->clk_rst); | ||
| 45 | } | ||
| 46 | |||
| 47 | struct clkops apmu_clk_ops = { | ||
| 48 | .enable = apmu_clk_enable, | ||
| 49 | .disable = apmu_clk_disable, | ||
| 50 | }; | ||
| 51 | |||
| 37 | static DEFINE_SPINLOCK(clocks_lock); | 52 | static DEFINE_SPINLOCK(clocks_lock); |
| 38 | 53 | ||
| 39 | int clk_enable(struct clk *clk) | 54 | int clk_enable(struct clk *clk) |
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h index ed967e78e6a8..eefffbe683b0 100644 --- a/arch/arm/mach-mmp/clock.h +++ b/arch/arm/mach-mmp/clock.h | |||
| @@ -25,6 +25,7 @@ struct clk { | |||
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | extern struct clkops apbc_clk_ops; | 27 | extern struct clkops apbc_clk_ops; |
| 28 | extern struct clkops apmu_clk_ops; | ||
| 28 | 29 | ||
| 29 | #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ | 30 | #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ |
| 30 | struct clk clk_##_name = { \ | 31 | struct clk clk_##_name = { \ |
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index 16295cfd5e29..d68871b0f28c 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h | |||
| @@ -31,7 +31,9 @@ | |||
| 31 | #define IRQ_PXA168_DDR_INT 26 | 31 | #define IRQ_PXA168_DDR_INT 26 |
| 32 | #define IRQ_PXA168_UART1 27 | 32 | #define IRQ_PXA168_UART1 27 |
| 33 | #define IRQ_PXA168_UART2 28 | 33 | #define IRQ_PXA168_UART2 28 |
| 34 | #define IRQ_PXA168_UART3 29 | ||
| 34 | #define IRQ_PXA168_WDT 35 | 35 | #define IRQ_PXA168_WDT 35 |
| 36 | #define IRQ_PXA168_MAIN_PMU 36 | ||
| 35 | #define IRQ_PXA168_FRQ_CHANGE 38 | 37 | #define IRQ_PXA168_FRQ_CHANGE 38 |
| 36 | #define IRQ_PXA168_SDH1 39 | 38 | #define IRQ_PXA168_SDH1 39 |
| 37 | #define IRQ_PXA168_SDH2 40 | 39 | #define IRQ_PXA168_SDH2 40 |
| @@ -46,7 +48,7 @@ | |||
| 46 | #define IRQ_PXA168_USB2 51 | 48 | #define IRQ_PXA168_USB2 51 |
| 47 | #define IRQ_PXA168_AC97 57 | 49 | #define IRQ_PXA168_AC97 57 |
| 48 | #define IRQ_PXA168_TWSI1 58 | 50 | #define IRQ_PXA168_TWSI1 58 |
| 49 | #define IRQ_PXA168_PMU 60 | 51 | #define IRQ_PXA168_AP_PMU 60 |
| 50 | #define IRQ_PXA168_SM_INT 63 | 52 | #define IRQ_PXA168_SM_INT 63 |
| 51 | 53 | ||
| 52 | /* | 54 | /* |
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h index 6bf1f0eefcd1..3ad612cbdf09 100644 --- a/arch/arm/mach-mmp/include/mach/pxa168.h +++ b/arch/arm/mach-mmp/include/mach/pxa168.h | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | #include <linux/i2c.h> | 4 | #include <linux/i2c.h> |
| 5 | #include <mach/devices.h> | 5 | #include <mach/devices.h> |
| 6 | #include <plat/i2c.h> | 6 | #include <plat/i2c.h> |
| 7 | #include <plat/pxa3xx_nand.h> | ||
| 7 | 8 | ||
| 8 | extern struct pxa_device_desc pxa168_device_uart1; | 9 | extern struct pxa_device_desc pxa168_device_uart1; |
| 9 | extern struct pxa_device_desc pxa168_device_uart2; | 10 | extern struct pxa_device_desc pxa168_device_uart2; |
| @@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa168_device_pwm1; | |||
| 13 | extern struct pxa_device_desc pxa168_device_pwm2; | 14 | extern struct pxa_device_desc pxa168_device_pwm2; |
| 14 | extern struct pxa_device_desc pxa168_device_pwm3; | 15 | extern struct pxa_device_desc pxa168_device_pwm3; |
| 15 | extern struct pxa_device_desc pxa168_device_pwm4; | 16 | extern struct pxa_device_desc pxa168_device_pwm4; |
| 17 | extern struct pxa_device_desc pxa168_device_nand; | ||
| 16 | 18 | ||
| 17 | static inline int pxa168_add_uart(int id) | 19 | static inline int pxa168_add_uart(int id) |
| 18 | { | 20 | { |
| @@ -64,4 +66,9 @@ static inline int pxa168_add_pwm(int id) | |||
| 64 | 66 | ||
| 65 | return pxa_register_device(d, NULL, 0); | 67 | return pxa_register_device(d, NULL, 0); |
| 66 | } | 68 | } |
| 69 | |||
| 70 | static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) | ||
| 71 | { | ||
| 72 | return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); | ||
| 73 | } | ||
| 67 | #endif /* __ASM_MACH_PXA168_H */ | 74 | #endif /* __ASM_MACH_PXA168_H */ |
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h index 6ae1ed7a0a9f..4f0b4ec6f5d0 100644 --- a/arch/arm/mach-mmp/include/mach/pxa910.h +++ b/arch/arm/mach-mmp/include/mach/pxa910.h | |||
| @@ -4,6 +4,7 @@ | |||
| 4 | #include <linux/i2c.h> | 4 | #include <linux/i2c.h> |
| 5 | #include <mach/devices.h> | 5 | #include <mach/devices.h> |
| 6 | #include <plat/i2c.h> | 6 | #include <plat/i2c.h> |
| 7 | #include <plat/pxa3xx_nand.h> | ||
| 7 | 8 | ||
| 8 | extern struct pxa_device_desc pxa910_device_uart1; | 9 | extern struct pxa_device_desc pxa910_device_uart1; |
| 9 | extern struct pxa_device_desc pxa910_device_uart2; | 10 | extern struct pxa_device_desc pxa910_device_uart2; |
| @@ -13,6 +14,7 @@ extern struct pxa_device_desc pxa910_device_pwm1; | |||
| 13 | extern struct pxa_device_desc pxa910_device_pwm2; | 14 | extern struct pxa_device_desc pxa910_device_pwm2; |
| 14 | extern struct pxa_device_desc pxa910_device_pwm3; | 15 | extern struct pxa_device_desc pxa910_device_pwm3; |
| 15 | extern struct pxa_device_desc pxa910_device_pwm4; | 16 | extern struct pxa_device_desc pxa910_device_pwm4; |
| 17 | extern struct pxa_device_desc pxa910_device_nand; | ||
| 16 | 18 | ||
| 17 | static inline int pxa910_add_uart(int id) | 19 | static inline int pxa910_add_uart(int id) |
| 18 | { | 20 | { |
| @@ -64,4 +66,9 @@ static inline int pxa910_add_pwm(int id) | |||
| 64 | 66 | ||
| 65 | return pxa_register_device(d, NULL, 0); | 67 | return pxa_register_device(d, NULL, 0); |
| 66 | } | 68 | } |
| 69 | |||
| 70 | static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info) | ||
| 71 | { | ||
| 72 | return pxa_register_device(&pxa910_device_nand, info, sizeof(*info)); | ||
| 73 | } | ||
| 67 | #endif /* __ASM_MACH_PXA910_H */ | 74 | #endif /* __ASM_MACH_PXA910_H */ |
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c index 71b1ae338753..37dbdde17fac 100644 --- a/arch/arm/mach-mmp/pxa168.c +++ b/arch/arm/mach-mmp/pxa168.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <mach/addr-map.h> | 19 | #include <mach/addr-map.h> |
| 20 | #include <mach/cputype.h> | 20 | #include <mach/cputype.h> |
| 21 | #include <mach/regs-apbc.h> | 21 | #include <mach/regs-apbc.h> |
| 22 | #include <mach/regs-apmu.h> | ||
| 22 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
| 23 | #include <mach/gpio.h> | 24 | #include <mach/gpio.h> |
| 24 | #include <mach/dma.h> | 25 | #include <mach/dma.h> |
| @@ -72,6 +73,8 @@ static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); | |||
| 72 | static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); | 73 | static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); |
| 73 | static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); | 74 | static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); |
| 74 | 75 | ||
| 76 | static APMU_CLK(nand, NAND, 0x01db, 208000000); | ||
| 77 | |||
| 75 | /* device and clock bindings */ | 78 | /* device and clock bindings */ |
| 76 | static struct clk_lookup pxa168_clkregs[] = { | 79 | static struct clk_lookup pxa168_clkregs[] = { |
| 77 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | 80 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| @@ -82,6 +85,7 @@ static struct clk_lookup pxa168_clkregs[] = { | |||
| 82 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), | 85 | INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), |
| 83 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), | 86 | INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), |
| 84 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), | 87 | INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), |
| 88 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | ||
| 85 | }; | 89 | }; |
| 86 | 90 | ||
| 87 | static int __init pxa168_init(void) | 91 | static int __init pxa168_init(void) |
| @@ -127,3 +131,4 @@ PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); | |||
| 127 | PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); | 131 | PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); |
| 128 | PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); | 132 | PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); |
| 129 | PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); | 133 | PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); |
| 134 | PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); | ||
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c index 5882ca6b49fb..d4049508a4df 100644 --- a/arch/arm/mach-mmp/pxa910.c +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -110,6 +110,8 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); | |||
| 110 | static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); | 110 | static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); |
| 111 | static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); | 111 | static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); |
| 112 | 112 | ||
| 113 | static APMU_CLK(nand, NAND, 0x01db, 208000000); | ||
| 114 | |||
| 113 | /* device and clock bindings */ | 115 | /* device and clock bindings */ |
| 114 | static struct clk_lookup pxa910_clkregs[] = { | 116 | static struct clk_lookup pxa910_clkregs[] = { |
| 115 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | 117 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), |
| @@ -120,6 +122,7 @@ static struct clk_lookup pxa910_clkregs[] = { | |||
| 120 | INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), | 122 | INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), |
| 121 | INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), | 123 | INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), |
| 122 | INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), | 124 | INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), |
| 125 | INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), | ||
| 123 | }; | 126 | }; |
| 124 | 127 | ||
| 125 | static int __init pxa910_init(void) | 128 | static int __init pxa910_init(void) |
| @@ -174,3 +177,4 @@ PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); | |||
| 174 | PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); | 177 | PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); |
| 175 | PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); | 178 | PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); |
| 176 | PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); | 179 | PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); |
| 180 | PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); | ||
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c index 08cfef6c92a2..8f49b2b12608 100644 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ b/arch/arm/mach-mmp/ttc_dkb.c | |||
| @@ -11,9 +11,13 @@ | |||
| 11 | #include <linux/init.h> | 11 | #include <linux/init.h> |
| 12 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/mtd/mtd.h> | ||
| 15 | #include <linux/mtd/partitions.h> | ||
| 16 | #include <linux/mtd/onenand.h> | ||
| 14 | 17 | ||
| 15 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 16 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 20 | #include <asm/mach/flash.h> | ||
| 17 | #include <mach/addr-map.h> | 21 | #include <mach/addr-map.h> |
| 18 | #include <mach/mfp-pxa910.h> | 22 | #include <mach/mfp-pxa910.h> |
| 19 | #include <mach/pxa910.h> | 23 | #include <mach/pxa910.h> |
| @@ -26,6 +30,86 @@ static unsigned long ttc_dkb_pin_config[] __initdata = { | |||
| 26 | /* UART2 */ | 30 | /* UART2 */ |
| 27 | GPIO47_UART2_RXD, | 31 | GPIO47_UART2_RXD, |
| 28 | GPIO48_UART2_TXD, | 32 | GPIO48_UART2_TXD, |
| 33 | |||
| 34 | /* DFI */ | ||
| 35 | DF_IO0_ND_IO0, | ||
| 36 | DF_IO1_ND_IO1, | ||
| 37 | DF_IO2_ND_IO2, | ||
| 38 | DF_IO3_ND_IO3, | ||
| 39 | DF_IO4_ND_IO4, | ||
| 40 | DF_IO5_ND_IO5, | ||
| 41 | DF_IO6_ND_IO6, | ||
| 42 | DF_IO7_ND_IO7, | ||
| 43 | DF_IO8_ND_IO8, | ||
| 44 | DF_IO9_ND_IO9, | ||
| 45 | DF_IO10_ND_IO10, | ||
| 46 | DF_IO11_ND_IO11, | ||
| 47 | DF_IO12_ND_IO12, | ||
| 48 | DF_IO13_ND_IO13, | ||
| 49 | DF_IO14_ND_IO14, | ||
| 50 | DF_IO15_ND_IO15, | ||
| 51 | DF_nCS0_SM_nCS2_nCS0, | ||
| 52 | DF_ALE_SM_WEn_ND_ALE, | ||
| 53 | DF_CLE_SM_OEn_ND_CLE, | ||
| 54 | DF_WEn_DF_WEn, | ||
| 55 | DF_REn_DF_REn, | ||
| 56 | DF_RDY0_DF_RDY0, | ||
| 57 | }; | ||
| 58 | |||
| 59 | static struct mtd_partition ttc_dkb_onenand_partitions[] = { | ||
| 60 | { | ||
| 61 | .name = "bootloader", | ||
| 62 | .offset = 0, | ||
| 63 | .size = SZ_1M, | ||
| 64 | .mask_flags = MTD_WRITEABLE, | ||
| 65 | }, { | ||
| 66 | .name = "reserved", | ||
| 67 | .offset = MTDPART_OFS_APPEND, | ||
| 68 | .size = SZ_128K, | ||
| 69 | .mask_flags = MTD_WRITEABLE, | ||
| 70 | }, { | ||
| 71 | .name = "reserved", | ||
| 72 | .offset = MTDPART_OFS_APPEND, | ||
| 73 | .size = SZ_8M, | ||
| 74 | .mask_flags = MTD_WRITEABLE, | ||
| 75 | }, { | ||
| 76 | .name = "kernel", | ||
| 77 | .offset = MTDPART_OFS_APPEND, | ||
| 78 | .size = (SZ_2M + SZ_1M), | ||
| 79 | .mask_flags = 0, | ||
| 80 | }, { | ||
| 81 | .name = "filesystem", | ||
| 82 | .offset = MTDPART_OFS_APPEND, | ||
| 83 | .size = SZ_48M, | ||
| 84 | .mask_flags = 0, | ||
| 85 | } | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct onenand_platform_data ttc_dkb_onenand_info = { | ||
| 89 | .parts = ttc_dkb_onenand_partitions, | ||
| 90 | .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions), | ||
| 91 | }; | ||
| 92 | |||
| 93 | static struct resource ttc_dkb_resource_onenand[] = { | ||
| 94 | [0] = { | ||
| 95 | .start = SMC_CS0_PHYS_BASE, | ||
| 96 | .end = SMC_CS0_PHYS_BASE + SZ_1M, | ||
| 97 | .flags = IORESOURCE_MEM, | ||
| 98 | }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | static struct platform_device ttc_dkb_device_onenand = { | ||
| 102 | .name = "onenand-flash", | ||
| 103 | .id = -1, | ||
| 104 | .resource = ttc_dkb_resource_onenand, | ||
| 105 | .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand), | ||
| 106 | .dev = { | ||
| 107 | .platform_data = &ttc_dkb_onenand_info, | ||
| 108 | }, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct platform_device *ttc_dkb_devices[] = { | ||
| 112 | &ttc_dkb_device_onenand, | ||
| 29 | }; | 113 | }; |
| 30 | 114 | ||
| 31 | static void __init ttc_dkb_init(void) | 115 | static void __init ttc_dkb_init(void) |
| @@ -34,6 +118,9 @@ static void __init ttc_dkb_init(void) | |||
| 34 | 118 | ||
| 35 | /* on-chip devices */ | 119 | /* on-chip devices */ |
| 36 | pxa910_add_uart(1); | 120 | pxa910_add_uart(1); |
| 121 | |||
| 122 | /* off-chip devices */ | ||
| 123 | platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); | ||
| 37 | } | 124 | } |
| 38 | 125 | ||
| 39 | MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") | 126 | MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") |
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index c8a2eac4d13c..b96c6a389363 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig | |||
| @@ -6,11 +6,13 @@ choice | |||
| 6 | 6 | ||
| 7 | config MACH_MX21 | 7 | config MACH_MX21 |
| 8 | bool "i.MX21 support" | 8 | bool "i.MX21 support" |
| 9 | select ARCH_MXC_AUDMUX_V1 | ||
| 9 | help | 10 | help |
| 10 | This enables support for Freescale's MX2 based i.MX21 processor. | 11 | This enables support for Freescale's MX2 based i.MX21 processor. |
| 11 | 12 | ||
| 12 | config MACH_MX27 | 13 | config MACH_MX27 |
| 13 | bool "i.MX27 support" | 14 | bool "i.MX27 support" |
| 15 | select ARCH_MXC_AUDMUX_V1 | ||
| 14 | help | 16 | help |
| 15 | This enables support for Freescale's MX2 based i.MX27 processor. | 17 | This enables support for Freescale's MX2 based i.MX27 processor. |
| 16 | 18 | ||
| @@ -102,4 +104,11 @@ config MACH_PCA100 | |||
| 102 | Include support for phyCARD-s (aka pca100) platform. This | 104 | Include support for phyCARD-s (aka pca100) platform. This |
| 103 | includes specific configurations for the module and its peripherals. | 105 | includes specific configurations for the module and its peripherals. |
| 104 | 106 | ||
| 107 | config MACH_MXT_TD60 | ||
| 108 | bool "Maxtrack i-MXT TD60" | ||
| 109 | depends on MACH_MX27 | ||
| 110 | help | ||
| 111 | Include support for i-MXT (aka td60) platform. This | ||
| 112 | includes specific configurations for the module and its peripherals. | ||
| 113 | |||
| 105 | endif | 114 | endif |
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 19560f045632..52aca0aaf9b5 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile | |||
| @@ -20,4 +20,5 @@ obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o | |||
| 20 | obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o | 20 | obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o |
| 21 | obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o | 21 | obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o |
| 22 | obj-$(CONFIG_MACH_PCA100) += pca100.o | 22 | obj-$(CONFIG_MACH_PCA100) += pca100.o |
| 23 | obj-$(CONFIG_MACH_MXT_TD60) += mxt_td60.o | ||
| 23 | 24 | ||
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index eede79855f4a..91901b5d56c2 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c | |||
| @@ -1000,7 +1000,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href) | |||
| 1000 | clk_enable(&per_clk[0]); | 1000 | clk_enable(&per_clk[0]); |
| 1001 | clk_enable(&gpio_clk); | 1001 | clk_enable(&gpio_clk); |
| 1002 | 1002 | ||
| 1003 | #ifdef CONFIG_DEBUG_LL_CONSOLE | 1003 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) |
| 1004 | clk_enable(&uart_clk[0]); | 1004 | clk_enable(&uart_clk[0]); |
| 1005 | #endif | 1005 | #endif |
| 1006 | 1006 | ||
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index ff5e33298914..b010bf9ceaab 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c | |||
| @@ -651,8 +651,8 @@ static struct clk_lookup lookups[] = { | |||
| 651 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) | 651 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1) |
| 652 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) | 652 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk) |
| 653 | _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) | 653 | _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1) |
| 654 | _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) | 654 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 655 | _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) | 655 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 656 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) | 656 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) |
| 657 | _REGISTER_CLOCK(NULL, "vpu", vpu_clk) | 657 | _REGISTER_CLOCK(NULL, "vpu", vpu_clk) |
| 658 | _REGISTER_CLOCK(NULL, "dma", dma_clk) | 658 | _REGISTER_CLOCK(NULL, "dma", dma_clk) |
| @@ -751,7 +751,7 @@ int __init mx27_clocks_init(unsigned long fref) | |||
| 751 | clk_enable(&emi_clk); | 751 | clk_enable(&emi_clk); |
| 752 | clk_enable(&iim_clk); | 752 | clk_enable(&iim_clk); |
| 753 | 753 | ||
| 754 | #ifdef CONFIG_DEBUG_LL_CONSOLE | 754 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) |
| 755 | clk_enable(&uart1_clk); | 755 | clk_enable(&uart1_clk); |
| 756 | #endif | 756 | #endif |
| 757 | 757 | ||
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 50199aff0143..3d398ce09b31 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
| @@ -530,6 +530,84 @@ struct platform_device mxc_usbh2 = { | |||
| 530 | }; | 530 | }; |
| 531 | #endif | 531 | #endif |
| 532 | 532 | ||
| 533 | static struct resource imx_ssi_resources0[] = { | ||
| 534 | { | ||
| 535 | .start = SSI1_BASE_ADDR, | ||
| 536 | .end = SSI1_BASE_ADDR + 0x6F, | ||
| 537 | .flags = IORESOURCE_MEM, | ||
| 538 | }, { | ||
| 539 | .start = MXC_INT_SSI1, | ||
| 540 | .end = MXC_INT_SSI1, | ||
| 541 | .flags = IORESOURCE_IRQ, | ||
| 542 | }, { | ||
| 543 | .name = "tx0", | ||
| 544 | .start = DMA_REQ_SSI1_TX0, | ||
| 545 | .end = DMA_REQ_SSI1_TX0, | ||
| 546 | .flags = IORESOURCE_DMA, | ||
| 547 | }, { | ||
| 548 | .name = "rx0", | ||
| 549 | .start = DMA_REQ_SSI1_RX0, | ||
| 550 | .end = DMA_REQ_SSI1_RX0, | ||
| 551 | .flags = IORESOURCE_DMA, | ||
| 552 | }, { | ||
| 553 | .name = "tx1", | ||
| 554 | .start = DMA_REQ_SSI1_TX1, | ||
| 555 | .end = DMA_REQ_SSI1_TX1, | ||
| 556 | .flags = IORESOURCE_DMA, | ||
| 557 | }, { | ||
| 558 | .name = "rx1", | ||
| 559 | .start = DMA_REQ_SSI1_RX1, | ||
| 560 | .end = DMA_REQ_SSI1_RX1, | ||
| 561 | .flags = IORESOURCE_DMA, | ||
| 562 | }, | ||
| 563 | }; | ||
| 564 | |||
| 565 | static struct resource imx_ssi_resources1[] = { | ||
| 566 | { | ||
| 567 | .start = SSI2_BASE_ADDR, | ||
| 568 | .end = SSI2_BASE_ADDR + 0x6F, | ||
| 569 | .flags = IORESOURCE_MEM, | ||
| 570 | }, { | ||
| 571 | .start = MXC_INT_SSI2, | ||
| 572 | .end = MXC_INT_SSI2, | ||
| 573 | .flags = IORESOURCE_IRQ, | ||
| 574 | }, { | ||
| 575 | .name = "tx0", | ||
| 576 | .start = DMA_REQ_SSI2_TX0, | ||
| 577 | .end = DMA_REQ_SSI2_TX0, | ||
| 578 | .flags = IORESOURCE_DMA, | ||
| 579 | }, { | ||
| 580 | .name = "rx0", | ||
| 581 | .start = DMA_REQ_SSI2_RX0, | ||
| 582 | .end = DMA_REQ_SSI2_RX0, | ||
| 583 | .flags = IORESOURCE_DMA, | ||
| 584 | }, { | ||
| 585 | .name = "tx1", | ||
| 586 | .start = DMA_REQ_SSI2_TX1, | ||
| 587 | .end = DMA_REQ_SSI2_TX1, | ||
| 588 | .flags = IORESOURCE_DMA, | ||
| 589 | }, { | ||
| 590 | .name = "rx1", | ||
| 591 | .start = DMA_REQ_SSI2_RX1, | ||
| 592 | .end = DMA_REQ_SSI2_RX1, | ||
| 593 | .flags = IORESOURCE_DMA, | ||
| 594 | }, | ||
| 595 | }; | ||
| 596 | |||
| 597 | struct platform_device imx_ssi_device0 = { | ||
| 598 | .name = "imx-ssi", | ||
| 599 | .id = 0, | ||
| 600 | .num_resources = ARRAY_SIZE(imx_ssi_resources0), | ||
| 601 | .resource = imx_ssi_resources0, | ||
| 602 | }; | ||
| 603 | |||
| 604 | struct platform_device imx_ssi_device1 = { | ||
| 605 | .name = "imx-ssi", | ||
| 606 | .id = 1, | ||
| 607 | .num_resources = ARRAY_SIZE(imx_ssi_resources1), | ||
| 608 | .resource = imx_ssi_resources1, | ||
| 609 | }; | ||
| 610 | |||
| 533 | /* GPIO port description */ | 611 | /* GPIO port description */ |
| 534 | static struct mxc_gpio_port imx_gpio_ports[] = { | 612 | static struct mxc_gpio_port imx_gpio_ports[] = { |
| 535 | { | 613 | { |
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index d315406d6725..97306aa18f1c 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h | |||
| @@ -26,4 +26,5 @@ extern struct platform_device mxc_usbh2; | |||
| 26 | extern struct platform_device mxc_spi_device0; | 26 | extern struct platform_device mxc_spi_device0; |
| 27 | extern struct platform_device mxc_spi_device1; | 27 | extern struct platform_device mxc_spi_device1; |
| 28 | extern struct platform_device mxc_spi_device2; | 28 | extern struct platform_device mxc_spi_device2; |
| 29 | 29 | extern struct platform_device imx_ssi_device0; | |
| 30 | extern struct platform_device imx_ssi_device1; | ||
diff --git a/arch/arm/mach-mx2/mxt_td60.c b/arch/arm/mach-mx2/mxt_td60.c new file mode 100644 index 000000000000..03dbbdc98955 --- /dev/null +++ b/arch/arm/mach-mx2/mxt_td60.c | |||
| @@ -0,0 +1,319 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 4 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/platform_device.h> | ||
| 22 | #include <linux/mtd/mtd.h> | ||
| 23 | #include <linux/mtd/map.h> | ||
| 24 | #include <linux/mtd/partitions.h> | ||
| 25 | #include <linux/mtd/physmap.h> | ||
| 26 | #include <linux/i2c.h> | ||
| 27 | #include <linux/irq.h> | ||
| 28 | #include <mach/common.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | #include <asm/mach/map.h> | ||
| 34 | #include <linux/gpio.h> | ||
| 35 | #include <mach/imx-uart.h> | ||
| 36 | #include <mach/iomux.h> | ||
| 37 | #include <mach/mxc_nand.h> | ||
| 38 | #include <mach/i2c.h> | ||
| 39 | #include <linux/i2c/pca953x.h> | ||
| 40 | #include <mach/imxfb.h> | ||
| 41 | #include <mach/mmc.h> | ||
| 42 | |||
| 43 | #include "devices.h" | ||
| 44 | |||
| 45 | static unsigned int mxt_td60_pins[] __initdata = { | ||
| 46 | /* UART0 */ | ||
| 47 | PE12_PF_UART1_TXD, | ||
| 48 | PE13_PF_UART1_RXD, | ||
| 49 | PE14_PF_UART1_CTS, | ||
| 50 | PE15_PF_UART1_RTS, | ||
| 51 | /* UART1 */ | ||
| 52 | PE3_PF_UART2_CTS, | ||
| 53 | PE4_PF_UART2_RTS, | ||
| 54 | PE6_PF_UART2_TXD, | ||
| 55 | PE7_PF_UART2_RXD, | ||
| 56 | /* UART2 */ | ||
| 57 | PE8_PF_UART3_TXD, | ||
| 58 | PE9_PF_UART3_RXD, | ||
| 59 | PE10_PF_UART3_CTS, | ||
| 60 | PE11_PF_UART3_RTS, | ||
| 61 | /* UART3 */ | ||
| 62 | PB26_AF_UART4_RTS, | ||
| 63 | PB28_AF_UART4_TXD, | ||
| 64 | PB29_AF_UART4_CTS, | ||
| 65 | PB31_AF_UART4_RXD, | ||
| 66 | /* UART4 */ | ||
| 67 | PB18_AF_UART5_TXD, | ||
| 68 | PB19_AF_UART5_RXD, | ||
| 69 | PB20_AF_UART5_CTS, | ||
| 70 | PB21_AF_UART5_RTS, | ||
| 71 | /* UART5 */ | ||
| 72 | PB10_AF_UART6_TXD, | ||
| 73 | PB12_AF_UART6_CTS, | ||
| 74 | PB11_AF_UART6_RXD, | ||
| 75 | PB13_AF_UART6_RTS, | ||
| 76 | /* FEC */ | ||
| 77 | PD0_AIN_FEC_TXD0, | ||
| 78 | PD1_AIN_FEC_TXD1, | ||
| 79 | PD2_AIN_FEC_TXD2, | ||
| 80 | PD3_AIN_FEC_TXD3, | ||
| 81 | PD4_AOUT_FEC_RX_ER, | ||
| 82 | PD5_AOUT_FEC_RXD1, | ||
| 83 | PD6_AOUT_FEC_RXD2, | ||
| 84 | PD7_AOUT_FEC_RXD3, | ||
| 85 | PD8_AF_FEC_MDIO, | ||
| 86 | PD9_AIN_FEC_MDC, | ||
| 87 | PD10_AOUT_FEC_CRS, | ||
| 88 | PD11_AOUT_FEC_TX_CLK, | ||
| 89 | PD12_AOUT_FEC_RXD0, | ||
| 90 | PD13_AOUT_FEC_RX_DV, | ||
| 91 | PD14_AOUT_FEC_RX_CLK, | ||
| 92 | PD15_AOUT_FEC_COL, | ||
| 93 | PD16_AIN_FEC_TX_ER, | ||
| 94 | PF23_AIN_FEC_TX_EN, | ||
| 95 | /* I2C1 */ | ||
| 96 | PD17_PF_I2C_DATA, | ||
| 97 | PD18_PF_I2C_CLK, | ||
| 98 | /* I2C2 */ | ||
| 99 | PC5_PF_I2C2_SDA, | ||
| 100 | PC6_PF_I2C2_SCL, | ||
| 101 | /* FB */ | ||
| 102 | PA5_PF_LSCLK, | ||
| 103 | PA6_PF_LD0, | ||
| 104 | PA7_PF_LD1, | ||
| 105 | PA8_PF_LD2, | ||
| 106 | PA9_PF_LD3, | ||
| 107 | PA10_PF_LD4, | ||
| 108 | PA11_PF_LD5, | ||
| 109 | PA12_PF_LD6, | ||
| 110 | PA13_PF_LD7, | ||
| 111 | PA14_PF_LD8, | ||
| 112 | PA15_PF_LD9, | ||
| 113 | PA16_PF_LD10, | ||
| 114 | PA17_PF_LD11, | ||
| 115 | PA18_PF_LD12, | ||
| 116 | PA19_PF_LD13, | ||
| 117 | PA20_PF_LD14, | ||
| 118 | PA21_PF_LD15, | ||
| 119 | PA22_PF_LD16, | ||
| 120 | PA23_PF_LD17, | ||
| 121 | PA25_PF_CLS, | ||
| 122 | PA27_PF_SPL_SPR, | ||
| 123 | PA28_PF_HSYNC, | ||
| 124 | PA29_PF_VSYNC, | ||
| 125 | PA30_PF_CONTRAST, | ||
| 126 | PA31_PF_OE_ACD, | ||
| 127 | /* OWIRE */ | ||
| 128 | PE16_AF_OWIRE, | ||
| 129 | /* SDHC1*/ | ||
| 130 | PE18_PF_SD1_D0, | ||
| 131 | PE19_PF_SD1_D1, | ||
| 132 | PE20_PF_SD1_D2, | ||
| 133 | PE21_PF_SD1_D3, | ||
| 134 | PE22_PF_SD1_CMD, | ||
| 135 | PE23_PF_SD1_CLK, | ||
| 136 | PF8_AF_ATA_IORDY, | ||
| 137 | /* SDHC2*/ | ||
| 138 | PB4_PF_SD2_D0, | ||
| 139 | PB5_PF_SD2_D1, | ||
| 140 | PB6_PF_SD2_D2, | ||
| 141 | PB7_PF_SD2_D3, | ||
| 142 | PB8_PF_SD2_CMD, | ||
| 143 | PB9_PF_SD2_CLK, | ||
| 144 | }; | ||
| 145 | |||
| 146 | static struct mxc_nand_platform_data mxt_td60_nand_board_info = { | ||
| 147 | .width = 1, | ||
| 148 | .hw_ecc = 1, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static struct imxi2c_platform_data mxt_td60_i2c_data = { | ||
| 152 | .bitrate = 100000, | ||
| 153 | }; | ||
| 154 | |||
| 155 | /* PCA9557 */ | ||
| 156 | static int mxt_td60_pca9557_setup(struct i2c_client *client, | ||
| 157 | unsigned gpio_base, unsigned ngpio, | ||
| 158 | void *context) | ||
| 159 | { | ||
| 160 | static int mxt_td60_gpio_value[] = { | ||
| 161 | -1, -1, -1, -1, -1, -1, -1, 1 | ||
| 162 | }; | ||
| 163 | int n; | ||
| 164 | |||
| 165 | for (n = 0; n < ARRAY_SIZE(mxt_td60_gpio_value); ++n) { | ||
| 166 | gpio_request(gpio_base + n, "MXT_TD60 GPIO Exp"); | ||
| 167 | if (mxt_td60_gpio_value[n] < 0) | ||
| 168 | gpio_direction_input(gpio_base + n); | ||
| 169 | else | ||
| 170 | gpio_direction_output(gpio_base + n, | ||
| 171 | mxt_td60_gpio_value[n]); | ||
| 172 | gpio_export(gpio_base + n, 0); | ||
| 173 | } | ||
| 174 | |||
| 175 | return 0; | ||
| 176 | } | ||
| 177 | |||
| 178 | static struct pca953x_platform_data mxt_td60_pca9557_pdata = { | ||
| 179 | .gpio_base = 240, /* place PCA9557 after all MX27 gpio pins */ | ||
| 180 | .invert = 0, /* Do not invert */ | ||
| 181 | .setup = mxt_td60_pca9557_setup, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static struct i2c_board_info mxt_td60_i2c_devices[] = { | ||
| 185 | { | ||
| 186 | I2C_BOARD_INFO("pca9557", 0x18), | ||
| 187 | .platform_data = &mxt_td60_pca9557_pdata, | ||
| 188 | }, | ||
| 189 | }; | ||
| 190 | |||
| 191 | static struct imxi2c_platform_data mxt_td60_i2c2_data = { | ||
| 192 | .bitrate = 100000, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct i2c_board_info mxt_td60_i2c2_devices[] = { | ||
| 196 | }; | ||
| 197 | |||
| 198 | static struct imx_fb_videomode mxt_td60_modes[] = { | ||
| 199 | { | ||
| 200 | .mode = { | ||
| 201 | .name = "Chimei LW700AT9003", | ||
| 202 | .refresh = 60, | ||
| 203 | .xres = 800, | ||
| 204 | .yres = 480, | ||
| 205 | .pixclock = 30303, | ||
| 206 | .hsync_len = 64, | ||
| 207 | .left_margin = 0x67, | ||
| 208 | .right_margin = 0x68, | ||
| 209 | .vsync_len = 16, | ||
| 210 | .upper_margin = 0x0f, | ||
| 211 | .lower_margin = 0x0f, | ||
| 212 | }, | ||
| 213 | .bpp = 16, | ||
| 214 | .pcr = 0xFA208B83, | ||
| 215 | }, | ||
| 216 | }; | ||
| 217 | |||
| 218 | static struct imx_fb_platform_data mxt_td60_fb_data = { | ||
| 219 | .mode = mxt_td60_modes, | ||
| 220 | .num_modes = ARRAY_SIZE(mxt_td60_modes), | ||
| 221 | |||
| 222 | /* | ||
| 223 | * - HSYNC active high | ||
| 224 | * - VSYNC active high | ||
| 225 | * - clk notenabled while idle | ||
| 226 | * - clock inverted | ||
| 227 | * - data not inverted | ||
| 228 | * - data enable low active | ||
| 229 | * - enable sharp mode | ||
| 230 | */ | ||
| 231 | .pwmr = 0x00A903FF, | ||
| 232 | .lscr1 = 0x00120300, | ||
| 233 | .dmacr = 0x00020010, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq, | ||
| 237 | void *data) | ||
| 238 | { | ||
| 239 | return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING, | ||
| 240 | "sdhc1-card-detect", data); | ||
| 241 | } | ||
| 242 | |||
| 243 | static void mxt_td60_sdhc1_exit(struct device *dev, void *data) | ||
| 244 | { | ||
| 245 | free_irq(IRQ_GPIOF(8), data); | ||
| 246 | } | ||
| 247 | |||
| 248 | static struct imxmmc_platform_data sdhc1_pdata = { | ||
| 249 | .init = mxt_td60_sdhc1_init, | ||
| 250 | .exit = mxt_td60_sdhc1_exit, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static struct platform_device *platform_devices[] __initdata = { | ||
| 254 | &mxc_fec_device, | ||
| 255 | }; | ||
| 256 | |||
| 257 | static struct imxuart_platform_data uart_pdata[] = { | ||
| 258 | { | ||
| 259 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 260 | }, { | ||
| 261 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 262 | }, { | ||
| 263 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 264 | }, { | ||
| 265 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 266 | }, { | ||
| 267 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 268 | }, { | ||
| 269 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 270 | }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | static void __init mxt_td60_board_init(void) | ||
| 274 | { | ||
| 275 | mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins), | ||
| 276 | "MXT_TD60"); | ||
| 277 | |||
| 278 | mxc_register_device(&mxc_uart_device0, &uart_pdata[0]); | ||
| 279 | mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); | ||
| 280 | mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); | ||
| 281 | mxc_register_device(&mxc_uart_device3, &uart_pdata[3]); | ||
| 282 | mxc_register_device(&mxc_uart_device4, &uart_pdata[4]); | ||
| 283 | mxc_register_device(&mxc_uart_device5, &uart_pdata[5]); | ||
| 284 | mxc_register_device(&mxc_nand_device, &mxt_td60_nand_board_info); | ||
| 285 | |||
| 286 | i2c_register_board_info(0, mxt_td60_i2c_devices, | ||
| 287 | ARRAY_SIZE(mxt_td60_i2c_devices)); | ||
| 288 | |||
| 289 | i2c_register_board_info(1, mxt_td60_i2c2_devices, | ||
| 290 | ARRAY_SIZE(mxt_td60_i2c2_devices)); | ||
| 291 | |||
| 292 | mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data); | ||
| 293 | mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data); | ||
| 294 | mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); | ||
| 295 | mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); | ||
| 296 | |||
| 297 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | ||
| 298 | } | ||
| 299 | |||
| 300 | static void __init mxt_td60_timer_init(void) | ||
| 301 | { | ||
| 302 | mx27_clocks_init(26000000); | ||
| 303 | } | ||
| 304 | |||
| 305 | static struct sys_timer mxt_td60_timer = { | ||
| 306 | .init = mxt_td60_timer_init, | ||
| 307 | }; | ||
| 308 | |||
| 309 | MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") | ||
| 310 | /* maintainer: Maxtrack Industrial */ | ||
| 311 | .phys_io = AIPI_BASE_ADDR, | ||
| 312 | .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, | ||
| 313 | .boot_params = PHYS_OFFSET + 0x100, | ||
| 314 | .map_io = mx27_map_io, | ||
| 315 | .init_irq = mx27_init_irq, | ||
| 316 | .init_machine = mxt_td60_board_init, | ||
| 317 | .timer = &mxt_td60_timer, | ||
| 318 | MACHINE_END | ||
| 319 | |||
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c index fe5b165b88cc..aea3d340d2e1 100644 --- a/arch/arm/mach-mx2/pca100.c +++ b/arch/arm/mach-mx2/pca100.c | |||
| @@ -237,7 +237,7 @@ MACHINE_START(PCA100, "phyCARD-i.MX27") | |||
| 237 | .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 237 | .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 238 | .boot_params = PHYS_OFFSET + 0x100, | 238 | .boot_params = PHYS_OFFSET + 0x100, |
| 239 | .map_io = mx27_map_io, | 239 | .map_io = mx27_map_io, |
| 240 | .init_irq = mxc_init_irq, | 240 | .init_irq = mx27_init_irq, |
| 241 | .init_machine = pca100_init, | 241 | .init_machine = pca100_init, |
| 242 | .timer = &pca100_timer, | 242 | .timer = &pca100_timer, |
| 243 | MACHINE_END | 243 | MACHINE_END |
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 851f2458bf65..ea8ed109a7c2 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig | |||
| @@ -2,11 +2,13 @@ if ARCH_MX3 | |||
| 2 | 2 | ||
| 3 | config ARCH_MX31 | 3 | config ARCH_MX31 |
| 4 | select ARCH_HAS_RNGA | 4 | select ARCH_HAS_RNGA |
| 5 | select ARCH_MXC_AUDMUX_V2 | ||
| 5 | bool | 6 | bool |
| 6 | 7 | ||
| 7 | config ARCH_MX35 | 8 | config ARCH_MX35 |
| 8 | bool | 9 | bool |
| 9 | select ARCH_MXC_IOMUX_V3 | 10 | select ARCH_MXC_IOMUX_V3 |
| 11 | select ARCH_MXC_AUDMUX_V2 | ||
| 10 | 12 | ||
| 11 | comment "MX3 platforms:" | 13 | comment "MX3 platforms:" |
| 12 | 14 | ||
| @@ -61,6 +63,7 @@ config MACH_MX31_3DS | |||
| 61 | config MACH_MX31MOBOARD | 63 | config MACH_MX31MOBOARD |
| 62 | bool "Support mx31moboard platforms (EPFL Mobots group)" | 64 | bool "Support mx31moboard platforms (EPFL Mobots group)" |
| 63 | select ARCH_MX31 | 65 | select ARCH_MX31 |
| 66 | select MXC_ULPI | ||
| 64 | help | 67 | help |
| 65 | Include support for mx31moboard platform. This includes specific | 68 | Include support for mx31moboard platform. This includes specific |
| 66 | configurations for the board and its peripherals. | 69 | configurations for the board and its peripherals. |
| @@ -100,4 +103,12 @@ config MACH_MX35_3DS | |||
| 100 | help | 103 | help |
| 101 | Include support for MX35PDK platform. This includes specific | 104 | Include support for MX35PDK platform. This includes specific |
| 102 | configurations for the board and its peripherals. | 105 | configurations for the board and its peripherals. |
| 106 | |||
| 107 | config MACH_KZM_ARM11_01 | ||
| 108 | bool "Support KZM-ARM11-01(Kyoto Microcomputer)" | ||
| 109 | select ARCH_MX31 | ||
| 110 | help | ||
| 111 | Include support for KZM-ARM11-01. This includes specific | ||
| 112 | configurations for the board and its peripherals. | ||
| 113 | |||
| 103 | endif | 114 | endif |
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 6b9775471be6..93c7b296be6a 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile | |||
| @@ -4,12 +4,12 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := mm.o devices.o | 7 | obj-y := mm.o devices.o cpu.o |
| 8 | obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o | 8 | obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o |
| 9 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o | 9 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o |
| 10 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o | 10 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o |
| 11 | obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o | 11 | obj-$(CONFIG_MACH_MX31LILLY) += mx31lilly.o mx31lilly-db.o |
| 12 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o | 12 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o mx31lite-db.o |
| 13 | obj-$(CONFIG_MACH_PCM037) += pcm037.o | 13 | obj-$(CONFIG_MACH_PCM037) += pcm037.o |
| 14 | obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o | 14 | obj-$(CONFIG_MACH_PCM037_EET) += pcm037_eet.o |
| 15 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o | 15 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o |
| @@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_QONG) += qong.o | |||
| 19 | obj-$(CONFIG_MACH_PCM043) += pcm043.o | 19 | obj-$(CONFIG_MACH_PCM043) += pcm043.o |
| 20 | obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o | 20 | obj-$(CONFIG_MACH_ARMADILLO5X0) += armadillo5x0.o |
| 21 | obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o | 21 | obj-$(CONFIG_MACH_MX35_3DS) += mx35pdk.o |
| 22 | obj-$(CONFIG_MACH_KZM_ARM11_01) += kzmarm11.o | ||
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c index 776c0ee1b3cd..54aab401dbdf 100644 --- a/arch/arm/mach-mx3/armadillo5x0.c +++ b/arch/arm/mach-mx3/armadillo5x0.c | |||
| @@ -33,6 +33,9 @@ | |||
| 33 | #include <linux/irq.h> | 33 | #include <linux/irq.h> |
| 34 | #include <linux/mtd/physmap.h> | 34 | #include <linux/mtd/physmap.h> |
| 35 | #include <linux/io.h> | 35 | #include <linux/io.h> |
| 36 | #include <linux/input.h> | ||
| 37 | #include <linux/gpio_keys.h> | ||
| 38 | #include <linux/i2c.h> | ||
| 36 | 39 | ||
| 37 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
| 38 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| @@ -97,6 +100,47 @@ static int armadillo5x0_pins[] = { | |||
| 97 | MX31_PIN_FPSHIFT__FPSHIFT, | 100 | MX31_PIN_FPSHIFT__FPSHIFT, |
| 98 | MX31_PIN_DRDY0__DRDY0, | 101 | MX31_PIN_DRDY0__DRDY0, |
| 99 | IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ | 102 | IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/ |
| 103 | /* I2C2 */ | ||
| 104 | MX31_PIN_CSPI2_MOSI__SCL, | ||
| 105 | MX31_PIN_CSPI2_MISO__SDA, | ||
| 106 | }; | ||
| 107 | |||
| 108 | /* RTC over I2C*/ | ||
| 109 | #define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4) | ||
| 110 | |||
| 111 | static struct i2c_board_info armadillo5x0_i2c_rtc = { | ||
| 112 | I2C_BOARD_INFO("s35390a", 0x30), | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* GPIO BUTTONS */ | ||
| 116 | static struct gpio_keys_button armadillo5x0_buttons[] = { | ||
| 117 | { | ||
| 118 | .code = KEY_ENTER, /*28*/ | ||
| 119 | .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0), | ||
| 120 | .active_low = 1, | ||
| 121 | .desc = "menu", | ||
| 122 | .wakeup = 1, | ||
| 123 | }, { | ||
| 124 | .code = KEY_BACK, /*158*/ | ||
| 125 | .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0), | ||
| 126 | .active_low = 1, | ||
| 127 | .desc = "back", | ||
| 128 | .wakeup = 1, | ||
| 129 | } | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct gpio_keys_platform_data armadillo5x0_button_data = { | ||
| 133 | .buttons = armadillo5x0_buttons, | ||
| 134 | .nbuttons = ARRAY_SIZE(armadillo5x0_buttons), | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct platform_device armadillo5x0_button_device = { | ||
| 138 | .name = "gpio-keys", | ||
| 139 | .id = -1, | ||
| 140 | .num_resources = 0, | ||
| 141 | .dev = { | ||
| 142 | .platform_data = &armadillo5x0_button_data, | ||
| 143 | } | ||
| 100 | }; | 144 | }; |
| 101 | 145 | ||
| 102 | /* | 146 | /* |
| @@ -278,7 +322,7 @@ static struct resource armadillo5x0_smc911x_resources[] = { | |||
| 278 | }; | 322 | }; |
| 279 | 323 | ||
| 280 | static struct smsc911x_platform_config smsc911x_info = { | 324 | static struct smsc911x_platform_config smsc911x_info = { |
| 281 | .flags = SMSC911X_USE_32BIT, | 325 | .flags = SMSC911X_USE_16BIT, |
| 282 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | 326 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, |
| 283 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | 327 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, |
| 284 | }; | 328 | }; |
| @@ -300,6 +344,8 @@ static struct imxuart_platform_data uart_pdata = { | |||
| 300 | 344 | ||
| 301 | static struct platform_device *devices[] __initdata = { | 345 | static struct platform_device *devices[] __initdata = { |
| 302 | &armadillo5x0_smc911x_device, | 346 | &armadillo5x0_smc911x_device, |
| 347 | &mxc_i2c_device1, | ||
| 348 | &armadillo5x0_button_device, | ||
| 303 | }; | 349 | }; |
| 304 | 350 | ||
| 305 | /* | 351 | /* |
| @@ -335,6 +381,18 @@ static void __init armadillo5x0_init(void) | |||
| 335 | 381 | ||
| 336 | /* set NAND page size to 2k if not configured via boot mode pins */ | 382 | /* set NAND page size to 2k if not configured via boot mode pins */ |
| 337 | __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); | 383 | __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); |
| 384 | |||
| 385 | /* RTC */ | ||
| 386 | /* Get RTC IRQ and register the chip */ | ||
| 387 | if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) { | ||
| 388 | if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0) | ||
| 389 | armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO); | ||
| 390 | else | ||
| 391 | gpio_free(ARMADILLO5X0_RTC_GPIO); | ||
| 392 | } | ||
| 393 | if (armadillo5x0_i2c_rtc.irq == 0) | ||
| 394 | pr_warning("armadillo5x0_init: failed to get RTC IRQ\n"); | ||
| 395 | i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1); | ||
| 338 | } | 396 | } |
| 339 | 397 | ||
| 340 | static void __init armadillo5x0_timer_init(void) | 398 | static void __init armadillo5x0_timer_init(void) |
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index c595260ec1f9..7584b4c6c556 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c | |||
| @@ -335,7 +335,7 @@ static void clk_cgr_disable(struct clk *clk) | |||
| 335 | 335 | ||
| 336 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); | 336 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); |
| 337 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); | 337 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); |
| 338 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); | 338 | /* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */ |
| 339 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); | 339 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); |
| 340 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); | 340 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); |
| 341 | DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); | 341 | DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); |
| @@ -381,12 +381,43 @@ DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); | |||
| 381 | DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); | 381 | DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL); |
| 382 | DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); | 382 | DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); |
| 383 | DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); | 383 | DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); |
| 384 | DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); | 384 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL); |
| 385 | 385 | ||
| 386 | DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); | 386 | DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); |
| 387 | DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); | 387 | DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); |
| 388 | DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | 388 | DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); |
| 389 | 389 | ||
| 390 | DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL); | ||
| 391 | |||
| 392 | static int clk_dummy_enable(struct clk *clk) | ||
| 393 | { | ||
| 394 | return 0; | ||
| 395 | } | ||
| 396 | |||
| 397 | static void clk_dummy_disable(struct clk *clk) | ||
| 398 | { | ||
| 399 | } | ||
| 400 | |||
| 401 | static unsigned long get_rate_nfc(struct clk *clk) | ||
| 402 | { | ||
| 403 | unsigned long div1; | ||
| 404 | |||
| 405 | div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1; | ||
| 406 | |||
| 407 | return get_rate_ahb(NULL) / div1; | ||
| 408 | } | ||
| 409 | |||
| 410 | /* NAND Controller: It seems it can't be disabled */ | ||
| 411 | static struct clk nfc_clk = { | ||
| 412 | .id = 0, | ||
| 413 | .enable_reg = 0, | ||
| 414 | .enable_shift = 0, | ||
| 415 | .get_rate = get_rate_nfc, | ||
| 416 | .set_rate = NULL, /* set_rate_nfc, */ | ||
| 417 | .enable = clk_dummy_enable, | ||
| 418 | .disable = clk_dummy_disable | ||
| 419 | }; | ||
| 420 | |||
| 390 | #define _REGISTER_CLOCK(d, n, c) \ | 421 | #define _REGISTER_CLOCK(d, n, c) \ |
| 391 | { \ | 422 | { \ |
| 392 | .dev_id = d, \ | 423 | .dev_id = d, \ |
| @@ -397,7 +428,6 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | |||
| 397 | static struct clk_lookup lookups[] = { | 428 | static struct clk_lookup lookups[] = { |
| 398 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | 429 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) |
| 399 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 430 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
| 400 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | ||
| 401 | _REGISTER_CLOCK(NULL, "can", can1_clk) | 431 | _REGISTER_CLOCK(NULL, "can", can1_clk) |
| 402 | _REGISTER_CLOCK(NULL, "can", can2_clk) | 432 | _REGISTER_CLOCK(NULL, "can", can2_clk) |
| 403 | _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) | 433 | _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) |
| @@ -434,8 +464,8 @@ static struct clk_lookup lookups[] = { | |||
| 434 | _REGISTER_CLOCK(NULL, "sdma", sdma_clk) | 464 | _REGISTER_CLOCK(NULL, "sdma", sdma_clk) |
| 435 | _REGISTER_CLOCK(NULL, "spba", spba_clk) | 465 | _REGISTER_CLOCK(NULL, "spba", spba_clk) |
| 436 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | 466 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) |
| 437 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | 467 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 438 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | 468 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 439 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | 469 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 440 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | 470 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 441 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 471 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| @@ -443,12 +473,14 @@ static struct clk_lookup lookups[] = { | |||
| 443 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) | 473 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk) |
| 444 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) | 474 | _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) |
| 445 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) | 475 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) |
| 476 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) | ||
| 446 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) | 477 | _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) |
| 447 | _REGISTER_CLOCK(NULL, "max", max_clk) | 478 | _REGISTER_CLOCK(NULL, "max", max_clk) |
| 448 | _REGISTER_CLOCK(NULL, "admux", admux_clk) | 479 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) |
| 449 | _REGISTER_CLOCK(NULL, "csi", csi_clk) | 480 | _REGISTER_CLOCK(NULL, "csi", csi_clk) |
| 450 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | 481 | _REGISTER_CLOCK(NULL, "iim", iim_clk) |
| 451 | _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) | 482 | _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) |
| 483 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) | ||
| 452 | }; | 484 | }; |
| 453 | 485 | ||
| 454 | int __init mx35_clocks_init() | 486 | int __init mx35_clocks_init() |
| @@ -456,7 +488,7 @@ int __init mx35_clocks_init() | |||
| 456 | int i; | 488 | int i; |
| 457 | unsigned int ll = 0; | 489 | unsigned int ll = 0; |
| 458 | 490 | ||
| 459 | #ifdef CONFIG_DEBUG_LL_CONSOLE | 491 | #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) |
| 460 | ll = (3 << 16); | 492 | ll = (3 << 16); |
| 461 | #endif | 493 | #endif |
| 462 | 494 | ||
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index b2a3bcf8266e..27a318af0d20 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c | |||
| @@ -558,8 +558,8 @@ static struct clk_lookup lookups[] = { | |||
| 558 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) | 558 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) |
| 559 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) | 559 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) |
| 560 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) | 560 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) |
| 561 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | 561 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
| 562 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | 562 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
| 563 | _REGISTER_CLOCK(NULL, "firi", firi_clk) | 563 | _REGISTER_CLOCK(NULL, "firi", firi_clk) |
| 564 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 564 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
| 565 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | 565 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) |
| @@ -616,6 +616,8 @@ int __init mx31_clocks_init(unsigned long fref) | |||
| 616 | 616 | ||
| 617 | clk_enable(&serial_pll_clk); | 617 | clk_enable(&serial_pll_clk); |
| 618 | 618 | ||
| 619 | mx31_read_cpu_rev(); | ||
| 620 | |||
| 619 | if (mx31_revision() >= CHIP_REV_2_0) { | 621 | if (mx31_revision() >= CHIP_REV_2_0) { |
| 620 | reg = __raw_readl(MXC_CCM_PMCR1); | 622 | reg = __raw_readl(MXC_CCM_PMCR1); |
| 621 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ | 623 | /* No PLL restart on DVFS switch; enable auto EMI handshake */ |
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c new file mode 100644 index 000000000000..db828809c675 --- /dev/null +++ b/arch/arm/mach-mx3/cpu.c | |||
| @@ -0,0 +1,57 @@ | |||
| 1 | /* | ||
| 2 | * MX3 CPU type detection | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <mach/hardware.h> | ||
| 15 | #include <mach/iim.h> | ||
| 16 | |||
| 17 | unsigned int mx31_cpu_rev; | ||
| 18 | EXPORT_SYMBOL(mx31_cpu_rev); | ||
| 19 | |||
| 20 | struct mx3_cpu_type { | ||
| 21 | u8 srev; | ||
| 22 | const char *name; | ||
| 23 | const char *v; | ||
| 24 | unsigned int rev; | ||
| 25 | }; | ||
| 26 | |||
| 27 | static struct mx3_cpu_type mx31_cpu_type[] __initdata = { | ||
| 28 | { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 }, | ||
| 29 | { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 }, | ||
| 30 | { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 }, | ||
| 31 | { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 }, | ||
| 32 | { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 }, | ||
| 33 | { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 }, | ||
| 34 | { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 }, | ||
| 35 | { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 }, | ||
| 36 | { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 }, | ||
| 37 | }; | ||
| 38 | |||
| 39 | void __init mx31_read_cpu_rev(void) | ||
| 40 | { | ||
| 41 | u32 i, srev; | ||
| 42 | |||
| 43 | /* read SREV register from IIM module */ | ||
| 44 | srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR) + MXC_IIMSREV); | ||
| 45 | |||
| 46 | for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) | ||
| 47 | if (srev == mx31_cpu_type[i].srev) { | ||
| 48 | printk(KERN_INFO | ||
| 49 | "CPU identified as %s, silicon rev %s\n", | ||
| 50 | mx31_cpu_type[i].name, mx31_cpu_type[i].v); | ||
| 51 | |||
| 52 | mx31_cpu_rev = mx31_cpu_type[i].rev; | ||
| 53 | return; | ||
| 54 | } | ||
| 55 | |||
| 56 | printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); | ||
| 57 | } | ||
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index e6abe181b967..6adb586515ea 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
| @@ -537,6 +537,44 @@ struct platform_device mxc_fec_device = { | |||
| 537 | }; | 537 | }; |
| 538 | #endif | 538 | #endif |
| 539 | 539 | ||
| 540 | static struct resource imx_ssi_resources0[] = { | ||
| 541 | { | ||
| 542 | .start = SSI1_BASE_ADDR, | ||
| 543 | .end = SSI1_BASE_ADDR + 0xfff, | ||
| 544 | .flags = IORESOURCE_MEM, | ||
| 545 | }, { | ||
| 546 | .start = MX31_INT_SSI1, | ||
| 547 | .end = MX31_INT_SSI1, | ||
| 548 | .flags = IORESOURCE_IRQ, | ||
| 549 | }, | ||
| 550 | }; | ||
| 551 | |||
| 552 | static struct resource imx_ssi_resources1[] = { | ||
| 553 | { | ||
| 554 | .start = SSI2_BASE_ADDR, | ||
| 555 | .end = SSI2_BASE_ADDR + 0xfff, | ||
| 556 | .flags = IORESOURCE_MEM | ||
| 557 | }, { | ||
| 558 | .start = MX31_INT_SSI2, | ||
| 559 | .end = MX31_INT_SSI2, | ||
| 560 | .flags = IORESOURCE_IRQ, | ||
| 561 | }, | ||
| 562 | }; | ||
| 563 | |||
| 564 | struct platform_device imx_ssi_device0 = { | ||
| 565 | .name = "imx-ssi", | ||
| 566 | .id = 0, | ||
| 567 | .num_resources = ARRAY_SIZE(imx_ssi_resources0), | ||
| 568 | .resource = imx_ssi_resources0, | ||
| 569 | }; | ||
| 570 | |||
| 571 | struct platform_device imx_ssi_device1 = { | ||
| 572 | .name = "imx-ssi", | ||
| 573 | .id = 1, | ||
| 574 | .num_resources = ARRAY_SIZE(imx_ssi_resources1), | ||
| 575 | .resource = imx_ssi_resources1, | ||
| 576 | }; | ||
| 577 | |||
| 540 | static int mx3_devices_init(void) | 578 | static int mx3_devices_init(void) |
| 541 | { | 579 | { |
| 542 | if (cpu_is_mx31()) { | 580 | if (cpu_is_mx31()) { |
| @@ -546,7 +584,7 @@ static int mx3_devices_init(void) | |||
| 546 | } | 584 | } |
| 547 | if (cpu_is_mx35()) { | 585 | if (cpu_is_mx35()) { |
| 548 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; | 586 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; |
| 549 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; | 587 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff; |
| 550 | otg_resources[0].start = MX35_OTG_BASE_ADDR; | 588 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
| 551 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | 589 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; |
| 552 | otg_resources[1].start = MXC_INT_USBOTG; | 590 | otg_resources[1].start = MXC_INT_USBOTG; |
| @@ -555,6 +593,10 @@ static int mx3_devices_init(void) | |||
| 555 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | 593 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; |
| 556 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | 594 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; |
| 557 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | 595 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; |
| 596 | imx_ssi_resources0[1].start = MX35_INT_SSI1; | ||
| 597 | imx_ssi_resources0[1].end = MX35_INT_SSI1; | ||
| 598 | imx_ssi_resources1[1].start = MX35_INT_SSI2; | ||
| 599 | imx_ssi_resources1[1].end = MX35_INT_SSI2; | ||
| 558 | } | 600 | } |
| 559 | 601 | ||
| 560 | return 0; | 602 | return 0; |
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index ab87419dc9a0..42cf175eac6b 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h | |||
| @@ -23,4 +23,6 @@ extern struct platform_device mxc_rnga_device; | |||
| 23 | extern struct platform_device mxc_spi_device0; | 23 | extern struct platform_device mxc_spi_device0; |
| 24 | extern struct platform_device mxc_spi_device1; | 24 | extern struct platform_device mxc_spi_device1; |
| 25 | extern struct platform_device mxc_spi_device2; | 25 | extern struct platform_device mxc_spi_device2; |
| 26 | extern struct platform_device imx_ssi_device0; | ||
| 27 | extern struct platform_device imx_ssi_device1; | ||
| 26 | 28 | ||
diff --git a/arch/arm/mach-mx3/kzmarm11.c b/arch/arm/mach-mx3/kzmarm11.c new file mode 100644 index 000000000000..6fa99ce3008a --- /dev/null +++ b/arch/arm/mach-mx3/kzmarm11.c | |||
| @@ -0,0 +1,268 @@ | |||
| 1 | /* | ||
| 2 | * KZM-ARM11-01 support | ||
| 3 | * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> | ||
| 4 | * | ||
| 5 | * based on code for MX31ADS, | ||
| 6 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 7 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | ||
| 8 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * GNU General Public License for more details. | ||
| 19 | * | ||
| 20 | * You should have received a copy of the GNU General Public License | ||
| 21 | * along with this program; if not, write to the Free Software | ||
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 23 | */ | ||
| 24 | |||
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/serial_8250.h> | ||
| 29 | #include <linux/smsc911x.h> | ||
| 30 | #include <linux/types.h> | ||
| 31 | |||
| 32 | #include <asm/irq.h> | ||
| 33 | #include <asm/mach-types.h> | ||
| 34 | #include <asm/setup.h> | ||
| 35 | #include <asm/mach/arch.h> | ||
| 36 | #include <asm/mach/irq.h> | ||
| 37 | #include <asm/mach/map.h> | ||
| 38 | #include <asm/mach/time.h> | ||
| 39 | |||
| 40 | #include <mach/board-kzmarm11.h> | ||
| 41 | #include <mach/clock.h> | ||
| 42 | #include <mach/common.h> | ||
| 43 | #include <mach/imx-uart.h> | ||
| 44 | #include <mach/iomux-mx3.h> | ||
| 45 | #include <mach/memory.h> | ||
| 46 | |||
| 47 | #include "devices.h" | ||
| 48 | |||
| 49 | #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) | ||
| 50 | /* | ||
| 51 | * KZM-ARM11-01 has an external UART on FPGA | ||
| 52 | */ | ||
| 53 | static struct plat_serial8250_port serial_platform_data[] = { | ||
| 54 | { | ||
| 55 | .membase = IO_ADDRESS(KZM_ARM11_16550), | ||
| 56 | .mapbase = KZM_ARM11_16550, | ||
| 57 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), | ||
| 58 | .irqflags = IRQ_TYPE_EDGE_RISING, | ||
| 59 | .uartclk = 14745600, | ||
| 60 | .regshift = 0, | ||
| 61 | .iotype = UPIO_MEM, | ||
| 62 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | | ||
| 63 | UPF_BUGGY_UART, | ||
| 64 | }, | ||
| 65 | {}, | ||
| 66 | }; | ||
| 67 | |||
| 68 | static struct resource serial8250_resources[] = { | ||
| 69 | { | ||
| 70 | .start = KZM_ARM11_16550, | ||
| 71 | .end = KZM_ARM11_16550 + 0x10, | ||
| 72 | .flags = IORESOURCE_MEM, | ||
| 73 | }, | ||
| 74 | { | ||
| 75 | .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), | ||
| 76 | .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), | ||
| 77 | .flags = IORESOURCE_IRQ, | ||
| 78 | }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static struct platform_device serial_device = { | ||
| 82 | .name = "serial8250", | ||
| 83 | .id = PLAT8250_DEV_PLATFORM, | ||
| 84 | .dev = { | ||
| 85 | .platform_data = serial_platform_data, | ||
| 86 | }, | ||
| 87 | .num_resources = ARRAY_SIZE(serial8250_resources), | ||
| 88 | .resource = serial8250_resources, | ||
| 89 | }; | ||
| 90 | |||
| 91 | static int __init kzm_init_ext_uart(void) | ||
| 92 | { | ||
| 93 | u8 tmp; | ||
| 94 | |||
| 95 | /* | ||
| 96 | * GPIO 1-1: external UART interrupt line | ||
| 97 | */ | ||
| 98 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO)); | ||
| 99 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int"); | ||
| 100 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)); | ||
| 101 | |||
| 102 | /* | ||
| 103 | * Unmask UART interrupt | ||
| 104 | */ | ||
| 105 | tmp = __raw_readb(IO_ADDRESS(KZM_ARM11_CTL1)); | ||
| 106 | tmp |= 0x2; | ||
| 107 | __raw_writeb(tmp, IO_ADDRESS(KZM_ARM11_CTL1)); | ||
| 108 | |||
| 109 | return platform_device_register(&serial_device); | ||
| 110 | } | ||
| 111 | #else | ||
| 112 | static inline int kzm_init_ext_uart(void) | ||
| 113 | { | ||
| 114 | return 0; | ||
| 115 | } | ||
| 116 | #endif | ||
| 117 | |||
| 118 | /* | ||
| 119 | * SMSC LAN9118 | ||
| 120 | */ | ||
| 121 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | ||
| 122 | static struct smsc911x_platform_config kzm_smsc9118_config = { | ||
| 123 | .phy_interface = PHY_INTERFACE_MODE_MII, | ||
| 124 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | ||
| 125 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
| 126 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct resource kzm_smsc9118_resources[] = { | ||
| 130 | { | ||
| 131 | .start = CS5_BASE_ADDR, | ||
| 132 | .end = CS5_BASE_ADDR + SZ_128K - 1, | ||
| 133 | .flags = IORESOURCE_MEM, | ||
| 134 | }, | ||
| 135 | { | ||
| 136 | .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), | ||
| 137 | .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2), | ||
| 138 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct platform_device kzm_smsc9118_device = { | ||
| 143 | .name = "smsc911x", | ||
| 144 | .id = -1, | ||
| 145 | .num_resources = ARRAY_SIZE(kzm_smsc9118_resources), | ||
| 146 | .resource = kzm_smsc9118_resources, | ||
| 147 | .dev = { | ||
| 148 | .platform_data = &kzm_smsc9118_config, | ||
| 149 | }, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static int __init kzm_init_smsc9118(void) | ||
| 153 | { | ||
| 154 | /* | ||
| 155 | * GPIO 1-2: SMSC9118 interrupt line | ||
| 156 | */ | ||
| 157 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO)); | ||
| 158 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int"); | ||
| 159 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2)); | ||
| 160 | |||
| 161 | return platform_device_register(&kzm_smsc9118_device); | ||
| 162 | } | ||
| 163 | #else | ||
| 164 | static inline int kzm_init_smsc9118(void) | ||
| 165 | { | ||
| 166 | return 0; | ||
| 167 | } | ||
| 168 | #endif | ||
| 169 | |||
| 170 | #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) | ||
| 171 | static struct imxuart_platform_data uart_pdata = { | ||
| 172 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static void __init kzm_init_imx_uart(void) | ||
| 176 | { | ||
| 177 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 178 | |||
| 179 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | ||
| 180 | } | ||
| 181 | #else | ||
| 182 | static inline void kzm_init_imx_uart(void) | ||
| 183 | { | ||
| 184 | } | ||
| 185 | #endif | ||
| 186 | |||
| 187 | static int kzm_pins[] __initdata = { | ||
| 188 | MX31_PIN_CTS1__CTS1, | ||
| 189 | MX31_PIN_RTS1__RTS1, | ||
| 190 | MX31_PIN_TXD1__TXD1, | ||
| 191 | MX31_PIN_RXD1__RXD1, | ||
| 192 | MX31_PIN_DCD_DCE1__DCD_DCE1, | ||
| 193 | MX31_PIN_RI_DCE1__RI_DCE1, | ||
| 194 | MX31_PIN_DSR_DCE1__DSR_DCE1, | ||
| 195 | MX31_PIN_DTR_DCE1__DTR_DCE1, | ||
| 196 | MX31_PIN_CTS2__CTS2, | ||
| 197 | MX31_PIN_RTS2__RTS2, | ||
| 198 | MX31_PIN_TXD2__TXD2, | ||
| 199 | MX31_PIN_RXD2__RXD2, | ||
| 200 | MX31_PIN_DCD_DTE1__DCD_DTE2, | ||
| 201 | MX31_PIN_RI_DTE1__RI_DTE2, | ||
| 202 | MX31_PIN_DSR_DTE1__DSR_DTE2, | ||
| 203 | MX31_PIN_DTR_DTE1__DTR_DTE2, | ||
| 204 | }; | ||
| 205 | |||
| 206 | /* | ||
| 207 | * Board specific initialization. | ||
| 208 | */ | ||
| 209 | static void __init kzm_board_init(void) | ||
| 210 | { | ||
| 211 | mxc_iomux_setup_multiple_pins(kzm_pins, | ||
| 212 | ARRAY_SIZE(kzm_pins), "kzm"); | ||
| 213 | kzm_init_ext_uart(); | ||
| 214 | kzm_init_smsc9118(); | ||
| 215 | kzm_init_imx_uart(); | ||
| 216 | |||
| 217 | pr_info("Clock input source is 26MHz\n"); | ||
| 218 | } | ||
| 219 | |||
| 220 | /* | ||
| 221 | * This structure defines static mappings for the kzm-arm11-01 board. | ||
| 222 | */ | ||
| 223 | static struct map_desc kzm_io_desc[] __initdata = { | ||
| 224 | { | ||
| 225 | .virtual = CS4_BASE_ADDR_VIRT, | ||
| 226 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | ||
| 227 | .length = CS4_SIZE, | ||
| 228 | .type = MT_DEVICE | ||
| 229 | }, | ||
| 230 | { | ||
| 231 | .virtual = CS5_BASE_ADDR_VIRT, | ||
| 232 | .pfn = __phys_to_pfn(CS5_BASE_ADDR), | ||
| 233 | .length = CS5_SIZE, | ||
| 234 | .type = MT_DEVICE | ||
| 235 | }, | ||
| 236 | }; | ||
| 237 | |||
| 238 | /* | ||
| 239 | * Set up static virtual mappings. | ||
| 240 | */ | ||
| 241 | static void __init kzm_map_io(void) | ||
| 242 | { | ||
| 243 | mx31_map_io(); | ||
| 244 | iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc)); | ||
| 245 | } | ||
| 246 | |||
| 247 | static void __init kzm_timer_init(void) | ||
| 248 | { | ||
| 249 | mx31_clocks_init(26000000); | ||
| 250 | } | ||
| 251 | |||
| 252 | static struct sys_timer kzm_timer = { | ||
| 253 | .init = kzm_timer_init, | ||
| 254 | }; | ||
| 255 | |||
| 256 | /* | ||
| 257 | * The following uses standard kernel macros define in arch.h in order to | ||
| 258 | * initialize __mach_desc_KZM_ARM11_01 data structure. | ||
| 259 | */ | ||
| 260 | MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") | ||
| 261 | .phys_io = AIPS1_BASE_ADDR, | ||
| 262 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | ||
| 263 | .boot_params = PHYS_OFFSET + 0x100, | ||
| 264 | .map_io = kzm_map_io, | ||
| 265 | .init_irq = mx31_init_irq, | ||
| 266 | .init_machine = kzm_board_init, | ||
| 267 | .timer = &kzm_timer, | ||
| 268 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c index 3b3a78f49c23..7aebd74a12e8 100644 --- a/arch/arm/mach-mx3/mx31lilly-db.c +++ b/arch/arm/mach-mx3/mx31lilly-db.c | |||
| @@ -109,6 +109,9 @@ static int mxc_mmc1_get_ro(struct device *dev) | |||
| 109 | 109 | ||
| 110 | static int gpio_det, gpio_wp; | 110 | static int gpio_det, gpio_wp; |
| 111 | 111 | ||
| 112 | #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 113 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 114 | |||
| 112 | static int mxc_mmc1_init(struct device *dev, | 115 | static int mxc_mmc1_init(struct device *dev, |
| 113 | irq_handler_t detect_irq, void *data) | 116 | irq_handler_t detect_irq, void *data) |
| 114 | { | 117 | { |
| @@ -117,6 +120,13 @@ static int mxc_mmc1_init(struct device *dev, | |||
| 117 | gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); | 120 | gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1); |
| 118 | gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); | 121 | gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0); |
| 119 | 122 | ||
| 123 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); | ||
| 124 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); | ||
| 125 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); | ||
| 126 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); | ||
| 127 | mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); | ||
| 128 | mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); | ||
| 129 | |||
| 120 | ret = gpio_request(gpio_det, "MMC detect"); | 130 | ret = gpio_request(gpio_det, "MMC detect"); |
| 121 | if (ret) | 131 | if (ret) |
| 122 | return ret; | 132 | return ret; |
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c index 423025150f6f..9ce029f554b9 100644 --- a/arch/arm/mach-mx3/mx31lilly.c +++ b/arch/arm/mach-mx3/mx31lilly.c | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | #include <linux/interrupt.h> | 31 | #include <linux/interrupt.h> |
| 32 | #include <linux/smsc911x.h> | 32 | #include <linux/smsc911x.h> |
| 33 | #include <linux/mtd/physmap.h> | 33 | #include <linux/mtd/physmap.h> |
| 34 | #include <linux/spi/spi.h> | ||
| 35 | #include <linux/mfd/mc13783.h> | ||
| 34 | 36 | ||
| 35 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
| 36 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
| @@ -41,6 +43,7 @@ | |||
| 41 | #include <mach/common.h> | 43 | #include <mach/common.h> |
| 42 | #include <mach/iomux-mx3.h> | 44 | #include <mach/iomux-mx3.h> |
| 43 | #include <mach/board-mx31lilly.h> | 45 | #include <mach/board-mx31lilly.h> |
| 46 | #include <mach/spi.h> | ||
| 44 | 47 | ||
| 45 | #include "devices.h" | 48 | #include "devices.h" |
| 46 | 49 | ||
| @@ -108,7 +111,36 @@ static struct platform_device physmap_flash_device = { | |||
| 108 | static struct platform_device *devices[] __initdata = { | 111 | static struct platform_device *devices[] __initdata = { |
| 109 | &smsc91x_device, | 112 | &smsc91x_device, |
| 110 | &physmap_flash_device, | 113 | &physmap_flash_device, |
| 111 | &mxc_i2c_device1, | 114 | }; |
| 115 | |||
| 116 | /* SPI */ | ||
| 117 | |||
| 118 | static int spi_internal_chipselect[] = { | ||
| 119 | MXC_SPI_CS(0), | ||
| 120 | MXC_SPI_CS(1), | ||
| 121 | MXC_SPI_CS(2), | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct spi_imx_master spi0_pdata = { | ||
| 125 | .chipselect = spi_internal_chipselect, | ||
| 126 | .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), | ||
| 127 | }; | ||
| 128 | |||
| 129 | static struct spi_imx_master spi1_pdata = { | ||
| 130 | .chipselect = spi_internal_chipselect, | ||
| 131 | .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), | ||
| 132 | }; | ||
| 133 | |||
| 134 | static struct mc13783_platform_data mc13783_pdata __initdata = { | ||
| 135 | .flags = MC13783_USE_RTC | MC13783_USE_TOUCHSCREEN, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct spi_board_info mc13783_dev __initdata = { | ||
| 139 | .modalias = "mc13783", | ||
| 140 | .max_speed_hz = 1000000, | ||
| 141 | .bus_num = 1, | ||
| 142 | .chip_select = 0, | ||
| 143 | .platform_data = &mc13783_pdata, | ||
| 112 | }; | 144 | }; |
| 113 | 145 | ||
| 114 | static int mx31lilly_baseboard; | 146 | static int mx31lilly_baseboard; |
| @@ -128,8 +160,27 @@ static void __init mx31lilly_board_init(void) | |||
| 128 | } | 160 | } |
| 129 | 161 | ||
| 130 | mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); | 162 | mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); |
| 131 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__SCL, "I2C SCL"); | 163 | |
| 132 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__SDA, "I2C SDA"); | 164 | /* SPI */ |
| 165 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK"); | ||
| 166 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX"); | ||
| 167 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX"); | ||
| 168 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY"); | ||
| 169 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0"); | ||
| 170 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1"); | ||
| 171 | mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2"); | ||
| 172 | |||
| 173 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK"); | ||
| 174 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX"); | ||
| 175 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX"); | ||
| 176 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY"); | ||
| 177 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0"); | ||
| 178 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1"); | ||
| 179 | mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2"); | ||
| 180 | |||
| 181 | mxc_register_device(&mxc_spi_device0, &spi0_pdata); | ||
| 182 | mxc_register_device(&mxc_spi_device1, &spi1_pdata); | ||
| 183 | spi_register_board_info(&mc13783_dev, 1); | ||
| 133 | 184 | ||
| 134 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 185 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 135 | } | 186 | } |
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c new file mode 100644 index 000000000000..694611d6b057 --- /dev/null +++ b/arch/arm/mach-mx3/mx31lite-db.c | |||
| @@ -0,0 +1,198 @@ | |||
| 1 | /* | ||
| 2 | * LogicPD i.MX31 SOM-LV development board support | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 5 | * | ||
| 6 | * based on code for other MX31 boards, | ||
| 7 | * | ||
| 8 | * Copyright 2005-2007 Freescale Semiconductor | ||
| 9 | * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com> | ||
| 10 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation; either version 2 of the License, or | ||
| 15 | * (at your option) any later version. | ||
| 16 | * | ||
| 17 | * This program is distributed in the hope that it will be useful, | ||
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 20 | * GNU General Public License for more details. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License | ||
| 23 | * along with this program; if not, write to the Free Software | ||
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 25 | */ | ||
| 26 | |||
| 27 | #include <linux/kernel.h> | ||
| 28 | #include <linux/types.h> | ||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/gpio.h> | ||
| 31 | #include <linux/platform_device.h> | ||
| 32 | #include <linux/leds.h> | ||
| 33 | #include <linux/platform_device.h> | ||
| 34 | |||
| 35 | #include <asm/mach-types.h> | ||
| 36 | #include <asm/mach/arch.h> | ||
| 37 | #include <asm/mach/map.h> | ||
| 38 | |||
| 39 | #include <mach/hardware.h> | ||
| 40 | #include <mach/common.h> | ||
| 41 | #include <mach/imx-uart.h> | ||
| 42 | #include <mach/iomux-mx3.h> | ||
| 43 | #include <mach/board-mx31lite.h> | ||
| 44 | #include <mach/mmc.h> | ||
| 45 | #include <mach/spi.h> | ||
| 46 | |||
| 47 | #include "devices.h" | ||
| 48 | |||
| 49 | /* | ||
| 50 | * This file contains board-specific initialization routines for the | ||
| 51 | * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'. | ||
| 52 | * If you design an own baseboard for the module, use this file as base | ||
| 53 | * for support code. | ||
| 54 | */ | ||
| 55 | |||
| 56 | static unsigned int litekit_db_board_pins[] __initdata = { | ||
| 57 | /* UART1 */ | ||
| 58 | MX31_PIN_CTS1__CTS1, | ||
| 59 | MX31_PIN_RTS1__RTS1, | ||
| 60 | MX31_PIN_TXD1__TXD1, | ||
| 61 | MX31_PIN_RXD1__RXD1, | ||
| 62 | /* SPI 0 */ | ||
| 63 | MX31_PIN_CSPI1_SCLK__SCLK, | ||
| 64 | MX31_PIN_CSPI1_MOSI__MOSI, | ||
| 65 | MX31_PIN_CSPI1_MISO__MISO, | ||
| 66 | MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, | ||
| 67 | MX31_PIN_CSPI1_SS0__SS0, | ||
| 68 | MX31_PIN_CSPI1_SS1__SS1, | ||
| 69 | MX31_PIN_CSPI1_SS2__SS2, | ||
| 70 | }; | ||
| 71 | |||
| 72 | /* UART */ | ||
| 73 | static struct imxuart_platform_data uart_pdata __initdata = { | ||
| 74 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* MMC */ | ||
| 78 | |||
| 79 | static int gpio_det, gpio_wp; | ||
| 80 | |||
| 81 | #define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 82 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 83 | |||
| 84 | static int mxc_mmc1_get_ro(struct device *dev) | ||
| 85 | { | ||
| 86 | return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0)); | ||
| 87 | } | ||
| 88 | |||
| 89 | static int mxc_mmc1_init(struct device *dev, | ||
| 90 | irq_handler_t detect_irq, void *data) | ||
| 91 | { | ||
| 92 | int ret; | ||
| 93 | |||
| 94 | gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1); | ||
| 95 | gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6); | ||
| 96 | |||
| 97 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG); | ||
| 98 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG); | ||
| 99 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG); | ||
| 100 | mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG); | ||
| 101 | mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG); | ||
| 102 | mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG); | ||
| 103 | |||
| 104 | ret = gpio_request(gpio_det, "MMC detect"); | ||
| 105 | if (ret) | ||
| 106 | return ret; | ||
| 107 | |||
| 108 | ret = gpio_request(gpio_wp, "MMC w/p"); | ||
| 109 | if (ret) | ||
| 110 | goto exit_free_det; | ||
| 111 | |||
| 112 | gpio_direction_input(gpio_det); | ||
| 113 | gpio_direction_input(gpio_wp); | ||
| 114 | |||
| 115 | ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq, | ||
| 116 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | ||
| 117 | "MMC detect", data); | ||
| 118 | if (ret) | ||
| 119 | goto exit_free_wp; | ||
| 120 | |||
| 121 | return 0; | ||
| 122 | |||
| 123 | exit_free_wp: | ||
| 124 | gpio_free(gpio_wp); | ||
| 125 | |||
| 126 | exit_free_det: | ||
| 127 | gpio_free(gpio_det); | ||
| 128 | |||
| 129 | return ret; | ||
| 130 | } | ||
| 131 | |||
| 132 | static void mxc_mmc1_exit(struct device *dev, void *data) | ||
| 133 | { | ||
| 134 | gpio_free(gpio_det); | ||
| 135 | gpio_free(gpio_wp); | ||
| 136 | free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); | ||
| 137 | } | ||
| 138 | |||
| 139 | static struct imxmmc_platform_data mmc_pdata = { | ||
| 140 | .get_ro = mxc_mmc1_get_ro, | ||
| 141 | .init = mxc_mmc1_init, | ||
| 142 | .exit = mxc_mmc1_exit, | ||
| 143 | }; | ||
| 144 | |||
| 145 | /* SPI */ | ||
| 146 | |||
| 147 | static int spi_internal_chipselect[] = { | ||
| 148 | MXC_SPI_CS(0), | ||
| 149 | MXC_SPI_CS(1), | ||
| 150 | MXC_SPI_CS(2), | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct spi_imx_master spi0_pdata = { | ||
| 154 | .chipselect = spi_internal_chipselect, | ||
| 155 | .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), | ||
| 156 | }; | ||
| 157 | |||
| 158 | /* GPIO LEDs */ | ||
| 159 | |||
| 160 | static struct gpio_led litekit_leds[] = { | ||
| 161 | { | ||
| 162 | .name = "GPIO0", | ||
| 163 | .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE), | ||
| 164 | .active_low = 1, | ||
| 165 | .default_state = LEDS_GPIO_DEFSTATE_OFF, | ||
| 166 | }, | ||
| 167 | { | ||
| 168 | .name = "GPIO1", | ||
| 169 | .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE), | ||
| 170 | .active_low = 1, | ||
| 171 | .default_state = LEDS_GPIO_DEFSTATE_OFF, | ||
| 172 | } | ||
| 173 | }; | ||
| 174 | |||
| 175 | static struct gpio_led_platform_data litekit_led_platform_data = { | ||
| 176 | .leds = litekit_leds, | ||
| 177 | .num_leds = ARRAY_SIZE(litekit_leds), | ||
| 178 | }; | ||
| 179 | |||
| 180 | static struct platform_device litekit_led_device = { | ||
| 181 | .name = "leds-gpio", | ||
| 182 | .id = -1, | ||
| 183 | .dev = { | ||
| 184 | .platform_data = &litekit_led_platform_data, | ||
| 185 | }, | ||
| 186 | }; | ||
| 187 | |||
| 188 | void __init mx31lite_db_init(void) | ||
| 189 | { | ||
| 190 | mxc_iomux_setup_multiple_pins(litekit_db_board_pins, | ||
| 191 | ARRAY_SIZE(litekit_db_board_pins), | ||
| 192 | "development board pins"); | ||
| 193 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 194 | mxc_register_device(&mxcsdhc_device0, &mmc_pdata); | ||
| 195 | mxc_register_device(&mxc_spi_device0, &spi0_pdata); | ||
| 196 | platform_device_register(&litekit_led_device); | ||
| 197 | } | ||
| 198 | |||
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index a8d57decdfdb..def6b6736594 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c | |||
| @@ -2,6 +2,7 @@ | |||
| 2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | 2 | * Copyright (C) 2000 Deep Blue Solutions Ltd |
| 3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | 3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 4 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 4 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 5 | * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 5 | * | 6 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by | 8 | * it under the terms of the GNU General Public License as published by |
| @@ -25,38 +26,47 @@ | |||
| 25 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 26 | #include <linux/gpio.h> | 27 | #include <linux/gpio.h> |
| 27 | #include <linux/smsc911x.h> | 28 | #include <linux/smsc911x.h> |
| 29 | #include <linux/mfd/mc13783.h> | ||
| 30 | #include <linux/spi/spi.h> | ||
| 31 | #include <linux/usb/otg.h> | ||
| 32 | #include <linux/usb/ulpi.h> | ||
| 33 | #include <linux/mtd/physmap.h> | ||
| 28 | 34 | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
| 32 | #include <asm/mach/time.h> | 37 | #include <asm/mach/time.h> |
| 33 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 34 | #include <mach/common.h> | ||
| 35 | #include <asm/page.h> | 39 | #include <asm/page.h> |
| 36 | #include <asm/setup.h> | 40 | #include <asm/setup.h> |
| 41 | |||
| 42 | #include <mach/hardware.h> | ||
| 43 | #include <mach/common.h> | ||
| 37 | #include <mach/board-mx31lite.h> | 44 | #include <mach/board-mx31lite.h> |
| 38 | #include <mach/imx-uart.h> | 45 | #include <mach/imx-uart.h> |
| 39 | #include <mach/iomux-mx3.h> | 46 | #include <mach/iomux-mx3.h> |
| 40 | #include <mach/irqs.h> | 47 | #include <mach/irqs.h> |
| 41 | #include <mach/mxc_nand.h> | 48 | #include <mach/mxc_nand.h> |
| 49 | #include <mach/spi.h> | ||
| 50 | #include <mach/mxc_ehci.h> | ||
| 51 | #include <mach/ulpi.h> | ||
| 52 | |||
| 42 | #include "devices.h" | 53 | #include "devices.h" |
| 43 | 54 | ||
| 44 | /* | 55 | /* |
| 45 | * This file contains the board-specific initialization routines. | 56 | * This file contains the module-specific initialization routines. |
| 46 | */ | 57 | */ |
| 47 | 58 | ||
| 48 | static unsigned int mx31lite_pins[] = { | 59 | static unsigned int mx31lite_pins[] = { |
| 49 | /* UART1 */ | ||
| 50 | MX31_PIN_CTS1__CTS1, | ||
| 51 | MX31_PIN_RTS1__RTS1, | ||
| 52 | MX31_PIN_TXD1__TXD1, | ||
| 53 | MX31_PIN_RXD1__RXD1, | ||
| 54 | /* LAN9117 IRQ pin */ | 60 | /* LAN9117 IRQ pin */ |
| 55 | IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), | 61 | IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), |
| 56 | }; | 62 | /* SPI 1 */ |
| 57 | 63 | MX31_PIN_CSPI2_SCLK__SCLK, | |
| 58 | static struct imxuart_platform_data uart_pdata = { | 64 | MX31_PIN_CSPI2_MOSI__MOSI, |
| 59 | .flags = IMXUART_HAVE_RTSCTS, | 65 | MX31_PIN_CSPI2_MISO__MISO, |
| 66 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | ||
| 67 | MX31_PIN_CSPI2_SS0__SS0, | ||
| 68 | MX31_PIN_CSPI2_SS1__SS1, | ||
| 69 | MX31_PIN_CSPI2_SS2__SS2, | ||
| 60 | }; | 70 | }; |
| 61 | 71 | ||
| 62 | static struct mxc_nand_platform_data mx31lite_nand_board_info = { | 72 | static struct mxc_nand_platform_data mx31lite_nand_board_info = { |
| @@ -93,6 +103,111 @@ static struct platform_device smsc911x_device = { | |||
| 93 | }; | 103 | }; |
| 94 | 104 | ||
| 95 | /* | 105 | /* |
| 106 | * SPI | ||
| 107 | * | ||
| 108 | * The MC13783 is the only hard-wired SPI device on the module. | ||
| 109 | */ | ||
| 110 | |||
| 111 | static int spi_internal_chipselect[] = { | ||
| 112 | MXC_SPI_CS(0), | ||
| 113 | }; | ||
| 114 | |||
| 115 | static struct spi_imx_master spi1_pdata = { | ||
| 116 | .chipselect = spi_internal_chipselect, | ||
| 117 | .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), | ||
| 118 | }; | ||
| 119 | |||
| 120 | static struct mc13783_platform_data mc13783_pdata __initdata = { | ||
| 121 | .flags = MC13783_USE_RTC | | ||
| 122 | MC13783_USE_REGULATOR, | ||
| 123 | }; | ||
| 124 | |||
| 125 | static struct spi_board_info mc13783_spi_dev __initdata = { | ||
| 126 | .modalias = "mc13783", | ||
| 127 | .max_speed_hz = 1000000, | ||
| 128 | .bus_num = 1, | ||
| 129 | .chip_select = 0, | ||
| 130 | .platform_data = &mc13783_pdata, | ||
| 131 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | ||
| 132 | }; | ||
| 133 | |||
| 134 | /* | ||
| 135 | * USB | ||
| 136 | */ | ||
| 137 | |||
| 138 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 139 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 140 | |||
| 141 | static int usbh2_init(struct platform_device *pdev) | ||
| 142 | { | ||
| 143 | int pins[] = { | ||
| 144 | MX31_PIN_USBH2_DATA0__USBH2_DATA0, | ||
| 145 | MX31_PIN_USBH2_DATA1__USBH2_DATA1, | ||
| 146 | MX31_PIN_USBH2_CLK__USBH2_CLK, | ||
| 147 | MX31_PIN_USBH2_DIR__USBH2_DIR, | ||
| 148 | MX31_PIN_USBH2_NXT__USBH2_NXT, | ||
| 149 | MX31_PIN_USBH2_STP__USBH2_STP, | ||
| 150 | }; | ||
| 151 | |||
| 152 | mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); | ||
| 153 | |||
| 154 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | ||
| 155 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | ||
| 156 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | ||
| 157 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | ||
| 158 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | ||
| 159 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | ||
| 160 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); | ||
| 161 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); | ||
| 162 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); | ||
| 163 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); | ||
| 164 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); | ||
| 165 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); | ||
| 166 | |||
| 167 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); | ||
| 168 | |||
| 169 | /* chip select */ | ||
| 170 | mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), | ||
| 171 | "USBH2_CS"); | ||
| 172 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); | ||
| 173 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); | ||
| 174 | |||
| 175 | return 0; | ||
| 176 | } | ||
| 177 | |||
| 178 | static struct mxc_usbh_platform_data usbh2_pdata = { | ||
| 179 | .init = usbh2_init, | ||
| 180 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | ||
| 181 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 182 | }; | ||
| 183 | |||
| 184 | /* | ||
| 185 | * NOR flash | ||
| 186 | */ | ||
| 187 | |||
| 188 | static struct physmap_flash_data nor_flash_data = { | ||
| 189 | .width = 2, | ||
| 190 | }; | ||
| 191 | |||
| 192 | static struct resource nor_flash_resource = { | ||
| 193 | .start = 0xa0000000, | ||
| 194 | .end = 0xa1ffffff, | ||
| 195 | .flags = IORESOURCE_MEM, | ||
| 196 | }; | ||
| 197 | |||
| 198 | static struct platform_device physmap_flash_device = { | ||
| 199 | .name = "physmap-flash", | ||
| 200 | .id = 0, | ||
| 201 | .dev = { | ||
| 202 | .platform_data = &nor_flash_data, | ||
| 203 | }, | ||
| 204 | .resource = &nor_flash_resource, | ||
| 205 | .num_resources = 1, | ||
| 206 | }; | ||
| 207 | |||
| 208 | |||
| 209 | |||
| 210 | /* | ||
| 96 | * This structure defines the MX31 memory map. | 211 | * This structure defines the MX31 memory map. |
| 97 | */ | 212 | */ |
| 98 | static struct map_desc mx31lite_io_desc[] __initdata = { | 213 | static struct map_desc mx31lite_io_desc[] __initdata = { |
| @@ -118,19 +233,40 @@ void __init mx31lite_map_io(void) | |||
| 118 | iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); | 233 | iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); |
| 119 | } | 234 | } |
| 120 | 235 | ||
| 121 | /* | 236 | static int mx31lite_baseboard; |
| 122 | * Board specific initialization. | 237 | core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); |
| 123 | */ | 238 | |
| 124 | static void __init mxc_board_init(void) | 239 | static void __init mxc_board_init(void) |
| 125 | { | 240 | { |
| 126 | int ret; | 241 | int ret; |
| 127 | 242 | ||
| 243 | switch (mx31lite_baseboard) { | ||
| 244 | case MX31LITE_NOBOARD: | ||
| 245 | break; | ||
| 246 | case MX31LITE_DB: | ||
| 247 | mx31lite_db_init(); | ||
| 248 | break; | ||
| 249 | default: | ||
| 250 | printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n", | ||
| 251 | mx31lite_baseboard); | ||
| 252 | } | ||
| 253 | |||
| 128 | mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), | 254 | mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), |
| 129 | "mx31lite"); | 255 | "mx31lite"); |
| 130 | 256 | ||
| 131 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 257 | /* NOR and NAND flash */ |
| 258 | platform_device_register(&physmap_flash_device); | ||
| 132 | mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); | 259 | mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); |
| 133 | 260 | ||
| 261 | mxc_register_device(&mxc_spi_device1, &spi1_pdata); | ||
| 262 | spi_register_board_info(&mc13783_spi_dev, 1); | ||
| 263 | |||
| 264 | /* USB */ | ||
| 265 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 266 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | ||
| 267 | |||
| 268 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | ||
| 269 | |||
| 134 | /* SMSC9117 IRQ pin */ | 270 | /* SMSC9117 IRQ pin */ |
| 135 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); | 271 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); |
| 136 | if (ret) | 272 | if (ret) |
| @@ -150,12 +286,7 @@ struct sys_timer mx31lite_timer = { | |||
| 150 | .init = mx31lite_timer_init, | 286 | .init = mx31lite_timer_init, |
| 151 | }; | 287 | }; |
| 152 | 288 | ||
| 153 | /* | 289 | MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") |
| 154 | * The following uses standard kernel macros defined in arch.h in order to | ||
| 155 | * initialize __mach_desc_MX31LITE data structure. | ||
| 156 | */ | ||
| 157 | |||
| 158 | MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT") | ||
| 159 | /* Maintainer: Freescale Semiconductor, Inc. */ | 290 | /* Maintainer: Freescale Semiconductor, Inc. */ |
| 160 | .phys_io = AIPS1_BASE_ADDR, | 291 | .phys_io = AIPS1_BASE_ADDR, |
| 161 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 292 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 5592cdb8d0ad..8fc624f141cb 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c | |||
| @@ -22,11 +22,15 @@ | |||
| 22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/types.h> | 23 | #include <linux/types.h> |
| 24 | 24 | ||
| 25 | #include <linux/usb/otg.h> | ||
| 26 | |||
| 25 | #include <mach/common.h> | 27 | #include <mach/common.h> |
| 26 | #include <mach/imx-uart.h> | 28 | #include <mach/imx-uart.h> |
| 27 | #include <mach/iomux-mx3.h> | 29 | #include <mach/iomux-mx3.h> |
| 28 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 29 | #include <mach/mmc.h> | 31 | #include <mach/mmc.h> |
| 32 | #include <mach/mxc_ehci.h> | ||
| 33 | #include <mach/ulpi.h> | ||
| 30 | 34 | ||
| 31 | #include "devices.h" | 35 | #include "devices.h" |
| 32 | 36 | ||
| @@ -39,6 +43,12 @@ static unsigned int devboard_pins[] = { | |||
| 39 | MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, | 43 | MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0, |
| 40 | MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, | 44 | MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, |
| 41 | MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, | 45 | MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, |
| 46 | /* USB H1 */ | ||
| 47 | MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, | ||
| 48 | MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, | ||
| 49 | MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, | ||
| 50 | MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, | ||
| 51 | MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, | ||
| 42 | }; | 52 | }; |
| 43 | 53 | ||
| 44 | static struct imxuart_platform_data uart_pdata = { | 54 | static struct imxuart_platform_data uart_pdata = { |
| @@ -98,6 +108,80 @@ static struct imxmmc_platform_data sdhc2_pdata = { | |||
| 98 | .exit = devboard_sdhc2_exit, | 108 | .exit = devboard_sdhc2_exit, |
| 99 | }; | 109 | }; |
| 100 | 110 | ||
| 111 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 112 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 113 | |||
| 114 | static int devboard_usbh1_hw_init(struct platform_device *pdev) | ||
| 115 | { | ||
| 116 | mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); | ||
| 117 | |||
| 118 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); | ||
| 119 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); | ||
| 120 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); | ||
| 121 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); | ||
| 122 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); | ||
| 123 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); | ||
| 124 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); | ||
| 125 | mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); | ||
| 126 | |||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | #define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) | ||
| 131 | #define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) | ||
| 132 | |||
| 133 | static int devboard_isp1105_init(struct otg_transceiver *otg) | ||
| 134 | { | ||
| 135 | int ret = gpio_request(USBH1_MODE, "usbh1-mode"); | ||
| 136 | if (ret) | ||
| 137 | return ret; | ||
| 138 | /* single ended */ | ||
| 139 | gpio_direction_output(USBH1_MODE, 0); | ||
| 140 | |||
| 141 | ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); | ||
| 142 | if (ret) { | ||
| 143 | gpio_free(USBH1_MODE); | ||
| 144 | return ret; | ||
| 145 | } | ||
| 146 | gpio_direction_output(USBH1_VBUSEN_B, 1); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | |||
| 152 | static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on) | ||
| 153 | { | ||
| 154 | if (on) | ||
| 155 | gpio_set_value(USBH1_VBUSEN_B, 0); | ||
| 156 | else | ||
| 157 | gpio_set_value(USBH1_VBUSEN_B, 1); | ||
| 158 | |||
| 159 | return 0; | ||
| 160 | } | ||
| 161 | |||
| 162 | static struct mxc_usbh_platform_data usbh1_pdata = { | ||
| 163 | .init = devboard_usbh1_hw_init, | ||
| 164 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | ||
| 165 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static int __init devboard_usbh1_init(void) | ||
| 169 | { | ||
| 170 | struct otg_transceiver *otg; | ||
| 171 | |||
| 172 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); | ||
| 173 | if (!otg) | ||
| 174 | return -ENOMEM; | ||
| 175 | |||
| 176 | otg->label = "ISP1105"; | ||
| 177 | otg->init = devboard_isp1105_init; | ||
| 178 | otg->set_vbus = devboard_isp1105_set_vbus; | ||
| 179 | |||
| 180 | usbh1_pdata.otg = otg; | ||
| 181 | |||
| 182 | return mxc_register_device(&mx31_usbh1, &usbh1_pdata); | ||
| 183 | } | ||
| 184 | |||
| 101 | /* | 185 | /* |
| 102 | * system init for baseboard usage. Will be called by mx31moboard init. | 186 | * system init for baseboard usage. Will be called by mx31moboard init. |
| 103 | */ | 187 | */ |
| @@ -111,4 +195,6 @@ void __init mx31moboard_devboard_init(void) | |||
| 111 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | 195 | mxc_register_device(&mxc_uart_device1, &uart_pdata); |
| 112 | 196 | ||
| 113 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); | 197 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); |
| 198 | |||
| 199 | devboard_usbh1_init(); | ||
| 114 | } | 200 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index 2bfaffb344f0..85184a35e674 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c | |||
| @@ -16,17 +16,26 @@ | |||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/delay.h> | ||
| 19 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 21 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/i2c.h> | ||
| 24 | #include <linux/spi/spi.h> | ||
| 22 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
| 23 | #include <linux/types.h> | 26 | #include <linux/types.h> |
| 24 | 27 | ||
| 28 | #include <linux/usb/otg.h> | ||
| 29 | |||
| 25 | #include <mach/common.h> | 30 | #include <mach/common.h> |
| 26 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 27 | #include <mach/imx-uart.h> | 32 | #include <mach/imx-uart.h> |
| 28 | #include <mach/iomux-mx3.h> | 33 | #include <mach/iomux-mx3.h> |
| 29 | #include <mach/mmc.h> | 34 | #include <mach/mmc.h> |
| 35 | #include <mach/mxc_ehci.h> | ||
| 36 | #include <mach/ulpi.h> | ||
| 37 | |||
| 38 | #include <media/soc_camera.h> | ||
| 30 | 39 | ||
| 31 | #include "devices.h" | 40 | #include "devices.h" |
| 32 | 41 | ||
| @@ -37,7 +46,6 @@ static unsigned int marxbot_pins[] = { | |||
| 37 | MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, | 46 | MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD, |
| 38 | MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, | 47 | MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29, |
| 39 | /* CSI */ | 48 | /* CSI */ |
| 40 | MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5, | ||
| 41 | MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, | 49 | MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7, |
| 42 | MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, | 50 | MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9, |
| 43 | MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, | 51 | MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11, |
| @@ -45,10 +53,19 @@ static unsigned int marxbot_pins[] = { | |||
| 45 | MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, | 53 | MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15, |
| 46 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, | 54 | MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK, |
| 47 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, | 55 | MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC, |
| 56 | MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5, | ||
| 48 | MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, | 57 | MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1, |
| 49 | MX31_PIN_TXD2__GPIO1_28, | 58 | MX31_PIN_TXD2__GPIO1_28, |
| 50 | /* dsPIC resets */ | 59 | /* dsPIC resets */ |
| 51 | MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, | 60 | MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22, |
| 61 | /*battery detection */ | ||
| 62 | MX31_PIN_LCS0__GPIO3_23, | ||
| 63 | /* USB H1 */ | ||
| 64 | MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM, | ||
| 65 | MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP, | ||
| 66 | MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB, | ||
| 67 | MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND, | ||
| 68 | MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12, | ||
| 52 | }; | 69 | }; |
| 53 | 70 | ||
| 54 | #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) | 71 | #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR) |
| @@ -120,6 +137,166 @@ static void dspics_resets_init(void) | |||
| 120 | } | 137 | } |
| 121 | } | 138 | } |
| 122 | 139 | ||
| 140 | static struct spi_board_info marxbot_spi_board_info[] __initdata = { | ||
| 141 | { | ||
| 142 | .modalias = "spidev", | ||
| 143 | .max_speed_hz = 300000, | ||
| 144 | .bus_num = 1, | ||
| 145 | .chip_select = 1, /* according spi1_cs[] ! */ | ||
| 146 | }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | #define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1) | ||
| 150 | #define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5) | ||
| 151 | #define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0) | ||
| 152 | #define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4) | ||
| 153 | #define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2) | ||
| 154 | |||
| 155 | static int marxbot_basecam_power(struct device *dev, int on) | ||
| 156 | { | ||
| 157 | gpio_set_value(BASECAM_POWER, !on); | ||
| 158 | return 0; | ||
| 159 | } | ||
| 160 | |||
| 161 | static int marxbot_basecam_reset(struct device *dev) | ||
| 162 | { | ||
| 163 | gpio_set_value(BASECAM_RST_B, 0); | ||
| 164 | udelay(100); | ||
| 165 | gpio_set_value(BASECAM_RST_B, 1); | ||
| 166 | return 0; | ||
| 167 | } | ||
| 168 | |||
| 169 | static struct i2c_board_info marxbot_i2c_devices[] = { | ||
| 170 | { | ||
| 171 | I2C_BOARD_INFO("mt9t031", 0x5d), | ||
| 172 | }, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static struct soc_camera_link base_iclink = { | ||
| 176 | .bus_id = 0, /* Must match with the camera ID */ | ||
| 177 | .power = marxbot_basecam_power, | ||
| 178 | .reset = marxbot_basecam_reset, | ||
| 179 | .board_info = &marxbot_i2c_devices[0], | ||
| 180 | .i2c_adapter_id = 0, | ||
| 181 | .module_name = "mt9t031", | ||
| 182 | }; | ||
| 183 | |||
| 184 | static struct platform_device marxbot_camera[] = { | ||
| 185 | { | ||
| 186 | .name = "soc-camera-pdrv", | ||
| 187 | .id = 0, | ||
| 188 | .dev = { | ||
| 189 | .platform_data = &base_iclink, | ||
| 190 | }, | ||
| 191 | }, | ||
| 192 | }; | ||
| 193 | |||
| 194 | static struct platform_device *marxbot_cameras[] __initdata = { | ||
| 195 | &marxbot_camera[0], | ||
| 196 | }; | ||
| 197 | |||
| 198 | static int __init marxbot_cam_init(void) | ||
| 199 | { | ||
| 200 | int ret = gpio_request(CAM_CHOICE, "cam-choice"); | ||
| 201 | if (ret) | ||
| 202 | return ret; | ||
| 203 | gpio_direction_output(CAM_CHOICE, 1); | ||
| 204 | |||
| 205 | ret = gpio_request(BASECAM_RST_B, "basecam-reset"); | ||
| 206 | if (ret) | ||
| 207 | return ret; | ||
| 208 | gpio_direction_output(BASECAM_RST_B, 1); | ||
| 209 | ret = gpio_request(BASECAM_POWER, "basecam-standby"); | ||
| 210 | if (ret) | ||
| 211 | return ret; | ||
| 212 | gpio_direction_output(BASECAM_POWER, 0); | ||
| 213 | |||
| 214 | ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset"); | ||
| 215 | if (ret) | ||
| 216 | return ret; | ||
| 217 | gpio_direction_output(TURRETCAM_RST_B, 1); | ||
| 218 | ret = gpio_request(TURRETCAM_POWER, "turretcam-standby"); | ||
| 219 | if (ret) | ||
| 220 | return ret; | ||
| 221 | gpio_direction_output(TURRETCAM_POWER, 0); | ||
| 222 | |||
| 223 | return 0; | ||
| 224 | } | ||
| 225 | |||
| 226 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 227 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 228 | |||
| 229 | static int marxbot_usbh1_hw_init(struct platform_device *pdev) | ||
| 230 | { | ||
| 231 | mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); | ||
| 232 | |||
| 233 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); | ||
| 234 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); | ||
| 235 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); | ||
| 236 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); | ||
| 237 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); | ||
| 238 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); | ||
| 239 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); | ||
| 240 | mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG); | ||
| 241 | |||
| 242 | return 0; | ||
| 243 | } | ||
| 244 | |||
| 245 | #define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B) | ||
| 246 | #define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE) | ||
| 247 | |||
| 248 | static int marxbot_isp1105_init(struct otg_transceiver *otg) | ||
| 249 | { | ||
| 250 | int ret = gpio_request(USBH1_MODE, "usbh1-mode"); | ||
| 251 | if (ret) | ||
| 252 | return ret; | ||
| 253 | /* single ended */ | ||
| 254 | gpio_direction_output(USBH1_MODE, 0); | ||
| 255 | |||
| 256 | ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen"); | ||
| 257 | if (ret) { | ||
| 258 | gpio_free(USBH1_MODE); | ||
| 259 | return ret; | ||
| 260 | } | ||
| 261 | gpio_direction_output(USBH1_VBUSEN_B, 1); | ||
| 262 | |||
| 263 | return 0; | ||
| 264 | } | ||
| 265 | |||
| 266 | |||
| 267 | static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on) | ||
| 268 | { | ||
| 269 | if (on) | ||
| 270 | gpio_set_value(USBH1_VBUSEN_B, 0); | ||
| 271 | else | ||
| 272 | gpio_set_value(USBH1_VBUSEN_B, 1); | ||
| 273 | |||
| 274 | return 0; | ||
| 275 | } | ||
| 276 | |||
| 277 | static struct mxc_usbh_platform_data usbh1_pdata = { | ||
| 278 | .init = marxbot_usbh1_hw_init, | ||
| 279 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | ||
| 280 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | ||
| 281 | }; | ||
| 282 | |||
| 283 | static int __init marxbot_usbh1_init(void) | ||
| 284 | { | ||
| 285 | struct otg_transceiver *otg; | ||
| 286 | |||
| 287 | otg = kzalloc(sizeof(*otg), GFP_KERNEL); | ||
| 288 | if (!otg) | ||
| 289 | return -ENOMEM; | ||
| 290 | |||
| 291 | otg->label = "ISP1105"; | ||
| 292 | otg->init = marxbot_isp1105_init; | ||
| 293 | otg->set_vbus = marxbot_isp1105_set_vbus; | ||
| 294 | |||
| 295 | usbh1_pdata.otg = otg; | ||
| 296 | |||
| 297 | return mxc_register_device(&mx31_usbh1, &usbh1_pdata); | ||
| 298 | } | ||
| 299 | |||
| 123 | /* | 300 | /* |
| 124 | * system init for baseboard usage. Will be called by mx31moboard init. | 301 | * system init for baseboard usage. Will be called by mx31moboard init. |
| 125 | */ | 302 | */ |
| @@ -133,4 +310,17 @@ void __init mx31moboard_marxbot_init(void) | |||
| 133 | dspics_resets_init(); | 310 | dspics_resets_init(); |
| 134 | 311 | ||
| 135 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); | 312 | mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); |
| 313 | |||
| 314 | spi_register_board_info(marxbot_spi_board_info, | ||
| 315 | ARRAY_SIZE(marxbot_spi_board_info)); | ||
| 316 | |||
| 317 | marxbot_cam_init(); | ||
| 318 | platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras)); | ||
| 319 | |||
| 320 | /* battery present pin */ | ||
| 321 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present"); | ||
| 322 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); | ||
| 323 | gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); | ||
| 324 | |||
| 325 | marxbot_usbh1_init(); | ||
| 136 | } | 326 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index 9243de54041a..b70529145936 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/delay.h> | 19 | #include <linux/delay.h> |
| 20 | #include <linux/dma-mapping.h> | ||
| 20 | #include <linux/fsl_devices.h> | 21 | #include <linux/fsl_devices.h> |
| 21 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 22 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| @@ -26,8 +27,14 @@ | |||
| 26 | #include <linux/mtd/physmap.h> | 27 | #include <linux/mtd/physmap.h> |
| 27 | #include <linux/mtd/partitions.h> | 28 | #include <linux/mtd/partitions.h> |
| 28 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/regulator/machine.h> | ||
| 31 | #include <linux/mfd/mc13783.h> | ||
| 32 | #include <linux/spi/spi.h> | ||
| 29 | #include <linux/types.h> | 33 | #include <linux/types.h> |
| 30 | 34 | ||
| 35 | #include <linux/usb/otg.h> | ||
| 36 | #include <linux/usb/ulpi.h> | ||
| 37 | |||
| 31 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 32 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/time.h> | 40 | #include <asm/mach/time.h> |
| @@ -37,16 +44,20 @@ | |||
| 37 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
| 38 | #include <mach/imx-uart.h> | 45 | #include <mach/imx-uart.h> |
| 39 | #include <mach/iomux-mx3.h> | 46 | #include <mach/iomux-mx3.h> |
| 47 | #include <mach/ipu.h> | ||
| 40 | #include <mach/i2c.h> | 48 | #include <mach/i2c.h> |
| 41 | #include <mach/mmc.h> | 49 | #include <mach/mmc.h> |
| 42 | #include <mach/mx31.h> | 50 | #include <mach/mxc_ehci.h> |
| 51 | #include <mach/mx3_camera.h> | ||
| 52 | #include <mach/spi.h> | ||
| 53 | #include <mach/ulpi.h> | ||
| 43 | 54 | ||
| 44 | #include "devices.h" | 55 | #include "devices.h" |
| 45 | 56 | ||
| 46 | static unsigned int moboard_pins[] = { | 57 | static unsigned int moboard_pins[] = { |
| 47 | /* UART0 */ | 58 | /* UART0 */ |
| 48 | MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, | ||
| 49 | MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, | 59 | MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, |
| 60 | MX31_PIN_CTS1__GPIO2_7, | ||
| 50 | /* UART4 */ | 61 | /* UART4 */ |
| 51 | MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, | 62 | MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, |
| 52 | MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, | 63 | MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, |
| @@ -73,12 +84,31 @@ static unsigned int moboard_pins[] = { | |||
| 73 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, | 84 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR, |
| 74 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, | 85 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP, |
| 75 | MX31_PIN_USB_OC__GPIO1_30, | 86 | MX31_PIN_USB_OC__GPIO1_30, |
| 87 | /* USB H2 */ | ||
| 88 | MX31_PIN_USBH2_DATA0__USBH2_DATA0, | ||
| 89 | MX31_PIN_USBH2_DATA1__USBH2_DATA1, | ||
| 90 | MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3, | ||
| 91 | MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5, | ||
| 92 | MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7, | ||
| 93 | MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR, | ||
| 94 | MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP, | ||
| 95 | MX31_PIN_SCK6__GPIO1_25, | ||
| 76 | /* LEDs */ | 96 | /* LEDs */ |
| 77 | MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, | 97 | MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1, |
| 78 | MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, | 98 | MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3, |
| 79 | /* SEL */ | 99 | /* SEL */ |
| 80 | MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, | 100 | MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9, |
| 81 | MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, | 101 | MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11, |
| 102 | /* SPI1 */ | ||
| 103 | MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO, | ||
| 104 | MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | ||
| 105 | MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2, | ||
| 106 | /* Atlas IRQ */ | ||
| 107 | MX31_PIN_GPIO1_3__GPIO1_3, | ||
| 108 | /* SPI2 */ | ||
| 109 | MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO, | ||
| 110 | MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY, | ||
| 111 | MX31_PIN_CSPI2_SS1__CSPI3_SS1, | ||
| 82 | }; | 112 | }; |
| 83 | 113 | ||
| 84 | static struct physmap_flash_data mx31moboard_flash_data = { | 114 | static struct physmap_flash_data mx31moboard_flash_data = { |
| @@ -101,7 +131,18 @@ static struct platform_device mx31moboard_flash = { | |||
| 101 | .num_resources = 1, | 131 | .num_resources = 1, |
| 102 | }; | 132 | }; |
| 103 | 133 | ||
| 104 | static struct imxuart_platform_data uart_pdata = { | 134 | static int moboard_uart0_init(struct platform_device *pdev) |
| 135 | { | ||
| 136 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack"); | ||
| 137 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0); | ||
| 138 | return 0; | ||
| 139 | } | ||
| 140 | |||
| 141 | static struct imxuart_platform_data uart0_pdata = { | ||
| 142 | .init = moboard_uart0_init, | ||
| 143 | }; | ||
| 144 | |||
| 145 | static struct imxuart_platform_data uart4_pdata = { | ||
| 105 | .flags = IMXUART_HAVE_RTSCTS, | 146 | .flags = IMXUART_HAVE_RTSCTS, |
| 106 | }; | 147 | }; |
| 107 | 148 | ||
| @@ -113,6 +154,103 @@ static struct imxi2c_platform_data moboard_i2c1_pdata = { | |||
| 113 | .bitrate = 100000, | 154 | .bitrate = 100000, |
| 114 | }; | 155 | }; |
| 115 | 156 | ||
| 157 | static int moboard_spi1_cs[] = { | ||
| 158 | MXC_SPI_CS(0), | ||
| 159 | MXC_SPI_CS(2), | ||
| 160 | }; | ||
| 161 | |||
| 162 | static struct spi_imx_master moboard_spi1_master = { | ||
| 163 | .chipselect = moboard_spi1_cs, | ||
| 164 | .num_chipselect = ARRAY_SIZE(moboard_spi1_cs), | ||
| 165 | }; | ||
| 166 | |||
| 167 | static struct regulator_consumer_supply sdhc_consumers[] = { | ||
| 168 | { | ||
| 169 | .dev = &mxcsdhc_device0.dev, | ||
| 170 | .supply = "sdhc0_vcc", | ||
| 171 | }, | ||
| 172 | { | ||
| 173 | .dev = &mxcsdhc_device1.dev, | ||
| 174 | .supply = "sdhc1_vcc", | ||
| 175 | }, | ||
| 176 | }; | ||
| 177 | |||
| 178 | static struct regulator_init_data sdhc_vreg_data = { | ||
| 179 | .constraints = { | ||
| 180 | .min_uV = 2700000, | ||
| 181 | .max_uV = 3000000, | ||
| 182 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | ||
| 183 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, | ||
| 184 | .valid_modes_mask = REGULATOR_MODE_NORMAL | | ||
| 185 | REGULATOR_MODE_FAST, | ||
| 186 | .always_on = 0, | ||
| 187 | .boot_on = 1, | ||
| 188 | }, | ||
| 189 | .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers), | ||
| 190 | .consumer_supplies = sdhc_consumers, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct regulator_consumer_supply cam_consumers[] = { | ||
| 194 | { | ||
| 195 | .dev = &mx3_camera.dev, | ||
| 196 | .supply = "cam_vcc", | ||
| 197 | }, | ||
| 198 | }; | ||
| 199 | |||
| 200 | static struct regulator_init_data cam_vreg_data = { | ||
| 201 | .constraints = { | ||
| 202 | .min_uV = 2700000, | ||
| 203 | .max_uV = 3000000, | ||
| 204 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | ||
| 205 | REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS, | ||
| 206 | .valid_modes_mask = REGULATOR_MODE_NORMAL | | ||
| 207 | REGULATOR_MODE_FAST, | ||
| 208 | .always_on = 0, | ||
| 209 | .boot_on = 1, | ||
| 210 | }, | ||
| 211 | .num_consumer_supplies = ARRAY_SIZE(cam_consumers), | ||
| 212 | .consumer_supplies = cam_consumers, | ||
| 213 | }; | ||
| 214 | |||
| 215 | static struct mc13783_regulator_init_data moboard_regulators[] = { | ||
| 216 | { | ||
| 217 | .id = MC13783_REGU_VMMC1, | ||
| 218 | .init_data = &sdhc_vreg_data, | ||
| 219 | }, | ||
| 220 | { | ||
| 221 | .id = MC13783_REGU_VCAM, | ||
| 222 | .init_data = &cam_vreg_data, | ||
| 223 | }, | ||
| 224 | }; | ||
| 225 | |||
| 226 | static struct mc13783_platform_data moboard_pmic = { | ||
| 227 | .regulators = moboard_regulators, | ||
| 228 | .num_regulators = ARRAY_SIZE(moboard_regulators), | ||
| 229 | .flags = MC13783_USE_REGULATOR | MC13783_USE_RTC | | ||
| 230 | MC13783_USE_ADC, | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct spi_board_info moboard_spi_board_info[] __initdata = { | ||
| 234 | { | ||
| 235 | .modalias = "mc13783", | ||
| 236 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | ||
| 237 | .max_speed_hz = 300000, | ||
| 238 | .bus_num = 1, | ||
| 239 | .chip_select = 0, | ||
| 240 | .platform_data = &moboard_pmic, | ||
| 241 | .mode = SPI_CS_HIGH, | ||
| 242 | }, | ||
| 243 | }; | ||
| 244 | |||
| 245 | static int moboard_spi2_cs[] = { | ||
| 246 | MXC_SPI_CS(1), | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct spi_imx_master moboard_spi2_master = { | ||
| 250 | .chipselect = moboard_spi2_cs, | ||
| 251 | .num_chipselect = ARRAY_SIZE(moboard_spi2_cs), | ||
| 252 | }; | ||
| 253 | |||
| 116 | #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) | 254 | #define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0) |
| 117 | #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) | 255 | #define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1) |
| 118 | 256 | ||
| @@ -208,6 +346,56 @@ static struct fsl_usb2_platform_data usb_pdata = { | |||
| 208 | .phy_mode = FSL_USB2_PHY_ULPI, | 346 | .phy_mode = FSL_USB2_PHY_ULPI, |
| 209 | }; | 347 | }; |
| 210 | 348 | ||
| 349 | #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) | ||
| 350 | |||
| 351 | static int moboard_usbh2_hw_init(struct platform_device *pdev) | ||
| 352 | { | ||
| 353 | int ret = gpio_request(USBH2_EN_B, "usbh2-en"); | ||
| 354 | if (ret) | ||
| 355 | return ret; | ||
| 356 | |||
| 357 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); | ||
| 358 | |||
| 359 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | ||
| 360 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | ||
| 361 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | ||
| 362 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | ||
| 363 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | ||
| 364 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | ||
| 365 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); | ||
| 366 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); | ||
| 367 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); | ||
| 368 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); | ||
| 369 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); | ||
| 370 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); | ||
| 371 | |||
| 372 | gpio_direction_output(USBH2_EN_B, 0); | ||
| 373 | |||
| 374 | return 0; | ||
| 375 | } | ||
| 376 | |||
| 377 | static int moboard_usbh2_hw_exit(struct platform_device *pdev) | ||
| 378 | { | ||
| 379 | gpio_free(USBH2_EN_B); | ||
| 380 | return 0; | ||
| 381 | } | ||
| 382 | |||
| 383 | static struct mxc_usbh_platform_data usbh2_pdata = { | ||
| 384 | .init = moboard_usbh2_hw_init, | ||
| 385 | .exit = moboard_usbh2_hw_exit, | ||
| 386 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | ||
| 387 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 388 | }; | ||
| 389 | |||
| 390 | static int __init moboard_usbh2_init(void) | ||
| 391 | { | ||
| 392 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 393 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | ||
| 394 | |||
| 395 | return mxc_register_device(&mx31_usbh2, &usbh2_pdata); | ||
| 396 | } | ||
| 397 | |||
| 398 | |||
| 211 | static struct gpio_led mx31moboard_leds[] = { | 399 | static struct gpio_led mx31moboard_leds[] = { |
| 212 | { | 400 | { |
| 213 | .name = "coreboard-led-0:red:running", | 401 | .name = "coreboard-led-0:red:running", |
| @@ -266,11 +454,48 @@ static void mx31moboard_init_sel_gpios(void) | |||
| 266 | } | 454 | } |
| 267 | } | 455 | } |
| 268 | 456 | ||
| 457 | static struct ipu_platform_data mx3_ipu_data = { | ||
| 458 | .irq_base = MXC_IPU_IRQ_START, | ||
| 459 | }; | ||
| 460 | |||
| 269 | static struct platform_device *devices[] __initdata = { | 461 | static struct platform_device *devices[] __initdata = { |
| 270 | &mx31moboard_flash, | 462 | &mx31moboard_flash, |
| 271 | &mx31moboard_leds_device, | 463 | &mx31moboard_leds_device, |
| 272 | }; | 464 | }; |
| 273 | 465 | ||
| 466 | static struct mx3_camera_pdata camera_pdata = { | ||
| 467 | .dma_dev = &mx3_ipu.dev, | ||
| 468 | .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10, | ||
| 469 | .mclk_10khz = 4800, | ||
| 470 | }; | ||
| 471 | |||
| 472 | #define CAMERA_BUF_SIZE (4*1024*1024) | ||
| 473 | |||
| 474 | static int __init mx31moboard_cam_alloc_dma(const size_t buf_size) | ||
| 475 | { | ||
| 476 | dma_addr_t dma_handle; | ||
| 477 | void *buf; | ||
| 478 | int dma; | ||
| 479 | |||
| 480 | if (buf_size < 2 * 1024 * 1024) | ||
| 481 | return -EINVAL; | ||
| 482 | |||
| 483 | buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL); | ||
| 484 | if (!buf) { | ||
| 485 | pr_err("%s: cannot allocate camera buffer-memory\n", __func__); | ||
| 486 | return -ENOMEM; | ||
| 487 | } | ||
| 488 | |||
| 489 | memset(buf, 0, buf_size); | ||
| 490 | |||
| 491 | dma = dma_declare_coherent_memory(&mx3_camera.dev, | ||
| 492 | dma_handle, dma_handle, buf_size, | ||
| 493 | DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE); | ||
| 494 | |||
| 495 | /* The way we call dma_declare_coherent_memory only a malloc can fail */ | ||
| 496 | return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM; | ||
| 497 | } | ||
| 498 | |||
| 274 | static int mx31moboard_baseboard; | 499 | static int mx31moboard_baseboard; |
| 275 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); | 500 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); |
| 276 | 501 | ||
| @@ -284,20 +509,34 @@ static void __init mxc_board_init(void) | |||
| 284 | 509 | ||
| 285 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 510 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 286 | 511 | ||
| 287 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 512 | mxc_register_device(&mxc_uart_device0, &uart0_pdata); |
| 288 | mxc_register_device(&mxc_uart_device4, &uart_pdata); | 513 | |
| 514 | mxc_register_device(&mxc_uart_device4, &uart4_pdata); | ||
| 289 | 515 | ||
| 290 | mx31moboard_init_sel_gpios(); | 516 | mx31moboard_init_sel_gpios(); |
| 291 | 517 | ||
| 292 | mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); | 518 | mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata); |
| 293 | mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); | 519 | mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata); |
| 294 | 520 | ||
| 521 | mxc_register_device(&mxc_spi_device1, &moboard_spi1_master); | ||
| 522 | mxc_register_device(&mxc_spi_device2, &moboard_spi2_master); | ||
| 523 | |||
| 524 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq"); | ||
| 525 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)); | ||
| 526 | spi_register_board_info(moboard_spi_board_info, | ||
| 527 | ARRAY_SIZE(moboard_spi_board_info)); | ||
| 528 | |||
| 295 | mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); | 529 | mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); |
| 296 | 530 | ||
| 531 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | ||
| 532 | if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) | ||
| 533 | mxc_register_device(&mx3_camera, &camera_pdata); | ||
| 534 | |||
| 297 | usb_xcvr_reset(); | 535 | usb_xcvr_reset(); |
| 298 | 536 | ||
| 299 | moboard_usbotg_init(); | 537 | moboard_usbotg_init(); |
| 300 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | 538 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); |
| 539 | moboard_usbh2_init(); | ||
| 301 | 540 | ||
| 302 | switch (mx31moboard_baseboard) { | 541 | switch (mx31moboard_baseboard) { |
| 303 | case MX31NOBOARD: | 542 | case MX31NOBOARD: |
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c index 6ff186e46ceb..0bbc65ea23c8 100644 --- a/arch/arm/mach-mx3/mx35pdk.c +++ b/arch/arm/mach-mx3/mx35pdk.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/memory.h> | 24 | #include <linux/memory.h> |
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <linux/fsl_devices.h> | ||
| 26 | 27 | ||
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| @@ -69,6 +70,15 @@ static struct pad_desc mx35pdk_pads[] = { | |||
| 69 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, | 70 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, |
| 70 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, | 71 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, |
| 71 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, | 72 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, |
| 73 | /* USBOTG */ | ||
| 74 | MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, | ||
| 75 | MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, | ||
| 76 | }; | ||
| 77 | |||
| 78 | /* OTG config */ | ||
| 79 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 80 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 81 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | ||
| 72 | }; | 82 | }; |
| 73 | 83 | ||
| 74 | /* | 84 | /* |
| @@ -81,6 +91,8 @@ static void __init mxc_board_init(void) | |||
| 81 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 91 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 82 | 92 | ||
| 83 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 93 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 94 | |||
| 95 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | ||
| 84 | } | 96 | } |
| 85 | 97 | ||
| 86 | static void __init mx35pdk_timer_init(void) | 98 | static void __init mx35pdk_timer_init(void) |
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c index e18a224671fa..e3aa829be586 100644 --- a/arch/arm/mach-mx3/pcm043.c +++ b/arch/arm/mach-mx3/pcm043.c | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #include <mach/iomux-mx35.h> | 43 | #include <mach/iomux-mx35.h> |
| 44 | #include <mach/ipu.h> | 44 | #include <mach/ipu.h> |
| 45 | #include <mach/mx3fb.h> | 45 | #include <mach/mx3fb.h> |
| 46 | #include <mach/mxc_nand.h> | ||
| 46 | 47 | ||
| 47 | #include "devices.h" | 48 | #include "devices.h" |
| 48 | 49 | ||
| @@ -206,6 +207,11 @@ static struct pad_desc pcm043_pads[] = { | |||
| 206 | MX35_PAD_ATA_CS0__GPIO2_6, | 207 | MX35_PAD_ATA_CS0__GPIO2_6, |
| 207 | }; | 208 | }; |
| 208 | 209 | ||
| 210 | static struct mxc_nand_platform_data pcm037_nand_board_info = { | ||
| 211 | .width = 1, | ||
| 212 | .hw_ecc = 1, | ||
| 213 | }; | ||
| 214 | |||
| 209 | /* | 215 | /* |
| 210 | * Board specific initialization. | 216 | * Board specific initialization. |
| 211 | */ | 217 | */ |
| @@ -216,6 +222,7 @@ static void __init mxc_board_init(void) | |||
| 216 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 222 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 217 | 223 | ||
| 218 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 224 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 225 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); | ||
| 219 | 226 | ||
| 220 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | 227 | mxc_register_device(&mxc_uart_device1, &uart_pdata); |
| 221 | 228 | ||
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index a6f8eab14ba5..d89c6adbe8bc 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -2,34 +2,105 @@ if ARCH_PXA | |||
| 2 | 2 | ||
| 3 | menu "Intel PXA2xx/PXA3xx Implementations" | 3 | menu "Intel PXA2xx/PXA3xx Implementations" |
| 4 | 4 | ||
| 5 | if PXA3xx | 5 | comment "Intel/Marvell Dev Platforms (sorted by hardware release time)" |
| 6 | 6 | ||
| 7 | menu "Supported PXA3xx Processor Variants" | 7 | config ARCH_LUBBOCK |
| 8 | bool "Intel DBPXA250 Development Platform (aka Lubbock)" | ||
| 9 | select PXA25x | ||
| 10 | select SA1111 | ||
| 11 | select PXA_HAVE_BOARD_IRQS | ||
| 8 | 12 | ||
| 9 | config CPU_PXA300 | 13 | config MACH_MAINSTONE |
| 10 | bool "PXA300 (codename Monahans-L)" | 14 | bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" |
| 15 | select PXA27x | ||
| 16 | select HAVE_PWM | ||
| 17 | select PXA_HAVE_BOARD_IRQS | ||
| 11 | 18 | ||
| 12 | config CPU_PXA310 | 19 | config MACH_ZYLONITE |
| 13 | bool "PXA310 (codename Monahans-LV)" | 20 | bool |
| 21 | select PXA3xx | ||
| 22 | select PXA_SSP | ||
| 23 | select HAVE_PWM | ||
| 24 | select PXA_HAVE_BOARD_IRQS | ||
| 25 | |||
| 26 | config MACH_ZYLONITE300 | ||
| 27 | bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" | ||
| 14 | select CPU_PXA300 | 28 | select CPU_PXA300 |
| 29 | select CPU_PXA310 | ||
| 30 | select MACH_ZYLONITE | ||
| 15 | 31 | ||
| 16 | config CPU_PXA320 | 32 | config MACH_ZYLONITE320 |
| 17 | bool "PXA320 (codename Monahans-P)" | 33 | bool "PXA3xx Development Platform (aka Zylonite) PXA320" |
| 34 | select CPU_PXA320 | ||
| 35 | select MACH_ZYLONITE | ||
| 18 | 36 | ||
| 19 | config CPU_PXA930 | 37 | config MACH_LITTLETON |
| 20 | bool "PXA930 (codename Tavor-P)" | 38 | bool "PXA3xx Form Factor Platform (aka Littleton)" |
| 39 | select PXA3xx | ||
| 40 | select PXA_SSP | ||
| 21 | 41 | ||
| 22 | config CPU_PXA935 | 42 | config MACH_TAVOREVB |
| 23 | bool "PXA935 (codename Tavor-P65)" | 43 | bool "PXA930 Evaluation Board (aka TavorEVB)" |
| 44 | select PXA3xx | ||
| 24 | select CPU_PXA930 | 45 | select CPU_PXA930 |
| 25 | 46 | ||
| 26 | config CPU_PXA950 | 47 | config MACH_SAAR |
| 27 | bool "PXA950 (codename Tavor-PV2)" | 48 | bool "PXA930 Handheld Platform (aka SAAR)" |
| 49 | select PXA3xx | ||
| 28 | select CPU_PXA930 | 50 | select CPU_PXA930 |
| 29 | 51 | ||
| 30 | endmenu | 52 | comment "Third Party Dev Platforms (sorted by vendor name)" |
| 31 | 53 | ||
| 32 | endif | 54 | config ARCH_PXA_IDP |
| 55 | bool "Accelent Xscale IDP" | ||
| 56 | select PXA25x | ||
| 57 | |||
| 58 | config ARCH_VIPER | ||
| 59 | bool "Arcom/Eurotech VIPER SBC" | ||
| 60 | select PXA25x | ||
| 61 | select ISA | ||
| 62 | select I2C_GPIO | ||
| 63 | select HAVE_PWM | ||
| 64 | select PXA_HAVE_BOARD_IRQS | ||
| 65 | select PXA_HAVE_ISA_IRQS | ||
| 66 | |||
| 67 | config MACH_BALLOON3 | ||
| 68 | bool "Balloon 3 board" | ||
| 69 | select PXA27x | ||
| 70 | select IWMMXT | ||
| 71 | select PXA_HAVE_BOARD_IRQS | ||
| 72 | |||
| 73 | config MACH_CSB726 | ||
| 74 | bool "Enable Cogent CSB726 System On a Module" | ||
| 75 | select PXA27x | ||
| 76 | select IWMMXT | ||
| 77 | help | ||
| 78 | Say Y here if you intend to run this kernel on a Cogent | ||
| 79 | CSB726 System On Module. | ||
| 80 | |||
| 81 | config CSB726_CSB701 | ||
| 82 | bool "Enable support for CSB701 baseboard" | ||
| 83 | depends on MACH_CSB726 | ||
| 84 | |||
| 85 | config MACH_ARMCORE | ||
| 86 | bool "CompuLab CM-X255/CM-X270 modules" | ||
| 87 | select PXA27x | ||
| 88 | select IWMMXT | ||
| 89 | select PXA25x | ||
| 90 | select PXA_SSP | ||
| 91 | |||
| 92 | config MACH_EM_X270 | ||
| 93 | bool "CompuLab EM-x270 platform" | ||
| 94 | select PXA27x | ||
| 95 | |||
| 96 | config MACH_EXEDA | ||
| 97 | bool "CompuLab eXeda platform" | ||
| 98 | select PXA27x | ||
| 99 | |||
| 100 | config MACH_CM_X300 | ||
| 101 | bool "CompuLab CM-X300 modules" | ||
| 102 | select PXA3xx | ||
| 103 | select CPU_PXA300 | ||
| 33 | 104 | ||
| 34 | config ARCH_GUMSTIX | 105 | config ARCH_GUMSTIX |
| 35 | bool "Gumstix XScale 255 boards" | 106 | bool "Gumstix XScale 255 boards" |
| @@ -62,185 +133,24 @@ config MACH_STARGATE2 | |||
| 62 | select IWMMXT | 133 | select IWMMXT |
| 63 | select PXA_HAVE_BOARD_IRQS | 134 | select PXA_HAVE_BOARD_IRQS |
| 64 | 135 | ||
| 65 | config ARCH_LUBBOCK | 136 | config MACH_XCEP |
| 66 | bool "Intel DBPXA250 Development Platform" | 137 | bool "Iskratel Electronics XCEP" |
| 67 | select PXA25x | ||
| 68 | select SA1111 | ||
| 69 | select PXA_HAVE_BOARD_IRQS | ||
| 70 | |||
| 71 | config MACH_LOGICPD_PXA270 | ||
| 72 | bool "LogicPD PXA270 Card Engine Development Platform" | ||
| 73 | select PXA27x | ||
| 74 | select HAVE_PWM | ||
| 75 | select PXA_HAVE_BOARD_IRQS | ||
| 76 | |||
| 77 | config MACH_MAINSTONE | ||
| 78 | bool "Intel HCDDBBVA0 Development Platform" | ||
| 79 | select PXA27x | ||
| 80 | select HAVE_PWM | ||
| 81 | select PXA_HAVE_BOARD_IRQS | ||
| 82 | |||
| 83 | config MACH_MP900C | ||
| 84 | bool "Nec Mobilepro 900/c" | ||
| 85 | select PXA25x | ||
| 86 | |||
| 87 | config MACH_BALLOON3 | ||
| 88 | bool "Balloon 3 board" | ||
| 89 | select PXA27x | ||
| 90 | select IWMMXT | ||
| 91 | select PXA_HAVE_BOARD_IRQS | ||
| 92 | |||
| 93 | config ARCH_PXA_IDP | ||
| 94 | bool "Accelent Xscale IDP" | ||
| 95 | select PXA25x | ||
| 96 | |||
| 97 | config PXA_SHARPSL | ||
| 98 | bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" | ||
| 99 | select SHARP_SCOOP | ||
| 100 | select SHARP_PARAM | ||
| 101 | help | ||
| 102 | Say Y here if you intend to run this kernel on a | ||
| 103 | Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), | ||
| 104 | SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), | ||
| 105 | SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) | ||
| 106 | handheld computer. | ||
| 107 | |||
| 108 | config SHARPSL_PM | ||
| 109 | bool | ||
| 110 | select APM_EMULATION | ||
| 111 | |||
| 112 | config CORGI_SSP_DEPRECATED | ||
| 113 | bool | ||
| 114 | select PXA_SSP | ||
| 115 | help | ||
| 116 | This option will include corgi_ssp.c and corgi_lcd.c | ||
| 117 | that corgi_ts.c and other legacy drivers (corgi_bl.c | ||
| 118 | and sharpsl_pm.c) may depend on. | ||
| 119 | |||
| 120 | config MACH_POODLE | ||
| 121 | bool "Enable Sharp SL-5600 (Poodle) Support" | ||
| 122 | depends on PXA_SHARPSL | ||
| 123 | select PXA25x | 138 | select PXA25x |
| 124 | select SHARP_LOCOMO | 139 | select MTD |
| 140 | select MTD_PARTITIONS | ||
| 141 | select MTD_PHYSMAP | ||
| 142 | select MTD_CFI_INTELEXT | ||
| 143 | select MTD_CFI | ||
| 144 | select MTD_CHAR | ||
| 145 | select SMC91X | ||
| 125 | select PXA_SSP | 146 | select PXA_SSP |
| 126 | |||
| 127 | config MACH_CORGI | ||
| 128 | bool "Enable Sharp SL-C700 (Corgi) Support" | ||
| 129 | depends on PXA_SHARPSL | ||
| 130 | select PXA25x | ||
| 131 | select PXA_SHARP_C7xx | ||
| 132 | |||
| 133 | config MACH_SHEPHERD | ||
| 134 | bool "Enable Sharp SL-C750 (Shepherd) Support" | ||
| 135 | depends on PXA_SHARPSL | ||
| 136 | select PXA25x | ||
| 137 | select PXA_SHARP_C7xx | ||
| 138 | |||
| 139 | config MACH_HUSKY | ||
| 140 | bool "Enable Sharp SL-C760 (Husky) Support" | ||
| 141 | depends on PXA_SHARPSL | ||
| 142 | select PXA25x | ||
| 143 | select PXA_SHARP_C7xx | ||
| 144 | |||
| 145 | config MACH_AKITA | ||
| 146 | bool "Enable Sharp SL-1000 (Akita) Support" | ||
| 147 | depends on PXA_SHARPSL | ||
| 148 | select PXA27x | ||
| 149 | select PXA_SHARP_Cxx00 | ||
| 150 | select MACH_SPITZ | ||
| 151 | select I2C | ||
| 152 | select I2C_PXA | ||
| 153 | |||
| 154 | config MACH_SPITZ | ||
| 155 | bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" | ||
| 156 | depends on PXA_SHARPSL | ||
| 157 | select PXA27x | ||
| 158 | select PXA_SHARP_Cxx00 | ||
| 159 | |||
| 160 | config MACH_BORZOI | ||
| 161 | bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" | ||
| 162 | depends on PXA_SHARPSL | ||
| 163 | select PXA27x | ||
| 164 | select PXA_SHARP_Cxx00 | ||
| 165 | |||
| 166 | config MACH_TOSA | ||
| 167 | bool "Enable Sharp SL-6000x (Tosa) Support" | ||
| 168 | depends on PXA_SHARPSL | ||
| 169 | select PXA25x | ||
| 170 | select PXA_HAVE_BOARD_IRQS | ||
| 171 | |||
| 172 | config ARCH_VIPER | ||
| 173 | bool "Arcom/Eurotech VIPER SBC" | ||
| 174 | select PXA25x | ||
| 175 | select ISA | ||
| 176 | select I2C_GPIO | ||
| 177 | select HAVE_PWM | ||
| 178 | select PXA_HAVE_BOARD_IRQS | ||
| 179 | select PXA_HAVE_ISA_IRQS | ||
| 180 | |||
| 181 | config ARCH_PXA_ESERIES | ||
| 182 | bool "PXA based Toshiba e-series PDAs" | ||
| 183 | select PXA25x | ||
| 184 | select PXA_HAVE_BOARD_IRQS | ||
| 185 | |||
| 186 | config MACH_E330 | ||
| 187 | bool "Toshiba e330" | ||
| 188 | default y | ||
| 189 | depends on ARCH_PXA_ESERIES | ||
| 190 | help | ||
| 191 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 192 | e330 family PDA. | ||
| 193 | |||
| 194 | config MACH_E350 | ||
| 195 | bool "Toshiba e350" | ||
| 196 | default y | ||
| 197 | depends on ARCH_PXA_ESERIES | ||
| 198 | help | ||
| 199 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 200 | e350 family PDA. | ||
| 201 | |||
| 202 | config MACH_E740 | ||
| 203 | bool "Toshiba e740" | ||
| 204 | default y | ||
| 205 | depends on ARCH_PXA_ESERIES | ||
| 206 | select FB_W100 | ||
| 207 | help | ||
| 208 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 209 | e740 family PDA. | ||
| 210 | |||
| 211 | config MACH_E750 | ||
| 212 | bool "Toshiba e750" | ||
| 213 | default y | ||
| 214 | depends on ARCH_PXA_ESERIES | ||
| 215 | select FB_W100 | ||
| 216 | help | ||
| 217 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 218 | e750 family PDA. | ||
| 219 | |||
| 220 | config MACH_E400 | ||
| 221 | bool "Toshiba e400" | ||
| 222 | default y | ||
| 223 | depends on ARCH_PXA_ESERIES | ||
| 224 | help | 147 | help |
| 225 | Say Y here if you intend to run this kernel on a Toshiba | 148 | PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. |
| 226 | e400 family PDA. | 149 | Tuned for usage in Libera instruments for particle accelerators. |
| 227 | |||
| 228 | config MACH_E800 | ||
| 229 | bool "Toshiba e800" | ||
| 230 | default y | ||
| 231 | depends on ARCH_PXA_ESERIES | ||
| 232 | select FB_W100 | ||
| 233 | help | ||
| 234 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 235 | e800 family PDA. | ||
| 236 | 150 | ||
| 237 | config TRIZEPS_PXA | 151 | config TRIZEPS_PXA |
| 238 | bool "PXA based Keith und Koep Trizeps DIMM-Modules" | 152 | bool "PXA based Keith und Koep Trizeps DIMM-Modules" |
| 239 | 153 | ||
| 240 | config MACH_H5000 | ||
| 241 | bool "HP iPAQ h5000" | ||
| 242 | select PXA25x | ||
| 243 | |||
| 244 | config MACH_TRIZEPS4 | 154 | config MACH_TRIZEPS4 |
| 245 | bool "Keith und Koep Trizeps4 DIMM-Module" | 155 | bool "Keith und Koep Trizeps4 DIMM-Module" |
| 246 | depends on TRIZEPS_PXA | 156 | depends on TRIZEPS_PXA |
| @@ -274,13 +184,38 @@ config TRIZEPS_PCMCIA | |||
| 274 | help | 184 | help |
| 275 | Enable PCMCIA support for Trizeps modules | 185 | Enable PCMCIA support for Trizeps modules |
| 276 | 186 | ||
| 277 | config MACH_EM_X270 | 187 | config MACH_LOGICPD_PXA270 |
| 278 | bool "CompuLab EM-x270 platform" | 188 | bool "LogicPD PXA270 Card Engine Development Platform" |
| 279 | select PXA27x | 189 | select PXA27x |
| 190 | select HAVE_PWM | ||
| 191 | select PXA_HAVE_BOARD_IRQS | ||
| 280 | 192 | ||
| 281 | config MACH_EXEDA | 193 | config MACH_PCM027 |
| 282 | bool "CompuLab eXeda platform" | 194 | bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" |
| 283 | select PXA27x | 195 | select PXA27x |
| 196 | select IWMMXT | ||
| 197 | select PXA_SSP | ||
| 198 | select PXA_HAVE_BOARD_IRQS | ||
| 199 | |||
| 200 | config MACH_PCM990_BASEBOARD | ||
| 201 | bool "PHYTEC PCM-990 development board" | ||
| 202 | select HAVE_PWM | ||
| 203 | depends on MACH_PCM027 | ||
| 204 | |||
| 205 | choice | ||
| 206 | prompt "display on pcm990" | ||
| 207 | depends on MACH_PCM990_BASEBOARD | ||
| 208 | |||
| 209 | config PCM990_DISPLAY_SHARP | ||
| 210 | bool "sharp lq084v1dg21 stn display" | ||
| 211 | |||
| 212 | config PCM990_DISPLAY_NEC | ||
| 213 | bool "nec nl6448bc20_18d tft display" | ||
| 214 | |||
| 215 | config PCM990_DISPLAY_NONE | ||
| 216 | bool "no display" | ||
| 217 | |||
| 218 | endchoice | ||
| 284 | 219 | ||
| 285 | config MACH_COLIBRI | 220 | config MACH_COLIBRI |
| 286 | bool "Toradex Colibri PXA270" | 221 | bool "Toradex Colibri PXA270" |
| @@ -290,45 +225,15 @@ config MACH_COLIBRI300 | |||
| 290 | bool "Toradex Colibri PXA300/310" | 225 | bool "Toradex Colibri PXA300/310" |
| 291 | select PXA3xx | 226 | select PXA3xx |
| 292 | select CPU_PXA300 | 227 | select CPU_PXA300 |
| 228 | select CPU_PXA310 | ||
| 229 | select HAVE_PWM | ||
| 293 | 230 | ||
| 294 | config MACH_COLIBRI320 | 231 | config MACH_COLIBRI320 |
| 295 | bool "Toradex Colibri PXA320" | 232 | bool "Toradex Colibri PXA320" |
| 296 | select PXA3xx | 233 | select PXA3xx |
| 297 | select CPU_PXA320 | 234 | select CPU_PXA320 |
| 298 | 235 | ||
| 299 | config MACH_ZYLONITE | 236 | comment "End-user Products (sorted by vendor name)" |
| 300 | bool "PXA3xx Development Platform (aka Zylonite)" | ||
| 301 | select PXA3xx | ||
| 302 | select PXA_SSP | ||
| 303 | select HAVE_PWM | ||
| 304 | select PXA_HAVE_BOARD_IRQS | ||
| 305 | |||
| 306 | config MACH_LITTLETON | ||
| 307 | bool "PXA3xx Form Factor Platform (aka Littleton)" | ||
| 308 | select PXA3xx | ||
| 309 | select PXA_SSP | ||
| 310 | |||
| 311 | config MACH_TAVOREVB | ||
| 312 | bool "PXA930 Evaluation Board (aka TavorEVB)" | ||
| 313 | select PXA3xx | ||
| 314 | select CPU_PXA930 | ||
| 315 | |||
| 316 | config MACH_SAAR | ||
| 317 | bool "PXA930 Handheld Platform (aka SAAR)" | ||
| 318 | select PXA3xx | ||
| 319 | select CPU_PXA930 | ||
| 320 | |||
| 321 | config MACH_ARMCORE | ||
| 322 | bool "CompuLab CM-X255/CM-X270 modules" | ||
| 323 | select PXA27x | ||
| 324 | select IWMMXT | ||
| 325 | select PXA25x | ||
| 326 | select PXA_SSP | ||
| 327 | |||
| 328 | config MACH_CM_X300 | ||
| 329 | bool "CompuLab CM-X300 modules" | ||
| 330 | select PXA3xx | ||
| 331 | select CPU_PXA300 | ||
| 332 | 237 | ||
| 333 | config MACH_H4700 | 238 | config MACH_H4700 |
| 334 | bool "HP iPAQ hx4700" | 239 | bool "HP iPAQ hx4700" |
| @@ -338,6 +243,15 @@ config MACH_H4700 | |||
| 338 | select HAVE_PWM | 243 | select HAVE_PWM |
| 339 | select PXA_HAVE_BOARD_IRQS | 244 | select PXA_HAVE_BOARD_IRQS |
| 340 | 245 | ||
| 246 | config MACH_H5000 | ||
| 247 | bool "HP iPAQ h5000" | ||
| 248 | select PXA25x | ||
| 249 | |||
| 250 | config MACH_HIMALAYA | ||
| 251 | bool "HTC Himalaya Support" | ||
| 252 | select CPU_PXA26x | ||
| 253 | select FB_W100 | ||
| 254 | |||
| 341 | config MACH_MAGICIAN | 255 | config MACH_MAGICIAN |
| 342 | bool "Enable HTC Magician Support" | 256 | bool "Enable HTC Magician Support" |
| 343 | select PXA27x | 257 | select PXA27x |
| @@ -346,11 +260,6 @@ config MACH_MAGICIAN | |||
| 346 | select HAVE_PWM | 260 | select HAVE_PWM |
| 347 | select PXA_HAVE_BOARD_IRQS | 261 | select PXA_HAVE_BOARD_IRQS |
| 348 | 262 | ||
| 349 | config MACH_HIMALAYA | ||
| 350 | bool "HTC Himalaya Support" | ||
| 351 | select CPU_PXA26x | ||
| 352 | select FB_W100 | ||
| 353 | |||
| 354 | config MACH_MIOA701 | 263 | config MACH_MIOA701 |
| 355 | bool "Mitac Mio A701 Support" | 264 | bool "Mitac Mio A701 Support" |
| 356 | select PXA27x | 265 | select PXA27x |
| @@ -362,13 +271,47 @@ config MACH_MIOA701 | |||
| 362 | MIO A701. Currently there is only basic support | 271 | MIO A701. Currently there is only basic support |
| 363 | for this PDA. | 272 | for this PDA. |
| 364 | 273 | ||
| 365 | config MACH_PCM027 | 274 | config PXA_EZX |
| 366 | bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" | 275 | bool "Motorola EZX Platform" |
| 367 | select PXA27x | 276 | select PXA27x |
| 368 | select IWMMXT | 277 | select IWMMXT |
| 369 | select PXA_SSP | 278 | select HAVE_PWM |
| 370 | select PXA_HAVE_BOARD_IRQS | 279 | select PXA_HAVE_BOARD_IRQS |
| 371 | 280 | ||
| 281 | config MACH_EZX_A780 | ||
| 282 | bool "Motorola EZX A780" | ||
| 283 | default y | ||
| 284 | depends on PXA_EZX | ||
| 285 | |||
| 286 | config MACH_EZX_E680 | ||
| 287 | bool "Motorola EZX E680" | ||
| 288 | default y | ||
| 289 | depends on PXA_EZX | ||
| 290 | |||
| 291 | config MACH_EZX_A1200 | ||
| 292 | bool "Motorola EZX A1200" | ||
| 293 | default y | ||
| 294 | depends on PXA_EZX | ||
| 295 | |||
| 296 | config MACH_EZX_A910 | ||
| 297 | bool "Motorola EZX A910" | ||
| 298 | default y | ||
| 299 | depends on PXA_EZX | ||
| 300 | |||
| 301 | config MACH_EZX_E6 | ||
| 302 | bool "Motorola EZX E6" | ||
| 303 | default y | ||
| 304 | depends on PXA_EZX | ||
| 305 | |||
| 306 | config MACH_EZX_E2 | ||
| 307 | bool "Motorola EZX E2" | ||
| 308 | default y | ||
| 309 | depends on PXA_EZX | ||
| 310 | |||
| 311 | config MACH_MP900C | ||
| 312 | bool "Nec Mobilepro 900/c" | ||
| 313 | select PXA25x | ||
| 314 | |||
| 372 | config ARCH_PXA_PALM | 315 | config ARCH_PXA_PALM |
| 373 | bool "PXA based Palm PDAs" | 316 | bool "PXA based Palm PDAs" |
| 374 | select HAVE_PWM | 317 | select HAVE_PWM |
| @@ -421,109 +364,172 @@ config MACH_PALMZ72 | |||
| 421 | Say Y here if you intend to run this kernel on Palm Zire 72 | 364 | Say Y here if you intend to run this kernel on Palm Zire 72 |
| 422 | handheld computer. | 365 | handheld computer. |
| 423 | 366 | ||
| 424 | config MACH_TREO680 | 367 | config MACH_PALMLD |
| 425 | bool "Palm Treo 680" | 368 | bool "Palm LifeDrive" |
| 426 | default y | 369 | default y |
| 427 | depends on ARCH_PXA_PALM | 370 | depends on ARCH_PXA_PALM |
| 428 | select PXA27x | 371 | select PXA27x |
| 429 | select IWMMXT | 372 | select IWMMXT |
| 430 | help | 373 | help |
| 431 | Say Y here if you intend to run this kernel on Palm Treo 680 | 374 | Say Y here if you intend to run this kernel on a Palm LifeDrive |
| 375 | handheld computer. | ||
| 376 | |||
| 377 | config PALM_TREO | ||
| 378 | bool | ||
| 379 | depends on ARCH_PXA_PALM | ||
| 380 | |||
| 381 | config MACH_CENTRO | ||
| 382 | bool "Palm Centro 685 (GSM)" | ||
| 383 | default y | ||
| 384 | depends on ARCH_PXA_PALM | ||
| 385 | select PXA27x | ||
| 386 | select IWMMXT | ||
| 387 | select PALM_TREO | ||
| 388 | help | ||
| 389 | Say Y here if you intend to run this kernel on Palm Centro 685 (GSM) | ||
| 432 | smartphone. | 390 | smartphone. |
| 433 | 391 | ||
| 434 | config MACH_PALMLD | 392 | config MACH_TREO680 |
| 435 | bool "Palm LifeDrive" | 393 | bool "Palm Treo 680" |
| 436 | default y | 394 | default y |
| 437 | depends on ARCH_PXA_PALM | 395 | depends on ARCH_PXA_PALM |
| 438 | select PXA27x | 396 | select PXA27x |
| 439 | select IWMMXT | 397 | select IWMMXT |
| 398 | select PALM_TREO | ||
| 440 | help | 399 | help |
| 441 | Say Y here if you intend to run this kernel on a Palm LifeDrive | 400 | Say Y here if you intend to run this kernel on Palm Treo 680 |
| 401 | smartphone. | ||
| 402 | |||
| 403 | config PXA_SHARPSL | ||
| 404 | bool "SHARP Zaurus SL-5600, SL-C7xx and SL-Cxx00 Models" | ||
| 405 | select SHARP_SCOOP | ||
| 406 | select SHARP_PARAM | ||
| 407 | help | ||
| 408 | Say Y here if you intend to run this kernel on a | ||
| 409 | Sharp Zaurus SL-5600 (Poodle), SL-C700 (Corgi), | ||
| 410 | SL-C750 (Shepherd), SL-C760 (Husky), SL-C1000 (Akita), | ||
| 411 | SL-C3000 (Spitz), SL-C3100 (Borzoi) or SL-C6000x (Tosa) | ||
| 442 | handheld computer. | 412 | handheld computer. |
| 443 | 413 | ||
| 444 | config MACH_PCM990_BASEBOARD | 414 | config SHARPSL_PM |
| 445 | bool "PHYTEC PCM-990 development board" | 415 | bool |
| 446 | select HAVE_PWM | 416 | select APM_EMULATION |
| 447 | depends on MACH_PCM027 | ||
| 448 | 417 | ||
| 449 | choice | 418 | config CORGI_SSP_DEPRECATED |
| 450 | prompt "display on pcm990" | 419 | bool |
| 451 | depends on MACH_PCM990_BASEBOARD | 420 | select PXA_SSP |
| 421 | help | ||
| 422 | This option will include corgi_ssp.c and corgi_lcd.c | ||
| 423 | that corgi_ts.c and other legacy drivers (corgi_bl.c | ||
| 424 | and sharpsl_pm.c) may depend on. | ||
| 452 | 425 | ||
| 453 | config PCM990_DISPLAY_SHARP | 426 | config MACH_POODLE |
| 454 | bool "sharp lq084v1dg21 stn display" | 427 | bool "Enable Sharp SL-5600 (Poodle) Support" |
| 428 | depends on PXA_SHARPSL | ||
| 429 | select PXA25x | ||
| 430 | select SHARP_LOCOMO | ||
| 431 | select PXA_SSP | ||
| 455 | 432 | ||
| 456 | config PCM990_DISPLAY_NEC | 433 | config MACH_CORGI |
| 457 | bool "nec nl6448bc20_18d tft display" | 434 | bool "Enable Sharp SL-C700 (Corgi) Support" |
| 435 | depends on PXA_SHARPSL | ||
| 436 | select PXA25x | ||
| 437 | select PXA_SHARP_C7xx | ||
| 458 | 438 | ||
| 459 | config PCM990_DISPLAY_NONE | 439 | config MACH_SHEPHERD |
| 460 | bool "no display" | 440 | bool "Enable Sharp SL-C750 (Shepherd) Support" |
| 441 | depends on PXA_SHARPSL | ||
| 442 | select PXA25x | ||
| 443 | select PXA_SHARP_C7xx | ||
| 461 | 444 | ||
| 462 | endchoice | 445 | config MACH_HUSKY |
| 446 | bool "Enable Sharp SL-C760 (Husky) Support" | ||
| 447 | depends on PXA_SHARPSL | ||
| 448 | select PXA25x | ||
| 449 | select PXA_SHARP_C7xx | ||
| 463 | 450 | ||
| 464 | config MACH_CSB726 | 451 | config MACH_AKITA |
| 465 | bool "Enable Cogent CSB726 System On a Module" | 452 | bool "Enable Sharp SL-1000 (Akita) Support" |
| 453 | depends on PXA_SHARPSL | ||
| 466 | select PXA27x | 454 | select PXA27x |
| 467 | select IWMMXT | 455 | select PXA_SHARP_Cxx00 |
| 468 | help | 456 | select MACH_SPITZ |
| 469 | Say Y here if you intend to run this kernel on a Cogent | 457 | select I2C |
| 470 | CSB726 System On Module. | 458 | select I2C_PXA |
| 471 | 459 | ||
| 472 | config CSB726_CSB701 | 460 | config MACH_SPITZ |
| 473 | bool "Enable supprot for CSB701 baseboard" | 461 | bool "Enable Sharp Zaurus SL-3000 (Spitz) Support" |
| 474 | depends on MACH_CSB726 | 462 | depends on PXA_SHARPSL |
| 463 | select PXA27x | ||
| 464 | select PXA_SHARP_Cxx00 | ||
| 475 | 465 | ||
| 476 | config PXA_EZX | 466 | config MACH_BORZOI |
| 477 | bool "Motorola EZX Platform" | 467 | bool "Enable Sharp Zaurus SL-3100 (Borzoi) Support" |
| 468 | depends on PXA_SHARPSL | ||
| 478 | select PXA27x | 469 | select PXA27x |
| 479 | select IWMMXT | 470 | select PXA_SHARP_Cxx00 |
| 480 | select HAVE_PWM | 471 | |
| 472 | config MACH_TOSA | ||
| 473 | bool "Enable Sharp SL-6000x (Tosa) Support" | ||
| 474 | depends on PXA_SHARPSL | ||
| 475 | select PXA25x | ||
| 481 | select PXA_HAVE_BOARD_IRQS | 476 | select PXA_HAVE_BOARD_IRQS |
| 482 | 477 | ||
| 483 | config MACH_EZX_A780 | 478 | config ARCH_PXA_ESERIES |
| 484 | bool "Motorola EZX A780" | 479 | bool "PXA based Toshiba e-series PDAs" |
| 485 | default y | 480 | select PXA25x |
| 486 | depends on PXA_EZX | 481 | select PXA_HAVE_BOARD_IRQS |
| 487 | 482 | ||
| 488 | config MACH_EZX_E680 | 483 | config MACH_E330 |
| 489 | bool "Motorola EZX E680" | 484 | bool "Toshiba e330" |
| 490 | default y | 485 | default y |
| 491 | depends on PXA_EZX | 486 | depends on ARCH_PXA_ESERIES |
| 487 | help | ||
| 488 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 489 | e330 family PDA. | ||
| 492 | 490 | ||
| 493 | config MACH_EZX_A1200 | 491 | config MACH_E350 |
| 494 | bool "Motorola EZX A1200" | 492 | bool "Toshiba e350" |
| 495 | default y | 493 | default y |
| 496 | depends on PXA_EZX | 494 | depends on ARCH_PXA_ESERIES |
| 495 | help | ||
| 496 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 497 | e350 family PDA. | ||
| 497 | 498 | ||
| 498 | config MACH_EZX_A910 | 499 | config MACH_E740 |
| 499 | bool "Motorola EZX A910" | 500 | bool "Toshiba e740" |
| 500 | default y | 501 | default y |
| 501 | depends on PXA_EZX | 502 | depends on ARCH_PXA_ESERIES |
| 503 | select FB_W100 | ||
| 504 | help | ||
| 505 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 506 | e740 family PDA. | ||
| 502 | 507 | ||
| 503 | config MACH_EZX_E6 | 508 | config MACH_E750 |
| 504 | bool "Motorola EZX E6" | 509 | bool "Toshiba e750" |
| 505 | default y | 510 | default y |
| 506 | depends on PXA_EZX | 511 | depends on ARCH_PXA_ESERIES |
| 512 | select FB_W100 | ||
| 513 | help | ||
| 514 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 515 | e750 family PDA. | ||
| 507 | 516 | ||
| 508 | config MACH_EZX_E2 | 517 | config MACH_E400 |
| 509 | bool "Motorola EZX E2" | 518 | bool "Toshiba e400" |
| 510 | default y | 519 | default y |
| 511 | depends on PXA_EZX | 520 | depends on ARCH_PXA_ESERIES |
| 521 | help | ||
| 522 | Say Y here if you intend to run this kernel on a Toshiba | ||
| 523 | e400 family PDA. | ||
| 512 | 524 | ||
| 513 | config MACH_XCEP | 525 | config MACH_E800 |
| 514 | bool "Iskratel Electronics XCEP" | 526 | bool "Toshiba e800" |
| 515 | select PXA25x | 527 | default y |
| 516 | select MTD | 528 | depends on ARCH_PXA_ESERIES |
| 517 | select MTD_PARTITIONS | 529 | select FB_W100 |
| 518 | select MTD_PHYSMAP | ||
| 519 | select MTD_CFI_INTELEXT | ||
| 520 | select MTD_CFI | ||
| 521 | select MTD_CHAR | ||
| 522 | select SMC91X | ||
| 523 | select PXA_SSP | ||
| 524 | help | 530 | help |
| 525 | PXA255 based Single Board Computer with SMC 91C111 ethernet chip and 64 MB of flash. | 531 | Say Y here if you intend to run this kernel on a Toshiba |
| 526 | Tuned for usage in Libera instruments for particle accelerators. | 532 | e800 family PDA. |
| 527 | 533 | ||
| 528 | endmenu | 534 | endmenu |
| 529 | 535 | ||
| @@ -551,6 +557,42 @@ config PXA3xx | |||
| 551 | help | 557 | help |
| 552 | Select code specific to PXA3xx variants | 558 | Select code specific to PXA3xx variants |
| 553 | 559 | ||
| 560 | config CPU_PXA300 | ||
| 561 | bool | ||
| 562 | select PXA3xx | ||
| 563 | help | ||
| 564 | PXA300 (codename Monahans-L) | ||
| 565 | |||
| 566 | config CPU_PXA310 | ||
| 567 | bool | ||
| 568 | select CPU_PXA300 | ||
| 569 | help | ||
| 570 | PXA310 (codename Monahans-LV) | ||
| 571 | |||
| 572 | config CPU_PXA320 | ||
| 573 | bool | ||
| 574 | select PXA3xx | ||
| 575 | help | ||
| 576 | PXA320 (codename Monahans-P) | ||
| 577 | |||
| 578 | config CPU_PXA930 | ||
| 579 | bool | ||
| 580 | select PXA3xx | ||
| 581 | help | ||
| 582 | PXA930 (codename Tavor-P) | ||
| 583 | |||
| 584 | config CPU_PXA935 | ||
| 585 | bool | ||
| 586 | select CPU_PXA930 | ||
| 587 | help | ||
| 588 | PXA935 (codename Tavor-P65) | ||
| 589 | |||
| 590 | config CPU_PXA950 | ||
| 591 | bool | ||
| 592 | select CPU_PXA930 | ||
| 593 | help | ||
| 594 | PXA950 (codename Tavor-PV2) | ||
| 595 | |||
| 554 | config PXA_SHARP_C7xx | 596 | config PXA_SHARP_C7xx |
| 555 | bool | 597 | bool |
| 556 | select PXA_SSP | 598 | select PXA_SSP |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index f10e152bfc27..b5d29e60a341 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -24,33 +24,63 @@ obj-$(CONFIG_CPU_PXA300) += pxa300.o | |||
| 24 | obj-$(CONFIG_CPU_PXA320) += pxa320.o | 24 | obj-$(CONFIG_CPU_PXA320) += pxa320.o |
| 25 | obj-$(CONFIG_CPU_PXA930) += pxa930.o | 25 | obj-$(CONFIG_CPU_PXA930) += pxa930.o |
| 26 | 26 | ||
| 27 | # Specific board support | 27 | # NOTE: keep the order of boards in accordance to their order in Kconfig |
| 28 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | 28 | |
| 29 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o | 29 | # Intel/Marvell Dev Platforms |
| 30 | obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o | ||
| 31 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 30 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 32 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | ||
| 33 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 31 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
| 34 | obj-$(CONFIG_MACH_BALLOON3) += balloon3.o | 32 | obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o |
| 35 | obj-$(CONFIG_MACH_MP900C) += mp900.o | 33 | obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o |
| 34 | obj-$(CONFIG_MACH_LITTLETON) += littleton.o | ||
| 35 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | ||
| 36 | obj-$(CONFIG_MACH_SAAR) += saar.o | ||
| 37 | |||
| 38 | # 3rd Party Dev Platforms | ||
| 36 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 39 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
| 40 | obj-$(CONFIG_ARCH_VIPER) += viper.o | ||
| 41 | obj-$(CONFIG_MACH_BALLOON3) += balloon3.o | ||
| 42 | obj-$(CONFIG_MACH_CSB726) += csb726.o | ||
| 43 | obj-$(CONFIG_CSB726_CSB701) += csb701.o | ||
| 44 | obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o | ||
| 45 | ifeq ($(CONFIG_PCI),y) | ||
| 46 | obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o | ||
| 47 | endif | ||
| 48 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o | ||
| 49 | obj-$(CONFIG_MACH_CM_X300) += cm-x300.o | ||
| 50 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | ||
| 51 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o | ||
| 52 | obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o | ||
| 53 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o | ||
| 54 | obj-$(CONFIG_MACH_STARGATE2) += stargate2.o | ||
| 55 | obj-$(CONFIG_MACH_XCEP) += xcep.o | ||
| 37 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o | 56 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o |
| 57 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | ||
| 58 | obj-$(CONFIG_MACH_PCM027) += pcm027.o | ||
| 59 | obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o | ||
| 38 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o | 60 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o |
| 39 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o | 61 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o |
| 40 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o | 62 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o |
| 63 | |||
| 64 | # End-user Products | ||
| 65 | obj-$(CONFIG_MACH_H4700) += hx4700.o | ||
| 41 | obj-$(CONFIG_MACH_H5000) += h5000.o | 66 | obj-$(CONFIG_MACH_H5000) += h5000.o |
| 67 | obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o | ||
| 68 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o | ||
| 69 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o | ||
| 70 | obj-$(CONFIG_PXA_EZX) += ezx.o | ||
| 71 | obj-$(CONFIG_MACH_MP900C) += mp900.o | ||
| 72 | obj-$(CONFIG_MACH_PALMTE2) += palmte2.o | ||
| 73 | obj-$(CONFIG_MACH_PALMTC) += palmtc.o | ||
| 74 | obj-$(CONFIG_MACH_PALMT5) += palmt5.o | ||
| 75 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o | ||
| 76 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o | ||
| 77 | obj-$(CONFIG_MACH_PALMLD) += palmld.o | ||
| 78 | obj-$(CONFIG_PALM_TREO) += palmtreo.o | ||
| 42 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o | 79 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o |
| 43 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o | 80 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o |
| 44 | obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o | 81 | obj-$(CONFIG_CORGI_SSP_DEPRECATED) += corgi_ssp.o corgi_lcd.o |
| 45 | obj-$(CONFIG_MACH_POODLE) += poodle.o | 82 | obj-$(CONFIG_MACH_POODLE) += poodle.o |
| 46 | obj-$(CONFIG_MACH_PCM027) += pcm027.o | ||
| 47 | obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o | ||
| 48 | obj-$(CONFIG_MACH_TOSA) += tosa.o | 83 | obj-$(CONFIG_MACH_TOSA) += tosa.o |
| 49 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o | ||
| 50 | obj-$(CONFIG_MACH_H4700) += hx4700.o | ||
| 51 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o | ||
| 52 | obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o | ||
| 53 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o | ||
| 54 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o | 84 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o |
| 55 | obj-$(CONFIG_MACH_E330) += e330.o | 85 | obj-$(CONFIG_MACH_E330) += e330.o |
| 56 | obj-$(CONFIG_MACH_E350) += e350.o | 86 | obj-$(CONFIG_MACH_E350) += e350.o |
| @@ -58,34 +88,6 @@ obj-$(CONFIG_MACH_E740) += e740.o | |||
| 58 | obj-$(CONFIG_MACH_E750) += e750.o | 88 | obj-$(CONFIG_MACH_E750) += e750.o |
| 59 | obj-$(CONFIG_MACH_E400) += e400.o | 89 | obj-$(CONFIG_MACH_E400) += e400.o |
| 60 | obj-$(CONFIG_MACH_E800) += e800.o | 90 | obj-$(CONFIG_MACH_E800) += e800.o |
| 61 | obj-$(CONFIG_MACH_PALMTE2) += palmte2.o | ||
| 62 | obj-$(CONFIG_MACH_PALMTC) += palmtc.o | ||
| 63 | obj-$(CONFIG_MACH_PALMT5) += palmt5.o | ||
| 64 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o | ||
| 65 | obj-$(CONFIG_MACH_PALMLD) += palmld.o | ||
| 66 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o | ||
| 67 | obj-$(CONFIG_MACH_TREO680) += treo680.o | ||
| 68 | obj-$(CONFIG_ARCH_VIPER) += viper.o | ||
| 69 | |||
| 70 | ifeq ($(CONFIG_MACH_ZYLONITE),y) | ||
| 71 | obj-y += zylonite.o | ||
| 72 | obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o | ||
| 73 | obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o | ||
| 74 | endif | ||
| 75 | obj-$(CONFIG_MACH_LITTLETON) += littleton.o | ||
| 76 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | ||
| 77 | obj-$(CONFIG_MACH_SAAR) += saar.o | ||
| 78 | |||
| 79 | obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx.o cm-x255.o cm-x270.o | ||
| 80 | obj-$(CONFIG_MACH_CM_X300) += cm-x300.o | ||
| 81 | obj-$(CONFIG_PXA_EZX) += ezx.o | ||
| 82 | |||
| 83 | obj-$(CONFIG_MACH_XCEP) += xcep.o | ||
| 84 | |||
| 85 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o | ||
| 86 | obj-$(CONFIG_MACH_STARGATE2) += stargate2.o | ||
| 87 | obj-$(CONFIG_MACH_CSB726) += csb726.o | ||
| 88 | obj-$(CONFIG_CSB726_CSB701) += csb701.o | ||
| 89 | 91 | ||
| 90 | # Support for blinky lights | 92 | # Support for blinky lights |
| 91 | led-y := leds.o | 93 | led-y := leds.o |
| @@ -95,8 +97,4 @@ led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o | |||
| 95 | 97 | ||
| 96 | obj-$(CONFIG_LEDS) += $(led-y) | 98 | obj-$(CONFIG_LEDS) += $(led-y) |
| 97 | 99 | ||
| 98 | ifeq ($(CONFIG_PCI),y) | ||
| 99 | obj-$(CONFIG_MACH_ARMCORE) += cm-x2xx-pci.o | ||
| 100 | endif | ||
| 101 | |||
| 102 | obj-$(CONFIG_TOSA_BT) += tosa-bt.o | 100 | obj-$(CONFIG_TOSA_BT) += tosa-bt.o |
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c index f23138b8fca3..b8cd07ca9380 100644 --- a/arch/arm/mach-pxa/balloon3.c +++ b/arch/arm/mach-pxa/balloon3.c | |||
| @@ -306,6 +306,10 @@ static void __init balloon3_init(void) | |||
| 306 | */ | 306 | */ |
| 307 | ARB_CNTRL = ARB_CORE_PARK | 0x234; | 307 | ARB_CNTRL = ARB_CORE_PARK | 0x234; |
| 308 | 308 | ||
| 309 | pxa_set_ffuart_info(NULL); | ||
| 310 | pxa_set_btuart_info(NULL); | ||
| 311 | pxa_set_stuart_info(NULL); | ||
| 312 | |||
| 309 | pxa_set_i2c_info(NULL); | 313 | pxa_set_i2c_info(NULL); |
| 310 | if (balloon3_has(BALLOON3_FEATURE_AUDIO)) | 314 | if (balloon3_has(BALLOON3_FEATURE_AUDIO)) |
| 311 | pxa_set_ac97_info(NULL); | 315 | pxa_set_ac97_info(NULL); |
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index b50ef39eabfc..bff6e78f033d 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
| @@ -453,6 +453,10 @@ static inline void cmx2xx_init_ac97(void) {} | |||
| 453 | 453 | ||
| 454 | static void __init cmx2xx_init(void) | 454 | static void __init cmx2xx_init(void) |
| 455 | { | 455 | { |
| 456 | pxa_set_ffuart_info(NULL); | ||
| 457 | pxa_set_btuart_info(NULL); | ||
| 458 | pxa_set_stuart_info(NULL); | ||
| 459 | |||
| 456 | cmx2xx_pm_init(); | 460 | cmx2xx_pm_init(); |
| 457 | 461 | ||
| 458 | if (cpu_is_pxa25x()) | 462 | if (cpu_is_pxa25x()) |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index 102916f1e465..d37cfa132a65 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
| @@ -3,9 +3,10 @@ | |||
| 3 | * | 3 | * |
| 4 | * Support for the CompuLab CM-X300 modules | 4 | * Support for the CompuLab CM-X300 modules |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2008 CompuLab Ltd. | 6 | * Copyright (C) 2008,2009 CompuLab Ltd. |
| 7 | * | 7 | * |
| 8 | * Mike Rapoport <mike@compulab.co.il> | 8 | * Mike Rapoport <mike@compulab.co.il> |
| 9 | * Igor Grinberg <grinberg@compulab.co.il> | ||
| 9 | * | 10 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| @@ -16,30 +17,41 @@ | |||
| 16 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 17 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
| 18 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/delay.h> | ||
| 19 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 20 | 22 | ||
| 21 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 22 | #include <linux/dm9000.h> | 24 | #include <linux/dm9000.h> |
| 23 | #include <linux/leds.h> | 25 | #include <linux/leds.h> |
| 24 | #include <linux/rtc-v3020.h> | 26 | #include <linux/rtc-v3020.h> |
| 27 | #include <linux/pwm_backlight.h> | ||
| 25 | 28 | ||
| 26 | #include <linux/i2c.h> | 29 | #include <linux/i2c.h> |
| 27 | #include <linux/i2c/pca953x.h> | 30 | #include <linux/i2c/pca953x.h> |
| 28 | 31 | ||
| 32 | #include <linux/mfd/da903x.h> | ||
| 33 | |||
| 34 | #include <linux/spi/spi.h> | ||
| 35 | #include <linux/spi/spi_gpio.h> | ||
| 36 | #include <linux/spi/tdo24m.h> | ||
| 37 | |||
| 29 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 30 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
| 31 | #include <asm/setup.h> | 40 | #include <asm/setup.h> |
| 32 | 41 | ||
| 33 | #include <mach/pxa300.h> | 42 | #include <mach/pxa300.h> |
| 43 | #include <mach/pxa27x-udc.h> | ||
| 34 | #include <mach/pxafb.h> | 44 | #include <mach/pxafb.h> |
| 35 | #include <mach/mmc.h> | 45 | #include <mach/mmc.h> |
| 36 | #include <mach/ohci.h> | 46 | #include <mach/ohci.h> |
| 37 | #include <plat/i2c.h> | 47 | #include <plat/i2c.h> |
| 38 | #include <mach/pxa3xx_nand.h> | 48 | #include <plat/pxa3xx_nand.h> |
| 49 | #include <mach/audio.h> | ||
| 39 | 50 | ||
| 40 | #include <asm/mach/map.h> | 51 | #include <asm/mach/map.h> |
| 41 | 52 | ||
| 42 | #include "generic.h" | 53 | #include "generic.h" |
| 54 | #include "devices.h" | ||
| 43 | 55 | ||
| 44 | #define CM_X300_ETH_PHYS 0x08000010 | 56 | #define CM_X300_ETH_PHYS 0x08000010 |
| 45 | 57 | ||
| @@ -53,7 +65,7 @@ | |||
| 53 | #define GPIO97_RTC_RD (97) | 65 | #define GPIO97_RTC_RD (97) |
| 54 | #define GPIO98_RTC_IO (98) | 66 | #define GPIO98_RTC_IO (98) |
| 55 | 67 | ||
| 56 | static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { | 68 | static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = { |
| 57 | /* LCD */ | 69 | /* LCD */ |
| 58 | GPIO54_LCD_LDD_0, | 70 | GPIO54_LCD_LDD_0, |
| 59 | GPIO55_LCD_LDD_1, | 71 | GPIO55_LCD_LDD_1, |
| @@ -137,7 +149,6 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { | |||
| 137 | GPIO36_UART1_DTR, | 149 | GPIO36_UART1_DTR, |
| 138 | 150 | ||
| 139 | /* GPIOs */ | 151 | /* GPIOs */ |
| 140 | GPIO79_GPIO, /* LED */ | ||
| 141 | GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ | 152 | GPIO82_GPIO | MFP_PULL_HIGH, /* MMC CD */ |
| 142 | GPIO85_GPIO, /* MMC WP */ | 153 | GPIO85_GPIO, /* MMC WP */ |
| 143 | GPIO99_GPIO, /* Ethernet IRQ */ | 154 | GPIO99_GPIO, /* Ethernet IRQ */ |
| @@ -151,6 +162,50 @@ static mfp_cfg_t cm_x300_mfp_cfg[] __initdata = { | |||
| 151 | /* Standard I2C */ | 162 | /* Standard I2C */ |
| 152 | GPIO21_I2C_SCL, | 163 | GPIO21_I2C_SCL, |
| 153 | GPIO22_I2C_SDA, | 164 | GPIO22_I2C_SDA, |
| 165 | |||
| 166 | /* PWM Backlight */ | ||
| 167 | GPIO19_PWM2_OUT, | ||
| 168 | }; | ||
| 169 | |||
| 170 | static mfp_cfg_t cm_x3xx_rev_lt130_mfp_cfg[] __initdata = { | ||
| 171 | /* GPIOs */ | ||
| 172 | GPIO79_GPIO, /* LED */ | ||
| 173 | GPIO77_GPIO, /* WiFi reset */ | ||
| 174 | GPIO78_GPIO, /* BT reset */ | ||
| 175 | }; | ||
| 176 | |||
| 177 | static mfp_cfg_t cm_x3xx_rev_ge130_mfp_cfg[] __initdata = { | ||
| 178 | /* GPIOs */ | ||
| 179 | GPIO76_GPIO, /* LED */ | ||
| 180 | GPIO71_GPIO, /* WiFi reset */ | ||
| 181 | GPIO70_GPIO, /* BT reset */ | ||
| 182 | }; | ||
| 183 | |||
| 184 | static mfp_cfg_t cm_x310_mfp_cfg[] __initdata = { | ||
| 185 | /* USB PORT 2 */ | ||
| 186 | ULPI_STP, | ||
| 187 | ULPI_NXT, | ||
| 188 | ULPI_DIR, | ||
| 189 | GPIO30_ULPI_DATA_OUT_0, | ||
| 190 | GPIO31_ULPI_DATA_OUT_1, | ||
| 191 | GPIO32_ULPI_DATA_OUT_2, | ||
| 192 | GPIO33_ULPI_DATA_OUT_3, | ||
| 193 | GPIO34_ULPI_DATA_OUT_4, | ||
| 194 | GPIO35_ULPI_DATA_OUT_5, | ||
| 195 | GPIO36_ULPI_DATA_OUT_6, | ||
| 196 | GPIO37_ULPI_DATA_OUT_7, | ||
| 197 | GPIO38_ULPI_CLK, | ||
| 198 | /* external PHY reset pin */ | ||
| 199 | GPIO127_GPIO, | ||
| 200 | |||
| 201 | /* USB PORT 3 */ | ||
| 202 | GPIO77_USB_P3_1, | ||
| 203 | GPIO78_USB_P3_2, | ||
| 204 | GPIO79_USB_P3_3, | ||
| 205 | GPIO80_USB_P3_4, | ||
| 206 | GPIO81_USB_P3_5, | ||
| 207 | GPIO82_USB_P3_6, | ||
| 208 | GPIO0_2_USBH_PEN, | ||
| 154 | }; | 209 | }; |
| 155 | 210 | ||
| 156 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | 211 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
| @@ -195,17 +250,18 @@ static void __init cm_x300_init_dm9000(void) | |||
| 195 | static inline void cm_x300_init_dm9000(void) {} | 250 | static inline void cm_x300_init_dm9000(void) {} |
| 196 | #endif | 251 | #endif |
| 197 | 252 | ||
| 253 | /* LCD */ | ||
| 198 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 254 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 199 | static struct pxafb_mode_info cm_x300_lcd_modes[] = { | 255 | static struct pxafb_mode_info cm_x300_lcd_modes[] = { |
| 200 | [0] = { | 256 | [0] = { |
| 201 | .pixclock = 38000, | 257 | .pixclock = 38250, |
| 202 | .bpp = 16, | 258 | .bpp = 16, |
| 203 | .xres = 480, | 259 | .xres = 480, |
| 204 | .yres = 640, | 260 | .yres = 640, |
| 205 | .hsync_len = 8, | 261 | .hsync_len = 8, |
| 206 | .vsync_len = 2, | 262 | .vsync_len = 2, |
| 207 | .left_margin = 8, | 263 | .left_margin = 8, |
| 208 | .upper_margin = 0, | 264 | .upper_margin = 2, |
| 209 | .right_margin = 24, | 265 | .right_margin = 24, |
| 210 | .lower_margin = 4, | 266 | .lower_margin = 4, |
| 211 | .cmap_greyscale = 0, | 267 | .cmap_greyscale = 0, |
| @@ -227,7 +283,7 @@ static struct pxafb_mode_info cm_x300_lcd_modes[] = { | |||
| 227 | 283 | ||
| 228 | static struct pxafb_mach_info cm_x300_lcd = { | 284 | static struct pxafb_mach_info cm_x300_lcd = { |
| 229 | .modes = cm_x300_lcd_modes, | 285 | .modes = cm_x300_lcd_modes, |
| 230 | .num_modes = 2, | 286 | .num_modes = ARRAY_SIZE(cm_x300_lcd_modes), |
| 231 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | 287 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
| 232 | }; | 288 | }; |
| 233 | 289 | ||
| @@ -239,6 +295,87 @@ static void __init cm_x300_init_lcd(void) | |||
| 239 | static inline void cm_x300_init_lcd(void) {} | 295 | static inline void cm_x300_init_lcd(void) {} |
| 240 | #endif | 296 | #endif |
| 241 | 297 | ||
| 298 | #if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE) | ||
| 299 | static struct platform_pwm_backlight_data cm_x300_backlight_data = { | ||
| 300 | .pwm_id = 2, | ||
| 301 | .max_brightness = 100, | ||
| 302 | .dft_brightness = 100, | ||
| 303 | .pwm_period_ns = 10000, | ||
| 304 | }; | ||
| 305 | |||
| 306 | static struct platform_device cm_x300_backlight_device = { | ||
| 307 | .name = "pwm-backlight", | ||
| 308 | .dev = { | ||
| 309 | .parent = &pxa27x_device_pwm0.dev, | ||
| 310 | .platform_data = &cm_x300_backlight_data, | ||
| 311 | }, | ||
| 312 | }; | ||
| 313 | |||
| 314 | static void cm_x300_init_bl(void) | ||
| 315 | { | ||
| 316 | platform_device_register(&cm_x300_backlight_device); | ||
| 317 | } | ||
| 318 | #else | ||
| 319 | static inline void cm_x300_init_bl(void) {} | ||
| 320 | #endif | ||
| 321 | |||
| 322 | #if defined(CONFIG_SPI_GPIO) || defined(CONFIG_SPI_GPIO_MODULE) | ||
| 323 | #define GPIO_LCD_BASE (144) | ||
| 324 | #define GPIO_LCD_DIN (GPIO_LCD_BASE + 8) /* aux_gpio3_0 */ | ||
| 325 | #define GPIO_LCD_DOUT (GPIO_LCD_BASE + 9) /* aux_gpio3_1 */ | ||
| 326 | #define GPIO_LCD_SCL (GPIO_LCD_BASE + 10) /* aux_gpio3_2 */ | ||
| 327 | #define GPIO_LCD_CS (GPIO_LCD_BASE + 11) /* aux_gpio3_3 */ | ||
| 328 | #define LCD_SPI_BUS_NUM (1) | ||
| 329 | |||
| 330 | static struct spi_gpio_platform_data cm_x300_spi_gpio_pdata = { | ||
| 331 | .sck = GPIO_LCD_SCL, | ||
| 332 | .mosi = GPIO_LCD_DIN, | ||
| 333 | .miso = GPIO_LCD_DOUT, | ||
| 334 | .num_chipselect = 1, | ||
| 335 | }; | ||
| 336 | |||
| 337 | static struct platform_device cm_x300_spi_gpio = { | ||
| 338 | .name = "spi_gpio", | ||
| 339 | .id = LCD_SPI_BUS_NUM, | ||
| 340 | .dev = { | ||
| 341 | .platform_data = &cm_x300_spi_gpio_pdata, | ||
| 342 | }, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static struct tdo24m_platform_data cm_x300_tdo24m_pdata = { | ||
| 346 | .model = TDO35S, | ||
| 347 | }; | ||
| 348 | |||
| 349 | static struct spi_board_info cm_x300_spi_devices[] __initdata = { | ||
| 350 | { | ||
| 351 | .modalias = "tdo24m", | ||
| 352 | .max_speed_hz = 1000000, | ||
| 353 | .bus_num = LCD_SPI_BUS_NUM, | ||
| 354 | .chip_select = 0, | ||
| 355 | .controller_data = (void *) GPIO_LCD_CS, | ||
| 356 | .platform_data = &cm_x300_tdo24m_pdata, | ||
| 357 | }, | ||
| 358 | }; | ||
| 359 | |||
| 360 | static void __init cm_x300_init_spi(void) | ||
| 361 | { | ||
| 362 | spi_register_board_info(cm_x300_spi_devices, | ||
| 363 | ARRAY_SIZE(cm_x300_spi_devices)); | ||
| 364 | platform_device_register(&cm_x300_spi_gpio); | ||
| 365 | } | ||
| 366 | #else | ||
| 367 | static inline void cm_x300_init_spi(void) {} | ||
| 368 | #endif | ||
| 369 | |||
| 370 | #if defined(CONFIG_SND_PXA2XX_LIB_AC97) | ||
| 371 | static void __init cm_x300_init_ac97(void) | ||
| 372 | { | ||
| 373 | pxa_set_ac97_info(NULL); | ||
| 374 | } | ||
| 375 | #else | ||
| 376 | static inline void cm_x300_init_ac97(void) {} | ||
| 377 | #endif | ||
| 378 | |||
| 242 | #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) | 379 | #if defined(CONFIG_MTD_NAND_PXA3xx) || defined(CONFIG_MTD_NAND_PXA3xx_MODULE) |
| 243 | static struct mtd_partition cm_x300_nand_partitions[] = { | 380 | static struct mtd_partition cm_x300_nand_partitions[] = { |
| 244 | [0] = { | 381 | [0] = { |
| @@ -333,9 +470,19 @@ static inline void cm_x300_init_mmc(void) {} | |||
| 333 | #endif | 470 | #endif |
| 334 | 471 | ||
| 335 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 472 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 473 | static int cm_x300_ohci_init(struct device *dev) | ||
| 474 | { | ||
| 475 | if (cpu_is_pxa300()) | ||
| 476 | UP2OCR = UP2OCR_HXS | ||
| 477 | | UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE; | ||
| 478 | |||
| 479 | return 0; | ||
| 480 | } | ||
| 481 | |||
| 336 | static struct pxaohci_platform_data cm_x300_ohci_platform_data = { | 482 | static struct pxaohci_platform_data cm_x300_ohci_platform_data = { |
| 337 | .port_mode = PMM_PERPORT_MODE, | 483 | .port_mode = PMM_PERPORT_MODE, |
| 338 | .flags = ENABLE_PORT1 | ENABLE_PORT2 | POWER_CONTROL_LOW, | 484 | .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW, |
| 485 | .init = cm_x300_ohci_init, | ||
| 339 | }; | 486 | }; |
| 340 | 487 | ||
| 341 | static void __init cm_x300_init_ohci(void) | 488 | static void __init cm_x300_init_ohci(void) |
| @@ -351,7 +498,6 @@ static struct gpio_led cm_x300_leds[] = { | |||
| 351 | [0] = { | 498 | [0] = { |
| 352 | .name = "cm-x300:green", | 499 | .name = "cm-x300:green", |
| 353 | .default_trigger = "heartbeat", | 500 | .default_trigger = "heartbeat", |
| 354 | .gpio = 79, | ||
| 355 | .active_low = 1, | 501 | .active_low = 1, |
| 356 | }, | 502 | }, |
| 357 | }; | 503 | }; |
| @@ -371,6 +517,11 @@ static struct platform_device cm_x300_led_device = { | |||
| 371 | 517 | ||
| 372 | static void __init cm_x300_init_leds(void) | 518 | static void __init cm_x300_init_leds(void) |
| 373 | { | 519 | { |
| 520 | if (system_rev < 130) | ||
| 521 | cm_x300_leds[0].gpio = 79; | ||
| 522 | else | ||
| 523 | cm_x300_leds[0].gpio = 76; | ||
| 524 | |||
| 374 | platform_device_register(&cm_x300_led_device); | 525 | platform_device_register(&cm_x300_led_device); |
| 375 | } | 526 | } |
| 376 | #else | 527 | #else |
| @@ -433,11 +584,94 @@ static void __init cm_x300_init_rtc(void) | |||
| 433 | static inline void cm_x300_init_rtc(void) {} | 584 | static inline void cm_x300_init_rtc(void) {} |
| 434 | #endif | 585 | #endif |
| 435 | 586 | ||
| 436 | static void __init cm_x300_init(void) | 587 | /* DA9030 */ |
| 588 | struct da903x_subdev_info cm_x300_da9030_subdevs[] = { | ||
| 589 | { | ||
| 590 | .name = "da903x-backlight", | ||
| 591 | .id = DA9030_ID_WLED, | ||
| 592 | } | ||
| 593 | }; | ||
| 594 | |||
| 595 | static struct da903x_platform_data cm_x300_da9030_info = { | ||
| 596 | .num_subdevs = ARRAY_SIZE(cm_x300_da9030_subdevs), | ||
| 597 | .subdevs = cm_x300_da9030_subdevs, | ||
| 598 | }; | ||
| 599 | |||
| 600 | static struct i2c_board_info cm_x300_pmic_info = { | ||
| 601 | I2C_BOARD_INFO("da9030", 0x49), | ||
| 602 | .irq = IRQ_GPIO(0), | ||
| 603 | .platform_data = &cm_x300_da9030_info, | ||
| 604 | }; | ||
| 605 | |||
| 606 | static struct i2c_pxa_platform_data cm_x300_pwr_i2c_info = { | ||
| 607 | .use_pio = 1, | ||
| 608 | }; | ||
| 609 | |||
| 610 | static void __init cm_x300_init_da9030(void) | ||
| 611 | { | ||
| 612 | pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); | ||
| 613 | i2c_register_board_info(1, &cm_x300_pmic_info, 1); | ||
| 614 | } | ||
| 615 | |||
| 616 | static void __init cm_x300_init_wi2wi(void) | ||
| 617 | { | ||
| 618 | int bt_reset, wlan_en; | ||
| 619 | int err; | ||
| 620 | |||
| 621 | if (system_rev < 130) { | ||
| 622 | wlan_en = 77; | ||
| 623 | bt_reset = 78; | ||
| 624 | } else { | ||
| 625 | wlan_en = 71; | ||
| 626 | bt_reset = 70; | ||
| 627 | } | ||
| 628 | |||
| 629 | /* Libertas and CSR reset */ | ||
| 630 | err = gpio_request(wlan_en, "wlan en"); | ||
| 631 | if (err) { | ||
| 632 | pr_err("CM-X300: failed to request wlan en gpio: %d\n", err); | ||
| 633 | } else { | ||
| 634 | gpio_direction_output(wlan_en, 1); | ||
| 635 | gpio_free(wlan_en); | ||
| 636 | } | ||
| 637 | |||
| 638 | err = gpio_request(bt_reset, "bt reset"); | ||
| 639 | if (err) { | ||
| 640 | pr_err("CM-X300: failed to request bt reset gpio: %d\n", err); | ||
| 641 | } else { | ||
| 642 | gpio_direction_output(bt_reset, 1); | ||
| 643 | udelay(10); | ||
| 644 | gpio_set_value(bt_reset, 0); | ||
| 645 | udelay(10); | ||
| 646 | gpio_set_value(bt_reset, 1); | ||
| 647 | gpio_free(bt_reset); | ||
| 648 | } | ||
| 649 | } | ||
| 650 | |||
| 651 | /* MFP */ | ||
| 652 | static void __init cm_x300_init_mfp(void) | ||
| 437 | { | 653 | { |
| 438 | /* board-processor specific GPIO initialization */ | 654 | /* board-processor specific GPIO initialization */ |
| 439 | pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x300_mfp_cfg)); | 655 | pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_mfp_cfg)); |
| 656 | |||
| 657 | if (system_rev < 130) | ||
| 658 | pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_lt130_mfp_cfg)); | ||
| 659 | else | ||
| 660 | pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x3xx_rev_ge130_mfp_cfg)); | ||
| 661 | |||
| 662 | if (cpu_is_pxa310()) | ||
| 663 | pxa3xx_mfp_config(ARRAY_AND_SIZE(cm_x310_mfp_cfg)); | ||
| 664 | } | ||
| 665 | |||
| 666 | static void __init cm_x300_init(void) | ||
| 667 | { | ||
| 668 | cm_x300_init_mfp(); | ||
| 669 | |||
| 670 | pxa_set_ffuart_info(NULL); | ||
| 671 | pxa_set_btuart_info(NULL); | ||
| 672 | pxa_set_stuart_info(NULL); | ||
| 440 | 673 | ||
| 674 | cm_x300_init_da9030(); | ||
| 441 | cm_x300_init_dm9000(); | 675 | cm_x300_init_dm9000(); |
| 442 | cm_x300_init_lcd(); | 676 | cm_x300_init_lcd(); |
| 443 | cm_x300_init_ohci(); | 677 | cm_x300_init_ohci(); |
| @@ -445,7 +679,11 @@ static void __init cm_x300_init(void) | |||
| 445 | cm_x300_init_nand(); | 679 | cm_x300_init_nand(); |
| 446 | cm_x300_init_leds(); | 680 | cm_x300_init_leds(); |
| 447 | cm_x300_init_i2c(); | 681 | cm_x300_init_i2c(); |
| 682 | cm_x300_init_spi(); | ||
| 448 | cm_x300_init_rtc(); | 683 | cm_x300_init_rtc(); |
| 684 | cm_x300_init_ac97(); | ||
| 685 | cm_x300_init_wi2wi(); | ||
| 686 | cm_x300_init_bl(); | ||
| 449 | } | 687 | } |
| 450 | 688 | ||
| 451 | static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, | 689 | static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags, |
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c index 01bcfaae75bc..061c45316de8 100644 --- a/arch/arm/mach-pxa/colibri-pxa270.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c | |||
| @@ -130,6 +130,9 @@ static struct platform_device *colibri_pxa270_devices[] __initdata = { | |||
| 130 | static void __init colibri_pxa270_init(void) | 130 | static void __init colibri_pxa270_init(void) |
| 131 | { | 131 | { |
| 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); | 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); |
| 133 | pxa_set_ffuart_info(NULL); | ||
| 134 | pxa_set_btuart_info(NULL); | ||
| 135 | pxa_set_stuart_info(NULL); | ||
| 133 | platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); | 136 | platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); |
| 134 | } | 137 | } |
| 135 | 138 | ||
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c index 37c239c56568..45c23fd6df31 100644 --- a/arch/arm/mach-pxa/colibri-pxa300.c +++ b/arch/arm/mach-pxa/colibri-pxa300.c | |||
| @@ -170,6 +170,10 @@ static inline void colibri_pxa310_init_ac97(void) {} | |||
| 170 | 170 | ||
| 171 | void __init colibri_pxa300_init(void) | 171 | void __init colibri_pxa300_init(void) |
| 172 | { | 172 | { |
| 173 | pxa_set_ffuart_info(NULL); | ||
| 174 | pxa_set_btuart_info(NULL); | ||
| 175 | pxa_set_stuart_info(NULL); | ||
| 176 | |||
| 173 | colibri_pxa300_init_eth(); | 177 | colibri_pxa300_init_eth(); |
| 174 | colibri_pxa300_init_ohci(); | 178 | colibri_pxa300_init_ohci(); |
| 175 | colibri_pxa3xx_init_nand(); | 179 | colibri_pxa3xx_init_nand(); |
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c index ec0e14b96682..ae835fad7d10 100644 --- a/arch/arm/mach-pxa/colibri-pxa320.c +++ b/arch/arm/mach-pxa/colibri-pxa320.c | |||
| @@ -199,6 +199,10 @@ static void __init colibri_pxa320_init_uart(void) | |||
| 199 | 199 | ||
| 200 | void __init colibri_pxa320_init(void) | 200 | void __init colibri_pxa320_init(void) |
| 201 | { | 201 | { |
| 202 | pxa_set_ffuart_info(NULL); | ||
| 203 | pxa_set_btuart_info(NULL); | ||
| 204 | pxa_set_stuart_info(NULL); | ||
| 205 | |||
| 202 | colibri_pxa320_init_eth(); | 206 | colibri_pxa320_init_eth(); |
| 203 | colibri_pxa320_init_ohci(); | 207 | colibri_pxa320_init_ohci(); |
| 204 | colibri_pxa3xx_init_nand(); | 208 | colibri_pxa3xx_init_nand(); |
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c index efebaf4d734d..e6c0a2287eb8 100644 --- a/arch/arm/mach-pxa/colibri-pxa3xx.c +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c | |||
| @@ -25,7 +25,7 @@ | |||
| 25 | #include <mach/colibri.h> | 25 | #include <mach/colibri.h> |
| 26 | #include <mach/mmc.h> | 26 | #include <mach/mmc.h> |
| 27 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
| 28 | #include <mach/pxa3xx_nand.h> | 28 | #include <plat/pxa3xx_nand.h> |
| 29 | 29 | ||
| 30 | #include "generic.h" | 30 | #include "generic.h" |
| 31 | #include "devices.h" | 31 | #include "devices.h" |
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index b536b5a5a10d..74446cf8ae69 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
| @@ -671,6 +671,10 @@ static void __init corgi_init(void) | |||
| 671 | 671 | ||
| 672 | pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config)); | 672 | pxa2xx_mfp_config(ARRAY_AND_SIZE(corgi_pin_config)); |
| 673 | 673 | ||
| 674 | pxa_set_ffuart_info(NULL); | ||
| 675 | pxa_set_btuart_info(NULL); | ||
| 676 | pxa_set_stuart_info(NULL); | ||
| 677 | |||
| 674 | corgi_init_spi(); | 678 | corgi_init_spi(); |
| 675 | 679 | ||
| 676 | pxa_set_udc_info(&udc_info); | 680 | pxa_set_udc_info(&udc_info); |
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index a093282fe4db..d4a0733e905b 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c | |||
| @@ -214,8 +214,8 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = { | |||
| 214 | .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, | 214 | .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, |
| 215 | .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, | 215 | .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, |
| 216 | .bat_levels = 40, | 216 | .bat_levels = 40, |
| 217 | .bat_levels_noac = spitz_battery_levels_noac, | 217 | .bat_levels_noac = sharpsl_battery_levels_noac, |
| 218 | .bat_levels_acin = spitz_battery_levels_acin, | 218 | .bat_levels_acin = sharpsl_battery_levels_acin, |
| 219 | .status_high_acin = 188, | 219 | .status_high_acin = 188, |
| 220 | .status_low_acin = 178, | 220 | .status_low_acin = 178, |
| 221 | .status_high_noac = 185, | 221 | .status_high_noac = 185, |
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c index 965480eb4fe6..88575b87bd33 100644 --- a/arch/arm/mach-pxa/csb726.c +++ b/arch/arm/mach-pxa/csb726.c | |||
| @@ -268,6 +268,9 @@ static void __init csb726_init(void) | |||
| 268 | /* MSC2 = 0x06697ff4; *//* none/SM501 */ | 268 | /* MSC2 = 0x06697ff4; *//* none/SM501 */ |
| 269 | MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ | 269 | MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ |
| 270 | 270 | ||
| 271 | pxa_set_ffuart_info(NULL); | ||
| 272 | pxa_set_btuart_info(NULL); | ||
| 273 | pxa_set_stuart_info(NULL); | ||
| 271 | pxa_set_i2c_info(NULL); | 274 | pxa_set_i2c_info(NULL); |
| 272 | pxa27x_set_i2c_power_info(NULL); | 275 | pxa27x_set_i2c_power_info(NULL); |
| 273 | pxa_set_mci_info(&csb726_mci); | 276 | pxa_set_mci_info(&csb726_mci); |
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 46fabe1cca11..3395463bb5a6 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
| @@ -4,17 +4,18 @@ | |||
| 4 | #include <linux/platform_device.h> | 4 | #include <linux/platform_device.h> |
| 5 | #include <linux/dma-mapping.h> | 5 | #include <linux/dma-mapping.h> |
| 6 | 6 | ||
| 7 | #include <mach/hardware.h> | ||
| 7 | #include <mach/udc.h> | 8 | #include <mach/udc.h> |
| 8 | #include <mach/pxafb.h> | 9 | #include <mach/pxafb.h> |
| 9 | #include <mach/mmc.h> | 10 | #include <mach/mmc.h> |
| 10 | #include <mach/irda.h> | 11 | #include <mach/irda.h> |
| 11 | #include <plat/i2c.h> | ||
| 12 | #include <mach/ohci.h> | 12 | #include <mach/ohci.h> |
| 13 | #include <mach/pxa27x_keypad.h> | 13 | #include <mach/pxa27x_keypad.h> |
| 14 | #include <mach/pxa2xx_spi.h> | 14 | #include <mach/pxa2xx_spi.h> |
| 15 | #include <mach/camera.h> | 15 | #include <mach/camera.h> |
| 16 | #include <mach/audio.h> | 16 | #include <mach/audio.h> |
| 17 | #include <mach/pxa3xx_nand.h> | 17 | #include <plat/i2c.h> |
| 18 | #include <plat/pxa3xx_nand.h> | ||
| 18 | 19 | ||
| 19 | #include "devices.h" | 20 | #include "devices.h" |
| 20 | #include "generic.h" | 21 | #include "generic.h" |
| @@ -167,13 +168,18 @@ static struct resource pxa_resource_ffuart[] = { | |||
| 167 | } | 168 | } |
| 168 | }; | 169 | }; |
| 169 | 170 | ||
| 170 | struct platform_device pxa_device_ffuart= { | 171 | struct platform_device pxa_device_ffuart = { |
| 171 | .name = "pxa2xx-uart", | 172 | .name = "pxa2xx-uart", |
| 172 | .id = 0, | 173 | .id = 0, |
| 173 | .resource = pxa_resource_ffuart, | 174 | .resource = pxa_resource_ffuart, |
| 174 | .num_resources = ARRAY_SIZE(pxa_resource_ffuart), | 175 | .num_resources = ARRAY_SIZE(pxa_resource_ffuart), |
| 175 | }; | 176 | }; |
| 176 | 177 | ||
| 178 | void __init pxa_set_ffuart_info(void *info) | ||
| 179 | { | ||
| 180 | pxa_register_device(&pxa_device_ffuart, info); | ||
| 181 | } | ||
| 182 | |||
| 177 | static struct resource pxa_resource_btuart[] = { | 183 | static struct resource pxa_resource_btuart[] = { |
| 178 | { | 184 | { |
| 179 | .start = 0x40200000, | 185 | .start = 0x40200000, |
| @@ -193,6 +199,11 @@ struct platform_device pxa_device_btuart = { | |||
| 193 | .num_resources = ARRAY_SIZE(pxa_resource_btuart), | 199 | .num_resources = ARRAY_SIZE(pxa_resource_btuart), |
| 194 | }; | 200 | }; |
| 195 | 201 | ||
| 202 | void __init pxa_set_btuart_info(void *info) | ||
| 203 | { | ||
| 204 | pxa_register_device(&pxa_device_btuart, info); | ||
| 205 | } | ||
| 206 | |||
| 196 | static struct resource pxa_resource_stuart[] = { | 207 | static struct resource pxa_resource_stuart[] = { |
| 197 | { | 208 | { |
| 198 | .start = 0x40700000, | 209 | .start = 0x40700000, |
| @@ -212,6 +223,11 @@ struct platform_device pxa_device_stuart = { | |||
| 212 | .num_resources = ARRAY_SIZE(pxa_resource_stuart), | 223 | .num_resources = ARRAY_SIZE(pxa_resource_stuart), |
| 213 | }; | 224 | }; |
| 214 | 225 | ||
| 226 | void __init pxa_set_stuart_info(void *info) | ||
| 227 | { | ||
| 228 | pxa_register_device(&pxa_device_stuart, info); | ||
| 229 | } | ||
| 230 | |||
| 215 | static struct resource pxa_resource_hwuart[] = { | 231 | static struct resource pxa_resource_hwuart[] = { |
| 216 | { | 232 | { |
| 217 | .start = 0x41600000, | 233 | .start = 0x41600000, |
| @@ -231,6 +247,14 @@ struct platform_device pxa_device_hwuart = { | |||
| 231 | .num_resources = ARRAY_SIZE(pxa_resource_hwuart), | 247 | .num_resources = ARRAY_SIZE(pxa_resource_hwuart), |
| 232 | }; | 248 | }; |
| 233 | 249 | ||
| 250 | void __init pxa_set_hwuart_info(void *info) | ||
| 251 | { | ||
| 252 | if (cpu_is_pxa255()) | ||
| 253 | pxa_register_device(&pxa_device_hwuart, info); | ||
| 254 | else | ||
| 255 | pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware"); | ||
| 256 | } | ||
| 257 | |||
| 234 | static struct resource pxai2c_resources[] = { | 258 | static struct resource pxai2c_resources[] = { |
| 235 | { | 259 | { |
| 236 | .start = 0x40301680, | 260 | .start = 0x40301680, |
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index 74d3f8987c5c..8fde3387279d 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c | |||
| @@ -55,6 +55,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 55 | 55 | ||
| 56 | static void __init e330_init(void) | 56 | static void __init e330_init(void) |
| 57 | { | 57 | { |
| 58 | pxa_set_ffuart_info(NULL); | ||
| 59 | pxa_set_btuart_info(NULL); | ||
| 60 | pxa_set_stuart_info(NULL); | ||
| 58 | eseries_register_clks(); | 61 | eseries_register_clks(); |
| 59 | eseries_get_tmio_gpios(); | 62 | eseries_get_tmio_gpios(); |
| 60 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 63 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index 080036272131..f50f055f5720 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c | |||
| @@ -56,6 +56,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 56 | 56 | ||
| 57 | static void __init e350_init(void) | 57 | static void __init e350_init(void) |
| 58 | { | 58 | { |
| 59 | pxa_set_ffuart_info(NULL); | ||
| 60 | pxa_set_btuart_info(NULL); | ||
| 61 | pxa_set_stuart_info(NULL); | ||
| 59 | eseries_register_clks(); | 62 | eseries_register_clks(); |
| 60 | eseries_get_tmio_gpios(); | 63 | eseries_get_tmio_gpios(); |
| 61 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 64 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index ed9c0c3f64a2..55b950f12844 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c | |||
| @@ -130,6 +130,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 130 | static void __init e400_init(void) | 130 | static void __init e400_init(void) |
| 131 | { | 131 | { |
| 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); | 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config)); |
| 133 | pxa_set_ffuart_info(NULL); | ||
| 134 | pxa_set_btuart_info(NULL); | ||
| 135 | pxa_set_stuart_info(NULL); | ||
| 133 | /* Fixme - e400 may have a switched clock */ | 136 | /* Fixme - e400 may have a switched clock */ |
| 134 | eseries_register_clks(); | 137 | eseries_register_clks(); |
| 135 | eseries_get_tmio_gpios(); | 138 | eseries_get_tmio_gpios(); |
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index 49acdfa6650d..94b23a9e3877 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c | |||
| @@ -192,6 +192,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 192 | static void __init e740_init(void) | 192 | static void __init e740_init(void) |
| 193 | { | 193 | { |
| 194 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); | 194 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); |
| 195 | pxa_set_ffuart_info(NULL); | ||
| 196 | pxa_set_btuart_info(NULL); | ||
| 197 | pxa_set_stuart_info(NULL); | ||
| 195 | eseries_register_clks(); | 198 | eseries_register_clks(); |
| 196 | clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, | 199 | clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, |
| 197 | "UDCCLK", &pxa25x_device_udc.dev), | 200 | "UDCCLK", &pxa25x_device_udc.dev), |
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index 4052ece3ef49..5eccbce73a33 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c | |||
| @@ -194,6 +194,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 194 | static void __init e750_init(void) | 194 | static void __init e750_init(void) |
| 195 | { | 195 | { |
| 196 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); | 196 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); |
| 197 | pxa_set_ffuart_info(NULL); | ||
| 198 | pxa_set_btuart_info(NULL); | ||
| 199 | pxa_set_stuart_info(NULL); | ||
| 197 | clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, | 200 | clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, |
| 198 | "GPIO11_CLK", NULL), | 201 | "GPIO11_CLK", NULL), |
| 199 | eseries_get_tmio_gpios(); | 202 | eseries_get_tmio_gpios(); |
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index 9866c7b9e784..aad129bed199 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c | |||
| @@ -195,6 +195,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 195 | 195 | ||
| 196 | static void __init e800_init(void) | 196 | static void __init e800_init(void) |
| 197 | { | 197 | { |
| 198 | pxa_set_ffuart_info(NULL); | ||
| 199 | pxa_set_btuart_info(NULL); | ||
| 200 | pxa_set_stuart_info(NULL); | ||
| 198 | clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, | 201 | clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, |
| 199 | "GPIO11_CLK", NULL), | 202 | "GPIO11_CLK", NULL), |
| 200 | eseries_get_tmio_gpios(); | 203 | eseries_get_tmio_gpios(); |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index aec7f4214b14..1c0de808b54d 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
| @@ -967,7 +967,7 @@ static inline void em_x270_init_gpio_keys(void) {} | |||
| 967 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | 967 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) |
| 968 | static struct regulator *em_x270_camera_ldo; | 968 | static struct regulator *em_x270_camera_ldo; |
| 969 | 969 | ||
| 970 | static int em_x270_sensor_init(struct device *dev) | 970 | static int em_x270_sensor_init(void) |
| 971 | { | 971 | { |
| 972 | int ret; | 972 | int ret; |
| 973 | 973 | ||
| @@ -996,7 +996,6 @@ static int em_x270_sensor_init(struct device *dev) | |||
| 996 | } | 996 | } |
| 997 | 997 | ||
| 998 | struct pxacamera_platform_data em_x270_camera_platform_data = { | 998 | struct pxacamera_platform_data em_x270_camera_platform_data = { |
| 999 | .init = em_x270_sensor_init, | ||
| 1000 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | 999 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | |
| 1001 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | 1000 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, |
| 1002 | .mclk_10khz = 2600, | 1001 | .mclk_10khz = 2600, |
| @@ -1049,8 +1048,10 @@ static struct platform_device em_x270_camera = { | |||
| 1049 | 1048 | ||
| 1050 | static void __init em_x270_init_camera(void) | 1049 | static void __init em_x270_init_camera(void) |
| 1051 | { | 1050 | { |
| 1052 | pxa_set_camera_info(&em_x270_camera_platform_data); | 1051 | if (em_x270_sensor_init() == 0) { |
| 1053 | platform_device_register(&em_x270_camera); | 1052 | pxa_set_camera_info(&em_x270_camera_platform_data); |
| 1053 | platform_device_register(&em_x270_camera); | ||
| 1054 | } | ||
| 1054 | } | 1055 | } |
| 1055 | #else | 1056 | #else |
| 1056 | static inline void em_x270_init_camera(void) {} | 1057 | static inline void em_x270_init_camera(void) {} |
| @@ -1286,6 +1287,10 @@ static void __init em_x270_init(void) | |||
| 1286 | { | 1287 | { |
| 1287 | pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config)); | 1288 | pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config)); |
| 1288 | 1289 | ||
| 1290 | pxa_set_ffuart_info(NULL); | ||
| 1291 | pxa_set_btuart_info(NULL); | ||
| 1292 | pxa_set_stuart_info(NULL); | ||
| 1293 | |||
| 1289 | #ifdef CONFIG_PM | 1294 | #ifdef CONFIG_PM |
| 1290 | pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP); | 1295 | pxa27x_set_pwrmode(PWRMODE_DEEPSLEEP); |
| 1291 | #endif | 1296 | #endif |
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index 588b265e5755..626c82b13970 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
| @@ -17,7 +17,11 @@ | |||
| 17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
| 18 | #include <linux/pwm_backlight.h> | 18 | #include <linux/pwm_backlight.h> |
| 19 | #include <linux/input.h> | 19 | #include <linux/input.h> |
| 20 | #include <linux/gpio.h> | ||
| 20 | #include <linux/gpio_keys.h> | 21 | #include <linux/gpio_keys.h> |
| 22 | #include <linux/leds-lp3944.h> | ||
| 23 | |||
| 24 | #include <media/soc_camera.h> | ||
| 21 | 25 | ||
| 22 | #include <asm/setup.h> | 26 | #include <asm/setup.h> |
| 23 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| @@ -29,6 +33,7 @@ | |||
| 29 | #include <plat/i2c.h> | 33 | #include <plat/i2c.h> |
| 30 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 31 | #include <mach/pxa27x_keypad.h> | 35 | #include <mach/pxa27x_keypad.h> |
| 36 | #include <mach/camera.h> | ||
| 32 | 37 | ||
| 33 | #include "devices.h" | 38 | #include "devices.h" |
| 34 | #include "generic.h" | 39 | #include "generic.h" |
| @@ -38,6 +43,9 @@ | |||
| 38 | #define GPIO15_A910_FLIP_LID 15 | 43 | #define GPIO15_A910_FLIP_LID 15 |
| 39 | #define GPIO12_E680_LOCK_SWITCH 12 | 44 | #define GPIO12_E680_LOCK_SWITCH 12 |
| 40 | #define GPIO15_E6_LOCK_SWITCH 15 | 45 | #define GPIO15_E6_LOCK_SWITCH 15 |
| 46 | #define GPIO50_nCAM_EN 50 | ||
| 47 | #define GPIO19_GEN1_CAM_RST 19 | ||
| 48 | #define GPIO28_GEN2_CAM_RST 28 | ||
| 41 | 49 | ||
| 42 | static struct platform_pwm_backlight_data ezx_backlight_data = { | 50 | static struct platform_pwm_backlight_data ezx_backlight_data = { |
| 43 | .pwm_id = 0, | 51 | .pwm_id = 0, |
| @@ -191,8 +199,8 @@ static unsigned long gen1_pin_config[] __initdata = { | |||
| 191 | GPIO94_CIF_DD_5, | 199 | GPIO94_CIF_DD_5, |
| 192 | GPIO17_CIF_DD_6, | 200 | GPIO17_CIF_DD_6, |
| 193 | GPIO108_CIF_DD_7, | 201 | GPIO108_CIF_DD_7, |
| 194 | GPIO50_GPIO, /* CAM_EN */ | 202 | GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */ |
| 195 | GPIO19_GPIO, /* CAM_RST */ | 203 | GPIO19_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */ |
| 196 | 204 | ||
| 197 | /* EMU */ | 205 | /* EMU */ |
| 198 | GPIO120_GPIO, /* EMU_MUX1 */ | 206 | GPIO120_GPIO, /* EMU_MUX1 */ |
| @@ -248,8 +256,8 @@ static unsigned long gen2_pin_config[] __initdata = { | |||
| 248 | GPIO48_CIF_DD_5, | 256 | GPIO48_CIF_DD_5, |
| 249 | GPIO93_CIF_DD_6, | 257 | GPIO93_CIF_DD_6, |
| 250 | GPIO12_CIF_DD_7, | 258 | GPIO12_CIF_DD_7, |
| 251 | GPIO50_GPIO, /* CAM_EN */ | 259 | GPIO50_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_EN */ |
| 252 | GPIO28_GPIO, /* CAM_RST */ | 260 | GPIO28_GPIO | MFP_LPM_DRIVE_HIGH, /* CAM_RST */ |
| 253 | GPIO17_GPIO, /* CAM_FLASH */ | 261 | GPIO17_GPIO, /* CAM_FLASH */ |
| 254 | }; | 262 | }; |
| 255 | #endif | 263 | #endif |
| @@ -683,6 +691,81 @@ static struct platform_device a780_gpio_keys = { | |||
| 683 | }, | 691 | }, |
| 684 | }; | 692 | }; |
| 685 | 693 | ||
| 694 | /* camera */ | ||
| 695 | static int a780_camera_init(void) | ||
| 696 | { | ||
| 697 | int err; | ||
| 698 | |||
| 699 | /* | ||
| 700 | * GPIO50_nCAM_EN is active low | ||
| 701 | * GPIO19_GEN1_CAM_RST is active on rising edge | ||
| 702 | */ | ||
| 703 | err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN"); | ||
| 704 | if (err) { | ||
| 705 | pr_err("%s: Failed to request nCAM_EN\n", __func__); | ||
| 706 | goto fail; | ||
| 707 | } | ||
| 708 | |||
| 709 | err = gpio_request(GPIO19_GEN1_CAM_RST, "CAM_RST"); | ||
| 710 | if (err) { | ||
| 711 | pr_err("%s: Failed to request CAM_RST\n", __func__); | ||
| 712 | goto fail_gpio_cam_rst; | ||
| 713 | } | ||
| 714 | |||
| 715 | gpio_direction_output(GPIO50_nCAM_EN, 1); | ||
| 716 | gpio_direction_output(GPIO19_GEN1_CAM_RST, 0); | ||
| 717 | |||
| 718 | return 0; | ||
| 719 | |||
| 720 | fail_gpio_cam_rst: | ||
| 721 | gpio_free(GPIO50_nCAM_EN); | ||
| 722 | fail: | ||
| 723 | return err; | ||
| 724 | } | ||
| 725 | |||
| 726 | static int a780_camera_power(struct device *dev, int on) | ||
| 727 | { | ||
| 728 | gpio_set_value(GPIO50_nCAM_EN, !on); | ||
| 729 | return 0; | ||
| 730 | } | ||
| 731 | |||
| 732 | static int a780_camera_reset(struct device *dev) | ||
| 733 | { | ||
| 734 | gpio_set_value(GPIO19_GEN1_CAM_RST, 0); | ||
| 735 | msleep(10); | ||
| 736 | gpio_set_value(GPIO19_GEN1_CAM_RST, 1); | ||
| 737 | |||
| 738 | return 0; | ||
| 739 | } | ||
| 740 | |||
| 741 | struct pxacamera_platform_data a780_pxacamera_platform_data = { | ||
| 742 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | ||
| 743 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | ||
| 744 | .mclk_10khz = 5000, | ||
| 745 | }; | ||
| 746 | |||
| 747 | static struct i2c_board_info a780_camera_i2c_board_info = { | ||
| 748 | I2C_BOARD_INFO("mt9m111", 0x5d), | ||
| 749 | }; | ||
| 750 | |||
| 751 | static struct soc_camera_link a780_iclink = { | ||
| 752 | .bus_id = 0, | ||
| 753 | .flags = SOCAM_SENSOR_INVERT_PCLK, | ||
| 754 | .i2c_adapter_id = 0, | ||
| 755 | .board_info = &a780_camera_i2c_board_info, | ||
| 756 | .module_name = "mt9m111", | ||
| 757 | .power = a780_camera_power, | ||
| 758 | .reset = a780_camera_reset, | ||
| 759 | }; | ||
| 760 | |||
| 761 | static struct platform_device a780_camera = { | ||
| 762 | .name = "soc-camera-pdrv", | ||
| 763 | .id = 0, | ||
| 764 | .dev = { | ||
| 765 | .platform_data = &a780_iclink, | ||
| 766 | }, | ||
| 767 | }; | ||
| 768 | |||
| 686 | static struct platform_device *a780_devices[] __initdata = { | 769 | static struct platform_device *a780_devices[] __initdata = { |
| 687 | &a780_gpio_keys, | 770 | &a780_gpio_keys, |
| 688 | }; | 771 | }; |
| @@ -693,12 +776,21 @@ static void __init a780_init(void) | |||
| 693 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); | 776 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); |
| 694 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config)); | 777 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a780_pin_config)); |
| 695 | 778 | ||
| 779 | pxa_set_ffuart_info(NULL); | ||
| 780 | pxa_set_btuart_info(NULL); | ||
| 781 | pxa_set_stuart_info(NULL); | ||
| 782 | |||
| 696 | pxa_set_i2c_info(NULL); | 783 | pxa_set_i2c_info(NULL); |
| 697 | 784 | ||
| 698 | set_pxa_fb_info(&ezx_fb_info_1); | 785 | set_pxa_fb_info(&ezx_fb_info_1); |
| 699 | 786 | ||
| 700 | pxa_set_keypad_info(&a780_keypad_platform_data); | 787 | pxa_set_keypad_info(&a780_keypad_platform_data); |
| 701 | 788 | ||
| 789 | if (a780_camera_init() == 0) { | ||
| 790 | pxa_set_camera_info(&a780_pxacamera_platform_data); | ||
| 791 | platform_device_register(&a780_camera); | ||
| 792 | } | ||
| 793 | |||
| 702 | platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); | 794 | platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); |
| 703 | platform_add_devices(ARRAY_AND_SIZE(a780_devices)); | 795 | platform_add_devices(ARRAY_AND_SIZE(a780_devices)); |
| 704 | } | 796 | } |
| @@ -754,6 +846,10 @@ static void __init e680_init(void) | |||
| 754 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); | 846 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen1_pin_config)); |
| 755 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config)); | 847 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e680_pin_config)); |
| 756 | 848 | ||
| 849 | pxa_set_ffuart_info(NULL); | ||
| 850 | pxa_set_btuart_info(NULL); | ||
| 851 | pxa_set_stuart_info(NULL); | ||
| 852 | |||
| 757 | pxa_set_i2c_info(NULL); | 853 | pxa_set_i2c_info(NULL); |
| 758 | i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); | 854 | i2c_register_board_info(0, ARRAY_AND_SIZE(e680_i2c_board_info)); |
| 759 | 855 | ||
| @@ -816,6 +912,10 @@ static void __init a1200_init(void) | |||
| 816 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | 912 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); |
| 817 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config)); | 913 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a1200_pin_config)); |
| 818 | 914 | ||
| 915 | pxa_set_ffuart_info(NULL); | ||
| 916 | pxa_set_btuart_info(NULL); | ||
| 917 | pxa_set_stuart_info(NULL); | ||
| 918 | |||
| 819 | pxa_set_i2c_info(NULL); | 919 | pxa_set_i2c_info(NULL); |
| 820 | i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); | 920 | i2c_register_board_info(0, ARRAY_AND_SIZE(a1200_i2c_board_info)); |
| 821 | 921 | ||
| @@ -864,6 +964,131 @@ static struct platform_device a910_gpio_keys = { | |||
| 864 | }, | 964 | }, |
| 865 | }; | 965 | }; |
| 866 | 966 | ||
| 967 | /* camera */ | ||
| 968 | static int a910_camera_init(void) | ||
| 969 | { | ||
| 970 | int err; | ||
| 971 | |||
| 972 | /* | ||
| 973 | * GPIO50_nCAM_EN is active low | ||
| 974 | * GPIO28_GEN2_CAM_RST is active on rising edge | ||
| 975 | */ | ||
| 976 | err = gpio_request(GPIO50_nCAM_EN, "nCAM_EN"); | ||
| 977 | if (err) { | ||
| 978 | pr_err("%s: Failed to request nCAM_EN\n", __func__); | ||
| 979 | goto fail; | ||
| 980 | } | ||
| 981 | |||
| 982 | err = gpio_request(GPIO28_GEN2_CAM_RST, "CAM_RST"); | ||
| 983 | if (err) { | ||
| 984 | pr_err("%s: Failed to request CAM_RST\n", __func__); | ||
| 985 | goto fail_gpio_cam_rst; | ||
| 986 | } | ||
| 987 | |||
| 988 | gpio_direction_output(GPIO50_nCAM_EN, 1); | ||
| 989 | gpio_direction_output(GPIO28_GEN2_CAM_RST, 0); | ||
| 990 | |||
| 991 | return 0; | ||
| 992 | |||
| 993 | fail_gpio_cam_rst: | ||
| 994 | gpio_free(GPIO50_nCAM_EN); | ||
| 995 | fail: | ||
| 996 | return err; | ||
| 997 | } | ||
| 998 | |||
| 999 | static int a910_camera_power(struct device *dev, int on) | ||
| 1000 | { | ||
| 1001 | gpio_set_value(GPIO50_nCAM_EN, !on); | ||
| 1002 | return 0; | ||
| 1003 | } | ||
| 1004 | |||
| 1005 | static int a910_camera_reset(struct device *dev) | ||
| 1006 | { | ||
| 1007 | gpio_set_value(GPIO28_GEN2_CAM_RST, 0); | ||
| 1008 | msleep(10); | ||
| 1009 | gpio_set_value(GPIO28_GEN2_CAM_RST, 1); | ||
| 1010 | |||
| 1011 | return 0; | ||
| 1012 | } | ||
| 1013 | |||
| 1014 | struct pxacamera_platform_data a910_pxacamera_platform_data = { | ||
| 1015 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | ||
| 1016 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | ||
| 1017 | .mclk_10khz = 5000, | ||
| 1018 | }; | ||
| 1019 | |||
| 1020 | static struct i2c_board_info a910_camera_i2c_board_info = { | ||
| 1021 | I2C_BOARD_INFO("mt9m111", 0x5d), | ||
| 1022 | }; | ||
| 1023 | |||
| 1024 | static struct soc_camera_link a910_iclink = { | ||
| 1025 | .bus_id = 0, | ||
| 1026 | .i2c_adapter_id = 0, | ||
| 1027 | .board_info = &a910_camera_i2c_board_info, | ||
| 1028 | .module_name = "mt9m111", | ||
| 1029 | .power = a910_camera_power, | ||
| 1030 | .reset = a910_camera_reset, | ||
| 1031 | }; | ||
| 1032 | |||
| 1033 | static struct platform_device a910_camera = { | ||
| 1034 | .name = "soc-camera-pdrv", | ||
| 1035 | .id = 0, | ||
| 1036 | .dev = { | ||
| 1037 | .platform_data = &a910_iclink, | ||
| 1038 | }, | ||
| 1039 | }; | ||
| 1040 | |||
| 1041 | /* leds-lp3944 */ | ||
| 1042 | static struct lp3944_platform_data a910_lp3944_leds = { | ||
| 1043 | .leds_size = LP3944_LEDS_MAX, | ||
| 1044 | .leds = { | ||
| 1045 | [0] = { | ||
| 1046 | .name = "a910:red:", | ||
| 1047 | .status = LP3944_LED_STATUS_OFF, | ||
| 1048 | .type = LP3944_LED_TYPE_LED, | ||
| 1049 | }, | ||
| 1050 | [1] = { | ||
| 1051 | .name = "a910:green:", | ||
| 1052 | .status = LP3944_LED_STATUS_OFF, | ||
| 1053 | .type = LP3944_LED_TYPE_LED, | ||
| 1054 | }, | ||
| 1055 | [2] { | ||
| 1056 | .name = "a910:blue:", | ||
| 1057 | .status = LP3944_LED_STATUS_OFF, | ||
| 1058 | .type = LP3944_LED_TYPE_LED, | ||
| 1059 | }, | ||
| 1060 | /* Leds 3 and 4 are used as display power switches */ | ||
| 1061 | [3] = { | ||
| 1062 | .name = "a910::cli_display", | ||
| 1063 | .status = LP3944_LED_STATUS_OFF, | ||
| 1064 | .type = LP3944_LED_TYPE_LED_INVERTED | ||
| 1065 | }, | ||
| 1066 | [4] = { | ||
| 1067 | .name = "a910::main_display", | ||
| 1068 | .status = LP3944_LED_STATUS_ON, | ||
| 1069 | .type = LP3944_LED_TYPE_LED_INVERTED | ||
| 1070 | }, | ||
| 1071 | [5] = { .type = LP3944_LED_TYPE_NONE }, | ||
| 1072 | [6] = { | ||
| 1073 | .name = "a910::torch", | ||
| 1074 | .status = LP3944_LED_STATUS_OFF, | ||
| 1075 | .type = LP3944_LED_TYPE_LED, | ||
| 1076 | }, | ||
| 1077 | [7] = { | ||
| 1078 | .name = "a910::flash", | ||
| 1079 | .status = LP3944_LED_STATUS_OFF, | ||
| 1080 | .type = LP3944_LED_TYPE_LED_INVERTED, | ||
| 1081 | }, | ||
| 1082 | }, | ||
| 1083 | }; | ||
| 1084 | |||
| 1085 | static struct i2c_board_info __initdata a910_i2c_board_info[] = { | ||
| 1086 | { | ||
| 1087 | I2C_BOARD_INFO("lp3944", 0x60), | ||
| 1088 | .platform_data = &a910_lp3944_leds, | ||
| 1089 | }, | ||
| 1090 | }; | ||
| 1091 | |||
| 867 | static struct platform_device *a910_devices[] __initdata = { | 1092 | static struct platform_device *a910_devices[] __initdata = { |
| 868 | &a910_gpio_keys, | 1093 | &a910_gpio_keys, |
| 869 | }; | 1094 | }; |
| @@ -874,12 +1099,22 @@ static void __init a910_init(void) | |||
| 874 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | 1099 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); |
| 875 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config)); | 1100 | pxa2xx_mfp_config(ARRAY_AND_SIZE(a910_pin_config)); |
| 876 | 1101 | ||
| 1102 | pxa_set_ffuart_info(NULL); | ||
| 1103 | pxa_set_btuart_info(NULL); | ||
| 1104 | pxa_set_stuart_info(NULL); | ||
| 1105 | |||
| 877 | pxa_set_i2c_info(NULL); | 1106 | pxa_set_i2c_info(NULL); |
| 1107 | i2c_register_board_info(0, ARRAY_AND_SIZE(a910_i2c_board_info)); | ||
| 878 | 1108 | ||
| 879 | set_pxa_fb_info(&ezx_fb_info_2); | 1109 | set_pxa_fb_info(&ezx_fb_info_2); |
| 880 | 1110 | ||
| 881 | pxa_set_keypad_info(&a910_keypad_platform_data); | 1111 | pxa_set_keypad_info(&a910_keypad_platform_data); |
| 882 | 1112 | ||
| 1113 | if (a910_camera_init() == 0) { | ||
| 1114 | pxa_set_camera_info(&a910_pxacamera_platform_data); | ||
| 1115 | platform_device_register(&a910_camera); | ||
| 1116 | } | ||
| 1117 | |||
| 883 | platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); | 1118 | platform_add_devices(ARRAY_AND_SIZE(ezx_devices)); |
| 884 | platform_add_devices(ARRAY_AND_SIZE(a910_devices)); | 1119 | platform_add_devices(ARRAY_AND_SIZE(a910_devices)); |
| 885 | } | 1120 | } |
| @@ -935,6 +1170,10 @@ static void __init e6_init(void) | |||
| 935 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | 1170 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); |
| 936 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config)); | 1171 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e6_pin_config)); |
| 937 | 1172 | ||
| 1173 | pxa_set_ffuart_info(NULL); | ||
| 1174 | pxa_set_btuart_info(NULL); | ||
| 1175 | pxa_set_stuart_info(NULL); | ||
| 1176 | |||
| 938 | pxa_set_i2c_info(NULL); | 1177 | pxa_set_i2c_info(NULL); |
| 939 | i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); | 1178 | i2c_register_board_info(0, ARRAY_AND_SIZE(e6_i2c_board_info)); |
| 940 | 1179 | ||
| @@ -971,6 +1210,10 @@ static void __init e2_init(void) | |||
| 971 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); | 1210 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gen2_pin_config)); |
| 972 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config)); | 1211 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e2_pin_config)); |
| 973 | 1212 | ||
| 1213 | pxa_set_ffuart_info(NULL); | ||
| 1214 | pxa_set_btuart_info(NULL); | ||
| 1215 | pxa_set_stuart_info(NULL); | ||
| 1216 | |||
| 974 | pxa_set_i2c_info(NULL); | 1217 | pxa_set_i2c_info(NULL); |
| 975 | i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); | 1218 | i2c_register_board_info(0, ARRAY_AND_SIZE(e2_i2c_board_info)); |
| 976 | 1219 | ||
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index 485fede83d97..890fb90a672f 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -67,3 +67,8 @@ extern struct sysdev_class pxa_irq_sysclass; | |||
| 67 | extern struct sysdev_class pxa_gpio_sysclass; | 67 | extern struct sysdev_class pxa_gpio_sysclass; |
| 68 | extern struct sysdev_class pxa2xx_mfp_sysclass; | 68 | extern struct sysdev_class pxa2xx_mfp_sysclass; |
| 69 | extern struct sysdev_class pxa3xx_mfp_sysclass; | 69 | extern struct sysdev_class pxa3xx_mfp_sysclass; |
| 70 | |||
| 71 | void __init pxa_set_ffuart_info(void *info); | ||
| 72 | void __init pxa_set_btuart_info(void *info); | ||
| 73 | void __init pxa_set_stuart_info(void *info); | ||
| 74 | void __init pxa_set_hwuart_info(void *info); | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index 1708c0109844..96c345129135 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
| @@ -211,6 +211,11 @@ static void __init gumstix_init(void) | |||
| 211 | { | 211 | { |
| 212 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); | 212 | pxa2xx_mfp_config(ARRAY_AND_SIZE(gumstix_pin_config)); |
| 213 | 213 | ||
| 214 | pxa_set_ffuart_info(NULL); | ||
| 215 | pxa_set_btuart_info(NULL); | ||
| 216 | pxa_set_stuart_info(NULL); | ||
| 217 | pxa_set_hwuart_info(NULL); | ||
| 218 | |||
| 214 | gumstix_bluetooth_init(); | 219 | gumstix_bluetooth_init(); |
| 215 | gumstix_udc_init(); | 220 | gumstix_udc_init(); |
| 216 | gumstix_mmc_init(); | 221 | gumstix_mmc_init(); |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index f3d220c32e07..c1cab0871c99 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c | |||
| @@ -193,6 +193,9 @@ static void __init h5000_init(void) | |||
| 193 | fix_msc(); | 193 | fix_msc(); |
| 194 | 194 | ||
| 195 | pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); | 195 | pxa2xx_mfp_config(ARRAY_AND_SIZE(h5000_pin_config)); |
| 196 | pxa_set_ffuart_info(NULL); | ||
| 197 | pxa_set_btuart_info(NULL); | ||
| 198 | pxa_set_stuart_info(NULL); | ||
| 196 | pxa_set_udc_info(&h5000_udc_mach_info); | 199 | pxa_set_udc_info(&h5000_udc_mach_info); |
| 197 | platform_add_devices(ARRAY_AND_SIZE(devices)); | 200 | platform_add_devices(ARRAY_AND_SIZE(devices)); |
| 198 | } | 201 | } |
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c index cea99fe65b97..f9a2e4b0f090 100644 --- a/arch/arm/mach-pxa/himalaya.c +++ b/arch/arm/mach-pxa/himalaya.c | |||
| @@ -150,6 +150,9 @@ static void __init himalaya_lcd_init(void) | |||
| 150 | 150 | ||
| 151 | static void __init himalaya_init(void) | 151 | static void __init himalaya_init(void) |
| 152 | { | 152 | { |
| 153 | pxa_set_ffuart_info(NULL); | ||
| 154 | pxa_set_btuart_info(NULL); | ||
| 155 | pxa_set_stuart_info(NULL); | ||
| 153 | himalaya_lcd_init(); | 156 | himalaya_lcd_init(); |
| 154 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 157 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 155 | } | 158 | } |
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c index 83bd3c6e3884..848c861dd23f 100644 --- a/arch/arm/mach-pxa/hx4700.c +++ b/arch/arm/mach-pxa/hx4700.c | |||
| @@ -820,6 +820,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 820 | &gpio_keys, | 820 | &gpio_keys, |
| 821 | &backlight, | 821 | &backlight, |
| 822 | &w3220, | 822 | &w3220, |
| 823 | &hx4700_lcd, | ||
| 823 | &egpio, | 824 | &egpio, |
| 824 | &bq24022, | 825 | &bq24022, |
| 825 | &gpio_vbus, | 826 | &gpio_vbus, |
| @@ -849,6 +850,10 @@ static void __init hx4700_init(void) | |||
| 849 | pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config)); | 850 | pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config)); |
| 850 | hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios)); | 851 | hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios)); |
| 851 | 852 | ||
| 853 | pxa_set_ffuart_info(NULL); | ||
| 854 | pxa_set_btuart_info(NULL); | ||
| 855 | pxa_set_stuart_info(NULL); | ||
| 856 | |||
| 852 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 857 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 853 | 858 | ||
| 854 | pxa_set_ficp_info(&ficp_info); | 859 | pxa_set_ficp_info(&ficp_info); |
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index b6486ef20b17..5c9e11d74f49 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
| @@ -179,6 +179,9 @@ static void __init idp_init(void) | |||
| 179 | printk("idp_init()\n"); | 179 | printk("idp_init()\n"); |
| 180 | 180 | ||
| 181 | pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config)); | 181 | pxa2xx_mfp_config(ARRAY_AND_SIZE(idp_pin_config)); |
| 182 | pxa_set_ffuart_info(NULL); | ||
| 183 | pxa_set_btuart_info(NULL); | ||
| 184 | pxa_set_stuart_info(NULL); | ||
| 182 | 185 | ||
| 183 | platform_device_register(&smc91x_device); | 186 | platform_device_register(&smc91x_device); |
| 184 | //platform_device_register(&mst_audio_device); | 187 | //platform_device_register(&mst_audio_device); |
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 2a4945db31c5..5b0862df61ab 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c | |||
| @@ -554,8 +554,12 @@ static struct i2c_pxa_platform_data i2c_pdata = { | |||
| 554 | 554 | ||
| 555 | static void __init imote2_init(void) | 555 | static void __init imote2_init(void) |
| 556 | { | 556 | { |
| 557 | |||
| 558 | pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); | 557 | pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config)); |
| 558 | |||
| 559 | pxa_set_ffuart_info(NULL); | ||
| 560 | pxa_set_btuart_info(NULL); | ||
| 561 | pxa_set_stuart_info(NULL); | ||
| 562 | |||
| 559 | /* SPI chip select directions - all other directions should | 563 | /* SPI chip select directions - all other directions should |
| 560 | * be handled by drivers.*/ | 564 | * be handled by drivers.*/ |
| 561 | gpio_direction_output(37, 0); | 565 | gpio_direction_output(37, 0); |
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index aa3d9f70a08a..50f1297bf5ac 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h | |||
| @@ -105,6 +105,7 @@ | |||
| 105 | * | 105 | * |
| 106 | * PXA935 A0 0x56056931 0x1E653013 | 106 | * PXA935 A0 0x56056931 0x1E653013 |
| 107 | * PXA935 B0 0x56056936 0x6E653013 | 107 | * PXA935 B0 0x56056936 0x6E653013 |
| 108 | * PXA935 B1 0x56056938 0x8E653013 | ||
| 108 | */ | 109 | */ |
| 109 | #ifdef CONFIG_PXA25x | 110 | #ifdef CONFIG_PXA25x |
| 110 | #define __cpu_is_pxa210(id) \ | 111 | #define __cpu_is_pxa210(id) \ |
| @@ -283,7 +284,7 @@ | |||
| 283 | _id == 0x3; \ | 284 | _id == 0x3; \ |
| 284 | }) | 285 | }) |
| 285 | 286 | ||
| 286 | #define __cpu_is_pxa9xx(id) \ | 287 | #define __cpu_is_pxa93x(id) \ |
| 287 | ({ \ | 288 | ({ \ |
| 288 | unsigned int _id = (id) >> 4 & 0xfff; \ | 289 | unsigned int _id = (id) >> 4 & 0xfff; \ |
| 289 | _id == 0x683 || _id == 0x693; \ | 290 | _id == 0x683 || _id == 0x693; \ |
| @@ -299,9 +300,9 @@ | |||
| 299 | __cpu_is_pxa3xx(read_cpuid_id()); \ | 300 | __cpu_is_pxa3xx(read_cpuid_id()); \ |
| 300 | }) | 301 | }) |
| 301 | 302 | ||
| 302 | #define cpu_is_pxa9xx() \ | 303 | #define cpu_is_pxa93x() \ |
| 303 | ({ \ | 304 | ({ \ |
| 304 | __cpu_is_pxa9xx(read_cpuid_id()); \ | 305 | __cpu_is_pxa93x(read_cpuid_id()); \ |
| 305 | }) | 306 | }) |
| 306 | /* | 307 | /* |
| 307 | * return current memory and LCD clock frequency in units of 10kHz | 308 | * return current memory and LCD clock frequency in units of 10kHz |
diff --git a/arch/arm/mach-pxa/include/mach/palmtreo.h b/arch/arm/mach-pxa/include/mach/palmtreo.h new file mode 100644 index 000000000000..2d3f14e3be29 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmtreo.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm Treo smartphones | ||
| 3 | * | ||
| 4 | * currently supported: | ||
| 5 | * Palm Treo 680 (GSM) | ||
| 6 | * Palm Centro 685 (GSM) | ||
| 7 | * | ||
| 8 | * Author: Tomas Cech <sleep_walker@suse.cz> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | * find more info at www.hackndev.com | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef _INCLUDE_TREO_H_ | ||
| 19 | #define _INCLUDE_TREO_H_ | ||
| 20 | |||
| 21 | /* GPIOs */ | ||
| 22 | #define GPIO_NR_TREO_POWER_DETECT 0 | ||
| 23 | #define GPIO_NR_TREO_AMP_EN 27 | ||
| 24 | #define GPIO_NR_TREO_GREEN_LED 20 | ||
| 25 | #define GPIO_NR_TREO_RED_LED 79 | ||
| 26 | #define GPIO_NR_TREO_SD_DETECT_N 113 | ||
| 27 | #define GPIO_NR_TREO_EP_DETECT_N 116 | ||
| 28 | #define GPIO_NR_TREO_USB_DETECT 1 | ||
| 29 | #define GPIO_NR_TREO_USB_PULLUP 114 | ||
| 30 | #define GPIO_NR_TREO_GSM_POWER 40 | ||
| 31 | #define GPIO_NR_TREO_GSM_RESET 87 | ||
| 32 | #define GPIO_NR_TREO_GSM_WAKE 57 | ||
| 33 | #define GPIO_NR_TREO_GSM_HOST_WAKE 14 | ||
| 34 | #define GPIO_NR_TREO_GSM_TRIGGER 10 | ||
| 35 | #define GPIO_NR_TREO_IR_EN 115 | ||
| 36 | #define GPIO_NR_TREO_IR_TXD 47 | ||
| 37 | #define GPIO_NR_TREO_BL_POWER 38 | ||
| 38 | #define GPIO_NR_TREO_LCD_POWER 25 | ||
| 39 | |||
| 40 | /* Treo680 specific GPIOs */ | ||
| 41 | #ifdef CONFIG_MACH_TREO680 | ||
| 42 | #define GPIO_NR_TREO680_SD_READONLY 33 | ||
| 43 | #define GPIO_NR_TREO680_SD_POWER 42 | ||
| 44 | #define GPIO_NR_TREO680_VIBRATE_EN 44 | ||
| 45 | #define GPIO_NR_TREO680_KEYB_BL 24 | ||
| 46 | #define GPIO_NR_TREO680_BT_EN 43 | ||
| 47 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 48 | |||
| 49 | /* Centro685 specific GPIOs */ | ||
| 50 | #define GPIO_NR_CENTRO_SD_POWER 21 | ||
| 51 | #define GPIO_NR_CENTRO_VIBRATE_EN 22 | ||
| 52 | #define GPIO_NR_CENTRO_KEYB_BL 33 | ||
| 53 | #define GPIO_NR_CENTRO_BT_EN 80 | ||
| 54 | |||
| 55 | /* Various addresses */ | ||
| 56 | #define TREO_PHYS_RAM_START 0xa0000000 | ||
| 57 | #define TREO_PHYS_IO_START 0x40000000 | ||
| 58 | #define TREO_STR_BASE 0xa2000000 | ||
| 59 | |||
| 60 | /* BACKLIGHT */ | ||
| 61 | #define TREO_MAX_INTENSITY 254 | ||
| 62 | #define TREO_DEFAULT_INTENSITY 160 | ||
| 63 | #define TREO_LIMIT_MASK 0x7F | ||
| 64 | #define TREO_PRESCALER 63 | ||
| 65 | #define TREO_PERIOD_NS 3500 | ||
| 66 | |||
| 67 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h index f73061c90b5e..160ec83f51a6 100644 --- a/arch/arm/mach-pxa/include/mach/pxafb.h +++ b/arch/arm/mach-pxa/include/mach/pxafb.h | |||
| @@ -76,7 +76,8 @@ struct pxafb_mode_info { | |||
| 76 | u_char bpp; | 76 | u_char bpp; |
| 77 | u_int cmap_greyscale:1, | 77 | u_int cmap_greyscale:1, |
| 78 | depth:8, | 78 | depth:8, |
| 79 | unused:23; | 79 | transparency:1, |
| 80 | unused:22; | ||
| 80 | 81 | ||
| 81 | /* Parallel Mode Timing */ | 82 | /* Parallel Mode Timing */ |
| 82 | u_char hsync_len; | 83 | u_char hsync_len; |
diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h new file mode 100644 index 000000000000..44b0b20b69a4 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA3xx_U2D_H | ||
| 2 | #define __ASM_ARCH_PXA3xx_U2D_H | ||
| 3 | |||
| 4 | #include <mach/bitfield.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * USB2 device controller registers and bits definitions | ||
| 8 | */ | ||
| 9 | #define U2DCR (0x0000) /* U2D Control Register */ | ||
| 10 | #define U2DCR_NDC (1 << 31) /* NAK During Config */ | ||
| 11 | #define U2DCR_HSTC (0x7 << 28) /* High Speed Timeout Calibration */ | ||
| 12 | #define U2DCR_SPEOREN (1 << 27) /* Short Packet EOR INTR generation Enable */ | ||
| 13 | #define U2DCR_FSTC (0x7 << 24) /* Full Speed Timeout Calibration */ | ||
| 14 | #define U2DCR_UCLKOVR (1 << 22) /* UTM Clock Override */ | ||
| 15 | #define U2DCR_ABP (1 << 21) /* Application Bus Power */ | ||
| 16 | #define U2DCR_ADD (1 << 20) /* Application Device Disconnect */ | ||
| 17 | #define U2DCR_CC (1 << 19) /* Configuration Change */ | ||
| 18 | #define U2DCR_HS (1 << 18) /* High Speed USB Detection */ | ||
| 19 | #define U2DCR_SMAC (1 << 17) /* Switch Endpoint Memory to Active Configuration */ | ||
| 20 | #define U2DCR_DWRE (1 << 16) /* Device Remote Wake-up Feature */ | ||
| 21 | #define U2DCR_ACN (0xf << 12) /* Active U2D Configuration Number */ | ||
| 22 | #define U2DCR_AIN (0xf << 8) /* Active U2D Interface Number */ | ||
| 23 | #define U2DCR_AAISN (0xf << 4) /* Active U2D Alternate Interface Setting Number */ | ||
| 24 | #define U2DCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */ | ||
| 25 | #define U2DCR_UDR (1 << 2) /* U2D Resume */ | ||
| 26 | #define U2DCR_UDA (1 << 1) /* U2D Active */ | ||
| 27 | #define U2DCR_UDE (1 << 0) /* U2D Enable */ | ||
| 28 | |||
| 29 | #define U2DICR (0x0004) /* U2D Interrupt Control Register */ | ||
| 30 | #define U2DISR (0x000C) /* U2D Interrupt Status Register */ | ||
| 31 | #define U2DINT_CC (1 << 31) /* Interrupt - Configuration Change */ | ||
| 32 | #define U2DINT_SOF (1 << 30) /* Interrupt - SOF */ | ||
| 33 | #define U2DINT_USOF (1 << 29) /* Interrupt - micro SOF */ | ||
| 34 | #define U2DINT_RU (1 << 28) /* Interrupt - Resume */ | ||
| 35 | #define U2DINT_SU (1 << 27) /* Interrupt - Suspend */ | ||
| 36 | #define U2DINT_RS (1 << 26) /* Interrupt - Reset */ | ||
| 37 | #define U2DINT_DPE (1 << 25) /* Interrupt - Data Packet Error */ | ||
| 38 | #define U2DINT_FIFOERR (0x4) /* Interrupt - endpoint FIFO error */ | ||
| 39 | #define U2DINT_PACKETCMP (0x2) /* Interrupt - endpoint packet complete */ | ||
| 40 | #define U2DINT_SPACKETCMP (0x1) /* Interrupt - endpoint short packet complete */ | ||
| 41 | |||
| 42 | #define U2DFNR (0x0014) /* U2D Frame Number Register */ | ||
| 43 | |||
| 44 | #define U2DINT(n, intr) (((intr) & 0x07) << (((n) & 0x07) * 3)) | ||
| 45 | #define U2DICR2 (0x0008) /* U2D Interrupt Control Register 2 */ | ||
| 46 | #define U2DISR2 (0x0010) /* U2D Interrupt Status Register 2 */ | ||
| 47 | |||
| 48 | #define U2DOTGCR (0x0020) /* U2D OTG Control Register */ | ||
| 49 | #define U2DOTGCR_OTGEN (1 << 31) /* On-The-Go Enable */ | ||
| 50 | #define U2DOTGCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocal Port Support */ | ||
| 51 | #define U2DOTGCR_AHNP (1 << 29) /* A-device Host Negotiation Protocal Support */ | ||
| 52 | #define U2DOTGCR_BHNP (1 << 28) /* B-device Host Negotiation Protocal Enable */ | ||
| 53 | |||
| 54 | #ifdef CONFIG_CPU_PXA930 | ||
| 55 | #define U2DOTGCR_LPA (1 << 15) /* ULPI low power mode active */ | ||
| 56 | #define U2DOTGCR_IESI (1 << 13) /* OTG interrupt Enable */ | ||
| 57 | #define U2DOTGCR_ISSI (1 << 12) /* OTG interrupt status */ | ||
| 58 | #endif | ||
| 59 | |||
| 60 | #define U2DOTGCR_CKAF (1 << 5) /* Carkit Mode Alternate Function Select */ | ||
| 61 | #define U2DOTGCR_UTMID (1 << 4) /* UTMI Interface Disable */ | ||
| 62 | #define U2DOTGCR_ULAF (1 << 3) /* ULPI Mode Alternate Function Select */ | ||
| 63 | #define U2DOTGCR_SMAF (1 << 2) /* Serial Mode Alternate Function Select */ | ||
| 64 | #define U2DOTGCR_RTSM (1 << 1) /* Return to Synchronous Mode (ULPI Mode) */ | ||
| 65 | #define U2DOTGCR_ULE (1 << 0) /* ULPI Wrapper Enable */ | ||
| 66 | |||
| 67 | #define U2DOTGICR (0x0024) /* U2D OTG Interrupt Control Register */ | ||
| 68 | #define U2DOTGISR (0x0028) /* U2D OTG Interrupt Status Register */ | ||
| 69 | |||
| 70 | #define U2DOTGINT_SF (1 << 17) /* OTG Set Feature Command Received */ | ||
| 71 | #define U2DOTGINT_SI (1 << 16) /* OTG Interrupt */ | ||
| 72 | #define U2DOTGINT_RLS1 (1 << 14) /* RXCMD Linestate[1] Change Interrupt Rise */ | ||
| 73 | #define U2DOTGINT_RLS0 (1 << 13) /* RXCMD Linestate[0] Change Interrupt Rise */ | ||
| 74 | #define U2DOTGINT_RID (1 << 12) /* RXCMD OTG ID Change Interrupt Rise */ | ||
| 75 | #define U2DOTGINT_RSE (1 << 11) /* RXCMD OTG Session End Interrupt Rise */ | ||
| 76 | #define U2DOTGINT_RSV (1 << 10) /* RXCMD OTG Session Valid Interrupt Rise */ | ||
| 77 | #define U2DOTGINT_RVV (1 << 9) /* RXCMD OTG Vbus Valid Interrupt Rise */ | ||
| 78 | #define U2DOTGINT_RCK (1 << 8) /* RXCMD Carkit Interrupt Rise */ | ||
| 79 | #define U2DOTGINT_FLS1 (1 << 6) /* RXCMD Linestate[1] Change Interrupt Fall */ | ||
| 80 | #define U2DOTGINT_FLS0 (1 << 5) /* RXCMD Linestate[0] Change Interrupt Fall */ | ||
| 81 | #define U2DOTGINT_FID (1 << 4) /* RXCMD OTG ID Change Interrupt Fall */ | ||
| 82 | #define U2DOTGINT_FSE (1 << 3) /* RXCMD OTG Session End Interrupt Fall */ | ||
| 83 | #define U2DOTGINT_FSV (1 << 2) /* RXCMD OTG Session Valid Interrupt Fall */ | ||
| 84 | #define U2DOTGINT_FVV (1 << 1) /* RXCMD OTG Vbus Valid Interrupt Fall */ | ||
| 85 | #define U2DOTGINT_FCK (1 << 0) /* RXCMD Carkit Interrupt Fall */ | ||
| 86 | |||
| 87 | #define U2DOTGUSR (0x002C) /* U2D OTG ULPI Status Register */ | ||
| 88 | #define U2DOTGUSR_LPA (1 << 31) /* ULPI Low Power Mode Active */ | ||
| 89 | #define U2DOTGUSR_S6A (1 << 30) /* ULPI Serial Mode (6-pin) Active */ | ||
| 90 | #define U2DOTGUSR_S3A (1 << 29) /* ULPI Serial Mode (3-pin) Active */ | ||
| 91 | #define U2DOTGUSR_CKA (1 << 28) /* ULPI Car Kit Mode Active */ | ||
| 92 | #define U2DOTGUSR_LS1 (1 << 6) /* RXCMD Linestate 1 Status */ | ||
| 93 | #define U2DOTGUSR_LS0 (1 << 5) /* RXCMD Linestate 0 Status */ | ||
| 94 | #define U2DOTGUSR_ID (1 << 4) /* OTG IDGnd Status */ | ||
| 95 | #define U2DOTGUSR_SE (1 << 3) /* OTG Session End Status */ | ||
| 96 | #define U2DOTGUSR_SV (1 << 2) /* OTG Session Valid Status */ | ||
| 97 | #define U2DOTGUSR_VV (1 << 1) /* OTG Vbus Valid Status */ | ||
| 98 | #define U2DOTGUSR_CK (1 << 0) /* Carkit Interrupt Status */ | ||
| 99 | |||
| 100 | #define U2DOTGUCR (0x0030) /* U2D OTG ULPI Control Register */ | ||
| 101 | #define U2DOTGUCR_RUN (1 << 25) /* RUN */ | ||
| 102 | #define U2DOTGUCR_RNW (1 << 24) /* Read or Write operation */ | ||
| 103 | #define U2DOTGUCR_ADDR (0x3f << 16) /* Address of the ULPI PHY register */ | ||
| 104 | #define U2DOTGUCR_WDATA (0xff << 8) /* The data for a WRITE command */ | ||
| 105 | #define U2DOTGUCR_RDATA (0xff << 0) /* The data for a READ command */ | ||
| 106 | |||
| 107 | #define U2DP3CR (0x0034) /* U2D Port 3 Control Register */ | ||
| 108 | #define U2DP3CR_P2SS (0x3 << 8) /* Host Port 2 Serial Mode Select */ | ||
| 109 | #define U2DP3CR_P3SS (0x7 << 4) /* Host Port 3 Serial Mode Select */ | ||
| 110 | #define U2DP3CR_VPVMBEN (0x1 << 2) /* Host Port 3 Vp/Vm Block Enable */ | ||
| 111 | #define U2DP3CR_CFG (0x3 << 0) /* Host Port 3 Configuration */ | ||
| 112 | |||
| 113 | #define U2DCSR0 (0x0100) /* U2D Control/Status Register - Endpoint 0 */ | ||
| 114 | #define U2DCSR0_IPA (1 << 8) /* IN Packet Adjusted */ | ||
| 115 | #define U2DCSR0_SA (1 << 7) /* SETUP Active */ | ||
| 116 | #define U2DCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ | ||
| 117 | #define U2DCSR0_FST (1 << 5) /* Force Stall */ | ||
| 118 | #define U2DCSR0_SST (1 << 4) /* Send Stall */ | ||
| 119 | #define U2DCSR0_DME (1 << 3) /* DMA Enable */ | ||
| 120 | #define U2DCSR0_FTF (1 << 2) /* Flush Transmit FIFO */ | ||
| 121 | #define U2DCSR0_IPR (1 << 1) /* IN Packet Ready */ | ||
| 122 | #define U2DCSR0_OPC (1 << 0) /* OUT Packet Complete */ | ||
| 123 | |||
| 124 | #define U2DCSR(x) (0x0100 + ((x) << 2)) /* U2D Control/Status Register - Endpoint x */ | ||
| 125 | #define U2DCSR_BF (1 << 10) /* Buffer Full, for OUT eps */ | ||
| 126 | #define U2DCSR_BE (1 << 10) /* Buffer Empty, for IN eps */ | ||
| 127 | #define U2DCSR_DPE (1 << 9) /* Data Packet Error, for ISO eps only */ | ||
| 128 | #define U2DCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ | ||
| 129 | #define U2DCSR_SP (1 << 7) /* Short Packet Control/Status, for OUT eps only, readonly */ | ||
| 130 | #define U2DCSR_BNE (1 << 6) /* Buffer Not Empty, for OUT eps */ | ||
| 131 | #define U2DCSR_BNF (1 << 6) /* Buffer Not Full, for IN eps */ | ||
| 132 | #define U2DCSR_FST (1 << 5) /* Force STALL, write 1 set */ | ||
| 133 | #define U2DCSR_SST (1 << 4) /* Sent STALL, write 1 clear */ | ||
| 134 | #define U2DCSR_DME (1 << 3) /* DMA Enable */ | ||
| 135 | #define U2DCSR_TRN (1 << 2) /* Tx/Rx NAK, write 1 clear */ | ||
| 136 | #define U2DCSR_PC (1 << 1) /* Packet Complete, write 1 clear */ | ||
| 137 | #define U2DCSR_FS (1 << 0) /* FIFO needs Service */ | ||
| 138 | |||
| 139 | #define U2DBCR0 (0x0200) /* U2D Byte Count Register - Endpoint 0 */ | ||
| 140 | #define U2DBCR(x) (0x0200 + ((x) << 2)) /* U2D Byte Count Register - Endpoint x */ | ||
| 141 | |||
| 142 | #define U2DDR0 (0x0300) /* U2D Data Register - Endpoint 0 */ | ||
| 143 | |||
| 144 | #define U2DEPCR(x) (0x0400 + ((x) << 2)) /* U2D Configuration Register - Endpoint x */ | ||
| 145 | #define U2DEPCR_EE (1 << 0) /* Endpoint Enable */ | ||
| 146 | #define U2DEPCR_BS_MASK (0x3FE) /* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */ | ||
| 147 | |||
| 148 | #define U2DSCA (0x0500) /* U2D Setup Command Address */ | ||
| 149 | #define U2DSCA_VALUE (0x0120) | ||
| 150 | |||
| 151 | #define U2DEN0 (0x0504) /* U2D Endpoint Information Register - Endpoint 0 */ | ||
| 152 | #define U2DEN(x) (0x0504 + ((x) << 2)) /* U2D Endpoint Information Register - Endpoint x */ | ||
| 153 | |||
| 154 | /* U2DMA registers */ | ||
| 155 | #define U2DMACSR0 (0x1000) /* U2DMA Control/Status Register - Channel 0 */ | ||
| 156 | #define U2DMACSR(x) (0x1000 + ((x) << 2)) /* U2DMA Control/Status Register - Channel x */ | ||
| 157 | #define U2DMACSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 158 | #define U2DMACSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 159 | #define U2DMACSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 160 | #define U2DMACSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 161 | #define U2DMACSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 162 | #define U2DMACSR_RASIRQEN (1 << 23) /* Request After Cnannel Stopped Interrupt Enable */ | ||
| 163 | #define U2DMACSR_MASKRUN (1 << 22) /* Mask Run */ | ||
| 164 | #define U2DMACSR_SCEMC (3 << 18) /* System Bus Split Completion Error Message Class */ | ||
| 165 | #define U2DMACSR_SCEMI (0x1f << 13) /* System Bus Split Completion Error Message Index */ | ||
| 166 | #define U2DMACSR_BUSERRTYPE (7 << 10) /* PX Bus Error Type */ | ||
| 167 | #define U2DMACSR_EORINTR (1 << 9) /* End Of Receive */ | ||
| 168 | #define U2DMACSR_REQPEND (1 << 8) /* Request Pending */ | ||
| 169 | #define U2DMACSR_RASINTR (1 << 4) /* Request After Channel Stopped (read / write 1 clear) */#define U2DMACSR_STOPINTR (1 << 3) /* Stop Interrupt (read only) */ | ||
| 170 | #define U2DMACSR_ENDINTR (1 << 2) /* End Interrupt (read / write 1 clear) */ | ||
| 171 | #define U2DMACSR_STARTINTR (1 << 1) /* Start Interrupt (read / write 1 clear) */ | ||
| 172 | #define U2DMACSR_BUSERRINTR (1 << 0) /* Bus Error Interrupt (read / write 1 clear) */ | ||
| 173 | |||
| 174 | #define U2DMACR (0x1080) /* U2DMA Control Register */ | ||
| 175 | #define U2DMAINT (0x10F0) /* U2DMA Interrupt Register */ | ||
| 176 | |||
| 177 | #define U2DMABR0 (0x1100) /* U2DMA Branch Register - Channel 0 */ | ||
| 178 | #define U2DMABR(x) (0x1100 + (x) << 2) /* U2DMA Branch Register - Channel x */ | ||
| 179 | |||
| 180 | #define U2DMADADR0 (0x1200) /* U2DMA Descriptor Address Register - Channel 0 */ | ||
| 181 | #define U2DMADADR(x) (0x1200 + (x) * 0x10) /* U2DMA Descriptor Address Register - Channel x */ | ||
| 182 | |||
| 183 | #define U2DMADADR_STOP (1U << 0) | ||
| 184 | |||
| 185 | #define U2DMASADR0 (0x1204) /* U2DMA Source Address Register - Channel 0 */ | ||
| 186 | #define U2DMASADR(x) (0x1204 + (x) * 0x10) /* U2DMA Source Address Register - Channel x */ | ||
| 187 | #define U2DMATADR0 (0x1208) /* U2DMA Target Address Register - Channel 0 */ | ||
| 188 | #define U2DMATADR(x) (0x1208 + (x) * 0x10) /* U2DMA Target Address Register - Channel x */ | ||
| 189 | |||
| 190 | #define U2DMACMDR0 (0x120C) /* U2DMA Command Address Register - Channel 0 */ | ||
| 191 | #define U2DMACMDR(x) (0x120C + (x) * 0x10) /* U2DMA Command Address Register - Channel x */ | ||
| 192 | |||
| 193 | #define U2DMACMDR_XFRDIS (1 << 31) /* Transfer Direction */ | ||
| 194 | #define U2DMACMDR_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 195 | #define U2DMACMDR_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 196 | #define U2DMACMDR_PACKCOMP (1 << 13) /* Packet Complete */ | ||
| 197 | #define U2DMACMDR_LEN (0x07ff) /* length mask (max = 2K - 1) */ | ||
| 198 | |||
| 199 | #endif /* __ASM_ARCH_PXA3xx_U2D_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/treo680.h b/arch/arm/mach-pxa/include/mach/treo680.h deleted file mode 100644 index af443b24d99a..000000000000 --- a/arch/arm/mach-pxa/include/mach/treo680.h +++ /dev/null | |||
| @@ -1,49 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm Treo 680 smartphone | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | */ | ||
| 9 | |||
| 10 | #ifndef _INCLUDE_TREO680_H_ | ||
| 11 | #define _INCLUDE_TREO680_H_ | ||
| 12 | |||
| 13 | /* GPIOs */ | ||
| 14 | #define GPIO_NR_TREO680_POWER_DETECT 0 | ||
| 15 | #define GPIO_NR_TREO680_AMP_EN 27 | ||
| 16 | #define GPIO_NR_TREO680_KEYB_BL 24 | ||
| 17 | #define GPIO_NR_TREO680_VIBRATE_EN 44 | ||
| 18 | #define GPIO_NR_TREO680_GREEN_LED 20 | ||
| 19 | #define GPIO_NR_TREO680_RED_LED 79 | ||
| 20 | #define GPIO_NR_TREO680_SD_DETECT_N 113 | ||
| 21 | #define GPIO_NR_TREO680_SD_READONLY 33 | ||
| 22 | #define GPIO_NR_TREO680_EP_DETECT_N 116 | ||
| 23 | #define GPIO_NR_TREO680_SD_POWER 42 | ||
| 24 | #define GPIO_NR_TREO680_USB_DETECT 1 | ||
| 25 | #define GPIO_NR_TREO680_USB_PULLUP 114 | ||
| 26 | #define GPIO_NR_TREO680_GSM_POWER 40 | ||
| 27 | #define GPIO_NR_TREO680_GSM_RESET 87 | ||
| 28 | #define GPIO_NR_TREO680_GSM_WAKE 57 | ||
| 29 | #define GPIO_NR_TREO680_GSM_HOST_WAKE 14 | ||
| 30 | #define GPIO_NR_TREO680_GSM_TRIGGER 10 | ||
| 31 | #define GPIO_NR_TREO680_BT_EN 43 | ||
| 32 | #define GPIO_NR_TREO680_IR_EN 115 | ||
| 33 | #define GPIO_NR_TREO680_IR_TXD 47 | ||
| 34 | #define GPIO_NR_TREO680_BL_POWER 38 | ||
| 35 | #define GPIO_NR_TREO680_LCD_POWER 25 | ||
| 36 | |||
| 37 | /* Various addresses */ | ||
| 38 | #define TREO680_PHYS_RAM_START 0xa0000000 | ||
| 39 | #define TREO680_PHYS_IO_START 0x40000000 | ||
| 40 | #define TREO680_STR_BASE 0xa2000000 | ||
| 41 | |||
| 42 | /* BACKLIGHT */ | ||
| 43 | #define TREO680_MAX_INTENSITY 254 | ||
| 44 | #define TREO680_DEFAULT_INTENSITY 160 | ||
| 45 | #define TREO680_LIMIT_MASK 0x7F | ||
| 46 | #define TREO680_PRESCALER 63 | ||
| 47 | #define TREO680_PERIOD_NS 3500 | ||
| 48 | |||
| 49 | #endif | ||
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 13848955d133..f28c1715b910 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
| @@ -44,10 +44,10 @@ | |||
| 44 | #include <mach/ssp.h> | 44 | #include <mach/ssp.h> |
| 45 | #include <mach/mmc.h> | 45 | #include <mach/mmc.h> |
| 46 | #include <mach/pxa2xx_spi.h> | 46 | #include <mach/pxa2xx_spi.h> |
| 47 | #include <plat/i2c.h> | ||
| 48 | #include <mach/pxa27x_keypad.h> | 47 | #include <mach/pxa27x_keypad.h> |
| 49 | #include <mach/pxa3xx_nand.h> | ||
| 50 | #include <mach/littleton.h> | 48 | #include <mach/littleton.h> |
| 49 | #include <plat/i2c.h> | ||
| 50 | #include <plat/pxa3xx_nand.h> | ||
| 51 | 51 | ||
| 52 | #include "generic.h" | 52 | #include "generic.h" |
| 53 | 53 | ||
| @@ -413,6 +413,10 @@ static void __init littleton_init(void) | |||
| 413 | /* initialize MFP configurations */ | 413 | /* initialize MFP configurations */ |
| 414 | pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg)); | 414 | pxa3xx_mfp_config(ARRAY_AND_SIZE(littleton_mfp_cfg)); |
| 415 | 415 | ||
| 416 | pxa_set_ffuart_info(NULL); | ||
| 417 | pxa_set_btuart_info(NULL); | ||
| 418 | pxa_set_stuart_info(NULL); | ||
| 419 | |||
| 416 | /* | 420 | /* |
| 417 | * Note: we depend bootloader set the correct | 421 | * Note: we depend bootloader set the correct |
| 418 | * value to MSC register for SMC91x. | 422 | * value to MSC register for SMC91x. |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index d64395f26a3e..1373c22dbb83 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
| @@ -455,6 +455,10 @@ static void __init lpd270_init(void) | |||
| 455 | { | 455 | { |
| 456 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config)); | 456 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config)); |
| 457 | 457 | ||
| 458 | pxa_set_ffuart_info(NULL); | ||
| 459 | pxa_set_btuart_info(NULL); | ||
| 460 | pxa_set_stuart_info(NULL); | ||
| 461 | |||
| 458 | lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | 462 | lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; |
| 459 | lpd270_flash_data[1].width = 4; | 463 | lpd270_flash_data[1].width = 4; |
| 460 | 464 | ||
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index c6a94d3fdd61..98ee7e590299 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -518,6 +518,10 @@ static void __init lubbock_init(void) | |||
| 518 | 518 | ||
| 519 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); | 519 | pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); |
| 520 | 520 | ||
| 521 | pxa_set_ffuart_info(NULL); | ||
| 522 | pxa_set_btuart_info(NULL); | ||
| 523 | pxa_set_stuart_info(NULL); | ||
| 524 | |||
| 521 | clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); | 525 | clk_add_alias("SA1111_CLK", NULL, "GPIO11_CLK", NULL); |
| 522 | pxa_set_udc_info(&udc_info); | 526 | pxa_set_udc_info(&udc_info); |
| 523 | set_pxa_fb_info(&sharp_lm8v31); | 527 | set_pxa_fb_info(&sharp_lm8v31); |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 5360c07f5138..8a38d604dc77 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
| @@ -742,6 +742,10 @@ static void __init magician_init(void) | |||
| 742 | 742 | ||
| 743 | pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config)); | 743 | pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config)); |
| 744 | 744 | ||
| 745 | pxa_set_ffuart_info(NULL); | ||
| 746 | pxa_set_btuart_info(NULL); | ||
| 747 | pxa_set_stuart_info(NULL); | ||
| 748 | |||
| 745 | platform_add_devices(ARRAY_AND_SIZE(devices)); | 749 | platform_add_devices(ARRAY_AND_SIZE(devices)); |
| 746 | 750 | ||
| 747 | err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN"); | 751 | err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN"); |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index a4eeae345e64..851ee0fc32e2 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
| @@ -576,6 +576,10 @@ static void __init mainstone_init(void) | |||
| 576 | 576 | ||
| 577 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); | 577 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); |
| 578 | 578 | ||
| 579 | pxa_set_ffuart_info(NULL); | ||
| 580 | pxa_set_btuart_info(NULL); | ||
| 581 | pxa_set_stuart_info(NULL); | ||
| 582 | |||
| 579 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; | 583 | mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4; |
| 580 | mst_flash_data[1].width = 4; | 584 | mst_flash_data[1].width = 4; |
| 581 | 585 | ||
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 3cab452e5567..2466a44d8fda 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
| @@ -798,6 +798,9 @@ static void __init mioa701_machine_init(void) | |||
| 798 | UP2OCR = UP2OCR_HXOE; | 798 | UP2OCR = UP2OCR_HXOE; |
| 799 | 799 | ||
| 800 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config)); | 800 | pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config)); |
| 801 | pxa_set_ffuart_info(NULL); | ||
| 802 | pxa_set_btuart_info(NULL); | ||
| 803 | pxa_set_stuart_info(NULL); | ||
| 801 | mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); | 804 | mio_gpio_request(ARRAY_AND_SIZE(global_gpios)); |
| 802 | bootstrap_init(); | 805 | bootstrap_init(); |
| 803 | set_pxa_fb_info(&mioa701_pxafb_info); | 806 | set_pxa_fb_info(&mioa701_pxafb_info); |
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index a65713ce019e..6d4503927a76 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c | |||
| @@ -84,6 +84,9 @@ static struct platform_device *devices[] __initdata = { | |||
| 84 | static void __init mp900c_init(void) | 84 | static void __init mp900c_init(void) |
| 85 | { | 85 | { |
| 86 | printk(KERN_INFO "MobilePro 900/C machine init\n"); | 86 | printk(KERN_INFO "MobilePro 900/C machine init\n"); |
| 87 | pxa_set_ffuart_info(NULL); | ||
| 88 | pxa_set_btuart_info(NULL); | ||
| 89 | pxa_set_stuart_info(NULL); | ||
| 87 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 90 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 88 | } | 91 | } |
| 89 | 92 | ||
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c index 1ad029dd4438..59140217890a 100644 --- a/arch/arm/mach-pxa/palmld.c +++ b/arch/arm/mach-pxa/palmld.c | |||
| @@ -530,6 +530,10 @@ static void __init palmld_init(void) | |||
| 530 | { | 530 | { |
| 531 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); | 531 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); |
| 532 | 532 | ||
| 533 | pxa_set_ffuart_info(NULL); | ||
| 534 | pxa_set_btuart_info(NULL); | ||
| 535 | pxa_set_stuart_info(NULL); | ||
| 536 | |||
| 533 | palmld_pm_init(); | 537 | palmld_pm_init(); |
| 534 | set_pxa_fb_info(&palmld_lcd_screen); | 538 | set_pxa_fb_info(&palmld_lcd_screen); |
| 535 | pxa_set_mci_info(&palmld_mci_platform_data); | 539 | pxa_set_mci_info(&palmld_mci_platform_data); |
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c index 2dd7ce28556b..7f89ca20f13a 100644 --- a/arch/arm/mach-pxa/palmt5.c +++ b/arch/arm/mach-pxa/palmt5.c | |||
| @@ -419,6 +419,10 @@ static void __init palmt5_init(void) | |||
| 419 | { | 419 | { |
| 420 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); | 420 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); |
| 421 | 421 | ||
| 422 | pxa_set_ffuart_info(NULL); | ||
| 423 | pxa_set_btuart_info(NULL); | ||
| 424 | pxa_set_stuart_info(NULL); | ||
| 425 | |||
| 422 | palmt5_pm_init(); | 426 | palmt5_pm_init(); |
| 423 | set_pxa_fb_info(&palmt5_lcd_screen); | 427 | set_pxa_fb_info(&palmt5_lcd_screen); |
| 424 | pxa_set_mci_info(&palmt5_mci_platform_data); | 428 | pxa_set_mci_info(&palmt5_mci_platform_data); |
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c index 0b92291a58f6..308417592007 100644 --- a/arch/arm/mach-pxa/palmtc.c +++ b/arch/arm/mach-pxa/palmtc.c | |||
| @@ -416,6 +416,11 @@ static void __init palmtc_init(void) | |||
| 416 | { | 416 | { |
| 417 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); | 417 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config)); |
| 418 | 418 | ||
| 419 | pxa_set_ffuart_info(NULL); | ||
| 420 | pxa_set_btuart_info(NULL); | ||
| 421 | pxa_set_stuart_info(NULL); | ||
| 422 | pxa_set_hwuart_info(NULL); | ||
| 423 | |||
| 419 | set_pxa_fb_info(&palmtc_lcd_screen); | 424 | set_pxa_fb_info(&palmtc_lcd_screen); |
| 420 | pxa_set_mci_info(&palmtc_mci_platform_data); | 425 | pxa_set_mci_info(&palmtc_mci_platform_data); |
| 421 | pxa_set_udc_info(&palmtc_udc_info); | 426 | pxa_set_udc_info(&palmtc_udc_info); |
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c index 277c4062e3c6..265d62bae7de 100644 --- a/arch/arm/mach-pxa/palmte2.c +++ b/arch/arm/mach-pxa/palmte2.c | |||
| @@ -373,6 +373,10 @@ static void __init palmte2_init(void) | |||
| 373 | { | 373 | { |
| 374 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmte2_pin_config)); | 374 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmte2_pin_config)); |
| 375 | 375 | ||
| 376 | pxa_set_ffuart_info(NULL); | ||
| 377 | pxa_set_btuart_info(NULL); | ||
| 378 | pxa_set_stuart_info(NULL); | ||
| 379 | |||
| 376 | set_pxa_fb_info(&palmte2_lcd_screen); | 380 | set_pxa_fb_info(&palmte2_lcd_screen); |
| 377 | pxa_set_mci_info(&palmte2_mci_platform_data); | 381 | pxa_set_mci_info(&palmte2_mci_platform_data); |
| 378 | palmte2_udc_init(); | 382 | palmte2_udc_init(); |
diff --git a/arch/arm/mach-pxa/treo680.c b/arch/arm/mach-pxa/palmtreo.c index fe085076fbf2..606eb7e8a17e 100644 --- a/arch/arm/mach-pxa/treo680.c +++ b/arch/arm/mach-pxa/palmtreo.c | |||
| @@ -1,5 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Hardware definitions for Palm Treo 680 | 2 | * Hardware definitions for Palm Treo smartphones |
| 3 | * | ||
| 4 | * currently supported: | ||
| 5 | * Palm Treo 680 (GSM) | ||
| 6 | * Palm Centro 685 (GSM) | ||
| 3 | * | 7 | * |
| 4 | * Author: Tomas Cech <sleep_walker@suse.cz> | 8 | * Author: Tomas Cech <sleep_walker@suse.cz> |
| 5 | * | 9 | * |
| @@ -31,7 +35,7 @@ | |||
| 31 | #include <mach/pxa27x.h> | 35 | #include <mach/pxa27x.h> |
| 32 | #include <mach/pxa27x-udc.h> | 36 | #include <mach/pxa27x-udc.h> |
| 33 | #include <mach/audio.h> | 37 | #include <mach/audio.h> |
| 34 | #include <mach/treo680.h> | 38 | #include <mach/palmtreo.h> |
| 35 | #include <mach/mmc.h> | 39 | #include <mach/mmc.h> |
| 36 | #include <mach/pxafb.h> | 40 | #include <mach/pxafb.h> |
| 37 | #include <mach/irda.h> | 41 | #include <mach/irda.h> |
| @@ -50,7 +54,7 @@ | |||
| 50 | /****************************************************************************** | 54 | /****************************************************************************** |
| 51 | * Pin configuration | 55 | * Pin configuration |
| 52 | ******************************************************************************/ | 56 | ******************************************************************************/ |
| 53 | static unsigned long treo680_pin_config[] __initdata = { | 57 | static unsigned long treo_pin_config[] __initdata = { |
| 54 | /* MMC */ | 58 | /* MMC */ |
| 55 | GPIO32_MMC_CLK, | 59 | GPIO32_MMC_CLK, |
| 56 | GPIO92_MMC_DAT_0, | 60 | GPIO92_MMC_DAT_0, |
| @@ -58,7 +62,6 @@ static unsigned long treo680_pin_config[] __initdata = { | |||
| 58 | GPIO110_MMC_DAT_2, | 62 | GPIO110_MMC_DAT_2, |
| 59 | GPIO111_MMC_DAT_3, | 63 | GPIO111_MMC_DAT_3, |
| 60 | GPIO112_MMC_CMD, | 64 | GPIO112_MMC_CMD, |
| 61 | GPIO33_GPIO, /* SD read only */ | ||
| 62 | GPIO113_GPIO, /* SD detect */ | 65 | GPIO113_GPIO, /* SD detect */ |
| 63 | 66 | ||
| 64 | /* AC97 */ | 67 | /* AC97 */ |
| @@ -80,12 +83,10 @@ static unsigned long treo680_pin_config[] __initdata = { | |||
| 80 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ | 83 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* usb detect */ |
| 81 | 84 | ||
| 82 | /* MATRIX KEYPAD */ | 85 | /* MATRIX KEYPAD */ |
| 83 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
| 84 | GPIO101_KP_MKIN_1, | 86 | GPIO101_KP_MKIN_1, |
| 85 | GPIO102_KP_MKIN_2, | 87 | GPIO102_KP_MKIN_2, |
| 86 | GPIO97_KP_MKIN_3, | 88 | GPIO97_KP_MKIN_3, |
| 87 | GPIO98_KP_MKIN_4, | 89 | GPIO98_KP_MKIN_4, |
| 88 | GPIO99_KP_MKIN_5, | ||
| 89 | GPIO91_KP_MKIN_6, | 90 | GPIO91_KP_MKIN_6, |
| 90 | GPIO13_KP_MKIN_7, | 91 | GPIO13_KP_MKIN_7, |
| 91 | GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, | 92 | GPIO103_KP_MKOUT_0 | MFP_LPM_DRIVE_HIGH, |
| @@ -150,19 +151,57 @@ static unsigned long treo680_pin_config[] __initdata = { | |||
| 150 | GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ | 151 | GPIO11_GPIO | WAKEUP_ON_EDGE_BOTH, /* bluetooth host wake up */ |
| 151 | }; | 152 | }; |
| 152 | 153 | ||
| 154 | #ifdef CONFIG_MACH_TREO680 | ||
| 155 | static unsigned long treo680_pin_config[] __initdata = { | ||
| 156 | GPIO33_GPIO, /* SD read only */ | ||
| 157 | |||
| 158 | /* MATRIX KEYPAD - different wake up source */ | ||
| 159 | GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH, | ||
| 160 | GPIO99_KP_MKIN_5, | ||
| 161 | }; | ||
| 162 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 163 | |||
| 164 | #ifdef CONFIG_MACH_CENTRO | ||
| 165 | static unsigned long centro685_pin_config[] __initdata = { | ||
| 166 | /* Bluetooth attached to BT UART*/ | ||
| 167 | MFP_CFG_OUT(GPIO80, AF0, DRIVE_LOW), /* power: LOW = off */ | ||
| 168 | GPIO42_BTUART_RXD, | ||
| 169 | GPIO43_BTUART_TXD, | ||
| 170 | GPIO44_BTUART_CTS, | ||
| 171 | GPIO45_BTUART_RTS, | ||
| 172 | |||
| 173 | /* MATRIX KEYPAD - different wake up source */ | ||
| 174 | GPIO100_KP_MKIN_0, | ||
| 175 | GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH, | ||
| 176 | }; | ||
| 177 | #endif /* CONFIG_MACH_CENTRO */ | ||
| 178 | |||
| 153 | /****************************************************************************** | 179 | /****************************************************************************** |
| 154 | * SD/MMC card controller | 180 | * SD/MMC card controller |
| 155 | ******************************************************************************/ | 181 | ******************************************************************************/ |
| 182 | #ifdef CONFIG_MACH_TREO680 | ||
| 156 | static struct pxamci_platform_data treo680_mci_platform_data = { | 183 | static struct pxamci_platform_data treo680_mci_platform_data = { |
| 157 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | 184 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 158 | .gpio_card_detect = GPIO_NR_TREO680_SD_DETECT_N, | 185 | .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, |
| 159 | .gpio_card_ro = GPIO_NR_TREO680_SD_READONLY, | 186 | .gpio_card_ro = GPIO_NR_TREO680_SD_READONLY, |
| 160 | .gpio_power = GPIO_NR_TREO680_SD_POWER, | 187 | .gpio_power = GPIO_NR_TREO680_SD_POWER, |
| 161 | }; | 188 | }; |
| 189 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 190 | |||
| 191 | #ifdef CONFIG_MACH_CENTRO | ||
| 192 | static struct pxamci_platform_data centro_mci_platform_data = { | ||
| 193 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 194 | .gpio_card_detect = GPIO_NR_TREO_SD_DETECT_N, | ||
| 195 | .gpio_card_ro = -1, | ||
| 196 | .gpio_power = GPIO_NR_CENTRO_SD_POWER, | ||
| 197 | .gpio_power_invert = 1, | ||
| 198 | }; | ||
| 199 | #endif /* CONFIG_MACH_CENTRO */ | ||
| 162 | 200 | ||
| 163 | /****************************************************************************** | 201 | /****************************************************************************** |
| 164 | * GPIO keyboard | 202 | * GPIO keyboard |
| 165 | ******************************************************************************/ | 203 | ******************************************************************************/ |
| 204 | #ifdef CONFIG_MACH_TREO680 | ||
| 166 | static unsigned int treo680_matrix_keys[] = { | 205 | static unsigned int treo680_matrix_keys[] = { |
| 167 | KEY(0, 0, KEY_F8), /* Red/Off/Power */ | 206 | KEY(0, 0, KEY_F8), /* Red/Off/Power */ |
| 168 | KEY(0, 1, KEY_LEFT), | 207 | KEY(0, 1, KEY_LEFT), |
| @@ -232,92 +271,167 @@ static struct pxa27x_keypad_platform_data treo680_keypad_platform_data = { | |||
| 232 | 271 | ||
| 233 | .debounce_interval = 30, | 272 | .debounce_interval = 30, |
| 234 | }; | 273 | }; |
| 274 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 275 | |||
| 276 | #ifdef CONFIG_MACH_CENTRO | ||
| 277 | static unsigned int centro_matrix_keys[] = { | ||
| 278 | KEY(0, 0, KEY_F9), /* Home */ | ||
| 279 | KEY(0, 1, KEY_LEFT), | ||
| 280 | KEY(0, 2, KEY_LEFTCTRL), /* Alternate */ | ||
| 281 | KEY(0, 3, KEY_L), | ||
| 282 | KEY(0, 4, KEY_A), | ||
| 283 | KEY(0, 5, KEY_Q), | ||
| 284 | KEY(0, 6, KEY_P), | ||
| 285 | |||
| 286 | KEY(1, 0, KEY_RIGHTCTRL), /* Menu */ | ||
| 287 | KEY(1, 1, KEY_RIGHT), | ||
| 288 | KEY(1, 2, KEY_LEFTSHIFT), /* Left shift */ | ||
| 289 | KEY(1, 3, KEY_Z), | ||
| 290 | KEY(1, 4, KEY_S), | ||
| 291 | KEY(1, 5, KEY_W), | ||
| 292 | |||
| 293 | KEY(2, 0, KEY_F1), /* Phone */ | ||
| 294 | KEY(2, 1, KEY_UP), | ||
| 295 | KEY(2, 2, KEY_0), | ||
| 296 | KEY(2, 3, KEY_X), | ||
| 297 | KEY(2, 4, KEY_D), | ||
| 298 | KEY(2, 5, KEY_E), | ||
| 299 | |||
| 300 | KEY(3, 0, KEY_F10), /* Calendar */ | ||
| 301 | KEY(3, 1, KEY_DOWN), | ||
| 302 | KEY(3, 2, KEY_SPACE), | ||
| 303 | KEY(3, 3, KEY_C), | ||
| 304 | KEY(3, 4, KEY_F), | ||
| 305 | KEY(3, 5, KEY_R), | ||
| 306 | |||
| 307 | KEY(4, 0, KEY_F12), /* Mail */ | ||
| 308 | KEY(4, 1, KEY_KPENTER), | ||
| 309 | KEY(4, 2, KEY_RIGHTALT), /* Alt */ | ||
| 310 | KEY(4, 3, KEY_V), | ||
| 311 | KEY(4, 4, KEY_G), | ||
| 312 | KEY(4, 5, KEY_T), | ||
| 313 | |||
| 314 | KEY(5, 0, KEY_F8), /* Red/Off/Power */ | ||
| 315 | KEY(5, 1, KEY_PAGEUP), /* Side up */ | ||
| 316 | KEY(5, 2, KEY_DOT), | ||
| 317 | KEY(5, 3, KEY_B), | ||
| 318 | KEY(5, 4, KEY_H), | ||
| 319 | KEY(5, 5, KEY_Y), | ||
| 320 | |||
| 321 | KEY(6, 0, KEY_TAB), /* Side Activate */ | ||
| 322 | KEY(6, 1, KEY_PAGEDOWN), /* Side down */ | ||
| 323 | KEY(6, 2, KEY_ENTER), | ||
| 324 | KEY(6, 3, KEY_N), | ||
| 325 | KEY(6, 4, KEY_J), | ||
| 326 | KEY(6, 5, KEY_U), | ||
| 327 | |||
| 328 | KEY(7, 0, KEY_F6), /* Green/Call */ | ||
| 329 | KEY(7, 1, KEY_O), | ||
| 330 | KEY(7, 2, KEY_BACKSPACE), | ||
| 331 | KEY(7, 3, KEY_M), | ||
| 332 | KEY(7, 4, KEY_K), | ||
| 333 | KEY(7, 5, KEY_I), | ||
| 334 | }; | ||
| 335 | |||
| 336 | static struct pxa27x_keypad_platform_data centro_keypad_platform_data = { | ||
| 337 | .matrix_key_rows = 8, | ||
| 338 | .matrix_key_cols = 7, | ||
| 339 | .matrix_key_map = centro_matrix_keys, | ||
| 340 | .matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys), | ||
| 341 | .direct_key_map = { KEY_CONNECT }, | ||
| 342 | .direct_key_num = 1, | ||
| 343 | |||
| 344 | .debounce_interval = 30, | ||
| 345 | }; | ||
| 346 | #endif /* CONFIG_MACH_CENTRO */ | ||
| 235 | 347 | ||
| 236 | /****************************************************************************** | 348 | /****************************************************************************** |
| 237 | * aSoC audio | 349 | * aSoC audio |
| 238 | ******************************************************************************/ | 350 | ******************************************************************************/ |
| 239 | 351 | ||
| 240 | static pxa2xx_audio_ops_t treo680_ac97_pdata = { | 352 | static pxa2xx_audio_ops_t treo_ac97_pdata = { |
| 241 | .reset_gpio = 95, | 353 | .reset_gpio = 95, |
| 242 | }; | 354 | }; |
| 243 | 355 | ||
| 244 | /****************************************************************************** | 356 | /****************************************************************************** |
| 245 | * Backlight | 357 | * Backlight |
| 246 | ******************************************************************************/ | 358 | ******************************************************************************/ |
| 247 | static int treo680_backlight_init(struct device *dev) | 359 | static int treo_backlight_init(struct device *dev) |
| 248 | { | 360 | { |
| 249 | int ret; | 361 | int ret; |
| 250 | 362 | ||
| 251 | ret = gpio_request(GPIO_NR_TREO680_BL_POWER, "BL POWER"); | 363 | ret = gpio_request(GPIO_NR_TREO_BL_POWER, "BL POWER"); |
| 252 | if (ret) | 364 | if (ret) |
| 253 | goto err; | 365 | goto err; |
| 254 | ret = gpio_direction_output(GPIO_NR_TREO680_BL_POWER, 0); | 366 | ret = gpio_direction_output(GPIO_NR_TREO_BL_POWER, 0); |
| 255 | if (ret) | 367 | if (ret) |
| 256 | goto err2; | 368 | goto err2; |
| 257 | 369 | ||
| 258 | return 0; | 370 | return 0; |
| 259 | 371 | ||
| 260 | err2: | 372 | err2: |
| 261 | gpio_free(GPIO_NR_TREO680_BL_POWER); | 373 | gpio_free(GPIO_NR_TREO_BL_POWER); |
| 262 | err: | 374 | err: |
| 263 | return ret; | 375 | return ret; |
| 264 | } | 376 | } |
| 265 | 377 | ||
| 266 | static int treo680_backlight_notify(int brightness) | 378 | static int treo_backlight_notify(int brightness) |
| 267 | { | 379 | { |
| 268 | gpio_set_value(GPIO_NR_TREO680_BL_POWER, brightness); | 380 | gpio_set_value(GPIO_NR_TREO_BL_POWER, brightness); |
| 269 | return TREO680_MAX_INTENSITY - brightness; | 381 | return TREO_MAX_INTENSITY - brightness; |
| 270 | }; | 382 | }; |
| 271 | 383 | ||
| 272 | static void treo680_backlight_exit(struct device *dev) | 384 | static void treo_backlight_exit(struct device *dev) |
| 273 | { | 385 | { |
| 274 | gpio_free(GPIO_NR_TREO680_BL_POWER); | 386 | gpio_free(GPIO_NR_TREO_BL_POWER); |
| 275 | } | 387 | } |
| 276 | 388 | ||
| 277 | static struct platform_pwm_backlight_data treo680_backlight_data = { | 389 | static struct platform_pwm_backlight_data treo_backlight_data = { |
| 278 | .pwm_id = 0, | 390 | .pwm_id = 0, |
| 279 | .max_brightness = TREO680_MAX_INTENSITY, | 391 | .max_brightness = TREO_MAX_INTENSITY, |
| 280 | .dft_brightness = TREO680_DEFAULT_INTENSITY, | 392 | .dft_brightness = TREO_DEFAULT_INTENSITY, |
| 281 | .pwm_period_ns = TREO680_PERIOD_NS, | 393 | .pwm_period_ns = TREO_PERIOD_NS, |
| 282 | .init = treo680_backlight_init, | 394 | .init = treo_backlight_init, |
| 283 | .notify = treo680_backlight_notify, | 395 | .notify = treo_backlight_notify, |
| 284 | .exit = treo680_backlight_exit, | 396 | .exit = treo_backlight_exit, |
| 285 | }; | 397 | }; |
| 286 | 398 | ||
| 287 | static struct platform_device treo680_backlight = { | 399 | static struct platform_device treo_backlight = { |
| 288 | .name = "pwm-backlight", | 400 | .name = "pwm-backlight", |
| 289 | .dev = { | 401 | .dev = { |
| 290 | .parent = &pxa27x_device_pwm0.dev, | 402 | .parent = &pxa27x_device_pwm0.dev, |
| 291 | .platform_data = &treo680_backlight_data, | 403 | .platform_data = &treo_backlight_data, |
| 292 | }, | 404 | }, |
| 293 | }; | 405 | }; |
| 294 | 406 | ||
| 295 | /****************************************************************************** | 407 | /****************************************************************************** |
| 296 | * IrDA | 408 | * IrDA |
| 297 | ******************************************************************************/ | 409 | ******************************************************************************/ |
| 298 | static struct pxaficp_platform_data treo680_ficp_info = { | 410 | static struct pxaficp_platform_data treo_ficp_info = { |
| 299 | .gpio_pwdown = GPIO_NR_TREO680_IR_EN, | 411 | .gpio_pwdown = GPIO_NR_TREO_IR_EN, |
| 300 | .transceiver_cap = IR_SIRMODE | IR_OFF, | 412 | .transceiver_cap = IR_SIRMODE | IR_OFF, |
| 301 | }; | 413 | }; |
| 302 | 414 | ||
| 303 | /****************************************************************************** | 415 | /****************************************************************************** |
| 304 | * UDC | 416 | * UDC |
| 305 | ******************************************************************************/ | 417 | ******************************************************************************/ |
| 306 | static struct pxa2xx_udc_mach_info treo680_udc_info __initdata = { | 418 | static struct pxa2xx_udc_mach_info treo_udc_info __initdata = { |
| 307 | .gpio_vbus = GPIO_NR_TREO680_USB_DETECT, | 419 | .gpio_vbus = GPIO_NR_TREO_USB_DETECT, |
| 308 | .gpio_vbus_inverted = 1, | 420 | .gpio_vbus_inverted = 1, |
| 309 | .gpio_pullup = GPIO_NR_TREO680_USB_PULLUP, | 421 | .gpio_pullup = GPIO_NR_TREO_USB_PULLUP, |
| 310 | }; | 422 | }; |
| 311 | 423 | ||
| 312 | 424 | ||
| 313 | /****************************************************************************** | 425 | /****************************************************************************** |
| 314 | * USB host | 426 | * USB host |
| 315 | ******************************************************************************/ | 427 | ******************************************************************************/ |
| 428 | #ifdef CONFIG_MACH_TREO680 | ||
| 316 | static struct pxaohci_platform_data treo680_ohci_info = { | 429 | static struct pxaohci_platform_data treo680_ohci_info = { |
| 317 | .port_mode = PMM_PERPORT_MODE, | 430 | .port_mode = PMM_PERPORT_MODE, |
| 318 | .flags = ENABLE_PORT1 | ENABLE_PORT3, | 431 | .flags = ENABLE_PORT1 | ENABLE_PORT3, |
| 319 | .power_budget = 0, | 432 | .power_budget = 0, |
| 320 | }; | 433 | }; |
| 434 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 321 | 435 | ||
| 322 | /****************************************************************************** | 436 | /****************************************************************************** |
| 323 | * Power supply | 437 | * Power supply |
| @@ -326,41 +440,41 @@ static int power_supply_init(struct device *dev) | |||
| 326 | { | 440 | { |
| 327 | int ret; | 441 | int ret; |
| 328 | 442 | ||
| 329 | ret = gpio_request(GPIO_NR_TREO680_POWER_DETECT, "CABLE_STATE_AC"); | 443 | ret = gpio_request(GPIO_NR_TREO_POWER_DETECT, "CABLE_STATE_AC"); |
| 330 | if (ret) | 444 | if (ret) |
| 331 | goto err1; | 445 | goto err1; |
| 332 | ret = gpio_direction_input(GPIO_NR_TREO680_POWER_DETECT); | 446 | ret = gpio_direction_input(GPIO_NR_TREO_POWER_DETECT); |
| 333 | if (ret) | 447 | if (ret) |
| 334 | goto err2; | 448 | goto err2; |
| 335 | 449 | ||
| 336 | return 0; | 450 | return 0; |
| 337 | 451 | ||
| 338 | err2: | 452 | err2: |
| 339 | gpio_free(GPIO_NR_TREO680_POWER_DETECT); | 453 | gpio_free(GPIO_NR_TREO_POWER_DETECT); |
| 340 | err1: | 454 | err1: |
| 341 | return ret; | 455 | return ret; |
| 342 | } | 456 | } |
| 343 | 457 | ||
| 344 | static int treo680_is_ac_online(void) | 458 | static int treo_is_ac_online(void) |
| 345 | { | 459 | { |
| 346 | return gpio_get_value(GPIO_NR_TREO680_POWER_DETECT); | 460 | return gpio_get_value(GPIO_NR_TREO_POWER_DETECT); |
| 347 | } | 461 | } |
| 348 | 462 | ||
| 349 | static void power_supply_exit(struct device *dev) | 463 | static void power_supply_exit(struct device *dev) |
| 350 | { | 464 | { |
| 351 | gpio_free(GPIO_NR_TREO680_POWER_DETECT); | 465 | gpio_free(GPIO_NR_TREO_POWER_DETECT); |
| 352 | } | 466 | } |
| 353 | 467 | ||
| 354 | static char *treo680_supplicants[] = { | 468 | static char *treo_supplicants[] = { |
| 355 | "main-battery", | 469 | "main-battery", |
| 356 | }; | 470 | }; |
| 357 | 471 | ||
| 358 | static struct pda_power_pdata power_supply_info = { | 472 | static struct pda_power_pdata power_supply_info = { |
| 359 | .init = power_supply_init, | 473 | .init = power_supply_init, |
| 360 | .is_ac_online = treo680_is_ac_online, | 474 | .is_ac_online = treo_is_ac_online, |
| 361 | .exit = power_supply_exit, | 475 | .exit = power_supply_exit, |
| 362 | .supplied_to = treo680_supplicants, | 476 | .supplied_to = treo_supplicants, |
| 363 | .num_supplicants = ARRAY_SIZE(treo680_supplicants), | 477 | .num_supplicants = ARRAY_SIZE(treo_supplicants), |
| 364 | }; | 478 | }; |
| 365 | 479 | ||
| 366 | static struct platform_device power_supply = { | 480 | static struct platform_device power_supply = { |
| @@ -374,7 +488,8 @@ static struct platform_device power_supply = { | |||
| 374 | /****************************************************************************** | 488 | /****************************************************************************** |
| 375 | * Vibra and LEDs | 489 | * Vibra and LEDs |
| 376 | ******************************************************************************/ | 490 | ******************************************************************************/ |
| 377 | static struct gpio_led gpio_leds[] = { | 491 | #ifdef CONFIG_MACH_TREO680 |
| 492 | static struct gpio_led treo680_gpio_leds[] = { | ||
| 378 | { | 493 | { |
| 379 | .name = "treo680:vibra:vibra", | 494 | .name = "treo680:vibra:vibra", |
| 380 | .default_trigger = "none", | 495 | .default_trigger = "none", |
| @@ -383,34 +498,68 @@ static struct gpio_led gpio_leds[] = { | |||
| 383 | { | 498 | { |
| 384 | .name = "treo680:green:led", | 499 | .name = "treo680:green:led", |
| 385 | .default_trigger = "mmc0", | 500 | .default_trigger = "mmc0", |
| 386 | .gpio = GPIO_NR_TREO680_GREEN_LED, | 501 | .gpio = GPIO_NR_TREO_GREEN_LED, |
| 387 | }, | 502 | }, |
| 388 | { | 503 | { |
| 389 | .name = "treo680:keybbl:keybbl", | 504 | .name = "treo680:white:keybbl", |
| 390 | .default_trigger = "none", | 505 | .default_trigger = "none", |
| 391 | .gpio = GPIO_NR_TREO680_KEYB_BL, | 506 | .gpio = GPIO_NR_TREO680_KEYB_BL, |
| 392 | }, | 507 | }, |
| 393 | }; | 508 | }; |
| 394 | 509 | ||
| 395 | static struct gpio_led_platform_data gpio_led_info = { | 510 | static struct gpio_led_platform_data treo680_gpio_led_info = { |
| 396 | .leds = gpio_leds, | 511 | .leds = treo680_gpio_leds, |
| 397 | .num_leds = ARRAY_SIZE(gpio_leds), | 512 | .num_leds = ARRAY_SIZE(treo680_gpio_leds), |
| 398 | }; | 513 | }; |
| 399 | 514 | ||
| 400 | static struct platform_device treo680_leds = { | 515 | static struct platform_device treo680_leds = { |
| 401 | .name = "leds-gpio", | 516 | .name = "leds-gpio", |
| 402 | .id = -1, | 517 | .id = -1, |
| 403 | .dev = { | 518 | .dev = { |
| 404 | .platform_data = &gpio_led_info, | 519 | .platform_data = &treo680_gpio_led_info, |
| 405 | } | 520 | } |
| 406 | }; | 521 | }; |
| 522 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 407 | 523 | ||
| 524 | #ifdef CONFIG_MACH_CENTRO | ||
| 525 | static struct gpio_led centro_gpio_leds[] = { | ||
| 526 | { | ||
| 527 | .name = "centro:vibra:vibra", | ||
| 528 | .default_trigger = "none", | ||
| 529 | .gpio = GPIO_NR_CENTRO_VIBRATE_EN, | ||
| 530 | }, | ||
| 531 | { | ||
| 532 | .name = "centro:green:led", | ||
| 533 | .default_trigger = "mmc0", | ||
| 534 | .gpio = GPIO_NR_TREO_GREEN_LED, | ||
| 535 | }, | ||
| 536 | { | ||
| 537 | .name = "centro:white:keybbl", | ||
| 538 | .default_trigger = "none", | ||
| 539 | .active_low = 1, | ||
| 540 | .gpio = GPIO_NR_CENTRO_KEYB_BL, | ||
| 541 | }, | ||
| 542 | }; | ||
| 543 | |||
| 544 | static struct gpio_led_platform_data centro_gpio_led_info = { | ||
| 545 | .leds = centro_gpio_leds, | ||
| 546 | .num_leds = ARRAY_SIZE(centro_gpio_leds), | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct platform_device centro_leds = { | ||
| 550 | .name = "leds-gpio", | ||
| 551 | .id = -1, | ||
| 552 | .dev = { | ||
| 553 | .platform_data = ¢ro_gpio_led_info, | ||
| 554 | } | ||
| 555 | }; | ||
| 556 | #endif /* CONFIG_MACH_CENTRO */ | ||
| 408 | 557 | ||
| 409 | /****************************************************************************** | 558 | /****************************************************************************** |
| 410 | * Framebuffer | 559 | * Framebuffer |
| 411 | ******************************************************************************/ | 560 | ******************************************************************************/ |
| 412 | /* TODO: add support for 324x324 */ | 561 | /* TODO: add support for 324x324 */ |
| 413 | static struct pxafb_mode_info treo680_lcd_modes[] = { | 562 | static struct pxafb_mode_info treo_lcd_modes[] = { |
| 414 | { | 563 | { |
| 415 | .pixclock = 86538, | 564 | .pixclock = 86538, |
| 416 | .xres = 320, | 565 | .xres = 320, |
| @@ -427,21 +576,21 @@ static struct pxafb_mode_info treo680_lcd_modes[] = { | |||
| 427 | }, | 576 | }, |
| 428 | }; | 577 | }; |
| 429 | 578 | ||
| 430 | static void treo680_lcd_power(int on, struct fb_var_screeninfo *info) | 579 | static void treo_lcd_power(int on, struct fb_var_screeninfo *info) |
| 431 | { | 580 | { |
| 432 | gpio_set_value(GPIO_NR_TREO680_BL_POWER, on); | 581 | gpio_set_value(GPIO_NR_TREO_BL_POWER, on); |
| 433 | } | 582 | } |
| 434 | 583 | ||
| 435 | static struct pxafb_mach_info treo680_lcd_screen = { | 584 | static struct pxafb_mach_info treo_lcd_screen = { |
| 436 | .modes = treo680_lcd_modes, | 585 | .modes = treo_lcd_modes, |
| 437 | .num_modes = ARRAY_SIZE(treo680_lcd_modes), | 586 | .num_modes = ARRAY_SIZE(treo_lcd_modes), |
| 438 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | 587 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, |
| 439 | }; | 588 | }; |
| 440 | 589 | ||
| 441 | /****************************************************************************** | 590 | /****************************************************************************** |
| 442 | * Power management - standby | 591 | * Power management - standby |
| 443 | ******************************************************************************/ | 592 | ******************************************************************************/ |
| 444 | static void __init treo680_pm_init(void) | 593 | static void __init treo_pm_init(void) |
| 445 | { | 594 | { |
| 446 | static u32 resume[] = { | 595 | static u32 resume[] = { |
| 447 | 0xe3a00101, /* mov r0, #0x40000000 */ | 596 | 0xe3a00101, /* mov r0, #0x40000000 */ |
| @@ -450,70 +599,118 @@ static void __init treo680_pm_init(void) | |||
| 450 | }; | 599 | }; |
| 451 | 600 | ||
| 452 | /* this is where the bootloader jumps */ | 601 | /* this is where the bootloader jumps */ |
| 453 | memcpy(phys_to_virt(TREO680_STR_BASE), resume, sizeof(resume)); | 602 | memcpy(phys_to_virt(TREO_STR_BASE), resume, sizeof(resume)); |
| 454 | } | 603 | } |
| 455 | 604 | ||
| 456 | /****************************************************************************** | 605 | /****************************************************************************** |
| 457 | * Machine init | 606 | * Machine init |
| 458 | ******************************************************************************/ | 607 | ******************************************************************************/ |
| 459 | static struct platform_device *devices[] __initdata = { | 608 | static struct platform_device *treo_devices[] __initdata = { |
| 460 | &treo680_backlight, | 609 | &treo_backlight, |
| 461 | &treo680_leds, | ||
| 462 | &power_supply, | 610 | &power_supply, |
| 463 | }; | 611 | }; |
| 464 | 612 | ||
| 613 | #ifdef CONFIG_MACH_TREO680 | ||
| 614 | static struct platform_device *treo680_devices[] __initdata = { | ||
| 615 | &treo680_leds, | ||
| 616 | }; | ||
| 617 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 618 | |||
| 619 | #ifdef CONFIG_MACH_CENTRO | ||
| 620 | static struct platform_device *centro_devices[] __initdata = { | ||
| 621 | ¢ro_leds, | ||
| 622 | }; | ||
| 623 | #endif /* CONFIG_MACH_CENTRO */ | ||
| 624 | |||
| 465 | /* setup udc GPIOs initial state */ | 625 | /* setup udc GPIOs initial state */ |
| 466 | static void __init treo680_udc_init(void) | 626 | static void __init treo_udc_init(void) |
| 467 | { | 627 | { |
| 468 | if (!gpio_request(GPIO_NR_TREO680_USB_PULLUP, "UDC Vbus")) { | 628 | if (!gpio_request(GPIO_NR_TREO_USB_PULLUP, "UDC Vbus")) { |
| 469 | gpio_direction_output(GPIO_NR_TREO680_USB_PULLUP, 1); | 629 | gpio_direction_output(GPIO_NR_TREO_USB_PULLUP, 1); |
| 470 | gpio_free(GPIO_NR_TREO680_USB_PULLUP); | 630 | gpio_free(GPIO_NR_TREO_USB_PULLUP); |
| 471 | } | 631 | } |
| 472 | } | 632 | } |
| 473 | 633 | ||
| 474 | static void __init treo680_lcd_power_init(void) | 634 | static void __init treo_lcd_power_init(void) |
| 475 | { | 635 | { |
| 476 | int ret; | 636 | int ret; |
| 477 | 637 | ||
| 478 | ret = gpio_request(GPIO_NR_TREO680_LCD_POWER, "LCD POWER"); | 638 | ret = gpio_request(GPIO_NR_TREO_LCD_POWER, "LCD POWER"); |
| 479 | if (ret) { | 639 | if (ret) { |
| 480 | pr_err("Treo680: LCD power GPIO request failed!\n"); | 640 | pr_err("Treo680: LCD power GPIO request failed!\n"); |
| 481 | return; | 641 | return; |
| 482 | } | 642 | } |
| 483 | 643 | ||
| 484 | ret = gpio_direction_output(GPIO_NR_TREO680_LCD_POWER, 0); | 644 | ret = gpio_direction_output(GPIO_NR_TREO_LCD_POWER, 0); |
| 485 | if (ret) { | 645 | if (ret) { |
| 486 | pr_err("Treo680: setting LCD power GPIO direction failed!\n"); | 646 | pr_err("Treo680: setting LCD power GPIO direction failed!\n"); |
| 487 | gpio_free(GPIO_NR_TREO680_LCD_POWER); | 647 | gpio_free(GPIO_NR_TREO_LCD_POWER); |
| 488 | return; | 648 | return; |
| 489 | } | 649 | } |
| 490 | 650 | ||
| 491 | treo680_lcd_screen.pxafb_lcd_power = treo680_lcd_power; | 651 | treo_lcd_screen.pxafb_lcd_power = treo_lcd_power; |
| 492 | } | 652 | } |
| 493 | 653 | ||
| 654 | static void __init treo_init(void) | ||
| 655 | { | ||
| 656 | pxa_set_ffuart_info(NULL); | ||
| 657 | pxa_set_btuart_info(NULL); | ||
| 658 | pxa_set_stuart_info(NULL); | ||
| 659 | |||
| 660 | treo_pm_init(); | ||
| 661 | pxa2xx_mfp_config(ARRAY_AND_SIZE(treo_pin_config)); | ||
| 662 | treo_lcd_power_init(); | ||
| 663 | set_pxa_fb_info(&treo_lcd_screen); | ||
| 664 | treo_udc_init(); | ||
| 665 | pxa_set_udc_info(&treo_udc_info); | ||
| 666 | pxa_set_ac97_info(&treo_ac97_pdata); | ||
| 667 | pxa_set_ficp_info(&treo_ficp_info); | ||
| 668 | |||
| 669 | platform_add_devices(ARRAY_AND_SIZE(treo_devices)); | ||
| 670 | } | ||
| 671 | |||
| 672 | #ifdef CONFIG_MACH_TREO680 | ||
| 494 | static void __init treo680_init(void) | 673 | static void __init treo680_init(void) |
| 495 | { | 674 | { |
| 496 | treo680_pm_init(); | 675 | treo_init(); |
| 497 | pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); | 676 | pxa2xx_mfp_config(ARRAY_AND_SIZE(treo680_pin_config)); |
| 498 | pxa_set_keypad_info(&treo680_keypad_platform_data); | ||
| 499 | treo680_lcd_power_init(); | ||
| 500 | set_pxa_fb_info(&treo680_lcd_screen); | ||
| 501 | pxa_set_mci_info(&treo680_mci_platform_data); | 677 | pxa_set_mci_info(&treo680_mci_platform_data); |
| 502 | treo680_udc_init(); | 678 | pxa_set_keypad_info(&treo680_keypad_platform_data); |
| 503 | pxa_set_udc_info(&treo680_udc_info); | ||
| 504 | pxa_set_ac97_info(&treo680_ac97_pdata); | ||
| 505 | pxa_set_ficp_info(&treo680_ficp_info); | ||
| 506 | pxa_set_ohci_info(&treo680_ohci_info); | 679 | pxa_set_ohci_info(&treo680_ohci_info); |
| 507 | 680 | ||
| 508 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 681 | platform_add_devices(ARRAY_AND_SIZE(treo680_devices)); |
| 509 | } | 682 | } |
| 510 | 683 | ||
| 511 | MACHINE_START(TREO680, "Palm Treo 680") | 684 | MACHINE_START(TREO680, "Palm Treo 680") |
| 512 | .phys_io = TREO680_PHYS_IO_START, | 685 | .phys_io = TREO_PHYS_IO_START, |
| 513 | .io_pg_offst = io_p2v(0x40000000), | 686 | .io_pg_offst = io_p2v(0x40000000), |
| 514 | .boot_params = 0xa0000100, | 687 | .boot_params = 0xa0000100, |
| 515 | .map_io = pxa_map_io, | 688 | .map_io = pxa_map_io, |
| 516 | .init_irq = pxa27x_init_irq, | 689 | .init_irq = pxa27x_init_irq, |
| 517 | .timer = &pxa_timer, | 690 | .timer = &pxa_timer, |
| 518 | .init_machine = treo680_init, | 691 | .init_machine = treo680_init, |
| 692 | MACHINE_END | ||
| 693 | #endif /* CONFIG_MACH_TREO680 */ | ||
| 694 | |||
| 695 | #ifdef CONFIG_MACH_CENTRO | ||
| 696 | static void __init centro_init(void) | ||
| 697 | { | ||
| 698 | treo_init(); | ||
| 699 | pxa2xx_mfp_config(ARRAY_AND_SIZE(centro685_pin_config)); | ||
| 700 | pxa_set_mci_info(¢ro_mci_platform_data); | ||
| 701 | |||
| 702 | pxa_set_keypad_info(¢ro_keypad_platform_data); | ||
| 703 | |||
| 704 | platform_add_devices(ARRAY_AND_SIZE(centro_devices)); | ||
| 705 | } | ||
| 706 | |||
| 707 | MACHINE_START(CENTRO, "Palm Centro 685") | ||
| 708 | .phys_io = TREO_PHYS_IO_START, | ||
| 709 | .io_pg_offst = io_p2v(0x40000000), | ||
| 710 | .boot_params = 0xa0000100, | ||
| 711 | .map_io = pxa_map_io, | ||
| 712 | .init_irq = pxa27x_init_irq, | ||
| 713 | .timer = &pxa_timer, | ||
| 714 | .init_machine = centro_init, | ||
| 519 | MACHINE_END | 715 | MACHINE_END |
| 716 | #endif /* CONFIG_MACH_CENTRO */ | ||
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index 76a2b37eaf30..7bf18c2f002f 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c | |||
| @@ -570,6 +570,10 @@ static void __init palmtx_init(void) | |||
| 570 | { | 570 | { |
| 571 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config)); | 571 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtx_pin_config)); |
| 572 | 572 | ||
| 573 | pxa_set_ffuart_info(NULL); | ||
| 574 | pxa_set_btuart_info(NULL); | ||
| 575 | pxa_set_stuart_info(NULL); | ||
| 576 | |||
| 573 | palmtx_pm_init(); | 577 | palmtx_pm_init(); |
| 574 | set_pxa_fb_info(&palmtx_lcd_screen); | 578 | set_pxa_fb_info(&palmtx_lcd_screen); |
| 575 | pxa_set_mci_info(&palmtx_mci_platform_data); | 579 | pxa_set_mci_info(&palmtx_mci_platform_data); |
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index c2bf493c5f53..d787ac7cfdd8 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
| @@ -491,6 +491,10 @@ static void __init palmz72_init(void) | |||
| 491 | { | 491 | { |
| 492 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); | 492 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmz72_pin_config)); |
| 493 | 493 | ||
| 494 | pxa_set_ffuart_info(NULL); | ||
| 495 | pxa_set_btuart_info(NULL); | ||
| 496 | pxa_set_stuart_info(NULL); | ||
| 497 | |||
| 494 | set_pxa_fb_info(&palmz72_lcd_screen); | 498 | set_pxa_fb_info(&palmz72_lcd_screen); |
| 495 | pxa_set_mci_info(&palmz72_mci_platform_data); | 499 | pxa_set_mci_info(&palmz72_mci_platform_data); |
| 496 | palmz72_udc_init(); | 500 | palmz72_udc_init(); |
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 6abfa2979c61..2190af066470 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
| @@ -227,6 +227,10 @@ static void __init pcm027_init(void) | |||
| 227 | 227 | ||
| 228 | pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config)); | 228 | pxa2xx_mfp_config(pcm027_pin_config, ARRAY_SIZE(pcm027_pin_config)); |
| 229 | 229 | ||
| 230 | pxa_set_ffuart_info(NULL); | ||
| 231 | pxa_set_btuart_info(NULL); | ||
| 232 | pxa_set_stuart_info(NULL); | ||
| 233 | |||
| 230 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 234 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 231 | 235 | ||
| 232 | /* at last call the baseboard to initialize itself */ | 236 | /* at last call the baseboard to initialize itself */ |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index bbda57078e0f..d5255ae74fe3 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
| @@ -359,19 +359,12 @@ static unsigned long pcm990_camera_pin_config[] = { | |||
| 359 | GPIO44_CIF_LV, | 359 | GPIO44_CIF_LV, |
| 360 | }; | 360 | }; |
| 361 | 361 | ||
| 362 | static int pcm990_pxacamera_init(struct device *dev) | ||
| 363 | { | ||
| 364 | pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config)); | ||
| 365 | return 0; | ||
| 366 | } | ||
| 367 | |||
| 368 | /* | 362 | /* |
| 369 | * CICR4: PCLK_EN: Pixel clock is supplied by the sensor | 363 | * CICR4: PCLK_EN: Pixel clock is supplied by the sensor |
| 370 | * MCLK_EN: Master clock is generated by PXA | 364 | * MCLK_EN: Master clock is generated by PXA |
| 371 | * PCP: Data sampled on the falling edge of pixel clock | 365 | * PCP: Data sampled on the falling edge of pixel clock |
| 372 | */ | 366 | */ |
| 373 | struct pxacamera_platform_data pcm990_pxacamera_platform_data = { | 367 | struct pxacamera_platform_data pcm990_pxacamera_platform_data = { |
| 374 | .init = pcm990_pxacamera_init, | ||
| 375 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 | | 368 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | PXA_CAMERA_DATAWIDTH_10 | |
| 376 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/, | 369 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN/* | PXA_CAMERA_PCP*/, |
| 377 | .mclk_10khz = 1000, | 370 | .mclk_10khz = 1000, |
| @@ -532,6 +525,7 @@ void __init pcm990_baseboard_init(void) | |||
| 532 | pxa_set_ac97_info(NULL); | 525 | pxa_set_ac97_info(NULL); |
| 533 | 526 | ||
| 534 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | 527 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) |
| 528 | pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_camera_pin_config)); | ||
| 535 | pxa_set_camera_info(&pcm990_pxacamera_platform_data); | 529 | pxa_set_camera_info(&pcm990_pxacamera_platform_data); |
| 536 | 530 | ||
| 537 | i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices)); | 531 | i2c_register_board_info(0, ARRAY_AND_SIZE(pcm990_i2c_devices)); |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index a186994f77fb..e5eeb3a62d01 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
| @@ -449,6 +449,10 @@ static void __init poodle_init(void) | |||
| 449 | 449 | ||
| 450 | pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config)); | 450 | pxa2xx_mfp_config(ARRAY_AND_SIZE(poodle_pin_config)); |
| 451 | 451 | ||
| 452 | pxa_set_ffuart_info(NULL); | ||
| 453 | pxa_set_btuart_info(NULL); | ||
| 454 | pxa_set_stuart_info(NULL); | ||
| 455 | |||
| 452 | platform_scoop_config = &poodle_pcmcia_config; | 456 | platform_scoop_config = &poodle_pcmcia_config; |
| 453 | 457 | ||
| 454 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); | 458 | ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 77c2693cfeef..2c1b0b70d01d 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -322,9 +322,6 @@ void __init pxa26x_init_irq(void) | |||
| 322 | 322 | ||
| 323 | static struct platform_device *pxa25x_devices[] __initdata = { | 323 | static struct platform_device *pxa25x_devices[] __initdata = { |
| 324 | &pxa25x_device_udc, | 324 | &pxa25x_device_udc, |
| 325 | &pxa_device_ffuart, | ||
| 326 | &pxa_device_btuart, | ||
| 327 | &pxa_device_stuart, | ||
| 328 | &pxa_device_i2s, | 325 | &pxa_device_i2s, |
| 329 | &sa1100_device_rtc, | 326 | &sa1100_device_rtc, |
| 330 | &pxa25x_device_ssp, | 327 | &pxa25x_device_ssp, |
| @@ -372,10 +369,8 @@ static int __init pxa25x_init(void) | |||
| 372 | } | 369 | } |
| 373 | 370 | ||
| 374 | /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ | 371 | /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */ |
| 375 | if (cpu_is_pxa255()) { | 372 | if (cpu_is_pxa255()) |
| 376 | clks_register(&pxa25x_hwuart_clkreg, 1); | 373 | clks_register(&pxa25x_hwuart_clkreg, 1); |
| 377 | ret = platform_device_register(&pxa_device_hwuart); | ||
| 378 | } | ||
| 379 | 374 | ||
| 380 | return ret; | 375 | return ret; |
| 381 | } | 376 | } |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index ec68cc16b4e3..6a0b73167e03 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -364,9 +364,6 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) | |||
| 364 | 364 | ||
| 365 | static struct platform_device *devices[] __initdata = { | 365 | static struct platform_device *devices[] __initdata = { |
| 366 | &pxa27x_device_udc, | 366 | &pxa27x_device_udc, |
| 367 | &pxa_device_ffuart, | ||
| 368 | &pxa_device_btuart, | ||
| 369 | &pxa_device_stuart, | ||
| 370 | &pxa_device_i2s, | 367 | &pxa_device_i2s, |
| 371 | &sa1100_device_rtc, | 368 | &sa1100_device_rtc, |
| 372 | &pxa_device_rtc, | 369 | &pxa_device_rtc, |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 09b7b1a10cad..fcb0721f4669 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <mach/pm.h> | 30 | #include <mach/pm.h> |
| 31 | #include <mach/dma.h> | 31 | #include <mach/dma.h> |
| 32 | #include <mach/ssp.h> | 32 | #include <mach/ssp.h> |
| 33 | #include <mach/regs-intc.h> | ||
| 33 | #include <plat/i2c.h> | 34 | #include <plat/i2c.h> |
| 34 | 35 | ||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| @@ -45,6 +46,9 @@ | |||
| 45 | #define ACCR_D0CS (1 << 26) | 46 | #define ACCR_D0CS (1 << 26) |
| 46 | #define ACCR_PCCE (1 << 11) | 47 | #define ACCR_PCCE (1 << 11) |
| 47 | 48 | ||
| 49 | #define PECR_IE(n) ((1 << ((n) * 2)) << 28) | ||
| 50 | #define PECR_IS(n) ((1 << ((n) * 2)) << 29) | ||
| 51 | |||
| 48 | /* crystal frequency to static memory controller multiplier (SMCFS) */ | 52 | /* crystal frequency to static memory controller multiplier (SMCFS) */ |
| 49 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; | 53 | static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, }; |
| 50 | 54 | ||
| @@ -237,6 +241,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1); | |||
| 237 | static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); | 241 | static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0); |
| 238 | static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); | 242 | static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5); |
| 239 | static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); | 243 | static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0); |
| 244 | static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0); | ||
| 240 | static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); | 245 | static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0); |
| 241 | static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); | 246 | static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0); |
| 242 | static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); | 247 | static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0); |
| @@ -261,6 +266,7 @@ static struct clk_lookup pxa3xx_clkregs[] = { | |||
| 261 | INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), | 266 | INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), |
| 262 | INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), | 267 | INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), |
| 263 | INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), | 268 | INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), |
| 269 | INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), | ||
| 264 | INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), | 270 | INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), |
| 265 | INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), | 271 | INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), |
| 266 | INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), | 272 | INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), |
| @@ -530,6 +536,43 @@ static inline void pxa3xx_init_pm(void) {} | |||
| 530 | #define pxa3xx_set_wake NULL | 536 | #define pxa3xx_set_wake NULL |
| 531 | #endif | 537 | #endif |
| 532 | 538 | ||
| 539 | static void pxa_ack_ext_wakeup(unsigned int irq) | ||
| 540 | { | ||
| 541 | PECR |= PECR_IS(irq - IRQ_WAKEUP0); | ||
| 542 | } | ||
| 543 | |||
| 544 | static void pxa_mask_ext_wakeup(unsigned int irq) | ||
| 545 | { | ||
| 546 | ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f)); | ||
| 547 | PECR &= ~PECR_IE(irq - IRQ_WAKEUP0); | ||
| 548 | } | ||
| 549 | |||
| 550 | static void pxa_unmask_ext_wakeup(unsigned int irq) | ||
| 551 | { | ||
| 552 | ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f); | ||
| 553 | PECR |= PECR_IE(irq - IRQ_WAKEUP0); | ||
| 554 | } | ||
| 555 | |||
| 556 | static struct irq_chip pxa_ext_wakeup_chip = { | ||
| 557 | .name = "WAKEUP", | ||
| 558 | .ack = pxa_ack_ext_wakeup, | ||
| 559 | .mask = pxa_mask_ext_wakeup, | ||
| 560 | .unmask = pxa_unmask_ext_wakeup, | ||
| 561 | }; | ||
| 562 | |||
| 563 | static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) | ||
| 564 | { | ||
| 565 | int irq; | ||
| 566 | |||
| 567 | for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { | ||
| 568 | set_irq_chip(irq, &pxa_ext_wakeup_chip); | ||
| 569 | set_irq_handler(irq, handle_edge_irq); | ||
| 570 | set_irq_flags(irq, IRQF_VALID); | ||
| 571 | } | ||
| 572 | |||
| 573 | pxa_ext_wakeup_chip.set_wake = fn; | ||
| 574 | } | ||
| 575 | |||
| 533 | void __init pxa3xx_init_irq(void) | 576 | void __init pxa3xx_init_irq(void) |
| 534 | { | 577 | { |
| 535 | /* enable CP6 access */ | 578 | /* enable CP6 access */ |
| @@ -539,6 +582,7 @@ void __init pxa3xx_init_irq(void) | |||
| 539 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 582 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 540 | 583 | ||
| 541 | pxa_init_irq(56, pxa3xx_set_wake); | 584 | pxa_init_irq(56, pxa3xx_set_wake); |
| 585 | pxa_init_ext_wakeup_irq(pxa3xx_set_wake); | ||
| 542 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); | 586 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
| 543 | } | 587 | } |
| 544 | 588 | ||
| @@ -553,9 +597,6 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) | |||
| 553 | 597 | ||
| 554 | static struct platform_device *devices[] __initdata = { | 598 | static struct platform_device *devices[] __initdata = { |
| 555 | &pxa27x_device_udc, | 599 | &pxa27x_device_udc, |
| 556 | &pxa_device_ffuart, | ||
| 557 | &pxa_device_btuart, | ||
| 558 | &pxa_device_stuart, | ||
| 559 | &pxa_device_i2s, | 600 | &pxa_device_i2s, |
| 560 | &sa1100_device_rtc, | 601 | &sa1100_device_rtc, |
| 561 | &pxa_device_rtc, | 602 | &pxa_device_rtc, |
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 8241a63ea589..115b6f234bdd 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
| @@ -22,9 +22,13 @@ | |||
| 22 | #include <linux/i2c.h> | 22 | #include <linux/i2c.h> |
| 23 | #include <linux/smc91x.h> | 23 | #include <linux/smc91x.h> |
| 24 | #include <linux/mfd/da903x.h> | 24 | #include <linux/mfd/da903x.h> |
| 25 | #include <linux/mtd/mtd.h> | ||
| 26 | #include <linux/mtd/partitions.h> | ||
| 27 | #include <linux/mtd/onenand.h> | ||
| 25 | 28 | ||
| 26 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 31 | #include <asm/mach/flash.h> | ||
| 28 | 32 | ||
| 29 | #include <mach/pxa930.h> | 33 | #include <mach/pxa930.h> |
| 30 | #include <plat/i2c.h> | 34 | #include <plat/i2c.h> |
| @@ -33,7 +37,7 @@ | |||
| 33 | #include "devices.h" | 37 | #include "devices.h" |
| 34 | #include "generic.h" | 38 | #include "generic.h" |
| 35 | 39 | ||
| 36 | #define GPIO_LCD_RESET (16) | 40 | #define GPIO_LCD_RESET (16) |
| 37 | 41 | ||
| 38 | /* SAAR MFP configurations */ | 42 | /* SAAR MFP configurations */ |
| 39 | static mfp_cfg_t saar_mfp_cfg[] __initdata = { | 43 | static mfp_cfg_t saar_mfp_cfg[] __initdata = { |
| @@ -56,6 +60,31 @@ static mfp_cfg_t saar_mfp_cfg[] __initdata = { | |||
| 56 | /* Ethernet */ | 60 | /* Ethernet */ |
| 57 | DF_nCS1_nCS3, | 61 | DF_nCS1_nCS3, |
| 58 | GPIO97_GPIO, | 62 | GPIO97_GPIO, |
| 63 | |||
| 64 | /* DFI */ | ||
| 65 | DF_INT_RnB_ND_INT_RnB, | ||
| 66 | DF_nRE_nOE_ND_nRE, | ||
| 67 | DF_nWE_ND_nWE, | ||
| 68 | DF_CLE_nOE_ND_CLE, | ||
| 69 | DF_nADV1_ALE_ND_ALE, | ||
| 70 | DF_nADV2_ALE_nCS3, | ||
| 71 | DF_nCS0_ND_nCS0, | ||
| 72 | DF_IO0_ND_IO0, | ||
| 73 | DF_IO1_ND_IO1, | ||
| 74 | DF_IO2_ND_IO2, | ||
| 75 | DF_IO3_ND_IO3, | ||
| 76 | DF_IO4_ND_IO4, | ||
| 77 | DF_IO5_ND_IO5, | ||
| 78 | DF_IO6_ND_IO6, | ||
| 79 | DF_IO7_ND_IO7, | ||
| 80 | DF_IO8_ND_IO8, | ||
| 81 | DF_IO9_ND_IO9, | ||
| 82 | DF_IO10_ND_IO10, | ||
| 83 | DF_IO11_ND_IO11, | ||
| 84 | DF_IO12_ND_IO12, | ||
| 85 | DF_IO13_ND_IO13, | ||
| 86 | DF_IO14_ND_IO14, | ||
| 87 | DF_IO15_ND_IO15, | ||
| 59 | }; | 88 | }; |
| 60 | 89 | ||
| 61 | #define SAAR_ETH_PHYS (0x14000000) | 90 | #define SAAR_ETH_PHYS (0x14000000) |
| @@ -451,10 +480,15 @@ static inline void saar_init_lcd(void) {} | |||
| 451 | #endif | 480 | #endif |
| 452 | 481 | ||
| 453 | #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) | 482 | #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE) |
| 483 | static struct da9034_backlight_pdata saar_da9034_backlight = { | ||
| 484 | .output_current = 4, /* 4mA */ | ||
| 485 | }; | ||
| 486 | |||
| 454 | static struct da903x_subdev_info saar_da9034_subdevs[] = { | 487 | static struct da903x_subdev_info saar_da9034_subdevs[] = { |
| 455 | [0] = { | 488 | [0] = { |
| 456 | .name = "da903x-backlight", | 489 | .name = "da903x-backlight", |
| 457 | .id = DA9034_ID_WLED, | 490 | .id = DA9034_ID_WLED, |
| 491 | .platform_data = &saar_da9034_backlight, | ||
| 458 | }, | 492 | }, |
| 459 | }; | 493 | }; |
| 460 | 494 | ||
| @@ -480,12 +514,81 @@ static void __init saar_init_i2c(void) | |||
| 480 | #else | 514 | #else |
| 481 | static inline void saar_init_i2c(void) {} | 515 | static inline void saar_init_i2c(void) {} |
| 482 | #endif | 516 | #endif |
| 517 | |||
| 518 | #if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE) | ||
| 519 | static struct mtd_partition saar_onenand_partitions[] = { | ||
| 520 | { | ||
| 521 | .name = "bootloader", | ||
| 522 | .offset = 0, | ||
| 523 | .size = SZ_1M, | ||
| 524 | .mask_flags = MTD_WRITEABLE, | ||
| 525 | }, { | ||
| 526 | .name = "reserved", | ||
| 527 | .offset = MTDPART_OFS_APPEND, | ||
| 528 | .size = SZ_128K, | ||
| 529 | .mask_flags = MTD_WRITEABLE, | ||
| 530 | }, { | ||
| 531 | .name = "reserved", | ||
| 532 | .offset = MTDPART_OFS_APPEND, | ||
| 533 | .size = SZ_8M, | ||
| 534 | .mask_flags = MTD_WRITEABLE, | ||
| 535 | }, { | ||
| 536 | .name = "kernel", | ||
| 537 | .offset = MTDPART_OFS_APPEND, | ||
| 538 | .size = (SZ_2M + SZ_1M), | ||
| 539 | .mask_flags = 0, | ||
| 540 | }, { | ||
| 541 | .name = "filesystem", | ||
| 542 | .offset = MTDPART_OFS_APPEND, | ||
| 543 | .size = SZ_48M, | ||
| 544 | .mask_flags = 0, | ||
| 545 | } | ||
| 546 | }; | ||
| 547 | |||
| 548 | static struct onenand_platform_data saar_onenand_info = { | ||
| 549 | .parts = saar_onenand_partitions, | ||
| 550 | .nr_parts = ARRAY_SIZE(saar_onenand_partitions), | ||
| 551 | }; | ||
| 552 | |||
| 553 | #define SMC_CS0_PHYS_BASE (0x10000000) | ||
| 554 | |||
| 555 | static struct resource saar_resource_onenand[] = { | ||
| 556 | [0] = { | ||
| 557 | .start = SMC_CS0_PHYS_BASE, | ||
| 558 | .end = SMC_CS0_PHYS_BASE + SZ_1M, | ||
| 559 | .flags = IORESOURCE_MEM, | ||
| 560 | }, | ||
| 561 | }; | ||
| 562 | |||
| 563 | static struct platform_device saar_device_onenand = { | ||
| 564 | .name = "onenand-flash", | ||
| 565 | .id = -1, | ||
| 566 | .dev = { | ||
| 567 | .platform_data = &saar_onenand_info, | ||
| 568 | }, | ||
| 569 | .resource = saar_resource_onenand, | ||
| 570 | .num_resources = ARRAY_SIZE(saar_resource_onenand), | ||
| 571 | }; | ||
| 572 | |||
| 573 | static void __init saar_init_onenand(void) | ||
| 574 | { | ||
| 575 | platform_device_register(&saar_device_onenand); | ||
| 576 | } | ||
| 577 | #else | ||
| 578 | static void __init saar_init_onenand(void) {} | ||
| 579 | #endif | ||
| 580 | |||
| 483 | static void __init saar_init(void) | 581 | static void __init saar_init(void) |
| 484 | { | 582 | { |
| 485 | /* initialize MFP configurations */ | 583 | /* initialize MFP configurations */ |
| 486 | pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); | 584 | pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg)); |
| 487 | 585 | ||
| 586 | pxa_set_ffuart_info(NULL); | ||
| 587 | pxa_set_btuart_info(NULL); | ||
| 588 | pxa_set_stuart_info(NULL); | ||
| 589 | |||
| 488 | platform_device_register(&smc91x_device); | 590 | platform_device_register(&smc91x_device); |
| 591 | saar_init_onenand(); | ||
| 489 | 592 | ||
| 490 | saar_init_i2c(); | 593 | saar_init_i2c(); |
| 491 | saar_init_lcd(); | 594 | saar_init_lcd(); |
diff --git a/arch/arm/mach-pxa/sharpsl.h b/arch/arm/mach-pxa/sharpsl.h index 55259f4756c8..1439785d3979 100644 --- a/arch/arm/mach-pxa/sharpsl.h +++ b/arch/arm/mach-pxa/sharpsl.h | |||
| @@ -42,8 +42,8 @@ void corgi_lcdtg_hw_init(int mode); | |||
| 42 | #define MAX1111_BATT_TEMP 2u | 42 | #define MAX1111_BATT_TEMP 2u |
| 43 | #define MAX1111_ACIN_VOLT 6u | 43 | #define MAX1111_ACIN_VOLT 6u |
| 44 | 44 | ||
| 45 | extern struct battery_thresh spitz_battery_levels_acin[]; | 45 | extern struct battery_thresh sharpsl_battery_levels_acin[]; |
| 46 | extern struct battery_thresh spitz_battery_levels_noac[]; | 46 | extern struct battery_thresh sharpsl_battery_levels_noac[]; |
| 47 | int sharpsl_pm_pxa_read_max1111(int channel); | 47 | int sharpsl_pm_pxa_read_max1111(int channel); |
| 48 | 48 | ||
| 49 | 49 | ||
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 629e05d1196e..67229a1ef55c 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
| @@ -78,7 +78,7 @@ DEFINE_LED_TRIGGER(sharpsl_charge_led_trigger); | |||
| 78 | 78 | ||
| 79 | 79 | ||
| 80 | 80 | ||
| 81 | struct battery_thresh spitz_battery_levels_acin[] = { | 81 | struct battery_thresh sharpsl_battery_levels_acin[] = { |
| 82 | { 213, 100}, | 82 | { 213, 100}, |
| 83 | { 212, 98}, | 83 | { 212, 98}, |
| 84 | { 211, 95}, | 84 | { 211, 95}, |
| @@ -121,7 +121,7 @@ struct battery_thresh spitz_battery_levels_acin[] = { | |||
| 121 | { 0, 0}, | 121 | { 0, 0}, |
| 122 | }; | 122 | }; |
| 123 | 123 | ||
| 124 | struct battery_thresh spitz_battery_levels_noac[] = { | 124 | struct battery_thresh sharpsl_battery_levels_noac[] = { |
| 125 | { 213, 100}, | 125 | { 213, 100}, |
| 126 | { 212, 98}, | 126 | { 212, 98}, |
| 127 | { 211, 95}, | 127 | { 211, 95}, |
| @@ -165,19 +165,20 @@ struct battery_thresh spitz_battery_levels_noac[] = { | |||
| 165 | }; | 165 | }; |
| 166 | 166 | ||
| 167 | /* MAX1111 Commands */ | 167 | /* MAX1111 Commands */ |
| 168 | #define MAXCTRL_PD0 1u << 0 | 168 | #define MAXCTRL_PD0 (1u << 0) |
| 169 | #define MAXCTRL_PD1 1u << 1 | 169 | #define MAXCTRL_PD1 (1u << 1) |
| 170 | #define MAXCTRL_SGL 1u << 2 | 170 | #define MAXCTRL_SGL (1u << 2) |
| 171 | #define MAXCTRL_UNI 1u << 3 | 171 | #define MAXCTRL_UNI (1u << 3) |
| 172 | #define MAXCTRL_SEL_SH 4 | 172 | #define MAXCTRL_SEL_SH 4 |
| 173 | #define MAXCTRL_STR 1u << 7 | 173 | #define MAXCTRL_STR (1u << 7) |
| 174 | 174 | ||
| 175 | /* | 175 | /* |
| 176 | * Read MAX1111 ADC | 176 | * Read MAX1111 ADC |
| 177 | */ | 177 | */ |
| 178 | int sharpsl_pm_pxa_read_max1111(int channel) | 178 | int sharpsl_pm_pxa_read_max1111(int channel) |
| 179 | { | 179 | { |
| 180 | if (machine_is_tosa()) // Ugly, better move this function into another module | 180 | /* Ugly, better move this function into another module */ |
| 181 | if (machine_is_tosa()) | ||
| 181 | return 0; | 182 | return 0; |
| 182 | 183 | ||
| 183 | #ifdef CONFIG_CORGI_SSP_DEPRECATED | 184 | #ifdef CONFIG_CORGI_SSP_DEPRECATED |
| @@ -238,7 +239,7 @@ EXPORT_SYMBOL(sharpsl_battery_kick); | |||
| 238 | 239 | ||
| 239 | static void sharpsl_battery_thread(struct work_struct *private_) | 240 | static void sharpsl_battery_thread(struct work_struct *private_) |
| 240 | { | 241 | { |
| 241 | int voltage, percent, apm_status, i = 0; | 242 | int voltage, percent, apm_status, i; |
| 242 | 243 | ||
| 243 | if (!sharpsl_pm.machinfo) | 244 | if (!sharpsl_pm.machinfo) |
| 244 | return; | 245 | return; |
| @@ -250,15 +251,14 @@ static void sharpsl_battery_thread(struct work_struct *private_) | |||
| 250 | && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL)) | 251 | && time_after(jiffies, sharpsl_pm.charge_start_time + SHARPSL_CHARGE_ON_TIME_INTERVAL)) |
| 251 | schedule_delayed_work(&toggle_charger, 0); | 252 | schedule_delayed_work(&toggle_charger, 0); |
| 252 | 253 | ||
| 253 | while(1) { | 254 | for (i = 0; i < 5; i++) { |
| 254 | voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); | 255 | voltage = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); |
| 255 | 256 | if (voltage > 0) | |
| 256 | if (voltage > 0) break; | ||
| 257 | if (i++ > 5) { | ||
| 258 | voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage; | ||
| 259 | dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n"); | ||
| 260 | break; | 257 | break; |
| 261 | } | 258 | } |
| 259 | if (voltage <= 0) { | ||
| 260 | voltage = sharpsl_pm.machinfo->bat_levels_noac[0].voltage; | ||
| 261 | dev_warn(sharpsl_pm.dev, "Warning: Cannot read main battery!\n"); | ||
| 262 | } | 262 | } |
| 263 | 263 | ||
| 264 | voltage = sharpsl_average_value(voltage); | 264 | voltage = sharpsl_average_value(voltage); |
| @@ -266,8 +266,10 @@ static void sharpsl_battery_thread(struct work_struct *private_) | |||
| 266 | percent = get_percentage(voltage); | 266 | percent = get_percentage(voltage); |
| 267 | 267 | ||
| 268 | /* At low battery voltages, the voltage has a tendency to start | 268 | /* At low battery voltages, the voltage has a tendency to start |
| 269 | creeping back up so we try to avoid this here */ | 269 | creeping back up so we try to avoid this here */ |
| 270 | if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) || (apm_status == APM_BATTERY_STATUS_HIGH) || percent <= sharpsl_pm.battstat.mainbat_percent) { | 270 | if ((sharpsl_pm.battstat.ac_status == APM_AC_ONLINE) |
| 271 | || (apm_status == APM_BATTERY_STATUS_HIGH) | ||
| 272 | || percent <= sharpsl_pm.battstat.mainbat_percent) { | ||
| 271 | sharpsl_pm.battstat.mainbat_voltage = voltage; | 273 | sharpsl_pm.battstat.mainbat_voltage = voltage; |
| 272 | sharpsl_pm.battstat.mainbat_status = apm_status; | 274 | sharpsl_pm.battstat.mainbat_status = apm_status; |
| 273 | sharpsl_pm.battstat.mainbat_percent = percent; | 275 | sharpsl_pm.battstat.mainbat_percent = percent; |
| @@ -279,8 +281,8 @@ static void sharpsl_battery_thread(struct work_struct *private_) | |||
| 279 | #ifdef CONFIG_BACKLIGHT_CORGI | 281 | #ifdef CONFIG_BACKLIGHT_CORGI |
| 280 | /* If battery is low. limit backlight intensity to save power. */ | 282 | /* If battery is low. limit backlight intensity to save power. */ |
| 281 | if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) | 283 | if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) |
| 282 | && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) || | 284 | && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW) |
| 283 | (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) { | 285 | || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) { |
| 284 | if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) { | 286 | if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) { |
| 285 | sharpsl_pm.machinfo->backlight_limit(1); | 287 | sharpsl_pm.machinfo->backlight_limit(1); |
| 286 | sharpsl_pm.flags |= SHARPSL_BL_LIMIT; | 288 | sharpsl_pm.flags |= SHARPSL_BL_LIMIT; |
| @@ -293,8 +295,8 @@ static void sharpsl_battery_thread(struct work_struct *private_) | |||
| 293 | 295 | ||
| 294 | /* Suspend if critical battery level */ | 296 | /* Suspend if critical battery level */ |
| 295 | if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) | 297 | if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE) |
| 296 | && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL) | 298 | && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL) |
| 297 | && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) { | 299 | && !(sharpsl_pm.flags & SHARPSL_APM_QUEUED)) { |
| 298 | sharpsl_pm.flags |= SHARPSL_APM_QUEUED; | 300 | sharpsl_pm.flags |= SHARPSL_APM_QUEUED; |
| 299 | dev_err(sharpsl_pm.dev, "Fatal Off\n"); | 301 | dev_err(sharpsl_pm.dev, "Fatal Off\n"); |
| 300 | apm_queue_event(APM_CRITICAL_SUSPEND); | 302 | apm_queue_event(APM_CRITICAL_SUSPEND); |
| @@ -346,7 +348,7 @@ static void sharpsl_charge_error(void) | |||
| 346 | 348 | ||
| 347 | static void sharpsl_charge_toggle(struct work_struct *private_) | 349 | static void sharpsl_charge_toggle(struct work_struct *private_) |
| 348 | { | 350 | { |
| 349 | dev_dbg(sharpsl_pm.dev, "Toogling Charger at time: %lx\n", jiffies); | 351 | dev_dbg(sharpsl_pm.dev, "Toggling Charger at time: %lx\n", jiffies); |
| 350 | 352 | ||
| 351 | if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) { | 353 | if (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) { |
| 352 | sharpsl_charge_off(); | 354 | sharpsl_charge_off(); |
| @@ -368,7 +370,7 @@ static void sharpsl_ac_timer(unsigned long data) | |||
| 368 | { | 370 | { |
| 369 | int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN); | 371 | int acin = sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN); |
| 370 | 372 | ||
| 371 | dev_dbg(sharpsl_pm.dev, "AC Status: %d\n",acin); | 373 | dev_dbg(sharpsl_pm.dev, "AC Status: %d\n", acin); |
| 372 | 374 | ||
| 373 | sharpsl_average_clear(); | 375 | sharpsl_average_clear(); |
| 374 | if (acin && (sharpsl_pm.charge_mode != CHRG_ON)) | 376 | if (acin && (sharpsl_pm.charge_mode != CHRG_ON)) |
| @@ -472,14 +474,14 @@ static int sharpsl_average_value(int ad) | |||
| 472 | sharpsl_ad[sharpsl_ad_index] = ad; | 474 | sharpsl_ad[sharpsl_ad_index] = ad; |
| 473 | sharpsl_ad_index++; | 475 | sharpsl_ad_index++; |
| 474 | if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) { | 476 | if (sharpsl_ad_index >= SHARPSL_CNV_VALUE_NUM) { |
| 475 | for (i=0; i < (SHARPSL_CNV_VALUE_NUM-1); i++) | 477 | for (i = 0; i < (SHARPSL_CNV_VALUE_NUM-1); i++) |
| 476 | sharpsl_ad[i] = sharpsl_ad[i+1]; | 478 | sharpsl_ad[i] = sharpsl_ad[i+1]; |
| 477 | sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1; | 479 | sharpsl_ad_index = SHARPSL_CNV_VALUE_NUM - 1; |
| 478 | } | 480 | } |
| 479 | for (i=0; i < sharpsl_ad_index; i++) | 481 | for (i = 0; i < sharpsl_ad_index; i++) |
| 480 | ad_val += sharpsl_ad[i]; | 482 | ad_val += sharpsl_ad[i]; |
| 481 | 483 | ||
| 482 | return (ad_val / sharpsl_ad_index); | 484 | return ad_val / sharpsl_ad_index; |
| 483 | } | 485 | } |
| 484 | 486 | ||
| 485 | /* | 487 | /* |
| @@ -492,8 +494,8 @@ static int get_select_val(int *val) | |||
| 492 | 494 | ||
| 493 | /* Find MAX val */ | 495 | /* Find MAX val */ |
| 494 | temp = val[0]; | 496 | temp = val[0]; |
| 495 | j=0; | 497 | j = 0; |
| 496 | for (i=1; i<5; i++) { | 498 | for (i = 1; i < 5; i++) { |
| 497 | if (temp < val[i]) { | 499 | if (temp < val[i]) { |
| 498 | temp = val[i]; | 500 | temp = val[i]; |
| 499 | j = i; | 501 | j = i; |
| @@ -502,21 +504,21 @@ static int get_select_val(int *val) | |||
| 502 | 504 | ||
| 503 | /* Find MIN val */ | 505 | /* Find MIN val */ |
| 504 | temp = val[4]; | 506 | temp = val[4]; |
| 505 | k=4; | 507 | k = 4; |
| 506 | for (i=3; i>=0; i--) { | 508 | for (i = 3; i >= 0; i--) { |
| 507 | if (temp > val[i]) { | 509 | if (temp > val[i]) { |
| 508 | temp = val[i]; | 510 | temp = val[i]; |
| 509 | k = i; | 511 | k = i; |
| 510 | } | 512 | } |
| 511 | } | 513 | } |
| 512 | 514 | ||
| 513 | for (i=0; i<5; i++) | 515 | for (i = 0; i < 5; i++) |
| 514 | if (i != j && i != k ) | 516 | if (i != j && i != k) |
| 515 | sum += val[i]; | 517 | sum += val[i]; |
| 516 | 518 | ||
| 517 | dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]); | 519 | dev_dbg(sharpsl_pm.dev, "Average: %d from values: %d, %d, %d, %d, %d\n", sum/3, val[0], val[1], val[2], val[3], val[4]); |
| 518 | 520 | ||
| 519 | return (sum/3); | 521 | return sum/3; |
| 520 | } | 522 | } |
| 521 | 523 | ||
| 522 | static int sharpsl_check_battery_temp(void) | 524 | static int sharpsl_check_battery_temp(void) |
| @@ -524,7 +526,7 @@ static int sharpsl_check_battery_temp(void) | |||
| 524 | int val, i, buff[5]; | 526 | int val, i, buff[5]; |
| 525 | 527 | ||
| 526 | /* Check battery temperature */ | 528 | /* Check battery temperature */ |
| 527 | for (i=0; i<5; i++) { | 529 | for (i = 0; i < 5; i++) { |
| 528 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); | 530 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); |
| 529 | sharpsl_pm.machinfo->measure_temp(1); | 531 | sharpsl_pm.machinfo->measure_temp(1); |
| 530 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); | 532 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_TEMP); |
| @@ -557,7 +559,7 @@ static int sharpsl_check_battery_voltage(void) | |||
| 557 | sharpsl_pm.machinfo->discharge1(1); | 559 | sharpsl_pm.machinfo->discharge1(1); |
| 558 | 560 | ||
| 559 | /* Check battery voltage */ | 561 | /* Check battery voltage */ |
| 560 | for (i=0; i<5; i++) { | 562 | for (i = 0; i < 5; i++) { |
| 561 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); | 563 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); |
| 562 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); | 564 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); |
| 563 | } | 565 | } |
| @@ -581,16 +583,16 @@ static int sharpsl_ac_check(void) | |||
| 581 | { | 583 | { |
| 582 | int temp, i, buff[5]; | 584 | int temp, i, buff[5]; |
| 583 | 585 | ||
| 584 | for (i=0; i<5; i++) { | 586 | for (i = 0; i < 5; i++) { |
| 585 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT); | 587 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_ACIN_VOLT); |
| 586 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN); | 588 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_ACIN); |
| 587 | } | 589 | } |
| 588 | 590 | ||
| 589 | temp = get_select_val(buff); | 591 | temp = get_select_val(buff); |
| 590 | dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n",temp); | 592 | dev_dbg(sharpsl_pm.dev, "AC Voltage: %d\n", temp); |
| 591 | 593 | ||
| 592 | if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) { | 594 | if ((temp > sharpsl_pm.machinfo->charge_acin_high) || (temp < sharpsl_pm.machinfo->charge_acin_low)) { |
| 593 | dev_err(sharpsl_pm.dev, "Error: AC check failed.\n"); | 595 | dev_err(sharpsl_pm.dev, "Error: AC check failed: voltage %d.\n", temp); |
| 594 | return -1; | 596 | return -1; |
| 595 | } | 597 | } |
| 596 | 598 | ||
| @@ -624,9 +626,9 @@ static int sharpsl_pm_resume(struct platform_device *pdev) | |||
| 624 | 626 | ||
| 625 | static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) | 627 | static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) |
| 626 | { | 628 | { |
| 627 | dev_dbg(sharpsl_pm.dev, "Time is: %08x\n",RCNR); | 629 | dev_dbg(sharpsl_pm.dev, "Time is: %08x\n", RCNR); |
| 628 | 630 | ||
| 629 | dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n",sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG); | 631 | dev_dbg(sharpsl_pm.dev, "Offline Charge Activate = %d\n", sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG); |
| 630 | /* not charging and AC-IN! */ | 632 | /* not charging and AC-IN! */ |
| 631 | 633 | ||
| 632 | if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) { | 634 | if ((sharpsl_pm.flags & SHARPSL_DO_OFFLINE_CHRG) && (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN))) { |
| @@ -644,12 +646,12 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable | |||
| 644 | if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) { | 646 | if ((sharpsl_pm.charge_mode == CHRG_ON) && ((alarm_enable && ((alarm_time - RCNR) > (SHARPSL_BATCHK_TIME_SUSPEND + 30))) || !alarm_enable)) { |
| 645 | RTSR &= RTSR_ALE; | 647 | RTSR &= RTSR_ALE; |
| 646 | RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND; | 648 | RTAR = RCNR + SHARPSL_BATCHK_TIME_SUSPEND; |
| 647 | dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n",RTAR); | 649 | dev_dbg(sharpsl_pm.dev, "Charging alarm at: %08x\n", RTAR); |
| 648 | sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE; | 650 | sharpsl_pm.flags |= SHARPSL_ALARM_ACTIVE; |
| 649 | } else if (alarm_enable) { | 651 | } else if (alarm_enable) { |
| 650 | RTSR &= RTSR_ALE; | 652 | RTSR &= RTSR_ALE; |
| 651 | RTAR = alarm_time; | 653 | RTAR = alarm_time; |
| 652 | dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n",RTAR); | 654 | dev_dbg(sharpsl_pm.dev, "User alarm at: %08x\n", RTAR); |
| 653 | } else { | 655 | } else { |
| 654 | dev_dbg(sharpsl_pm.dev, "No alarms set.\n"); | 656 | dev_dbg(sharpsl_pm.dev, "No alarms set.\n"); |
| 655 | } | 657 | } |
| @@ -658,19 +660,18 @@ static void corgi_goto_sleep(unsigned long alarm_time, unsigned int alarm_enable | |||
| 658 | 660 | ||
| 659 | sharpsl_pm.machinfo->postsuspend(); | 661 | sharpsl_pm.machinfo->postsuspend(); |
| 660 | 662 | ||
| 661 | dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n",PEDR); | 663 | dev_dbg(sharpsl_pm.dev, "Corgi woken up from suspend: %08x\n", PEDR); |
| 662 | } | 664 | } |
| 663 | 665 | ||
| 664 | static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) | 666 | static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enable, suspend_state_t state) |
| 665 | { | 667 | { |
| 666 | if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable) ) | 668 | if (!sharpsl_pm.machinfo->should_wakeup(!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE) && alarm_enable)) { |
| 667 | { | ||
| 668 | if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) { | 669 | if (!(sharpsl_pm.flags & SHARPSL_ALARM_ACTIVE)) { |
| 669 | dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n"); | 670 | dev_dbg(sharpsl_pm.dev, "No user triggered wakeup events and not charging. Strange. Suspend.\n"); |
| 670 | corgi_goto_sleep(alarm_time, alarm_enable, state); | 671 | corgi_goto_sleep(alarm_time, alarm_enable, state); |
| 671 | return 1; | 672 | return 1; |
| 672 | } | 673 | } |
| 673 | if(sharpsl_off_charge_battery()) { | 674 | if (sharpsl_off_charge_battery()) { |
| 674 | dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n"); | 675 | dev_dbg(sharpsl_pm.dev, "Charging. Suspend...\n"); |
| 675 | corgi_goto_sleep(alarm_time, alarm_enable, state); | 676 | corgi_goto_sleep(alarm_time, alarm_enable, state); |
| 676 | return 1; | 677 | return 1; |
| @@ -697,7 +698,7 @@ static int corgi_pxa_pm_enter(suspend_state_t state) | |||
| 697 | 698 | ||
| 698 | corgi_goto_sleep(alarm_time, alarm_status, state); | 699 | corgi_goto_sleep(alarm_time, alarm_status, state); |
| 699 | 700 | ||
| 700 | while (corgi_enter_suspend(alarm_time,alarm_status,state)) | 701 | while (corgi_enter_suspend(alarm_time, alarm_status, state)) |
| 701 | {} | 702 | {} |
| 702 | 703 | ||
| 703 | if (sharpsl_pm.machinfo->earlyresume) | 704 | if (sharpsl_pm.machinfo->earlyresume) |
| @@ -732,7 +733,7 @@ static int sharpsl_fatal_check(void) | |||
| 732 | sharpsl_pm.machinfo->discharge1(1); | 733 | sharpsl_pm.machinfo->discharge1(1); |
| 733 | 734 | ||
| 734 | /* Check battery : check inserting battery ? */ | 735 | /* Check battery : check inserting battery ? */ |
| 735 | for (i=0; i<5; i++) { | 736 | for (i = 0; i < 5; i++) { |
| 736 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); | 737 | buff[i] = sharpsl_pm.machinfo->read_devdata(SHARPSL_BATT_VOLT); |
| 737 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); | 738 | mdelay(SHARPSL_CHECK_BATTERY_WAIT_TIME_VOLT); |
| 738 | } | 739 | } |
| @@ -812,7 +813,7 @@ static int sharpsl_off_charge_battery(void) | |||
| 812 | mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); | 813 | mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); |
| 813 | 814 | ||
| 814 | time = RCNR; | 815 | time = RCNR; |
| 815 | while(1) { | 816 | while (1) { |
| 816 | /* Check if any wakeup event had occurred */ | 817 | /* Check if any wakeup event had occurred */ |
| 817 | if (sharpsl_pm.machinfo->charger_wakeup() != 0) | 818 | if (sharpsl_pm.machinfo->charger_wakeup() != 0) |
| 818 | return 0; | 819 | return 0; |
| @@ -835,9 +836,9 @@ static int sharpsl_off_charge_battery(void) | |||
| 835 | mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); | 836 | mdelay(SHARPSL_CHARGE_CO_CHECK_TIME); |
| 836 | 837 | ||
| 837 | time = RCNR; | 838 | time = RCNR; |
| 838 | while(1) { | 839 | while (1) { |
| 839 | /* Check if any wakeup event had occurred */ | 840 | /* Check if any wakeup event had occurred */ |
| 840 | if (sharpsl_pm.machinfo->charger_wakeup() != 0) | 841 | if (sharpsl_pm.machinfo->charger_wakeup()) |
| 841 | return 0; | 842 | return 0; |
| 842 | /* Check for timeout */ | 843 | /* Check for timeout */ |
| 843 | if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) { | 844 | if ((RCNR-time) > SHARPSL_WAIT_CO_TIME) { |
| @@ -864,12 +865,12 @@ static int sharpsl_off_charge_battery(void) | |||
| 864 | 865 | ||
| 865 | static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf) | 866 | static ssize_t battery_percentage_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 866 | { | 867 | { |
| 867 | return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_percent); | 868 | return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_percent); |
| 868 | } | 869 | } |
| 869 | 870 | ||
| 870 | static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf) | 871 | static ssize_t battery_voltage_show(struct device *dev, struct device_attribute *attr, char *buf) |
| 871 | { | 872 | { |
| 872 | return sprintf(buf, "%d\n",sharpsl_pm.battstat.mainbat_voltage); | 873 | return sprintf(buf, "%d\n", sharpsl_pm.battstat.mainbat_voltage); |
| 873 | } | 874 | } |
| 874 | 875 | ||
| 875 | static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL); | 876 | static DEVICE_ATTR(battery_percentage, 0444, battery_percentage_show, NULL); |
| @@ -943,8 +944,7 @@ static int __init sharpsl_pm_probe(struct platform_device *pdev) | |||
| 943 | } | 944 | } |
| 944 | } | 945 | } |
| 945 | 946 | ||
| 946 | if (sharpsl_pm.machinfo->batfull_irq) | 947 | if (sharpsl_pm.machinfo->batfull_irq) { |
| 947 | { | ||
| 948 | /* Register interrupt handler. */ | 948 | /* Register interrupt handler. */ |
| 949 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { | 949 | if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { |
| 950 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); | 950 | dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull)); |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index d98023f55503..4b50f144fa48 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -768,6 +768,10 @@ static void __init common_init(void) | |||
| 768 | 768 | ||
| 769 | pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config)); | 769 | pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config)); |
| 770 | 770 | ||
| 771 | pxa_set_ffuart_info(NULL); | ||
| 772 | pxa_set_btuart_info(NULL); | ||
| 773 | pxa_set_stuart_info(NULL); | ||
| 774 | |||
| 771 | spitz_init_spi(); | 775 | spitz_init_spi(); |
| 772 | 776 | ||
| 773 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 777 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 724ffb030317..fc5a70c40358 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c | |||
| @@ -103,7 +103,7 @@ static void spitz_presuspend(void) | |||
| 103 | PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); | 103 | PFER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); |
| 104 | PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC; | 104 | PWER = GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET) | PWER_RTC; |
| 105 | PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); | 105 | PKWR = GPIO_bit(SPITZ_GPIO_SYNC) | GPIO_bit(SPITZ_GPIO_KEY_INT) | GPIO_bit(SPITZ_GPIO_RESET); |
| 106 | PKSR = 0xffffffff; // clear | 106 | PKSR = 0xffffffff; /* clear */ |
| 107 | 107 | ||
| 108 | /* nRESET_OUT Disable */ | 108 | /* nRESET_OUT Disable */ |
| 109 | PSLR |= PSLR_SL_ROD; | 109 | PSLR |= PSLR_SL_ROD; |
| @@ -149,7 +149,7 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm) | |||
| 149 | if (resume_on_alarm && (PEDR & PWER_RTC)) | 149 | if (resume_on_alarm && (PEDR & PWER_RTC)) |
| 150 | is_resume |= PWER_RTC; | 150 | is_resume |= PWER_RTC; |
| 151 | 151 | ||
| 152 | dev_dbg(sharpsl_pm.dev, "is_resume: %x\n",is_resume); | 152 | dev_dbg(sharpsl_pm.dev, "is_resume: %x\n", is_resume); |
| 153 | return is_resume; | 153 | return is_resume; |
| 154 | } | 154 | } |
| 155 | 155 | ||
| @@ -160,7 +160,7 @@ static unsigned long spitz_charger_wakeup(void) | |||
| 160 | 160 | ||
| 161 | unsigned long spitzpm_read_devdata(int type) | 161 | unsigned long spitzpm_read_devdata(int type) |
| 162 | { | 162 | { |
| 163 | switch(type) { | 163 | switch (type) { |
| 164 | case SHARPSL_STATUS_ACIN: | 164 | case SHARPSL_STATUS_ACIN: |
| 165 | return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0); | 165 | return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0); |
| 166 | case SHARPSL_STATUS_LOCK: | 166 | case SHARPSL_STATUS_LOCK: |
| @@ -199,7 +199,7 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { | |||
| 199 | #if defined(CONFIG_LCD_CORGI) | 199 | #if defined(CONFIG_LCD_CORGI) |
| 200 | .backlight_limit = corgi_lcd_limit_intensity, | 200 | .backlight_limit = corgi_lcd_limit_intensity, |
| 201 | #elif defined(CONFIG_BACKLIGHT_CORGI) | 201 | #elif defined(CONFIG_BACKLIGHT_CORGI) |
| 202 | .backlight_limit = corgibl_limit_intensity, | 202 | .backlight_limit = corgibl_limit_intensity, |
| 203 | #endif | 203 | #endif |
| 204 | .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, | 204 | .charge_on_volt = SHARPSL_CHARGE_ON_VOLT, |
| 205 | .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, | 205 | .charge_on_temp = SHARPSL_CHARGE_ON_TEMP, |
| @@ -208,8 +208,8 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = { | |||
| 208 | .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, | 208 | .fatal_acin_volt = SHARPSL_FATAL_ACIN_VOLT, |
| 209 | .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, | 209 | .fatal_noacin_volt= SHARPSL_FATAL_NOACIN_VOLT, |
| 210 | .bat_levels = 40, | 210 | .bat_levels = 40, |
| 211 | .bat_levels_noac = spitz_battery_levels_noac, | 211 | .bat_levels_noac = sharpsl_battery_levels_noac, |
| 212 | .bat_levels_acin = spitz_battery_levels_acin, | 212 | .bat_levels_acin = sharpsl_battery_levels_acin, |
| 213 | .status_high_acin = 188, | 213 | .status_high_acin = 188, |
| 214 | .status_low_acin = 178, | 214 | .status_low_acin = 178, |
| 215 | .status_high_noac = 185, | 215 | .status_high_noac = 185, |
| @@ -241,7 +241,7 @@ static int __devinit spitzpm_init(void) | |||
| 241 | 241 | ||
| 242 | static void spitzpm_exit(void) | 242 | static void spitzpm_exit(void) |
| 243 | { | 243 | { |
| 244 | platform_device_unregister(spitzpm_device); | 244 | platform_device_unregister(spitzpm_device); |
| 245 | } | 245 | } |
| 246 | 246 | ||
| 247 | module_init(spitzpm_init); | 247 | module_init(spitzpm_init); |
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 965e38c6bafe..9ebe658590fa 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c | |||
| @@ -342,8 +342,9 @@ void ssp_free(struct ssp_device *ssp) | |||
| 342 | } | 342 | } |
| 343 | EXPORT_SYMBOL(ssp_free); | 343 | EXPORT_SYMBOL(ssp_free); |
| 344 | 344 | ||
| 345 | static int __devinit ssp_probe(struct platform_device *pdev, int type) | 345 | static int __devinit ssp_probe(struct platform_device *pdev) |
| 346 | { | 346 | { |
| 347 | const struct platform_device_id *id = platform_get_device_id(pdev); | ||
| 347 | struct resource *res; | 348 | struct resource *res; |
| 348 | struct ssp_device *ssp; | 349 | struct ssp_device *ssp; |
| 349 | int ret = 0; | 350 | int ret = 0; |
| @@ -413,7 +414,7 @@ static int __devinit ssp_probe(struct platform_device *pdev, int type) | |||
| 413 | */ | 414 | */ |
| 414 | ssp->port_id = pdev->id + 1; | 415 | ssp->port_id = pdev->id + 1; |
| 415 | ssp->use_count = 0; | 416 | ssp->use_count = 0; |
| 416 | ssp->type = type; | 417 | ssp->type = (int)id->driver_data; |
| 417 | 418 | ||
| 418 | mutex_lock(&ssp_lock); | 419 | mutex_lock(&ssp_lock); |
| 419 | list_add(&ssp->node, &ssp_list); | 420 | list_add(&ssp->node, &ssp_list); |
| @@ -457,75 +458,31 @@ static int __devexit ssp_remove(struct platform_device *pdev) | |||
| 457 | return 0; | 458 | return 0; |
| 458 | } | 459 | } |
| 459 | 460 | ||
| 460 | static int __devinit pxa25x_ssp_probe(struct platform_device *pdev) | 461 | static const struct platform_device_id ssp_id_table[] = { |
| 461 | { | 462 | { "pxa25x-ssp", PXA25x_SSP }, |
| 462 | return ssp_probe(pdev, PXA25x_SSP); | 463 | { "pxa25x-nssp", PXA25x_NSSP }, |
| 463 | } | 464 | { "pxa27x-ssp", PXA27x_SSP }, |
| 464 | 465 | { }, | |
| 465 | static int __devinit pxa25x_nssp_probe(struct platform_device *pdev) | ||
| 466 | { | ||
| 467 | return ssp_probe(pdev, PXA25x_NSSP); | ||
| 468 | } | ||
| 469 | |||
| 470 | static int __devinit pxa27x_ssp_probe(struct platform_device *pdev) | ||
| 471 | { | ||
| 472 | return ssp_probe(pdev, PXA27x_SSP); | ||
| 473 | } | ||
| 474 | |||
| 475 | static struct platform_driver pxa25x_ssp_driver = { | ||
| 476 | .driver = { | ||
| 477 | .name = "pxa25x-ssp", | ||
| 478 | }, | ||
| 479 | .probe = pxa25x_ssp_probe, | ||
| 480 | .remove = __devexit_p(ssp_remove), | ||
| 481 | }; | 466 | }; |
| 482 | 467 | ||
| 483 | static struct platform_driver pxa25x_nssp_driver = { | 468 | static struct platform_driver ssp_driver = { |
| 484 | .driver = { | 469 | .probe = ssp_probe, |
| 485 | .name = "pxa25x-nssp", | ||
| 486 | }, | ||
| 487 | .probe = pxa25x_nssp_probe, | ||
| 488 | .remove = __devexit_p(ssp_remove), | 470 | .remove = __devexit_p(ssp_remove), |
| 489 | }; | ||
| 490 | |||
| 491 | static struct platform_driver pxa27x_ssp_driver = { | ||
| 492 | .driver = { | 471 | .driver = { |
| 493 | .name = "pxa27x-ssp", | 472 | .owner = THIS_MODULE, |
| 473 | .name = "pxa2xx-ssp", | ||
| 494 | }, | 474 | }, |
| 495 | .probe = pxa27x_ssp_probe, | 475 | .id_table = ssp_id_table, |
| 496 | .remove = __devexit_p(ssp_remove), | ||
| 497 | }; | 476 | }; |
| 498 | 477 | ||
| 499 | static int __init pxa_ssp_init(void) | 478 | static int __init pxa_ssp_init(void) |
| 500 | { | 479 | { |
| 501 | int ret = 0; | 480 | return platform_driver_register(&ssp_driver); |
| 502 | |||
| 503 | ret = platform_driver_register(&pxa25x_ssp_driver); | ||
| 504 | if (ret) { | ||
| 505 | printk(KERN_ERR "failed to register pxa25x_ssp_driver"); | ||
| 506 | return ret; | ||
| 507 | } | ||
| 508 | |||
| 509 | ret = platform_driver_register(&pxa25x_nssp_driver); | ||
| 510 | if (ret) { | ||
| 511 | printk(KERN_ERR "failed to register pxa25x_nssp_driver"); | ||
| 512 | return ret; | ||
| 513 | } | ||
| 514 | |||
| 515 | ret = platform_driver_register(&pxa27x_ssp_driver); | ||
| 516 | if (ret) { | ||
| 517 | printk(KERN_ERR "failed to register pxa27x_ssp_driver"); | ||
| 518 | return ret; | ||
| 519 | } | ||
| 520 | |||
| 521 | return ret; | ||
| 522 | } | 481 | } |
| 523 | 482 | ||
| 524 | static void __exit pxa_ssp_exit(void) | 483 | static void __exit pxa_ssp_exit(void) |
| 525 | { | 484 | { |
| 526 | platform_driver_unregister(&pxa25x_ssp_driver); | 485 | platform_driver_unregister(&ssp_driver); |
| 527 | platform_driver_unregister(&pxa25x_nssp_driver); | ||
| 528 | platform_driver_unregister(&pxa27x_ssp_driver); | ||
| 529 | } | 486 | } |
| 530 | 487 | ||
| 531 | arch_initcall(pxa_ssp_init); | 488 | arch_initcall(pxa_ssp_init); |
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c index 3b205b69f3fb..a98a434f0111 100644 --- a/arch/arm/mach-pxa/stargate2.c +++ b/arch/arm/mach-pxa/stargate2.c | |||
| @@ -760,6 +760,10 @@ static void __init stargate2_init(void) | |||
| 760 | 760 | ||
| 761 | pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); | 761 | pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config)); |
| 762 | 762 | ||
| 763 | pxa_set_ffuart_info(NULL); | ||
| 764 | pxa_set_btuart_info(NULL); | ||
| 765 | pxa_set_stuart_info(NULL); | ||
| 766 | |||
| 763 | /* spi chip selects */ | 767 | /* spi chip selects */ |
| 764 | gpio_direction_output(37, 0); | 768 | gpio_direction_output(37, 0); |
| 765 | gpio_direction_output(24, 0); | 769 | gpio_direction_output(24, 0); |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index b75353a2ec75..f02dcb5b4e97 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
| @@ -477,6 +477,10 @@ static void __init tavorevb_init(void) | |||
| 477 | /* initialize MFP configurations */ | 477 | /* initialize MFP configurations */ |
| 478 | pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); | 478 | pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg)); |
| 479 | 479 | ||
| 480 | pxa_set_ffuart_info(NULL); | ||
| 481 | pxa_set_btuart_info(NULL); | ||
| 482 | pxa_set_stuart_info(NULL); | ||
| 483 | |||
| 480 | platform_device_register(&smc91x_device); | 484 | platform_device_register(&smc91x_device); |
| 481 | 485 | ||
| 482 | tavorevb_init_lcd(); | 486 | tavorevb_init_lcd(); |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index e81a52673d49..c854c168a451 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -825,6 +825,11 @@ static void __init tosa_init(void) | |||
| 825 | int dummy; | 825 | int dummy; |
| 826 | 826 | ||
| 827 | pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config)); | 827 | pxa2xx_mfp_config(ARRAY_AND_SIZE(tosa_pin_config)); |
| 828 | |||
| 829 | pxa_set_ffuart_info(NULL); | ||
| 830 | pxa_set_btuart_info(NULL); | ||
| 831 | pxa_set_stuart_info(NULL); | ||
| 832 | |||
| 828 | gpio_set_wake(MFP_PIN_GPIO1, 1); | 833 | gpio_set_wake(MFP_PIN_GPIO1, 1); |
| 829 | /* We can't pass to gpio-keys since it will drop the Reset altfunc */ | 834 | /* We can't pass to gpio-keys since it will drop the Reset altfunc */ |
| 830 | 835 | ||
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index 3981e0356d12..0aa858ebc573 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
| @@ -524,6 +524,10 @@ static void __init trizeps4_init(void) | |||
| 524 | ARRAY_SIZE(trizeps4_devices)); | 524 | ARRAY_SIZE(trizeps4_devices)); |
| 525 | } | 525 | } |
| 526 | 526 | ||
| 527 | pxa_set_ffuart_info(NULL); | ||
| 528 | pxa_set_btuart_info(NULL); | ||
| 529 | pxa_set_stuart_info(NULL); | ||
| 530 | |||
| 527 | if (0) /* dont know how to determine LCD */ | 531 | if (0) /* dont know how to determine LCD */ |
| 528 | set_pxa_fb_info(&sharp_lcd); | 532 | set_pxa_fb_info(&sharp_lcd); |
| 529 | else | 533 | else |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index d33c232b686c..cf0d71b7797e 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
| @@ -301,15 +301,6 @@ static void __init viper_init_irq(void) | |||
| 301 | set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), | 301 | set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), |
| 302 | viper_irq_handler); | 302 | viper_irq_handler); |
| 303 | set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); | 303 | set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); |
| 304 | |||
| 305 | #ifndef CONFIG_SERIAL_PXA | ||
| 306 | /* | ||
| 307 | * 8250 doesn't support IRQ_TYPE being passed as part | ||
| 308 | * of the plat_serial8250_port structure... | ||
| 309 | */ | ||
| 310 | set_irq_type(gpio_to_irq(VIPER_UARTA_GPIO), IRQ_TYPE_EDGE_RISING); | ||
| 311 | set_irq_type(gpio_to_irq(VIPER_UARTB_GPIO), IRQ_TYPE_EDGE_RISING); | ||
| 312 | #endif | ||
| 313 | } | 304 | } |
| 314 | 305 | ||
| 315 | /* Flat Panel */ | 306 | /* Flat Panel */ |
| @@ -539,6 +530,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 539 | { | 530 | { |
| 540 | .mapbase = VIPER_UARTA_PHYS, | 531 | .mapbase = VIPER_UARTA_PHYS, |
| 541 | .irq = gpio_to_irq(VIPER_UARTA_GPIO), | 532 | .irq = gpio_to_irq(VIPER_UARTA_GPIO), |
| 533 | .irqflags = IRQF_TRIGGER_RISING, | ||
| 542 | .uartclk = 1843200, | 534 | .uartclk = 1843200, |
| 543 | .regshift = 1, | 535 | .regshift = 1, |
| 544 | .iotype = UPIO_MEM, | 536 | .iotype = UPIO_MEM, |
| @@ -548,6 +540,7 @@ static struct plat_serial8250_port serial_platform_data[] = { | |||
| 548 | { | 540 | { |
| 549 | .mapbase = VIPER_UARTB_PHYS, | 541 | .mapbase = VIPER_UARTB_PHYS, |
| 550 | .irq = gpio_to_irq(VIPER_UARTB_GPIO), | 542 | .irq = gpio_to_irq(VIPER_UARTB_GPIO), |
| 543 | .irqflags = IRQF_TRIGGER_RISING, | ||
| 551 | .uartclk = 1843200, | 544 | .uartclk = 1843200, |
| 552 | .regshift = 1, | 545 | .regshift = 1, |
| 553 | .iotype = UPIO_MEM, | 546 | .iotype = UPIO_MEM, |
| @@ -908,6 +901,10 @@ static void __init viper_init(void) | |||
| 908 | 901 | ||
| 909 | pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config)); | 902 | pxa2xx_mfp_config(ARRAY_AND_SIZE(viper_pin_config)); |
| 910 | 903 | ||
| 904 | pxa_set_ffuart_info(NULL); | ||
| 905 | pxa_set_btuart_info(NULL); | ||
| 906 | pxa_set_stuart_info(NULL); | ||
| 907 | |||
| 911 | /* Wake-up serial console */ | 908 | /* Wake-up serial console */ |
| 912 | viper_init_serial_gpio(); | 909 | viper_init_serial_gpio(); |
| 913 | 910 | ||
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c index 3fd79cbb36c8..d3b4e3f2e033 100644 --- a/arch/arm/mach-pxa/xcep.c +++ b/arch/arm/mach-pxa/xcep.c | |||
| @@ -165,6 +165,11 @@ static void __init xcep_init(void) | |||
| 165 | { | 165 | { |
| 166 | pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config)); | 166 | pxa2xx_mfp_config(ARRAY_AND_SIZE(xcep_pin_config)); |
| 167 | 167 | ||
| 168 | pxa_set_ffuart_info(NULL); | ||
| 169 | pxa_set_btuart_info(NULL); | ||
| 170 | pxa_set_stuart_info(NULL); | ||
| 171 | pxa_set_hwuart_info(NULL); | ||
| 172 | |||
| 168 | /* See Intel XScale Developer's Guide for details */ | 173 | /* See Intel XScale Developer's Guide for details */ |
| 169 | /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ | 174 | /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */ |
| 170 | MSC1 = (MSC1 & 0xffff) | 0xD5540000; | 175 | MSC1 = (MSC1 & 0xffff) | 0xD5540000; |
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c index 09784d3954e4..b66e9e2d06e7 100644 --- a/arch/arm/mach-pxa/zylonite.c +++ b/arch/arm/mach-pxa/zylonite.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <mach/mmc.h> | 31 | #include <mach/mmc.h> |
| 32 | #include <mach/ohci.h> | 32 | #include <mach/ohci.h> |
| 33 | #include <mach/pxa27x_keypad.h> | 33 | #include <mach/pxa27x_keypad.h> |
| 34 | #include <mach/pxa3xx_nand.h> | 34 | #include <plat/pxa3xx_nand.h> |
| 35 | 35 | ||
| 36 | #include "devices.h" | 36 | #include "devices.h" |
| 37 | #include "generic.h" | 37 | #include "generic.h" |
| @@ -444,6 +444,10 @@ static inline void zylonite_init_ohci(void) {} | |||
| 444 | 444 | ||
| 445 | static void __init zylonite_init(void) | 445 | static void __init zylonite_init(void) |
| 446 | { | 446 | { |
| 447 | pxa_set_ffuart_info(NULL); | ||
| 448 | pxa_set_btuart_info(NULL); | ||
| 449 | pxa_set_stuart_info(NULL); | ||
| 450 | |||
| 447 | /* board-processor specific initialization */ | 451 | /* board-processor specific initialization */ |
| 448 | zylonite_pxa300_init(); | 452 | zylonite_pxa300_init(); |
| 449 | zylonite_pxa320_init(); | 453 | zylonite_pxa320_init(); |
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h index 1535540edc82..3fd889200e99 100644 --- a/arch/arm/mach-s3c2400/include/mach/map.h +++ b/arch/arm/mach-s3c2400/include/mach/map.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2400/include/mach/map.h | 1 | /* arch/arm/mach-s3c2400/include/mach/map.h |
| 2 | * | 2 | * |
| 3 | * Copyright 2003,2007 Simtec Electronics | 3 | * Copyright 2003-2007 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 3d4e9da3fa52..dd1fcc7e6708 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
| @@ -81,6 +81,14 @@ config ARCH_H1940 | |||
| 81 | help | 81 | help |
| 82 | Say Y here if you are using the HP IPAQ H1940 | 82 | Say Y here if you are using the HP IPAQ H1940 |
| 83 | 83 | ||
| 84 | config H1940BT | ||
| 85 | tristate "Control the state of H1940 bluetooth chip" | ||
| 86 | depends on ARCH_H1940 | ||
| 87 | select RFKILL | ||
| 88 | help | ||
| 89 | This is a simple driver that is able to control | ||
| 90 | the state of built in bluetooth chip on h1940. | ||
| 91 | |||
| 84 | config PM_H1940 | 92 | config PM_H1940 |
| 85 | bool | 93 | bool |
| 86 | help | 94 | help |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 2ab5ba4b266f..0d468e96e83e 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
| @@ -21,7 +21,8 @@ obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o | |||
| 21 | # Machine support | 21 | # Machine support |
| 22 | 22 | ||
| 23 | obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o | 23 | obj-$(CONFIG_ARCH_SMDK2410) += mach-smdk2410.o |
| 24 | obj-$(CONFIG_ARCH_H1940) += mach-h1940.o h1940-bluetooth.o | 24 | obj-$(CONFIG_ARCH_H1940) += mach-h1940.o |
| 25 | obj-$(CONFIG_H1940BT) += h1940-bluetooth.o | ||
| 25 | obj-$(CONFIG_PM_H1940) += pm-h1940.o | 26 | obj-$(CONFIG_PM_H1940) += pm-h1940.o |
| 26 | obj-$(CONFIG_MACH_N30) += mach-n30.o | 27 | obj-$(CONFIG_MACH_N30) += mach-n30.o |
| 27 | obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o | 28 | obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o |
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c index 9a37c87152b0..217b102866d0 100644 --- a/arch/arm/mach-s3c2410/bast-irq.c +++ b/arch/arm/mach-s3c2410/bast-irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/bast-irq.c | 1 | /* linux/arch/arm/mach-s3c2410/bast-irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2005 Simtec Electronics | 3 | * Copyright 2003-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://www.simtec.co.uk/products/EB2410ITX/ | 6 | * http://www.simtec.co.uk/products/EB2410ITX/ |
| @@ -141,7 +141,7 @@ static __init int bast_irq_init(void) | |||
| 141 | unsigned int i; | 141 | unsigned int i; |
| 142 | 142 | ||
| 143 | if (machine_is_bast()) { | 143 | if (machine_is_bast()) { |
| 144 | printk(KERN_INFO "BAST PC104 IRQ routing, (c) 2005 Simtec Electronics\n"); | 144 | printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n"); |
| 145 | 145 | ||
| 146 | /* zap all the IRQs */ | 146 | /* zap all the IRQs */ |
| 147 | 147 | ||
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c index 9d1186877d08..75189df995ae 100644 --- a/arch/arm/mach-s3c2410/cpu-freq.c +++ b/arch/arm/mach-s3c2410/cpu-freq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/cpu-freq.c | 1 | /* linux/arch/arm/mach-s3c2410/cpu-freq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2008 Simtec Electronics | 3 | * Copyright (c) 2006-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c index 5aabf117cbb0..b7d1f8d27bc2 100644 --- a/arch/arm/mach-s3c2410/h1940-bluetooth.c +++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/ctype.h> | 17 | #include <linux/ctype.h> |
| 18 | #include <linux/leds.h> | 18 | #include <linux/leds.h> |
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | #include <linux/rfkill.h> | ||
| 20 | 21 | ||
| 21 | #include <mach/regs-gpio.h> | 22 | #include <mach/regs-gpio.h> |
| 22 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| @@ -24,21 +25,10 @@ | |||
| 24 | 25 | ||
| 25 | #define DRV_NAME "h1940-bt" | 26 | #define DRV_NAME "h1940-bt" |
| 26 | 27 | ||
| 27 | #ifdef CONFIG_LEDS_H1940 | ||
| 28 | DEFINE_LED_TRIGGER(bt_led_trigger); | ||
| 29 | #endif | ||
| 30 | |||
| 31 | static int state; | ||
| 32 | |||
| 33 | /* Bluetooth control */ | 28 | /* Bluetooth control */ |
| 34 | static void h1940bt_enable(int on) | 29 | static void h1940bt_enable(int on) |
| 35 | { | 30 | { |
| 36 | if (on) { | 31 | if (on) { |
| 37 | #ifdef CONFIG_LEDS_H1940 | ||
| 38 | /* flashing Blue */ | ||
| 39 | led_trigger_event(bt_led_trigger, LED_HALF); | ||
| 40 | #endif | ||
| 41 | |||
| 42 | /* Power on the chip */ | 32 | /* Power on the chip */ |
| 43 | h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); | 33 | h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER); |
| 44 | /* Reset the chip */ | 34 | /* Reset the chip */ |
| @@ -46,48 +36,31 @@ static void h1940bt_enable(int on) | |||
| 46 | s3c2410_gpio_setpin(S3C2410_GPH(1), 1); | 36 | s3c2410_gpio_setpin(S3C2410_GPH(1), 1); |
| 47 | mdelay(10); | 37 | mdelay(10); |
| 48 | s3c2410_gpio_setpin(S3C2410_GPH(1), 0); | 38 | s3c2410_gpio_setpin(S3C2410_GPH(1), 0); |
| 49 | |||
| 50 | state = 1; | ||
| 51 | } | 39 | } |
| 52 | else { | 40 | else { |
| 53 | #ifdef CONFIG_LEDS_H1940 | ||
| 54 | led_trigger_event(bt_led_trigger, 0); | ||
| 55 | #endif | ||
| 56 | |||
| 57 | s3c2410_gpio_setpin(S3C2410_GPH(1), 1); | 41 | s3c2410_gpio_setpin(S3C2410_GPH(1), 1); |
| 58 | mdelay(10); | 42 | mdelay(10); |
| 59 | s3c2410_gpio_setpin(S3C2410_GPH(1), 0); | 43 | s3c2410_gpio_setpin(S3C2410_GPH(1), 0); |
| 60 | mdelay(10); | 44 | mdelay(10); |
| 61 | h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); | 45 | h1940_latch_control(H1940_LATCH_BLUETOOTH_POWER, 0); |
| 62 | |||
| 63 | state = 0; | ||
| 64 | } | 46 | } |
| 65 | } | 47 | } |
| 66 | 48 | ||
| 67 | static ssize_t h1940bt_show(struct device *dev, struct device_attribute *attr, char *buf) | 49 | static int h1940bt_set_block(void *data, bool blocked) |
| 68 | { | 50 | { |
| 69 | return snprintf(buf, PAGE_SIZE, "%d\n", state); | 51 | h1940bt_enable(!blocked); |
| 52 | return 0; | ||
| 70 | } | 53 | } |
| 71 | 54 | ||
| 72 | static ssize_t h1940bt_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) | 55 | static const struct rfkill_ops h1940bt_rfkill_ops = { |
| 73 | { | 56 | .set_block = h1940bt_set_block, |
| 74 | int new_state; | 57 | }; |
| 75 | char *endp; | ||
| 76 | |||
| 77 | new_state = simple_strtoul(buf, &endp, 0); | ||
| 78 | if (*endp && !isspace(*endp)) | ||
| 79 | return -EINVAL; | ||
| 80 | |||
| 81 | h1940bt_enable(new_state); | ||
| 82 | |||
| 83 | return count; | ||
| 84 | } | ||
| 85 | static DEVICE_ATTR(enable, 0644, | ||
| 86 | h1940bt_show, | ||
| 87 | h1940bt_store); | ||
| 88 | 58 | ||
| 89 | static int __init h1940bt_probe(struct platform_device *pdev) | 59 | static int __init h1940bt_probe(struct platform_device *pdev) |
| 90 | { | 60 | { |
| 61 | struct rfkill *rfk; | ||
| 62 | int ret = 0; | ||
| 63 | |||
| 91 | /* Configures BT serial port GPIOs */ | 64 | /* Configures BT serial port GPIOs */ |
| 92 | s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); | 65 | s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0); |
| 93 | s3c2410_gpio_pullup(S3C2410_GPH(0), 1); | 66 | s3c2410_gpio_pullup(S3C2410_GPH(0), 1); |
| @@ -98,21 +71,44 @@ static int __init h1940bt_probe(struct platform_device *pdev) | |||
| 98 | s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); | 71 | s3c2410_gpio_cfgpin(S3C2410_GPH(3), S3C2410_GPH3_RXD0); |
| 99 | s3c2410_gpio_pullup(S3C2410_GPH(3), 1); | 72 | s3c2410_gpio_pullup(S3C2410_GPH(3), 1); |
| 100 | 73 | ||
| 101 | #ifdef CONFIG_LEDS_H1940 | ||
| 102 | led_trigger_register_simple("h1940-bluetooth", &bt_led_trigger); | ||
| 103 | #endif | ||
| 104 | 74 | ||
| 105 | /* disable BT by default */ | 75 | rfk = rfkill_alloc(DRV_NAME, &pdev->dev, RFKILL_TYPE_BLUETOOTH, |
| 106 | h1940bt_enable(0); | 76 | &h1940bt_rfkill_ops, NULL); |
| 77 | if (!rfk) { | ||
| 78 | ret = -ENOMEM; | ||
| 79 | goto err_rfk_alloc; | ||
| 80 | } | ||
| 81 | |||
| 82 | rfkill_set_led_trigger_name(rfk, "h1940-bluetooth"); | ||
| 83 | |||
| 84 | ret = rfkill_register(rfk); | ||
| 85 | if (ret) | ||
| 86 | goto err_rfkill; | ||
| 87 | |||
| 88 | platform_set_drvdata(pdev, rfk); | ||
| 89 | |||
| 90 | return 0; | ||
| 107 | 91 | ||
| 108 | return device_create_file(&pdev->dev, &dev_attr_enable); | 92 | err_rfkill: |
| 93 | rfkill_destroy(rfk); | ||
| 94 | err_rfk_alloc: | ||
| 95 | return ret; | ||
| 109 | } | 96 | } |
| 110 | 97 | ||
| 111 | static int h1940bt_remove(struct platform_device *pdev) | 98 | static int h1940bt_remove(struct platform_device *pdev) |
| 112 | { | 99 | { |
| 113 | #ifdef CONFIG_LEDS_H1940 | 100 | struct rfkill *rfk = platform_get_drvdata(pdev); |
| 114 | led_trigger_unregister_simple(bt_led_trigger); | 101 | |
| 115 | #endif | 102 | platform_set_drvdata(pdev, NULL); |
| 103 | |||
| 104 | if (rfk) { | ||
| 105 | rfkill_unregister(rfk); | ||
| 106 | rfkill_destroy(rfk); | ||
| 107 | } | ||
| 108 | rfk = NULL; | ||
| 109 | |||
| 110 | h1940bt_enable(0); | ||
| 111 | |||
| 116 | return 0; | 112 | return 0; |
| 117 | } | 113 | } |
| 118 | 114 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h index 20493b048360..bee2a7a932a0 100644 --- a/arch/arm/mach-s3c2410/include/mach/bast-cpld.h +++ b/arch/arm/mach-s3c2410/include/mach/bast-cpld.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/bast-cpld.h | 1 | /* arch/arm/mach-s3c2410/include/mach/bast-cpld.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * BAST - CPLD control constants | 6 | * BAST - CPLD control constants |
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-irq.h b/arch/arm/mach-s3c2410/include/mach/bast-irq.h index 501c202b53cf..cac428c42e7f 100644 --- a/arch/arm/mach-s3c2410/include/mach/bast-irq.h +++ b/arch/arm/mach-s3c2410/include/mach/bast-irq.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/bast-irq.h | 1 | /* arch/arm/mach-s3c2410/include/mach/bast-irq.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Machine BAST - IRQ Number definitions | 6 | * Machine BAST - IRQ Number definitions |
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-map.h b/arch/arm/mach-s3c2410/include/mach/bast-map.h index c2c5baf07345..6e7dc9d0cf0e 100644 --- a/arch/arm/mach-s3c2410/include/mach/bast-map.h +++ b/arch/arm/mach-s3c2410/include/mach/bast-map.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/bast-map.h | 1 | /* arch/arm/mach-s3c2410/include/mach/bast-map.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Machine BAST - Memory map definitions | 6 | * Machine BAST - Memory map definitions |
diff --git a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h index 61684cb8ce59..4c38b39b741d 100644 --- a/arch/arm/mach-s3c2410/include/mach/bast-pmu.h +++ b/arch/arm/mach-s3c2410/include/mach/bast-pmu.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h | 1 | /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * Vincent Sanders <vince@simtec.co.uk> | 5 | * Vincent Sanders <vince@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h index 92e2687009ea..08ac5f96c012 100644 --- a/arch/arm/mach-s3c2410/include/mach/dma.h +++ b/arch/arm/mach-s3c2410/include/mach/dma.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/dma.h | 1 | /* arch/arm/mach-s3c2410/include/mach/dma.h |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2003,2004,2006 Simtec Electronics | 3 | * Copyright (C) 2003-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Samsung S3C24XX DMA support | 6 | * Samsung S3C24XX DMA support |
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index 801dff13858d..035a493952db 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h | 1 | /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2009 Simtec Electronics | 3 | * Copyright (c) 2003-2009 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * S3C2410 - hardware | 6 | * S3C2410 - hardware |
diff --git a/arch/arm/mach-s3c2410/include/mach/osiris-map.h b/arch/arm/mach-s3c2410/include/mach/osiris-map.h index 639eff523d4e..17380f848428 100644 --- a/arch/arm/mach-s3c2410/include/mach/osiris-map.h +++ b/arch/arm/mach-s3c2410/include/mach/osiris-map.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/osiris-map.h | 1 | /* arch/arm/mach-s3c2410/include/mach/osiris-map.h |
| 2 | * | 2 | * |
| 3 | * (c) 2005 Simtec Electronics | 3 | * Copyright 2005 Simtec Electronics |
| 4 | * http://www.simtec.co.uk/products/ | 4 | * http://www.simtec.co.uk/products/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h index 2a5d90e957fb..9a0d169be137 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-clock.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-clock.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index f6e8eec879c8..ebc85c6dadbf 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpio.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003-2004 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-power.h b/arch/arm/mach-s3c2410/include/mach/regs-power.h index 2d36353f57d7..4932b87bdf3d 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-power.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-power.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-power.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-power.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h index c9432103750d..72f756c5e504 100644 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | |||
| 2 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h | 1 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h |
| 3 | * | 2 | * |
| 4 | * Copyright (c) 2003, 2007 Simtec Electronics | 3 | * Copyright (c) 2003-2007 Simtec Electronics |
| 5 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 6 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 7 | * | 6 | * |
diff --git a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h index f53f85b4ad8b..47add133b8ee 100644 --- a/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h +++ b/arch/arm/mach-s3c2410/include/mach/vr1000-irq.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h | 1 | /* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Machine VR1000 - IRQ Number definitions | 6 | * Machine VR1000 - IRQ Number definitions |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 647c9adb018f..4c79ac8a6c33 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/mach-bast.c | 1 | /* linux/arch/arm/mach-s3c2410/mach-bast.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003-2005,2008 Simtec Electronics | 3 | * Copyright 2003-2008 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://www.simtec.co.uk/products/EB2410ITX/ | 6 | * http://www.simtec.co.uk/products/EB2410ITX/ |
| @@ -61,11 +61,12 @@ | |||
| 61 | #include <plat/devs.h> | 61 | #include <plat/devs.h> |
| 62 | #include <plat/cpu.h> | 62 | #include <plat/cpu.h> |
| 63 | #include <plat/cpu-freq.h> | 63 | #include <plat/cpu-freq.h> |
| 64 | #include <plat/audio-simtec.h> | ||
| 64 | 65 | ||
| 65 | #include "usb-simtec.h" | 66 | #include "usb-simtec.h" |
| 66 | #include "nor-simtec.h" | 67 | #include "nor-simtec.h" |
| 67 | 68 | ||
| 68 | #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" | 69 | #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics" |
| 69 | 70 | ||
| 70 | /* macros for virtual address mods for the io space entries */ | 71 | /* macros for virtual address mods for the io space entries */ |
| 71 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) | 72 | #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) |
| @@ -247,7 +248,7 @@ static int chip0_map[] = { 1 }; | |||
| 247 | static int chip1_map[] = { 2 }; | 248 | static int chip1_map[] = { 2 }; |
| 248 | static int chip2_map[] = { 3 }; | 249 | static int chip2_map[] = { 3 }; |
| 249 | 250 | ||
| 250 | static struct mtd_partition bast_default_nand_part[] = { | 251 | static struct mtd_partition __initdata bast_default_nand_part[] = { |
| 251 | [0] = { | 252 | [0] = { |
| 252 | .name = "Boot Agent", | 253 | .name = "Boot Agent", |
| 253 | .size = SZ_16K, | 254 | .size = SZ_16K, |
| @@ -273,7 +274,7 @@ static struct mtd_partition bast_default_nand_part[] = { | |||
| 273 | * socket. | 274 | * socket. |
| 274 | */ | 275 | */ |
| 275 | 276 | ||
| 276 | static struct s3c2410_nand_set bast_nand_sets[] = { | 277 | static struct s3c2410_nand_set __initdata bast_nand_sets[] = { |
| 277 | [0] = { | 278 | [0] = { |
| 278 | .name = "SmartMedia", | 279 | .name = "SmartMedia", |
| 279 | .nr_chips = 1, | 280 | .nr_chips = 1, |
| @@ -323,7 +324,7 @@ static void bast_nand_select(struct s3c2410_nand_set *set, int slot) | |||
| 323 | __raw_writeb(tmp, BAST_VA_CTRL2); | 324 | __raw_writeb(tmp, BAST_VA_CTRL2); |
| 324 | } | 325 | } |
| 325 | 326 | ||
| 326 | static struct s3c2410_platform_nand bast_nand_info = { | 327 | static struct s3c2410_platform_nand __initdata bast_nand_info = { |
| 327 | .tacls = 30, | 328 | .tacls = 30, |
| 328 | .twrph0 = 60, | 329 | .twrph0 = 60, |
| 329 | .twrph1 = 60, | 330 | .twrph1 = 60, |
| @@ -608,6 +609,11 @@ static struct s3c_cpufreq_board __initdata bast_cpufreq = { | |||
| 608 | .need_io = 1, | 609 | .need_io = 1, |
| 609 | }; | 610 | }; |
| 610 | 611 | ||
| 612 | static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = { | ||
| 613 | .have_mic = 1, | ||
| 614 | .have_lout = 1, | ||
| 615 | }; | ||
| 616 | |||
| 611 | static void __init bast_map_io(void) | 617 | static void __init bast_map_io(void) |
| 612 | { | 618 | { |
| 613 | /* initialise the clocks */ | 619 | /* initialise the clocks */ |
| @@ -625,7 +631,6 @@ static void __init bast_map_io(void) | |||
| 625 | 631 | ||
| 626 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); | 632 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
| 627 | 633 | ||
| 628 | s3c_device_nand.dev.platform_data = &bast_nand_info; | ||
| 629 | s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; | 634 | s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; |
| 630 | 635 | ||
| 631 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | 636 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
| @@ -639,6 +644,7 @@ static void __init bast_init(void) | |||
| 639 | sysdev_register(&bast_pm_sysdev); | 644 | sysdev_register(&bast_pm_sysdev); |
| 640 | 645 | ||
| 641 | s3c_i2c0_set_platdata(&bast_i2c_info); | 646 | s3c_i2c0_set_platdata(&bast_i2c_info); |
| 647 | s3c_nand_set_platdata(&bast_nand_info); | ||
| 642 | s3c24xx_fb_set_platdata(&bast_fb_info); | 648 | s3c24xx_fb_set_platdata(&bast_fb_info); |
| 643 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); | 649 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
| 644 | 650 | ||
| @@ -647,6 +653,7 @@ static void __init bast_init(void) | |||
| 647 | 653 | ||
| 648 | usb_simtec_init(); | 654 | usb_simtec_init(); |
| 649 | nor_simtec_init(); | 655 | nor_simtec_init(); |
| 656 | simtec_audio_add(NULL, true, &bast_audio); | ||
| 650 | 657 | ||
| 651 | s3c_cpufreq_setboard(&bast_cpufreq); | 658 | s3c_cpufreq_setboard(&bast_cpufreq); |
| 652 | } | 659 | } |
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index d9cd5ddecf4a..49053254c98d 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
| @@ -21,6 +21,11 @@ | |||
| 21 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
| 22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/pwm_backlight.h> | ||
| 26 | #include <video/platform_lcd.h> | ||
| 27 | |||
| 28 | #include <linux/mmc/host.h> | ||
| 24 | 29 | ||
| 25 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| @@ -32,9 +37,12 @@ | |||
| 32 | 37 | ||
| 33 | #include <plat/regs-serial.h> | 38 | #include <plat/regs-serial.h> |
| 34 | #include <mach/regs-lcd.h> | 39 | #include <mach/regs-lcd.h> |
| 35 | #include <mach/regs-gpio.h> | ||
| 36 | #include <mach/regs-clock.h> | 40 | #include <mach/regs-clock.h> |
| 37 | 41 | ||
| 42 | #include <mach/regs-gpio.h> | ||
| 43 | #include <mach/gpio-fns.h> | ||
| 44 | #include <mach/gpio-nrs.h> | ||
| 45 | |||
| 38 | #include <mach/h1940.h> | 46 | #include <mach/h1940.h> |
| 39 | #include <mach/h1940-latch.h> | 47 | #include <mach/h1940-latch.h> |
| 40 | #include <mach/fb.h> | 48 | #include <mach/fb.h> |
| @@ -46,6 +54,7 @@ | |||
| 46 | #include <plat/cpu.h> | 54 | #include <plat/cpu.h> |
| 47 | #include <plat/pll.h> | 55 | #include <plat/pll.h> |
| 48 | #include <plat/pm.h> | 56 | #include <plat/pm.h> |
| 57 | #include <plat/mci.h> | ||
| 49 | 58 | ||
| 50 | static struct map_desc h1940_iodesc[] __initdata = { | 59 | static struct map_desc h1940_iodesc[] __initdata = { |
| 51 | [0] = { | 60 | [0] = { |
| @@ -171,16 +180,90 @@ static struct s3c2410fb_mach_info h1940_fb_info __initdata = { | |||
| 171 | .gpdup_mask= 0xffffffff, | 180 | .gpdup_mask= 0xffffffff, |
| 172 | }; | 181 | }; |
| 173 | 182 | ||
| 174 | static struct platform_device s3c_device_leds = { | 183 | static struct platform_device h1940_device_leds = { |
| 175 | .name = "h1940-leds", | 184 | .name = "h1940-leds", |
| 176 | .id = -1, | 185 | .id = -1, |
| 177 | }; | 186 | }; |
| 178 | 187 | ||
| 179 | static struct platform_device s3c_device_bluetooth = { | 188 | static struct platform_device h1940_device_bluetooth = { |
| 180 | .name = "h1940-bt", | 189 | .name = "h1940-bt", |
| 181 | .id = -1, | 190 | .id = -1, |
| 182 | }; | 191 | }; |
| 183 | 192 | ||
| 193 | static struct s3c24xx_mci_pdata h1940_mmc_cfg = { | ||
| 194 | .gpio_detect = S3C2410_GPF(5), | ||
| 195 | .gpio_wprotect = S3C2410_GPH(8), | ||
| 196 | .set_power = NULL, | ||
| 197 | .ocr_avail = MMC_VDD_32_33, | ||
| 198 | }; | ||
| 199 | |||
| 200 | static int h1940_backlight_init(struct device *dev) | ||
| 201 | { | ||
| 202 | gpio_request(S3C2410_GPB(0), "Backlight"); | ||
| 203 | |||
| 204 | s3c2410_gpio_setpin(S3C2410_GPB(0), 0); | ||
| 205 | s3c2410_gpio_pullup(S3C2410_GPB(0), 0); | ||
| 206 | s3c2410_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); | ||
| 207 | |||
| 208 | return 0; | ||
| 209 | } | ||
| 210 | |||
| 211 | static void h1940_backlight_exit(struct device *dev) | ||
| 212 | { | ||
| 213 | s3c2410_gpio_cfgpin(S3C2410_GPB(0), 1/*S3C2410_GPB0_OUTP*/); | ||
| 214 | } | ||
| 215 | |||
| 216 | static struct platform_pwm_backlight_data backlight_data = { | ||
| 217 | .pwm_id = 0, | ||
| 218 | .max_brightness = 100, | ||
| 219 | .dft_brightness = 50, | ||
| 220 | /* tcnt = 0x31 */ | ||
| 221 | .pwm_period_ns = 36296, | ||
| 222 | .init = h1940_backlight_init, | ||
| 223 | .exit = h1940_backlight_exit, | ||
| 224 | }; | ||
| 225 | |||
| 226 | static struct platform_device h1940_backlight = { | ||
| 227 | .name = "pwm-backlight", | ||
| 228 | .dev = { | ||
| 229 | .parent = &s3c_device_timer[0].dev, | ||
| 230 | .platform_data = &backlight_data, | ||
| 231 | }, | ||
| 232 | .id = -1, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static void h1940_lcd_power_set(struct plat_lcd_data *pd, | ||
| 236 | unsigned int power) | ||
| 237 | { | ||
| 238 | int value; | ||
| 239 | |||
| 240 | if (!power) { | ||
| 241 | /* set to 3ec */ | ||
| 242 | s3c2410_gpio_setpin(S3C2410_GPC(0), 0); | ||
| 243 | /* wait for 3ac */ | ||
| 244 | do { | ||
| 245 | value = s3c2410_gpio_getpin(S3C2410_GPC(6)); | ||
| 246 | } while (value); | ||
| 247 | /* set to 38c */ | ||
| 248 | s3c2410_gpio_setpin(S3C2410_GPC(5), 0); | ||
| 249 | } else { | ||
| 250 | /* Set to 3ac */ | ||
| 251 | s3c2410_gpio_setpin(S3C2410_GPC(5), 1); | ||
| 252 | /* Set to 3ad */ | ||
| 253 | s3c2410_gpio_setpin(S3C2410_GPC(0), 1); | ||
| 254 | } | ||
| 255 | } | ||
| 256 | |||
| 257 | static struct plat_lcd_data h1940_lcd_power_data = { | ||
| 258 | .set_power = h1940_lcd_power_set, | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct platform_device h1940_lcd_powerdev = { | ||
| 262 | .name = "platform-lcd", | ||
| 263 | .dev.parent = &s3c_device_lcd.dev, | ||
| 264 | .dev.platform_data = &h1940_lcd_power_data, | ||
| 265 | }; | ||
| 266 | |||
| 184 | static struct platform_device *h1940_devices[] __initdata = { | 267 | static struct platform_device *h1940_devices[] __initdata = { |
| 185 | &s3c_device_usb, | 268 | &s3c_device_usb, |
| 186 | &s3c_device_lcd, | 269 | &s3c_device_lcd, |
| @@ -188,8 +271,13 @@ static struct platform_device *h1940_devices[] __initdata = { | |||
| 188 | &s3c_device_i2c0, | 271 | &s3c_device_i2c0, |
| 189 | &s3c_device_iis, | 272 | &s3c_device_iis, |
| 190 | &s3c_device_usbgadget, | 273 | &s3c_device_usbgadget, |
| 191 | &s3c_device_leds, | 274 | &h1940_device_leds, |
| 192 | &s3c_device_bluetooth, | 275 | &h1940_device_bluetooth, |
| 276 | &s3c_device_sdi, | ||
| 277 | &s3c_device_rtc, | ||
| 278 | &s3c_device_timer[0], | ||
| 279 | &h1940_backlight, | ||
| 280 | &h1940_lcd_powerdev, | ||
| 193 | }; | 281 | }; |
| 194 | 282 | ||
| 195 | static void __init h1940_map_io(void) | 283 | static void __init h1940_map_io(void) |
| @@ -219,6 +307,8 @@ static void __init h1940_init(void) | |||
| 219 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); | 307 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); |
| 220 | s3c_i2c0_set_platdata(NULL); | 308 | s3c_i2c0_set_platdata(NULL); |
| 221 | 309 | ||
| 310 | s3c_device_sdi.dev.platform_data = &h1940_mmc_cfg; | ||
| 311 | |||
| 222 | /* Turn off suspend on both USB ports, and switch the | 312 | /* Turn off suspend on both USB ports, and switch the |
| 223 | * selectable USB port to USB device mode. */ | 313 | * selectable USB port to USB device mode. */ |
| 224 | 314 | ||
| @@ -231,6 +321,11 @@ static void __init h1940_init(void) | |||
| 231 | | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); | 321 | | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); |
| 232 | writel(tmp, S3C2410_UPLLCON); | 322 | writel(tmp, S3C2410_UPLLCON); |
| 233 | 323 | ||
| 324 | gpio_request(S3C2410_GPC(0), "LCD power"); | ||
| 325 | gpio_request(S3C2410_GPC(5), "LCD power"); | ||
| 326 | gpio_request(S3C2410_GPC(6), "LCD power"); | ||
| 327 | |||
| 328 | |||
| 234 | platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); | 329 | platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); |
| 235 | } | 330 | } |
| 236 | 331 | ||
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 0f6ed61af415..0405712c2263 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c | |||
| @@ -338,7 +338,7 @@ static struct platform_device *n35_devices[] __initdata = { | |||
| 338 | &n35_button_device, | 338 | &n35_button_device, |
| 339 | }; | 339 | }; |
| 340 | 340 | ||
| 341 | static struct s3c2410_platform_i2c n30_i2ccfg = { | 341 | static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { |
| 342 | .flags = 0, | 342 | .flags = 0, |
| 343 | .slave_addr = 0x10, | 343 | .slave_addr = 0x10, |
| 344 | .frequency = 10*1000, | 344 | .frequency = 10*1000, |
| @@ -500,8 +500,8 @@ static void __init n30_init_irq(void) | |||
| 500 | static void __init n30_init(void) | 500 | static void __init n30_init(void) |
| 501 | { | 501 | { |
| 502 | s3c24xx_fb_set_platdata(&n30_fb_info); | 502 | s3c24xx_fb_set_platdata(&n30_fb_info); |
| 503 | s3c_device_i2c0.dev.platform_data = &n30_i2ccfg; | ||
| 504 | s3c24xx_udc_set_platdata(&n30_udc_cfg); | 503 | s3c24xx_udc_set_platdata(&n30_udc_cfg); |
| 504 | s3c_i2c0_set_platdata(&n30_i2ccfg); | ||
| 505 | 505 | ||
| 506 | /* Turn off suspend on both USB ports, and switch the | 506 | /* Turn off suspend on both USB ports, and switch the |
| 507 | * selectable USB port to USB device mode. */ | 507 | * selectable USB port to USB device mode. */ |
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 2cc9849eb448..ab092bcda393 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c | |||
| @@ -258,7 +258,7 @@ static struct platform_device *qt2410_devices[] __initdata = { | |||
| 258 | &qt2410_led, | 258 | &qt2410_led, |
| 259 | }; | 259 | }; |
| 260 | 260 | ||
| 261 | static struct mtd_partition qt2410_nand_part[] = { | 261 | static struct mtd_partition __initdata qt2410_nand_part[] = { |
| 262 | [0] = { | 262 | [0] = { |
| 263 | .name = "U-Boot", | 263 | .name = "U-Boot", |
| 264 | .size = 0x30000, | 264 | .size = 0x30000, |
| @@ -286,7 +286,7 @@ static struct mtd_partition qt2410_nand_part[] = { | |||
| 286 | }, | 286 | }, |
| 287 | }; | 287 | }; |
| 288 | 288 | ||
| 289 | static struct s3c2410_nand_set qt2410_nand_sets[] = { | 289 | static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = { |
| 290 | [0] = { | 290 | [0] = { |
| 291 | .name = "NAND", | 291 | .name = "NAND", |
| 292 | .nr_chips = 1, | 292 | .nr_chips = 1, |
| @@ -299,7 +299,7 @@ static struct s3c2410_nand_set qt2410_nand_sets[] = { | |||
| 299 | * chips and beyond. | 299 | * chips and beyond. |
| 300 | */ | 300 | */ |
| 301 | 301 | ||
| 302 | static struct s3c2410_platform_nand qt2410_nand_info = { | 302 | static struct s3c2410_platform_nand __initdata qt2410_nand_info = { |
| 303 | .tacls = 20, | 303 | .tacls = 20, |
| 304 | .twrph0 = 60, | 304 | .twrph0 = 60, |
| 305 | .twrph1 = 20, | 305 | .twrph1 = 20, |
| @@ -331,7 +331,7 @@ static void __init qt2410_map_io(void) | |||
| 331 | 331 | ||
| 332 | static void __init qt2410_machine_init(void) | 332 | static void __init qt2410_machine_init(void) |
| 333 | { | 333 | { |
| 334 | s3c_device_nand.dev.platform_data = &qt2410_nand_info; | 334 | s3c_nand_set_platdata(&qt2410_nand_info); |
| 335 | 335 | ||
| 336 | switch (tft_type) { | 336 | switch (tft_type) { |
| 337 | case 'p': /* production */ | 337 | case 'p': /* production */ |
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 1628cc773a2c..0d61fb577170 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/mach-vr1000.c | 1 | /* linux/arch/arm/mach-s3c2410/mach-vr1000.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003-2005,2008 Simtec Electronics | 3 | * Copyright (c) 2003-2008 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Machine support for Thorcom VR1000 board. Designed for Thorcom by | 6 | * Machine support for Thorcom VR1000 board. Designed for Thorcom by |
| @@ -49,6 +49,7 @@ | |||
| 49 | #include <plat/devs.h> | 49 | #include <plat/devs.h> |
| 50 | #include <plat/cpu.h> | 50 | #include <plat/cpu.h> |
| 51 | #include <plat/iic.h> | 51 | #include <plat/iic.h> |
| 52 | #include <plat/audio-simtec.h> | ||
| 52 | 53 | ||
| 53 | #include "usb-simtec.h" | 54 | #include "usb-simtec.h" |
| 54 | #include "nor-simtec.h" | 55 | #include "nor-simtec.h" |
| @@ -393,6 +394,7 @@ static void __init vr1000_init(void) | |||
| 393 | ARRAY_SIZE(vr1000_i2c_devs)); | 394 | ARRAY_SIZE(vr1000_i2c_devs)); |
| 394 | 395 | ||
| 395 | nor_simtec_init(); | 396 | nor_simtec_init(); |
| 397 | simtec_audio_add(NULL, true, NULL); | ||
| 396 | } | 398 | } |
| 397 | 399 | ||
| 398 | MACHINE_START(VR1000, "Thorcom-VR1000") | 400 | MACHINE_START(VR1000, "Thorcom-VR1000") |
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c index f178c2fd9d85..8338865e11c0 100644 --- a/arch/arm/mach-s3c2410/pll.c +++ b/arch/arm/mach-s3c2410/pll.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/pll.c | 1 | /* arch/arm/mach-s3c2410/pll.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2007 Simtec Electronics | 3 | * Copyright (c) 2006-2007 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * Vincent Sanders <vince@arm.linux.org.uk> | 6 | * Vincent Sanders <vince@arm.linux.org.uk> |
diff --git a/arch/arm/mach-s3c2410/usb-simtec.c b/arch/arm/mach-s3c2410/usb-simtec.c index 50e25fc5f8ab..6b9d0d83a6f9 100644 --- a/arch/arm/mach-s3c2410/usb-simtec.c +++ b/arch/arm/mach-s3c2410/usb-simtec.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2410/usb-simtec.c | 1 | /* linux/arch/arm/mach-s3c2410/usb-simtec.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2005 Simtec Electronics | 3 | * Copyright 2004-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://www.simtec.co.uk/products/EB2410ITX/ | 6 | * http://www.simtec.co.uk/products/EB2410ITX/ |
| @@ -108,7 +108,7 @@ int usb_simtec_init(void) | |||
| 108 | { | 108 | { |
| 109 | int ret; | 109 | int ret; |
| 110 | 110 | ||
| 111 | printk("USB Power Control, (c) 2004 Simtec Electronics\n"); | 111 | printk("USB Power Control, Copyright 2004 Simtec Electronics\n"); |
| 112 | 112 | ||
| 113 | ret = gpio_request(S3C2410_GPB(4), "USB power control"); | 113 | ret = gpio_request(S3C2410_GPB(4), "USB power control"); |
| 114 | if (ret < 0) { | 114 | if (ret < 0) { |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 8df506eac903..c9fa3fca486c 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
| @@ -96,7 +96,7 @@ static struct s3c2410_uartcfg jive_uartcfgs[] = { | |||
| 96 | * 0x017d0000-0x02bd0000 : cramfs B | 96 | * 0x017d0000-0x02bd0000 : cramfs B |
| 97 | * 0x02bd0000-0x03fd0000 : yaffs | 97 | * 0x02bd0000-0x03fd0000 : yaffs |
| 98 | */ | 98 | */ |
| 99 | static struct mtd_partition jive_imageA_nand_part[] = { | 99 | static struct mtd_partition __initdata jive_imageA_nand_part[] = { |
| 100 | 100 | ||
| 101 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER | 101 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER |
| 102 | /* Don't allow access to the bootloader from linux */ | 102 | /* Don't allow access to the bootloader from linux */ |
| @@ -154,7 +154,7 @@ static struct mtd_partition jive_imageA_nand_part[] = { | |||
| 154 | }, | 154 | }, |
| 155 | }; | 155 | }; |
| 156 | 156 | ||
| 157 | static struct mtd_partition jive_imageB_nand_part[] = { | 157 | static struct mtd_partition __initdata jive_imageB_nand_part[] = { |
| 158 | 158 | ||
| 159 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER | 159 | #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER |
| 160 | /* Don't allow access to the bootloader from linux */ | 160 | /* Don't allow access to the bootloader from linux */ |
| @@ -213,7 +213,7 @@ static struct mtd_partition jive_imageB_nand_part[] = { | |||
| 213 | }, | 213 | }, |
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | static struct s3c2410_nand_set jive_nand_sets[] = { | 216 | static struct s3c2410_nand_set __initdata jive_nand_sets[] = { |
| 217 | [0] = { | 217 | [0] = { |
| 218 | .name = "flash", | 218 | .name = "flash", |
| 219 | .nr_chips = 1, | 219 | .nr_chips = 1, |
| @@ -222,7 +222,7 @@ static struct s3c2410_nand_set jive_nand_sets[] = { | |||
| 222 | }, | 222 | }, |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | static struct s3c2410_platform_nand jive_nand_info = { | 225 | static struct s3c2410_platform_nand __initdata jive_nand_info = { |
| 226 | /* set taken from osiris nand timings, possibly still conservative */ | 226 | /* set taken from osiris nand timings, possibly still conservative */ |
| 227 | .tacls = 30, | 227 | .tacls = 30, |
| 228 | .twrph0 = 55, | 228 | .twrph0 = 55, |
| @@ -631,7 +631,8 @@ static void __init jive_machine_init(void) | |||
| 631 | 631 | ||
| 632 | s3c_pm_init(); | 632 | s3c_pm_init(); |
| 633 | 633 | ||
| 634 | s3c_device_nand.dev.platform_data = &jive_nand_info; | 634 | /** TODO - check that this is after the cmdline option! */ |
| 635 | s3c_nand_set_platdata(&jive_nand_info); | ||
| 635 | 636 | ||
| 636 | /* initialise the spi */ | 637 | /* initialise the spi */ |
| 637 | 638 | ||
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index 11e8ad49fc7b..a6ba591b26bb 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c | |||
| @@ -76,7 +76,7 @@ static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = { | |||
| 76 | } | 76 | } |
| 77 | }; | 77 | }; |
| 78 | 78 | ||
| 79 | static struct mtd_partition vstms_nand_part[] = { | 79 | static struct mtd_partition __initdata vstms_nand_part[] = { |
| 80 | [0] = { | 80 | [0] = { |
| 81 | .name = "Boot Agent", | 81 | .name = "Boot Agent", |
| 82 | .size = 0x7C000, | 82 | .size = 0x7C000, |
| @@ -99,7 +99,7 @@ static struct mtd_partition vstms_nand_part[] = { | |||
| 99 | }, | 99 | }, |
| 100 | }; | 100 | }; |
| 101 | 101 | ||
| 102 | static struct s3c2410_nand_set vstms_nand_sets[] = { | 102 | static struct s3c2410_nand_set __initdata vstms_nand_sets[] = { |
| 103 | [0] = { | 103 | [0] = { |
| 104 | .name = "NAND", | 104 | .name = "NAND", |
| 105 | .nr_chips = 1, | 105 | .nr_chips = 1, |
| @@ -112,7 +112,7 @@ static struct s3c2410_nand_set vstms_nand_sets[] = { | |||
| 112 | * chips and beyond. | 112 | * chips and beyond. |
| 113 | */ | 113 | */ |
| 114 | 114 | ||
| 115 | static struct s3c2410_platform_nand vstms_nand_info = { | 115 | static struct s3c2410_platform_nand __initdata vstms_nand_info = { |
| 116 | .tacls = 20, | 116 | .tacls = 20, |
| 117 | .twrph0 = 60, | 117 | .twrph0 = 60, |
| 118 | .twrph1 = 20, | 118 | .twrph1 = 20, |
| @@ -143,8 +143,6 @@ static void __init vstms_fixup(struct machine_desc *desc, | |||
| 143 | 143 | ||
| 144 | static void __init vstms_map_io(void) | 144 | static void __init vstms_map_io(void) |
| 145 | { | 145 | { |
| 146 | s3c_device_nand.dev.platform_data = &vstms_nand_info; | ||
| 147 | |||
| 148 | s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); | 146 | s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc)); |
| 149 | s3c24xx_init_clocks(12000000); | 147 | s3c24xx_init_clocks(12000000); |
| 150 | s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); | 148 | s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs)); |
| @@ -153,6 +151,8 @@ static void __init vstms_map_io(void) | |||
| 153 | static void __init vstms_init(void) | 151 | static void __init vstms_init(void) |
| 154 | { | 152 | { |
| 155 | s3c_i2c0_set_platdata(NULL); | 153 | s3c_i2c0_set_platdata(NULL); |
| 154 | s3c_nand_set_platdata(&vstms_nand_info); | ||
| 155 | |||
| 156 | platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); | 156 | platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); |
| 157 | } | 157 | } |
| 158 | 158 | ||
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index a8b69d77571b..cf10e14b7b49 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig | |||
| @@ -53,6 +53,19 @@ config MACH_OSIRIS | |||
| 53 | Say Y here if you are using the Simtec IM2440D20 module, also | 53 | Say Y here if you are using the Simtec IM2440D20 module, also |
| 54 | known as the Osiris. | 54 | known as the Osiris. |
| 55 | 55 | ||
| 56 | config MACH_OSIRIS_DVS | ||
| 57 | tristate "Simtec IM2440D20 (OSIRIS) Dynamic Voltage Scaling driver" | ||
| 58 | depends on MACH_OSIRIS | ||
| 59 | select TPS65010 | ||
| 60 | help | ||
| 61 | Say Y/M here if you want to have dynamic voltage scaling support | ||
| 62 | on the Simtec IM2440D20 (OSIRIS) module via the TPS65011. | ||
| 63 | |||
| 64 | The DVS driver alters the voltage supplied to the ARM core | ||
| 65 | depending on the frequency it is running at. The driver itself | ||
| 66 | does not do any of the frequency alteration, which is left up | ||
| 67 | to the cpufreq driver. | ||
| 68 | |||
| 56 | config MACH_RX3715 | 69 | config MACH_RX3715 |
| 57 | bool "HP iPAQ rx3715" | 70 | bool "HP iPAQ rx3715" |
| 58 | select CPU_S3C2440 | 71 | select CPU_S3C2440 |
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index bfadcf684a2a..5f3224531885 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile | |||
| @@ -23,3 +23,7 @@ obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o | |||
| 23 | obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o | 23 | obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o |
| 24 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o | 24 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o |
| 25 | obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o | 25 | obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o |
| 26 | |||
| 27 | # extra machine support | ||
| 28 | |||
| 29 | obj-$(CONFIG_MACH_OSIRIS_DVS) += mach-osiris-dvs.o | ||
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c index 63c5ab65727f..0c049b95c378 100644 --- a/arch/arm/mach-s3c2440/irq.c +++ b/arch/arm/mach-s3c2440/irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/irq.c | 1 | /* linux/arch/arm/mach-s3c2440/irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 68f3870991bf..62a4c3eba97f 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-anubis.c | 1 | /* linux/arch/arm/mach-s3c2440/mach-anubis.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003-2005,2008 Simtec Electronics | 3 | * Copyright 2003-2009 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
| @@ -53,8 +53,9 @@ | |||
| 53 | #include <plat/clock.h> | 53 | #include <plat/clock.h> |
| 54 | #include <plat/devs.h> | 54 | #include <plat/devs.h> |
| 55 | #include <plat/cpu.h> | 55 | #include <plat/cpu.h> |
| 56 | #include <plat/audio-simtec.h> | ||
| 56 | 57 | ||
| 57 | #define COPYRIGHT ", (c) 2005 Simtec Electronics" | 58 | #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics" |
| 58 | 59 | ||
| 59 | static struct map_desc anubis_iodesc[] __initdata = { | 60 | static struct map_desc anubis_iodesc[] __initdata = { |
| 60 | /* ISA IO areas */ | 61 | /* ISA IO areas */ |
| @@ -138,7 +139,7 @@ static int external_map[] = { 2 }; | |||
| 138 | static int chip0_map[] = { 0 }; | 139 | static int chip0_map[] = { 0 }; |
| 139 | static int chip1_map[] = { 1 }; | 140 | static int chip1_map[] = { 1 }; |
| 140 | 141 | ||
| 141 | static struct mtd_partition anubis_default_nand_part[] = { | 142 | static struct mtd_partition __initdata anubis_default_nand_part[] = { |
| 142 | [0] = { | 143 | [0] = { |
| 143 | .name = "Boot Agent", | 144 | .name = "Boot Agent", |
| 144 | .size = SZ_16K, | 145 | .size = SZ_16K, |
| @@ -161,7 +162,7 @@ static struct mtd_partition anubis_default_nand_part[] = { | |||
| 161 | } | 162 | } |
| 162 | }; | 163 | }; |
| 163 | 164 | ||
| 164 | static struct mtd_partition anubis_default_nand_part_large[] = { | 165 | static struct mtd_partition __initdata anubis_default_nand_part_large[] = { |
| 165 | [0] = { | 166 | [0] = { |
| 166 | .name = "Boot Agent", | 167 | .name = "Boot Agent", |
| 167 | .size = SZ_128K, | 168 | .size = SZ_128K, |
| @@ -191,7 +192,7 @@ static struct mtd_partition anubis_default_nand_part_large[] = { | |||
| 191 | * socket. | 192 | * socket. |
| 192 | */ | 193 | */ |
| 193 | 194 | ||
| 194 | static struct s3c2410_nand_set anubis_nand_sets[] = { | 195 | static struct s3c2410_nand_set __initdata anubis_nand_sets[] = { |
| 195 | [1] = { | 196 | [1] = { |
| 196 | .name = "External", | 197 | .name = "External", |
| 197 | .nr_chips = 1, | 198 | .nr_chips = 1, |
| @@ -233,7 +234,7 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) | |||
| 233 | __raw_writeb(tmp, ANUBIS_VA_CTRL1); | 234 | __raw_writeb(tmp, ANUBIS_VA_CTRL1); |
| 234 | } | 235 | } |
| 235 | 236 | ||
| 236 | static struct s3c2410_platform_nand anubis_nand_info = { | 237 | static struct s3c2410_platform_nand __initdata anubis_nand_info = { |
| 237 | .tacls = 25, | 238 | .tacls = 25, |
| 238 | .twrph0 = 55, | 239 | .twrph0 = 55, |
| 239 | .twrph1 = 40, | 240 | .twrph1 = 40, |
| @@ -437,6 +438,17 @@ static struct i2c_board_info anubis_i2c_devs[] __initdata = { | |||
| 437 | } | 438 | } |
| 438 | }; | 439 | }; |
| 439 | 440 | ||
| 441 | /* Audio setup */ | ||
| 442 | static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = { | ||
| 443 | .have_mic = 1, | ||
| 444 | .have_lout = 1, | ||
| 445 | .output_cdclk = 1, | ||
| 446 | .use_mpllin = 1, | ||
| 447 | .amp_gpio = S3C2410_GPB(2), | ||
| 448 | .amp_gain[0] = S3C2410_GPD(10), | ||
| 449 | .amp_gain[1] = S3C2410_GPD(11), | ||
| 450 | }; | ||
| 451 | |||
| 440 | static void __init anubis_map_io(void) | 452 | static void __init anubis_map_io(void) |
| 441 | { | 453 | { |
| 442 | /* initialise the clocks */ | 454 | /* initialise the clocks */ |
| @@ -454,8 +466,6 @@ static void __init anubis_map_io(void) | |||
| 454 | 466 | ||
| 455 | s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks)); | 467 | s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks)); |
| 456 | 468 | ||
| 457 | s3c_device_nand.dev.platform_data = &anubis_nand_info; | ||
| 458 | |||
| 459 | s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); | 469 | s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc)); |
| 460 | s3c24xx_init_clocks(0); | 470 | s3c24xx_init_clocks(0); |
| 461 | s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); | 471 | s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs)); |
| @@ -476,6 +486,9 @@ static void __init anubis_map_io(void) | |||
| 476 | static void __init anubis_init(void) | 486 | static void __init anubis_init(void) |
| 477 | { | 487 | { |
| 478 | s3c_i2c0_set_platdata(NULL); | 488 | s3c_i2c0_set_platdata(NULL); |
| 489 | s3c_nand_set_platdata(&anubis_nand_info); | ||
| 490 | simtec_audio_add(NULL, false, &anubis_audio); | ||
| 491 | |||
| 479 | platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); | 492 | platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); |
| 480 | 493 | ||
| 481 | i2c_register_board_info(0, anubis_i2c_devs, | 494 | i2c_register_board_info(0, anubis_i2c_devs, |
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index dfc7010935da..aa69290e04c6 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c | |||
| @@ -96,7 +96,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { | |||
| 96 | 96 | ||
| 97 | /* NAND Flash on AT2440EVB board */ | 97 | /* NAND Flash on AT2440EVB board */ |
| 98 | 98 | ||
| 99 | static struct mtd_partition at2440evb_default_nand_part[] = { | 99 | static struct mtd_partition __initdata at2440evb_default_nand_part[] = { |
| 100 | [0] = { | 100 | [0] = { |
| 101 | .name = "Boot Agent", | 101 | .name = "Boot Agent", |
| 102 | .size = SZ_256K, | 102 | .size = SZ_256K, |
| @@ -114,7 +114,7 @@ static struct mtd_partition at2440evb_default_nand_part[] = { | |||
| 114 | }, | 114 | }, |
| 115 | }; | 115 | }; |
| 116 | 116 | ||
| 117 | static struct s3c2410_nand_set at2440evb_nand_sets[] = { | 117 | static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = { |
| 118 | [0] = { | 118 | [0] = { |
| 119 | .name = "nand", | 119 | .name = "nand", |
| 120 | .nr_chips = 1, | 120 | .nr_chips = 1, |
| @@ -123,7 +123,7 @@ static struct s3c2410_nand_set at2440evb_nand_sets[] = { | |||
| 123 | }, | 123 | }, |
| 124 | }; | 124 | }; |
| 125 | 125 | ||
| 126 | static struct s3c2410_platform_nand at2440evb_nand_info = { | 126 | static struct s3c2410_platform_nand __initdata at2440evb_nand_info = { |
| 127 | .tacls = 25, | 127 | .tacls = 25, |
| 128 | .twrph0 = 55, | 128 | .twrph0 = 55, |
| 129 | .twrph1 = 40, | 129 | .twrph1 = 40, |
| @@ -216,8 +216,6 @@ static struct platform_device *at2440evb_devices[] __initdata = { | |||
| 216 | 216 | ||
| 217 | static void __init at2440evb_map_io(void) | 217 | static void __init at2440evb_map_io(void) |
| 218 | { | 218 | { |
| 219 | s3c_device_nand.dev.platform_data = &at2440evb_nand_info; | ||
| 220 | s3c_device_sdi.name = "s3c2440-sdi"; | ||
| 221 | s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; | 219 | s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; |
| 222 | 220 | ||
| 223 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); | 221 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); |
| @@ -228,6 +226,7 @@ static void __init at2440evb_map_io(void) | |||
| 228 | static void __init at2440evb_init(void) | 226 | static void __init at2440evb_init(void) |
| 229 | { | 227 | { |
| 230 | s3c24xx_fb_set_platdata(&at2440evb_fb_info); | 228 | s3c24xx_fb_set_platdata(&at2440evb_fb_info); |
| 229 | s3c_nand_set_platdata(&at2440evb_nand_info); | ||
| 231 | s3c_i2c0_set_platdata(NULL); | 230 | s3c_i2c0_set_platdata(NULL); |
| 232 | 231 | ||
| 233 | platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); | 232 | platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); |
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c index 1c3382fefdd2..547d4fc99131 100644 --- a/arch/arm/mach-s3c2440/mach-mini2440.c +++ b/arch/arm/mach-s3c2440/mach-mini2440.c | |||
| @@ -532,7 +532,6 @@ static void __init mini2440_map_io(void) | |||
| 532 | s3c24xx_init_clocks(12000000); | 532 | s3c24xx_init_clocks(12000000); |
| 533 | s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); | 533 | s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs)); |
| 534 | 534 | ||
| 535 | s3c_device_nand.dev.platform_data = &mini2440_nand_info; | ||
| 536 | s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; | 535 | s3c_device_sdi.dev.platform_data = &mini2440_mmc_cfg; |
| 537 | } | 536 | } |
| 538 | 537 | ||
| @@ -677,8 +676,11 @@ static void __init mini2440_init(void) | |||
| 677 | printk("\n"); | 676 | printk("\n"); |
| 678 | s3c24xx_fb_set_platdata(&mini2440_fb_info); | 677 | s3c24xx_fb_set_platdata(&mini2440_fb_info); |
| 679 | } | 678 | } |
| 679 | |||
| 680 | s3c24xx_udc_set_platdata(&mini2440_udc_cfg); | 680 | s3c24xx_udc_set_platdata(&mini2440_udc_cfg); |
| 681 | s3c_nand_set_platdata(&mini2440_nand_info); | ||
| 681 | s3c_i2c0_set_platdata(NULL); | 682 | s3c_i2c0_set_platdata(NULL); |
| 683 | |||
| 682 | i2c_register_board_info(0, mini2440_i2c_devs, | 684 | i2c_register_board_info(0, mini2440_i2c_devs, |
| 683 | ARRAY_SIZE(mini2440_i2c_devs)); | 685 | ARRAY_SIZE(mini2440_i2c_devs)); |
| 684 | 686 | ||
diff --git a/arch/arm/mach-s3c2440/mach-osiris-dvs.c b/arch/arm/mach-s3c2440/mach-osiris-dvs.c new file mode 100644 index 000000000000..ad2792dfbee1 --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-osiris-dvs.c | |||
| @@ -0,0 +1,194 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-osiris-dvs.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Simtec Osiris Dynamic Voltage Scaling support. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/cpufreq.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | |||
| 20 | #include <linux/i2c/tps65010.h> | ||
| 21 | |||
| 22 | #include <plat/cpu-freq.h> | ||
| 23 | |||
| 24 | #define OSIRIS_GPIO_DVS S3C2410_GPB(5) | ||
| 25 | |||
| 26 | static bool dvs_en; | ||
| 27 | |||
| 28 | static void osiris_dvs_tps_setdvs(bool on) | ||
| 29 | { | ||
| 30 | unsigned vregs1 = 0, vdcdc2 = 0; | ||
| 31 | |||
| 32 | if (!on) { | ||
| 33 | vdcdc2 = TPS_VCORE_DISCH | TPS_LP_COREOFF; | ||
| 34 | vregs1 = TPS_LDO1_OFF; /* turn off in low-power mode */ | ||
| 35 | } | ||
| 36 | |||
| 37 | dvs_en = on; | ||
| 38 | vdcdc2 |= TPS_VCORE_1_3V | TPS_VCORE_LP_1_0V; | ||
| 39 | vregs1 |= TPS_LDO2_ENABLE | TPS_LDO1_ENABLE; | ||
| 40 | |||
| 41 | tps65010_config_vregs1(vregs1); | ||
| 42 | tps65010_config_vdcdc2(vdcdc2); | ||
| 43 | } | ||
| 44 | |||
| 45 | static bool is_dvs(struct s3c_freq *f) | ||
| 46 | { | ||
| 47 | /* at the moment, we assume ARMCLK = HCLK => DVS */ | ||
| 48 | return f->armclk == f->hclk; | ||
| 49 | } | ||
| 50 | |||
| 51 | /* keep track of current state */ | ||
| 52 | static bool cur_dvs = false; | ||
| 53 | |||
| 54 | static int osiris_dvs_notify(struct notifier_block *nb, | ||
| 55 | unsigned long val, void *data) | ||
| 56 | { | ||
| 57 | struct cpufreq_freqs *cf = data; | ||
| 58 | struct s3c_cpufreq_freqs *freqs = to_s3c_cpufreq(cf); | ||
| 59 | bool old_dvs = is_dvs(&freqs->old); | ||
| 60 | bool new_dvs = is_dvs(&freqs->new); | ||
| 61 | int ret = 0; | ||
| 62 | |||
| 63 | if (!dvs_en) | ||
| 64 | return 0; | ||
| 65 | |||
| 66 | printk(KERN_DEBUG "%s: old %ld,%ld new %ld,%ld\n", __func__, | ||
| 67 | freqs->old.armclk, freqs->old.hclk, | ||
| 68 | freqs->new.armclk, freqs->new.hclk); | ||
| 69 | |||
| 70 | switch (val) { | ||
| 71 | case CPUFREQ_PRECHANGE: | ||
| 72 | if (old_dvs & !new_dvs || | ||
| 73 | cur_dvs & !new_dvs) { | ||
| 74 | pr_debug("%s: exiting dvs\n", __func__); | ||
| 75 | cur_dvs = false; | ||
| 76 | gpio_set_value(OSIRIS_GPIO_DVS, 1); | ||
| 77 | } | ||
| 78 | break; | ||
| 79 | case CPUFREQ_POSTCHANGE: | ||
| 80 | if (!old_dvs & new_dvs || | ||
| 81 | !cur_dvs & new_dvs) { | ||
| 82 | pr_debug("entering dvs\n"); | ||
| 83 | cur_dvs = true; | ||
| 84 | gpio_set_value(OSIRIS_GPIO_DVS, 0); | ||
| 85 | } | ||
| 86 | break; | ||
| 87 | } | ||
| 88 | |||
| 89 | return ret; | ||
| 90 | } | ||
| 91 | |||
| 92 | static struct notifier_block osiris_dvs_nb = { | ||
| 93 | .notifier_call = osiris_dvs_notify, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static int __devinit osiris_dvs_probe(struct platform_device *pdev) | ||
| 97 | { | ||
| 98 | int ret; | ||
| 99 | |||
| 100 | dev_info(&pdev->dev, "initialising\n"); | ||
| 101 | |||
| 102 | ret = gpio_request(OSIRIS_GPIO_DVS, "osiris-dvs"); | ||
| 103 | if (ret) { | ||
| 104 | dev_err(&pdev->dev, "cannot claim gpio\n"); | ||
| 105 | goto err_nogpio; | ||
| 106 | } | ||
| 107 | |||
| 108 | /* start with dvs disabled */ | ||
| 109 | gpio_direction_output(OSIRIS_GPIO_DVS, 1); | ||
| 110 | |||
| 111 | ret = cpufreq_register_notifier(&osiris_dvs_nb, | ||
| 112 | CPUFREQ_TRANSITION_NOTIFIER); | ||
| 113 | if (ret) { | ||
| 114 | dev_err(&pdev->dev, "failed to register with cpufreq\n"); | ||
| 115 | goto err_nofreq; | ||
| 116 | } | ||
| 117 | |||
| 118 | osiris_dvs_tps_setdvs(true); | ||
| 119 | |||
| 120 | return 0; | ||
| 121 | |||
| 122 | err_nofreq: | ||
| 123 | gpio_free(OSIRIS_GPIO_DVS); | ||
| 124 | |||
| 125 | err_nogpio: | ||
| 126 | return ret; | ||
| 127 | } | ||
| 128 | |||
| 129 | static int __devexit osiris_dvs_remove(struct platform_device *pdev) | ||
| 130 | { | ||
| 131 | dev_info(&pdev->dev, "exiting\n"); | ||
| 132 | |||
| 133 | /* disable any current dvs */ | ||
| 134 | gpio_set_value(OSIRIS_GPIO_DVS, 1); | ||
| 135 | osiris_dvs_tps_setdvs(false); | ||
| 136 | |||
| 137 | cpufreq_unregister_notifier(&osiris_dvs_nb, | ||
| 138 | CPUFREQ_TRANSITION_NOTIFIER); | ||
| 139 | |||
| 140 | gpio_free(OSIRIS_GPIO_DVS); | ||
| 141 | |||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | /* the CONFIG_PM block is so small, it isn't worth actaully compiling it | ||
| 146 | * out if the configuration isn't set. */ | ||
| 147 | |||
| 148 | static int osiris_dvs_suspend(struct device *dev) | ||
| 149 | { | ||
| 150 | gpio_set_value(OSIRIS_GPIO_DVS, 1); | ||
| 151 | osiris_dvs_tps_setdvs(false); | ||
| 152 | cur_dvs = false; | ||
| 153 | |||
| 154 | return 0; | ||
| 155 | } | ||
| 156 | |||
| 157 | static int osiris_dvs_resume(struct device *dev) | ||
| 158 | { | ||
| 159 | osiris_dvs_tps_setdvs(true); | ||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | static const struct dev_pm_ops osiris_dvs_pm = { | ||
| 164 | .suspend = osiris_dvs_suspend, | ||
| 165 | .resume = osiris_dvs_resume, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct platform_driver osiris_dvs_driver = { | ||
| 169 | .probe = osiris_dvs_probe, | ||
| 170 | .remove = __devexit_p(osiris_dvs_remove), | ||
| 171 | .driver = { | ||
| 172 | .name = "osiris-dvs", | ||
| 173 | .owner = THIS_MODULE, | ||
| 174 | .pm = &osiris_dvs_pm, | ||
| 175 | }, | ||
| 176 | }; | ||
| 177 | |||
| 178 | static int __init osiris_dvs_init(void) | ||
| 179 | { | ||
| 180 | return platform_driver_register(&osiris_dvs_driver); | ||
| 181 | } | ||
| 182 | |||
| 183 | static void __exit osiris_dvs_exit(void) | ||
| 184 | { | ||
| 185 | platform_driver_unregister(&osiris_dvs_driver); | ||
| 186 | } | ||
| 187 | |||
| 188 | module_init(osiris_dvs_init); | ||
| 189 | module_exit(osiris_dvs_exit); | ||
| 190 | |||
| 191 | MODULE_DESCRIPTION("Simtec OSIRIS DVS support"); | ||
| 192 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | ||
| 193 | MODULE_LICENSE("GPL"); | ||
| 194 | MODULE_ALIAS("platform:osiris-dvs"); | ||
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 2105a41281a4..015dfb2a80da 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-osiris.c | 1 | /* linux/arch/arm/mach-s3c2440/mach-osiris.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2005,2008 Simtec Electronics | 3 | * Copyright (c) 2005-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
| @@ -23,6 +23,8 @@ | |||
| 23 | #include <linux/i2c.h> | 23 | #include <linux/i2c.h> |
| 24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 25 | 25 | ||
| 26 | #include <linux/i2c/tps65010.h> | ||
| 27 | |||
| 26 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 28 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
| @@ -148,7 +150,7 @@ static int external_map[] = { 2 }; | |||
| 148 | static int chip0_map[] = { 0 }; | 150 | static int chip0_map[] = { 0 }; |
| 149 | static int chip1_map[] = { 1 }; | 151 | static int chip1_map[] = { 1 }; |
| 150 | 152 | ||
| 151 | static struct mtd_partition osiris_default_nand_part[] = { | 153 | static struct mtd_partition __initdata osiris_default_nand_part[] = { |
| 152 | [0] = { | 154 | [0] = { |
| 153 | .name = "Boot Agent", | 155 | .name = "Boot Agent", |
| 154 | .size = SZ_16K, | 156 | .size = SZ_16K, |
| @@ -171,7 +173,7 @@ static struct mtd_partition osiris_default_nand_part[] = { | |||
| 171 | } | 173 | } |
| 172 | }; | 174 | }; |
| 173 | 175 | ||
| 174 | static struct mtd_partition osiris_default_nand_part_large[] = { | 176 | static struct mtd_partition __initdata osiris_default_nand_part_large[] = { |
| 175 | [0] = { | 177 | [0] = { |
| 176 | .name = "Boot Agent", | 178 | .name = "Boot Agent", |
| 177 | .size = SZ_128K, | 179 | .size = SZ_128K, |
| @@ -201,7 +203,7 @@ static struct mtd_partition osiris_default_nand_part_large[] = { | |||
| 201 | * socket. | 203 | * socket. |
| 202 | */ | 204 | */ |
| 203 | 205 | ||
| 204 | static struct s3c2410_nand_set osiris_nand_sets[] = { | 206 | static struct s3c2410_nand_set __initdata osiris_nand_sets[] = { |
| 205 | [1] = { | 207 | [1] = { |
| 206 | .name = "External", | 208 | .name = "External", |
| 207 | .nr_chips = 1, | 209 | .nr_chips = 1, |
| @@ -243,7 +245,7 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) | |||
| 243 | __raw_writeb(tmp, OSIRIS_VA_CTRL0); | 245 | __raw_writeb(tmp, OSIRIS_VA_CTRL0); |
| 244 | } | 246 | } |
| 245 | 247 | ||
| 246 | static struct s3c2410_platform_nand osiris_nand_info = { | 248 | static struct s3c2410_platform_nand __initdata osiris_nand_info = { |
| 247 | .tacls = 25, | 249 | .tacls = 25, |
| 248 | .twrph0 = 60, | 250 | .twrph0 = 60, |
| 249 | .twrph1 = 60, | 251 | .twrph1 = 60, |
| @@ -326,12 +328,44 @@ static struct sys_device osiris_pm_sysdev = { | |||
| 326 | .cls = &osiris_pm_sysclass, | 328 | .cls = &osiris_pm_sysclass, |
| 327 | }; | 329 | }; |
| 328 | 330 | ||
| 331 | /* Link for DVS driver to TPS65011 */ | ||
| 332 | |||
| 333 | static void osiris_tps_release(struct device *dev) | ||
| 334 | { | ||
| 335 | /* static device, do not need to release anything */ | ||
| 336 | } | ||
| 337 | |||
| 338 | static struct platform_device osiris_tps_device = { | ||
| 339 | .name = "osiris-dvs", | ||
| 340 | .id = -1, | ||
| 341 | .dev.release = osiris_tps_release, | ||
| 342 | }; | ||
| 343 | |||
| 344 | static int osiris_tps_setup(struct i2c_client *client, void *context) | ||
| 345 | { | ||
| 346 | osiris_tps_device.dev.parent = &client->dev; | ||
| 347 | return platform_device_register(&osiris_tps_device); | ||
| 348 | } | ||
| 349 | |||
| 350 | static int osiris_tps_remove(struct i2c_client *client, void *context) | ||
| 351 | { | ||
| 352 | platform_device_unregister(&osiris_tps_device); | ||
| 353 | return 0; | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct tps65010_board osiris_tps_board = { | ||
| 357 | .base = -1, /* GPIO can go anywhere at the moment */ | ||
| 358 | .setup = osiris_tps_setup, | ||
| 359 | .teardown = osiris_tps_remove, | ||
| 360 | }; | ||
| 361 | |||
| 329 | /* I2C devices fitted. */ | 362 | /* I2C devices fitted. */ |
| 330 | 363 | ||
| 331 | static struct i2c_board_info osiris_i2c_devs[] __initdata = { | 364 | static struct i2c_board_info osiris_i2c_devs[] __initdata = { |
| 332 | { | 365 | { |
| 333 | I2C_BOARD_INFO("tps65011", 0x48), | 366 | I2C_BOARD_INFO("tps65011", 0x48), |
| 334 | .irq = IRQ_EINT20, | 367 | .irq = IRQ_EINT20, |
| 368 | .platform_data = &osiris_tps_board, | ||
| 335 | }, | 369 | }, |
| 336 | }; | 370 | }; |
| 337 | 371 | ||
| @@ -377,8 +411,6 @@ static void __init osiris_map_io(void) | |||
| 377 | 411 | ||
| 378 | s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks)); | 412 | s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks)); |
| 379 | 413 | ||
| 380 | s3c_device_nand.dev.platform_data = &osiris_nand_info; | ||
| 381 | |||
| 382 | s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); | 414 | s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc)); |
| 383 | s3c24xx_init_clocks(0); | 415 | s3c24xx_init_clocks(0); |
| 384 | s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); | 416 | s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs)); |
| @@ -408,6 +440,7 @@ static void __init osiris_init(void) | |||
| 408 | sysdev_register(&osiris_pm_sysdev); | 440 | sysdev_register(&osiris_pm_sysdev); |
| 409 | 441 | ||
| 410 | s3c_i2c0_set_platdata(NULL); | 442 | s3c_i2c0_set_platdata(NULL); |
| 443 | s3c_nand_set_platdata(&osiris_nand_info); | ||
| 411 | 444 | ||
| 412 | s3c_cpufreq_setboard(&osiris_cpufreq); | 445 | s3c_cpufreq_setboard(&osiris_cpufreq); |
| 413 | 446 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index bc8d8d1ebd1a..a952a13afb1f 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-rx3715.c | 1 | /* linux/arch/arm/mach-s3c2440/mach-rx3715.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://www.handhelds.org/projects/rx3715.html | 6 | * http://www.handhelds.org/projects/rx3715.html |
| @@ -149,7 +149,7 @@ static struct s3c2410fb_mach_info rx3715_fb_info __initdata = { | |||
| 149 | .gpdup_mask = 0xffffffff, | 149 | .gpdup_mask = 0xffffffff, |
| 150 | }; | 150 | }; |
| 151 | 151 | ||
| 152 | static struct mtd_partition rx3715_nand_part[] = { | 152 | static struct mtd_partition __initdata rx3715_nand_part[] = { |
| 153 | [0] = { | 153 | [0] = { |
| 154 | .name = "Whole Flash", | 154 | .name = "Whole Flash", |
| 155 | .offset = 0, | 155 | .offset = 0, |
| @@ -158,7 +158,7 @@ static struct mtd_partition rx3715_nand_part[] = { | |||
| 158 | } | 158 | } |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | static struct s3c2410_nand_set rx3715_nand_sets[] = { | 161 | static struct s3c2410_nand_set __initdata rx3715_nand_sets[] = { |
| 162 | [0] = { | 162 | [0] = { |
| 163 | .name = "Internal", | 163 | .name = "Internal", |
| 164 | .nr_chips = 1, | 164 | .nr_chips = 1, |
| @@ -167,7 +167,7 @@ static struct s3c2410_nand_set rx3715_nand_sets[] = { | |||
| 167 | }, | 167 | }, |
| 168 | }; | 168 | }; |
| 169 | 169 | ||
| 170 | static struct s3c2410_platform_nand rx3715_nand_info = { | 170 | static struct s3c2410_platform_nand __initdata rx3715_nand_info = { |
| 171 | .tacls = 25, | 171 | .tacls = 25, |
| 172 | .twrph0 = 50, | 172 | .twrph0 = 50, |
| 173 | .twrph1 = 15, | 173 | .twrph1 = 15, |
| @@ -186,8 +186,6 @@ static struct platform_device *rx3715_devices[] __initdata = { | |||
| 186 | 186 | ||
| 187 | static void __init rx3715_map_io(void) | 187 | static void __init rx3715_map_io(void) |
| 188 | { | 188 | { |
| 189 | s3c_device_nand.dev.platform_data = &rx3715_nand_info; | ||
| 190 | |||
| 191 | s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); | 189 | s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); |
| 192 | s3c24xx_init_clocks(16934000); | 190 | s3c24xx_init_clocks(16934000); |
| 193 | s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); | 191 | s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); |
| @@ -205,6 +203,7 @@ static void __init rx3715_init_machine(void) | |||
| 205 | #endif | 203 | #endif |
| 206 | s3c_pm_init(); | 204 | s3c_pm_init(); |
| 207 | 205 | ||
| 206 | s3c_nand_set_platdata(&rx3715_nand_info); | ||
| 208 | s3c24xx_fb_set_platdata(&rx3715_fb_info); | 207 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
| 209 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); | 208 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
| 210 | } | 209 | } |
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index db6eafbd4d90..ec13e748ccc5 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c2440/mach-smdk2440.c | 1 | /* linux/arch/arm/mach-s3c2440/mach-smdk2440.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2005 Simtec Electronics | 3 | * Copyright (c) 2004-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://www.fluff.org/ben/smdk2440/ | 6 | * http://www.fluff.org/ben/smdk2440/ |
diff --git a/arch/arm/mach-s3c2442/mach-gta02.c b/arch/arm/mach-s3c2442/mach-gta02.c index 0fb385bd9cd9..f76d6ff4aeb9 100644 --- a/arch/arm/mach-s3c2442/mach-gta02.c +++ b/arch/arm/mach-s3c2442/mach-gta02.c | |||
| @@ -423,7 +423,7 @@ static struct i2c_board_info gta02_i2c_devs[] __initdata = { | |||
| 423 | }, | 423 | }, |
| 424 | }; | 424 | }; |
| 425 | 425 | ||
| 426 | static struct s3c2410_nand_set gta02_nand_sets[] = { | 426 | static struct s3c2410_nand_set __initdata gta02_nand_sets[] = { |
| 427 | [0] = { | 427 | [0] = { |
| 428 | /* | 428 | /* |
| 429 | * This name is also hard-coded in the boot loaders, so | 429 | * This name is also hard-coded in the boot loaders, so |
| @@ -442,7 +442,7 @@ static struct s3c2410_nand_set gta02_nand_sets[] = { | |||
| 442 | * data sheet (K5D2G13ACM-D075 MCP Memory). | 442 | * data sheet (K5D2G13ACM-D075 MCP Memory). |
| 443 | */ | 443 | */ |
| 444 | 444 | ||
| 445 | static struct s3c2410_platform_nand gta02_nand_info = { | 445 | static struct s3c2410_platform_nand __initdata gta02_nand_info = { |
| 446 | .tacls = 0, | 446 | .tacls = 0, |
| 447 | .twrph0 = 25, | 447 | .twrph0 = 25, |
| 448 | .twrph1 = 15, | 448 | .twrph1 = 15, |
| @@ -621,9 +621,9 @@ static void __init gta02_machine_init(void) | |||
| 621 | #endif | 621 | #endif |
| 622 | 622 | ||
| 623 | s3c_device_usb.dev.platform_data = >a02_usb_info; | 623 | s3c_device_usb.dev.platform_data = >a02_usb_info; |
| 624 | s3c_device_nand.dev.platform_data = >a02_nand_info; | ||
| 625 | 624 | ||
| 626 | s3c24xx_udc_set_platdata(>a02_udc_cfg); | 625 | s3c24xx_udc_set_platdata(>a02_udc_cfg); |
| 626 | s3c_nand_set_platdata(>a02_nand_info); | ||
| 627 | s3c_i2c0_set_platdata(NULL); | 627 | s3c_i2c0_set_platdata(NULL); |
| 628 | 628 | ||
| 629 | i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); | 629 | i2c_register_board_info(0, gta02_i2c_devs, ARRAY_SIZE(gta02_i2c_devs)); |
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h index 79e4d93ea2b6..d88c8b24fe34 100644 --- a/arch/arm/mach-s3c24a0/include/mach/map.h +++ b/arch/arm/mach-s3c24a0/include/mach/map.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/map.h | 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/map.h |
| 2 | * | 2 | * |
| 3 | * Copyright 2003,2007 Simtec Electronics | 3 | * Copyright 2003-2007 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h index af2abd756c30..be0af518b488 100644 --- a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h | 1 | /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h index fc8b223bad4f..f3b48f841d84 100644 --- a/arch/arm/mach-s3c6400/include/mach/map.h +++ b/arch/arm/mach-s3c6400/include/mach/map.h | |||
| @@ -64,6 +64,9 @@ | |||
| 64 | 64 | ||
| 65 | #define S3C64XX_PA_USBHOST (0x74300000) | 65 | #define S3C64XX_PA_USBHOST (0x74300000) |
| 66 | 66 | ||
| 67 | #define S3C64XX_PA_USB_HSPHY (0x7C100000) | ||
| 68 | #define S3C64XX_VA_USB_HSPHY S3C_ADDR_CPU(0x00200000) | ||
| 69 | |||
| 67 | /* place VICs close together */ | 70 | /* place VICs close together */ |
| 68 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) | 71 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) |
| 69 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | 72 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) |
| @@ -79,5 +82,6 @@ | |||
| 79 | #define S3C_PA_FB S3C64XX_PA_FB | 82 | #define S3C_PA_FB S3C64XX_PA_FB |
| 80 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST | 83 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST |
| 81 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG | 84 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG |
| 85 | #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY | ||
| 82 | 86 | ||
| 83 | #endif /* __ASM_ARCH_6400_MAP_H */ | 87 | #endif /* __ASM_ARCH_6400_MAP_H */ |
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h index 47019795ce06..f56611526c63 100644 --- a/arch/arm/mach-s3c6400/include/mach/regs-fb.h +++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h | |||
| @@ -1,195 +1,30 @@ | |||
| 1 | /* arch/arm/mach-s3c6400/include/mach/regs-fb.h | 1 | /* |
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | 2 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2008 Simtec Electronics | 3 | * Copyright 2008 Simtec Electronics |
| 5 | * http://armlinux.simtec.co.uk/ | 4 | * Copyright 2009 Samsung Electronics Co. |
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C64XX - new-style framebuffer register definitions | ||
| 9 | * | 5 | * |
| 10 | * This is the register set for the new style framebuffer interface | 6 | * Pawel Osciak <p.osciak@samsung.com> |
| 11 | * found from the S3C2443 onwards and specifically the S3C64XX series | 7 | * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk> |
| 12 | * S3C6400 and S3C6410. | ||
| 13 | * | 8 | * |
| 14 | * The file contains the cpu specific items which change between whichever | 9 | * Framebuffer register definitions for Samsung S3C64xx. |
| 15 | * architecture is selected. See <plat/regs-fb.h> for the core definitions | ||
| 16 | * that are the same. | ||
| 17 | * | 10 | * |
| 18 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License version 2 as | 12 | * it under the terms of the GNU General Public License version 2 as |
| 20 | * published by the Free Software Foundation. | 13 | * published by the Free Software Foundation. |
| 21 | */ | 14 | */ |
| 22 | 15 | ||
| 23 | /* include the core definitions here, in case we really do need to | 16 | #ifndef __ASM_ARCH_MACH_REGS_FB_H |
| 24 | * override them at a later date. | 17 | #define __ASM_ARCH_MACH_REGS_FB_H __FILE__ |
| 25 | */ | ||
| 26 | |||
| 27 | #include <plat/regs-fb.h> | ||
| 28 | |||
| 29 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | ||
| 30 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
| 31 | |||
| 32 | /* Video timing controls */ | ||
| 33 | #define VIDTCON0 (0x10) | ||
| 34 | #define VIDTCON1 (0x14) | ||
| 35 | #define VIDTCON2 (0x18) | ||
| 36 | |||
| 37 | /* Window position controls */ | ||
| 38 | |||
| 39 | #define WINCON(_win) (0x20 + ((_win) * 4)) | ||
| 40 | |||
| 41 | /* OSD1 and OSD4 do not have register D */ | ||
| 42 | |||
| 43 | #define VIDOSD_A(_win) (0x40 + ((_win) * 16)) | ||
| 44 | #define VIDOSD_B(_win) (0x44 + ((_win) * 16)) | ||
| 45 | #define VIDOSD_C(_win) (0x48 + ((_win) * 16)) | ||
| 46 | #define VIDOSD_D(_win) (0x4C + ((_win) * 16)) | ||
| 47 | |||
| 48 | /* Video buffer addresses */ | ||
| 49 | |||
| 50 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | ||
| 51 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | ||
| 52 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | ||
| 53 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | ||
| 54 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | ||
| 55 | |||
| 56 | #define VIDINTCON0 (0x130) | ||
| 57 | |||
| 58 | #define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) | ||
| 59 | |||
| 60 | /* WINCONx */ | ||
| 61 | |||
| 62 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
| 63 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
| 64 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
| 65 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
| 66 | |||
| 67 | #define WINCONx_ENLOCAL (1 << 22) | ||
| 68 | #define WINCONx_BUFSTATUS (1 << 21) | ||
| 69 | #define WINCONx_BUFSEL (1 << 20) | ||
| 70 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
| 71 | #define WINCONx_YCbCr (1 << 13) | ||
| 72 | |||
| 73 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
| 74 | |||
| 75 | #define WINCON2_LOCALSEL_CAMIF (1 << 23) | ||
| 76 | #define WINCON2_BLD_PIX (1 << 6) | ||
| 77 | |||
| 78 | #define WINCON2_ALPHA_SEL (1 << 1) | ||
| 79 | #define WINCON2_BPPMODE_MASK (0xf << 2) | ||
| 80 | #define WINCON2_BPPMODE_SHIFT (2) | ||
| 81 | #define WINCON2_BPPMODE_1BPP (0x0 << 2) | ||
| 82 | #define WINCON2_BPPMODE_2BPP (0x1 << 2) | ||
| 83 | #define WINCON2_BPPMODE_4BPP (0x2 << 2) | ||
| 84 | #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) | ||
| 85 | #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 86 | #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 87 | #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 88 | #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 89 | #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 90 | #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 91 | #define WINCON2_BPPMODE_24BPP_888 (0xb << 2) | ||
| 92 | #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 93 | #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 94 | #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 95 | |||
| 96 | #define WINCON3_BLD_PIX (1 << 6) | ||
| 97 | |||
| 98 | #define WINCON3_ALPHA_SEL (1 << 1) | ||
| 99 | #define WINCON3_BPPMODE_MASK (0xf << 2) | ||
| 100 | #define WINCON3_BPPMODE_SHIFT (2) | ||
| 101 | #define WINCON3_BPPMODE_1BPP (0x0 << 2) | ||
| 102 | #define WINCON3_BPPMODE_2BPP (0x1 << 2) | ||
| 103 | #define WINCON3_BPPMODE_4BPP (0x2 << 2) | ||
| 104 | #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 105 | #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 106 | #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 107 | #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 108 | #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 109 | #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 110 | #define WINCON3_BPPMODE_24BPP_888 (0xb << 2) | ||
| 111 | #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 112 | #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 113 | #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 114 | |||
| 115 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
| 116 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
| 117 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
| 118 | |||
| 119 | #define DITHMODE (0x170) | ||
| 120 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | ||
| 121 | |||
| 122 | |||
| 123 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
| 124 | #define DITHMODE_R_POS_SHIFT (5) | ||
| 125 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
| 126 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
| 127 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
| 128 | |||
| 129 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
| 130 | #define DITHMODE_G_POS_SHIFT (3) | ||
| 131 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
| 132 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
| 133 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
| 134 | |||
| 135 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
| 136 | #define DITHMODE_B_POS_SHIFT (1) | ||
| 137 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
| 138 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
| 139 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
| 140 | 18 | ||
| 141 | #define DITHMODE_DITH_EN (1 << 0) | 19 | #include <plat/regs-fb-v4.h> |
| 142 | |||
| 143 | #define WPALCON (0x1A0) | ||
| 144 | |||
| 145 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
| 146 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
| 147 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
| 148 | 20 | ||
| 149 | /* Palette registers */ | 21 | /* Palette registers */ |
| 150 | |||
| 151 | #define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) | 22 | #define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) |
| 152 | #define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) | 23 | #define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) |
| 153 | #define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) | 24 | #define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) |
| 154 | #define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) | 25 | #define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) |
| 155 | #define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) | 26 | #define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) |
| 156 | 27 | ||
| 157 | /* system specific implementation code for palette sizes, and other | ||
| 158 | * information that changes depending on which architecture is being | ||
| 159 | * compiled. | ||
| 160 | */ | ||
| 161 | |||
| 162 | /* return true if window _win has OSD register D */ | ||
| 163 | #define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) | ||
| 164 | |||
| 165 | static inline unsigned int s3c_fb_win_pal_size(unsigned int win) | ||
| 166 | { | ||
| 167 | if (win < 2) | ||
| 168 | return 256; | ||
| 169 | if (win < 4) | ||
| 170 | return 16; | ||
| 171 | if (win == 4) | ||
| 172 | return 4; | ||
| 173 | |||
| 174 | BUG(); /* shouldn't get here */ | ||
| 175 | } | ||
| 176 | |||
| 177 | static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) | ||
| 178 | { | ||
| 179 | /* all windows can do 1/2 bpp */ | ||
| 180 | |||
| 181 | if ((bpp == 25 || bpp == 19) && win == 0) | ||
| 182 | return 0; /* win 0 does not have 19 or 25bpp modes */ | ||
| 183 | |||
| 184 | if (bpp == 4 && win == 4) | ||
| 185 | return 0; | ||
| 186 | |||
| 187 | if (bpp == 8 && (win >= 3)) | ||
| 188 | return 0; /* win 3/4 cannot do 8bpp in any mode */ | ||
| 189 | |||
| 190 | return 1; | ||
| 191 | } | ||
| 192 | |||
| 193 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | 28 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) |
| 194 | { | 29 | { |
| 195 | switch (window) { | 30 | switch (window) { |
| @@ -203,57 +38,4 @@ static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | |||
| 203 | BUG(); | 38 | BUG(); |
| 204 | } | 39 | } |
| 205 | 40 | ||
| 206 | static inline int s3c_fb_pal_is16(unsigned int window) | 41 | #endif /* __ASM_ARCH_MACH_REGS_FB_H */ |
| 207 | { | ||
| 208 | return window > 1; | ||
| 209 | } | ||
| 210 | |||
| 211 | struct s3c_fb_palette { | ||
| 212 | struct fb_bitfield r; | ||
| 213 | struct fb_bitfield g; | ||
| 214 | struct fb_bitfield b; | ||
| 215 | struct fb_bitfield a; | ||
| 216 | }; | ||
| 217 | |||
| 218 | static inline void s3c_fb_init_palette(unsigned int window, | ||
| 219 | struct s3c_fb_palette *palette) | ||
| 220 | { | ||
| 221 | if (window < 2) { | ||
| 222 | /* Windows 0/1 are 8/8/8 or A/8/8/8 */ | ||
| 223 | palette->r.offset = 16; | ||
| 224 | palette->r.length = 8; | ||
| 225 | palette->g.offset = 8; | ||
| 226 | palette->g.length = 8; | ||
| 227 | palette->b.offset = 0; | ||
| 228 | palette->b.length = 8; | ||
| 229 | } else { | ||
| 230 | /* currently we assume RGB 5/6/5 */ | ||
| 231 | palette->r.offset = 11; | ||
| 232 | palette->r.length = 5; | ||
| 233 | palette->g.offset = 5; | ||
| 234 | palette->g.length = 6; | ||
| 235 | palette->b.offset = 0; | ||
| 236 | palette->b.length = 5; | ||
| 237 | } | ||
| 238 | } | ||
| 239 | |||
| 240 | /* Notes on per-window bpp settings | ||
| 241 | * | ||
| 242 | * Value Win0 Win1 Win2 Win3 Win 4 | ||
| 243 | * 0000 1(P) 1(P) 1(P) 1(P) 1(P) | ||
| 244 | * 0001 2(P) 2(P) 2(P) 2(P) 2(P) | ||
| 245 | * 0010 4(P) 4(P) 4(P) 4(P) -none- | ||
| 246 | * 0011 8(P) 8(P) -none- -none- -none- | ||
| 247 | * 0100 -none- 8(A232) 8(A232) -none- -none- | ||
| 248 | * 0101 16(565) 16(565) 16(565) 16(565) 16(565) | ||
| 249 | * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) | ||
| 250 | * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) | ||
| 251 | * 1000 18(666) 18(666) 18(666) 18(666) 18(666) | ||
| 252 | * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) | ||
| 253 | * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) | ||
| 254 | * 1011 24(888) 24(888) 24(888) 24(888) 24(888) | ||
| 255 | * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) | ||
| 256 | * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) | ||
| 257 | * 1110 -none- -none- -none- -none- -none- | ||
| 258 | * 1111 -none- -none- -none- -none- -none- | ||
| 259 | */ | ||
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c index b42bdd0f2138..d876ee503671 100644 --- a/arch/arm/mach-s3c6400/s3c6400.c +++ b/arch/arm/mach-s3c6400/s3c6400.c | |||
| @@ -45,6 +45,7 @@ void __init s3c6400_map_io(void) | |||
| 45 | 45 | ||
| 46 | s3c6400_default_sdhci0(); | 46 | s3c6400_default_sdhci0(); |
| 47 | s3c6400_default_sdhci1(); | 47 | s3c6400_default_sdhci1(); |
| 48 | s3c6400_default_sdhci2(); | ||
| 48 | 49 | ||
| 49 | /* the i2c devices are directly compatible with s3c2440 */ | 50 | /* the i2c devices are directly compatible with s3c2440 */ |
| 50 | s3c_i2c0_setname("s3c2440-i2c"); | 51 | s3c_i2c0_setname("s3c2440-i2c"); |
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c index 9b67c663d9d8..522c08691952 100644 --- a/arch/arm/mach-s3c6410/cpu.c +++ b/arch/arm/mach-s3c6410/cpu.c | |||
| @@ -58,6 +58,7 @@ void __init s3c6410_map_io(void) | |||
| 58 | /* initialise device information early */ | 58 | /* initialise device information early */ |
| 59 | s3c6410_default_sdhci0(); | 59 | s3c6410_default_sdhci0(); |
| 60 | s3c6410_default_sdhci1(); | 60 | s3c6410_default_sdhci1(); |
| 61 | s3c6410_default_sdhci2(); | ||
| 61 | 62 | ||
| 62 | /* the i2c devices are directly compatible with s3c2440 */ | 63 | /* the i2c devices are directly compatible with s3c2440 */ |
| 63 | s3c_i2c0_setname("s3c2440-i2c"); | 64 | s3c_i2c0_setname("s3c2440-i2c"); |
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c index c5741056193f..cdd4b5378552 100644 --- a/arch/arm/mach-s3c6410/mach-hmt.c +++ b/arch/arm/mach-s3c6410/mach-hmt.c | |||
| @@ -250,7 +250,7 @@ static void __init hmt_machine_init(void) | |||
| 250 | { | 250 | { |
| 251 | s3c_i2c0_set_platdata(NULL); | 251 | s3c_i2c0_set_platdata(NULL); |
| 252 | s3c_fb_set_platdata(&hmt_lcd_pdata); | 252 | s3c_fb_set_platdata(&hmt_lcd_pdata); |
| 253 | s3c_device_nand.dev.platform_data = &hmt_nand_info; | 253 | s3c_nand_set_platdata(&hmt_nand_info); |
| 254 | 254 | ||
| 255 | gpio_request(S3C64XX_GPC(7), "usb power"); | 255 | gpio_request(S3C64XX_GPC(7), "usb power"); |
| 256 | gpio_direction_output(S3C64XX_GPC(7), 0); | 256 | gpio_direction_output(S3C64XX_GPC(7), 0); |
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c index 9f1a21462620..480d297c1de2 100644 --- a/arch/arm/mach-s3c6410/mach-smdk6410.c +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <linux/delay.h> | 26 | #include <linux/delay.h> |
| 27 | #include <linux/smsc911x.h> | 27 | #include <linux/smsc911x.h> |
| 28 | #include <linux/regulator/fixed.h> | ||
| 28 | 29 | ||
| 29 | #ifdef CONFIG_SMDK6410_WM1190_EV1 | 30 | #ifdef CONFIG_SMDK6410_WM1190_EV1 |
| 30 | #include <linux/mfd/wm8350/core.h> | 31 | #include <linux/mfd/wm8350/core.h> |
| @@ -184,6 +185,43 @@ static struct platform_device smdk6410_smsc911x = { | |||
| 184 | }, | 185 | }, |
| 185 | }; | 186 | }; |
| 186 | 187 | ||
| 188 | #ifdef CONFIG_REGULATOR | ||
| 189 | static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = { | ||
| 190 | { | ||
| 191 | /* WM8580 */ | ||
| 192 | .supply = "PVDD", | ||
| 193 | .dev_name = "0-001b", | ||
| 194 | }, | ||
| 195 | { | ||
| 196 | /* WM8580 */ | ||
| 197 | .supply = "AVDD", | ||
| 198 | .dev_name = "0-001b", | ||
| 199 | }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct regulator_init_data smdk6410_b_pwr_5v_data = { | ||
| 203 | .constraints = { | ||
| 204 | .always_on = 1, | ||
| 205 | }, | ||
| 206 | .num_consumer_supplies = ARRAY_SIZE(smdk6410_b_pwr_5v_consumers), | ||
| 207 | .consumer_supplies = smdk6410_b_pwr_5v_consumers, | ||
| 208 | }; | ||
| 209 | |||
| 210 | static struct fixed_voltage_config smdk6410_b_pwr_5v_pdata = { | ||
| 211 | .supply_name = "B_PWR_5V", | ||
| 212 | .microvolts = 5000000, | ||
| 213 | .init_data = &smdk6410_b_pwr_5v_data, | ||
| 214 | }; | ||
| 215 | |||
| 216 | static struct platform_device smdk6410_b_pwr_5v = { | ||
| 217 | .name = "reg-fixed-voltage", | ||
| 218 | .id = -1, | ||
| 219 | .dev = { | ||
| 220 | .platform_data = &smdk6410_b_pwr_5v_pdata, | ||
| 221 | }, | ||
| 222 | }; | ||
| 223 | #endif | ||
| 224 | |||
| 187 | static struct map_desc smdk6410_iodesc[] = {}; | 225 | static struct map_desc smdk6410_iodesc[] = {}; |
| 188 | 226 | ||
| 189 | static struct platform_device *smdk6410_devices[] __initdata = { | 227 | static struct platform_device *smdk6410_devices[] __initdata = { |
| @@ -198,6 +236,10 @@ static struct platform_device *smdk6410_devices[] __initdata = { | |||
| 198 | &s3c_device_fb, | 236 | &s3c_device_fb, |
| 199 | &s3c_device_usb, | 237 | &s3c_device_usb, |
| 200 | &s3c_device_usb_hsotg, | 238 | &s3c_device_usb_hsotg, |
| 239 | |||
| 240 | #ifdef CONFIG_REGULATOR | ||
| 241 | &smdk6410_b_pwr_5v, | ||
| 242 | #endif | ||
| 201 | &smdk6410_lcd_powerdev, | 243 | &smdk6410_lcd_powerdev, |
| 202 | 244 | ||
| 203 | &smdk6410_smsc911x, | 245 | &smdk6410_smsc911x, |
| @@ -232,6 +274,14 @@ static struct regulator_init_data wm8350_dcdc3_data = { | |||
| 232 | }; | 274 | }; |
| 233 | 275 | ||
| 234 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ | 276 | /* USB, EXT, PCM, ADC/DAC, USB, MMC */ |
| 277 | static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = { | ||
| 278 | { | ||
| 279 | /* WM8580 */ | ||
| 280 | .supply = "DVDD", | ||
| 281 | .dev_name = "0-001b", | ||
| 282 | }, | ||
| 283 | }; | ||
| 284 | |||
| 235 | static struct regulator_init_data wm8350_dcdc4_data = { | 285 | static struct regulator_init_data wm8350_dcdc4_data = { |
| 236 | .constraints = { | 286 | .constraints = { |
| 237 | .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV", | 287 | .name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV", |
| @@ -239,6 +289,8 @@ static struct regulator_init_data wm8350_dcdc4_data = { | |||
| 239 | .max_uV = 3000000, | 289 | .max_uV = 3000000, |
| 240 | .always_on = 1, | 290 | .always_on = 1, |
| 241 | }, | 291 | }, |
| 292 | .num_consumer_supplies = ARRAY_SIZE(wm8350_dcdc4_consumers), | ||
| 293 | .consumer_supplies = wm8350_dcdc4_consumers, | ||
| 242 | }; | 294 | }; |
| 243 | 295 | ||
| 244 | /* ARM core */ | 296 | /* ARM core */ |
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index b1a4ba504416..0dd2b8c6eabe 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig | |||
| @@ -14,9 +14,23 @@ config CPU_S5PC100 | |||
| 14 | help | 14 | help |
| 15 | Enable S5PC100 CPU support | 15 | Enable S5PC100 CPU support |
| 16 | 16 | ||
| 17 | config S5PC100_SETUP_SDHCI | ||
| 18 | bool | ||
| 19 | select S5PC1XX_SETUP_SDHCI_GPIO | ||
| 20 | help | ||
| 21 | Internal helper functions for S5PC100 based SDHCI systems | ||
| 22 | |||
| 17 | config MACH_SMDKC100 | 23 | config MACH_SMDKC100 |
| 18 | bool "SMDKC100" | 24 | bool "SMDKC100" |
| 19 | select CPU_S5PC100 | 25 | select CPU_S5PC100 |
| 26 | select S3C_DEV_FB | ||
| 27 | select S3C_DEV_I2C1 | ||
| 28 | select S3C_DEV_HSMMC | ||
| 29 | select S3C_DEV_HSMMC1 | ||
| 30 | select S3C_DEV_HSMMC2 | ||
| 31 | select S5PC1XX_SETUP_I2C0 | ||
| 20 | select S5PC1XX_SETUP_I2C1 | 32 | select S5PC1XX_SETUP_I2C1 |
| 33 | select S5PC1XX_SETUP_FB_24BPP | ||
| 34 | select S5PC100_SETUP_SDHCI | ||
| 21 | help | 35 | help |
| 22 | Machine support for the Samsung SMDKC100 | 36 | Machine support for the Samsung SMDKC100 |
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index afc89b381d7a..809ff10f768f 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile | |||
| @@ -13,5 +13,9 @@ obj- := | |||
| 13 | 13 | ||
| 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o | 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o |
| 15 | 15 | ||
| 16 | # Helper and device support | ||
| 17 | |||
| 18 | obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o | ||
| 19 | |||
| 16 | # machine support | 20 | # machine support |
| 17 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o | 21 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o |
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index 0e718890da32..d79e7574a852 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #include <linux/serial_core.h> | 22 | #include <linux/serial_core.h> |
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | 24 | ||
| 25 | #include <asm/proc-fns.h> | ||
| 26 | |||
| 25 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 27 | #include <asm/mach/irq.h> | 29 | #include <asm/mach/irq.h> |
| @@ -32,6 +34,7 @@ | |||
| 32 | 34 | ||
| 33 | #include <plat/cpu-freq.h> | 35 | #include <plat/cpu-freq.h> |
| 34 | #include <plat/regs-serial.h> | 36 | #include <plat/regs-serial.h> |
| 37 | #include <plat/regs-power.h> | ||
| 35 | 38 | ||
| 36 | #include <plat/cpu.h> | 39 | #include <plat/cpu.h> |
| 37 | #include <plat/devs.h> | 40 | #include <plat/devs.h> |
| @@ -45,6 +48,23 @@ | |||
| 45 | static struct map_desc s5pc100_iodesc[] __initdata = { | 48 | static struct map_desc s5pc100_iodesc[] __initdata = { |
| 46 | }; | 49 | }; |
| 47 | 50 | ||
| 51 | static void s5pc100_idle(void) | ||
| 52 | { | ||
| 53 | unsigned long tmp; | ||
| 54 | |||
| 55 | tmp = __raw_readl(S5PC100_PWR_CFG); | ||
| 56 | tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE; | ||
| 57 | tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK; | ||
| 58 | tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE; | ||
| 59 | __raw_writel(tmp, S5PC100_PWR_CFG); | ||
| 60 | |||
| 61 | tmp = __raw_readl(S5PC100_OTHERS); | ||
| 62 | tmp |= S5PC100_PMU_INT_DISABLE; | ||
| 63 | __raw_writel(tmp, S5PC100_OTHERS); | ||
| 64 | |||
| 65 | cpu_do_idle(); | ||
| 66 | } | ||
| 67 | |||
| 48 | /* s5pc100_map_io | 68 | /* s5pc100_map_io |
| 49 | * | 69 | * |
| 50 | * register the standard cpu IO areas | 70 | * register the standard cpu IO areas |
| @@ -55,6 +75,13 @@ void __init s5pc100_map_io(void) | |||
| 55 | iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); | 75 | iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); |
| 56 | 76 | ||
| 57 | /* initialise device information early */ | 77 | /* initialise device information early */ |
| 78 | s5pc100_default_sdhci0(); | ||
| 79 | s5pc100_default_sdhci1(); | ||
| 80 | s5pc100_default_sdhci2(); | ||
| 81 | |||
| 82 | /* the i2c devices are directly compatible with s3c2440 */ | ||
| 83 | s3c_i2c0_setname("s3c2440-i2c"); | ||
| 84 | s3c_i2c1_setname("s3c2440-i2c"); | ||
| 58 | } | 85 | } |
| 59 | 86 | ||
| 60 | void __init s5pc100_init_clocks(int xtal) | 87 | void __init s5pc100_init_clocks(int xtal) |
| @@ -93,5 +120,7 @@ int __init s5pc100_init(void) | |||
| 93 | { | 120 | { |
| 94 | printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); | 121 | printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); |
| 95 | 122 | ||
| 123 | s5pc1xx_idle = s5pc100_idle; | ||
| 124 | |||
| 96 | return sysdev_register(&s5pc100_sysdev); | 125 | return sysdev_register(&s5pc100_sysdev); |
| 97 | } | 126 | } |
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index c74fc93d7d15..2c4cbe8ee6b7 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h | |||
| @@ -18,40 +18,45 @@ | |||
| 18 | #define gpio_to_irq __gpio_to_irq | 18 | #define gpio_to_irq __gpio_to_irq |
| 19 | 19 | ||
| 20 | /* GPIO bank sizes */ | 20 | /* GPIO bank sizes */ |
| 21 | #define S5PC1XX_GPIO_A0_NR (8) | 21 | #define S5PC100_GPIO_A0_NR (8) |
| 22 | #define S5PC1XX_GPIO_A1_NR (5) | 22 | #define S5PC100_GPIO_A1_NR (5) |
| 23 | #define S5PC1XX_GPIO_B_NR (8) | 23 | #define S5PC100_GPIO_B_NR (8) |
| 24 | #define S5PC1XX_GPIO_C_NR (5) | 24 | #define S5PC100_GPIO_C_NR (5) |
| 25 | #define S5PC1XX_GPIO_D_NR (7) | 25 | #define S5PC100_GPIO_D_NR (7) |
| 26 | #define S5PC1XX_GPIO_E0_NR (8) | 26 | #define S5PC100_GPIO_E0_NR (8) |
| 27 | #define S5PC1XX_GPIO_E1_NR (6) | 27 | #define S5PC100_GPIO_E1_NR (6) |
| 28 | #define S5PC1XX_GPIO_F0_NR (8) | 28 | #define S5PC100_GPIO_F0_NR (8) |
| 29 | #define S5PC1XX_GPIO_F1_NR (8) | 29 | #define S5PC100_GPIO_F1_NR (8) |
| 30 | #define S5PC1XX_GPIO_F2_NR (8) | 30 | #define S5PC100_GPIO_F2_NR (8) |
| 31 | #define S5PC1XX_GPIO_F3_NR (4) | 31 | #define S5PC100_GPIO_F3_NR (4) |
| 32 | #define S5PC1XX_GPIO_G0_NR (8) | 32 | #define S5PC100_GPIO_G0_NR (8) |
| 33 | #define S5PC1XX_GPIO_G1_NR (3) | 33 | #define S5PC100_GPIO_G1_NR (3) |
| 34 | #define S5PC1XX_GPIO_G2_NR (7) | 34 | #define S5PC100_GPIO_G2_NR (7) |
| 35 | #define S5PC1XX_GPIO_G3_NR (7) | 35 | #define S5PC100_GPIO_G3_NR (7) |
| 36 | #define S5PC1XX_GPIO_H0_NR (8) | 36 | #define S5PC100_GPIO_H0_NR (8) |
| 37 | #define S5PC1XX_GPIO_H1_NR (8) | 37 | #define S5PC100_GPIO_H1_NR (8) |
| 38 | #define S5PC1XX_GPIO_H2_NR (8) | 38 | #define S5PC100_GPIO_H2_NR (8) |
| 39 | #define S5PC1XX_GPIO_H3_NR (8) | 39 | #define S5PC100_GPIO_H3_NR (8) |
| 40 | #define S5PC1XX_GPIO_I_NR (8) | 40 | #define S5PC100_GPIO_I_NR (8) |
| 41 | #define S5PC1XX_GPIO_J0_NR (8) | 41 | #define S5PC100_GPIO_J0_NR (8) |
| 42 | #define S5PC1XX_GPIO_J1_NR (5) | 42 | #define S5PC100_GPIO_J1_NR (5) |
| 43 | #define S5PC1XX_GPIO_J2_NR (8) | 43 | #define S5PC100_GPIO_J2_NR (8) |
| 44 | #define S5PC1XX_GPIO_J3_NR (8) | 44 | #define S5PC100_GPIO_J3_NR (8) |
| 45 | #define S5PC1XX_GPIO_J4_NR (4) | 45 | #define S5PC100_GPIO_J4_NR (4) |
| 46 | #define S5PC1XX_GPIO_K0_NR (8) | 46 | #define S5PC100_GPIO_K0_NR (8) |
| 47 | #define S5PC1XX_GPIO_K1_NR (6) | 47 | #define S5PC100_GPIO_K1_NR (6) |
| 48 | #define S5PC1XX_GPIO_K2_NR (8) | 48 | #define S5PC100_GPIO_K2_NR (8) |
| 49 | #define S5PC1XX_GPIO_K3_NR (8) | 49 | #define S5PC100_GPIO_K3_NR (8) |
| 50 | #define S5PC1XX_GPIO_MP00_NR (8) | 50 | #define S5PC100_GPIO_L0_NR (8) |
| 51 | #define S5PC1XX_GPIO_MP01_NR (8) | 51 | #define S5PC100_GPIO_L1_NR (8) |
| 52 | #define S5PC1XX_GPIO_MP02_NR (8) | 52 | #define S5PC100_GPIO_L2_NR (8) |
| 53 | #define S5PC1XX_GPIO_MP03_NR (8) | 53 | #define S5PC100_GPIO_L3_NR (8) |
| 54 | #define S5PC1XX_GPIO_MP04_NR (5) | 54 | #define S5PC100_GPIO_L4_NR (8) |
| 55 | #define S5PC100_GPIO_MP00_NR (8) | ||
| 56 | #define S5PC100_GPIO_MP01_NR (8) | ||
| 57 | #define S5PC100_GPIO_MP02_NR (8) | ||
| 58 | #define S5PC100_GPIO_MP03_NR (8) | ||
| 59 | #define S5PC100_GPIO_MP04_NR (5) | ||
| 55 | 60 | ||
| 56 | /* GPIO bank numbes */ | 61 | /* GPIO bank numbes */ |
| 57 | 62 | ||
| @@ -64,83 +69,94 @@ | |||
| 64 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | 69 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) |
| 65 | 70 | ||
| 66 | enum s3c_gpio_number { | 71 | enum s3c_gpio_number { |
| 67 | S5PC1XX_GPIO_A0_START = 0, | 72 | S5PC100_GPIO_A0_START = 0, |
| 68 | S5PC1XX_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0), | 73 | S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0), |
| 69 | S5PC1XX_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1), | 74 | S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1), |
| 70 | S5PC1XX_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B), | 75 | S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B), |
| 71 | S5PC1XX_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C), | 76 | S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C), |
| 72 | S5PC1XX_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D), | 77 | S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D), |
| 73 | S5PC1XX_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0), | 78 | S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0), |
| 74 | S5PC1XX_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1), | 79 | S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1), |
| 75 | S5PC1XX_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0), | 80 | S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0), |
| 76 | S5PC1XX_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1), | 81 | S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1), |
| 77 | S5PC1XX_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2), | 82 | S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2), |
| 78 | S5PC1XX_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3), | 83 | S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3), |
| 79 | S5PC1XX_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0), | 84 | S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0), |
| 80 | S5PC1XX_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1), | 85 | S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1), |
| 81 | S5PC1XX_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2), | 86 | S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2), |
| 82 | S5PC1XX_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3), | 87 | S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3), |
| 83 | S5PC1XX_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0), | 88 | S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0), |
| 84 | S5PC1XX_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1), | 89 | S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1), |
| 85 | S5PC1XX_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2), | 90 | S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2), |
| 86 | S5PC1XX_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3), | 91 | S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3), |
| 87 | S5PC1XX_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I), | 92 | S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I), |
| 88 | S5PC1XX_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0), | 93 | S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0), |
| 89 | S5PC1XX_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1), | 94 | S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1), |
| 90 | S5PC1XX_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2), | 95 | S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2), |
| 91 | S5PC1XX_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3), | 96 | S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3), |
| 92 | S5PC1XX_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4), | 97 | S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4), |
| 93 | S5PC1XX_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0), | 98 | S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0), |
| 94 | S5PC1XX_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1), | 99 | S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1), |
| 95 | S5PC1XX_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2), | 100 | S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2), |
| 96 | S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3), | 101 | S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3), |
| 97 | S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00), | 102 | S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0), |
| 98 | S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01), | 103 | S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1), |
| 99 | S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02), | 104 | S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2), |
| 100 | S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03), | 105 | S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3), |
| 106 | S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4), | ||
| 107 | S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00), | ||
| 108 | S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01), | ||
| 109 | S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02), | ||
| 110 | S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03), | ||
| 111 | S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04), | ||
| 101 | }; | 112 | }; |
| 102 | 113 | ||
| 103 | /* S5PC1XX GPIO number definitions. */ | 114 | /* S5PC100 GPIO number definitions. */ |
| 104 | #define S5PC1XX_GPA0(_nr) (S5PC1XX_GPIO_A0_START + (_nr)) | 115 | #define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr)) |
| 105 | #define S5PC1XX_GPA1(_nr) (S5PC1XX_GPIO_A1_START + (_nr)) | 116 | #define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr)) |
| 106 | #define S5PC1XX_GPB(_nr) (S5PC1XX_GPIO_B_START + (_nr)) | 117 | #define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr)) |
| 107 | #define S5PC1XX_GPC(_nr) (S5PC1XX_GPIO_C_START + (_nr)) | 118 | #define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr)) |
| 108 | #define S5PC1XX_GPD(_nr) (S5PC1XX_GPIO_D_START + (_nr)) | 119 | #define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr)) |
| 109 | #define S5PC1XX_GPE0(_nr) (S5PC1XX_GPIO_E0_START + (_nr)) | 120 | #define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr)) |
| 110 | #define S5PC1XX_GPE1(_nr) (S5PC1XX_GPIO_E1_START + (_nr)) | 121 | #define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr)) |
| 111 | #define S5PC1XX_GPF0(_nr) (S5PC1XX_GPIO_F0_START + (_nr)) | 122 | #define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr)) |
| 112 | #define S5PC1XX_GPF1(_nr) (S5PC1XX_GPIO_F1_START + (_nr)) | 123 | #define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr)) |
| 113 | #define S5PC1XX_GPF2(_nr) (S5PC1XX_GPIO_F2_START + (_nr)) | 124 | #define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr)) |
| 114 | #define S5PC1XX_GPF3(_nr) (S5PC1XX_GPIO_F3_START + (_nr)) | 125 | #define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr)) |
| 115 | #define S5PC1XX_GPG0(_nr) (S5PC1XX_GPIO_G0_START + (_nr)) | 126 | #define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr)) |
| 116 | #define S5PC1XX_GPG1(_nr) (S5PC1XX_GPIO_G1_START + (_nr)) | 127 | #define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr)) |
| 117 | #define S5PC1XX_GPG2(_nr) (S5PC1XX_GPIO_G2_START + (_nr)) | 128 | #define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr)) |
| 118 | #define S5PC1XX_GPG3(_nr) (S5PC1XX_GPIO_G3_START + (_nr)) | 129 | #define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr)) |
| 119 | #define S5PC1XX_GPH0(_nr) (S5PC1XX_GPIO_H0_START + (_nr)) | 130 | #define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr)) |
| 120 | #define S5PC1XX_GPH1(_nr) (S5PC1XX_GPIO_H1_START + (_nr)) | 131 | #define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr)) |
| 121 | #define S5PC1XX_GPH2(_nr) (S5PC1XX_GPIO_H2_START + (_nr)) | 132 | #define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr)) |
| 122 | #define S5PC1XX_GPH3(_nr) (S5PC1XX_GPIO_H3_START + (_nr)) | 133 | #define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr)) |
| 123 | #define S5PC1XX_GPI(_nr) (S5PC1XX_GPIO_I_START + (_nr)) | 134 | #define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr)) |
| 124 | #define S5PC1XX_GPJ0(_nr) (S5PC1XX_GPIO_J0_START + (_nr)) | 135 | #define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr)) |
| 125 | #define S5PC1XX_GPJ1(_nr) (S5PC1XX_GPIO_J1_START + (_nr)) | 136 | #define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr)) |
| 126 | #define S5PC1XX_GPJ2(_nr) (S5PC1XX_GPIO_J2_START + (_nr)) | 137 | #define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr)) |
| 127 | #define S5PC1XX_GPJ3(_nr) (S5PC1XX_GPIO_J3_START + (_nr)) | 138 | #define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr)) |
| 128 | #define S5PC1XX_GPJ4(_nr) (S5PC1XX_GPIO_J4_START + (_nr)) | 139 | #define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr)) |
| 129 | #define S5PC1XX_GPK0(_nr) (S5PC1XX_GPIO_K0_START + (_nr)) | 140 | #define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr)) |
| 130 | #define S5PC1XX_GPK1(_nr) (S5PC1XX_GPIO_K1_START + (_nr)) | 141 | #define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr)) |
| 131 | #define S5PC1XX_GPK2(_nr) (S5PC1XX_GPIO_K2_START + (_nr)) | 142 | #define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr)) |
| 132 | #define S5PC1XX_GPK3(_nr) (S5PC1XX_GPIO_K3_START + (_nr)) | 143 | #define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr)) |
| 133 | #define S5PC1XX_MP00(_nr) (S5PC1XX_GPIO_MP00_START + (_nr)) | 144 | #define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr)) |
| 134 | #define S5PC1XX_MP01(_nr) (S5PC1XX_GPIO_MP01_START + (_nr)) | 145 | #define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr)) |
| 135 | #define S5PC1XX_MP02(_nr) (S5PC1XX_GPIO_MP02_START + (_nr)) | 146 | #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) |
| 136 | #define S5PC1XX_MP03(_nr) (S5PC1XX_GPIO_MP03_START + (_nr)) | 147 | #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) |
| 137 | #define S5PC1XX_MP04(_nr) (S5PC1XX_GPIO_MP04_START + (_nr)) | 148 | #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) |
| 149 | #define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr)) | ||
| 150 | #define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr)) | ||
| 151 | #define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr)) | ||
| 152 | #define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr)) | ||
| 153 | #define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr)) | ||
| 154 | #define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr)) | ||
| 138 | 155 | ||
| 139 | /* the end of the S5PC1XX specific gpios */ | 156 | /* It used the end of the S5PC1XX gpios */ |
| 140 | #define S5PC1XX_GPIO_END (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) | 157 | #define S3C_GPIO_END S5PC100_GPIO_END |
| 141 | #define S3C_GPIO_END S5PC1XX_GPIO_END | ||
| 142 | 158 | ||
| 143 | /* define the number of gpios we need to the one after the MP04() range */ | 159 | /* define the number of gpios we need to the one after the MP04() range */ |
| 144 | #define ARCH_NR_GPIOS (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1) | 160 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) |
| 145 | 161 | ||
| 146 | #include <asm-generic/gpio.h> | 162 | #include <asm-generic/gpio.h> |
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index 622720dba289..b53fa48a52c6 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h | |||
| @@ -11,4 +11,9 @@ | |||
| 11 | 11 | ||
| 12 | #include <plat/irqs.h> | 12 | #include <plat/irqs.h> |
| 13 | 13 | ||
| 14 | /* LCD */ | ||
| 15 | #define IRQ_LCD_FIFO IRQ_LCD0 | ||
| 16 | #define IRQ_LCD_VSYNC IRQ_LCD1 | ||
| 17 | #define IRQ_LCD_SYSTEM IRQ_LCD2 | ||
| 18 | |||
| 14 | #endif /* __ASM_ARCH_IRQ_H */ | 19 | #endif /* __ASM_ARCH_IRQ_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 9e9f39130b2c..4681ebe8bef6 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h | |||
| @@ -17,6 +17,19 @@ | |||
| 17 | 17 | ||
| 18 | #include <plat/map-base.h> | 18 | #include <plat/map-base.h> |
| 19 | 19 | ||
| 20 | /* | ||
| 21 | * map-base.h has already defined virtual memory address | ||
| 22 | * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) | ||
| 23 | * S3C_VA_SYS S3C_ADDR(0x00100000) system control | ||
| 24 | * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) | ||
| 25 | * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block | ||
| 26 | * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog | ||
| 27 | * S3C_VA_UART S3C_ADDR(0x01000000) UART | ||
| 28 | * | ||
| 29 | * S5PC100 specific virtual memory address can be defined here | ||
| 30 | * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO | ||
| 31 | * | ||
| 32 | */ | ||
| 20 | 33 | ||
| 21 | /* Chip ID */ | 34 | /* Chip ID */ |
| 22 | #define S5PC100_PA_CHIPID (0xE0000000) | 35 | #define S5PC100_PA_CHIPID (0xE0000000) |
| @@ -24,13 +37,20 @@ | |||
| 24 | #define S5PC1XX_VA_CHIPID S3C_VA_SYS | 37 | #define S5PC1XX_VA_CHIPID S3C_VA_SYS |
| 25 | 38 | ||
| 26 | /* System */ | 39 | /* System */ |
| 27 | #define S5PC100_PA_SYS (0xE0100000) | 40 | #define S5PC100_PA_CLK (0xE0100000) |
| 28 | #define S5PC100_PA_CLK (S5PC100_PA_SYS + 0x0) | 41 | #define S5PC100_PA_CLK_OTHER (0xE0200000) |
| 29 | #define S5PC100_PA_PWR (S5PC100_PA_SYS + 0x8000) | 42 | #define S5PC100_PA_PWR (0xE0108000) |
| 30 | #define S5PC1XX_PA_CLK S5PC100_PA_CLK | 43 | #define S5PC1XX_PA_CLK S5PC100_PA_CLK |
| 31 | #define S5PC1XX_PA_PWR S5PC100_PA_PWR | 44 | #define S5PC1XX_PA_PWR S5PC100_PA_PWR |
| 45 | #define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER | ||
| 32 | #define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) | 46 | #define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) |
| 33 | #define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) | 47 | #define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) |
| 48 | #define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000) | ||
| 49 | |||
| 50 | /* GPIO */ | ||
| 51 | #define S5PC100_PA_GPIO (0xE0300000) | ||
| 52 | #define S5PC1XX_PA_GPIO S5PC100_PA_GPIO | ||
| 53 | #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) | ||
| 34 | 54 | ||
| 35 | /* Interrupt */ | 55 | /* Interrupt */ |
| 36 | #define S5PC100_PA_VIC (0xE4000000) | 56 | #define S5PC100_PA_VIC (0xE4000000) |
| @@ -40,23 +60,64 @@ | |||
| 40 | #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) | 60 | #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) |
| 41 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) | 61 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) |
| 42 | 62 | ||
| 63 | /* DMA */ | ||
| 64 | #define S5PC100_PA_MDMA (0xE8100000) | ||
| 65 | #define S5PC100_PA_PDMA0 (0xE9000000) | ||
| 66 | #define S5PC100_PA_PDMA1 (0xE9200000) | ||
| 67 | |||
| 43 | /* Timer */ | 68 | /* Timer */ |
| 44 | #define S5PC100_PA_TIMER (0xEA000000) | 69 | #define S5PC100_PA_TIMER (0xEA000000) |
| 45 | #define S5PC1XX_PA_TIMER S5PC100_PA_TIMER | 70 | #define S5PC1XX_PA_TIMER S5PC100_PA_TIMER |
| 46 | #define S5PC1XX_VA_TIMER S3C_VA_TIMER | 71 | #define S5PC1XX_VA_TIMER S3C_VA_TIMER |
| 47 | 72 | ||
| 73 | /* RTC */ | ||
| 74 | #define S5PC100_PA_RTC (0xEA300000) | ||
| 75 | |||
| 48 | /* UART */ | 76 | /* UART */ |
| 49 | #define S5PC100_PA_UART (0xEC000000) | 77 | #define S5PC100_PA_UART (0xEC000000) |
| 50 | #define S5PC1XX_PA_UART S5PC100_PA_UART | 78 | #define S5PC1XX_PA_UART S5PC100_PA_UART |
| 51 | #define S5PC1XX_VA_UART S3C_VA_UART | 79 | #define S5PC1XX_VA_UART S3C_VA_UART |
| 52 | 80 | ||
| 53 | /* IIC */ | 81 | /* I2C */ |
| 54 | #define S5PC100_PA_IIC (0xEC100000) | 82 | #define S5PC100_PA_I2C (0xEC100000) |
| 83 | #define S5PC100_PA_I2C1 (0xEC200000) | ||
| 84 | |||
| 85 | /* USB HS OTG */ | ||
| 86 | #define S5PC100_PA_USB_HSOTG (0xED200000) | ||
| 87 | #define S5PC100_PA_USB_HSPHY (0xED300000) | ||
| 88 | |||
| 89 | /* SD/MMC */ | ||
| 90 | #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) | ||
| 91 | #define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0) | ||
| 92 | #define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1) | ||
| 93 | #define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2) | ||
| 94 | |||
| 95 | /* LCD */ | ||
| 96 | #define S5PC100_PA_FB (0xEE000000) | ||
| 97 | |||
| 98 | /* Multimedia */ | ||
| 99 | #define S5PC100_PA_G2D (0xEE800000) | ||
| 100 | #define S5PC100_PA_JPEG (0xEE500000) | ||
| 101 | #define S5PC100_PA_ROTATOR (0xEE100000) | ||
| 102 | #define S5PC100_PA_G3D (0xEF000000) | ||
| 103 | |||
| 104 | /* I2S */ | ||
| 105 | #define S5PC100_PA_I2S0 (0xF2000000) | ||
| 106 | #define S5PC100_PA_I2S1 (0xF2100000) | ||
| 107 | #define S5PC100_PA_I2S2 (0xF2200000) | ||
| 108 | |||
| 109 | /* KEYPAD */ | ||
| 110 | #define S5PC100_PA_KEYPAD (0xF3100000) | ||
| 111 | |||
| 112 | /* ADC & TouchScreen */ | ||
| 113 | #define S5PC100_PA_TSADC (0xF3000000) | ||
| 55 | 114 | ||
| 56 | /* ETC */ | 115 | /* ETC */ |
| 57 | #define S5PC100_PA_SDRAM (0x20000000) | 116 | #define S5PC100_PA_SDRAM (0x20000000) |
| 117 | #define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM | ||
| 58 | 118 | ||
| 59 | /* compatibility defines. */ | 119 | /* compatibility defines. */ |
| 120 | #define S3C_PA_RTC S5PC100_PA_RTC | ||
| 60 | #define S3C_PA_UART S5PC100_PA_UART | 121 | #define S3C_PA_UART S5PC100_PA_UART |
| 61 | #define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) | 122 | #define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) |
| 62 | #define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) | 123 | #define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) |
| @@ -67,9 +128,23 @@ | |||
| 67 | #define S3C_VA_UART2 (S3C_VA_UART + 0x800) | 128 | #define S3C_VA_UART2 (S3C_VA_UART + 0x800) |
| 68 | #define S3C_VA_UART3 (S3C_VA_UART + 0xC00) | 129 | #define S3C_VA_UART3 (S3C_VA_UART + 0xC00) |
| 69 | #define S3C_UART_OFFSET 0x400 | 130 | #define S3C_UART_OFFSET 0x400 |
| 131 | #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) | ||
| 132 | #define S3C_PA_FB S5PC100_PA_FB | ||
| 133 | #define S3C_PA_G2D S5PC100_PA_G2D | ||
| 134 | #define S3C_PA_G3D S5PC100_PA_G3D | ||
| 135 | #define S3C_PA_JPEG S5PC100_PA_JPEG | ||
| 136 | #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR | ||
| 70 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) | 137 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) |
| 71 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | 138 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) |
| 72 | #define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) | 139 | #define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) |
| 73 | #define S3C_PA_IIC S5PC100_PA_IIC | 140 | #define S3C_PA_IIC S5PC100_PA_I2C |
| 141 | #define S3C_PA_IIC1 S5PC100_PA_I2C1 | ||
| 142 | #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG | ||
| 143 | #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY | ||
| 144 | #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 | ||
| 145 | #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 | ||
| 146 | #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 | ||
| 147 | #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD | ||
| 148 | #define S3C_PA_TSADC S5PC100_PA_TSADC | ||
| 74 | 149 | ||
| 75 | #endif /* __ASM_ARCH_C100_MAP_H */ | 150 | #endif /* __ASM_ARCH_C100_MAP_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h new file mode 100644 index 000000000000..1732cd28c765 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-fb.h | |||
| @@ -0,0 +1,139 @@ | |||
| 1 | /* arch/arm/mach-s5pc100/include/mach/regs-fb.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Pawel Osciak <p.osciak@samsung.com> | ||
| 5 | * | ||
| 6 | * Framebuffer register definitions for Samsung S5PC100. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_FB_H | ||
| 14 | #define __ASM_ARCH_REGS_FB_H __FILE__ | ||
| 15 | |||
| 16 | #include <plat/regs-fb-v4.h> | ||
| 17 | |||
| 18 | /* VP1 interface timing control */ | ||
| 19 | #define VP1CON0 (0x118) | ||
| 20 | #define VP1_RATECON_EN (1 << 31) | ||
| 21 | #define VP1_CLKRATE_MASK (0xff) | ||
| 22 | |||
| 23 | #define VP1CON1 (0x11c) | ||
| 24 | #define VP1_VTREGCON_EN (1 << 31) | ||
| 25 | #define VP1_VBPD_MASK (0xfff) | ||
| 26 | #define VP1_VBPD_SHIFT (16) | ||
| 27 | |||
| 28 | |||
| 29 | #define WPALCON_H (0x19c) | ||
| 30 | #define WPALCON_L (0x1a0) | ||
| 31 | |||
| 32 | /* Pallete contro for WPAL0 and WPAL1 is the same as in S3C64xx, but | ||
| 33 | * different for WPAL2-4 | ||
| 34 | */ | ||
| 35 | /* In WPALCON_L (aka WPALCON) */ | ||
| 36 | #define WPALCON_W1PAL_32BPP_A888 (0x7 << 3) | ||
| 37 | #define WPALCON_W0PAL_32BPP_A888 (0x7 << 0) | ||
| 38 | |||
| 39 | /* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H, | ||
| 40 | * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]). | ||
| 41 | */ | ||
| 42 | #define WPALCON_L_WxPAL_L_MASK (0x1) | ||
| 43 | #define WPALCON_L_W2PAL_L_SHIFT (6) | ||
| 44 | #define WPALCON_L_W3PAL_L_SHIFT (7) | ||
| 45 | #define WPALCON_L_W4PAL_L_SHIFT (8) | ||
| 46 | |||
| 47 | #define WPALCON_L_WxPAL_H_MASK (0x3) | ||
| 48 | #define WPALCON_H_W2PAL_H_SHIFT (9) | ||
| 49 | #define WPALCON_H_W3PAL_H_SHIFT (13) | ||
| 50 | #define WPALCON_H_W4PAL_H_SHIFT (17) | ||
| 51 | |||
| 52 | /* Per-window alpha value registers */ | ||
| 53 | /* For window 0 8-bit alpha values are in VIDW0ALPHAx, | ||
| 54 | * for windows 1-4 alpha values consist of two parts, the 4 low bits are | ||
| 55 | * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC, | ||
| 56 | * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0]) | ||
| 57 | */ | ||
| 58 | #define VIDWxALPHA0(_win) (0x200 + (_win * 8)) | ||
| 59 | #define VIDWxALPHA1(_win) (0x204 + (_win * 8)) | ||
| 60 | |||
| 61 | /* Only for window 0 in VIDW0ALPHAx. */ | ||
| 62 | #define VIDW0ALPHAx_R(_x) ((_x) << 16) | ||
| 63 | #define VIDW0ALPHAx_R_MASK (0xff << 16) | ||
| 64 | #define VIDW0ALPHAx_R_SHIFT (16) | ||
| 65 | #define VIDW0ALPHAx_G(_x) ((_x) << 8) | ||
| 66 | #define VIDW0ALPHAx_G_MASK (0xff << 8) | ||
| 67 | #define VIDW0ALPHAx_G_SHIFT (8) | ||
| 68 | #define VIDW0ALPHAx_B(_x) ((_x) << 0) | ||
| 69 | #define VIDW0ALPHAx_B_MASK (0xff << 0) | ||
| 70 | #define VIDW0ALPHAx_B_SHIFT (0) | ||
| 71 | |||
| 72 | /* Low 4 bits of alpha0-1 for windows 1-4 */ | ||
| 73 | #define VIDW14ALPHAx_R_L(_x) ((_x) << 16) | ||
| 74 | #define VIDW14ALPHAx_R_L_MASK (0xf << 16) | ||
| 75 | #define VIDW14ALPHAx_R_L_SHIFT (16) | ||
| 76 | #define VIDW14ALPHAx_G_L(_x) ((_x) << 8) | ||
| 77 | #define VIDW14ALPHAx_G_L_MASK (0xf << 8) | ||
| 78 | #define VIDW14ALPHAx_G_L_SHIFT (8) | ||
| 79 | #define VIDW14ALPHAx_B_L(_x) ((_x) << 0) | ||
| 80 | #define VIDW14ALPHAx_B_L_MASK (0xf << 0) | ||
| 81 | #define VIDW14ALPHAx_B_L_SHIFT (0) | ||
| 82 | |||
| 83 | |||
| 84 | /* Per-window blending equation control registers */ | ||
| 85 | #define BLENDEQx(_win) (0x244 + ((_win) * 4)) | ||
| 86 | #define BLENDEQ1 (0x244) | ||
| 87 | #define BLENDEQ2 (0x248) | ||
| 88 | #define BLENDEQ3 (0x24c) | ||
| 89 | #define BLENDEQ4 (0x250) | ||
| 90 | |||
| 91 | #define BLENDEQx_Q_FUNC(_x) ((_x) << 18) | ||
| 92 | #define BLENDEQx_Q_FUNC_MASK (0xf << 18) | ||
| 93 | #define BLENDEQx_P_FUNC(_x) ((_x) << 12) | ||
| 94 | #define BLENDEQx_P_FUNC_MASK (0xf << 12) | ||
| 95 | #define BLENDEQx_B_FUNC(_x) ((_x) << 6) | ||
| 96 | #define BLENDEQx_B_FUNC_MASK (0xf << 6) | ||
| 97 | #define BLENDEQx_A_FUNC(_x) ((_x) << 0) | ||
| 98 | #define BLENDEQx_A_FUNC_MASK (0xf << 0) | ||
| 99 | |||
| 100 | #define BLENDCON (0x260) | ||
| 101 | #define BLENDCON_8BIT_ALPHA (1 << 0) | ||
| 102 | |||
| 103 | /* Per-window palette base addresses (start of palette memory). | ||
| 104 | * Each window palette area consists of 256 32-bit entries. | ||
| 105 | * START is the first address (entry 0th), END is the address of 255th entry. | ||
| 106 | */ | ||
| 107 | #define WIN0_PAL_BASE (0x2400) | ||
| 108 | #define WIN0_PAL_END (0x27fc) | ||
| 109 | #define WIN1_PAL_BASE (0x2800) | ||
| 110 | #define WIN1_PAL_END (0x2bfc) | ||
| 111 | #define WIN2_PAL_BASE (0x2c00) | ||
| 112 | #define WIN2_PAL_END (0x2ffc) | ||
| 113 | #define WIN3_PAL_BASE (0x3000) | ||
| 114 | #define WIN3_PAL_END (0x33fc) | ||
| 115 | #define WIN4_PAL_BASE (0x3400) | ||
| 116 | #define WIN4_PAL_END (0x37fc) | ||
| 117 | |||
| 118 | #define WIN0_PAL(_entry) (WIN0_PAL_BASE + ((_entry) * 4)) | ||
| 119 | #define WIN1_PAL(_entry) (WIN1_PAL_BASE + ((_entry) * 4)) | ||
| 120 | #define WIN2_PAL(_entry) (WIN2_PAL_BASE + ((_entry) * 4)) | ||
| 121 | #define WIN3_PAL(_entry) (WIN3_PAL_BASE + ((_entry) * 4)) | ||
| 122 | #define WIN4_PAL(_entry) (WIN4_PAL_BASE + ((_entry) * 4)) | ||
| 123 | |||
| 124 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | ||
| 125 | { | ||
| 126 | switch (window) { | ||
| 127 | case 0: return WIN0_PAL(reg); | ||
| 128 | case 1: return WIN1_PAL(reg); | ||
| 129 | case 2: return WIN2_PAL(reg); | ||
| 130 | case 3: return WIN3_PAL(reg); | ||
| 131 | case 4: return WIN4_PAL(reg); | ||
| 132 | } | ||
| 133 | |||
| 134 | BUG(); | ||
| 135 | } | ||
| 136 | |||
| 137 | |||
| 138 | #endif /* __ASM_ARCH_REGS_FB_H */ | ||
| 139 | |||
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index e39014375470..f0d31a2a598c 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h | |||
| @@ -11,14 +11,21 @@ | |||
| 11 | #ifndef __ASM_ARCH_SYSTEM_H | 11 | #ifndef __ASM_ARCH_SYSTEM_H |
| 12 | #define __ASM_ARCH_SYSTEM_H __FILE__ | 12 | #define __ASM_ARCH_SYSTEM_H __FILE__ |
| 13 | 13 | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <plat/regs-clock.h> | ||
| 17 | |||
| 18 | void (*s5pc1xx_idle)(void); | ||
| 19 | |||
| 14 | static void arch_idle(void) | 20 | static void arch_idle(void) |
| 15 | { | 21 | { |
| 16 | /* nothing here yet */ | 22 | if (s5pc1xx_idle) |
| 23 | s5pc1xx_idle(); | ||
| 17 | } | 24 | } |
| 18 | 25 | ||
| 19 | static void arch_reset(char mode, const char *cmd) | 26 | static void arch_reset(char mode, const char *cmd) |
| 20 | { | 27 | { |
| 21 | /* nothing here yet */ | 28 | __raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET); |
| 29 | return; | ||
| 22 | } | 30 | } |
| 23 | |||
| 24 | #endif /* __ASM_ARCH_IRQ_H */ | 31 | #endif /* __ASM_ARCH_IRQ_H */ |
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index 214093cd7632..ae3c52cd0ebb 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
| @@ -27,16 +27,22 @@ | |||
| 27 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
| 28 | 28 | ||
| 29 | #include <mach/map.h> | 29 | #include <mach/map.h> |
| 30 | #include <mach/regs-fb.h> | ||
| 31 | #include <video/platform_lcd.h> | ||
| 30 | 32 | ||
| 31 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| 32 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
| 33 | 35 | ||
| 34 | #include <plat/regs-serial.h> | 36 | #include <plat/regs-serial.h> |
| 37 | #include <plat/gpio-cfg.h> | ||
| 38 | #include <plat/regs-gpio.h> | ||
| 35 | 39 | ||
| 36 | #include <plat/clock.h> | 40 | #include <plat/clock.h> |
| 37 | #include <plat/devs.h> | 41 | #include <plat/devs.h> |
| 38 | #include <plat/cpu.h> | 42 | #include <plat/cpu.h> |
| 39 | #include <plat/s5pc100.h> | 43 | #include <plat/s5pc100.h> |
| 44 | #include <plat/fb.h> | ||
| 45 | #include <plat/iic.h> | ||
| 40 | 46 | ||
| 41 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) | 47 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) |
| 42 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | 48 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) |
| @@ -73,9 +79,78 @@ static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | |||
| 73 | }, | 79 | }, |
| 74 | }; | 80 | }; |
| 75 | 81 | ||
| 82 | /* I2C0 */ | ||
| 83 | static struct i2c_board_info i2c_devs0[] __initdata = { | ||
| 84 | }; | ||
| 85 | |||
| 86 | /* I2C1 */ | ||
| 87 | static struct i2c_board_info i2c_devs1[] __initdata = { | ||
| 88 | }; | ||
| 89 | |||
| 90 | /* LCD power controller */ | ||
| 91 | static void smdkc100_lcd_power_set(struct plat_lcd_data *pd, | ||
| 92 | unsigned int power) | ||
| 93 | { | ||
| 94 | /* backlight */ | ||
| 95 | gpio_direction_output(S5PC100_GPD(0), power); | ||
| 96 | |||
| 97 | if (power) { | ||
| 98 | /* module reset */ | ||
| 99 | gpio_direction_output(S5PC100_GPH0(6), 1); | ||
| 100 | mdelay(100); | ||
| 101 | gpio_direction_output(S5PC100_GPH0(6), 0); | ||
| 102 | mdelay(10); | ||
| 103 | gpio_direction_output(S5PC100_GPH0(6), 1); | ||
| 104 | mdelay(10); | ||
| 105 | } | ||
| 106 | } | ||
| 107 | |||
| 108 | static struct plat_lcd_data smdkc100_lcd_power_data = { | ||
| 109 | .set_power = smdkc100_lcd_power_set, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct platform_device smdkc100_lcd_powerdev = { | ||
| 113 | .name = "platform-lcd", | ||
| 114 | .dev.parent = &s3c_device_fb.dev, | ||
| 115 | .dev.platform_data = &smdkc100_lcd_power_data, | ||
| 116 | }; | ||
| 117 | |||
| 118 | /* Frame Buffer */ | ||
| 119 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { | ||
| 120 | /* this is to ensure we use win0 */ | ||
| 121 | .win_mode = { | ||
| 122 | .refresh = 70, | ||
| 123 | .pixclock = (8+13+3+800)*(7+5+1+480), | ||
| 124 | .left_margin = 8, | ||
| 125 | .right_margin = 13, | ||
| 126 | .upper_margin = 7, | ||
| 127 | .lower_margin = 5, | ||
| 128 | .hsync_len = 3, | ||
| 129 | .vsync_len = 1, | ||
| 130 | .xres = 800, | ||
| 131 | .yres = 480, | ||
| 132 | }, | ||
| 133 | .max_bpp = 32, | ||
| 134 | .default_bpp = 16, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { | ||
| 138 | .win[0] = &smdkc100_fb_win0, | ||
| 139 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
| 140 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
| 141 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, | ||
| 142 | }; | ||
| 143 | |||
| 76 | static struct map_desc smdkc100_iodesc[] = {}; | 144 | static struct map_desc smdkc100_iodesc[] = {}; |
| 77 | 145 | ||
| 78 | static struct platform_device *smdkc100_devices[] __initdata = { | 146 | static struct platform_device *smdkc100_devices[] __initdata = { |
| 147 | &s3c_device_i2c0, | ||
| 148 | &s3c_device_i2c1, | ||
| 149 | &s3c_device_fb, | ||
| 150 | &s3c_device_hsmmc0, | ||
| 151 | &s3c_device_hsmmc1, | ||
| 152 | &s3c_device_hsmmc2, | ||
| 153 | &smdkc100_lcd_powerdev, | ||
| 79 | }; | 154 | }; |
| 80 | 155 | ||
| 81 | static void __init smdkc100_map_io(void) | 156 | static void __init smdkc100_map_io(void) |
| @@ -87,12 +162,24 @@ static void __init smdkc100_map_io(void) | |||
| 87 | 162 | ||
| 88 | static void __init smdkc100_machine_init(void) | 163 | static void __init smdkc100_machine_init(void) |
| 89 | { | 164 | { |
| 165 | /* I2C */ | ||
| 166 | s3c_i2c0_set_platdata(NULL); | ||
| 167 | s3c_i2c1_set_platdata(NULL); | ||
| 168 | i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); | ||
| 169 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); | ||
| 170 | |||
| 171 | s3c_fb_set_platdata(&smdkc100_lcd_pdata); | ||
| 172 | |||
| 173 | /* LCD init */ | ||
| 174 | gpio_request(S5PC100_GPD(0), "GPD"); | ||
| 175 | gpio_request(S5PC100_GPH0(6), "GPH0"); | ||
| 176 | smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); | ||
| 90 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); | 177 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); |
| 91 | } | 178 | } |
| 92 | 179 | ||
| 93 | MACHINE_START(SMDKC100, "SMDKC100") | 180 | MACHINE_START(SMDKC100, "SMDKC100") |
| 94 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ | 181 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ |
| 95 | .phys_io = S5PC1XX_PA_UART & 0xfff00000, | 182 | .phys_io = S5PC100_PA_UART & 0xfff00000, |
| 96 | .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, | 183 | .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, |
| 97 | .boot_params = S5PC100_PA_SDRAM + 0x100, | 184 | .boot_params = S5PC100_PA_SDRAM + 0x100, |
| 98 | 185 | ||
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c new file mode 100644 index 000000000000..4385986a3da0 --- /dev/null +++ b/arch/arm/mach-s5pc100/setup-sdhci.c | |||
| @@ -0,0 +1,65 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pc100/setup-sdhci.c | ||
| 2 | * | ||
| 3 | * Copyright 2008 Samsung Electronics | ||
| 4 | * | ||
| 5 | * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC) | ||
| 6 | * | ||
| 7 | * Based on mach-s3c6410/setup-sdhci.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | |||
| 20 | #include <linux/mmc/card.h> | ||
| 21 | #include <linux/mmc/host.h> | ||
| 22 | |||
| 23 | #include <plat/regs-sdhci.h> | ||
| 24 | #include <plat/sdhci.h> | ||
| 25 | |||
| 26 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ | ||
| 27 | |||
| 28 | char *s5pc100_hsmmc_clksrcs[4] = { | ||
| 29 | [0] = "hsmmc", | ||
| 30 | [1] = "hsmmc", | ||
| 31 | /* [2] = "mmc_bus", not yet succesfuuly used yet */ | ||
| 32 | /* [3] = "48m", - note not succesfully used yet */ | ||
| 33 | }; | ||
| 34 | |||
| 35 | |||
| 36 | void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, | ||
| 37 | void __iomem *r, | ||
| 38 | struct mmc_ios *ios, | ||
| 39 | struct mmc_card *card) | ||
| 40 | { | ||
| 41 | u32 ctrl2, ctrl3; | ||
| 42 | |||
| 43 | /* don't need to alter anything acording to card-type */ | ||
| 44 | |||
| 45 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); | ||
| 46 | |||
| 47 | ctrl2 = readl(r + S3C_SDHCI_CONTROL2); | ||
| 48 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | ||
| 49 | ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | ||
| 50 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | ||
| 51 | S3C_SDHCI_CTRL2_ENFBCLKRX | | ||
| 52 | S3C_SDHCI_CTRL2_DFCNT_NONE | | ||
| 53 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | ||
| 54 | |||
| 55 | if (ios->clock < 25 * 1000000) | ||
| 56 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | | ||
| 57 | S3C_SDHCI_CTRL3_FCSEL2 | | ||
| 58 | S3C_SDHCI_CTRL3_FCSEL1 | | ||
| 59 | S3C_SDHCI_CTRL3_FCSEL0); | ||
| 60 | else | ||
| 61 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | ||
| 62 | |||
| 63 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | ||
| 64 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | ||
| 65 | } | ||
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 7b7d4c36c11c..dd4698c67cc3 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -388,7 +388,7 @@ config CPU_FEROCEON_OLD_ID | |||
| 388 | 388 | ||
| 389 | # ARMv6 | 389 | # ARMv6 |
| 390 | config CPU_V6 | 390 | config CPU_V6 |
| 391 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX | 391 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE |
| 392 | select CPU_32v6 | 392 | select CPU_32v6 |
| 393 | select CPU_ABRT_EV6 | 393 | select CPU_ABRT_EV6 |
| 394 | select CPU_PABRT_V6 | 394 | select CPU_PABRT_V6 |
| @@ -764,6 +764,15 @@ config CACHE_L2X0 | |||
| 764 | help | 764 | help |
| 765 | This option enables the L2x0 PrimeCell. | 765 | This option enables the L2x0 PrimeCell. |
| 766 | 766 | ||
| 767 | config CACHE_TAUROS2 | ||
| 768 | bool "Enable the Tauros2 L2 cache controller" | ||
| 769 | depends on ARCH_DOVE | ||
| 770 | default y | ||
| 771 | select OUTER_CACHE | ||
| 772 | help | ||
| 773 | This option enables the Tauros2 L2 cache controller (as | ||
| 774 | found on PJ1/PJ4). | ||
| 775 | |||
| 767 | config CACHE_XSC3L2 | 776 | config CACHE_XSC3L2 |
| 768 | bool "Enable the L2 cache on XScale3" | 777 | bool "Enable the L2 cache on XScale3" |
| 769 | depends on CPU_XSC3 | 778 | depends on CPU_XSC3 |
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 42352e75742b..827e238e5d4a 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile | |||
| @@ -87,4 +87,4 @@ obj-$(CONFIG_CPU_V7) += proc-v7.o | |||
| 87 | obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o | 87 | obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o |
| 88 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o | 88 | obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o |
| 89 | obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o | 89 | obj-$(CONFIG_CACHE_XSC3L2) += cache-xsc3l2.o |
| 90 | 90 | obj-$(CONFIG_CACHE_TAUROS2) += cache-tauros2.o | |
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c new file mode 100644 index 000000000000..50868651890f --- /dev/null +++ b/arch/arm/mm/cache-tauros2.c | |||
| @@ -0,0 +1,263 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Marvell Semiconductor | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | * | ||
| 10 | * References: | ||
| 11 | * - PJ1 CPU Core Datasheet, | ||
| 12 | * Document ID MV-S104837-01, Rev 0.7, January 24 2008. | ||
| 13 | * - PJ4 CPU Core Datasheet, | ||
| 14 | * Document ID MV-S105190-00, Rev 0.7, March 14 2008. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/init.h> | ||
| 18 | #include <asm/cacheflush.h> | ||
| 19 | #include <asm/hardware/cache-tauros2.h> | ||
| 20 | |||
| 21 | |||
| 22 | /* | ||
| 23 | * When Tauros2 is used on a CPU that supports the v7 hierarchical | ||
| 24 | * cache operations, the cache handling code in proc-v7.S takes care | ||
| 25 | * of everything, including handling DMA coherency. | ||
| 26 | * | ||
| 27 | * So, we only need to register outer cache operations here if we're | ||
| 28 | * being used on a pre-v7 CPU, and we only need to build support for | ||
| 29 | * outer cache operations into the kernel image if the kernel has been | ||
| 30 | * configured to support a pre-v7 CPU. | ||
| 31 | */ | ||
| 32 | #if __LINUX_ARM_ARCH__ < 7 | ||
| 33 | /* | ||
| 34 | * Low-level cache maintenance operations. | ||
| 35 | */ | ||
| 36 | static inline void tauros2_clean_pa(unsigned long addr) | ||
| 37 | { | ||
| 38 | __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); | ||
| 39 | } | ||
| 40 | |||
| 41 | static inline void tauros2_clean_inv_pa(unsigned long addr) | ||
| 42 | { | ||
| 43 | __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); | ||
| 44 | } | ||
| 45 | |||
| 46 | static inline void tauros2_inv_pa(unsigned long addr) | ||
| 47 | { | ||
| 48 | __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); | ||
| 49 | } | ||
| 50 | |||
| 51 | |||
| 52 | /* | ||
| 53 | * Linux primitives. | ||
| 54 | * | ||
| 55 | * Note that the end addresses passed to Linux primitives are | ||
| 56 | * noninclusive. | ||
| 57 | */ | ||
| 58 | #define CACHE_LINE_SIZE 32 | ||
| 59 | |||
| 60 | static void tauros2_inv_range(unsigned long start, unsigned long end) | ||
| 61 | { | ||
| 62 | /* | ||
| 63 | * Clean and invalidate partial first cache line. | ||
| 64 | */ | ||
| 65 | if (start & (CACHE_LINE_SIZE - 1)) { | ||
| 66 | tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); | ||
| 67 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; | ||
| 68 | } | ||
| 69 | |||
| 70 | /* | ||
| 71 | * Clean and invalidate partial last cache line. | ||
| 72 | */ | ||
| 73 | if (end & (CACHE_LINE_SIZE - 1)) { | ||
| 74 | tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); | ||
| 75 | end &= ~(CACHE_LINE_SIZE - 1); | ||
| 76 | } | ||
| 77 | |||
| 78 | /* | ||
| 79 | * Invalidate all full cache lines between 'start' and 'end'. | ||
| 80 | */ | ||
| 81 | while (start < end) { | ||
| 82 | tauros2_inv_pa(start); | ||
| 83 | start += CACHE_LINE_SIZE; | ||
| 84 | } | ||
| 85 | |||
| 86 | dsb(); | ||
| 87 | } | ||
| 88 | |||
| 89 | static void tauros2_clean_range(unsigned long start, unsigned long end) | ||
| 90 | { | ||
| 91 | start &= ~(CACHE_LINE_SIZE - 1); | ||
| 92 | while (start < end) { | ||
| 93 | tauros2_clean_pa(start); | ||
| 94 | start += CACHE_LINE_SIZE; | ||
| 95 | } | ||
| 96 | |||
| 97 | dsb(); | ||
| 98 | } | ||
| 99 | |||
| 100 | static void tauros2_flush_range(unsigned long start, unsigned long end) | ||
| 101 | { | ||
| 102 | start &= ~(CACHE_LINE_SIZE - 1); | ||
| 103 | while (start < end) { | ||
| 104 | tauros2_clean_inv_pa(start); | ||
| 105 | start += CACHE_LINE_SIZE; | ||
| 106 | } | ||
| 107 | |||
| 108 | dsb(); | ||
| 109 | } | ||
| 110 | #endif | ||
| 111 | |||
| 112 | static inline u32 __init read_extra_features(void) | ||
| 113 | { | ||
| 114 | u32 u; | ||
| 115 | |||
| 116 | __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); | ||
| 117 | |||
| 118 | return u; | ||
| 119 | } | ||
| 120 | |||
| 121 | static inline void __init write_extra_features(u32 u) | ||
| 122 | { | ||
| 123 | __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); | ||
| 124 | } | ||
| 125 | |||
| 126 | static void __init disable_l2_prefetch(void) | ||
| 127 | { | ||
| 128 | u32 u; | ||
| 129 | |||
| 130 | /* | ||
| 131 | * Read the CPU Extra Features register and verify that the | ||
| 132 | * Disable L2 Prefetch bit is set. | ||
| 133 | */ | ||
| 134 | u = read_extra_features(); | ||
| 135 | if (!(u & 0x01000000)) { | ||
| 136 | printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n"); | ||
| 137 | write_extra_features(u | 0x01000000); | ||
| 138 | } | ||
| 139 | } | ||
| 140 | |||
| 141 | static inline int __init cpuid_scheme(void) | ||
| 142 | { | ||
| 143 | extern int processor_id; | ||
| 144 | |||
| 145 | return !!((processor_id & 0x000f0000) == 0x000f0000); | ||
| 146 | } | ||
| 147 | |||
| 148 | static inline u32 __init read_mmfr3(void) | ||
| 149 | { | ||
| 150 | u32 mmfr3; | ||
| 151 | |||
| 152 | __asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3)); | ||
| 153 | |||
| 154 | return mmfr3; | ||
| 155 | } | ||
| 156 | |||
| 157 | static inline u32 __init read_actlr(void) | ||
| 158 | { | ||
| 159 | u32 actlr; | ||
| 160 | |||
| 161 | __asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr)); | ||
| 162 | |||
| 163 | return actlr; | ||
| 164 | } | ||
| 165 | |||
| 166 | static inline void __init write_actlr(u32 actlr) | ||
| 167 | { | ||
| 168 | __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); | ||
| 169 | } | ||
| 170 | |||
| 171 | void __init tauros2_init(void) | ||
| 172 | { | ||
| 173 | extern int processor_id; | ||
| 174 | char *mode; | ||
| 175 | |||
| 176 | disable_l2_prefetch(); | ||
| 177 | |||
| 178 | #ifdef CONFIG_CPU_32v5 | ||
| 179 | if ((processor_id & 0xff0f0000) == 0x56050000) { | ||
| 180 | u32 feat; | ||
| 181 | |||
| 182 | /* | ||
| 183 | * v5 CPUs with Tauros2 have the L2 cache enable bit | ||
| 184 | * located in the CPU Extra Features register. | ||
| 185 | */ | ||
| 186 | feat = read_extra_features(); | ||
| 187 | if (!(feat & 0x00400000)) { | ||
| 188 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); | ||
| 189 | write_extra_features(feat | 0x00400000); | ||
| 190 | } | ||
| 191 | |||
| 192 | mode = "ARMv5"; | ||
| 193 | outer_cache.inv_range = tauros2_inv_range; | ||
| 194 | outer_cache.clean_range = tauros2_clean_range; | ||
| 195 | outer_cache.flush_range = tauros2_flush_range; | ||
| 196 | } | ||
| 197 | #endif | ||
| 198 | |||
| 199 | #ifdef CONFIG_CPU_32v6 | ||
| 200 | /* | ||
| 201 | * Check whether this CPU lacks support for the v7 hierarchical | ||
| 202 | * cache ops. (PJ4 is in its v6 personality mode if the MMFR3 | ||
| 203 | * register indicates no support for the v7 hierarchical cache | ||
| 204 | * ops.) | ||
| 205 | */ | ||
| 206 | if (cpuid_scheme() && (read_mmfr3() & 0xf) == 0) { | ||
| 207 | /* | ||
| 208 | * When Tauros2 is used in an ARMv6 system, the L2 | ||
| 209 | * enable bit is in the ARMv6 ARM-mandated position | ||
| 210 | * (bit [26] of the System Control Register). | ||
| 211 | */ | ||
| 212 | if (!(get_cr() & 0x04000000)) { | ||
| 213 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); | ||
| 214 | adjust_cr(0x04000000, 0x04000000); | ||
| 215 | } | ||
| 216 | |||
| 217 | mode = "ARMv6"; | ||
| 218 | outer_cache.inv_range = tauros2_inv_range; | ||
| 219 | outer_cache.clean_range = tauros2_clean_range; | ||
| 220 | outer_cache.flush_range = tauros2_flush_range; | ||
| 221 | } | ||
| 222 | #endif | ||
| 223 | |||
| 224 | #ifdef CONFIG_CPU_32v7 | ||
| 225 | /* | ||
| 226 | * Check whether this CPU has support for the v7 hierarchical | ||
| 227 | * cache ops. (PJ4 is in its v7 personality mode if the MMFR3 | ||
| 228 | * register indicates support for the v7 hierarchical cache | ||
| 229 | * ops.) | ||
| 230 | * | ||
| 231 | * (Although strictly speaking there may exist CPUs that | ||
| 232 | * implement the v7 cache ops but are only ARMv6 CPUs (due to | ||
| 233 | * not complying with all of the other ARMv7 requirements), | ||
| 234 | * there are no real-life examples of Tauros2 being used on | ||
| 235 | * such CPUs as of yet.) | ||
| 236 | */ | ||
| 237 | if (cpuid_scheme() && (read_mmfr3() & 0xf) == 1) { | ||
| 238 | u32 actlr; | ||
| 239 | |||
| 240 | /* | ||
| 241 | * When Tauros2 is used in an ARMv7 system, the L2 | ||
| 242 | * enable bit is located in the Auxiliary System Control | ||
| 243 | * Register (which is the only register allowed by the | ||
| 244 | * ARMv7 spec to contain fine-grained cache control bits). | ||
| 245 | */ | ||
| 246 | actlr = read_actlr(); | ||
| 247 | if (!(actlr & 0x00000002)) { | ||
| 248 | printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); | ||
| 249 | write_actlr(actlr | 0x00000002); | ||
| 250 | } | ||
| 251 | |||
| 252 | mode = "ARMv7"; | ||
| 253 | } | ||
| 254 | #endif | ||
| 255 | |||
| 256 | if (mode == NULL) { | ||
| 257 | printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n"); | ||
| 258 | return; | ||
| 259 | } | ||
| 260 | |||
| 261 | printk(KERN_INFO "Tauros2: L2 cache support initialised " | ||
| 262 | "in %s mode.\n", mode); | ||
| 263 | } | ||
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 2427cdcd9098..8c7fbd19a4b3 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -881,7 +881,7 @@ void __init reserve_node_zero(pg_data_t *pgdat) | |||
| 881 | BOOTMEM_EXCLUSIVE); | 881 | BOOTMEM_EXCLUSIVE); |
| 882 | } | 882 | } |
| 883 | 883 | ||
| 884 | if (machine_is_treo680()) { | 884 | if (machine_is_treo680() || machine_is_centro()) { |
| 885 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, | 885 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, |
| 886 | BOOTMEM_EXCLUSIVE); | 886 | BOOTMEM_EXCLUSIVE); |
| 887 | reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, | 887 | reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, |
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 70f75d2e3ead..5485c821101c 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S | |||
| @@ -130,9 +130,16 @@ ENTRY(cpu_v6_set_pte_ext) | |||
| 130 | 130 | ||
| 131 | 131 | ||
| 132 | 132 | ||
| 133 | 133 | .type cpu_v6_name, #object | |
| 134 | cpu_v6_name: | 134 | cpu_v6_name: |
| 135 | .asciz "ARMv6-compatible processor" | 135 | .asciz "ARMv6-compatible processor" |
| 136 | .size cpu_v6_name, . - cpu_v6_name | ||
| 137 | |||
| 138 | .type cpu_pj4_name, #object | ||
| 139 | cpu_pj4_name: | ||
| 140 | .asciz "Marvell PJ4 processor" | ||
| 141 | .size cpu_pj4_name, . - cpu_pj4_name | ||
| 142 | |||
| 136 | .align | 143 | .align |
| 137 | 144 | ||
| 138 | __INIT | 145 | __INIT |
| @@ -241,3 +248,27 @@ __v6_proc_info: | |||
| 241 | .long v6_user_fns | 248 | .long v6_user_fns |
| 242 | .long v6_cache_fns | 249 | .long v6_cache_fns |
| 243 | .size __v6_proc_info, . - __v6_proc_info | 250 | .size __v6_proc_info, . - __v6_proc_info |
| 251 | |||
| 252 | .type __pj4_v6_proc_info, #object | ||
| 253 | __pj4_v6_proc_info: | ||
| 254 | .long 0x560f5810 | ||
| 255 | .long 0xff0ffff0 | ||
| 256 | .long PMD_TYPE_SECT | \ | ||
| 257 | PMD_SECT_BUFFERABLE | \ | ||
| 258 | PMD_SECT_CACHEABLE | \ | ||
| 259 | PMD_SECT_AP_WRITE | \ | ||
| 260 | PMD_SECT_AP_READ | ||
| 261 | .long PMD_TYPE_SECT | \ | ||
| 262 | PMD_SECT_XN | \ | ||
| 263 | PMD_SECT_AP_WRITE | \ | ||
| 264 | PMD_SECT_AP_READ | ||
| 265 | b __v6_setup | ||
| 266 | .long cpu_arch_name | ||
| 267 | .long cpu_elf_name | ||
| 268 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | ||
| 269 | .long cpu_pj4_name | ||
| 270 | .long v6_processor_functions | ||
| 271 | .long v6wbi_tlb_fns | ||
| 272 | .long v6_user_fns | ||
| 273 | .long v6_cache_fns | ||
| 274 | .size __pj4_v6_proc_info, . - __pj4_v6_proc_info | ||
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 2028f3702881..fab134e29826 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S | |||
| @@ -396,7 +396,7 @@ __xsc3_setup: | |||
| 396 | orr r4, r4, #0x18 @ cache the page table in L2 | 396 | orr r4, r4, #0x18 @ cache the page table in L2 |
| 397 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | 397 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer |
| 398 | 398 | ||
| 399 | mov r0, #0 @ don't allow CP access | 399 | mov r0, #1 << 6 @ cp6 access for early sched_clock |
| 400 | mcr p15, 0, r0, c15, c1, 0 @ write CP access register | 400 | mcr p15, 0, r0, c15, c1, 0 @ write CP access register |
| 401 | 401 | ||
| 402 | mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg | 402 | mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg |
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c index 8da95d57c21f..6c8a02ad98e3 100644 --- a/arch/arm/plat-iop/time.c +++ b/arch/arm/plat-iop/time.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/timex.h> | 20 | #include <linux/timex.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/clocksource.h> | ||
| 23 | #include <linux/clockchips.h> | ||
| 22 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 23 | #include <asm/irq.h> | 25 | #include <asm/irq.h> |
| 24 | #include <asm/uaccess.h> | 26 | #include <asm/uaccess.h> |
| @@ -26,45 +28,136 @@ | |||
| 26 | #include <asm/mach/time.h> | 28 | #include <asm/mach/time.h> |
| 27 | #include <mach/time.h> | 29 | #include <mach/time.h> |
| 28 | 30 | ||
| 31 | /* | ||
| 32 | * IOP clocksource (free-running timer 1). | ||
| 33 | */ | ||
| 34 | static cycle_t iop_clocksource_read(struct clocksource *unused) | ||
| 35 | { | ||
| 36 | return 0xffffffffu - read_tcr1(); | ||
| 37 | } | ||
| 38 | |||
| 39 | static struct clocksource iop_clocksource = { | ||
| 40 | .name = "iop_timer1", | ||
| 41 | .rating = 300, | ||
| 42 | .read = iop_clocksource_read, | ||
| 43 | .mask = CLOCKSOURCE_MASK(32), | ||
| 44 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz) | ||
| 48 | { | ||
| 49 | u64 temp; | ||
| 50 | u32 shift; | ||
| 51 | |||
| 52 | /* Find shift and mult values for hz. */ | ||
| 53 | shift = 32; | ||
| 54 | do { | ||
| 55 | temp = (u64) NSEC_PER_SEC << shift; | ||
| 56 | do_div(temp, hz); | ||
| 57 | if ((temp >> 32) == 0) | ||
| 58 | break; | ||
| 59 | } while (--shift != 0); | ||
| 60 | |||
| 61 | cs->shift = shift; | ||
| 62 | cs->mult = (u32) temp; | ||
| 63 | |||
| 64 | printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n", | ||
| 65 | cs->name, cs->shift, cs->mult); | ||
| 66 | } | ||
| 67 | |||
| 68 | /* | ||
| 69 | * IOP sched_clock() implementation via its clocksource. | ||
| 70 | */ | ||
| 71 | unsigned long long sched_clock(void) | ||
| 72 | { | ||
| 73 | cycle_t cyc = iop_clocksource_read(NULL); | ||
| 74 | struct clocksource *cs = &iop_clocksource; | ||
| 75 | |||
| 76 | return clocksource_cyc2ns(cyc, cs->mult, cs->shift); | ||
| 77 | } | ||
| 78 | |||
| 79 | /* | ||
| 80 | * IOP clockevents (interrupting timer 0). | ||
| 81 | */ | ||
| 82 | static int iop_set_next_event(unsigned long delta, | ||
| 83 | struct clock_event_device *unused) | ||
| 84 | { | ||
| 85 | u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1; | ||
| 86 | |||
| 87 | BUG_ON(delta == 0); | ||
| 88 | write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD)); | ||
| 89 | write_tcr0(delta); | ||
| 90 | write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN); | ||
| 91 | |||
| 92 | return 0; | ||
| 93 | } | ||
| 94 | |||
| 29 | static unsigned long ticks_per_jiffy; | 95 | static unsigned long ticks_per_jiffy; |
| 30 | static unsigned long ticks_per_usec; | ||
| 31 | static unsigned long next_jiffy_time; | ||
| 32 | 96 | ||
| 33 | unsigned long iop_gettimeoffset(void) | 97 | static void iop_set_mode(enum clock_event_mode mode, |
| 98 | struct clock_event_device *unused) | ||
| 34 | { | 99 | { |
| 35 | unsigned long offset, temp; | 100 | u32 tmr = read_tmr0(); |
| 101 | |||
| 102 | switch (mode) { | ||
| 103 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 104 | write_tmr0(tmr & ~IOP_TMR_EN); | ||
| 105 | write_tcr0(ticks_per_jiffy - 1); | ||
| 106 | tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN); | ||
| 107 | break; | ||
| 108 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 109 | /* ->set_next_event sets period and enables timer */ | ||
| 110 | tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN); | ||
| 111 | break; | ||
| 112 | case CLOCK_EVT_MODE_RESUME: | ||
| 113 | tmr |= IOP_TMR_EN; | ||
| 114 | break; | ||
| 115 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 116 | case CLOCK_EVT_MODE_UNUSED: | ||
| 117 | default: | ||
| 118 | tmr &= ~IOP_TMR_EN; | ||
| 119 | break; | ||
| 120 | } | ||
| 36 | 121 | ||
| 37 | /* enable cp6, if necessary, to avoid taking the overhead of an | 122 | write_tmr0(tmr); |
| 38 | * undefined instruction trap | 123 | } |
| 39 | */ | 124 | |
| 40 | asm volatile ( | 125 | static struct clock_event_device iop_clockevent = { |
| 41 | "mrc p15, 0, %0, c15, c1, 0\n\t" | 126 | .name = "iop_timer0", |
| 42 | "tst %0, #(1 << 6)\n\t" | 127 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 43 | "orreq %0, %0, #(1 << 6)\n\t" | 128 | .rating = 300, |
| 44 | "mcreq p15, 0, %0, c15, c1, 0\n\t" | 129 | .set_next_event = iop_set_next_event, |
| 45 | #ifdef CONFIG_CPU_XSCALE | 130 | .set_mode = iop_set_mode, |
| 46 | "mrceq p15, 0, %0, c15, c1, 0\n\t" | 131 | }; |
| 47 | "moveq %0, %0\n\t" | 132 | |
| 48 | "subeq pc, pc, #4\n\t" | 133 | static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz) |
| 49 | #endif | 134 | { |
| 50 | : "=r"(temp) : : "cc"); | 135 | u64 temp; |
| 51 | 136 | u32 shift; | |
| 52 | offset = next_jiffy_time - read_tcr1(); | 137 | |
| 53 | 138 | /* Find shift and mult values for hz. */ | |
| 54 | return offset / ticks_per_usec; | 139 | shift = 32; |
| 140 | do { | ||
| 141 | temp = (u64) hz << shift; | ||
| 142 | do_div(temp, NSEC_PER_SEC); | ||
| 143 | if ((temp >> 32) == 0) | ||
| 144 | break; | ||
| 145 | } while (--shift != 0); | ||
| 146 | |||
| 147 | ce->shift = shift; | ||
| 148 | ce->mult = (u32) temp; | ||
| 149 | |||
| 150 | printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n", | ||
| 151 | ce->name, ce->shift, ce->mult); | ||
| 55 | } | 152 | } |
| 56 | 153 | ||
| 57 | static irqreturn_t | 154 | static irqreturn_t |
| 58 | iop_timer_interrupt(int irq, void *dev_id) | 155 | iop_timer_interrupt(int irq, void *dev_id) |
| 59 | { | 156 | { |
| 60 | write_tisr(1); | 157 | struct clock_event_device *evt = dev_id; |
| 61 | |||
| 62 | while ((signed long)(next_jiffy_time - read_tcr1()) | ||
| 63 | >= ticks_per_jiffy) { | ||
| 64 | timer_tick(); | ||
| 65 | next_jiffy_time -= ticks_per_jiffy; | ||
| 66 | } | ||
| 67 | 158 | ||
| 159 | write_tisr(1); | ||
| 160 | evt->event_handler(evt); | ||
| 68 | return IRQ_HANDLED; | 161 | return IRQ_HANDLED; |
| 69 | } | 162 | } |
| 70 | 163 | ||
| @@ -72,6 +165,7 @@ static struct irqaction iop_timer_irq = { | |||
| 72 | .name = "IOP Timer Tick", | 165 | .name = "IOP Timer Tick", |
| 73 | .handler = iop_timer_interrupt, | 166 | .handler = iop_timer_interrupt, |
| 74 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 167 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 168 | .dev_id = &iop_clockevent, | ||
| 75 | }; | 169 | }; |
| 76 | 170 | ||
| 77 | static unsigned long iop_tick_rate; | 171 | static unsigned long iop_tick_rate; |
| @@ -86,21 +180,33 @@ void __init iop_init_time(unsigned long tick_rate) | |||
| 86 | u32 timer_ctl; | 180 | u32 timer_ctl; |
| 87 | 181 | ||
| 88 | ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); | 182 | ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); |
| 89 | ticks_per_usec = tick_rate / 1000000; | ||
| 90 | next_jiffy_time = 0xffffffff; | ||
| 91 | iop_tick_rate = tick_rate; | 183 | iop_tick_rate = tick_rate; |
| 92 | 184 | ||
| 93 | timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | | 185 | timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | |
| 94 | IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; | 186 | IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; |
| 95 | 187 | ||
| 96 | /* | 188 | /* |
| 97 | * We use timer 0 for our timer interrupt, and timer 1 as | 189 | * Set up interrupting clockevent timer 0. |
| 98 | * monotonic counter for tracking missed jiffies. | ||
| 99 | */ | 190 | */ |
| 191 | write_tmr0(timer_ctl & ~IOP_TMR_EN); | ||
| 192 | setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); | ||
| 193 | iop_clockevent_set_hz(&iop_clockevent, tick_rate); | ||
| 194 | iop_clockevent.max_delta_ns = | ||
| 195 | clockevent_delta2ns(0xfffffffe, &iop_clockevent); | ||
| 196 | iop_clockevent.min_delta_ns = | ||
| 197 | clockevent_delta2ns(0xf, &iop_clockevent); | ||
| 198 | iop_clockevent.cpumask = cpumask_of(0); | ||
| 199 | clockevents_register_device(&iop_clockevent); | ||
| 100 | write_trr0(ticks_per_jiffy - 1); | 200 | write_trr0(ticks_per_jiffy - 1); |
| 201 | write_tcr0(ticks_per_jiffy - 1); | ||
| 101 | write_tmr0(timer_ctl); | 202 | write_tmr0(timer_ctl); |
| 203 | |||
| 204 | /* | ||
| 205 | * Set up free-running clocksource timer 1. | ||
| 206 | */ | ||
| 102 | write_trr1(0xffffffff); | 207 | write_trr1(0xffffffff); |
| 208 | write_tcr1(0xffffffff); | ||
| 103 | write_tmr1(timer_ctl); | 209 | write_tmr1(timer_ctl); |
| 104 | 210 | iop_clocksource_set_hz(&iop_clocksource, tick_rate); | |
| 105 | setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); | 211 | clocksource_register(&iop_clocksource); |
| 106 | } | 212 | } |
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index ca5c7c226341..8b0a1ee039fa 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -69,10 +69,20 @@ config MXC_PWM | |||
| 69 | help | 69 | help |
| 70 | Enable support for the i.MX PWM controller(s). | 70 | Enable support for the i.MX PWM controller(s). |
| 71 | 71 | ||
| 72 | config MXC_ULPI | ||
| 73 | bool | ||
| 74 | |||
| 72 | config ARCH_HAS_RNGA | 75 | config ARCH_HAS_RNGA |
| 73 | bool | 76 | bool |
| 74 | depends on ARCH_MXC | 77 | depends on ARCH_MXC |
| 75 | 78 | ||
| 76 | config ARCH_MXC_IOMUX_V3 | 79 | config ARCH_MXC_IOMUX_V3 |
| 77 | bool | 80 | bool |
| 81 | |||
| 82 | config ARCH_MXC_AUDMUX_V1 | ||
| 83 | bool | ||
| 84 | |||
| 85 | config ARCH_MXC_AUDMUX_V2 | ||
| 86 | bool | ||
| 87 | |||
| 78 | endif | 88 | endif |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index e3212c8ff421..4cbca9da1505 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o | |||
| 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o | 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o |
| 10 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o | 10 | obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o |
| 11 | obj-$(CONFIG_MXC_PWM) += pwm.o | 11 | obj-$(CONFIG_MXC_PWM) += pwm.o |
| 12 | obj-$(CONFIG_MXC_ULPI) += ulpi.o | ||
| 13 | obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o | ||
| 14 | obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o | ||
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c new file mode 100644 index 000000000000..da6387dcdf21 --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v1.c | |||
| @@ -0,0 +1,58 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * Initial development of this code was funded by | ||
| 5 | * Phytec Messtechnik GmbH, http://www.phytec.de | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/module.h> | ||
| 23 | #include <linux/err.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/clk.h> | ||
| 26 | #include <mach/audmux.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | |||
| 29 | static void __iomem *audmux_base; | ||
| 30 | |||
| 31 | static unsigned char port_mapping[] = { | ||
| 32 | 0x0, 0x4, 0x8, 0x10, 0x14, 0x1c, | ||
| 33 | }; | ||
| 34 | |||
| 35 | int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr) | ||
| 36 | { | ||
| 37 | if (!audmux_base) { | ||
| 38 | printk("%s: not configured\n", __func__); | ||
| 39 | return -ENOSYS; | ||
| 40 | } | ||
| 41 | |||
| 42 | if (port >= ARRAY_SIZE(port_mapping)) | ||
| 43 | return -EINVAL; | ||
| 44 | |||
| 45 | writel(pcr, audmux_base + port_mapping[port]); | ||
| 46 | |||
| 47 | return 0; | ||
| 48 | } | ||
| 49 | EXPORT_SYMBOL_GPL(mxc_audmux_v1_configure_port); | ||
| 50 | |||
| 51 | static int mxc_audmux_v1_init(void) | ||
| 52 | { | ||
| 53 | if (cpu_is_mx27() || cpu_is_mx21()) | ||
| 54 | audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); | ||
| 55 | return 0; | ||
| 56 | } | ||
| 57 | |||
| 58 | postcore_initcall(mxc_audmux_v1_init); | ||
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c new file mode 100644 index 000000000000..6f21096086fd --- /dev/null +++ b/arch/arm/plat-mxc/audmux-v2.c | |||
| @@ -0,0 +1,74 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | ||
| 3 | * | ||
| 4 | * Initial development of this code was funded by | ||
| 5 | * Phytec Messtechnik GmbH, http://www.phytec.de | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | */ | ||
| 21 | |||
| 22 | #include <linux/module.h> | ||
| 23 | #include <linux/err.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/clk.h> | ||
| 26 | #include <mach/audmux.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | |||
| 29 | static struct clk *audmux_clk; | ||
| 30 | static void __iomem *audmux_base; | ||
| 31 | |||
| 32 | #define MXC_AUDMUX_V2_PTCR(x) ((x) * 8) | ||
| 33 | #define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4) | ||
| 34 | |||
| 35 | int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, | ||
| 36 | unsigned int pdcr) | ||
| 37 | { | ||
| 38 | if (!audmux_base) | ||
| 39 | return -ENOSYS; | ||
| 40 | |||
| 41 | if (audmux_clk) | ||
| 42 | clk_enable(audmux_clk); | ||
| 43 | |||
| 44 | writel(ptcr, audmux_base + MXC_AUDMUX_V2_PTCR(port)); | ||
| 45 | writel(pdcr, audmux_base + MXC_AUDMUX_V2_PDCR(port)); | ||
| 46 | |||
| 47 | if (audmux_clk) | ||
| 48 | clk_disable(audmux_clk); | ||
| 49 | |||
| 50 | return 0; | ||
| 51 | } | ||
| 52 | EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port); | ||
| 53 | |||
| 54 | static int mxc_audmux_v2_init(void) | ||
| 55 | { | ||
| 56 | int ret; | ||
| 57 | |||
| 58 | if (cpu_is_mx35()) { | ||
| 59 | audmux_clk = clk_get(NULL, "audmux"); | ||
| 60 | if (IS_ERR(audmux_clk)) { | ||
| 61 | ret = PTR_ERR(audmux_clk); | ||
| 62 | printk(KERN_ERR "%s: cannot get clock: %d\n", __func__, | ||
| 63 | ret); | ||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | } | ||
| 67 | |||
| 68 | if (cpu_is_mx31() || cpu_is_mx35()) | ||
| 69 | audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR); | ||
| 70 | |||
| 71 | return 0; | ||
| 72 | } | ||
| 73 | |||
| 74 | postcore_initcall(mxc_audmux_v2_init); | ||
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 77646436c00e..9c1b3f9c4f4d 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c | |||
| @@ -156,7 +156,8 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg) | |||
| 156 | } | 156 | } |
| 157 | 157 | ||
| 158 | now = min(imxdma->resbytes, sg->length); | 158 | now = min(imxdma->resbytes, sg->length); |
| 159 | imxdma->resbytes -= now; | 159 | if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP) |
| 160 | imxdma->resbytes -= now; | ||
| 160 | 161 | ||
| 161 | if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) | 162 | if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) |
| 162 | __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); | 163 | __raw_writel(sg->dma_address, DMA_BASE + DMA_DAR(channel)); |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index cfc4a8b43e6a..d65ebe303b9f 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
| @@ -282,7 +282,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
| 282 | for (j = port[i].virtual_irq_start; | 282 | for (j = port[i].virtual_irq_start; |
| 283 | j < port[i].virtual_irq_start + 32; j++) { | 283 | j < port[i].virtual_irq_start + 32; j++) { |
| 284 | set_irq_chip(j, &gpio_irq_chip); | 284 | set_irq_chip(j, &gpio_irq_chip); |
| 285 | set_irq_handler(j, handle_edge_irq); | 285 | set_irq_handler(j, handle_level_irq); |
| 286 | set_irq_flags(j, IRQF_VALID); | 286 | set_irq_flags(j, IRQF_VALID); |
| 287 | } | 287 | } |
| 288 | 288 | ||
diff --git a/arch/arm/plat-mxc/include/mach/audmux.h b/arch/arm/plat-mxc/include/mach/audmux.h new file mode 100644 index 000000000000..5cd6466964af --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/audmux.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | #ifndef __MACH_AUDMUX_H | ||
| 2 | #define __MACH_AUDMUX_H | ||
| 3 | |||
| 4 | #define MX27_AUDMUX_HPCR1_SSI0 0 | ||
| 5 | #define MX27_AUDMUX_HPCR2_SSI1 1 | ||
| 6 | #define MX27_AUDMUX_HPCR3_SSI_PINS_4 2 | ||
| 7 | #define MX27_AUDMUX_PPCR1_SSI_PINS_1 3 | ||
| 8 | #define MX27_AUDMUX_PPCR2_SSI_PINS_2 4 | ||
| 9 | #define MX27_AUDMUX_PPCR3_SSI_PINS_3 5 | ||
| 10 | |||
| 11 | #define MX31_AUDMUX_PORT1_SSI0 0 | ||
| 12 | #define MX31_AUDMUX_PORT2_SSI1 1 | ||
| 13 | #define MX31_AUDMUX_PORT3_SSI_PINS_3 2 | ||
| 14 | #define MX31_AUDMUX_PORT4_SSI_PINS_4 3 | ||
| 15 | #define MX31_AUDMUX_PORT5_SSI_PINS_5 4 | ||
| 16 | #define MX31_AUDMUX_PORT6_SSI_PINS_6 5 | ||
| 17 | |||
| 18 | /* Register definitions for the i.MX21/27 Digital Audio Multiplexer */ | ||
| 19 | #define MXC_AUDMUX_V1_PCR_INMMASK(x) ((x) & 0xff) | ||
| 20 | #define MXC_AUDMUX_V1_PCR_INMEN (1 << 8) | ||
| 21 | #define MXC_AUDMUX_V1_PCR_TXRXEN (1 << 10) | ||
| 22 | #define MXC_AUDMUX_V1_PCR_SYN (1 << 12) | ||
| 23 | #define MXC_AUDMUX_V1_PCR_RXDSEL(x) (((x) & 0x7) << 13) | ||
| 24 | #define MXC_AUDMUX_V1_PCR_RFCSEL(x) (((x) & 0xf) << 20) | ||
| 25 | #define MXC_AUDMUX_V1_PCR_RCLKDIR (1 << 24) | ||
| 26 | #define MXC_AUDMUX_V1_PCR_RFSDIR (1 << 25) | ||
| 27 | #define MXC_AUDMUX_V1_PCR_TFCSEL(x) (((x) & 0xf) << 26) | ||
| 28 | #define MXC_AUDMUX_V1_PCR_TCLKDIR (1 << 30) | ||
| 29 | #define MXC_AUDMUX_V1_PCR_TFSDIR (1 << 31) | ||
| 30 | |||
| 31 | /* Register definitions for the i.MX25/31/35 Digital Audio Multiplexer */ | ||
| 32 | #define MXC_AUDMUX_V2_PTCR_TFSDIR (1 << 31) | ||
| 33 | #define MXC_AUDMUX_V2_PTCR_TFSEL(x) (((x) & 0xf) << 27) | ||
| 34 | #define MXC_AUDMUX_V2_PTCR_TCLKDIR (1 << 26) | ||
| 35 | #define MXC_AUDMUX_V2_PTCR_TCSEL(x) (((x) & 0xf) << 22) | ||
| 36 | #define MXC_AUDMUX_V2_PTCR_RFSDIR (1 << 21) | ||
| 37 | #define MXC_AUDMUX_V2_PTCR_RFSEL(x) (((x) & 0xf) << 17) | ||
| 38 | #define MXC_AUDMUX_V2_PTCR_RCLKDIR (1 << 16) | ||
| 39 | #define MXC_AUDMUX_V2_PTCR_RCSEL(x) (((x) & 0xf) << 12) | ||
| 40 | #define MXC_AUDMUX_V2_PTCR_SYN (1 << 11) | ||
| 41 | |||
| 42 | #define MXC_AUDMUX_V2_PDCR_RXDSEL(x) (((x) & 0x7) << 13) | ||
| 43 | #define MXC_AUDMUX_V2_PDCR_TXRXEN (1 << 12) | ||
| 44 | #define MXC_AUDMUX_V2_PDCR_MODE(x) (((x) & 0x3) << 8) | ||
| 45 | #define MXC_AUDMUX_V2_PDCR_INMMASK(x) ((x) & 0xff) | ||
| 46 | |||
| 47 | int mxc_audmux_v1_configure_port(unsigned int port, unsigned int pcr); | ||
| 48 | |||
| 49 | int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr, | ||
| 50 | unsigned int pdcr); | ||
| 51 | |||
| 52 | #endif /* __MACH_AUDMUX_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h new file mode 100644 index 000000000000..05ff2f31ef1f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 17 | */ | ||
| 18 | #ifndef __ARM_ARCH_BOARD_KZM_ARM11_H | ||
| 19 | #define __ARM_ARCH_BOARD_KZM_ARM11_H | ||
| 20 | |||
| 21 | /* | ||
| 22 | * KZM-ARM11-01 Board Control Registers on FPGA | ||
| 23 | */ | ||
| 24 | #define KZM_ARM11_CTL1 (CS4_BASE_ADDR + 0x1000) | ||
| 25 | #define KZM_ARM11_CTL2 (CS4_BASE_ADDR + 0x1001) | ||
| 26 | #define KZM_ARM11_RSW1 (CS4_BASE_ADDR + 0x1002) | ||
| 27 | #define KZM_ARM11_BACK_LIGHT (CS4_BASE_ADDR + 0x1004) | ||
| 28 | #define KZM_ARM11_FPGA_REV (CS4_BASE_ADDR + 0x1008) | ||
| 29 | #define KZM_ARM11_7SEG_LED (CS4_BASE_ADDR + 0x1010) | ||
| 30 | #define KZM_ARM11_LEDS (CS4_BASE_ADDR + 0x1020) | ||
| 31 | #define KZM_ARM11_DIPSW2 (CS4_BASE_ADDR + 0x1003) | ||
| 32 | |||
| 33 | /* | ||
| 34 | * External UART for touch panel on FPGA | ||
| 35 | */ | ||
| 36 | #define KZM_ARM11_16550 (CS4_BASE_ADDR + 0x1050) | ||
| 37 | |||
| 38 | #endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */ | ||
| 39 | |||
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h index 8e64325d6905..0184b638c268 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h | |||
| @@ -1,15 +1,42 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> | ||
| 4 | * | ||
| 5 | * Based on code for mobots boards, | ||
| 6 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 20 | * MA 02110-1301, USA. | ||
| 3 | */ | 21 | */ |
| 4 | 22 | ||
| 23 | #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | ||
| 24 | #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | ||
| 25 | |||
| 26 | #ifndef __ASSEMBLY__ | ||
| 27 | |||
| 28 | enum mx31lilly_boards { | ||
| 29 | MX31LITE_NOBOARD = 0, | ||
| 30 | MX31LITE_DB = 1, | ||
| 31 | }; | ||
| 32 | |||
| 5 | /* | 33 | /* |
| 6 | * This program is free software; you can redistribute it and/or modify | 34 | * This CPU module needs a baseboard to work. After basic initializing |
| 7 | * it under the terms of the GNU General Public License version 2 as | 35 | * its own devices, it calls baseboard's init function. |
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | 36 | */ |
| 10 | 37 | ||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | 38 | extern void mx31lite_db_init(void); |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__ | ||
| 13 | 39 | ||
| 14 | #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ | 40 | #endif |
| 15 | 41 | ||
| 42 | #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h index b3876cc238ca..07be8ad7ec37 100644 --- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h +++ b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h | |||
| @@ -58,6 +58,14 @@ imx_dma_setup_single(int channel, dma_addr_t dma_address, | |||
| 58 | unsigned int dma_length, unsigned int dev_addr, | 58 | unsigned int dma_length, unsigned int dev_addr, |
| 59 | unsigned int dmamode); | 59 | unsigned int dmamode); |
| 60 | 60 | ||
| 61 | |||
| 62 | /* | ||
| 63 | * Use this flag as the dma_length argument to imx_dma_setup_sg() | ||
| 64 | * to create an endless running dma loop. The end of the scatterlist | ||
| 65 | * must be linked to the beginning for this to work. | ||
| 66 | */ | ||
| 67 | #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1) | ||
| 68 | |||
| 61 | int | 69 | int |
| 62 | imx_dma_setup_sg(int channel, struct scatterlist *sg, | 70 | imx_dma_setup_sg(int channel, struct scatterlist *sg, |
| 63 | unsigned int sgcount, unsigned int dma_length, | 71 | unsigned int sgcount, unsigned int dma_length, |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 446f86763816..eaabd4e96925 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h | |||
| @@ -524,10 +524,18 @@ enum iomux_pins { | |||
| 524 | #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) | 524 | #define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC) |
| 525 | #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) | 525 | #define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC) |
| 526 | #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) | 526 | #define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC) |
| 527 | #define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC) | ||
| 528 | #define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC) | ||
| 529 | #define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC) | ||
| 530 | #define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC) | ||
| 527 | #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) | 531 | #define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC) |
| 528 | #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) | 532 | #define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC) |
| 529 | #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) | 533 | #define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC) |
| 530 | #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) | 534 | #define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC) |
| 535 | #define MX31_PIN_DCD_DTE1__DCD_DTE2 IOMUX_MODE(MX31_PIN_DCD_DTE1, IOMUX_CONFIG_ALT1) | ||
| 536 | #define MX31_PIN_RI_DTE1__RI_DTE2 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_ALT1) | ||
| 537 | #define MX31_PIN_DSR_DTE1__DSR_DTE2 IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_ALT1) | ||
| 538 | #define MX31_PIN_DTR_DTE1__DTR_DTE2 IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_OCONFIG_ALT3 | IOMUX_ICONFIG_NONE) | ||
| 531 | #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) | 539 | #define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2) |
| 532 | #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) | 540 | #define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2) |
| 533 | #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) | 541 | #define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2) |
| @@ -623,6 +631,8 @@ enum iomux_pins { | |||
| 623 | #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) | 631 | #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) |
| 624 | #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) | 632 | #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) |
| 625 | #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) | 633 | #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) |
| 634 | #define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) | ||
| 635 | #define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) | ||
| 626 | #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) | 636 | #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) |
| 627 | #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) | 637 | #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) |
| 628 | #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) | 638 | #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) |
| @@ -642,12 +652,22 @@ enum iomux_pins { | |||
| 642 | #define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) | 652 | #define MX31_PIN_CSPI1_SS2__USBH1_RCV IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_ALT1) |
| 643 | #define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) | 653 | #define MX31_PIN_CSPI1_SCLK__USBH1_OEB IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1) |
| 644 | #define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) | 654 | #define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1) |
| 655 | #define MX31_PIN_SFS6__USBH1_SUSPEND IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_FUNC) | ||
| 656 | #define MX31_PIN_NFRE_B__GPIO1_11 IOMUX_MODE(MX31_PIN_NFRE_B, IOMUX_CONFIG_GPIO) | ||
| 657 | #define MX31_PIN_NFALE__GPIO1_12 IOMUX_MODE(MX31_PIN_NFALE, IOMUX_CONFIG_GPIO) | ||
| 645 | #define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) | 658 | #define MX31_PIN_USBH2_DATA0__USBH2_DATA0 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC) |
| 646 | #define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) | 659 | #define MX31_PIN_USBH2_DATA1__USBH2_DATA1 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC) |
| 660 | #define MX31_PIN_STXD3__USBH2_DATA2 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC) | ||
| 661 | #define MX31_PIN_SRXD3__USBH2_DATA3 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC) | ||
| 662 | #define MX31_PIN_SCK3__USBH2_DATA4 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC) | ||
| 663 | #define MX31_PIN_SFS3__USBH2_DATA5 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC) | ||
| 664 | #define MX31_PIN_STXD6__USBH2_DATA6 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC) | ||
| 665 | #define MX31_PIN_SRXD6__USBH2_DATA7 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC) | ||
| 647 | #define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) | 666 | #define MX31_PIN_USBH2_CLK__USBH2_CLK IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC) |
| 648 | #define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) | 667 | #define MX31_PIN_USBH2_DIR__USBH2_DIR IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC) |
| 649 | #define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) | 668 | #define MX31_PIN_USBH2_NXT__USBH2_NXT IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC) |
| 650 | #define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) | 669 | #define MX31_PIN_USBH2_STP__USBH2_STP IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC) |
| 670 | #define MX31_PIN_SCK6__GPIO1_25 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO) | ||
| 651 | #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) | 671 | #define MX31_PIN_USB_OC__GPIO1_30 IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO) |
| 652 | #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) | 672 | #define MX31_PIN_I2C_DAT__I2C1_SDA IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC) |
| 653 | #define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) | 673 | #define MX31_PIN_I2C_CLK__I2C1_SCL IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC) |
| @@ -693,7 +713,19 @@ enum iomux_pins { | |||
| 693 | #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) | 713 | #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) |
| 694 | #define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) | 714 | #define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) |
| 695 | #define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) | 715 | #define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) |
| 696 | 716 | #define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) | |
| 717 | #define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) | ||
| 718 | #define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) | ||
| 719 | #define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) | ||
| 720 | #define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) | ||
| 721 | #define MX31_PIN_STXD4__STXD4 IOMUX_MODE(MX31_PIN_STXD4, IOMUX_CONFIG_FUNC) | ||
| 722 | #define MX31_PIN_SRXD4__SRXD4 IOMUX_MODE(MX31_PIN_SRXD4, IOMUX_CONFIG_FUNC) | ||
| 723 | #define MX31_PIN_SCK4__SCK4 IOMUX_MODE(MX31_PIN_SCK4, IOMUX_CONFIG_FUNC) | ||
| 724 | #define MX31_PIN_SFS4__SFS4 IOMUX_MODE(MX31_PIN_SFS4, IOMUX_CONFIG_FUNC) | ||
| 725 | #define MX31_PIN_STXD5__STXD5 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_FUNC) | ||
| 726 | #define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) | ||
| 727 | #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) | ||
| 728 | #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) | ||
| 697 | 729 | ||
| 698 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 | 730 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 |
| 699 | * cspi1_ss1*/ | 731 | * cspi1_ss1*/ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index a0fa40265468..1deda0184892 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h | |||
| @@ -88,9 +88,7 @@ struct pad_desc { | |||
| 88 | #define PAD_CTL_SRE_FAST (1 << 0) | 88 | #define PAD_CTL_SRE_FAST (1 << 0) |
| 89 | 89 | ||
| 90 | /* | 90 | /* |
| 91 | * setups a single pad: | 91 | * setups a single pad in the iomuxer |
| 92 | * - reserves the pad so that it is not claimed by another driver | ||
| 93 | * - setups the iomux according to the configuration | ||
| 94 | */ | 92 | */ |
| 95 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad); | 93 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad); |
| 96 | 94 | ||
| @@ -101,19 +99,6 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad); | |||
| 101 | int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); | 99 | int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); |
| 102 | 100 | ||
| 103 | /* | 101 | /* |
| 104 | * releases a single pad: | ||
| 105 | * - make it available for a future use by another driver | ||
| 106 | * - DOES NOT reconfigure the IOMUX in its reset state | ||
| 107 | */ | ||
| 108 | void mxc_iomux_v3_release_pad(struct pad_desc *pad); | ||
| 109 | |||
| 110 | /* | ||
| 111 | * releases multiple pads | ||
| 112 | * convenvient way to call the above function with tables | ||
| 113 | */ | ||
| 114 | void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); | ||
| 115 | |||
| 116 | /* | ||
| 117 | * Initialise the iomux controller | 102 | * Initialise the iomux controller |
| 118 | */ | 103 | */ |
| 119 | void mxc_iomux_v3_init(void __iomem *iomux_v3_base); | 104 | void mxc_iomux_v3_init(void __iomem *iomux_v3_base); |
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h index 6d49f8ae3259..011cfcd8b820 100644 --- a/arch/arm/plat-mxc/include/mach/iomux.h +++ b/arch/arm/plat-mxc/include/mach/iomux.h | |||
| @@ -123,6 +123,7 @@ | |||
| 123 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | 123 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) |
| 124 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | 124 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) |
| 125 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) | 125 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) |
| 126 | #define IRQ_GPIOF(x) (IRQ_GPIOE(32) + x) | ||
| 126 | 127 | ||
| 127 | 128 | ||
| 128 | extern void mxc_gpio_mode(int gpio_mode); | 129 | extern void mxc_gpio_mode(int gpio_mode); |
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h index 21112c695ec5..bb297d8765a7 100644 --- a/arch/arm/plat-mxc/include/mach/mx21.h +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
| @@ -25,46 +25,191 @@ | |||
| 25 | #ifndef __ASM_ARCH_MXC_MX21_H__ | 25 | #ifndef __ASM_ARCH_MXC_MX21_H__ |
| 26 | #define __ASM_ARCH_MXC_MX21_H__ | 26 | #define __ASM_ARCH_MXC_MX21_H__ |
| 27 | 27 | ||
| 28 | #define MX21_AIPI_BASE_ADDR 0x10000000 | ||
| 29 | #define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000 | ||
| 30 | #define MX21_AIPI_SIZE SZ_1M | ||
| 31 | #define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) | ||
| 32 | #define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) | ||
| 33 | #define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000) | ||
| 34 | #define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000) | ||
| 35 | #define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000) | ||
| 36 | #define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000) | ||
| 37 | #define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000) | ||
| 38 | #define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000) | ||
| 39 | #define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000) | ||
| 40 | #define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000) | ||
| 41 | #define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000) | ||
| 42 | #define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000) | ||
| 43 | #define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000) | ||
| 44 | #define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000) | ||
| 45 | #define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000) | ||
| 46 | #define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000) | ||
| 47 | #define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000) | ||
| 48 | #define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000) | ||
| 49 | #define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) | ||
| 50 | #define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) | ||
| 51 | #define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) | ||
| 52 | #define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) | ||
| 53 | #define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) | ||
| 54 | #define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) | ||
| 55 | #define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000) | ||
| 56 | #define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000) | ||
| 57 | #define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000) | ||
| 58 | #define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400) | ||
| 59 | #define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000) | ||
| 60 | #define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800) | ||
| 61 | #define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000) | ||
| 62 | #define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000) | ||
| 63 | |||
| 64 | #define MX21_AVIC_BASE_ADDR 0x10040000 | ||
| 65 | |||
| 66 | #define MX21_SAHB1_BASE_ADDR 0x80000000 | ||
| 67 | #define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
| 68 | #define MX21_SAHB1_SIZE SZ_1M | ||
| 69 | #define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) | ||
| 70 | |||
| 28 | /* Memory regions and CS */ | 71 | /* Memory regions and CS */ |
| 29 | #define SDRAM_BASE_ADDR 0xC0000000 | 72 | #define MX21_SDRAM_BASE_ADDR 0xc0000000 |
| 30 | #define CSD1_BASE_ADDR 0xC4000000 | 73 | #define MX21_CSD1_BASE_ADDR 0xc4000000 |
| 31 | 74 | ||
| 32 | #define CS0_BASE_ADDR 0xC8000000 | 75 | #define MX21_CS0_BASE_ADDR 0xc8000000 |
| 33 | #define CS1_BASE_ADDR 0xCC000000 | 76 | #define MX21_CS1_BASE_ADDR 0xcc000000 |
| 34 | #define CS2_BASE_ADDR 0xD0000000 | 77 | #define MX21_CS2_BASE_ADDR 0xd0000000 |
| 35 | #define CS3_BASE_ADDR 0xD1000000 | 78 | #define MX21_CS3_BASE_ADDR 0xd1000000 |
| 36 | #define CS4_BASE_ADDR 0xD2000000 | 79 | #define MX21_CS4_BASE_ADDR 0xd2000000 |
| 37 | #define CS5_BASE_ADDR 0xDD000000 | 80 | #define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000 |
| 38 | #define PCMCIA_MEM_BASE_ADDR 0xD4000000 | 81 | #define MX21_CS5_BASE_ADDR 0xdd000000 |
| 39 | 82 | ||
| 40 | /* NAND, SDRAM, WEIM etc controllers */ | 83 | /* NAND, SDRAM, WEIM etc controllers */ |
| 41 | #define X_MEMC_BASE_ADDR 0xDF000000 | 84 | #define MX21_X_MEMC_BASE_ADDR 0xdf000000 |
| 42 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | 85 | #define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000 |
| 43 | #define X_MEMC_SIZE SZ_256K | 86 | #define MX21_X_MEMC_SIZE SZ_256K |
| 44 | 87 | ||
| 45 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | 88 | #define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) |
| 46 | #define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | 89 | #define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000) |
| 47 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | 90 | #define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000) |
| 48 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | 91 | #define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000) |
| 49 | 92 | ||
| 50 | #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ | 93 | #define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ |
| 51 | 94 | ||
| 52 | /* fixed interrupt numbers */ | 95 | /* fixed interrupt numbers */ |
| 53 | #define MXC_INT_USBCTRL 58 | 96 | #define MX21_INT_CSPI3 6 |
| 54 | #define MXC_INT_USBCTRL 58 | 97 | #define MX21_INT_GPIO 8 |
| 55 | #define MXC_INT_USBMNP 57 | 98 | #define MX21_INT_FIRI 9 |
| 56 | #define MXC_INT_USBFUNC 56 | 99 | #define MX21_INT_SDHC2 10 |
| 57 | #define MXC_INT_USBHOST 55 | 100 | #define MX21_INT_SDHC1 11 |
| 58 | #define MXC_INT_USBDMA 54 | 101 | #define MX21_INT_I2C 12 |
| 59 | #define MXC_INT_USBWKUP 53 | 102 | #define MX21_INT_SSI2 13 |
| 60 | #define MXC_INT_EMMADEC 50 | 103 | #define MX21_INT_SSI1 14 |
| 61 | #define MXC_INT_EMMAENC 49 | 104 | #define MX21_INT_CSPI2 15 |
| 62 | #define MXC_INT_BMI 30 | 105 | #define MX21_INT_CSPI1 16 |
| 63 | #define MXC_INT_FIRI 9 | 106 | #define MX21_INT_UART4 17 |
| 107 | #define MX21_INT_UART3 18 | ||
| 108 | #define MX21_INT_UART2 19 | ||
| 109 | #define MX21_INT_UART1 20 | ||
| 110 | #define MX21_INT_KPP 21 | ||
| 111 | #define MX21_INT_RTC 22 | ||
| 112 | #define MX21_INT_PWM 23 | ||
| 113 | #define MX21_INT_GPT3 24 | ||
| 114 | #define MX21_INT_GPT2 25 | ||
| 115 | #define MX21_INT_GPT1 26 | ||
| 116 | #define MX21_INT_WDOG 27 | ||
| 117 | #define MX21_INT_PCMCIA 28 | ||
| 118 | #define MX21_INT_NANDFC 29 | ||
| 119 | #define MX21_INT_BMI 30 | ||
| 120 | #define MX21_INT_CSI 31 | ||
| 121 | #define MX21_INT_DMACH0 32 | ||
| 122 | #define MX21_INT_DMACH1 33 | ||
| 123 | #define MX21_INT_DMACH2 34 | ||
| 124 | #define MX21_INT_DMACH3 35 | ||
| 125 | #define MX21_INT_DMACH4 36 | ||
| 126 | #define MX21_INT_DMACH5 37 | ||
| 127 | #define MX21_INT_DMACH6 38 | ||
| 128 | #define MX21_INT_DMACH7 39 | ||
| 129 | #define MX21_INT_DMACH8 40 | ||
| 130 | #define MX21_INT_DMACH9 41 | ||
| 131 | #define MX21_INT_DMACH10 42 | ||
| 132 | #define MX21_INT_DMACH11 43 | ||
| 133 | #define MX21_INT_DMACH12 44 | ||
| 134 | #define MX21_INT_DMACH13 45 | ||
| 135 | #define MX21_INT_DMACH14 46 | ||
| 136 | #define MX21_INT_DMACH15 47 | ||
| 137 | #define MX21_INT_EMMAENC 49 | ||
| 138 | #define MX21_INT_EMMADEC 50 | ||
| 139 | #define MX21_INT_EMMAPRP 51 | ||
| 140 | #define MX21_INT_EMMAPP 52 | ||
| 141 | #define MX21_INT_USBWKUP 53 | ||
| 142 | #define MX21_INT_USBDMA 54 | ||
| 143 | #define MX21_INT_USBHOST 55 | ||
| 144 | #define MX21_INT_USBFUNC 56 | ||
| 145 | #define MX21_INT_USBMNP 57 | ||
| 146 | #define MX21_INT_USBCTRL 58 | ||
| 147 | #define MX21_INT_SLCDC 60 | ||
| 148 | #define MX21_INT_LCDC 61 | ||
| 64 | 149 | ||
| 65 | /* fixed DMA request numbers */ | 150 | /* fixed DMA request numbers */ |
| 66 | #define DMA_REQ_BMI_RX 29 | 151 | #define MX21_DMA_REQ_CSPI3_RX 1 |
| 67 | #define DMA_REQ_BMI_TX 28 | 152 | #define MX21_DMA_REQ_CSPI3_TX 2 |
| 68 | #define DMA_REQ_FIRI_RX 4 | 153 | #define MX21_DMA_REQ_EXT 3 |
| 154 | #define MX21_DMA_REQ_FIRI_RX 4 | ||
| 155 | #define MX21_DMA_REQ_SDHC2 6 | ||
| 156 | #define MX21_DMA_REQ_SDHC1 7 | ||
| 157 | #define MX21_DMA_REQ_SSI2_RX0 8 | ||
| 158 | #define MX21_DMA_REQ_SSI2_TX0 9 | ||
| 159 | #define MX21_DMA_REQ_SSI2_RX1 10 | ||
| 160 | #define MX21_DMA_REQ_SSI2_TX1 11 | ||
| 161 | #define MX21_DMA_REQ_SSI1_RX0 12 | ||
| 162 | #define MX21_DMA_REQ_SSI1_TX0 13 | ||
| 163 | #define MX21_DMA_REQ_SSI1_RX1 14 | ||
| 164 | #define MX21_DMA_REQ_SSI1_TX1 15 | ||
| 165 | #define MX21_DMA_REQ_CSPI2_RX 16 | ||
| 166 | #define MX21_DMA_REQ_CSPI2_TX 17 | ||
| 167 | #define MX21_DMA_REQ_CSPI1_RX 18 | ||
| 168 | #define MX21_DMA_REQ_CSPI1_TX 19 | ||
| 169 | #define MX21_DMA_REQ_UART4_RX 20 | ||
| 170 | #define MX21_DMA_REQ_UART4_TX 21 | ||
| 171 | #define MX21_DMA_REQ_UART3_RX 22 | ||
| 172 | #define MX21_DMA_REQ_UART3_TX 23 | ||
| 173 | #define MX21_DMA_REQ_UART2_RX 24 | ||
| 174 | #define MX21_DMA_REQ_UART2_TX 25 | ||
| 175 | #define MX21_DMA_REQ_UART1_RX 26 | ||
| 176 | #define MX21_DMA_REQ_UART1_TX 27 | ||
| 177 | #define MX21_DMA_REQ_BMI_TX 28 | ||
| 178 | #define MX21_DMA_REQ_BMI_RX 29 | ||
| 179 | #define MX21_DMA_REQ_CSI_STAT 30 | ||
| 180 | #define MX21_DMA_REQ_CSI_RX 31 | ||
| 181 | |||
| 182 | /* these should go away */ | ||
| 183 | #define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR | ||
| 184 | #define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR | ||
| 185 | #define CS0_BASE_ADDR MX21_CS0_BASE_ADDR | ||
| 186 | #define CS1_BASE_ADDR MX21_CS1_BASE_ADDR | ||
| 187 | #define CS2_BASE_ADDR MX21_CS2_BASE_ADDR | ||
| 188 | #define CS3_BASE_ADDR MX21_CS3_BASE_ADDR | ||
| 189 | #define CS4_BASE_ADDR MX21_CS4_BASE_ADDR | ||
| 190 | #define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR | ||
| 191 | #define CS5_BASE_ADDR MX21_CS5_BASE_ADDR | ||
| 192 | #define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR | ||
| 193 | #define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT | ||
| 194 | #define X_MEMC_SIZE MX21_X_MEMC_SIZE | ||
| 195 | #define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR | ||
| 196 | #define EIM_BASE_ADDR MX21_EIM_BASE_ADDR | ||
| 197 | #define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR | ||
| 198 | #define NFC_BASE_ADDR MX21_NFC_BASE_ADDR | ||
| 199 | #define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR | ||
| 200 | #define MXC_INT_FIRI MX21_INT_FIRI | ||
| 201 | #define MXC_INT_BMI MX21_INT_BMI | ||
| 202 | #define MXC_INT_EMMAENC MX21_INT_EMMAENC | ||
| 203 | #define MXC_INT_EMMADEC MX21_INT_EMMADEC | ||
| 204 | #define MXC_INT_USBWKUP MX21_INT_USBWKUP | ||
| 205 | #define MXC_INT_USBDMA MX21_INT_USBDMA | ||
| 206 | #define MXC_INT_USBHOST MX21_INT_USBHOST | ||
| 207 | #define MXC_INT_USBFUNC MX21_INT_USBFUNC | ||
| 208 | #define MXC_INT_USBMNP MX21_INT_USBMNP | ||
| 209 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
| 210 | #define MXC_INT_USBCTRL MX21_INT_USBCTRL | ||
| 211 | #define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX | ||
| 212 | #define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX | ||
| 213 | #define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX | ||
| 69 | 214 | ||
| 70 | #endif /* __ASM_ARCH_MXC_MX21_H__ */ | 215 | #endif /* __ASM_ARCH_MXC_MX21_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index ec64bd9a8ab1..91e738144804 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h | |||
| @@ -1,14 +1,14 @@ | |||
| 1 | #ifndef __MACH_MX25_H__ | 1 | #ifndef __MACH_MX25_H__ |
| 2 | #define __MACH_MX25_H__ | 2 | #define __MACH_MX25_H__ |
| 3 | 3 | ||
| 4 | #define MX25_AIPS1_BASE_ADDR 0x43F00000 | 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
| 5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xFC000000 | 5 | #define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000 |
| 6 | #define MX25_AIPS1_SIZE SZ_1M | 6 | #define MX25_AIPS1_SIZE SZ_1M |
| 7 | #define MX25_AIPS2_BASE_ADDR 0x53F00000 | 7 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
| 8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xFC200000 | 8 | #define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000 |
| 9 | #define MX25_AIPS2_SIZE SZ_1M | 9 | #define MX25_AIPS2_SIZE SZ_1M |
| 10 | #define MX25_AVIC_BASE_ADDR 0x68000000 | 10 | #define MX25_AVIC_BASE_ADDR 0x68000000 |
| 11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xFC400000 | 11 | #define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000 |
| 12 | #define MX25_AVIC_SIZE SZ_1M | 12 | #define MX25_AVIC_SIZE SZ_1M |
| 13 | 13 | ||
| 14 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) | 14 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) |
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index dc3ad9aa952a..e2ae19f51710 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
| @@ -24,87 +24,198 @@ | |||
| 24 | #ifndef __ASM_ARCH_MXC_MX27_H__ | 24 | #ifndef __ASM_ARCH_MXC_MX27_H__ |
| 25 | #define __ASM_ARCH_MXC_MX27_H__ | 25 | #define __ASM_ARCH_MXC_MX27_H__ |
| 26 | 26 | ||
| 27 | /* IRAM */ | 27 | #define MX27_AIPI_BASE_ADDR 0x10000000 |
| 28 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ | 28 | #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 |
| 29 | 29 | #define MX27_AIPI_SIZE SZ_1M | |
| 30 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) | 30 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) |
| 31 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) | 31 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) |
| 32 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) | 32 | #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) |
| 33 | #define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000) | 33 | #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) |
| 34 | #define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000) | 34 | #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) |
| 35 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) | 35 | #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) |
| 36 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) | 36 | #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) |
| 37 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) | 37 | #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) |
| 38 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) | 38 | #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) |
| 39 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR | 39 | #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) |
| 40 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) | 40 | #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) |
| 41 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) | 41 | #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) |
| 42 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) | 42 | #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) |
| 43 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) | 43 | #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) |
| 44 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) | 44 | #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) |
| 45 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) | 45 | #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) |
| 46 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) | 46 | #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) |
| 47 | #define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) | ||
| 48 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) | ||
| 49 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | ||
| 50 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | ||
| 51 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) | ||
| 52 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) | ||
| 53 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) | ||
| 54 | #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) | ||
| 55 | #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) | ||
| 56 | #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) | ||
| 57 | #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) | ||
| 58 | #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) | ||
| 59 | #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) | ||
| 60 | #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) | ||
| 61 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) | ||
| 62 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) | ||
| 63 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) | ||
| 64 | #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) | ||
| 65 | #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR | ||
| 66 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) | ||
| 67 | #define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) | ||
| 68 | #define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) | ||
| 69 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) | ||
| 70 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) | ||
| 71 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) | ||
| 72 | #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) | ||
| 73 | #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) | ||
| 74 | #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) | ||
| 75 | #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) | ||
| 76 | #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) | ||
| 77 | #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) | ||
| 78 | #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) | ||
| 79 | |||
| 80 | #define MX27_AVIC_BASE_ADDR 0x10040000 | ||
| 47 | 81 | ||
| 48 | /* ROM patch */ | 82 | /* ROM patch */ |
| 49 | #define ROMP_BASE_ADDR 0x10041000 | 83 | #define MX27_ROMP_BASE_ADDR 0x10041000 |
| 50 | 84 | ||
| 51 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) | 85 | #define MX27_SAHB1_BASE_ADDR 0x80000000 |
| 86 | #define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 | ||
| 87 | #define MX27_SAHB1_SIZE SZ_1M | ||
| 88 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) | ||
| 89 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) | ||
| 52 | 90 | ||
| 53 | /* Memory regions and CS */ | 91 | /* Memory regions and CS */ |
| 54 | #define SDRAM_BASE_ADDR 0xA0000000 | 92 | #define MX27_SDRAM_BASE_ADDR 0xa0000000 |
| 55 | #define CSD1_BASE_ADDR 0xB0000000 | 93 | #define MX27_CSD1_BASE_ADDR 0xb0000000 |
| 56 | 94 | ||
| 57 | #define CS0_BASE_ADDR 0xC0000000 | 95 | #define MX27_CS0_BASE_ADDR 0xc0000000 |
| 58 | #define CS1_BASE_ADDR 0xC8000000 | 96 | #define MX27_CS1_BASE_ADDR 0xc8000000 |
| 59 | #define CS2_BASE_ADDR 0xD0000000 | 97 | #define MX27_CS2_BASE_ADDR 0xd0000000 |
| 60 | #define CS3_BASE_ADDR 0xD2000000 | 98 | #define MX27_CS3_BASE_ADDR 0xd2000000 |
| 61 | #define CS4_BASE_ADDR 0xD4000000 | 99 | #define MX27_CS4_BASE_ADDR 0xd4000000 |
| 62 | #define CS5_BASE_ADDR 0xD6000000 | 100 | #define MX27_CS5_BASE_ADDR 0xd6000000 |
| 63 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 | ||
| 64 | 101 | ||
| 65 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | 102 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
| 66 | #define X_MEMC_BASE_ADDR 0xD8000000 | 103 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 |
| 67 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | 104 | #define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 |
| 68 | #define X_MEMC_SIZE SZ_1M | 105 | #define MX27_X_MEMC_SIZE SZ_1M |
| 106 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) | ||
| 107 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) | ||
| 108 | #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) | ||
| 109 | #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) | ||
| 110 | #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) | ||
| 69 | 111 | ||
| 70 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) | 112 | #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 |
| 71 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | 113 | |
| 72 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | 114 | /* IRAM */ |
| 73 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | 115 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ |
| 74 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 75 | 116 | ||
| 76 | /* fixed interrupt numbers */ | 117 | /* fixed interrupt numbers */ |
| 77 | #define MXC_INT_CCM 63 | 118 | #define MX27_INT_I2C2 1 |
| 78 | #define MXC_INT_IIM 62 | 119 | #define MX27_INT_GPT6 2 |
| 79 | #define MXC_INT_SAHARA 59 | 120 | #define MX27_INT_GPT5 3 |
| 80 | #define MXC_INT_SCC_SCM 58 | 121 | #define MX27_INT_GPT4 4 |
| 81 | #define MXC_INT_SCC_SMN 57 | 122 | #define MX27_INT_RTIC 5 |
| 82 | #define MXC_INT_USB3 56 | 123 | #define MX27_INT_CSPI3 6 |
| 83 | #define MXC_INT_USB2 55 | 124 | #define MX27_INT_SDHC 7 |
| 84 | #define MXC_INT_USB1 54 | 125 | #define MX27_INT_GPIO 8 |
| 85 | #define MXC_INT_VPU 53 | 126 | #define MX27_INT_SDHC3 9 |
| 86 | #define MXC_INT_FEC 50 | 127 | #define MX27_INT_SDHC2 10 |
| 87 | #define MXC_INT_UART5 49 | 128 | #define MX27_INT_SDHC1 11 |
| 88 | #define MXC_INT_UART6 48 | 129 | #define MX27_INT_I2C 12 |
| 89 | #define MXC_INT_ATA 30 | 130 | #define MX27_INT_SSI2 13 |
| 90 | #define MXC_INT_SDHC3 9 | 131 | #define MX27_INT_SSI1 14 |
| 91 | #define MXC_INT_SDHC 7 | 132 | #define MX27_INT_CSPI2 15 |
| 92 | #define MXC_INT_RTIC 5 | 133 | #define MX27_INT_CSPI1 16 |
| 93 | #define MXC_INT_GPT4 4 | 134 | #define MX27_INT_UART4 17 |
| 94 | #define MXC_INT_GPT5 3 | 135 | #define MX27_INT_UART3 18 |
| 95 | #define MXC_INT_GPT6 2 | 136 | #define MX27_INT_UART2 19 |
| 96 | #define MXC_INT_I2C2 1 | 137 | #define MX27_INT_UART1 20 |
| 138 | #define MX27_INT_KPP 21 | ||
| 139 | #define MX27_INT_RTC 22 | ||
| 140 | #define MX27_INT_PWM 23 | ||
| 141 | #define MX27_INT_GPT3 24 | ||
| 142 | #define MX27_INT_GPT2 25 | ||
| 143 | #define MX27_INT_GPT1 26 | ||
| 144 | #define MX27_INT_WDOG 27 | ||
| 145 | #define MX27_INT_PCMCIA 28 | ||
| 146 | #define MX27_INT_NANDFC 29 | ||
| 147 | #define MX27_INT_ATA 30 | ||
| 148 | #define MX27_INT_CSI 31 | ||
| 149 | #define MX27_INT_DMACH0 32 | ||
| 150 | #define MX27_INT_DMACH1 33 | ||
| 151 | #define MX27_INT_DMACH2 34 | ||
| 152 | #define MX27_INT_DMACH3 35 | ||
| 153 | #define MX27_INT_DMACH4 36 | ||
| 154 | #define MX27_INT_DMACH5 37 | ||
| 155 | #define MX27_INT_DMACH6 38 | ||
| 156 | #define MX27_INT_DMACH7 39 | ||
| 157 | #define MX27_INT_DMACH8 40 | ||
| 158 | #define MX27_INT_DMACH9 41 | ||
| 159 | #define MX27_INT_DMACH10 42 | ||
| 160 | #define MX27_INT_DMACH11 43 | ||
| 161 | #define MX27_INT_DMACH12 44 | ||
| 162 | #define MX27_INT_DMACH13 45 | ||
| 163 | #define MX27_INT_DMACH14 46 | ||
| 164 | #define MX27_INT_DMACH15 47 | ||
| 165 | #define MX27_INT_UART6 48 | ||
| 166 | #define MX27_INT_UART5 49 | ||
| 167 | #define MX27_INT_FEC 50 | ||
| 168 | #define MX27_INT_EMMAPRP 51 | ||
| 169 | #define MX27_INT_EMMAPP 52 | ||
| 170 | #define MX27_INT_VPU 53 | ||
| 171 | #define MX27_INT_USB1 54 | ||
| 172 | #define MX27_INT_USB2 55 | ||
| 173 | #define MX27_INT_USB3 56 | ||
| 174 | #define MX27_INT_SCC_SMN 57 | ||
| 175 | #define MX27_INT_SCC_SCM 58 | ||
| 176 | #define MX27_INT_SAHARA 59 | ||
| 177 | #define MX27_INT_SLCDC 60 | ||
| 178 | #define MX27_INT_LCDC 61 | ||
| 179 | #define MX27_INT_IIM 62 | ||
| 180 | #define MX27_INT_CCM 63 | ||
| 97 | 181 | ||
| 98 | /* fixed DMA request numbers */ | 182 | /* fixed DMA request numbers */ |
| 99 | #define DMA_REQ_NFC 37 | 183 | #define MX27_DMA_REQ_CSPI3_RX 1 |
| 100 | #define DMA_REQ_SDHC3 36 | 184 | #define MX27_DMA_REQ_CSPI3_TX 2 |
| 101 | #define DMA_REQ_UART6_RX 35 | 185 | #define MX27_DMA_REQ_EXT 3 |
| 102 | #define DMA_REQ_UART6_TX 34 | 186 | #define MX27_DMA_REQ_MSHC 4 |
| 103 | #define DMA_REQ_UART5_RX 33 | 187 | #define MX27_DMA_REQ_SDHC2 6 |
| 104 | #define DMA_REQ_UART5_TX 32 | 188 | #define MX27_DMA_REQ_SDHC1 7 |
| 105 | #define DMA_REQ_ATA_RCV 29 | 189 | #define MX27_DMA_REQ_SSI2_RX0 8 |
| 106 | #define DMA_REQ_ATA_TX 28 | 190 | #define MX27_DMA_REQ_SSI2_TX0 9 |
| 107 | #define DMA_REQ_MSHC 4 | 191 | #define MX27_DMA_REQ_SSI2_RX1 10 |
| 192 | #define MX27_DMA_REQ_SSI2_TX1 11 | ||
| 193 | #define MX27_DMA_REQ_SSI1_RX0 12 | ||
| 194 | #define MX27_DMA_REQ_SSI1_TX0 13 | ||
| 195 | #define MX27_DMA_REQ_SSI1_RX1 14 | ||
| 196 | #define MX27_DMA_REQ_SSI1_TX1 15 | ||
| 197 | #define MX27_DMA_REQ_CSPI2_RX 16 | ||
| 198 | #define MX27_DMA_REQ_CSPI2_TX 17 | ||
| 199 | #define MX27_DMA_REQ_CSPI1_RX 18 | ||
| 200 | #define MX27_DMA_REQ_CSPI1_TX 19 | ||
| 201 | #define MX27_DMA_REQ_UART4_RX 20 | ||
| 202 | #define MX27_DMA_REQ_UART4_TX 21 | ||
| 203 | #define MX27_DMA_REQ_UART3_RX 22 | ||
| 204 | #define MX27_DMA_REQ_UART3_TX 23 | ||
| 205 | #define MX27_DMA_REQ_UART2_RX 24 | ||
| 206 | #define MX27_DMA_REQ_UART2_TX 25 | ||
| 207 | #define MX27_DMA_REQ_UART1_RX 26 | ||
| 208 | #define MX27_DMA_REQ_UART1_TX 27 | ||
| 209 | #define MX27_DMA_REQ_ATA_TX 28 | ||
| 210 | #define MX27_DMA_REQ_ATA_RCV 29 | ||
| 211 | #define MX27_DMA_REQ_CSI_STAT 30 | ||
| 212 | #define MX27_DMA_REQ_CSI_RX 31 | ||
| 213 | #define MX27_DMA_REQ_UART5_TX 32 | ||
| 214 | #define MX27_DMA_REQ_UART5_RX 33 | ||
| 215 | #define MX27_DMA_REQ_UART6_TX 34 | ||
| 216 | #define MX27_DMA_REQ_UART6_RX 35 | ||
| 217 | #define MX27_DMA_REQ_SDHC3 36 | ||
| 218 | #define MX27_DMA_REQ_NFC 37 | ||
| 108 | 219 | ||
| 109 | /* silicon revisions specific to i.MX27 */ | 220 | /* silicon revisions specific to i.MX27 */ |
| 110 | #define CHIP_REV_1_0 0x00 | 221 | #define CHIP_REV_1_0 0x00 |
| @@ -114,6 +225,72 @@ | |||
| 114 | extern int mx27_revision(void); | 225 | extern int mx27_revision(void); |
| 115 | #endif | 226 | #endif |
| 116 | 227 | ||
| 117 | /* Mandatory defines used globally */ | 228 | /* these should go away */ |
| 229 | #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR | ||
| 230 | #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR | ||
| 231 | #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR | ||
| 232 | #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR | ||
| 233 | #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR | ||
| 234 | #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR | ||
| 235 | #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR | ||
| 236 | #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR | ||
| 237 | #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR | ||
| 238 | #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR | ||
| 239 | #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR | ||
| 240 | #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR | ||
| 241 | #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR | ||
| 242 | #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR | ||
| 243 | #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR | ||
| 244 | #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR | ||
| 245 | #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR | ||
| 246 | #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR | ||
| 247 | #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR | ||
| 248 | #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR | ||
| 249 | #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR | ||
| 250 | #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR | ||
| 251 | #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR | ||
| 252 | #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR | ||
| 253 | #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR | ||
| 254 | #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR | ||
| 255 | #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR | ||
| 256 | #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR | ||
| 257 | #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT | ||
| 258 | #define X_MEMC_SIZE MX27_X_MEMC_SIZE | ||
| 259 | #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR | ||
| 260 | #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR | ||
| 261 | #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR | ||
| 262 | #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR | ||
| 263 | #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR | ||
| 264 | #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR | ||
| 265 | #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR | ||
| 266 | #define MXC_INT_I2C2 MX27_INT_I2C2 | ||
| 267 | #define MXC_INT_GPT6 MX27_INT_GPT6 | ||
| 268 | #define MXC_INT_GPT5 MX27_INT_GPT5 | ||
| 269 | #define MXC_INT_GPT4 MX27_INT_GPT4 | ||
| 270 | #define MXC_INT_RTIC MX27_INT_RTIC | ||
| 271 | #define MXC_INT_SDHC MX27_INT_SDHC | ||
| 272 | #define MXC_INT_SDHC3 MX27_INT_SDHC3 | ||
| 273 | #define MXC_INT_ATA MX27_INT_ATA | ||
| 274 | #define MXC_INT_UART6 MX27_INT_UART6 | ||
| 275 | #define MXC_INT_UART5 MX27_INT_UART5 | ||
| 276 | #define MXC_INT_FEC MX27_INT_FEC | ||
| 277 | #define MXC_INT_VPU MX27_INT_VPU | ||
| 278 | #define MXC_INT_USB1 MX27_INT_USB1 | ||
| 279 | #define MXC_INT_USB2 MX27_INT_USB2 | ||
| 280 | #define MXC_INT_USB3 MX27_INT_USB3 | ||
| 281 | #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN | ||
| 282 | #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM | ||
| 283 | #define MXC_INT_SAHARA MX27_INT_SAHARA | ||
| 284 | #define MXC_INT_IIM MX27_INT_IIM | ||
| 285 | #define MXC_INT_CCM MX27_INT_CCM | ||
| 286 | #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC | ||
| 287 | #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX | ||
| 288 | #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV | ||
| 289 | #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX | ||
| 290 | #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX | ||
| 291 | #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX | ||
| 292 | #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX | ||
| 293 | #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 | ||
| 294 | #define DMA_REQ_NFC MX27_DMA_REQ_NFC | ||
| 118 | 295 | ||
| 119 | #endif /* __ASM_ARCH_MXC_MX27_H__ */ | 296 | #endif /* __ASM_ARCH_MXC_MX27_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h index db5d921e0fe6..f2eaf140ed02 100644 --- a/arch/arm/plat-mxc/include/mach/mx2x.h +++ b/arch/arm/plat-mxc/include/mach/mx2x.h | |||
| @@ -25,51 +25,49 @@ | |||
| 25 | 25 | ||
| 26 | /* The following addresses are common between i.MX21 and i.MX27 */ | 26 | /* The following addresses are common between i.MX21 and i.MX27 */ |
| 27 | 27 | ||
| 28 | /* Register offests */ | 28 | /* Register offsets */ |
| 29 | #define AIPI_BASE_ADDR 0x10000000 | 29 | #define MX2x_AIPI_BASE_ADDR 0x10000000 |
| 30 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | 30 | #define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000 |
| 31 | #define AIPI_SIZE SZ_1M | 31 | #define MX2x_AIPI_SIZE SZ_1M |
| 32 | 32 | #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) | |
| 33 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | 33 | #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) |
| 34 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | 34 | #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) |
| 35 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | 35 | #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) |
| 36 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | 36 | #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) |
| 37 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | 37 | #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) |
| 38 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | 38 | #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) |
| 39 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | 39 | #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) |
| 40 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | 40 | #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) |
| 41 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | 41 | #define MX2x_UART1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0a000) |
| 42 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | 42 | #define MX2x_UART2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0b000) |
| 43 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | 43 | #define MX2x_UART3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0c000) |
| 44 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | 44 | #define MX2x_UART4_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0d000) |
| 45 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | 45 | #define MX2x_CSPI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0e000) |
| 46 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | 46 | #define MX2x_CSPI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x0f000) |
| 47 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | 47 | #define MX2x_SSI1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x10000) |
| 48 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | 48 | #define MX2x_SSI2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x11000) |
| 49 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | 49 | #define MX2x_I2C_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x12000) |
| 50 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | 50 | #define MX2x_SDHC1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x13000) |
| 51 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | 51 | #define MX2x_SDHC2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x14000) |
| 52 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | 52 | #define MX2x_GPIO_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x15000) |
| 53 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | 53 | #define MX2x_AUDMUX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x16000) |
| 54 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | 54 | #define MX2x_CSPI3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x17000) |
| 55 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | 55 | #define MX2x_LCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x21000) |
| 56 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | 56 | #define MX2x_SLCDC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x22000) |
| 57 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | 57 | #define MX2x_USBOTG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x24000) |
| 58 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | 58 | #define MX2x_EMMA_PP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26000) |
| 59 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) | 59 | #define MX2x_EMMA_PRP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x26400) |
| 60 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | 60 | #define MX2x_CCM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27000) |
| 61 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | 61 | #define MX2x_SYSCTRL_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x27800) |
| 62 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | 62 | #define MX2x_JAM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3e000) |
| 63 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | 63 | #define MX2x_MAX_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x3f000) |
| 64 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | 64 | |
| 65 | 65 | #define MX2x_AVIC_BASE_ADDR 0x10040000 | |
| 66 | #define AVIC_BASE_ADDR 0x10040000 | 66 | |
| 67 | 67 | #define MX2x_SAHB1_BASE_ADDR 0x80000000 | |
| 68 | #define SAHB1_BASE_ADDR 0x80000000 | 68 | #define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000 |
| 69 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | 69 | #define MX2x_SAHB1_SIZE SZ_1M |
| 70 | #define SAHB1_SIZE SZ_1M | 70 | #define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) |
| 71 | |||
| 72 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 73 | 71 | ||
| 74 | /* | 72 | /* |
| 75 | * This macro defines the physical to virtual address mapping for all the | 73 | * This macro defines the physical to virtual address mapping for all the |
| @@ -105,78 +103,189 @@ | |||
| 105 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | 103 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) |
| 106 | 104 | ||
| 107 | /* fixed interrupt numbers */ | 105 | /* fixed interrupt numbers */ |
| 108 | #define MXC_INT_LCDC 61 | 106 | #define MX2x_INT_CSPI3 6 |
| 109 | #define MXC_INT_SLCDC 60 | 107 | #define MX2x_INT_GPIO 8 |
| 110 | #define MXC_INT_EMMAPP 52 | 108 | #define MX2x_INT_SDHC2 10 |
| 111 | #define MXC_INT_EMMAPRP 51 | 109 | #define MX2x_INT_SDHC1 11 |
| 112 | #define MXC_INT_DMACH15 47 | 110 | #define MX2x_INT_I2C 12 |
| 113 | #define MXC_INT_DMACH14 46 | 111 | #define MX2x_INT_SSI2 13 |
| 114 | #define MXC_INT_DMACH13 45 | 112 | #define MX2x_INT_SSI1 14 |
| 115 | #define MXC_INT_DMACH12 44 | 113 | #define MX2x_INT_CSPI2 15 |
| 116 | #define MXC_INT_DMACH11 43 | 114 | #define MX2x_INT_CSPI1 16 |
| 117 | #define MXC_INT_DMACH10 42 | 115 | #define MX2x_INT_UART4 17 |
| 118 | #define MXC_INT_DMACH9 41 | 116 | #define MX2x_INT_UART3 18 |
| 119 | #define MXC_INT_DMACH8 40 | 117 | #define MX2x_INT_UART2 19 |
| 120 | #define MXC_INT_DMACH7 39 | 118 | #define MX2x_INT_UART1 20 |
| 121 | #define MXC_INT_DMACH6 38 | 119 | #define MX2x_INT_KPP 21 |
| 122 | #define MXC_INT_DMACH5 37 | 120 | #define MX2x_INT_RTC 22 |
| 123 | #define MXC_INT_DMACH4 36 | 121 | #define MX2x_INT_PWM 23 |
| 124 | #define MXC_INT_DMACH3 35 | 122 | #define MX2x_INT_GPT3 24 |
| 125 | #define MXC_INT_DMACH2 34 | 123 | #define MX2x_INT_GPT2 25 |
| 126 | #define MXC_INT_DMACH1 33 | 124 | #define MX2x_INT_GPT1 26 |
| 127 | #define MXC_INT_DMACH0 32 | 125 | #define MX2x_INT_WDOG 27 |
| 128 | #define MXC_INT_CSI 31 | 126 | #define MX2x_INT_PCMCIA 28 |
| 129 | #define MXC_INT_NANDFC 29 | 127 | #define MX2x_INT_NANDFC 29 |
| 130 | #define MXC_INT_PCMCIA 28 | 128 | #define MX2x_INT_CSI 31 |
| 131 | #define MXC_INT_WDOG 27 | 129 | #define MX2x_INT_DMACH0 32 |
| 132 | #define MXC_INT_GPT1 26 | 130 | #define MX2x_INT_DMACH1 33 |
| 133 | #define MXC_INT_GPT2 25 | 131 | #define MX2x_INT_DMACH2 34 |
| 134 | #define MXC_INT_GPT3 24 | 132 | #define MX2x_INT_DMACH3 35 |
| 135 | #define MXC_INT_GPT INT_GPT1 | 133 | #define MX2x_INT_DMACH4 36 |
| 136 | #define MXC_INT_PWM 23 | 134 | #define MX2x_INT_DMACH5 37 |
| 137 | #define MXC_INT_RTC 22 | 135 | #define MX2x_INT_DMACH6 38 |
| 138 | #define MXC_INT_KPP 21 | 136 | #define MX2x_INT_DMACH7 39 |
| 139 | #define MXC_INT_UART1 20 | 137 | #define MX2x_INT_DMACH8 40 |
| 140 | #define MXC_INT_UART2 19 | 138 | #define MX2x_INT_DMACH9 41 |
| 141 | #define MXC_INT_UART3 18 | 139 | #define MX2x_INT_DMACH10 42 |
| 142 | #define MXC_INT_UART4 17 | 140 | #define MX2x_INT_DMACH11 43 |
| 143 | #define MXC_INT_CSPI1 16 | 141 | #define MX2x_INT_DMACH12 44 |
| 144 | #define MXC_INT_CSPI2 15 | 142 | #define MX2x_INT_DMACH13 45 |
| 145 | #define MXC_INT_SSI1 14 | 143 | #define MX2x_INT_DMACH14 46 |
| 146 | #define MXC_INT_SSI2 13 | 144 | #define MX2x_INT_DMACH15 47 |
| 147 | #define MXC_INT_I2C 12 | 145 | #define MX2x_INT_EMMAPRP 51 |
| 148 | #define MXC_INT_SDHC1 11 | 146 | #define MX2x_INT_EMMAPP 52 |
| 149 | #define MXC_INT_SDHC2 10 | 147 | #define MX2x_INT_SLCDC 60 |
| 150 | #define MXC_INT_GPIO 8 | 148 | #define MX2x_INT_LCDC 61 |
| 151 | #define MXC_INT_CSPI3 6 | ||
| 152 | 149 | ||
| 153 | /* fixed DMA request numbers */ | 150 | /* fixed DMA request numbers */ |
| 154 | #define DMA_REQ_CSI_RX 31 | 151 | #define MX2x_DMA_REQ_CSPI3_RX 1 |
| 155 | #define DMA_REQ_CSI_STAT 30 | 152 | #define MX2x_DMA_REQ_CSPI3_TX 2 |
| 156 | #define DMA_REQ_UART1_TX 27 | 153 | #define MX2x_DMA_REQ_EXT 3 |
| 157 | #define DMA_REQ_UART1_RX 26 | 154 | #define MX2x_DMA_REQ_SDHC2 6 |
| 158 | #define DMA_REQ_UART2_TX 25 | 155 | #define MX2x_DMA_REQ_SDHC1 7 |
| 159 | #define DMA_REQ_UART2_RX 24 | 156 | #define MX2x_DMA_REQ_SSI2_RX0 8 |
| 160 | #define DMA_REQ_UART3_TX 23 | 157 | #define MX2x_DMA_REQ_SSI2_TX0 9 |
| 161 | #define DMA_REQ_UART3_RX 22 | 158 | #define MX2x_DMA_REQ_SSI2_RX1 10 |
| 162 | #define DMA_REQ_UART4_TX 21 | 159 | #define MX2x_DMA_REQ_SSI2_TX1 11 |
| 163 | #define DMA_REQ_UART4_RX 20 | 160 | #define MX2x_DMA_REQ_SSI1_RX0 12 |
| 164 | #define DMA_REQ_CSPI1_TX 19 | 161 | #define MX2x_DMA_REQ_SSI1_TX0 13 |
| 165 | #define DMA_REQ_CSPI1_RX 18 | 162 | #define MX2x_DMA_REQ_SSI1_RX1 14 |
| 166 | #define DMA_REQ_CSPI2_TX 17 | 163 | #define MX2x_DMA_REQ_SSI1_TX1 15 |
| 167 | #define DMA_REQ_CSPI2_RX 16 | 164 | #define MX2x_DMA_REQ_CSPI2_RX 16 |
| 168 | #define DMA_REQ_SSI1_TX1 15 | 165 | #define MX2x_DMA_REQ_CSPI2_TX 17 |
| 169 | #define DMA_REQ_SSI1_RX1 14 | 166 | #define MX2x_DMA_REQ_CSPI1_RX 18 |
| 170 | #define DMA_REQ_SSI1_TX0 13 | 167 | #define MX2x_DMA_REQ_CSPI1_TX 19 |
| 171 | #define DMA_REQ_SSI1_RX0 12 | 168 | #define MX2x_DMA_REQ_UART4_RX 20 |
| 172 | #define DMA_REQ_SSI2_TX1 11 | 169 | #define MX2x_DMA_REQ_UART4_TX 21 |
| 173 | #define DMA_REQ_SSI2_RX1 10 | 170 | #define MX2x_DMA_REQ_UART3_RX 22 |
| 174 | #define DMA_REQ_SSI2_TX0 9 | 171 | #define MX2x_DMA_REQ_UART3_TX 23 |
| 175 | #define DMA_REQ_SSI2_RX0 8 | 172 | #define MX2x_DMA_REQ_UART2_RX 24 |
| 176 | #define DMA_REQ_SDHC1 7 | 173 | #define MX2x_DMA_REQ_UART2_TX 25 |
| 177 | #define DMA_REQ_SDHC2 6 | 174 | #define MX2x_DMA_REQ_UART1_RX 26 |
| 178 | #define DMA_REQ_EXT 3 | 175 | #define MX2x_DMA_REQ_UART1_TX 27 |
| 179 | #define DMA_REQ_CSPI3_TX 2 | 176 | #define MX2x_DMA_REQ_CSI_STAT 30 |
| 180 | #define DMA_REQ_CSPI3_RX 1 | 177 | #define MX2x_DMA_REQ_CSI_RX 31 |
| 178 | |||
| 179 | /* these should go away */ | ||
| 180 | #define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR | ||
| 181 | #define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT | ||
| 182 | #define AIPI_SIZE MX2x_AIPI_SIZE | ||
| 183 | #define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR | ||
| 184 | #define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR | ||
| 185 | #define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR | ||
| 186 | #define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR | ||
| 187 | #define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR | ||
| 188 | #define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR | ||
| 189 | #define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR | ||
| 190 | #define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR | ||
| 191 | #define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR | ||
| 192 | #define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR | ||
| 193 | #define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR | ||
| 194 | #define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR | ||
| 195 | #define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR | ||
| 196 | #define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR | ||
| 197 | #define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR | ||
| 198 | #define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR | ||
| 199 | #define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR | ||
| 200 | #define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR | ||
| 201 | #define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR | ||
| 202 | #define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR | ||
| 203 | #define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR | ||
| 204 | #define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR | ||
| 205 | #define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR | ||
| 206 | #define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR | ||
| 207 | #define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR | ||
| 208 | #define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR | ||
| 209 | #define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR | ||
| 210 | #define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR | ||
| 211 | #define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR | ||
| 212 | #define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR | ||
| 213 | #define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR | ||
| 214 | #define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR | ||
| 215 | #define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR | ||
| 216 | #define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR | ||
| 217 | #define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT | ||
| 218 | #define SAHB1_SIZE MX2x_SAHB1_SIZE | ||
| 219 | #define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR | ||
| 220 | #define MXC_INT_CSPI3 MX2x_INT_CSPI3 | ||
| 221 | #define MXC_INT_GPIO MX2x_INT_GPIO | ||
| 222 | #define MXC_INT_SDHC2 MX2x_INT_SDHC2 | ||
| 223 | #define MXC_INT_SDHC1 MX2x_INT_SDHC1 | ||
| 224 | #define MXC_INT_I2C MX2x_INT_I2C | ||
| 225 | #define MXC_INT_SSI2 MX2x_INT_SSI2 | ||
| 226 | #define MXC_INT_SSI1 MX2x_INT_SSI1 | ||
| 227 | #define MXC_INT_CSPI2 MX2x_INT_CSPI2 | ||
| 228 | #define MXC_INT_CSPI1 MX2x_INT_CSPI1 | ||
| 229 | #define MXC_INT_UART4 MX2x_INT_UART4 | ||
| 230 | #define MXC_INT_UART3 MX2x_INT_UART3 | ||
| 231 | #define MXC_INT_UART2 MX2x_INT_UART2 | ||
| 232 | #define MXC_INT_UART1 MX2x_INT_UART1 | ||
| 233 | #define MXC_INT_KPP MX2x_INT_KPP | ||
| 234 | #define MXC_INT_RTC MX2x_INT_RTC | ||
| 235 | #define MXC_INT_PWM MX2x_INT_PWM | ||
| 236 | #define MXC_INT_GPT3 MX2x_INT_GPT3 | ||
| 237 | #define MXC_INT_GPT2 MX2x_INT_GPT2 | ||
| 238 | #define MXC_INT_GPT1 MX2x_INT_GPT1 | ||
| 239 | #define MXC_INT_WDOG MX2x_INT_WDOG | ||
| 240 | #define MXC_INT_PCMCIA MX2x_INT_PCMCIA | ||
| 241 | #define MXC_INT_NANDFC MX2x_INT_NANDFC | ||
| 242 | #define MXC_INT_CSI MX2x_INT_CSI | ||
| 243 | #define MXC_INT_DMACH0 MX2x_INT_DMACH0 | ||
| 244 | #define MXC_INT_DMACH1 MX2x_INT_DMACH1 | ||
| 245 | #define MXC_INT_DMACH2 MX2x_INT_DMACH2 | ||
| 246 | #define MXC_INT_DMACH3 MX2x_INT_DMACH3 | ||
| 247 | #define MXC_INT_DMACH4 MX2x_INT_DMACH4 | ||
| 248 | #define MXC_INT_DMACH5 MX2x_INT_DMACH5 | ||
| 249 | #define MXC_INT_DMACH6 MX2x_INT_DMACH6 | ||
| 250 | #define MXC_INT_DMACH7 MX2x_INT_DMACH7 | ||
| 251 | #define MXC_INT_DMACH8 MX2x_INT_DMACH8 | ||
| 252 | #define MXC_INT_DMACH9 MX2x_INT_DMACH9 | ||
| 253 | #define MXC_INT_DMACH10 MX2x_INT_DMACH10 | ||
| 254 | #define MXC_INT_DMACH11 MX2x_INT_DMACH11 | ||
| 255 | #define MXC_INT_DMACH12 MX2x_INT_DMACH12 | ||
| 256 | #define MXC_INT_DMACH13 MX2x_INT_DMACH13 | ||
| 257 | #define MXC_INT_DMACH14 MX2x_INT_DMACH14 | ||
| 258 | #define MXC_INT_DMACH15 MX2x_INT_DMACH15 | ||
| 259 | #define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP | ||
| 260 | #define MXC_INT_EMMAPP MX2x_INT_EMMAPP | ||
| 261 | #define MXC_INT_SLCDC MX2x_INT_SLCDC | ||
| 262 | #define MXC_INT_LCDC MX2x_INT_LCDC | ||
| 263 | #define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX | ||
| 264 | #define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX | ||
| 265 | #define DMA_REQ_EXT MX2x_DMA_REQ_EXT | ||
| 266 | #define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2 | ||
| 267 | #define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1 | ||
| 268 | #define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0 | ||
| 269 | #define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0 | ||
| 270 | #define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1 | ||
| 271 | #define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1 | ||
| 272 | #define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0 | ||
| 273 | #define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0 | ||
| 274 | #define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1 | ||
| 275 | #define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1 | ||
| 276 | #define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX | ||
| 277 | #define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX | ||
| 278 | #define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX | ||
| 279 | #define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX | ||
| 280 | #define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX | ||
| 281 | #define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX | ||
| 282 | #define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX | ||
| 283 | #define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX | ||
| 284 | #define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX | ||
| 285 | #define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX | ||
| 286 | #define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX | ||
| 287 | #define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX | ||
| 288 | #define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT | ||
| 289 | #define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX | ||
| 181 | 290 | ||
| 182 | #endif /* __ASM_ARCH_MXC_MX2x_H__ */ | 291 | #endif /* __ASM_ARCH_MXC_MX2x_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index 14ac0dcc82f4..b8b47d139eb5 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
| @@ -1,45 +1,218 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * IRAM | 2 | * IRAM |
| 3 | */ | 3 | */ |
| 4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | 4 | #define MX31_IRAM_BASE_ADDR 0x1ffc0000 /* internal ram */ |
| 5 | #define MX31_IRAM_SIZE SZ_16K | 5 | #define MX31_IRAM_SIZE SZ_16K |
| 6 | 6 | ||
| 7 | #define MX31_OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | 7 | #define MX31_L2CC_BASE_ADDR 0x30000000 |
| 8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | 8 | #define MX31_L2CC_SIZE SZ_1M |
| 9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | ||
| 10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | ||
| 11 | 9 | ||
| 12 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) | 10 | #define MX31_AIPS1_BASE_ADDR 0x43f00000 |
| 13 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) | 11 | #define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000 |
| 14 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) | 12 | #define MX31_AIPS1_SIZE SZ_1M |
| 15 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) | 13 | #define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) |
| 14 | #define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) | ||
| 15 | #define MX31_CLKCTL_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x0c000) | ||
| 16 | #define MX31_ETB_SLOT4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x10000) | ||
| 17 | #define MX31_ETB_SLOT5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x14000) | ||
| 18 | #define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) | ||
| 19 | #define MX31_I2C_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) | ||
| 20 | #define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) | ||
| 21 | #define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) | ||
| 22 | #define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) | ||
| 23 | #define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) | ||
| 24 | #define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) | ||
| 25 | #define MX31_I2C2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x98000) | ||
| 26 | #define MX31_OWIRE_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x9c000) | ||
| 27 | #define MX31_SSI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa0000) | ||
| 28 | #define MX31_CSPI1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa4000) | ||
| 29 | #define MX31_KPP_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xa8000) | ||
| 30 | #define MX31_IOMUXC_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xac000) | ||
| 31 | #define MX31_UART4_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb0000) | ||
| 32 | #define MX31_UART5_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb4000) | ||
| 33 | #define MX31_ECT_IP1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xb8000) | ||
| 34 | #define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) | ||
| 16 | 35 | ||
| 17 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) | 36 | #define MX31_SPBA0_BASE_ADDR 0x50000000 |
| 18 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) | 37 | #define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000 |
| 19 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) | 38 | #define MX31_SPBA0_SIZE SZ_1M |
| 20 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) | 39 | #define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) |
| 21 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) | 40 | #define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) |
| 41 | #define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) | ||
| 42 | #define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) | ||
| 43 | #define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) | ||
| 44 | #define MX31_SIM1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x18000) | ||
| 45 | #define MX31_IIM_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x1c000) | ||
| 46 | #define MX31_ATA_DMA_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x20000) | ||
| 47 | #define MX31_MSHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x24000) | ||
| 48 | #define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) | ||
| 22 | 49 | ||
| 23 | #define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | 50 | #define MX31_AIPS2_BASE_ADDR 0x53f00000 |
| 51 | #define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 52 | #define MX31_AIPS2_SIZE SZ_1M | ||
| 53 | #define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) | ||
| 54 | #define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) | ||
| 55 | #define MX31_FIRI_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x8c000) | ||
| 56 | #define MX31_GPT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x90000) | ||
| 57 | #define MX31_EPIT1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x94000) | ||
| 58 | #define MX31_EPIT2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x98000) | ||
| 59 | #define MX31_GPIO3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xa4000) | ||
| 60 | #define MX31_SCC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xac000) | ||
| 61 | #define MX31_SCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xae000) | ||
| 62 | #define MX31_SMN_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xaf000) | ||
| 63 | #define MX31_RNGA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xb0000) | ||
| 64 | #define MX31_IPU_CTRL_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc0000) | ||
| 65 | #define MX31_AUDMUX_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc4000) | ||
| 66 | #define MX31_MPEG4_ENC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xc8000) | ||
| 67 | #define MX31_GPIO1_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xcc000) | ||
| 68 | #define MX31_GPIO2_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd0000) | ||
| 69 | #define MX31_SDMA_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd4000) | ||
| 70 | #define MX31_RTC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xd8000) | ||
| 71 | #define MX31_WDOG_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xdc000) | ||
| 72 | #define MX31_PWM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xe0000) | ||
| 73 | #define MX31_RTIC_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0xec000) | ||
| 24 | 74 | ||
| 25 | #define MXC_INT_MPEG4_ENCODER 5 | 75 | #define MX31_ROMP_BASE_ADDR 0x60000000 |
| 26 | #define MXC_INT_FIRI 7 | 76 | #define MX31_ROMP_BASE_ADDR_VIRT 0xfc500000 |
| 77 | #define MX31_ROMP_SIZE SZ_1M | ||
| 78 | |||
| 79 | #define MX31_AVIC_BASE_ADDR 0x68000000 | ||
| 80 | #define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 81 | #define MX31_AVIC_SIZE SZ_1M | ||
| 82 | |||
| 83 | #define MX31_IPU_MEM_BASE_ADDR 0x70000000 | ||
| 84 | #define MX31_CSD0_BASE_ADDR 0x80000000 | ||
| 85 | #define MX31_CSD1_BASE_ADDR 0x90000000 | ||
| 86 | |||
| 87 | #define MX31_CS0_BASE_ADDR 0xa0000000 | ||
| 88 | #define MX31_CS1_BASE_ADDR 0xa8000000 | ||
| 89 | #define MX31_CS2_BASE_ADDR 0xb0000000 | ||
| 90 | #define MX31_CS3_BASE_ADDR 0xb2000000 | ||
| 91 | |||
| 92 | #define MX31_CS4_BASE_ADDR 0xb4000000 | ||
| 93 | #define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 | ||
| 94 | #define MX31_CS4_SIZE SZ_32M | ||
| 95 | |||
| 96 | #define MX31_CS5_BASE_ADDR 0xb6000000 | ||
| 97 | #define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 | ||
| 98 | #define MX31_CS5_SIZE SZ_32M | ||
| 99 | |||
| 100 | #define MX31_X_MEMC_BASE_ADDR 0xb8000000 | ||
| 101 | #define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
| 102 | #define MX31_X_MEMC_SIZE SZ_64K | ||
| 103 | #define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) | ||
| 104 | #define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) | ||
| 105 | #define MX31_WEIM_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x2000) | ||
| 106 | #define MX31_M3IF_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x3000) | ||
| 107 | #define MX31_EMI_CTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x4000) | ||
| 108 | #define MX31_PCMCIA_CTL_BASE_ADDR MX31_EMI_CTL_BASE_ADDR | ||
| 109 | |||
| 110 | #define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 | ||
| 111 | |||
| 112 | #define MX31_INT_I2C3 3 | ||
| 113 | #define MX31_INT_I2C2 4 | ||
| 114 | #define MX31_INT_MPEG4_ENCODER 5 | ||
| 115 | #define MX31_INT_RTIC 6 | ||
| 116 | #define MX31_INT_FIRI 7 | ||
| 27 | #define MX31_INT_MMC_SDHC2 8 | 117 | #define MX31_INT_MMC_SDHC2 8 |
| 28 | #define MXC_INT_MMC_SDHC1 9 | 118 | #define MX31_INT_MMC_SDHC1 9 |
| 119 | #define MX31_INT_I2C 10 | ||
| 29 | #define MX31_INT_SSI2 11 | 120 | #define MX31_INT_SSI2 11 |
| 30 | #define MX31_INT_SSI1 12 | 121 | #define MX31_INT_SSI1 12 |
| 31 | #define MXC_INT_MBX 16 | 122 | #define MX31_INT_CSPI2 13 |
| 32 | #define MXC_INT_CSPI3 17 | 123 | #define MX31_INT_CSPI1 14 |
| 33 | #define MXC_INT_SIM2 20 | 124 | #define MX31_INT_ATA 15 |
| 34 | #define MXC_INT_SIM1 21 | 125 | #define MX31_INT_MBX 16 |
| 35 | #define MXC_INT_CCM_DVFS 31 | 126 | #define MX31_INT_CSPI3 17 |
| 36 | #define MXC_INT_USB1 35 | 127 | #define MX31_INT_UART3 18 |
| 37 | #define MXC_INT_USB2 36 | 128 | #define MX31_INT_IIM 19 |
| 38 | #define MXC_INT_USB3 37 | 129 | #define MX31_INT_SIM2 20 |
| 39 | #define MXC_INT_USB4 38 | 130 | #define MX31_INT_SIM1 21 |
| 40 | #define MXC_INT_MSHC2 40 | 131 | #define MX31_INT_RNGA 22 |
| 41 | #define MXC_INT_UART4 46 | 132 | #define MX31_INT_EVTMON 23 |
| 42 | #define MXC_INT_UART5 47 | 133 | #define MX31_INT_KPP 24 |
| 43 | #define MXC_INT_CCM 53 | 134 | #define MX31_INT_RTC 25 |
| 44 | #define MXC_INT_PCMCIA 54 | 135 | #define MX31_INT_PWM 26 |
| 136 | #define MX31_INT_EPIT2 27 | ||
| 137 | #define MX31_INT_EPIT1 28 | ||
| 138 | #define MX31_INT_GPT 29 | ||
| 139 | #define MX31_INT_POWER_FAIL 30 | ||
| 140 | #define MX31_INT_CCM_DVFS 31 | ||
| 141 | #define MX31_INT_UART2 32 | ||
| 142 | #define MX31_INT_NANDFC 33 | ||
| 143 | #define MX31_INT_SDMA 34 | ||
| 144 | #define MX31_INT_USB1 35 | ||
| 145 | #define MX31_INT_USB2 36 | ||
| 146 | #define MX31_INT_USB3 37 | ||
| 147 | #define MX31_INT_USB4 38 | ||
| 148 | #define MX31_INT_MSHC1 39 | ||
| 149 | #define MX31_INT_MSHC2 40 | ||
| 150 | #define MX31_INT_IPU_ERR 41 | ||
| 151 | #define MX31_INT_IPU_SYN 42 | ||
| 152 | #define MX31_INT_UART1 45 | ||
| 153 | #define MX31_INT_UART4 46 | ||
| 154 | #define MX31_INT_UART5 47 | ||
| 155 | #define MX31_INT_ECT 48 | ||
| 156 | #define MX31_INT_SCC_SCM 49 | ||
| 157 | #define MX31_INT_SCC_SMN 50 | ||
| 158 | #define MX31_INT_GPIO2 51 | ||
| 159 | #define MX31_INT_GPIO1 52 | ||
| 160 | #define MX31_INT_CCM 53 | ||
| 161 | #define MX31_INT_PCMCIA 54 | ||
| 162 | #define MX31_INT_WDOG 55 | ||
| 163 | #define MX31_INT_GPIO3 56 | ||
| 164 | #define MX31_INT_EXT_POWER 58 | ||
| 165 | #define MX31_INT_EXT_TEMPER 59 | ||
| 166 | #define MX31_INT_EXT_SENSOR60 60 | ||
| 167 | #define MX31_INT_EXT_SENSOR61 61 | ||
| 168 | #define MX31_INT_EXT_WDOG 62 | ||
| 169 | #define MX31_INT_EXT_TV 63 | ||
| 170 | |||
| 171 | #define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 172 | |||
| 173 | /* silicon revisions specific to i.MX31 */ | ||
| 174 | #define MX31_CHIP_REV_1_0 0x10 | ||
| 175 | #define MX31_CHIP_REV_1_1 0x11 | ||
| 176 | #define MX31_CHIP_REV_1_2 0x12 | ||
| 177 | #define MX31_CHIP_REV_1_3 0x13 | ||
| 178 | #define MX31_CHIP_REV_2_0 0x20 | ||
| 179 | #define MX31_CHIP_REV_2_1 0x21 | ||
| 180 | #define MX31_CHIP_REV_2_2 0x22 | ||
| 181 | #define MX31_CHIP_REV_2_3 0x23 | ||
| 182 | #define MX31_CHIP_REV_3_0 0x30 | ||
| 183 | #define MX31_CHIP_REV_3_1 0x31 | ||
| 184 | #define MX31_CHIP_REV_3_2 0x32 | ||
| 185 | |||
| 186 | #define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0 | ||
| 187 | #define MX31_SYSTEM_REV_NUM 3 | ||
| 45 | 188 | ||
| 189 | /* these should go away */ | ||
| 190 | #define ATA_BASE_ADDR MX31_ATA_BASE_ADDR | ||
| 191 | #define UART4_BASE_ADDR MX31_UART4_BASE_ADDR | ||
| 192 | #define UART5_BASE_ADDR MX31_UART5_BASE_ADDR | ||
| 193 | #define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR | ||
| 194 | #define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR | ||
| 195 | #define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR | ||
| 196 | #define IIM_BASE_ADDR MX31_IIM_BASE_ADDR | ||
| 197 | #define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR | ||
| 198 | #define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR | ||
| 199 | #define SCM_BASE_ADDR MX31_SCM_BASE_ADDR | ||
| 200 | #define SMN_BASE_ADDR MX31_SMN_BASE_ADDR | ||
| 201 | #define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR | ||
| 202 | #define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER | ||
| 203 | #define MXC_INT_FIRI MX31_INT_FIRI | ||
| 204 | #define MXC_INT_MMC_SDHC1 MX31_INT_MMC_SDHC1 | ||
| 205 | #define MXC_INT_MBX MX31_INT_MBX | ||
| 206 | #define MXC_INT_CSPI3 MX31_INT_CSPI3 | ||
| 207 | #define MXC_INT_SIM2 MX31_INT_SIM2 | ||
| 208 | #define MXC_INT_SIM1 MX31_INT_SIM1 | ||
| 209 | #define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS | ||
| 210 | #define MXC_INT_USB1 MX31_INT_USB1 | ||
| 211 | #define MXC_INT_USB2 MX31_INT_USB2 | ||
| 212 | #define MXC_INT_USB3 MX31_INT_USB3 | ||
| 213 | #define MXC_INT_USB4 MX31_INT_USB4 | ||
| 214 | #define MXC_INT_MSHC2 MX31_INT_MSHC2 | ||
| 215 | #define MXC_INT_UART4 MX31_INT_UART4 | ||
| 216 | #define MXC_INT_UART5 MX31_INT_UART5 | ||
| 217 | #define MXC_INT_CCM MX31_INT_CCM | ||
| 218 | #define MXC_INT_PCMCIA MX31_INT_PCMCIA | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h index ab4cfec6c8ab..af871bce35b6 100644 --- a/arch/arm/plat-mxc/include/mach/mx35.h +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
| @@ -2,29 +2,196 @@ | |||
| 2 | * IRAM | 2 | * IRAM |
| 3 | */ | 3 | */ |
| 4 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ | 4 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ |
| 5 | #define MX35_IRAM_SIZE SZ_128K | 5 | #define MX35_IRAM_SIZE SZ_128K |
| 6 | 6 | ||
| 7 | #define MXC_FEC_BASE_ADDR 0x50038000 | 7 | #define MX35_L2CC_BASE_ADDR 0x30000000 |
| 8 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | 8 | #define MX35_L2CC_SIZE SZ_1M |
| 9 | #define MX35_NFC_BASE_ADDR 0xBB000000 | 9 | |
| 10 | #define MX35_AIPS1_BASE_ADDR 0x43f00000 | ||
| 11 | #define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000 | ||
| 12 | #define MX35_AIPS1_SIZE SZ_1M | ||
| 13 | #define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) | ||
| 14 | #define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) | ||
| 15 | #define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000) | ||
| 16 | #define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000) | ||
| 17 | #define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000) | ||
| 18 | #define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000) | ||
| 19 | #define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000) | ||
| 20 | #define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000) | ||
| 21 | #define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000) | ||
| 22 | #define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000) | ||
| 23 | #define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000) | ||
| 24 | #define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000) | ||
| 25 | #define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000) | ||
| 26 | #define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000) | ||
| 27 | #define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000) | ||
| 28 | #define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000) | ||
| 29 | #define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000) | ||
| 30 | #define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) | ||
| 31 | |||
| 32 | #define MX35_SPBA0_BASE_ADDR 0x50000000 | ||
| 33 | #define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000 | ||
| 34 | #define MX35_SPBA0_SIZE SZ_1M | ||
| 35 | #define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) | ||
| 36 | #define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) | ||
| 37 | #define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000) | ||
| 38 | #define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000) | ||
| 39 | #define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000) | ||
| 40 | #define MX35_FEC_BASE_ADDR 0x50038000 | ||
| 41 | #define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) | ||
| 42 | |||
| 43 | #define MX35_AIPS2_BASE_ADDR 0x53f00000 | ||
| 44 | #define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000 | ||
| 45 | #define MX35_AIPS2_SIZE SZ_1M | ||
| 46 | #define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) | ||
| 47 | #define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) | ||
| 48 | #define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000) | ||
| 49 | #define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000) | ||
| 50 | #define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) | ||
| 51 | #define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) | ||
| 52 | #define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) | ||
| 53 | #define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) | ||
| 54 | #define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) | ||
| 55 | #define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) | ||
| 56 | #define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000) | ||
| 57 | #define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000) | ||
| 58 | #define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000) | ||
| 59 | #define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000) | ||
| 60 | #define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000) | ||
| 61 | #define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) | ||
| 62 | #define MX35_OTG_BASE_ADDR 0x53ff4000 | ||
| 63 | |||
| 64 | #define MX35_ROMP_BASE_ADDR 0x60000000 | ||
| 65 | #define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000 | ||
| 66 | #define MX35_ROMP_SIZE SZ_1M | ||
| 67 | |||
| 68 | #define MX35_AVIC_BASE_ADDR 0x68000000 | ||
| 69 | #define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000 | ||
| 70 | #define MX35_AVIC_SIZE SZ_1M | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Memory regions and CS | ||
| 74 | */ | ||
| 75 | #define MX35_IPU_MEM_BASE_ADDR 0x70000000 | ||
| 76 | #define MX35_CSD0_BASE_ADDR 0x80000000 | ||
| 77 | #define MX35_CSD1_BASE_ADDR 0x90000000 | ||
| 78 | |||
| 79 | #define MX35_CS0_BASE_ADDR 0xa0000000 | ||
| 80 | #define MX35_CS1_BASE_ADDR 0xa8000000 | ||
| 81 | #define MX35_CS2_BASE_ADDR 0xb0000000 | ||
| 82 | #define MX35_CS3_BASE_ADDR 0xb2000000 | ||
| 83 | |||
| 84 | #define MX35_CS4_BASE_ADDR 0xb4000000 | ||
| 85 | #define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 | ||
| 86 | #define MX35_CS4_SIZE SZ_32M | ||
| 87 | |||
| 88 | #define MX35_CS5_BASE_ADDR 0xb6000000 | ||
| 89 | #define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 | ||
| 90 | #define MX35_CS5_SIZE SZ_32M | ||
| 91 | |||
| 92 | /* | ||
| 93 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 94 | */ | ||
| 95 | #define MX35_X_MEMC_BASE_ADDR 0xb8000000 | ||
| 96 | #define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000 | ||
| 97 | #define MX35_X_MEMC_SIZE SZ_64K | ||
| 98 | #define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) | ||
| 99 | #define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) | ||
| 100 | #define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000) | ||
| 101 | #define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000) | ||
| 102 | #define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR | ||
| 103 | |||
| 104 | #define MX35_NFC_BASE_ADDR 0xbb000000 | ||
| 105 | #define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 | ||
| 10 | 106 | ||
| 11 | /* | 107 | /* |
| 12 | * Interrupt numbers | 108 | * Interrupt numbers |
| 13 | */ | 109 | */ |
| 14 | #define MXC_INT_OWIRE 2 | 110 | #define MX35_INT_OWIRE 2 |
| 111 | #define MX35_INT_I2C3 3 | ||
| 112 | #define MX35_INT_I2C2 4 | ||
| 113 | #define MX35_INT_RTIC 6 | ||
| 15 | #define MX35_INT_MMC_SDHC1 7 | 114 | #define MX35_INT_MMC_SDHC1 7 |
| 16 | #define MXC_INT_MMC_SDHC2 8 | 115 | #define MX35_INT_MMC_SDHC2 8 |
| 17 | #define MXC_INT_MMC_SDHC3 9 | 116 | #define MX35_INT_MMC_SDHC3 9 |
| 117 | #define MX35_INT_I2C 10 | ||
| 18 | #define MX35_INT_SSI1 11 | 118 | #define MX35_INT_SSI1 11 |
| 19 | #define MX35_INT_SSI2 12 | 119 | #define MX35_INT_SSI2 12 |
| 20 | #define MXC_INT_GPU2D 16 | 120 | #define MX35_INT_CSPI2 13 |
| 21 | #define MXC_INT_ASRC 17 | 121 | #define MX35_INT_CSPI1 14 |
| 22 | #define MXC_INT_USBHS 35 | 122 | #define MX35_INT_ATA 15 |
| 23 | #define MXC_INT_USBOTG 37 | 123 | #define MX35_INT_GPU2D 16 |
| 24 | #define MXC_INT_ESAI 40 | 124 | #define MX35_INT_ASRC 17 |
| 25 | #define MXC_INT_CAN1 43 | 125 | #define MX35_INT_UART3 18 |
| 26 | #define MXC_INT_CAN2 44 | 126 | #define MX35_INT_IIM 19 |
| 27 | #define MXC_INT_MLB 46 | 127 | #define MX35_INT_RNGA 22 |
| 28 | #define MXC_INT_SPDIF 47 | 128 | #define MX35_INT_EVTMON 23 |
| 29 | #define MXC_INT_FEC 57 | 129 | #define MX35_INT_KPP 24 |
| 130 | #define MX35_INT_RTC 25 | ||
| 131 | #define MX35_INT_PWM 26 | ||
| 132 | #define MX35_INT_EPIT2 27 | ||
| 133 | #define MX35_INT_EPIT1 28 | ||
| 134 | #define MX35_INT_GPT 29 | ||
| 135 | #define MX35_INT_POWER_FAIL 30 | ||
| 136 | #define MX35_INT_UART2 32 | ||
| 137 | #define MX35_INT_NANDFC 33 | ||
| 138 | #define MX35_INT_SDMA 34 | ||
| 139 | #define MX35_INT_USBHS 35 | ||
| 140 | #define MX35_INT_USBOTG 37 | ||
| 141 | #define MX35_INT_MSHC1 39 | ||
| 142 | #define MX35_INT_ESAI 40 | ||
| 143 | #define MX35_INT_IPU_ERR 41 | ||
| 144 | #define MX35_INT_IPU_SYN 42 | ||
| 145 | #define MX35_INT_CAN1 43 | ||
| 146 | #define MX35_INT_CAN2 44 | ||
| 147 | #define MX35_INT_UART1 45 | ||
| 148 | #define MX35_INT_MLB 46 | ||
| 149 | #define MX35_INT_SPDIF 47 | ||
| 150 | #define MX35_INT_ECT 48 | ||
| 151 | #define MX35_INT_SCC_SCM 49 | ||
| 152 | #define MX35_INT_SCC_SMN 50 | ||
| 153 | #define MX35_INT_GPIO2 51 | ||
| 154 | #define MX35_INT_GPIO1 52 | ||
| 155 | #define MX35_INT_WDOG 55 | ||
| 156 | #define MX35_INT_GPIO3 56 | ||
| 157 | #define MX35_INT_FEC 57 | ||
| 158 | #define MX35_INT_EXT_POWER 58 | ||
| 159 | #define MX35_INT_EXT_TEMPER 59 | ||
| 160 | #define MX35_INT_EXT_SENSOR60 60 | ||
| 161 | #define MX35_INT_EXT_SENSOR61 61 | ||
| 162 | #define MX35_INT_EXT_WDOG 62 | ||
| 163 | #define MX35_INT_EXT_TV 63 | ||
| 164 | |||
| 165 | #define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 166 | |||
| 167 | /* silicon revisions specific to i.MX31 */ | ||
| 168 | #define MX35_CHIP_REV_1_0 0x10 | ||
| 169 | #define MX35_CHIP_REV_1_1 0x11 | ||
| 170 | #define MX35_CHIP_REV_1_2 0x12 | ||
| 171 | #define MX35_CHIP_REV_1_3 0x13 | ||
| 172 | #define MX35_CHIP_REV_2_0 0x20 | ||
| 173 | #define MX35_CHIP_REV_2_1 0x21 | ||
| 174 | #define MX35_CHIP_REV_2_2 0x22 | ||
| 175 | #define MX35_CHIP_REV_2_3 0x23 | ||
| 176 | #define MX35_CHIP_REV_3_0 0x30 | ||
| 177 | #define MX35_CHIP_REV_3_1 0x31 | ||
| 178 | #define MX35_CHIP_REV_3_2 0x32 | ||
| 179 | |||
| 180 | #define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0 | ||
| 181 | #define MX35_SYSTEM_REV_NUM 3 | ||
| 30 | 182 | ||
| 183 | /* these should go away */ | ||
| 184 | #define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR | ||
| 185 | #define MXC_INT_OWIRE MX35_INT_OWIRE | ||
| 186 | #define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2 | ||
| 187 | #define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3 | ||
| 188 | #define MXC_INT_GPU2D MX35_INT_GPU2D | ||
| 189 | #define MXC_INT_ASRC MX35_INT_ASRC | ||
| 190 | #define MXC_INT_USBHS MX35_INT_USBHS | ||
| 191 | #define MXC_INT_USBOTG MX35_INT_USBOTG | ||
| 192 | #define MXC_INT_ESAI MX35_INT_ESAI | ||
| 193 | #define MXC_INT_CAN1 MX35_INT_CAN1 | ||
| 194 | #define MXC_INT_CAN2 MX35_INT_CAN2 | ||
| 195 | #define MXC_INT_MLB MX35_INT_MLB | ||
| 196 | #define MXC_INT_SPDIF MX35_INT_SPDIF | ||
| 197 | #define MXC_INT_FEC MX35_INT_FEC | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h index 009f4440276b..be69272407ad 100644 --- a/arch/arm/plat-mxc/include/mach/mx3x.h +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
| @@ -34,120 +34,117 @@ | |||
| 34 | * C0000000 64M PCMCIA/CF | 34 | * C0000000 64M PCMCIA/CF |
| 35 | */ | 35 | */ |
| 36 | 36 | ||
| 37 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 38 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 39 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 40 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 41 | |||
| 42 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 43 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 44 | #define CS4_SIZE SZ_32M | ||
| 45 | |||
| 46 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 47 | #define CS5_BASE_ADDR_VIRT 0xF6000000 | ||
| 48 | #define CS5_SIZE SZ_32M | ||
| 49 | |||
| 50 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 51 | |||
| 52 | /* | 37 | /* |
| 53 | * L2CC | 38 | * L2CC |
| 54 | */ | 39 | */ |
| 55 | #define L2CC_BASE_ADDR 0x30000000 | 40 | #define MX3x_L2CC_BASE_ADDR 0x30000000 |
| 56 | #define L2CC_SIZE SZ_1M | 41 | #define MX3x_L2CC_SIZE SZ_1M |
| 57 | 42 | ||
| 58 | /* | 43 | /* |
| 59 | * AIPS 1 | 44 | * AIPS 1 |
| 60 | */ | 45 | */ |
| 61 | #define AIPS1_BASE_ADDR 0x43F00000 | 46 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 |
| 62 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | 47 | #define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000 |
| 63 | #define AIPS1_SIZE SZ_1M | 48 | #define MX3x_AIPS1_SIZE SZ_1M |
| 64 | 49 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) | |
| 65 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | 50 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) |
| 66 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | 51 | #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) |
| 67 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | 52 | #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) |
| 68 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | 53 | #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) |
| 69 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | 54 | #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) |
| 70 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | 55 | #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) |
| 71 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | 56 | #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) |
| 72 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | 57 | #define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) |
| 73 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | 58 | #define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) |
| 74 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | 59 | #define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) |
| 75 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | 60 | #define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) |
| 76 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | 61 | #define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) |
| 77 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | 62 | #define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) |
| 78 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | 63 | #define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) |
| 79 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | 64 | #define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) |
| 80 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | 65 | #define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) |
| 81 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | 66 | #define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) |
| 82 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 83 | 67 | ||
| 84 | /* | 68 | /* |
| 85 | * SPBA global module enabled #0 | 69 | * SPBA global module enabled #0 |
| 86 | */ | 70 | */ |
| 87 | #define SPBA0_BASE_ADDR 0x50000000 | 71 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 |
| 88 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | 72 | #define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000 |
| 89 | #define SPBA0_SIZE SZ_1M | 73 | #define MX3x_SPBA0_SIZE SZ_1M |
| 90 | 74 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) | |
| 91 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | 75 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) |
| 92 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | 76 | #define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) |
| 93 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | 77 | #define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) |
| 94 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | 78 | #define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) |
| 95 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | 79 | #define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) |
| 96 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 97 | 80 | ||
| 98 | /* | 81 | /* |
| 99 | * AIPS 2 | 82 | * AIPS 2 |
| 100 | */ | 83 | */ |
| 101 | #define AIPS2_BASE_ADDR 0x53F00000 | 84 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 |
| 102 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | 85 | #define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000 |
| 103 | #define AIPS2_SIZE SZ_1M | 86 | #define MX3x_AIPS2_SIZE SZ_1M |
| 104 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | 87 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) |
| 105 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | 88 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) |
| 106 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | 89 | #define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) |
| 107 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | 90 | #define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) |
| 108 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | 91 | #define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) |
| 109 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | 92 | #define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) |
| 110 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | 93 | #define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) |
| 111 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | 94 | #define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) |
| 112 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | 95 | #define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) |
| 113 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | 96 | #define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) |
| 114 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | 97 | #define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) |
| 115 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | 98 | #define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) |
| 116 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | 99 | #define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) |
| 117 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | 100 | #define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) |
| 118 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | 101 | #define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) |
| 119 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | 102 | #define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) |
| 120 | 103 | ||
| 121 | /* | 104 | /* |
| 122 | * ROMP and AVIC | 105 | * ROMP and AVIC |
| 123 | */ | 106 | */ |
| 124 | #define ROMP_BASE_ADDR 0x60000000 | 107 | #define MX3x_ROMP_BASE_ADDR 0x60000000 |
| 125 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | 108 | #define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000 |
| 126 | #define ROMP_SIZE SZ_1M | 109 | #define MX3x_ROMP_SIZE SZ_1M |
| 127 | 110 | ||
| 128 | #define AVIC_BASE_ADDR 0x68000000 | 111 | #define MX3x_AVIC_BASE_ADDR 0x68000000 |
| 129 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | 112 | #define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000 |
| 130 | #define AVIC_SIZE SZ_1M | 113 | #define MX3x_AVIC_SIZE SZ_1M |
| 131 | 114 | ||
| 132 | /* | 115 | /* |
| 133 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | 116 | * Memory regions and CS |
| 134 | */ | 117 | */ |
| 135 | #define X_MEMC_BASE_ADDR 0xB8000000 | 118 | #define MX3x_IPU_MEM_BASE_ADDR 0x70000000 |
| 136 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | 119 | #define MX3x_CSD0_BASE_ADDR 0x80000000 |
| 137 | #define X_MEMC_SIZE SZ_64K | 120 | #define MX3x_CSD1_BASE_ADDR 0x90000000 |
| 138 | 121 | ||
| 139 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | 122 | #define MX3x_CS0_BASE_ADDR 0xa0000000 |
| 140 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | 123 | #define MX3x_CS1_BASE_ADDR 0xa8000000 |
| 141 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | 124 | #define MX3x_CS2_BASE_ADDR 0xb0000000 |
| 142 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | 125 | #define MX3x_CS3_BASE_ADDR 0xb2000000 |
| 143 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | 126 | |
| 127 | #define MX3x_CS4_BASE_ADDR 0xb4000000 | ||
| 128 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 | ||
| 129 | #define MX3x_CS4_SIZE SZ_32M | ||
| 130 | |||
| 131 | #define MX3x_CS5_BASE_ADDR 0xb6000000 | ||
| 132 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 | ||
| 133 | #define MX3x_CS5_SIZE SZ_32M | ||
| 144 | 134 | ||
| 145 | /* | 135 | /* |
| 146 | * Memory regions and CS | 136 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
| 147 | */ | 137 | */ |
| 148 | #define IPU_MEM_BASE_ADDR 0x70000000 | 138 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 |
| 149 | #define CSD0_BASE_ADDR 0x80000000 | 139 | #define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000 |
| 150 | #define CSD1_BASE_ADDR 0x90000000 | 140 | #define MX3x_X_MEMC_SIZE SZ_64K |
| 141 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) | ||
| 142 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) | ||
| 143 | #define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) | ||
| 144 | #define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) | ||
| 145 | #define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR | ||
| 146 | |||
| 147 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 | ||
| 151 | 148 | ||
| 152 | /*! | 149 | /*! |
| 153 | * This macro defines the physical to virtual address mapping for all the | 150 | * This macro defines the physical to virtual address mapping for all the |
| @@ -202,74 +199,207 @@ | |||
| 202 | /* | 199 | /* |
| 203 | * Interrupt numbers | 200 | * Interrupt numbers |
| 204 | */ | 201 | */ |
| 205 | #define MXC_INT_I2C3 3 | 202 | #define MX3x_INT_I2C3 3 |
| 206 | #define MXC_INT_I2C2 4 | 203 | #define MX3x_INT_I2C2 4 |
| 207 | #define MXC_INT_RTIC 6 | 204 | #define MX3x_INT_RTIC 6 |
| 208 | #define MXC_INT_I2C 10 | 205 | #define MX3x_INT_I2C 10 |
| 209 | #define MXC_INT_CSPI2 13 | 206 | #define MX3x_INT_CSPI2 13 |
| 210 | #define MXC_INT_CSPI1 14 | 207 | #define MX3x_INT_CSPI1 14 |
| 211 | #define MXC_INT_ATA 15 | 208 | #define MX3x_INT_ATA 15 |
| 212 | #define MXC_INT_UART3 18 | 209 | #define MX3x_INT_UART3 18 |
| 213 | #define MXC_INT_IIM 19 | 210 | #define MX3x_INT_IIM 19 |
| 214 | #define MXC_INT_RNGA 22 | 211 | #define MX3x_INT_RNGA 22 |
| 215 | #define MXC_INT_EVTMON 23 | 212 | #define MX3x_INT_EVTMON 23 |
| 216 | #define MXC_INT_KPP 24 | 213 | #define MX3x_INT_KPP 24 |
| 217 | #define MXC_INT_RTC 25 | 214 | #define MX3x_INT_RTC 25 |
| 218 | #define MXC_INT_PWM 26 | 215 | #define MX3x_INT_PWM 26 |
| 219 | #define MXC_INT_EPIT2 27 | 216 | #define MX3x_INT_EPIT2 27 |
| 220 | #define MXC_INT_EPIT1 28 | 217 | #define MX3x_INT_EPIT1 28 |
| 221 | #define MXC_INT_GPT 29 | 218 | #define MX3x_INT_GPT 29 |
| 222 | #define MXC_INT_POWER_FAIL 30 | 219 | #define MX3x_INT_POWER_FAIL 30 |
| 223 | #define MXC_INT_UART2 32 | 220 | #define MX3x_INT_UART2 32 |
| 224 | #define MXC_INT_NANDFC 33 | 221 | #define MX3x_INT_NANDFC 33 |
| 225 | #define MXC_INT_SDMA 34 | 222 | #define MX3x_INT_SDMA 34 |
| 226 | #define MXC_INT_MSHC1 39 | 223 | #define MX3x_INT_MSHC1 39 |
| 227 | #define MXC_INT_IPU_ERR 41 | 224 | #define MX3x_INT_IPU_ERR 41 |
| 228 | #define MXC_INT_IPU_SYN 42 | 225 | #define MX3x_INT_IPU_SYN 42 |
| 229 | #define MXC_INT_UART1 45 | 226 | #define MX3x_INT_UART1 45 |
| 230 | #define MXC_INT_ECT 48 | 227 | #define MX3x_INT_ECT 48 |
| 231 | #define MXC_INT_SCC_SCM 49 | 228 | #define MX3x_INT_SCC_SCM 49 |
| 232 | #define MXC_INT_SCC_SMN 50 | 229 | #define MX3x_INT_SCC_SMN 50 |
| 233 | #define MXC_INT_GPIO2 51 | 230 | #define MX3x_INT_GPIO2 51 |
| 234 | #define MXC_INT_GPIO1 52 | 231 | #define MX3x_INT_GPIO1 52 |
| 235 | #define MXC_INT_WDOG 55 | 232 | #define MX3x_INT_WDOG 55 |
| 236 | #define MXC_INT_GPIO3 56 | 233 | #define MX3x_INT_GPIO3 56 |
| 237 | #define MXC_INT_EXT_POWER 58 | 234 | #define MX3x_INT_EXT_POWER 58 |
| 238 | #define MXC_INT_EXT_TEMPER 59 | 235 | #define MX3x_INT_EXT_TEMPER 59 |
| 239 | #define MXC_INT_EXT_SENSOR60 60 | 236 | #define MX3x_INT_EXT_SENSOR60 60 |
| 240 | #define MXC_INT_EXT_SENSOR61 61 | 237 | #define MX3x_INT_EXT_SENSOR61 61 |
| 241 | #define MXC_INT_EXT_WDOG 62 | 238 | #define MX3x_INT_EXT_WDOG 62 |
| 242 | #define MXC_INT_EXT_TV 63 | 239 | #define MX3x_INT_EXT_TV 63 |
| 243 | 240 | ||
| 244 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | 241 | #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ |
| 245 | 242 | ||
| 246 | /* silicon revisions specific to i.MX31 */ | 243 | /* silicon revisions specific to i.MX31 */ |
| 247 | #define CHIP_REV_1_0 0x10 | 244 | #define MX3x_CHIP_REV_1_0 0x10 |
| 248 | #define CHIP_REV_1_1 0x11 | 245 | #define MX3x_CHIP_REV_1_1 0x11 |
| 249 | #define CHIP_REV_1_2 0x12 | 246 | #define MX3x_CHIP_REV_1_2 0x12 |
| 250 | #define CHIP_REV_1_3 0x13 | 247 | #define MX3x_CHIP_REV_1_3 0x13 |
| 251 | #define CHIP_REV_2_0 0x20 | 248 | #define MX3x_CHIP_REV_2_0 0x20 |
| 252 | #define CHIP_REV_2_1 0x21 | 249 | #define MX3x_CHIP_REV_2_1 0x21 |
| 253 | #define CHIP_REV_2_2 0x22 | 250 | #define MX3x_CHIP_REV_2_2 0x22 |
| 254 | #define CHIP_REV_2_3 0x23 | 251 | #define MX3x_CHIP_REV_2_3 0x23 |
| 255 | #define CHIP_REV_3_0 0x30 | 252 | #define MX3x_CHIP_REV_3_0 0x30 |
| 256 | #define CHIP_REV_3_1 0x31 | 253 | #define MX3x_CHIP_REV_3_1 0x31 |
| 257 | #define CHIP_REV_3_2 0x32 | 254 | #define MX3x_CHIP_REV_3_2 0x32 |
| 258 | 255 | ||
| 259 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | 256 | #define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0 |
| 260 | #define SYSTEM_REV_NUM 3 | 257 | #define MX3x_SYSTEM_REV_NUM 3 |
| 261 | 258 | ||
| 262 | /* Mandatory defines used globally */ | 259 | /* Mandatory defines used globally */ |
| 263 | 260 | ||
| 264 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | 261 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) |
| 265 | 262 | ||
| 266 | extern unsigned int system_rev; | 263 | extern unsigned int mx31_cpu_rev; |
| 264 | extern void mx31_read_cpu_rev(void); | ||
| 267 | 265 | ||
| 268 | static inline int mx31_revision(void) | 266 | static inline int mx31_revision(void) |
| 269 | { | 267 | { |
| 270 | return system_rev; | 268 | return mx31_cpu_rev; |
| 271 | } | 269 | } |
| 272 | #endif | 270 | #endif |
| 273 | 271 | ||
| 274 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | 272 | /* these should go away */ |
| 273 | #define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR | ||
| 274 | #define L2CC_SIZE MX3x_L2CC_SIZE | ||
| 275 | #define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR | ||
| 276 | #define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT | ||
| 277 | #define AIPS1_SIZE MX3x_AIPS1_SIZE | ||
| 278 | #define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR | ||
| 279 | #define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR | ||
| 280 | #define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR | ||
| 281 | #define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR | ||
| 282 | #define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR | ||
| 283 | #define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR | ||
| 284 | #define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR | ||
| 285 | #define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR | ||
| 286 | #define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR | ||
| 287 | #define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR | ||
| 288 | #define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR | ||
| 289 | #define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR | ||
| 290 | #define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR | ||
| 291 | #define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR | ||
| 292 | #define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR | ||
| 293 | #define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR | ||
| 294 | #define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR | ||
| 295 | #define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR | ||
| 296 | #define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR | ||
| 297 | #define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT | ||
| 298 | #define SPBA0_SIZE MX3x_SPBA0_SIZE | ||
| 299 | #define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR | ||
| 300 | #define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR | ||
| 301 | #define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR | ||
| 302 | #define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR | ||
| 303 | #define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR | ||
| 304 | #define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR | ||
| 305 | #define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR | ||
| 306 | #define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT | ||
| 307 | #define AIPS2_SIZE MX3x_AIPS2_SIZE | ||
| 308 | #define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR | ||
| 309 | #define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR | ||
| 310 | #define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR | ||
| 311 | #define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR | ||
| 312 | #define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR | ||
| 313 | #define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR | ||
| 314 | #define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR | ||
| 315 | #define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR | ||
| 316 | #define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR | ||
| 317 | #define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR | ||
| 318 | #define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR | ||
| 319 | #define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR | ||
| 320 | #define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR | ||
| 321 | #define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR | ||
| 322 | #define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR | ||
| 323 | #define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR | ||
| 324 | #define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR | ||
| 325 | #define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT | ||
| 326 | #define ROMP_SIZE MX3x_ROMP_SIZE | ||
| 327 | #define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR | ||
| 328 | #define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT | ||
| 329 | #define AVIC_SIZE MX3x_AVIC_SIZE | ||
| 330 | #define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR | ||
| 331 | #define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR | ||
| 332 | #define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR | ||
| 333 | #define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR | ||
| 334 | #define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR | ||
| 335 | #define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR | ||
| 336 | #define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR | ||
| 337 | #define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR | ||
| 338 | #define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT | ||
| 339 | #define CS4_SIZE MX3x_CS4_SIZE | ||
| 340 | #define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR | ||
| 341 | #define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT | ||
| 342 | #define CS5_SIZE MX3x_CS5_SIZE | ||
| 343 | #define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR | ||
| 344 | #define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT | ||
| 345 | #define X_MEMC_SIZE MX3x_X_MEMC_SIZE | ||
| 346 | #define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR | ||
| 347 | #define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR | ||
| 348 | #define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR | ||
| 349 | #define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR | ||
| 350 | #define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR | ||
| 351 | #define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR | ||
| 352 | #define MXC_INT_I2C3 MX3x_INT_I2C3 | ||
| 353 | #define MXC_INT_I2C2 MX3x_INT_I2C2 | ||
| 354 | #define MXC_INT_RTIC MX3x_INT_RTIC | ||
| 355 | #define MXC_INT_I2C MX3x_INT_I2C | ||
| 356 | #define MXC_INT_CSPI2 MX3x_INT_CSPI2 | ||
| 357 | #define MXC_INT_CSPI1 MX3x_INT_CSPI1 | ||
| 358 | #define MXC_INT_ATA MX3x_INT_ATA | ||
| 359 | #define MXC_INT_UART3 MX3x_INT_UART3 | ||
| 360 | #define MXC_INT_IIM MX3x_INT_IIM | ||
| 361 | #define MXC_INT_RNGA MX3x_INT_RNGA | ||
| 362 | #define MXC_INT_EVTMON MX3x_INT_EVTMON | ||
| 363 | #define MXC_INT_KPP MX3x_INT_KPP | ||
| 364 | #define MXC_INT_RTC MX3x_INT_RTC | ||
| 365 | #define MXC_INT_PWM MX3x_INT_PWM | ||
| 366 | #define MXC_INT_EPIT2 MX3x_INT_EPIT2 | ||
| 367 | #define MXC_INT_EPIT1 MX3x_INT_EPIT1 | ||
| 368 | #define MXC_INT_GPT MX3x_INT_GPT | ||
| 369 | #define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL | ||
| 370 | #define MXC_INT_UART2 MX3x_INT_UART2 | ||
| 371 | #define MXC_INT_NANDFC MX3x_INT_NANDFC | ||
| 372 | #define MXC_INT_SDMA MX3x_INT_SDMA | ||
| 373 | #define MXC_INT_MSHC1 MX3x_INT_MSHC1 | ||
| 374 | #define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR | ||
| 375 | #define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN | ||
| 376 | #define MXC_INT_UART1 MX3x_INT_UART1 | ||
| 377 | #define MXC_INT_ECT MX3x_INT_ECT | ||
| 378 | #define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM | ||
| 379 | #define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN | ||
| 380 | #define MXC_INT_GPIO2 MX3x_INT_GPIO2 | ||
| 381 | #define MXC_INT_GPIO1 MX3x_INT_GPIO1 | ||
| 382 | #define MXC_INT_WDOG MX3x_INT_WDOG | ||
| 383 | #define MXC_INT_GPIO3 MX3x_INT_GPIO3 | ||
| 384 | #define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER | ||
| 385 | #define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER | ||
| 386 | #define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60 | ||
| 387 | #define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61 | ||
| 388 | #define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG | ||
| 389 | #define MXC_INT_EXT_TV MX3x_INT_EXT_TV | ||
| 390 | #define PROD_SIGNATURE MX3x_PROD_SIGNATURE | ||
| 391 | #define CHIP_REV_1_0 MX3x_CHIP_REV_1_0 | ||
| 392 | #define CHIP_REV_1_1 MX3x_CHIP_REV_1_1 | ||
| 393 | #define CHIP_REV_1_2 MX3x_CHIP_REV_1_2 | ||
| 394 | #define CHIP_REV_1_3 MX3x_CHIP_REV_1_3 | ||
| 395 | #define CHIP_REV_2_0 MX3x_CHIP_REV_2_0 | ||
| 396 | #define CHIP_REV_2_1 MX3x_CHIP_REV_2_1 | ||
| 397 | #define CHIP_REV_2_2 MX3x_CHIP_REV_2_2 | ||
| 398 | #define CHIP_REV_2_3 MX3x_CHIP_REV_2_3 | ||
| 399 | #define CHIP_REV_3_0 MX3x_CHIP_REV_3_0 | ||
| 400 | #define CHIP_REV_3_1 MX3x_CHIP_REV_3_1 | ||
| 401 | #define CHIP_REV_3_2 MX3x_CHIP_REV_3_2 | ||
| 402 | #define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN | ||
| 403 | #define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM | ||
| 275 | 404 | ||
| 405 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/ulpi.h b/arch/arm/plat-mxc/include/mach/ulpi.h new file mode 100644 index 000000000000..96b6ab4c40c3 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/ulpi.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __MACH_ULPI_H | ||
| 2 | #define __MACH_ULPI_H | ||
| 3 | |||
| 4 | extern struct otg_io_access_ops mxc_ulpi_access_ops; | ||
| 5 | |||
| 6 | #endif /* __MACH_ULPI_H */ | ||
| 7 | |||
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 082a3908256b..4d5d395ad63b 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h | |||
| @@ -83,6 +83,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |||
| 83 | case MACH_TYPE_MX27ADS: | 83 | case MACH_TYPE_MX27ADS: |
| 84 | case MACH_TYPE_PCM038: | 84 | case MACH_TYPE_PCM038: |
| 85 | case MACH_TYPE_MX21ADS: | 85 | case MACH_TYPE_MX21ADS: |
| 86 | case MACH_TYPE_PCA100: | ||
| 87 | case MACH_TYPE_MXT_TD60: | ||
| 86 | uart_base = MX2X_UART1_BASE_ADDR; | 88 | uart_base = MX2X_UART1_BASE_ADDR; |
| 87 | break; | 89 | break; |
| 88 | case MACH_TYPE_MX31LITE: | 90 | case MACH_TYPE_MX31LITE: |
| @@ -94,6 +96,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) | |||
| 94 | case MACH_TYPE_MX31ADS: | 96 | case MACH_TYPE_MX31ADS: |
| 95 | case MACH_TYPE_MX35_3DS: | 97 | case MACH_TYPE_MX35_3DS: |
| 96 | case MACH_TYPE_PCM043: | 98 | case MACH_TYPE_PCM043: |
| 99 | case MACH_TYPE_LILLY1131: | ||
| 97 | uart_base = MX3X_UART1_BASE_ADDR; | 100 | uart_base = MX3X_UART1_BASE_ADDR; |
| 98 | break; | 101 | break; |
| 99 | case MACH_TYPE_MAGX_ZN5: | 102 | case MACH_TYPE_MAGX_ZN5: |
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 851ca99bf1b1..b318c6a222d5 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c | |||
| @@ -31,19 +31,11 @@ | |||
| 31 | 31 | ||
| 32 | static void __iomem *base; | 32 | static void __iomem *base; |
| 33 | 33 | ||
| 34 | static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; | ||
| 35 | |||
| 36 | /* | 34 | /* |
| 37 | * setups a single pin: | 35 | * setups a single pad in the iomuxer |
| 38 | * - reserves the pin so that it is not claimed by another driver | ||
| 39 | * - setups the iomux according to the configuration | ||
| 40 | */ | 36 | */ |
| 41 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad) | 37 | int mxc_iomux_v3_setup_pad(struct pad_desc *pad) |
| 42 | { | 38 | { |
| 43 | unsigned int pad_ofs = pad->pad_ctrl_ofs; | ||
| 44 | |||
| 45 | if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) | ||
| 46 | return -EBUSY; | ||
| 47 | if (pad->mux_ctrl_ofs) | 39 | if (pad->mux_ctrl_ofs) |
| 48 | __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); | 40 | __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); |
| 49 | 41 | ||
| @@ -66,37 +58,13 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) | |||
| 66 | for (i = 0; i < count; i++) { | 58 | for (i = 0; i < count; i++) { |
| 67 | ret = mxc_iomux_v3_setup_pad(p); | 59 | ret = mxc_iomux_v3_setup_pad(p); |
| 68 | if (ret) | 60 | if (ret) |
| 69 | goto setup_error; | 61 | return ret; |
| 70 | p++; | 62 | p++; |
| 71 | } | 63 | } |
| 72 | return 0; | 64 | return 0; |
| 73 | |||
| 74 | setup_error: | ||
| 75 | mxc_iomux_v3_release_multiple_pads(pad_list, i); | ||
| 76 | return ret; | ||
| 77 | } | 65 | } |
| 78 | EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); | 66 | EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); |
| 79 | 67 | ||
| 80 | void mxc_iomux_v3_release_pad(struct pad_desc *pad) | ||
| 81 | { | ||
| 82 | unsigned int pad_ofs = pad->pad_ctrl_ofs; | ||
| 83 | |||
| 84 | clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map); | ||
| 85 | } | ||
| 86 | EXPORT_SYMBOL(mxc_iomux_v3_release_pad); | ||
| 87 | |||
| 88 | void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) | ||
| 89 | { | ||
| 90 | struct pad_desc *p = pad_list; | ||
| 91 | int i; | ||
| 92 | |||
| 93 | for (i = 0; i < count; i++) { | ||
| 94 | mxc_iomux_v3_release_pad(p); | ||
| 95 | p++; | ||
| 96 | } | ||
| 97 | } | ||
| 98 | EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); | ||
| 99 | |||
| 100 | void mxc_iomux_v3_init(void __iomem *iomux_v3_base) | 68 | void mxc_iomux_v3_init(void __iomem *iomux_v3_base) |
| 101 | { | 69 | { |
| 102 | base = iomux_v3_base; | 70 | base = iomux_v3_base; |
diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c new file mode 100644 index 000000000000..582c6dfaba4a --- /dev/null +++ b/arch/arm/plat-mxc/ulpi.c | |||
| @@ -0,0 +1,113 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | ||
| 3 | * Copyright 2009 Daniel Mack <daniel@caiaq.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/usb/otg.h> | ||
| 25 | |||
| 26 | #include <mach/ulpi.h> | ||
| 27 | |||
| 28 | /* ULPIVIEW register bits */ | ||
| 29 | #define ULPIVW_WU (1 << 31) /* Wakeup */ | ||
| 30 | #define ULPIVW_RUN (1 << 30) /* read/write run */ | ||
| 31 | #define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */ | ||
| 32 | #define ULPIVW_SS (1 << 27) /* SyncState */ | ||
| 33 | #define ULPIVW_PORT_MASK 0x07 /* Port field */ | ||
| 34 | #define ULPIVW_PORT_SHIFT 24 | ||
| 35 | #define ULPIVW_ADDR_MASK 0xff /* data address field */ | ||
| 36 | #define ULPIVW_ADDR_SHIFT 16 | ||
| 37 | #define ULPIVW_RDATA_MASK 0xff /* read data field */ | ||
| 38 | #define ULPIVW_RDATA_SHIFT 8 | ||
| 39 | #define ULPIVW_WDATA_MASK 0xff /* write data field */ | ||
| 40 | #define ULPIVW_WDATA_SHIFT 0 | ||
| 41 | |||
| 42 | static int ulpi_poll(void __iomem *view, u32 bit) | ||
| 43 | { | ||
| 44 | int timeout = 10000; | ||
| 45 | |||
| 46 | while (timeout--) { | ||
| 47 | u32 data = __raw_readl(view); | ||
| 48 | |||
| 49 | if (!(data & bit)) | ||
| 50 | return 0; | ||
| 51 | |||
| 52 | cpu_relax(); | ||
| 53 | }; | ||
| 54 | |||
| 55 | printk(KERN_WARNING "timeout polling for ULPI device\n"); | ||
| 56 | |||
| 57 | return -ETIMEDOUT; | ||
| 58 | } | ||
| 59 | |||
| 60 | static int ulpi_read(struct otg_transceiver *otg, u32 reg) | ||
| 61 | { | ||
| 62 | int ret; | ||
| 63 | void __iomem *view = otg->io_priv; | ||
| 64 | |||
| 65 | /* make sure interface is running */ | ||
| 66 | if (!(__raw_readl(view) & ULPIVW_SS)) { | ||
| 67 | __raw_writel(ULPIVW_WU, view); | ||
| 68 | |||
| 69 | /* wait for wakeup */ | ||
| 70 | ret = ulpi_poll(view, ULPIVW_WU); | ||
| 71 | if (ret) | ||
| 72 | return ret; | ||
| 73 | } | ||
| 74 | |||
| 75 | /* read the register */ | ||
| 76 | __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view); | ||
| 77 | |||
| 78 | /* wait for completion */ | ||
| 79 | ret = ulpi_poll(view, ULPIVW_RUN); | ||
| 80 | if (ret) | ||
| 81 | return ret; | ||
| 82 | |||
| 83 | return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK; | ||
| 84 | } | ||
| 85 | |||
| 86 | static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg) | ||
| 87 | { | ||
| 88 | int ret; | ||
| 89 | void __iomem *view = otg->io_priv; | ||
| 90 | |||
| 91 | /* make sure the interface is running */ | ||
| 92 | if (!(__raw_readl(view) & ULPIVW_SS)) { | ||
| 93 | __raw_writel(ULPIVW_WU, view); | ||
| 94 | /* wait for wakeup */ | ||
| 95 | ret = ulpi_poll(view, ULPIVW_WU); | ||
| 96 | if (ret) | ||
| 97 | return ret; | ||
| 98 | } | ||
| 99 | |||
| 100 | __raw_writel((ULPIVW_RUN | ULPIVW_WRITE | | ||
| 101 | (reg << ULPIVW_ADDR_SHIFT) | | ||
| 102 | ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view); | ||
| 103 | |||
| 104 | /* wait for completion */ | ||
| 105 | return ulpi_poll(view, ULPIVW_RUN); | ||
| 106 | } | ||
| 107 | |||
| 108 | struct otg_io_access_ops mxc_ulpi_access_ops = { | ||
| 109 | .read = ulpi_read, | ||
| 110 | .write = ulpi_write, | ||
| 111 | }; | ||
| 112 | EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops); | ||
| 113 | |||
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h index 3478eae32d8a..3478eae32d8a 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx_nand.h +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | |||
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 8931c5f0e46b..e139a72c2149 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig | |||
| @@ -159,6 +159,12 @@ config S3C_GPIO_CFG_S3C64XX | |||
| 159 | Internal configuration to enable S3C64XX style GPIO configuration | 159 | Internal configuration to enable S3C64XX style GPIO configuration |
| 160 | functions. | 160 | functions. |
| 161 | 161 | ||
| 162 | config S5P_GPIO_CFG_S5PC1XX | ||
| 163 | bool | ||
| 164 | help | ||
| 165 | Internal configuration to enable S5PC1XX style GPIO configuration | ||
| 166 | functions. | ||
| 167 | |||
| 162 | # DMA | 168 | # DMA |
| 163 | 169 | ||
| 164 | config S3C_DMA | 170 | config S3C_DMA |
| @@ -178,6 +184,11 @@ config S3C_DEV_HSMMC1 | |||
| 178 | help | 184 | help |
| 179 | Compile in platform device definitions for HSMMC channel 1 | 185 | Compile in platform device definitions for HSMMC channel 1 |
| 180 | 186 | ||
| 187 | config S3C_DEV_HSMMC2 | ||
| 188 | bool | ||
| 189 | help | ||
| 190 | Compile in platform device definitions for HSMMC channel 2 | ||
| 191 | |||
| 181 | config S3C_DEV_I2C1 | 192 | config S3C_DEV_I2C1 |
| 182 | bool | 193 | bool |
| 183 | help | 194 | help |
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 3c09109e9e84..50444da98425 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
| @@ -36,6 +36,7 @@ obj-$(CONFIG_HAVE_PWM) += pwm.o | |||
| 36 | 36 | ||
| 37 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | 37 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o |
| 38 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | 38 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o |
| 39 | obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o | ||
| 39 | obj-y += dev-i2c0.o | 40 | obj-y += dev-i2c0.o |
| 40 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | 41 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
| 41 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | 42 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c index 4d01ef1a25dd..619cfa82dcab 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-s3c/clock.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/clock.c | 1 | /* linux/arch/arm/plat-s3c24xx/clock.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004-2005 Simtec Electronics | 3 | * Copyright 2004-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * S3C24XX Core clock control support | 6 | * S3C24XX Core clock control support |
| @@ -337,7 +337,7 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | |||
| 337 | 337 | ||
| 338 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | 338 | int __init s3c24xx_register_baseclocks(unsigned long xtal) |
| 339 | { | 339 | { |
| 340 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | 340 | printk(KERN_INFO "S3C24XX Clocks, Copyright 2004 Simtec Electronics\n"); |
| 341 | 341 | ||
| 342 | clk_xtal.rate = xtal; | 342 | clk_xtal.rate = xtal; |
| 343 | 343 | ||
diff --git a/arch/arm/plat-s3c/dev-hsmmc2.c b/arch/arm/plat-s3c/dev-hsmmc2.c new file mode 100644 index 000000000000..824580bc0e06 --- /dev/null +++ b/arch/arm/plat-s3c/dev-hsmmc2.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dev-hsmmc2.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Samsung Electronics | ||
| 4 | * Copyright (c) 2009 Maurus Cuelenaere | ||
| 5 | * | ||
| 6 | * Based on arch/arm/plat-s3c/dev-hsmmc1.c | ||
| 7 | * original file Copyright (c) 2008 Simtec Electronics | ||
| 8 | * | ||
| 9 | * S3C series device definition for hsmmc device 2 | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/mmc/host.h> | ||
| 19 | |||
| 20 | #include <mach/map.h> | ||
| 21 | #include <plat/sdhci.h> | ||
| 22 | #include <plat/devs.h> | ||
| 23 | |||
| 24 | #define S3C_SZ_HSMMC (0x1000) | ||
| 25 | |||
| 26 | static struct resource s3c_hsmmc2_resource[] = { | ||
| 27 | [0] = { | ||
| 28 | .start = S3C_PA_HSMMC2, | ||
| 29 | .end = S3C_PA_HSMMC2 + S3C_SZ_HSMMC - 1, | ||
| 30 | .flags = IORESOURCE_MEM, | ||
| 31 | }, | ||
| 32 | [1] = { | ||
| 33 | .start = IRQ_HSMMC2, | ||
| 34 | .end = IRQ_HSMMC2, | ||
| 35 | .flags = IORESOURCE_IRQ, | ||
| 36 | } | ||
| 37 | }; | ||
| 38 | |||
| 39 | static u64 s3c_device_hsmmc2_dmamask = 0xffffffffUL; | ||
| 40 | |||
| 41 | struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = { | ||
| 42 | .max_width = 4, | ||
| 43 | .host_caps = (MMC_CAP_4_BIT_DATA | | ||
| 44 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), | ||
| 45 | }; | ||
| 46 | |||
| 47 | struct platform_device s3c_device_hsmmc2 = { | ||
| 48 | .name = "s3c-sdhci", | ||
| 49 | .id = 2, | ||
| 50 | .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource), | ||
| 51 | .resource = s3c_hsmmc2_resource, | ||
| 52 | .dev = { | ||
| 53 | .dma_mask = &s3c_device_hsmmc2_dmamask, | ||
| 54 | .coherent_dma_mask = 0xffffffffUL, | ||
| 55 | .platform_data = &s3c_hsmmc2_def_platdata, | ||
| 56 | }, | ||
| 57 | }; | ||
| 58 | |||
| 59 | void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd) | ||
| 60 | { | ||
| 61 | struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata; | ||
| 62 | |||
| 63 | set->max_width = pd->max_width; | ||
| 64 | |||
| 65 | if (pd->cfg_gpio) | ||
| 66 | set->cfg_gpio = pd->cfg_gpio; | ||
| 67 | if (pd->cfg_card) | ||
| 68 | set->cfg_card = pd->cfg_card; | ||
| 69 | } | ||
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c index 428372868fbb..4c761529b949 100644 --- a/arch/arm/plat-s3c/dev-i2c0.c +++ b/arch/arm/plat-s3c/dev-i2c0.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dev-i2c0.c | 1 | /* linux/arch/arm/plat-s3c/dev-i2c0.c |
| 2 | * | 2 | * |
| 3 | * Copyright 2008,2009 Simtec Electronics | 3 | * Copyright 2008-2009 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c index 8349c462788c..d44f79110506 100644 --- a/arch/arm/plat-s3c/dev-i2c1.c +++ b/arch/arm/plat-s3c/dev-i2c1.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dev-i2c1.c | 1 | /* linux/arch/arm/plat-s3c/dev-i2c1.c |
| 2 | * | 2 | * |
| 3 | * Copyright 2008,2009 Simtec Electronics | 3 | * Copyright 2008-2009 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c index 4e5323732434..e771e77dcd54 100644 --- a/arch/arm/plat-s3c/dev-nand.c +++ b/arch/arm/plat-s3c/dev-nand.c | |||
| @@ -9,8 +9,12 @@ | |||
| 9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
| 10 | #include <linux/platform_device.h> | 10 | #include <linux/platform_device.h> |
| 11 | 11 | ||
| 12 | #include <linux/mtd/mtd.h> | ||
| 13 | #include <linux/mtd/partitions.h> | ||
| 14 | |||
| 12 | #include <mach/map.h> | 15 | #include <mach/map.h> |
| 13 | #include <plat/devs.h> | 16 | #include <plat/devs.h> |
| 17 | #include <plat/nand.h> | ||
| 14 | 18 | ||
| 15 | static struct resource s3c_nand_resource[] = { | 19 | static struct resource s3c_nand_resource[] = { |
| 16 | [0] = { | 20 | [0] = { |
| @@ -28,3 +32,96 @@ struct platform_device s3c_device_nand = { | |||
| 28 | }; | 32 | }; |
| 29 | 33 | ||
| 30 | EXPORT_SYMBOL(s3c_device_nand); | 34 | EXPORT_SYMBOL(s3c_device_nand); |
| 35 | |||
| 36 | /** | ||
| 37 | * s3c_nand_copy_set() - copy nand set data | ||
| 38 | * @set: The new structure, directly copied from the old. | ||
| 39 | * | ||
| 40 | * Copy all the fields from the NAND set field from what is probably __initdata | ||
| 41 | * to new kernel memory. The code returns 0 if the copy happened correctly or | ||
| 42 | * an error code for the calling function to display. | ||
| 43 | * | ||
| 44 | * Note, we currently do not try and look to see if we've already copied the | ||
| 45 | * data in a previous set. | ||
| 46 | */ | ||
| 47 | static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set) | ||
| 48 | { | ||
| 49 | void *ptr; | ||
| 50 | int size; | ||
| 51 | |||
| 52 | size = sizeof(struct mtd_partition) * set->nr_partitions; | ||
| 53 | if (size) { | ||
| 54 | ptr = kmemdup(set->partitions, size, GFP_KERNEL); | ||
| 55 | set->partitions = ptr; | ||
| 56 | |||
| 57 | if (!ptr) | ||
| 58 | return -ENOMEM; | ||
| 59 | } | ||
| 60 | |||
| 61 | size = sizeof(int) * set->nr_chips; | ||
| 62 | if (size) { | ||
| 63 | ptr = kmemdup(set->nr_map, size, GFP_KERNEL); | ||
| 64 | set->nr_map = ptr; | ||
| 65 | |||
| 66 | if (!ptr) | ||
| 67 | return -ENOMEM; | ||
| 68 | } | ||
| 69 | |||
| 70 | if (set->ecc_layout) { | ||
| 71 | ptr = kmemdup(set->ecc_layout, | ||
| 72 | sizeof(struct nand_ecclayout), GFP_KERNEL); | ||
| 73 | set->ecc_layout = ptr; | ||
| 74 | |||
| 75 | if (!ptr) | ||
| 76 | return -ENOMEM; | ||
| 77 | } | ||
| 78 | |||
| 79 | return 0; | ||
| 80 | } | ||
| 81 | |||
| 82 | void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand) | ||
| 83 | { | ||
| 84 | struct s3c2410_platform_nand *npd; | ||
| 85 | int size; | ||
| 86 | int ret; | ||
| 87 | |||
| 88 | /* note, if we get a failure in allocation, we simply drop out of the | ||
| 89 | * function. If there is so little memory available at initialisation | ||
| 90 | * time then there is little chance the system is going to run. | ||
| 91 | */ | ||
| 92 | |||
| 93 | npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL); | ||
| 94 | if (!npd) { | ||
| 95 | printk(KERN_ERR "%s: failed copying platform data\n", __func__); | ||
| 96 | return; | ||
| 97 | } | ||
| 98 | |||
| 99 | /* now see if we need to copy any of the nand set data */ | ||
| 100 | |||
| 101 | size = sizeof(struct s3c2410_nand_set) * npd->nr_sets; | ||
| 102 | if (size) { | ||
| 103 | struct s3c2410_nand_set *from = npd->sets; | ||
| 104 | struct s3c2410_nand_set *to; | ||
| 105 | int i; | ||
| 106 | |||
| 107 | to = kmemdup(from, size, GFP_KERNEL); | ||
| 108 | npd->sets = to; /* set, even if we failed */ | ||
| 109 | |||
| 110 | if (!to) { | ||
| 111 | printk(KERN_ERR "%s: no memory for sets\n", __func__); | ||
| 112 | return; | ||
| 113 | } | ||
| 114 | |||
| 115 | for (i = 0; i < npd->nr_sets; i++) { | ||
| 116 | ret = s3c_nand_copy_set(to); | ||
| 117 | if (!ret) { | ||
| 118 | printk(KERN_ERR "%s: failed to copy set %d\n", | ||
| 119 | __func__, i); | ||
| 120 | return; | ||
| 121 | } | ||
| 122 | to++; | ||
| 123 | } | ||
| 124 | } | ||
| 125 | } | ||
| 126 | |||
| 127 | EXPORT_SYMBOL_GPL(s3c_nand_set_platdata); | ||
diff --git a/arch/arm/plat-s3c/dma.c b/arch/arm/plat-s3c/dma.c index c9db75c06af5..a995850cd9d5 100644 --- a/arch/arm/plat-s3c/dma.c +++ b/arch/arm/plat-s3c/dma.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dma.c | 1 | /* linux/arch/arm/plat-s3c/dma.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003-2005,2006,2009 Simtec Electronics | 3 | * Copyright (c) 2003-2009 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c/include/plat/audio-simtec.h index 0f440b9168db..53a93656d5db 100644 --- a/arch/arm/plat-s3c/include/plat/audio-simtec.h +++ b/arch/arm/plat-s3c/include/plat/audio-simtec.h | |||
| @@ -33,5 +33,5 @@ struct s3c24xx_audio_simtec_pdata { | |||
| 33 | void (*startup)(void); | 33 | void (*startup)(void); |
| 34 | }; | 34 | }; |
| 35 | 35 | ||
| 36 | extern int simtec_audio_add(const char *codec_name, | 36 | extern int simtec_audio_add(const char *codec_name, bool has_lr_routing, |
| 37 | struct s3c24xx_audio_simtec_pdata *pdata); | 37 | struct s3c24xx_audio_simtec_pdata *pdata); |
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h index 7b982b7f28cd..94eb06a2ea5c 100644 --- a/arch/arm/plat-s3c/include/plat/cpu-freq.h +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | 1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2007 Simtec Electronics | 3 | * Copyright (c) 2006-2007 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index fbc3d498e02e..d1131ca11e97 100644 --- a/arch/arm/plat-s3c/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h | |||
| @@ -12,6 +12,9 @@ | |||
| 12 | 12 | ||
| 13 | /* todo - fix when rmk changes iodescs to use `void __iomem *` */ | 13 | /* todo - fix when rmk changes iodescs to use `void __iomem *` */ |
| 14 | 14 | ||
| 15 | #ifndef __SAMSUNG_PLAT_CPU_H | ||
| 16 | #define __SAMSUNG_PLAT_CPU_H | ||
| 17 | |||
| 15 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } | 18 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } |
| 16 | 19 | ||
| 17 | #ifndef MHZ | 20 | #ifndef MHZ |
| @@ -73,3 +76,6 @@ extern struct sysdev_class s3c2443_sysclass; | |||
| 73 | extern struct sysdev_class s3c6410_sysclass; | 76 | extern struct sysdev_class s3c6410_sysclass; |
| 74 | extern struct sysdev_class s3c64xx_sysclass; | 77 | extern struct sysdev_class s3c64xx_sysclass; |
| 75 | 78 | ||
| 79 | extern void (*s5pc1xx_idle)(void); | ||
| 80 | |||
| 81 | #endif | ||
diff --git a/arch/arm/plat-s3c/include/plat/dma.h b/arch/arm/plat-s3c/include/plat/dma.h index 34dba98f08e1..e429d10be3ad 100644 --- a/arch/arm/plat-s3c/include/plat/dma.h +++ b/arch/arm/plat-s3c/include/plat/dma.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/dma.h | 1 | /* arch/arm/plat-s3c/include/plat/dma.h |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2003,2004,2006 Simtec Electronics | 3 | * Copyright (C) 2003-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Samsung S3C DMA support | 6 | * Samsung S3C DMA support |
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h index 214ff561b0dd..f8db87930f8b 100644 --- a/arch/arm/plat-s3c/include/plat/fb.h +++ b/arch/arm/plat-s3c/include/plat/fb.h | |||
| @@ -70,4 +70,11 @@ extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); | |||
| 70 | */ | 70 | */ |
| 71 | extern void s3c64xx_fb_gpio_setup_24bpp(void); | 71 | extern void s3c64xx_fb_gpio_setup_24bpp(void); |
| 72 | 72 | ||
| 73 | /** | ||
| 74 | * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD | ||
| 75 | * | ||
| 76 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | ||
| 77 | */ | ||
| 78 | extern void s5pc100_fb_gpio_setup_24bpp(void); | ||
| 79 | |||
| 73 | #endif /* __PLAT_S3C_FB_H */ | 80 | #endif /* __PLAT_S3C_FB_H */ |
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h index 67450f115748..3083df00dee6 100644 --- a/arch/arm/plat-s3c/include/plat/iic.h +++ b/arch/arm/plat-s3c/include/plat/iic.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/iic.h | 1 | /* arch/arm/plat-s3c/include/plat/iic.h |
| 2 | * | 2 | * |
| 3 | * Copyright 2004,2009 Simtec Electronics | 3 | * Copyright 2004-2009 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * S3C - I2C Controller platform_device info | 6 | * S3C - I2C Controller platform_device info |
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index 18f958801e64..065985978413 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h | |||
| @@ -55,3 +55,11 @@ struct s3c2410_platform_nand { | |||
| 55 | int chip); | 55 | int chip); |
| 56 | }; | 56 | }; |
| 57 | 57 | ||
| 58 | /** | ||
| 59 | * s3c_nand_set_platdata() - register NAND platform data. | ||
| 60 | * @nand: The NAND platform data to register with s3c_device_nand. | ||
| 61 | * | ||
| 62 | * This function copies the given NAND platform data, @nand and registers | ||
| 63 | * it with the s3c_device_nand. This allows @nand to be __initdata. | ||
| 64 | */ | ||
| 65 | extern void s3c_nand_set_platdata(struct s3c2410_platform_nand *nand); | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb-v4.h b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h new file mode 100644 index 000000000000..a60ed0d06c94 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-fb-v4.h | |||
| @@ -0,0 +1,235 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/regs-fb-v4.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C64XX - new-style framebuffer register definitions | ||
| 9 | * | ||
| 10 | * This is the register set for the new style framebuffer interface | ||
| 11 | * found from the S3C2443 onwards and specifically the S3C64XX series | ||
| 12 | * S3C6400 and S3C6410. | ||
| 13 | * | ||
| 14 | * The file contains the cpu specific items which change between whichever | ||
| 15 | * architecture is selected. See <plat/regs-fb.h> for the core definitions | ||
| 16 | * that are the same. | ||
| 17 | * | ||
| 18 | * This program is free software; you can redistribute it and/or modify | ||
| 19 | * it under the terms of the GNU General Public License version 2 as | ||
| 20 | * published by the Free Software Foundation. | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* include the core definitions here, in case we really do need to | ||
| 24 | * override them at a later date. | ||
| 25 | */ | ||
| 26 | |||
| 27 | #include <plat/regs-fb.h> | ||
| 28 | |||
| 29 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | ||
| 30 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
| 31 | |||
| 32 | /* Video timing controls */ | ||
| 33 | #define VIDTCON0 (0x10) | ||
| 34 | #define VIDTCON1 (0x14) | ||
| 35 | #define VIDTCON2 (0x18) | ||
| 36 | |||
| 37 | /* Window position controls */ | ||
| 38 | |||
| 39 | #define WINCON(_win) (0x20 + ((_win) * 4)) | ||
| 40 | |||
| 41 | /* OSD1 and OSD4 do not have register D */ | ||
| 42 | |||
| 43 | #define VIDOSD_A(_win) (0x40 + ((_win) * 16)) | ||
| 44 | #define VIDOSD_B(_win) (0x44 + ((_win) * 16)) | ||
| 45 | #define VIDOSD_C(_win) (0x48 + ((_win) * 16)) | ||
| 46 | #define VIDOSD_D(_win) (0x4C + ((_win) * 16)) | ||
| 47 | |||
| 48 | |||
| 49 | #define VIDINTCON0 (0x130) | ||
| 50 | |||
| 51 | #define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) | ||
| 52 | |||
| 53 | /* WINCONx */ | ||
| 54 | |||
| 55 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
| 56 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
| 57 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
| 58 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
| 59 | |||
| 60 | #define WINCONx_ENLOCAL (1 << 22) | ||
| 61 | #define WINCONx_BUFSTATUS (1 << 21) | ||
| 62 | #define WINCONx_BUFSEL (1 << 20) | ||
| 63 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
| 64 | #define WINCONx_YCbCr (1 << 13) | ||
| 65 | |||
| 66 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
| 67 | |||
| 68 | #define WINCON2_LOCALSEL_CAMIF (1 << 23) | ||
| 69 | #define WINCON2_BLD_PIX (1 << 6) | ||
| 70 | |||
| 71 | #define WINCON2_ALPHA_SEL (1 << 1) | ||
| 72 | #define WINCON2_BPPMODE_MASK (0xf << 2) | ||
| 73 | #define WINCON2_BPPMODE_SHIFT (2) | ||
| 74 | #define WINCON2_BPPMODE_1BPP (0x0 << 2) | ||
| 75 | #define WINCON2_BPPMODE_2BPP (0x1 << 2) | ||
| 76 | #define WINCON2_BPPMODE_4BPP (0x2 << 2) | ||
| 77 | #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) | ||
| 78 | #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 79 | #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 80 | #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 81 | #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 82 | #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 83 | #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 84 | #define WINCON2_BPPMODE_24BPP_888 (0xb << 2) | ||
| 85 | #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 86 | #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 87 | #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 88 | |||
| 89 | #define WINCON3_BLD_PIX (1 << 6) | ||
| 90 | |||
| 91 | #define WINCON3_ALPHA_SEL (1 << 1) | ||
| 92 | #define WINCON3_BPPMODE_MASK (0xf << 2) | ||
| 93 | #define WINCON3_BPPMODE_SHIFT (2) | ||
| 94 | #define WINCON3_BPPMODE_1BPP (0x0 << 2) | ||
| 95 | #define WINCON3_BPPMODE_2BPP (0x1 << 2) | ||
| 96 | #define WINCON3_BPPMODE_4BPP (0x2 << 2) | ||
| 97 | #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) | ||
| 98 | #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
| 99 | #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
| 100 | #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) | ||
| 101 | #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
| 102 | #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) | ||
| 103 | #define WINCON3_BPPMODE_24BPP_888 (0xb << 2) | ||
| 104 | #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) | ||
| 105 | #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) | ||
| 106 | #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) | ||
| 107 | |||
| 108 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
| 109 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
| 110 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
| 111 | |||
| 112 | #define DITHMODE (0x170) | ||
| 113 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | ||
| 114 | |||
| 115 | |||
| 116 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
| 117 | #define DITHMODE_R_POS_SHIFT (5) | ||
| 118 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
| 119 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
| 120 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
| 121 | |||
| 122 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
| 123 | #define DITHMODE_G_POS_SHIFT (3) | ||
| 124 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
| 125 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
| 126 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
| 127 | |||
| 128 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
| 129 | #define DITHMODE_B_POS_SHIFT (1) | ||
| 130 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
| 131 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
| 132 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
| 133 | |||
| 134 | #define DITHMODE_DITH_EN (1 << 0) | ||
| 135 | |||
| 136 | #define WPALCON (0x1A0) | ||
| 137 | |||
| 138 | /* Palette control */ | ||
| 139 | /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), | ||
| 140 | * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ | ||
| 141 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
| 142 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
| 143 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
| 144 | |||
| 145 | |||
| 146 | /* system specific implementation code for palette sizes, and other | ||
| 147 | * information that changes depending on which architecture is being | ||
| 148 | * compiled. | ||
| 149 | */ | ||
| 150 | |||
| 151 | /* return true if window _win has OSD register D */ | ||
| 152 | #define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) | ||
| 153 | |||
| 154 | static inline unsigned int s3c_fb_win_pal_size(unsigned int win) | ||
| 155 | { | ||
| 156 | if (win < 2) | ||
| 157 | return 256; | ||
| 158 | if (win < 4) | ||
| 159 | return 16; | ||
| 160 | if (win == 4) | ||
| 161 | return 4; | ||
| 162 | |||
| 163 | BUG(); /* shouldn't get here */ | ||
| 164 | } | ||
| 165 | |||
| 166 | static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) | ||
| 167 | { | ||
| 168 | /* all windows can do 1/2 bpp */ | ||
| 169 | |||
| 170 | if ((bpp == 25 || bpp == 19) && win == 0) | ||
| 171 | return 0; /* win 0 does not have 19 or 25bpp modes */ | ||
| 172 | |||
| 173 | if (bpp == 4 && win == 4) | ||
| 174 | return 0; | ||
| 175 | |||
| 176 | if (bpp == 8 && (win >= 3)) | ||
| 177 | return 0; /* win 3/4 cannot do 8bpp in any mode */ | ||
| 178 | |||
| 179 | return 1; | ||
| 180 | } | ||
| 181 | |||
| 182 | static inline int s3c_fb_pal_is16(unsigned int window) | ||
| 183 | { | ||
| 184 | return window > 1; | ||
| 185 | } | ||
| 186 | |||
| 187 | struct s3c_fb_palette { | ||
| 188 | struct fb_bitfield r; | ||
| 189 | struct fb_bitfield g; | ||
| 190 | struct fb_bitfield b; | ||
| 191 | struct fb_bitfield a; | ||
| 192 | }; | ||
| 193 | |||
| 194 | static inline void s3c_fb_init_palette(unsigned int window, | ||
| 195 | struct s3c_fb_palette *palette) | ||
| 196 | { | ||
| 197 | if (window < 2) { | ||
| 198 | /* Windows 0/1 are 8/8/8 or A/8/8/8 */ | ||
| 199 | palette->r.offset = 16; | ||
| 200 | palette->r.length = 8; | ||
| 201 | palette->g.offset = 8; | ||
| 202 | palette->g.length = 8; | ||
| 203 | palette->b.offset = 0; | ||
| 204 | palette->b.length = 8; | ||
| 205 | } else { | ||
| 206 | /* currently we assume RGB 5/6/5 */ | ||
| 207 | palette->r.offset = 11; | ||
| 208 | palette->r.length = 5; | ||
| 209 | palette->g.offset = 5; | ||
| 210 | palette->g.length = 6; | ||
| 211 | palette->b.offset = 0; | ||
| 212 | palette->b.length = 5; | ||
| 213 | } | ||
| 214 | } | ||
| 215 | |||
| 216 | /* Notes on per-window bpp settings | ||
| 217 | * | ||
| 218 | * Value Win0 Win1 Win2 Win3 Win 4 | ||
| 219 | * 0000 1(P) 1(P) 1(P) 1(P) 1(P) | ||
| 220 | * 0001 2(P) 2(P) 2(P) 2(P) 2(P) | ||
| 221 | * 0010 4(P) 4(P) 4(P) 4(P) -none- | ||
| 222 | * 0011 8(P) 8(P) -none- -none- -none- | ||
| 223 | * 0100 -none- 8(A232) 8(A232) -none- -none- | ||
| 224 | * 0101 16(565) 16(565) 16(565) 16(565) 16(565) | ||
| 225 | * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) | ||
| 226 | * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) | ||
| 227 | * 1000 18(666) 18(666) 18(666) 18(666) 18(666) | ||
| 228 | * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) | ||
| 229 | * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) | ||
| 230 | * 1011 24(888) 24(888) 24(888) 24(888) 24(888) | ||
| 231 | * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) | ||
| 232 | * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) | ||
| 233 | * 1110 -none- -none- -none- -none- -none- | ||
| 234 | * 1111 -none- -none- -none- -none- -none- | ||
| 235 | */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-nand.h b/arch/arm/plat-s3c/include/plat/regs-nand.h index b2caa4bca270..238efea7b9e4 100644 --- a/arch/arm/plat-s3c/include/plat/regs-nand.h +++ b/arch/arm/plat-s3c/include/plat/regs-nand.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/regs-nand.h | 1 | /* arch/arm/mach-s3c2410/include/mach/regs-nand.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk> | 3 | * Copyright (c) 2004-2005 Simtec Electronics <linux@simtec.co.uk> |
| 4 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 66af75a5cdd1..85d8904e7f24 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | 7 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) |
| 8 | * | 8 | * |
| 9 | * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk) | 9 | * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk) |
| 10 | * | 10 | * |
| 11 | * Adapted from: | 11 | * Adapted from: |
| 12 | * | 12 | * |
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h index f615308ccdfb..53198673b6bd 100644 --- a/arch/arm/plat-s3c/include/plat/sdhci.h +++ b/arch/arm/plat-s3c/include/plat/sdhci.h | |||
| @@ -57,6 +57,7 @@ struct s3c_sdhci_platdata { | |||
| 57 | */ | 57 | */ |
| 58 | extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); | 58 | extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); |
| 59 | extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); | 59 | extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); |
| 60 | extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd); | ||
| 60 | 61 | ||
| 61 | /* Default platform data, exported so that per-cpu initialisation can | 62 | /* Default platform data, exported so that per-cpu initialisation can |
| 62 | * set the correct one when there are more than one cpu type selected. | 63 | * set the correct one when there are more than one cpu type selected. |
| @@ -64,11 +65,16 @@ extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); | |||
| 64 | 65 | ||
| 65 | extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; | 66 | extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; |
| 66 | extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; | 67 | extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; |
| 68 | extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata; | ||
| 67 | 69 | ||
| 68 | /* Helper function availablity */ | 70 | /* Helper function availablity */ |
| 69 | 71 | ||
| 70 | extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | 72 | extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
| 71 | extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 73 | extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
| 74 | extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | ||
| 75 | extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | ||
| 76 | extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
| 77 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
| 72 | 78 | ||
| 73 | /* S3C6400 SDHCI setup */ | 79 | /* S3C6400 SDHCI setup */ |
| 74 | 80 | ||
| @@ -103,6 +109,17 @@ static inline void s3c6400_default_sdhci1(void) | |||
| 103 | static inline void s3c6400_default_sdhci1(void) { } | 109 | static inline void s3c6400_default_sdhci1(void) { } |
| 104 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | 110 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ |
| 105 | 111 | ||
| 112 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
| 113 | static inline void s3c6400_default_sdhci2(void) | ||
| 114 | { | ||
| 115 | s3c_hsmmc2_def_platdata.clocks = s3c6400_hsmmc_clksrcs; | ||
| 116 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; | ||
| 117 | s3c_hsmmc2_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card; | ||
| 118 | } | ||
| 119 | #else | ||
| 120 | static inline void s3c6400_default_sdhci2(void) { } | ||
| 121 | #endif /* CONFIG_S3C_DEV_HSMMC2 */ | ||
| 122 | |||
| 106 | #else | 123 | #else |
| 107 | static inline void s3c6400_default_sdhci0(void) { } | 124 | static inline void s3c6400_default_sdhci0(void) { } |
| 108 | static inline void s3c6400_default_sdhci1(void) { } | 125 | static inline void s3c6400_default_sdhci1(void) { } |
| @@ -140,9 +157,70 @@ static inline void s3c6410_default_sdhci1(void) | |||
| 140 | static inline void s3c6410_default_sdhci1(void) { } | 157 | static inline void s3c6410_default_sdhci1(void) { } |
| 141 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | 158 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ |
| 142 | 159 | ||
| 160 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
| 161 | static inline void s3c6410_default_sdhci2(void) | ||
| 162 | { | ||
| 163 | s3c_hsmmc2_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | ||
| 164 | s3c_hsmmc2_def_platdata.cfg_gpio = s3c64xx_setup_sdhci2_cfg_gpio; | ||
| 165 | s3c_hsmmc2_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | ||
| 166 | } | ||
| 167 | #else | ||
| 168 | static inline void s3c6410_default_sdhci2(void) { } | ||
| 169 | #endif /* CONFIG_S3C_DEV_HSMMC2 */ | ||
| 170 | |||
| 143 | #else | 171 | #else |
| 144 | static inline void s3c6410_default_sdhci0(void) { } | 172 | static inline void s3c6410_default_sdhci0(void) { } |
| 145 | static inline void s3c6410_default_sdhci1(void) { } | 173 | static inline void s3c6410_default_sdhci1(void) { } |
| 146 | #endif /* CONFIG_S3C6410_SETUP_SDHCI */ | 174 | #endif /* CONFIG_S3C6410_SETUP_SDHCI */ |
| 147 | 175 | ||
| 176 | /* S5PC100 SDHCI setup */ | ||
| 177 | |||
| 178 | #ifdef CONFIG_S5PC100_SETUP_SDHCI | ||
| 179 | extern char *s5pc100_hsmmc_clksrcs[4]; | ||
| 180 | |||
| 181 | extern void s5pc100_setup_sdhci0_cfg_card(struct platform_device *dev, | ||
| 182 | void __iomem *r, | ||
| 183 | struct mmc_ios *ios, | ||
| 184 | struct mmc_card *card); | ||
| 185 | |||
| 186 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
| 187 | static inline void s5pc100_default_sdhci0(void) | ||
| 188 | { | ||
| 189 | s3c_hsmmc0_def_platdata.clocks = s5pc100_hsmmc_clksrcs; | ||
| 190 | s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; | ||
| 191 | s3c_hsmmc0_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; | ||
| 192 | } | ||
| 193 | #else | ||
| 194 | static inline void s5pc100_default_sdhci0(void) { } | ||
| 195 | #endif /* CONFIG_S3C_DEV_HSMMC */ | ||
| 196 | |||
| 197 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
| 198 | static inline void s5pc100_default_sdhci1(void) | ||
| 199 | { | ||
| 200 | s3c_hsmmc1_def_platdata.clocks = s5pc100_hsmmc_clksrcs; | ||
| 201 | s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; | ||
| 202 | s3c_hsmmc1_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; | ||
| 203 | } | ||
| 204 | #else | ||
| 205 | static inline void s5pc100_default_sdhci1(void) { } | ||
| 206 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | ||
| 207 | |||
| 208 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
| 209 | static inline void s5pc100_default_sdhci2(void) | ||
| 210 | { | ||
| 211 | s3c_hsmmc2_def_platdata.clocks = s5pc100_hsmmc_clksrcs; | ||
| 212 | s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; | ||
| 213 | s3c_hsmmc2_def_platdata.cfg_card = s5pc100_setup_sdhci0_cfg_card; | ||
| 214 | } | ||
| 215 | #else | ||
| 216 | static inline void s5pc100_default_sdhci2(void) { } | ||
| 217 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | ||
| 218 | |||
| 219 | |||
| 220 | #else | ||
| 221 | static inline void s5pc100_default_sdhci0(void) { } | ||
| 222 | static inline void s5pc100_default_sdhci1(void) { } | ||
| 223 | static inline void s5pc100_default_sdhci2(void) { } | ||
| 224 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ | ||
| 225 | |||
| 148 | #endif /* __PLAT_S3C_SDHCI_H */ | 226 | #endif /* __PLAT_S3C_SDHCI_H */ |
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c index 39f2555564da..8eb1f439861c 100644 --- a/arch/arm/plat-s3c/pm-check.c +++ b/arch/arm/plat-s3c/pm-check.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm-check.c | 1 | /* linux/arch/arm/plat-s3c/pm-check.c |
| 2 | * originally in linux/arch/arm/plat-s3c24xx/pm.c | 2 | * originally in linux/arch/arm/plat-s3c24xx/pm.c |
| 3 | * | 3 | * |
| 4 | * Copyright (c) 2004,2006,2008 Simtec Electronics | 4 | * Copyright (c) 2004-2008 Simtec Electronics |
| 5 | * http://armlinux.simtec.co.uk | 5 | * http://armlinux.simtec.co.uk |
| 6 | * Ben Dooks <ben@simtec.co.uk> | 6 | * Ben Dooks <ben@simtec.co.uk> |
| 7 | * | 7 | * |
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index 8d97db2c7a0d..767470601e5c 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm.c | 1 | /* linux/arch/arm/plat-s3c/pm.c |
| 2 | * | 2 | * |
| 3 | * Copyright 2008 Openmoko, Inc. | 3 | * Copyright 2008 Openmoko, Inc. |
| 4 | * Copyright 2004,2006,2008 Simtec Electronics | 4 | * Copyright 2004-2008 Simtec Electronics |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 9c7aca489643..20fbf936bb93 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
| @@ -178,4 +178,11 @@ config MACH_SMDK | |||
| 178 | help | 178 | help |
| 179 | Common machine code for SMDK2410 and SMDK2440 | 179 | Common machine code for SMDK2410 and SMDK2440 |
| 180 | 180 | ||
| 181 | config S3C24XX_SIMTEC_AUDIO | ||
| 182 | bool | ||
| 183 | depends on (ARCH_BAST || MACH_VR1000 || MACH_OSIRIS || MACH_ANUBIS) | ||
| 184 | default y | ||
| 185 | help | ||
| 186 | Add audio devices for common Simtec S3C24XX boards | ||
| 187 | |||
| 181 | endif | 188 | endif |
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 7780d2dd833a..5dee8c12e8b4 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
| @@ -55,3 +55,4 @@ obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10) += spi-bus1-gpd8_9_10.o | |||
| 55 | # machine common support | 55 | # machine common support |
| 56 | 56 | ||
| 57 | obj-$(CONFIG_MACH_SMDK) += common-smdk.o | 57 | obj-$(CONFIG_MACH_SMDK) += common-smdk.o |
| 58 | obj-$(CONFIG_S3C24XX_SIMTEC_AUDIO) += simtec-audio.o | ||
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c index 0afb217a775e..ac061a1bcb37 100644 --- a/arch/arm/plat-s3c24xx/clock-dclk.c +++ b/arch/arm/plat-s3c24xx/clock-dclk.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/clock-dclk.c | 1 | /* linux/arch/arm/plat-s3c24xx/clock-dclk.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2008 Simtec Electronics | 3 | * Copyright (c) 2004-2008 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index aa119863c5ce..9e0e20ad2e46 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c | |||
| @@ -198,7 +198,7 @@ void __init smdk_machine_init(void) | |||
| 198 | if (machine_is_smdk2443()) | 198 | if (machine_is_smdk2443()) |
| 199 | smdk_nand_info.twrph0 = 50; | 199 | smdk_nand_info.twrph0 = 50; |
| 200 | 200 | ||
| 201 | s3c_device_nand.dev.platform_data = &smdk_nand_info; | 201 | s3c_nand_set_platdata(&smdk_nand_info); |
| 202 | 202 | ||
| 203 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); | 203 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); |
| 204 | 204 | ||
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c index 4f1b789a1173..2d42efb9f4e9 100644 --- a/arch/arm/plat-s3c24xx/cpu-freq.c +++ b/arch/arm/plat-s3c24xx/cpu-freq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/cpu-freq.c | 1 | /* linux/arch/arm/plat-s3c24xx/cpu-freq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2007,2008 Simtec Electronics | 3 | * Copyright (c) 2006-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index f046f8c51084..f65192d5b1d7 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/dma.c | 1 | /* linux/arch/arm/plat-s3c24xx/dma.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003-2005,2006 Simtec Electronics | 3 | * Copyright 2003-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * S3C2410 DMA core | 6 | * S3C2410 DMA core |
| @@ -1310,7 +1310,7 @@ int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq, | |||
| 1310 | int channel; | 1310 | int channel; |
| 1311 | int ret; | 1311 | int ret; |
| 1312 | 1312 | ||
| 1313 | printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); | 1313 | printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n"); |
| 1314 | 1314 | ||
| 1315 | dma_channels = channels; | 1315 | dma_channels = channels; |
| 1316 | 1316 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h index c776120b99e6..33d421d78bad 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h +++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | 1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2007,2009 Simtec Electronics | 3 | * Copyright (c) 2006-2009 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/include/plat/mci.h b/arch/arm/plat-s3c24xx/include/plat/mci.h index c2cef6139683..36aaa10fad06 100644 --- a/arch/arm/plat-s3c24xx/include/plat/mci.h +++ b/arch/arm/plat-s3c24xx/include/plat/mci.h | |||
| @@ -1,6 +1,31 @@ | |||
| 1 | #ifndef _ARCH_MCI_H | 1 | #ifndef _ARCH_MCI_H |
| 2 | #define _ARCH_MCI_H | 2 | #define _ARCH_MCI_H |
| 3 | 3 | ||
| 4 | /** | ||
| 5 | * struct s3c24xx_mci_pdata - sd/mmc controller platform data | ||
| 6 | * @no_wprotect: Set this to indicate there is no write-protect switch. | ||
| 7 | * @no_detect: Set this if there is no detect switch. | ||
| 8 | * @wprotect_invert: Invert the default sense of the write protect switch. | ||
| 9 | * @detect_invert: Invert the default sense of the write protect switch. | ||
| 10 | * @use_dma: Set to allow the use of DMA. | ||
| 11 | * @gpio_detect: GPIO number for the card detect line. | ||
| 12 | * @gpio_wprotect: GPIO number for the write protect line. | ||
| 13 | * @ocr_avail: The mask of the available power states, non-zero to use. | ||
| 14 | * @set_power: Callback to control the power mode. | ||
| 15 | * | ||
| 16 | * The @gpio_detect is used for card detection when @no_wprotect is unset, | ||
| 17 | * and the default sense is that 0 returned from gpio_get_value() means | ||
| 18 | * that a card is inserted. If @detect_invert is set, then the value from | ||
| 19 | * gpio_get_value() is inverted, which makes 1 mean card inserted. | ||
| 20 | * | ||
| 21 | * The driver will use @gpio_wprotect to signal whether the card is write | ||
| 22 | * protected if @no_wprotect is not set. A 0 returned from gpio_get_value() | ||
| 23 | * means the card is read/write, and 1 means read-only. The @wprotect_invert | ||
| 24 | * will invert the value returned from gpio_get_value(). | ||
| 25 | * | ||
| 26 | * Card power is set by @ocr_availa, using MCC_VDD_ constants if it is set | ||
| 27 | * to a non-zero value, otherwise the default of 3.2-3.4V is used. | ||
| 28 | */ | ||
| 4 | struct s3c24xx_mci_pdata { | 29 | struct s3c24xx_mci_pdata { |
| 5 | unsigned int no_wprotect : 1; | 30 | unsigned int no_wprotect : 1; |
| 6 | unsigned int no_detect : 1; | 31 | unsigned int no_detect : 1; |
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h index 3bc0a216df97..1b0f4c36d384 100644 --- a/arch/arm/plat-s3c24xx/include/plat/regs-dma.h +++ b/arch/arm/plat-s3c24xx/include/plat/regs-dma.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/dma.h | 1 | /* arch/arm/mach-s3c2410/include/mach/dma.h |
| 2 | * | 2 | * |
| 3 | * Copyright (C) 2003,2004,2006 Simtec Electronics | 3 | * Copyright (C) 2003-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * Samsung S3C24XX DMA support | 6 | * Samsung S3C24XX DMA support |
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c index b7acf1a8ecd2..ea8dea3339a4 100644 --- a/arch/arm/plat-s3c24xx/irq-pm.c +++ b/arch/arm/plat-s3c24xx/irq-pm.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c | 1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index d02f5f02045e..ef0f521437d7 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq.c | 1 | /* linux/arch/arm/plat-s3c24xx/irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index da0d3217d3e3..663b280d65da 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/pm-simtec.c | 1 | /* linux/arch/arm/plat-s3c24xx/pm-simtec.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004 Simtec Electronics | 3 | * Copyright 2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| @@ -35,7 +35,7 @@ | |||
| 35 | 35 | ||
| 36 | #include <plat/pm.h> | 36 | #include <plat/pm.h> |
| 37 | 37 | ||
| 38 | #define COPYRIGHT ", (c) 2005 Simtec Electronics" | 38 | #define COPYRIGHT ", Copyright 2005 Simtec Electronics" |
| 39 | 39 | ||
| 40 | /* pm_simtec_init | 40 | /* pm_simtec_init |
| 41 | * | 41 | * |
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 56e5253ca02c..3620dd299095 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/pm.c | 1 | /* linux/arch/arm/plat-s3c24xx/pm.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004,2006 Simtec Electronics | 3 | * Copyright (c) 2004-2006 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * S3C24XX Power Manager (Suspend-To-RAM) support | 6 | * S3C24XX Power Manager (Suspend-To-RAM) support |
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c index d0a3a145cd4d..963fb0b4379e 100644 --- a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c +++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c | 1 | /* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2008,2009 Simtec Electronics | 3 | * Copyright (c) 2006-2009 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c index fd45e47facbc..24993dce10b5 100644 --- a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c +++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c | 1 | /* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2008 Simtec Electronics | 3 | * Copyright (c) 2006-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c index ae2e6c604f27..976002fb1b8f 100644 --- a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c +++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c | 1 | /* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2008,2009 Simtec Electronics | 3 | * Copyright (c) 2006-2009 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * Vincent Sanders <vince@simtec.co.uk> | 6 | * Vincent Sanders <vince@simtec.co.uk> |
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c index ff9443b233aa..49f65032f2c0 100644 --- a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c +++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c | 1 | /* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2006,2007 Simtec Electronics | 3 | * Copyright (c) 2006-2007 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * Vincent Sanders <vince@arm.linux.org.uk> | 6 | * Vincent Sanders <vince@arm.linux.org.uk> |
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index dde41f171aff..79371091aa38 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c | 1 | /* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2004-2005,2008 Simtec Electronics | 3 | * Copyright (c) 2004-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ | 4 | * http://armlinux.simtec.co.uk/ |
| 5 | * Ben Dooks <ben@simtec.co.uk> | 5 | * Ben Dooks <ben@simtec.co.uk> |
| 6 | * | 6 | * |
diff --git a/arch/arm/plat-s3c24xx/s3c244x-irq.c b/arch/arm/plat-s3c24xx/s3c244x-irq.c index 0902afd227ca..a75c0c2431ea 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-irq.c +++ b/arch/arm/plat-s3c24xx/s3c244x-irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c | 1 | /* linux/arch/arm/plat-s3c24xx/s3c244x-irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
diff --git a/arch/arm/plat-s3c24xx/simtec-audio.c b/arch/arm/plat-s3c24xx/simtec-audio.c new file mode 100644 index 000000000000..6bc832e0d8ea --- /dev/null +++ b/arch/arm/plat-s3c24xx/simtec-audio.c | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/simtec-audio.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * Audio setup for various Simtec S3C24XX implementations | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/device.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | |||
| 20 | #include <mach/bast-map.h> | ||
| 21 | #include <mach/bast-irq.h> | ||
| 22 | #include <mach/bast-cpld.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/regs-gpio.h> | ||
| 26 | |||
| 27 | #include <plat/audio-simtec.h> | ||
| 28 | #include <plat/devs.h> | ||
| 29 | |||
| 30 | /* platform ops for audio */ | ||
| 31 | |||
| 32 | static void simtec_audio_startup_lrroute(void) | ||
| 33 | { | ||
| 34 | unsigned int tmp; | ||
| 35 | unsigned long flags; | ||
| 36 | |||
| 37 | local_irq_save(flags); | ||
| 38 | |||
| 39 | tmp = __raw_readb(BAST_VA_CTRL1); | ||
| 40 | tmp &= ~BAST_CPLD_CTRL1_LRMASK; | ||
| 41 | tmp |= BAST_CPLD_CTRL1_LRCDAC; | ||
| 42 | __raw_writeb(tmp, BAST_VA_CTRL1); | ||
| 43 | |||
| 44 | local_irq_restore(flags); | ||
| 45 | } | ||
| 46 | |||
| 47 | static struct s3c24xx_audio_simtec_pdata simtec_audio_platdata; | ||
| 48 | static char our_name[32]; | ||
| 49 | |||
| 50 | static struct platform_device simtec_audio_dev = { | ||
| 51 | .name = our_name, | ||
| 52 | .id = -1, | ||
| 53 | .dev = { | ||
| 54 | .parent = &s3c_device_iis.dev, | ||
| 55 | .platform_data = &simtec_audio_platdata, | ||
| 56 | }, | ||
| 57 | }; | ||
| 58 | |||
| 59 | int __init simtec_audio_add(const char *name, bool has_lr_routing, | ||
| 60 | struct s3c24xx_audio_simtec_pdata *spd) | ||
| 61 | { | ||
| 62 | if (!name) | ||
| 63 | name = "tlv320aic23"; | ||
| 64 | |||
| 65 | snprintf(our_name, sizeof(our_name)-1, "s3c24xx-simtec-%s", name); | ||
| 66 | |||
| 67 | /* copy platform data so the source can be __initdata */ | ||
| 68 | if (spd) | ||
| 69 | simtec_audio_platdata = *spd; | ||
| 70 | |||
| 71 | if (has_lr_routing) | ||
| 72 | simtec_audio_platdata.startup = simtec_audio_startup_lrroute; | ||
| 73 | |||
| 74 | platform_device_register(&s3c_device_iis); | ||
| 75 | platform_device_register(&simtec_audio_dev); | ||
| 76 | return 0; | ||
| 77 | } | ||
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c index b1fdd83940a6..49796d2db86d 100644 --- a/arch/arm/plat-s3c64xx/cpu.c +++ b/arch/arm/plat-s3c64xx/cpu.c | |||
| @@ -107,6 +107,11 @@ static struct map_desc s3c_iodesc[] __initdata = { | |||
| 107 | .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), | 107 | .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG), |
| 108 | .length = SZ_4K, | 108 | .length = SZ_4K, |
| 109 | .type = MT_DEVICE, | 109 | .type = MT_DEVICE, |
| 110 | }, { | ||
| 111 | .virtual = (unsigned long)S3C_VA_USB_HSPHY, | ||
| 112 | .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY), | ||
| 113 | .length = SZ_1K, | ||
| 114 | .type = MT_DEVICE, | ||
| 110 | }, | 115 | }, |
| 111 | }; | 116 | }; |
| 112 | 117 | ||
diff --git a/arch/arm/plat-s3c64xx/cpufreq.c b/arch/arm/plat-s3c64xx/cpufreq.c index e6e0843215df..74c0e8347de5 100644 --- a/arch/arm/plat-s3c64xx/cpufreq.c +++ b/arch/arm/plat-s3c64xx/cpufreq.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | static struct clk *armclk; | 20 | static struct clk *armclk; |
| 21 | static struct regulator *vddarm; | 21 | static struct regulator *vddarm; |
| 22 | static unsigned long regulator_latency; | ||
| 22 | 23 | ||
| 23 | #ifdef CONFIG_CPU_S3C6410 | 24 | #ifdef CONFIG_CPU_S3C6410 |
| 24 | struct s3c64xx_dvfs { | 25 | struct s3c64xx_dvfs { |
| @@ -27,11 +28,10 @@ struct s3c64xx_dvfs { | |||
| 27 | }; | 28 | }; |
| 28 | 29 | ||
| 29 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { | 30 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { |
| 30 | [0] = { 1000000, 1000000 }, | 31 | [0] = { 1000000, 1150000 }, |
| 31 | [1] = { 1000000, 1050000 }, | 32 | [1] = { 1050000, 1150000 }, |
| 32 | [2] = { 1050000, 1100000 }, | 33 | [2] = { 1100000, 1150000 }, |
| 33 | [3] = { 1050000, 1150000 }, | 34 | [3] = { 1200000, 1350000 }, |
| 34 | [4] = { 1250000, 1350000 }, | ||
| 35 | }; | 35 | }; |
| 36 | 36 | ||
| 37 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | 37 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { |
| @@ -41,9 +41,9 @@ static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | |||
| 41 | { 1, 266000 }, | 41 | { 1, 266000 }, |
| 42 | { 2, 333000 }, | 42 | { 2, 333000 }, |
| 43 | { 2, 400000 }, | 43 | { 2, 400000 }, |
| 44 | { 3, 532000 }, | 44 | { 2, 532000 }, |
| 45 | { 3, 533000 }, | 45 | { 2, 533000 }, |
| 46 | { 4, 667000 }, | 46 | { 3, 667000 }, |
| 47 | { 0, CPUFREQ_TABLE_END }, | 47 | { 0, CPUFREQ_TABLE_END }, |
| 48 | }; | 48 | }; |
| 49 | #endif | 49 | #endif |
| @@ -141,7 +141,7 @@ err: | |||
| 141 | } | 141 | } |
| 142 | 142 | ||
| 143 | #ifdef CONFIG_REGULATOR | 143 | #ifdef CONFIG_REGULATOR |
| 144 | static void __init s3c64xx_cpufreq_constrain_voltages(void) | 144 | static void __init s3c64xx_cpufreq_config_regulator(void) |
| 145 | { | 145 | { |
| 146 | int count, v, i, found; | 146 | int count, v, i, found; |
| 147 | struct cpufreq_frequency_table *freq; | 147 | struct cpufreq_frequency_table *freq; |
| @@ -150,11 +150,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void) | |||
| 150 | count = regulator_count_voltages(vddarm); | 150 | count = regulator_count_voltages(vddarm); |
| 151 | if (count < 0) { | 151 | if (count < 0) { |
| 152 | pr_err("cpufreq: Unable to check supported voltages\n"); | 152 | pr_err("cpufreq: Unable to check supported voltages\n"); |
| 153 | return; | ||
| 154 | } | 153 | } |
| 155 | 154 | ||
| 156 | freq = s3c64xx_freq_table; | 155 | freq = s3c64xx_freq_table; |
| 157 | while (freq->frequency != CPUFREQ_TABLE_END) { | 156 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { |
| 158 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) | 157 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) |
| 159 | continue; | 158 | continue; |
| 160 | 159 | ||
| @@ -175,6 +174,10 @@ static void __init s3c64xx_cpufreq_constrain_voltages(void) | |||
| 175 | 174 | ||
| 176 | freq++; | 175 | freq++; |
| 177 | } | 176 | } |
| 177 | |||
| 178 | /* Guess based on having to do an I2C/SPI write; in future we | ||
| 179 | * will be able to query the regulator performance here. */ | ||
| 180 | regulator_latency = 1 * 1000 * 1000; | ||
| 178 | } | 181 | } |
| 179 | #endif | 182 | #endif |
| 180 | 183 | ||
| @@ -206,7 +209,7 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) | |||
| 206 | pr_err("cpufreq: Only frequency scaling available\n"); | 209 | pr_err("cpufreq: Only frequency scaling available\n"); |
| 207 | vddarm = NULL; | 210 | vddarm = NULL; |
| 208 | } else { | 211 | } else { |
| 209 | s3c64xx_cpufreq_constrain_voltages(); | 212 | s3c64xx_cpufreq_config_regulator(); |
| 210 | } | 213 | } |
| 211 | #endif | 214 | #endif |
| 212 | 215 | ||
| @@ -217,8 +220,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) | |||
| 217 | /* Check for frequencies we can generate */ | 220 | /* Check for frequencies we can generate */ |
| 218 | r = clk_round_rate(armclk, freq->frequency * 1000); | 221 | r = clk_round_rate(armclk, freq->frequency * 1000); |
| 219 | r /= 1000; | 222 | r /= 1000; |
| 220 | if (r != freq->frequency) | 223 | if (r != freq->frequency) { |
| 224 | pr_debug("cpufreq: %dkHz unsupported by clock\n", | ||
| 225 | freq->frequency); | ||
| 221 | freq->frequency = CPUFREQ_ENTRY_INVALID; | 226 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
| 227 | } | ||
| 222 | 228 | ||
| 223 | /* If we have no regulator then assume startup | 229 | /* If we have no regulator then assume startup |
| 224 | * frequency is the maximum we can support. */ | 230 | * frequency is the maximum we can support. */ |
| @@ -230,9 +236,11 @@ static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) | |||
| 230 | 236 | ||
| 231 | policy->cur = clk_get_rate(armclk) / 1000; | 237 | policy->cur = clk_get_rate(armclk) / 1000; |
| 232 | 238 | ||
| 233 | /* Pick a conservative guess in ns: we'll need ~1 I2C/SPI | 239 | /* Datasheet says PLL stabalisation time (if we were to use |
| 234 | * write plus clock reprogramming. */ | 240 | * the PLLs, which we don't currently) is ~300us worst case, |
| 235 | policy->cpuinfo.transition_latency = 2 * 1000 * 1000; | 241 | * but add some fudge. |
| 242 | */ | ||
| 243 | policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency; | ||
| 236 | 244 | ||
| 237 | ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); | 245 | ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table); |
| 238 | if (ret != 0) { | 246 | if (ret != 0) { |
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index 92859290ea33..778560457277 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c | |||
| @@ -213,6 +213,11 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { | |||
| 213 | .get_pull = s3c_gpio_getpull_updown, | 213 | .get_pull = s3c_gpio_getpull_updown, |
| 214 | }; | 214 | }; |
| 215 | 215 | ||
| 216 | int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) | ||
| 217 | { | ||
| 218 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; | ||
| 219 | } | ||
| 220 | |||
| 216 | static struct s3c_gpio_chip gpio_4bit[] = { | 221 | static struct s3c_gpio_chip gpio_4bit[] = { |
| 217 | { | 222 | { |
| 218 | .base = S3C64XX_GPA_BASE, | 223 | .base = S3C64XX_GPA_BASE, |
| @@ -269,10 +274,16 @@ static struct s3c_gpio_chip gpio_4bit[] = { | |||
| 269 | .base = S3C64XX_GPM(0), | 274 | .base = S3C64XX_GPM(0), |
| 270 | .ngpio = S3C64XX_GPIO_M_NR, | 275 | .ngpio = S3C64XX_GPIO_M_NR, |
| 271 | .label = "GPM", | 276 | .label = "GPM", |
| 277 | .to_irq = s3c64xx_gpio2int_gpm, | ||
| 272 | }, | 278 | }, |
| 273 | }, | 279 | }, |
| 274 | }; | 280 | }; |
| 275 | 281 | ||
| 282 | int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) | ||
| 283 | { | ||
| 284 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; | ||
| 285 | } | ||
| 286 | |||
| 276 | static struct s3c_gpio_chip gpio_4bit2[] = { | 287 | static struct s3c_gpio_chip gpio_4bit2[] = { |
| 277 | { | 288 | { |
| 278 | .base = S3C64XX_GPH_BASE + 0x4, | 289 | .base = S3C64XX_GPH_BASE + 0x4, |
| @@ -297,6 +308,7 @@ static struct s3c_gpio_chip gpio_4bit2[] = { | |||
| 297 | .base = S3C64XX_GPL(0), | 308 | .base = S3C64XX_GPL(0), |
| 298 | .ngpio = S3C64XX_GPIO_L_NR, | 309 | .ngpio = S3C64XX_GPIO_L_NR, |
| 299 | .label = "GPL", | 310 | .label = "GPL", |
| 311 | .to_irq = s3c64xx_gpio2int_gpl, | ||
| 300 | }, | 312 | }, |
| 301 | }, | 313 | }, |
| 302 | }; | 314 | }; |
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h index c47daf7e2723..e22b49f4f982 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h | |||
| @@ -36,18 +36,18 @@ | |||
| 36 | 36 | ||
| 37 | #define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) | 37 | #define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) |
| 38 | #define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) | 38 | #define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) |
| 39 | #define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) | 39 | #define S3C64XX_GPC4_I2S_V40_DO0 (0x05 << 16) |
| 40 | #define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) | 40 | #define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) |
| 41 | 41 | ||
| 42 | #define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) | 42 | #define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) |
| 43 | #define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) | 43 | #define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) |
| 44 | #define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) | 44 | #define S3C64XX_GPC5_I2S_V40_DO1 (0x05 << 20) |
| 45 | #define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) | 45 | #define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) |
| 46 | 46 | ||
| 47 | #define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) | 47 | #define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) |
| 48 | #define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) | 48 | #define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) |
| 49 | 49 | ||
| 50 | #define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) | 50 | #define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) |
| 51 | #define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) | 51 | #define S3C64XX_GPC7_I2S_V40_DO2 (0x05 << 28) |
| 52 | #define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) | 52 | #define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) |
| 53 | 53 | ||
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c index f81b7b818ba0..ebdf183a0911 100644 --- a/arch/arm/plat-s3c64xx/irq-eint.c +++ b/arch/arm/plat-s3c64xx/irq-eint.c | |||
| @@ -65,7 +65,7 @@ static void s3c_irq_eint_maskack(unsigned int irq) | |||
| 65 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | 65 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) |
| 66 | { | 66 | { |
| 67 | int offs = eint_offset(irq); | 67 | int offs = eint_offset(irq); |
| 68 | int pin; | 68 | int pin, pin_val; |
| 69 | int shift; | 69 | int shift; |
| 70 | u32 ctrl, mask; | 70 | u32 ctrl, mask; |
| 71 | u32 newvalue = 0; | 71 | u32 newvalue = 0; |
| @@ -109,7 +109,10 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | |||
| 109 | return -1; | 109 | return -1; |
| 110 | } | 110 | } |
| 111 | 111 | ||
| 112 | shift = (offs / 2) * 4; | 112 | if (offs <= 15) |
| 113 | shift = (offs / 2) * 4; | ||
| 114 | else | ||
| 115 | shift = ((offs - 16) / 2) * 4; | ||
| 113 | mask = 0x7 << shift; | 116 | mask = 0x7 << shift; |
| 114 | 117 | ||
| 115 | ctrl = __raw_readl(reg); | 118 | ctrl = __raw_readl(reg); |
| @@ -119,12 +122,18 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | |||
| 119 | 122 | ||
| 120 | /* set the GPIO pin appropriately */ | 123 | /* set the GPIO pin appropriately */ |
| 121 | 124 | ||
| 122 | if (offs < 23) | 125 | if (offs < 16) { |
| 123 | pin = S3C64XX_GPN(offs); | 126 | pin = S3C64XX_GPN(offs); |
| 124 | else | 127 | pin_val = S3C_GPIO_SFN(2); |
| 128 | } else if (offs < 23) { | ||
| 129 | pin = S3C64XX_GPL(offs + 8 - 16); | ||
| 130 | pin_val = S3C_GPIO_SFN(3); | ||
| 131 | } else { | ||
| 125 | pin = S3C64XX_GPM(offs - 23); | 132 | pin = S3C64XX_GPM(offs - 23); |
| 133 | pin_val = S3C_GPIO_SFN(3); | ||
| 134 | } | ||
| 126 | 135 | ||
| 127 | s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2)); | 136 | s3c_gpio_cfgpin(pin, pin_val); |
| 128 | 137 | ||
| 129 | return 0; | 138 | return 0; |
| 130 | } | 139 | } |
diff --git a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c index 5417123b0ac1..a58c0cc7ba5e 100644 --- a/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c +++ b/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c | |||
| @@ -53,3 +53,23 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | |||
| 53 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); | 53 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); |
| 54 | s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); | 54 | s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); |
| 55 | } | 55 | } |
| 56 | |||
| 57 | void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
| 58 | { | ||
| 59 | unsigned int gpio; | ||
| 60 | unsigned int end; | ||
| 61 | |||
| 62 | end = S3C64XX_GPH(6 + width); | ||
| 63 | |||
| 64 | /* Set all the necessary GPH pins to special-function 1 */ | ||
| 65 | for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { | ||
| 66 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); | ||
| 67 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 68 | } | ||
| 69 | |||
| 70 | /* Set all the necessary GPC pins to special-function 1 */ | ||
| 71 | for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) { | ||
| 72 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); | ||
| 73 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 74 | } | ||
| 75 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index a8a711c3c064..1608e62b0c9d 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig | |||
| @@ -15,6 +15,9 @@ config PLAT_S5PC1XX | |||
| 15 | select ARCH_REQUIRE_GPIOLIB | 15 | select ARCH_REQUIRE_GPIOLIB |
| 16 | select S3C_GPIO_TRACK | 16 | select S3C_GPIO_TRACK |
| 17 | select S3C_GPIO_PULL_UPDOWN | 17 | select S3C_GPIO_PULL_UPDOWN |
| 18 | select S3C_GPIO_CFG_S3C24XX | ||
| 19 | select S3C_GPIO_CFG_S3C64XX | ||
| 20 | select S5P_GPIO_CFG_S5PC1XX | ||
| 18 | help | 21 | help |
| 19 | Base platform code for any Samsung S5PC1XX device | 22 | Base platform code for any Samsung S5PC1XX device |
| 20 | 23 | ||
| @@ -34,7 +37,12 @@ config CPU_S5PC100_CLOCK | |||
| 34 | 37 | ||
| 35 | # platform specific device setup | 38 | # platform specific device setup |
| 36 | 39 | ||
| 37 | config S5PC100_SETUP_I2C0 | 40 | config S5PC1XX_SETUP_FB_24BPP |
| 41 | bool | ||
| 42 | help | ||
| 43 | Common setup code for S5PC1XX with an 24bpp RGB display helper. | ||
| 44 | |||
| 45 | config S5PC1XX_SETUP_I2C0 | ||
| 38 | bool | 46 | bool |
| 39 | default y | 47 | default y |
| 40 | help | 48 | help |
| @@ -43,8 +51,14 @@ config S5PC100_SETUP_I2C0 | |||
| 43 | Note, currently since i2c0 is always compiled, this setup helper | 51 | Note, currently since i2c0 is always compiled, this setup helper |
| 44 | is always compiled with it. | 52 | is always compiled with it. |
| 45 | 53 | ||
| 46 | config S5PC100_SETUP_I2C1 | 54 | config S5PC1XX_SETUP_I2C1 |
| 47 | bool | 55 | bool |
| 48 | help | 56 | help |
| 49 | Common setup code for i2c bus 1. | 57 | Common setup code for i2c bus 1. |
| 58 | |||
| 59 | config S5PC1XX_SETUP_SDHCI_GPIO | ||
| 60 | bool | ||
| 61 | help | ||
| 62 | Common setup code for SDHCI gpio. | ||
| 63 | |||
| 50 | endif | 64 | endif |
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index f1ecb2c37ee2..278f26806089 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile | |||
| @@ -13,7 +13,9 @@ obj- := | |||
| 13 | 13 | ||
| 14 | obj-y += dev-uart.o | 14 | obj-y += dev-uart.o |
| 15 | obj-y += cpu.o | 15 | obj-y += cpu.o |
| 16 | obj-y += irq.o | 16 | obj-y += irq.o irq-gpio.o irq-eint.o |
| 17 | obj-y += clock.o | ||
| 18 | obj-y += gpiolib.o | ||
| 17 | 19 | ||
| 18 | # CPU support | 20 | # CPU support |
| 19 | 21 | ||
| @@ -22,5 +24,8 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o | |||
| 22 | 24 | ||
| 23 | # Device setup | 25 | # Device setup |
| 24 | 26 | ||
| 25 | obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o | 27 | obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o |
| 26 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o | 28 | obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o |
| 29 | obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o | ||
| 30 | obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o | ||
| 31 | obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c new file mode 100644 index 000000000000..26c21d849790 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/clock.c | |||
| @@ -0,0 +1,728 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/clock.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * | ||
| 5 | * S5PC1XX Base clock support | ||
| 6 | * | ||
| 7 | * Based on plat-s3c64xx/clock.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/ioport.h> | ||
| 18 | #include <linux/clk.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <mach/map.h> | ||
| 23 | |||
| 24 | #include <plat/regs-clock.h> | ||
| 25 | #include <plat/devs.h> | ||
| 26 | #include <plat/clock.h> | ||
| 27 | |||
| 28 | struct clk clk_27m = { | ||
| 29 | .name = "clk_27m", | ||
| 30 | .id = -1, | ||
| 31 | .rate = 27000000, | ||
| 32 | }; | ||
| 33 | |||
| 34 | static int clk_48m_ctrl(struct clk *clk, int enable) | ||
| 35 | { | ||
| 36 | unsigned long flags; | ||
| 37 | u32 val; | ||
| 38 | |||
| 39 | /* can't rely on clock lock, this register has other usages */ | ||
| 40 | local_irq_save(flags); | ||
| 41 | |||
| 42 | val = __raw_readl(S5PC100_CLKSRC1); | ||
| 43 | if (enable) | ||
| 44 | val |= S5PC100_CLKSRC1_CLK48M_MASK; | ||
| 45 | else | ||
| 46 | val &= ~S5PC100_CLKSRC1_CLK48M_MASK; | ||
| 47 | |||
| 48 | __raw_writel(val, S5PC100_CLKSRC1); | ||
| 49 | local_irq_restore(flags); | ||
| 50 | |||
| 51 | return 0; | ||
| 52 | } | ||
| 53 | |||
| 54 | struct clk clk_48m = { | ||
| 55 | .name = "clk_48m", | ||
| 56 | .id = -1, | ||
| 57 | .rate = 48000000, | ||
| 58 | .enable = clk_48m_ctrl, | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct clk clk_54m = { | ||
| 62 | .name = "clk_54m", | ||
| 63 | .id = -1, | ||
| 64 | .rate = 54000000, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
| 68 | { | ||
| 69 | clk->rate = rate; | ||
| 70 | return 0; | ||
| 71 | } | ||
| 72 | |||
| 73 | static int clk_dummy_enable(struct clk *clk, int enable) | ||
| 74 | { | ||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | |||
| 78 | struct clk clk_hd0 = { | ||
| 79 | .name = "hclkd0", | ||
| 80 | .id = -1, | ||
| 81 | .rate = 0, | ||
| 82 | .parent = NULL, | ||
| 83 | .ctrlbit = 0, | ||
| 84 | .set_rate = clk_default_setrate, | ||
| 85 | .enable = clk_dummy_enable, | ||
| 86 | }; | ||
| 87 | |||
| 88 | struct clk clk_pd0 = { | ||
| 89 | .name = "pclkd0", | ||
| 90 | .id = -1, | ||
| 91 | .rate = 0, | ||
| 92 | .parent = NULL, | ||
| 93 | .ctrlbit = 0, | ||
| 94 | .set_rate = clk_default_setrate, | ||
| 95 | .enable = clk_dummy_enable, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) | ||
| 99 | { | ||
| 100 | unsigned int ctrlbit = clk->ctrlbit; | ||
| 101 | u32 con; | ||
| 102 | |||
| 103 | con = __raw_readl(reg); | ||
| 104 | if (enable) | ||
| 105 | con |= ctrlbit; | ||
| 106 | else | ||
| 107 | con &= ~ctrlbit; | ||
| 108 | __raw_writel(con, reg); | ||
| 109 | |||
| 110 | return 0; | ||
| 111 | } | ||
| 112 | |||
| 113 | static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable) | ||
| 114 | { | ||
| 115 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); | ||
| 116 | } | ||
| 117 | |||
| 118 | static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable) | ||
| 119 | { | ||
| 120 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); | ||
| 121 | } | ||
| 122 | |||
| 123 | static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable) | ||
| 124 | { | ||
| 125 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); | ||
| 126 | } | ||
| 127 | |||
| 128 | static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable) | ||
| 129 | { | ||
| 130 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); | ||
| 131 | } | ||
| 132 | |||
| 133 | static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable) | ||
| 134 | { | ||
| 135 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); | ||
| 136 | } | ||
| 137 | |||
| 138 | static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable) | ||
| 139 | { | ||
| 140 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); | ||
| 141 | } | ||
| 142 | |||
| 143 | static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable) | ||
| 144 | { | ||
| 145 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); | ||
| 146 | } | ||
| 147 | |||
| 148 | static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable) | ||
| 149 | { | ||
| 150 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); | ||
| 151 | } | ||
| 152 | |||
| 153 | static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable) | ||
| 154 | { | ||
| 155 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); | ||
| 156 | } | ||
| 157 | |||
| 158 | static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable) | ||
| 159 | { | ||
| 160 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); | ||
| 161 | } | ||
| 162 | |||
| 163 | int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | ||
| 164 | { | ||
| 165 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); | ||
| 166 | } | ||
| 167 | |||
| 168 | int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | ||
| 169 | { | ||
| 170 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); | ||
| 171 | } | ||
| 172 | |||
| 173 | static struct clk s5pc100_init_clocks_disable[] = { | ||
| 174 | { | ||
| 175 | .name = "dsi", | ||
| 176 | .id = -1, | ||
| 177 | .parent = &clk_p, | ||
| 178 | .enable = s5pc100_clk_d11_ctrl, | ||
| 179 | .ctrlbit = S5PC100_CLKGATE_D11_DSI, | ||
| 180 | }, { | ||
| 181 | .name = "csi", | ||
| 182 | .id = -1, | ||
| 183 | .parent = &clk_h, | ||
| 184 | .enable = s5pc100_clk_d11_ctrl, | ||
| 185 | .ctrlbit = S5PC100_CLKGATE_D11_CSI, | ||
| 186 | }, { | ||
| 187 | .name = "ccan", | ||
| 188 | .id = 0, | ||
| 189 | .parent = &clk_p, | ||
| 190 | .enable = s5pc100_clk_d14_ctrl, | ||
| 191 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, | ||
| 192 | }, { | ||
| 193 | .name = "ccan", | ||
| 194 | .id = 1, | ||
| 195 | .parent = &clk_p, | ||
| 196 | .enable = s5pc100_clk_d14_ctrl, | ||
| 197 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, | ||
| 198 | }, { | ||
| 199 | .name = "keypad", | ||
| 200 | .id = -1, | ||
| 201 | .parent = &clk_p, | ||
| 202 | .enable = s5pc100_clk_d15_ctrl, | ||
| 203 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
| 204 | }, { | ||
| 205 | .name = "hclkd2", | ||
| 206 | .id = -1, | ||
| 207 | .parent = NULL, | ||
| 208 | .enable = s5pc100_clk_d20_ctrl, | ||
| 209 | .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, | ||
| 210 | }, { | ||
| 211 | .name = "iis-d2", | ||
| 212 | .id = -1, | ||
| 213 | .parent = NULL, | ||
| 214 | .enable = s5pc100_clk_d20_ctrl, | ||
| 215 | .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, | ||
| 216 | }, | ||
| 217 | }; | ||
| 218 | |||
| 219 | static struct clk s5pc100_init_clocks[] = { | ||
| 220 | /* System1 (D0_0) devices */ | ||
| 221 | { | ||
| 222 | .name = "intc", | ||
| 223 | .id = -1, | ||
| 224 | .parent = &clk_hd0, | ||
| 225 | .enable = s5pc100_clk_d00_ctrl, | ||
| 226 | .ctrlbit = S5PC100_CLKGATE_D00_INTC, | ||
| 227 | }, { | ||
| 228 | .name = "tzic", | ||
| 229 | .id = -1, | ||
| 230 | .parent = &clk_hd0, | ||
| 231 | .enable = s5pc100_clk_d00_ctrl, | ||
| 232 | .ctrlbit = S5PC100_CLKGATE_D00_TZIC, | ||
| 233 | }, { | ||
| 234 | .name = "cf-ata", | ||
| 235 | .id = -1, | ||
| 236 | .parent = &clk_hd0, | ||
| 237 | .enable = s5pc100_clk_d00_ctrl, | ||
| 238 | .ctrlbit = S5PC100_CLKGATE_D00_CFCON, | ||
| 239 | }, { | ||
| 240 | .name = "mdma", | ||
| 241 | .id = -1, | ||
| 242 | .parent = &clk_hd0, | ||
| 243 | .enable = s5pc100_clk_d00_ctrl, | ||
| 244 | .ctrlbit = S5PC100_CLKGATE_D00_MDMA, | ||
| 245 | }, { | ||
| 246 | .name = "g2d", | ||
| 247 | .id = -1, | ||
| 248 | .parent = &clk_hd0, | ||
| 249 | .enable = s5pc100_clk_d00_ctrl, | ||
| 250 | .ctrlbit = S5PC100_CLKGATE_D00_G2D, | ||
| 251 | }, { | ||
| 252 | .name = "secss", | ||
| 253 | .id = -1, | ||
| 254 | .parent = &clk_hd0, | ||
| 255 | .enable = s5pc100_clk_d00_ctrl, | ||
| 256 | .ctrlbit = S5PC100_CLKGATE_D00_SECSS, | ||
| 257 | }, { | ||
| 258 | .name = "cssys", | ||
| 259 | .id = -1, | ||
| 260 | .parent = &clk_hd0, | ||
| 261 | .enable = s5pc100_clk_d00_ctrl, | ||
| 262 | .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, | ||
| 263 | }, | ||
| 264 | |||
| 265 | /* Memory (D0_1) devices */ | ||
| 266 | { | ||
| 267 | .name = "dmc", | ||
| 268 | .id = -1, | ||
| 269 | .parent = &clk_hd0, | ||
| 270 | .enable = s5pc100_clk_d01_ctrl, | ||
| 271 | .ctrlbit = S5PC100_CLKGATE_D01_DMC, | ||
| 272 | }, { | ||
| 273 | .name = "sromc", | ||
| 274 | .id = -1, | ||
| 275 | .parent = &clk_hd0, | ||
| 276 | .enable = s5pc100_clk_d01_ctrl, | ||
| 277 | .ctrlbit = S5PC100_CLKGATE_D01_SROMC, | ||
| 278 | }, { | ||
| 279 | .name = "onenand", | ||
| 280 | .id = -1, | ||
| 281 | .parent = &clk_hd0, | ||
| 282 | .enable = s5pc100_clk_d01_ctrl, | ||
| 283 | .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, | ||
| 284 | }, { | ||
| 285 | .name = "nand", | ||
| 286 | .id = -1, | ||
| 287 | .parent = &clk_hd0, | ||
| 288 | .enable = s5pc100_clk_d01_ctrl, | ||
| 289 | .ctrlbit = S5PC100_CLKGATE_D01_NFCON, | ||
| 290 | }, { | ||
| 291 | .name = "intmem", | ||
| 292 | .id = -1, | ||
| 293 | .parent = &clk_hd0, | ||
| 294 | .enable = s5pc100_clk_d01_ctrl, | ||
| 295 | .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, | ||
| 296 | }, { | ||
| 297 | .name = "ebi", | ||
| 298 | .id = -1, | ||
| 299 | .parent = &clk_hd0, | ||
| 300 | .enable = s5pc100_clk_d01_ctrl, | ||
| 301 | .ctrlbit = S5PC100_CLKGATE_D01_EBI, | ||
| 302 | }, | ||
| 303 | |||
| 304 | /* System2 (D0_2) devices */ | ||
| 305 | { | ||
| 306 | .name = "seckey", | ||
| 307 | .id = -1, | ||
| 308 | .parent = &clk_pd0, | ||
| 309 | .enable = s5pc100_clk_d02_ctrl, | ||
| 310 | .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, | ||
| 311 | }, { | ||
| 312 | .name = "sdm", | ||
| 313 | .id = -1, | ||
| 314 | .parent = &clk_hd0, | ||
| 315 | .enable = s5pc100_clk_d02_ctrl, | ||
| 316 | .ctrlbit = S5PC100_CLKGATE_D02_SDM, | ||
| 317 | }, | ||
| 318 | |||
| 319 | /* File (D1_0) devices */ | ||
| 320 | { | ||
| 321 | .name = "pdma", | ||
| 322 | .id = 0, | ||
| 323 | .parent = &clk_h, | ||
| 324 | .enable = s5pc100_clk_d10_ctrl, | ||
| 325 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, | ||
| 326 | }, { | ||
| 327 | .name = "pdma", | ||
| 328 | .id = 1, | ||
| 329 | .parent = &clk_h, | ||
| 330 | .enable = s5pc100_clk_d10_ctrl, | ||
| 331 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, | ||
| 332 | }, { | ||
| 333 | .name = "usb-host", | ||
| 334 | .id = -1, | ||
| 335 | .parent = &clk_h, | ||
| 336 | .enable = s5pc100_clk_d10_ctrl, | ||
| 337 | .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, | ||
| 338 | }, { | ||
| 339 | .name = "otg", | ||
| 340 | .id = -1, | ||
| 341 | .parent = &clk_h, | ||
| 342 | .enable = s5pc100_clk_d10_ctrl, | ||
| 343 | .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, | ||
| 344 | }, { | ||
| 345 | .name = "modem", | ||
| 346 | .id = -1, | ||
| 347 | .parent = &clk_h, | ||
| 348 | .enable = s5pc100_clk_d10_ctrl, | ||
| 349 | .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, | ||
| 350 | }, { | ||
| 351 | .name = "hsmmc", | ||
| 352 | .id = 0, | ||
| 353 | .parent = &clk_48m, | ||
| 354 | .enable = s5pc100_clk_d10_ctrl, | ||
| 355 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, | ||
| 356 | }, { | ||
| 357 | .name = "hsmmc", | ||
| 358 | .id = 1, | ||
| 359 | .parent = &clk_48m, | ||
| 360 | .enable = s5pc100_clk_d10_ctrl, | ||
| 361 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, | ||
| 362 | }, { | ||
| 363 | .name = "hsmmc", | ||
| 364 | .id = 2, | ||
| 365 | .parent = &clk_48m, | ||
| 366 | .enable = s5pc100_clk_d10_ctrl, | ||
| 367 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, | ||
| 368 | }, | ||
| 369 | |||
| 370 | /* Multimedia1 (D1_1) devices */ | ||
| 371 | { | ||
| 372 | .name = "lcd", | ||
| 373 | .id = -1, | ||
| 374 | .parent = &clk_p, | ||
| 375 | .enable = s5pc100_clk_d11_ctrl, | ||
| 376 | .ctrlbit = S5PC100_CLKGATE_D11_LCD, | ||
| 377 | }, { | ||
| 378 | .name = "rotator", | ||
| 379 | .id = -1, | ||
| 380 | .parent = &clk_p, | ||
| 381 | .enable = s5pc100_clk_d11_ctrl, | ||
| 382 | .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, | ||
| 383 | }, { | ||
| 384 | .name = "fimc", | ||
| 385 | .id = -1, | ||
| 386 | .parent = &clk_p, | ||
| 387 | .enable = s5pc100_clk_d11_ctrl, | ||
| 388 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, | ||
| 389 | }, { | ||
| 390 | .name = "fimc", | ||
| 391 | .id = -1, | ||
| 392 | .parent = &clk_p, | ||
| 393 | .enable = s5pc100_clk_d11_ctrl, | ||
| 394 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, | ||
| 395 | }, { | ||
| 396 | .name = "fimc", | ||
| 397 | .id = -1, | ||
| 398 | .parent = &clk_p, | ||
| 399 | .enable = s5pc100_clk_d11_ctrl, | ||
| 400 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, | ||
| 401 | }, { | ||
| 402 | .name = "jpeg", | ||
| 403 | .id = -1, | ||
| 404 | .parent = &clk_p, | ||
| 405 | .enable = s5pc100_clk_d11_ctrl, | ||
| 406 | .ctrlbit = S5PC100_CLKGATE_D11_JPEG, | ||
| 407 | }, { | ||
| 408 | .name = "g3d", | ||
| 409 | .id = -1, | ||
| 410 | .parent = &clk_p, | ||
| 411 | .enable = s5pc100_clk_d11_ctrl, | ||
| 412 | .ctrlbit = S5PC100_CLKGATE_D11_G3D, | ||
| 413 | }, | ||
| 414 | |||
| 415 | /* Multimedia2 (D1_2) devices */ | ||
| 416 | { | ||
| 417 | .name = "tv", | ||
| 418 | .id = -1, | ||
| 419 | .parent = &clk_p, | ||
| 420 | .enable = s5pc100_clk_d12_ctrl, | ||
| 421 | .ctrlbit = S5PC100_CLKGATE_D12_TV, | ||
| 422 | }, { | ||
| 423 | .name = "vp", | ||
| 424 | .id = -1, | ||
| 425 | .parent = &clk_p, | ||
| 426 | .enable = s5pc100_clk_d12_ctrl, | ||
| 427 | .ctrlbit = S5PC100_CLKGATE_D12_VP, | ||
| 428 | }, { | ||
| 429 | .name = "mixer", | ||
| 430 | .id = -1, | ||
| 431 | .parent = &clk_p, | ||
| 432 | .enable = s5pc100_clk_d12_ctrl, | ||
| 433 | .ctrlbit = S5PC100_CLKGATE_D12_MIXER, | ||
| 434 | }, { | ||
| 435 | .name = "hdmi", | ||
| 436 | .id = -1, | ||
| 437 | .parent = &clk_p, | ||
| 438 | .enable = s5pc100_clk_d12_ctrl, | ||
| 439 | .ctrlbit = S5PC100_CLKGATE_D12_HDMI, | ||
| 440 | }, { | ||
| 441 | .name = "mfc", | ||
| 442 | .id = -1, | ||
| 443 | .parent = &clk_p, | ||
| 444 | .enable = s5pc100_clk_d12_ctrl, | ||
| 445 | .ctrlbit = S5PC100_CLKGATE_D12_MFC, | ||
| 446 | }, | ||
| 447 | |||
| 448 | /* System (D1_3) devices */ | ||
| 449 | { | ||
| 450 | .name = "chipid", | ||
| 451 | .id = -1, | ||
| 452 | .parent = &clk_p, | ||
| 453 | .enable = s5pc100_clk_d13_ctrl, | ||
| 454 | .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, | ||
| 455 | }, { | ||
| 456 | .name = "gpio", | ||
| 457 | .id = -1, | ||
| 458 | .parent = &clk_p, | ||
| 459 | .enable = s5pc100_clk_d13_ctrl, | ||
| 460 | .ctrlbit = S5PC100_CLKGATE_D13_GPIO, | ||
| 461 | }, { | ||
| 462 | .name = "apc", | ||
| 463 | .id = -1, | ||
| 464 | .parent = &clk_p, | ||
| 465 | .enable = s5pc100_clk_d13_ctrl, | ||
| 466 | .ctrlbit = S5PC100_CLKGATE_D13_APC, | ||
| 467 | }, { | ||
| 468 | .name = "iec", | ||
| 469 | .id = -1, | ||
| 470 | .parent = &clk_p, | ||
| 471 | .enable = s5pc100_clk_d13_ctrl, | ||
| 472 | .ctrlbit = S5PC100_CLKGATE_D13_IEC, | ||
| 473 | }, { | ||
| 474 | .name = "timers", | ||
| 475 | .id = -1, | ||
| 476 | .parent = &clk_p, | ||
| 477 | .enable = s5pc100_clk_d13_ctrl, | ||
| 478 | .ctrlbit = S5PC100_CLKGATE_D13_PWM, | ||
| 479 | }, { | ||
| 480 | .name = "systimer", | ||
| 481 | .id = -1, | ||
| 482 | .parent = &clk_p, | ||
| 483 | .enable = s5pc100_clk_d13_ctrl, | ||
| 484 | .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, | ||
| 485 | }, { | ||
| 486 | .name = "watchdog", | ||
| 487 | .id = -1, | ||
| 488 | .parent = &clk_p, | ||
| 489 | .enable = s5pc100_clk_d13_ctrl, | ||
| 490 | .ctrlbit = S5PC100_CLKGATE_D13_WDT, | ||
| 491 | }, { | ||
| 492 | .name = "rtc", | ||
| 493 | .id = -1, | ||
| 494 | .parent = &clk_p, | ||
| 495 | .enable = s5pc100_clk_d13_ctrl, | ||
| 496 | .ctrlbit = S5PC100_CLKGATE_D13_RTC, | ||
| 497 | }, | ||
| 498 | |||
| 499 | /* Connectivity (D1_4) devices */ | ||
| 500 | { | ||
| 501 | .name = "uart", | ||
| 502 | .id = 0, | ||
| 503 | .parent = &clk_p, | ||
| 504 | .enable = s5pc100_clk_d14_ctrl, | ||
| 505 | .ctrlbit = S5PC100_CLKGATE_D14_UART0, | ||
| 506 | }, { | ||
| 507 | .name = "uart", | ||
| 508 | .id = 1, | ||
| 509 | .parent = &clk_p, | ||
| 510 | .enable = s5pc100_clk_d14_ctrl, | ||
| 511 | .ctrlbit = S5PC100_CLKGATE_D14_UART1, | ||
| 512 | }, { | ||
| 513 | .name = "uart", | ||
| 514 | .id = 2, | ||
| 515 | .parent = &clk_p, | ||
| 516 | .enable = s5pc100_clk_d14_ctrl, | ||
| 517 | .ctrlbit = S5PC100_CLKGATE_D14_UART2, | ||
| 518 | }, { | ||
| 519 | .name = "uart", | ||
| 520 | .id = 3, | ||
| 521 | .parent = &clk_p, | ||
| 522 | .enable = s5pc100_clk_d14_ctrl, | ||
| 523 | .ctrlbit = S5PC100_CLKGATE_D14_UART3, | ||
| 524 | }, { | ||
| 525 | .name = "i2c", | ||
| 526 | .id = -1, | ||
| 527 | .parent = &clk_p, | ||
| 528 | .enable = s5pc100_clk_d14_ctrl, | ||
| 529 | .ctrlbit = S5PC100_CLKGATE_D14_IIC, | ||
| 530 | }, { | ||
| 531 | .name = "hdmi-i2c", | ||
| 532 | .id = -1, | ||
| 533 | .parent = &clk_p, | ||
| 534 | .enable = s5pc100_clk_d14_ctrl, | ||
| 535 | .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, | ||
| 536 | }, { | ||
| 537 | .name = "spi", | ||
| 538 | .id = 0, | ||
| 539 | .parent = &clk_p, | ||
| 540 | .enable = s5pc100_clk_d14_ctrl, | ||
| 541 | .ctrlbit = S5PC100_CLKGATE_D14_SPI0, | ||
| 542 | }, { | ||
| 543 | .name = "spi", | ||
| 544 | .id = 1, | ||
| 545 | .parent = &clk_p, | ||
| 546 | .enable = s5pc100_clk_d14_ctrl, | ||
| 547 | .ctrlbit = S5PC100_CLKGATE_D14_SPI1, | ||
| 548 | }, { | ||
| 549 | .name = "spi", | ||
| 550 | .id = 2, | ||
| 551 | .parent = &clk_p, | ||
| 552 | .enable = s5pc100_clk_d14_ctrl, | ||
| 553 | .ctrlbit = S5PC100_CLKGATE_D14_SPI2, | ||
| 554 | }, { | ||
| 555 | .name = "irda", | ||
| 556 | .id = -1, | ||
| 557 | .parent = &clk_p, | ||
| 558 | .enable = s5pc100_clk_d14_ctrl, | ||
| 559 | .ctrlbit = S5PC100_CLKGATE_D14_IRDA, | ||
| 560 | }, { | ||
| 561 | .name = "hsitx", | ||
| 562 | .id = -1, | ||
| 563 | .parent = &clk_p, | ||
| 564 | .enable = s5pc100_clk_d14_ctrl, | ||
| 565 | .ctrlbit = S5PC100_CLKGATE_D14_HSITX, | ||
| 566 | }, { | ||
| 567 | .name = "hsirx", | ||
| 568 | .id = -1, | ||
| 569 | .parent = &clk_p, | ||
| 570 | .enable = s5pc100_clk_d14_ctrl, | ||
| 571 | .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, | ||
| 572 | }, | ||
| 573 | |||
| 574 | /* Audio (D1_5) devices */ | ||
| 575 | { | ||
| 576 | .name = "iis", | ||
| 577 | .id = 0, | ||
| 578 | .parent = &clk_p, | ||
| 579 | .enable = s5pc100_clk_d15_ctrl, | ||
| 580 | .ctrlbit = S5PC100_CLKGATE_D15_IIS0, | ||
| 581 | }, { | ||
| 582 | .name = "iis", | ||
| 583 | .id = 1, | ||
| 584 | .parent = &clk_p, | ||
| 585 | .enable = s5pc100_clk_d15_ctrl, | ||
| 586 | .ctrlbit = S5PC100_CLKGATE_D15_IIS1, | ||
| 587 | }, { | ||
| 588 | .name = "iis", | ||
| 589 | .id = 2, | ||
| 590 | .parent = &clk_p, | ||
| 591 | .enable = s5pc100_clk_d15_ctrl, | ||
| 592 | .ctrlbit = S5PC100_CLKGATE_D15_IIS2, | ||
| 593 | }, { | ||
| 594 | .name = "ac97", | ||
| 595 | .id = -1, | ||
| 596 | .parent = &clk_p, | ||
| 597 | .enable = s5pc100_clk_d15_ctrl, | ||
| 598 | .ctrlbit = S5PC100_CLKGATE_D15_AC97, | ||
| 599 | }, { | ||
| 600 | .name = "pcm", | ||
| 601 | .id = 0, | ||
| 602 | .parent = &clk_p, | ||
| 603 | .enable = s5pc100_clk_d15_ctrl, | ||
| 604 | .ctrlbit = S5PC100_CLKGATE_D15_PCM0, | ||
| 605 | }, { | ||
| 606 | .name = "pcm", | ||
| 607 | .id = 1, | ||
| 608 | .parent = &clk_p, | ||
| 609 | .enable = s5pc100_clk_d15_ctrl, | ||
| 610 | .ctrlbit = S5PC100_CLKGATE_D15_PCM1, | ||
| 611 | }, { | ||
| 612 | .name = "spdif", | ||
| 613 | .id = -1, | ||
| 614 | .parent = &clk_p, | ||
| 615 | .enable = s5pc100_clk_d15_ctrl, | ||
| 616 | .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, | ||
| 617 | }, { | ||
| 618 | .name = "adc", | ||
| 619 | .id = -1, | ||
| 620 | .parent = &clk_p, | ||
| 621 | .enable = s5pc100_clk_d15_ctrl, | ||
| 622 | .ctrlbit = S5PC100_CLKGATE_D15_TSADC, | ||
| 623 | }, { | ||
| 624 | .name = "cg", | ||
| 625 | .id = -1, | ||
| 626 | .parent = &clk_p, | ||
| 627 | .enable = s5pc100_clk_d15_ctrl, | ||
| 628 | .ctrlbit = S5PC100_CLKGATE_D15_CG, | ||
| 629 | }, | ||
| 630 | |||
| 631 | /* Audio (D2_0) devices: all disabled */ | ||
| 632 | |||
| 633 | /* Special Clocks 0 */ | ||
| 634 | { | ||
| 635 | .name = "sclk_hpm", | ||
| 636 | .id = -1, | ||
| 637 | .parent = NULL, | ||
| 638 | .enable = s5pc100_sclk0_ctrl, | ||
| 639 | .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, | ||
| 640 | }, { | ||
| 641 | .name = "sclk_onenand", | ||
| 642 | .id = -1, | ||
| 643 | .parent = NULL, | ||
| 644 | .enable = s5pc100_sclk0_ctrl, | ||
| 645 | .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, | ||
| 646 | }, { | ||
| 647 | .name = "spi_48", | ||
| 648 | .id = 0, | ||
| 649 | .parent = &clk_48m, | ||
| 650 | .enable = s5pc100_sclk0_ctrl, | ||
| 651 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, | ||
| 652 | }, { | ||
| 653 | .name = "spi_48", | ||
| 654 | .id = 1, | ||
| 655 | .parent = &clk_48m, | ||
| 656 | .enable = s5pc100_sclk0_ctrl, | ||
| 657 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, | ||
| 658 | }, { | ||
| 659 | .name = "spi_48", | ||
| 660 | .id = 2, | ||
| 661 | .parent = &clk_48m, | ||
| 662 | .enable = s5pc100_sclk0_ctrl, | ||
| 663 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, | ||
| 664 | }, { | ||
| 665 | .name = "mmc_48", | ||
| 666 | .id = 0, | ||
| 667 | .parent = &clk_48m, | ||
| 668 | .enable = s5pc100_sclk0_ctrl, | ||
| 669 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, | ||
| 670 | }, { | ||
| 671 | .name = "mmc_48", | ||
| 672 | .id = 1, | ||
| 673 | .parent = &clk_48m, | ||
| 674 | .enable = s5pc100_sclk0_ctrl, | ||
| 675 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, | ||
| 676 | }, { | ||
| 677 | .name = "mmc_48", | ||
| 678 | .id = 2, | ||
| 679 | .parent = &clk_48m, | ||
| 680 | .enable = s5pc100_sclk0_ctrl, | ||
| 681 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, | ||
| 682 | }, | ||
| 683 | /* Special Clocks 1 */ | ||
| 684 | }; | ||
| 685 | |||
| 686 | static struct clk *clks[] __initdata = { | ||
| 687 | &clk_ext, | ||
| 688 | &clk_epll, | ||
| 689 | &clk_27m, | ||
| 690 | &clk_48m, | ||
| 691 | &clk_54m, | ||
| 692 | }; | ||
| 693 | |||
| 694 | void __init s5pc1xx_register_clocks(void) | ||
| 695 | { | ||
| 696 | struct clk *clkp; | ||
| 697 | int ret; | ||
| 698 | int ptr; | ||
| 699 | int size; | ||
| 700 | |||
| 701 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
| 702 | |||
| 703 | clkp = s5pc100_init_clocks; | ||
| 704 | size = ARRAY_SIZE(s5pc100_init_clocks); | ||
| 705 | |||
| 706 | for (ptr = 0; ptr < size; ptr++, clkp++) { | ||
| 707 | ret = s3c24xx_register_clock(clkp); | ||
| 708 | if (ret < 0) { | ||
| 709 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 710 | clkp->name, ret); | ||
| 711 | } | ||
| 712 | } | ||
| 713 | |||
| 714 | clkp = s5pc100_init_clocks_disable; | ||
| 715 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); | ||
| 716 | |||
| 717 | for (ptr = 0; ptr < size; ptr++, clkp++) { | ||
| 718 | ret = s3c24xx_register_clock(clkp); | ||
| 719 | if (ret < 0) { | ||
| 720 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 721 | clkp->name, ret); | ||
| 722 | } | ||
| 723 | |||
| 724 | (clkp->enable)(clkp, 0); | ||
| 725 | } | ||
| 726 | |||
| 727 | s3c_pwmclk_init(); | ||
| 728 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c index 715a7330794d..02baeaa2a121 100644 --- a/arch/arm/plat-s5pc1xx/cpu.c +++ b/arch/arm/plat-s5pc1xx/cpu.c | |||
| @@ -55,6 +55,16 @@ static struct cpu_table cpu_ids[] __initdata = { | |||
| 55 | 55 | ||
| 56 | static struct map_desc s5pc1xx_iodesc[] __initdata = { | 56 | static struct map_desc s5pc1xx_iodesc[] __initdata = { |
| 57 | { | 57 | { |
| 58 | .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER, | ||
| 59 | .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER), | ||
| 60 | .length = SZ_4K, | ||
| 61 | .type = MT_DEVICE, | ||
| 62 | }, { | ||
| 63 | .virtual = (unsigned long)S5PC1XX_VA_GPIO, | ||
| 64 | .pfn = __phys_to_pfn(S5PC100_PA_GPIO), | ||
| 65 | .length = SZ_4K, | ||
| 66 | .type = MT_DEVICE, | ||
| 67 | }, { | ||
| 58 | .virtual = (unsigned long)S5PC1XX_VA_CHIPID, | 68 | .virtual = (unsigned long)S5PC1XX_VA_CHIPID, |
| 59 | .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), | 69 | .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), |
| 60 | .length = SZ_16, | 70 | .length = SZ_16, |
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c new file mode 100644 index 000000000000..bba675df9c75 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/gpio-config.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/gpio-config.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics | ||
| 4 | * | ||
| 5 | * S5PC1XX GPIO Configuration. | ||
| 6 | * | ||
| 7 | * Based on plat-s3c64xx/gpio-config.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <mach/gpio-core.h> | ||
| 20 | #include <plat/gpio-cfg-s5pc1xx.h> | ||
| 21 | |||
| 22 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) | ||
| 23 | { | ||
| 24 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
| 25 | void __iomem *reg; | ||
| 26 | int shift = off * 2; | ||
| 27 | u32 drvstr; | ||
| 28 | |||
| 29 | if (!chip) | ||
| 30 | return -EINVAL; | ||
| 31 | |||
| 32 | reg = chip->base + 0x0C; | ||
| 33 | |||
| 34 | drvstr = __raw_readl(reg); | ||
| 35 | drvstr = 0xffff & (0x3 << shift); | ||
| 36 | drvstr = drvstr >> shift; | ||
| 37 | |||
| 38 | return (__force s5p_gpio_drvstr_t)drvstr; | ||
| 39 | } | ||
| 40 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | ||
| 41 | |||
| 42 | int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, | ||
| 43 | s5p_gpio_drvstr_t drvstr) | ||
| 44 | { | ||
| 45 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
| 46 | void __iomem *reg; | ||
| 47 | int shift = off * 2; | ||
| 48 | u32 tmp; | ||
| 49 | |||
| 50 | if (!chip) | ||
| 51 | return -EINVAL; | ||
| 52 | |||
| 53 | reg = chip->base + 0x0C; | ||
| 54 | |||
| 55 | tmp = __raw_readl(reg); | ||
| 56 | tmp |= drvstr << shift; | ||
| 57 | |||
| 58 | __raw_writel(tmp, reg); | ||
| 59 | |||
| 60 | return 0; | ||
| 61 | } | ||
| 62 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | ||
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/plat-s5pc1xx/gpiolib.c new file mode 100644 index 000000000000..facb410e7a71 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/gpiolib.c | |||
| @@ -0,0 +1,503 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-s5pc1xx/gpiolib.c | ||
| 3 | * | ||
| 4 | * Copyright 2009 Samsung Electronics Co | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * S5PC1XX - GPIOlib support | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | |||
| 19 | #include <mach/map.h> | ||
| 20 | #include <mach/gpio-core.h> | ||
| 21 | |||
| 22 | #include <plat/gpio-cfg.h> | ||
| 23 | #include <plat/gpio-cfg-helpers.h> | ||
| 24 | #include <plat/regs-gpio.h> | ||
| 25 | |||
| 26 | /* S5PC100 GPIO bank summary: | ||
| 27 | * | ||
| 28 | * Bank GPIOs Style INT Type | ||
| 29 | * A0 8 4Bit GPIO_INT0 | ||
| 30 | * A1 5 4Bit GPIO_INT1 | ||
| 31 | * B 8 4Bit GPIO_INT2 | ||
| 32 | * C 5 4Bit GPIO_INT3 | ||
| 33 | * D 7 4Bit GPIO_INT4 | ||
| 34 | * E0 8 4Bit GPIO_INT5 | ||
| 35 | * E1 6 4Bit GPIO_INT6 | ||
| 36 | * F0 8 4Bit GPIO_INT7 | ||
| 37 | * F1 8 4Bit GPIO_INT8 | ||
| 38 | * F2 8 4Bit GPIO_INT9 | ||
| 39 | * F3 4 4Bit GPIO_INT10 | ||
| 40 | * G0 8 4Bit GPIO_INT11 | ||
| 41 | * G1 3 4Bit GPIO_INT12 | ||
| 42 | * G2 7 4Bit GPIO_INT13 | ||
| 43 | * G3 7 4Bit GPIO_INT14 | ||
| 44 | * H0 8 4Bit WKUP_INT | ||
| 45 | * H1 8 4Bit WKUP_INT | ||
| 46 | * H2 8 4Bit WKUP_INT | ||
| 47 | * H3 8 4Bit WKUP_INT | ||
| 48 | * I 8 4Bit GPIO_INT15 | ||
| 49 | * J0 8 4Bit GPIO_INT16 | ||
| 50 | * J1 5 4Bit GPIO_INT17 | ||
| 51 | * J2 8 4Bit GPIO_INT18 | ||
| 52 | * J3 8 4Bit GPIO_INT19 | ||
| 53 | * J4 4 4Bit GPIO_INT20 | ||
| 54 | * K0 8 4Bit None | ||
| 55 | * K1 6 4Bit None | ||
| 56 | * K2 8 4Bit None | ||
| 57 | * K3 8 4Bit None | ||
| 58 | * L0 8 4Bit None | ||
| 59 | * L1 8 4Bit None | ||
| 60 | * L2 8 4Bit None | ||
| 61 | * L3 8 4Bit None | ||
| 62 | */ | ||
| 63 | |||
| 64 | #define OFF_GPCON (0x00) | ||
| 65 | #define OFF_GPDAT (0x04) | ||
| 66 | |||
| 67 | #define con_4bit_shift(__off) ((__off) * 4) | ||
| 68 | |||
| 69 | #if 1 | ||
| 70 | #define gpio_dbg(x...) do { } while (0) | ||
| 71 | #else | ||
| 72 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
| 73 | #endif | ||
| 74 | |||
| 75 | /* The s5pc1xx_gpiolib routines are to control the gpio banks where | ||
| 76 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
| 77 | * following example: | ||
| 78 | * | ||
| 79 | * base + 0x00: Control register, 4 bits per gpio | ||
| 80 | * gpio n: 4 bits starting at (4*n) | ||
| 81 | * 0000 = input, 0001 = output, others mean special-function | ||
| 82 | * base + 0x04: Data register, 1 bit per gpio | ||
| 83 | * bit n: data bit n | ||
| 84 | * | ||
| 85 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
| 86 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
| 87 | * the output. | ||
| 88 | */ | ||
| 89 | |||
| 90 | static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) | ||
| 91 | { | ||
| 92 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 93 | void __iomem *base = ourchip->base; | ||
| 94 | unsigned long con; | ||
| 95 | |||
| 96 | con = __raw_readl(base + OFF_GPCON); | ||
| 97 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 98 | __raw_writel(con, base + OFF_GPCON); | ||
| 99 | |||
| 100 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
| 101 | |||
| 102 | return 0; | ||
| 103 | } | ||
| 104 | |||
| 105 | static int s5pc1xx_gpiolib_output(struct gpio_chip *chip, | ||
| 106 | unsigned offset, int value) | ||
| 107 | { | ||
| 108 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
| 109 | void __iomem *base = ourchip->base; | ||
| 110 | unsigned long con; | ||
| 111 | unsigned long dat; | ||
| 112 | |||
| 113 | con = __raw_readl(base + OFF_GPCON); | ||
| 114 | con &= ~(0xf << con_4bit_shift(offset)); | ||
| 115 | con |= 0x1 << con_4bit_shift(offset); | ||
| 116 | |||
| 117 | dat = __raw_readl(base + OFF_GPDAT); | ||
| 118 | if (value) | ||
| 119 | dat |= 1 << offset; | ||
| 120 | else | ||
| 121 | dat &= ~(1 << offset); | ||
| 122 | |||
| 123 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 124 | __raw_writel(con, base + OFF_GPCON); | ||
| 125 | __raw_writel(dat, base + OFF_GPDAT); | ||
| 126 | |||
| 127 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
| 128 | |||
| 129 | return 0; | ||
| 130 | } | ||
| 131 | |||
| 132 | static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | ||
| 133 | { | ||
| 134 | return S3C_IRQ_GPIO(chip->base + offset); | ||
| 135 | } | ||
| 136 | |||
| 137 | static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) | ||
| 138 | { | ||
| 139 | int base; | ||
| 140 | |||
| 141 | base = chip->base - S5PC100_GPH0(0); | ||
| 142 | if (base == 0) | ||
| 143 | return IRQ_EINT(offset); | ||
| 144 | base = chip->base - S5PC100_GPH1(0); | ||
| 145 | if (base == 0) | ||
| 146 | return IRQ_EINT(8 + offset); | ||
| 147 | base = chip->base - S5PC100_GPH2(0); | ||
| 148 | if (base == 0) | ||
| 149 | return IRQ_EINT(16 + offset); | ||
| 150 | base = chip->base - S5PC100_GPH3(0); | ||
| 151 | if (base == 0) | ||
| 152 | return IRQ_EINT(24 + offset); | ||
| 153 | return -EINVAL; | ||
| 154 | } | ||
| 155 | |||
| 156 | static struct s3c_gpio_cfg gpio_cfg = { | ||
| 157 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
| 158 | .set_pull = s3c_gpio_setpull_updown, | ||
| 159 | .get_pull = s3c_gpio_getpull_updown, | ||
| 160 | }; | ||
| 161 | |||
| 162 | static struct s3c_gpio_cfg gpio_cfg_eint = { | ||
| 163 | .cfg_eint = 0xf, | ||
| 164 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
| 165 | .set_pull = s3c_gpio_setpull_updown, | ||
| 166 | .get_pull = s3c_gpio_getpull_updown, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct s3c_gpio_cfg gpio_cfg_noint = { | ||
| 170 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
| 171 | .set_pull = s3c_gpio_setpull_updown, | ||
| 172 | .get_pull = s3c_gpio_getpull_updown, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | ||
| 176 | { | ||
| 177 | .base = S5PC100_GPA0_BASE, | ||
| 178 | .config = &gpio_cfg, | ||
| 179 | .chip = { | ||
| 180 | .base = S5PC100_GPA0(0), | ||
| 181 | .ngpio = S5PC100_GPIO_A0_NR, | ||
| 182 | .label = "GPA0", | ||
| 183 | }, | ||
| 184 | }, { | ||
| 185 | .base = S5PC100_GPA1_BASE, | ||
| 186 | .config = &gpio_cfg, | ||
| 187 | .chip = { | ||
| 188 | .base = S5PC100_GPA1(0), | ||
| 189 | .ngpio = S5PC100_GPIO_A1_NR, | ||
| 190 | .label = "GPA1", | ||
| 191 | }, | ||
| 192 | }, { | ||
| 193 | .base = S5PC100_GPB_BASE, | ||
| 194 | .config = &gpio_cfg, | ||
| 195 | .chip = { | ||
| 196 | .base = S5PC100_GPB(0), | ||
| 197 | .ngpio = S5PC100_GPIO_B_NR, | ||
| 198 | .label = "GPB", | ||
| 199 | }, | ||
| 200 | }, { | ||
| 201 | .base = S5PC100_GPC_BASE, | ||
| 202 | .config = &gpio_cfg, | ||
| 203 | .chip = { | ||
| 204 | .base = S5PC100_GPC(0), | ||
| 205 | .ngpio = S5PC100_GPIO_C_NR, | ||
| 206 | .label = "GPC", | ||
| 207 | }, | ||
| 208 | }, { | ||
| 209 | .base = S5PC100_GPD_BASE, | ||
| 210 | .config = &gpio_cfg, | ||
| 211 | .chip = { | ||
| 212 | .base = S5PC100_GPD(0), | ||
| 213 | .ngpio = S5PC100_GPIO_D_NR, | ||
| 214 | .label = "GPD", | ||
| 215 | }, | ||
| 216 | }, { | ||
| 217 | .base = S5PC100_GPE0_BASE, | ||
| 218 | .config = &gpio_cfg, | ||
| 219 | .chip = { | ||
| 220 | .base = S5PC100_GPE0(0), | ||
| 221 | .ngpio = S5PC100_GPIO_E0_NR, | ||
| 222 | .label = "GPE0", | ||
| 223 | }, | ||
| 224 | }, { | ||
| 225 | .base = S5PC100_GPE1_BASE, | ||
| 226 | .config = &gpio_cfg, | ||
| 227 | .chip = { | ||
| 228 | .base = S5PC100_GPE1(0), | ||
| 229 | .ngpio = S5PC100_GPIO_E1_NR, | ||
| 230 | .label = "GPE1", | ||
| 231 | }, | ||
| 232 | }, { | ||
| 233 | .base = S5PC100_GPF0_BASE, | ||
| 234 | .config = &gpio_cfg, | ||
| 235 | .chip = { | ||
| 236 | .base = S5PC100_GPF0(0), | ||
| 237 | .ngpio = S5PC100_GPIO_F0_NR, | ||
| 238 | .label = "GPF0", | ||
| 239 | }, | ||
| 240 | }, { | ||
| 241 | .base = S5PC100_GPF1_BASE, | ||
| 242 | .config = &gpio_cfg, | ||
| 243 | .chip = { | ||
| 244 | .base = S5PC100_GPF1(0), | ||
| 245 | .ngpio = S5PC100_GPIO_F1_NR, | ||
| 246 | .label = "GPF1", | ||
| 247 | }, | ||
| 248 | }, { | ||
| 249 | .base = S5PC100_GPF2_BASE, | ||
| 250 | .config = &gpio_cfg, | ||
| 251 | .chip = { | ||
| 252 | .base = S5PC100_GPF2(0), | ||
| 253 | .ngpio = S5PC100_GPIO_F2_NR, | ||
| 254 | .label = "GPF2", | ||
| 255 | }, | ||
| 256 | }, { | ||
| 257 | .base = S5PC100_GPF3_BASE, | ||
| 258 | .config = &gpio_cfg, | ||
| 259 | .chip = { | ||
| 260 | .base = S5PC100_GPF3(0), | ||
| 261 | .ngpio = S5PC100_GPIO_F3_NR, | ||
| 262 | .label = "GPF3", | ||
| 263 | }, | ||
| 264 | }, { | ||
| 265 | .base = S5PC100_GPG0_BASE, | ||
| 266 | .config = &gpio_cfg, | ||
| 267 | .chip = { | ||
| 268 | .base = S5PC100_GPG0(0), | ||
| 269 | .ngpio = S5PC100_GPIO_G0_NR, | ||
| 270 | .label = "GPG0", | ||
| 271 | }, | ||
| 272 | }, { | ||
| 273 | .base = S5PC100_GPG1_BASE, | ||
| 274 | .config = &gpio_cfg, | ||
| 275 | .chip = { | ||
| 276 | .base = S5PC100_GPG1(0), | ||
| 277 | .ngpio = S5PC100_GPIO_G1_NR, | ||
| 278 | .label = "GPG1", | ||
| 279 | }, | ||
| 280 | }, { | ||
| 281 | .base = S5PC100_GPG2_BASE, | ||
| 282 | .config = &gpio_cfg, | ||
| 283 | .chip = { | ||
| 284 | .base = S5PC100_GPG2(0), | ||
| 285 | .ngpio = S5PC100_GPIO_G2_NR, | ||
| 286 | .label = "GPG2", | ||
| 287 | }, | ||
| 288 | }, { | ||
| 289 | .base = S5PC100_GPG3_BASE, | ||
| 290 | .config = &gpio_cfg, | ||
| 291 | .chip = { | ||
| 292 | .base = S5PC100_GPG3(0), | ||
| 293 | .ngpio = S5PC100_GPIO_G3_NR, | ||
| 294 | .label = "GPG3", | ||
| 295 | }, | ||
| 296 | }, { | ||
| 297 | .base = S5PC100_GPH0_BASE, | ||
| 298 | .config = &gpio_cfg_eint, | ||
| 299 | .chip = { | ||
| 300 | .base = S5PC100_GPH0(0), | ||
| 301 | .ngpio = S5PC100_GPIO_H0_NR, | ||
| 302 | .label = "GPH0", | ||
| 303 | }, | ||
| 304 | }, { | ||
| 305 | .base = S5PC100_GPH1_BASE, | ||
| 306 | .config = &gpio_cfg_eint, | ||
| 307 | .chip = { | ||
| 308 | .base = S5PC100_GPH1(0), | ||
| 309 | .ngpio = S5PC100_GPIO_H1_NR, | ||
| 310 | .label = "GPH1", | ||
| 311 | }, | ||
| 312 | }, { | ||
| 313 | .base = S5PC100_GPH2_BASE, | ||
| 314 | .config = &gpio_cfg_eint, | ||
| 315 | .chip = { | ||
| 316 | .base = S5PC100_GPH2(0), | ||
| 317 | .ngpio = S5PC100_GPIO_H2_NR, | ||
| 318 | .label = "GPH2", | ||
| 319 | }, | ||
| 320 | }, { | ||
| 321 | .base = S5PC100_GPH3_BASE, | ||
| 322 | .config = &gpio_cfg_eint, | ||
| 323 | .chip = { | ||
| 324 | .base = S5PC100_GPH3(0), | ||
| 325 | .ngpio = S5PC100_GPIO_H3_NR, | ||
| 326 | .label = "GPH3", | ||
| 327 | }, | ||
| 328 | }, { | ||
| 329 | .base = S5PC100_GPI_BASE, | ||
| 330 | .config = &gpio_cfg, | ||
| 331 | .chip = { | ||
| 332 | .base = S5PC100_GPI(0), | ||
| 333 | .ngpio = S5PC100_GPIO_I_NR, | ||
| 334 | .label = "GPI", | ||
| 335 | }, | ||
| 336 | }, { | ||
| 337 | .base = S5PC100_GPJ0_BASE, | ||
| 338 | .config = &gpio_cfg, | ||
| 339 | .chip = { | ||
| 340 | .base = S5PC100_GPJ0(0), | ||
| 341 | .ngpio = S5PC100_GPIO_J0_NR, | ||
| 342 | .label = "GPJ0", | ||
| 343 | }, | ||
| 344 | }, { | ||
| 345 | .base = S5PC100_GPJ1_BASE, | ||
| 346 | .config = &gpio_cfg, | ||
| 347 | .chip = { | ||
| 348 | .base = S5PC100_GPJ1(0), | ||
| 349 | .ngpio = S5PC100_GPIO_J1_NR, | ||
| 350 | .label = "GPJ1", | ||
| 351 | }, | ||
| 352 | }, { | ||
| 353 | .base = S5PC100_GPJ2_BASE, | ||
| 354 | .config = &gpio_cfg, | ||
| 355 | .chip = { | ||
| 356 | .base = S5PC100_GPJ2(0), | ||
| 357 | .ngpio = S5PC100_GPIO_J2_NR, | ||
| 358 | .label = "GPJ2", | ||
| 359 | }, | ||
| 360 | }, { | ||
| 361 | .base = S5PC100_GPJ3_BASE, | ||
| 362 | .config = &gpio_cfg, | ||
| 363 | .chip = { | ||
| 364 | .base = S5PC100_GPJ3(0), | ||
| 365 | .ngpio = S5PC100_GPIO_J3_NR, | ||
| 366 | .label = "GPJ3", | ||
| 367 | }, | ||
| 368 | }, { | ||
| 369 | .base = S5PC100_GPJ4_BASE, | ||
| 370 | .config = &gpio_cfg, | ||
| 371 | .chip = { | ||
| 372 | .base = S5PC100_GPJ4(0), | ||
| 373 | .ngpio = S5PC100_GPIO_J4_NR, | ||
| 374 | .label = "GPJ4", | ||
| 375 | }, | ||
| 376 | }, { | ||
| 377 | .base = S5PC100_GPK0_BASE, | ||
| 378 | .config = &gpio_cfg_noint, | ||
| 379 | .chip = { | ||
| 380 | .base = S5PC100_GPK0(0), | ||
| 381 | .ngpio = S5PC100_GPIO_K0_NR, | ||
| 382 | .label = "GPK0", | ||
| 383 | }, | ||
| 384 | }, { | ||
| 385 | .base = S5PC100_GPK1_BASE, | ||
| 386 | .config = &gpio_cfg_noint, | ||
| 387 | .chip = { | ||
| 388 | .base = S5PC100_GPK1(0), | ||
| 389 | .ngpio = S5PC100_GPIO_K1_NR, | ||
| 390 | .label = "GPK1", | ||
| 391 | }, | ||
| 392 | }, { | ||
| 393 | .base = S5PC100_GPK2_BASE, | ||
| 394 | .config = &gpio_cfg_noint, | ||
| 395 | .chip = { | ||
| 396 | .base = S5PC100_GPK2(0), | ||
| 397 | .ngpio = S5PC100_GPIO_K2_NR, | ||
| 398 | .label = "GPK2", | ||
| 399 | }, | ||
| 400 | }, { | ||
| 401 | .base = S5PC100_GPK3_BASE, | ||
| 402 | .config = &gpio_cfg_noint, | ||
| 403 | .chip = { | ||
| 404 | .base = S5PC100_GPK3(0), | ||
| 405 | .ngpio = S5PC100_GPIO_K3_NR, | ||
| 406 | .label = "GPK3", | ||
| 407 | }, | ||
| 408 | }, { | ||
| 409 | .base = S5PC100_GPL0_BASE, | ||
| 410 | .config = &gpio_cfg_noint, | ||
| 411 | .chip = { | ||
| 412 | .base = S5PC100_GPL0(0), | ||
| 413 | .ngpio = S5PC100_GPIO_L0_NR, | ||
| 414 | .label = "GPL0", | ||
| 415 | }, | ||
| 416 | }, { | ||
| 417 | .base = S5PC100_GPL1_BASE, | ||
| 418 | .config = &gpio_cfg_noint, | ||
| 419 | .chip = { | ||
| 420 | .base = S5PC100_GPL1(0), | ||
| 421 | .ngpio = S5PC100_GPIO_L1_NR, | ||
| 422 | .label = "GPL1", | ||
| 423 | }, | ||
| 424 | }, { | ||
| 425 | .base = S5PC100_GPL2_BASE, | ||
| 426 | .config = &gpio_cfg_noint, | ||
| 427 | .chip = { | ||
| 428 | .base = S5PC100_GPL2(0), | ||
| 429 | .ngpio = S5PC100_GPIO_L2_NR, | ||
| 430 | .label = "GPL2", | ||
| 431 | }, | ||
| 432 | }, { | ||
| 433 | .base = S5PC100_GPL3_BASE, | ||
| 434 | .config = &gpio_cfg_noint, | ||
| 435 | .chip = { | ||
| 436 | .base = S5PC100_GPL3(0), | ||
| 437 | .ngpio = S5PC100_GPIO_L3_NR, | ||
| 438 | .label = "GPL3", | ||
| 439 | }, | ||
| 440 | }, { | ||
| 441 | .base = S5PC100_GPL4_BASE, | ||
| 442 | .config = &gpio_cfg_noint, | ||
| 443 | .chip = { | ||
| 444 | .base = S5PC100_GPL4(0), | ||
| 445 | .ngpio = S5PC100_GPIO_L4_NR, | ||
| 446 | .label = "GPL4", | ||
| 447 | }, | ||
| 448 | }, | ||
| 449 | }; | ||
| 450 | |||
| 451 | /* FIXME move from irq-gpio.c */ | ||
| 452 | extern struct irq_chip s5pc1xx_gpioint; | ||
| 453 | extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); | ||
| 454 | |||
| 455 | static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) | ||
| 456 | { | ||
| 457 | chip->chip.direction_input = s5pc1xx_gpiolib_input; | ||
| 458 | chip->chip.direction_output = s5pc1xx_gpiolib_output; | ||
| 459 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
| 460 | |||
| 461 | /* Interrupt */ | ||
| 462 | if (chip->config == &gpio_cfg) { | ||
| 463 | int i, irq; | ||
| 464 | |||
| 465 | chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; | ||
| 466 | |||
| 467 | for (i = 0; i < chip->chip.ngpio; i++) { | ||
| 468 | irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; | ||
| 469 | set_irq_chip(irq, &s5pc1xx_gpioint); | ||
| 470 | set_irq_data(irq, &chip->chip); | ||
| 471 | set_irq_handler(irq, handle_level_irq); | ||
| 472 | set_irq_flags(irq, IRQF_VALID); | ||
| 473 | } | ||
| 474 | } else if (chip->config == &gpio_cfg_eint) | ||
| 475 | chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; | ||
| 476 | } | ||
| 477 | |||
| 478 | static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips, | ||
| 479 | int nr_chips, | ||
| 480 | void (*fn)(struct s3c_gpio_chip *)) | ||
| 481 | { | ||
| 482 | for (; nr_chips > 0; nr_chips--, chips++) { | ||
| 483 | if (fn) | ||
| 484 | (fn)(chips); | ||
| 485 | s3c_gpiolib_add(chips); | ||
| 486 | } | ||
| 487 | } | ||
| 488 | |||
| 489 | static __init int s5pc1xx_gpiolib_init(void) | ||
| 490 | { | ||
| 491 | struct s3c_gpio_chip *chips; | ||
| 492 | int nr_chips; | ||
| 493 | |||
| 494 | chips = s5pc100_gpio_chips; | ||
| 495 | nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); | ||
| 496 | |||
| 497 | s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link); | ||
| 498 | /* Interrupt */ | ||
| 499 | set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); | ||
| 500 | |||
| 501 | return 0; | ||
| 502 | } | ||
| 503 | core_initcall(s5pc1xx_gpiolib_init); | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h new file mode 100644 index 000000000000..72ad59f61efc --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronic | ||
| 4 | * | ||
| 5 | * S5PC1XX Platform - GPIO pin configuration | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* This file contains the necessary definitions to get the basic gpio | ||
| 13 | * pin configuration done such as setting a pin to input or output or | ||
| 14 | * changing the pull-{up,down} configurations. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef __GPIO_CFG_S5PC1XX_H | ||
| 18 | #define __GPIO_CFG_S5PC1XX_H __FILE__ | ||
| 19 | |||
| 20 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; | ||
| 21 | |||
| 22 | #define S5P_GPIO_DRVSTR_LV1 0x00 | ||
| 23 | #define S5P_GPIO_DRVSTR_LV2 0x01 | ||
| 24 | #define S5P_GPIO_DRVSTR_LV3 0x10 | ||
| 25 | #define S5P_GPIO_DRVSTR_LV4 0x11 | ||
| 26 | |||
| 27 | extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off); | ||
| 28 | |||
| 29 | extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, | ||
| 30 | s5p_gpio_drvstr_t drvstr); | ||
| 31 | |||
| 32 | #endif /* __GPIO_CFG_S5PC1XX_H */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h new file mode 100644 index 000000000000..33ad267e8477 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * | ||
| 5 | * External Interrupt (GPH0 ~ GPH3) control register definitions | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0) | ||
| 13 | #define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4) | ||
| 14 | #define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8) | ||
| 15 | #define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC) | ||
| 16 | #define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4)) | ||
| 17 | |||
| 18 | #define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80) | ||
| 19 | #define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84) | ||
| 20 | #define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88) | ||
| 21 | #define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C) | ||
| 22 | #define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90) | ||
| 23 | #define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94) | ||
| 24 | #define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98) | ||
| 25 | #define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C) | ||
| 26 | #define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4)) | ||
| 27 | |||
| 28 | #define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100) | ||
| 29 | #define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104) | ||
| 30 | #define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108) | ||
| 31 | #define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C) | ||
| 32 | #define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4)) | ||
| 33 | |||
| 34 | #define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140) | ||
| 35 | #define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144) | ||
| 36 | #define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148) | ||
| 37 | #define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C) | ||
| 38 | #define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4)) | ||
| 39 | |||
| 40 | #define S5PC1XX_WKUP_INT_LOWLEV (0x00) | ||
| 41 | #define S5PC1XX_WKUP_INT_HILEV (0x01) | ||
| 42 | #define S5PC1XX_WKUP_INT_FALLEDGE (0x02) | ||
| 43 | #define S5PC1XX_WKUP_INT_RISEEDGE (0x03) | ||
| 44 | #define S5PC1XX_WKUP_INT_BOTHEDGE (0x04) | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h index f07d8c3b25d6..ef8736366f0d 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h | |||
| @@ -171,12 +171,21 @@ | |||
| 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) | 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) |
| 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) | 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) |
| 173 | 173 | ||
| 174 | /* External interrupt */ | ||
| 174 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) | 175 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 1) |
| 175 | 176 | ||
| 176 | #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) | 177 | #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) |
| 177 | #define IRQ_EINT(x) S3C_EINT(x) | 178 | #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) |
| 179 | #define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0)) | ||
| 178 | 180 | ||
| 179 | #define NR_IRQS (IRQ_EINT(31)+1) | 181 | /* GPIO interrupt */ |
| 182 | #define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) | ||
| 183 | #define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) | ||
| 184 | |||
| 185 | /* | ||
| 186 | * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs | ||
| 187 | */ | ||
| 188 | #define NR_IRQS (S3C_IRQ_GPIO(320) + 1) | ||
| 180 | 189 | ||
| 181 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ | 190 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ |
| 182 | 191 | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h index 75c8390cb827..c5cc86e92d65 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | |||
| @@ -13,68 +13,69 @@ | |||
| 13 | #ifndef __PLAT_REGS_CLOCK_H | 13 | #ifndef __PLAT_REGS_CLOCK_H |
| 14 | #define __PLAT_REGS_CLOCK_H __FILE__ | 14 | #define __PLAT_REGS_CLOCK_H __FILE__ |
| 15 | 15 | ||
| 16 | #define S5PC1XX_CLKREG(x) (S5PC1XX_VA_CLK + (x)) | 16 | #define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x)) |
| 17 | 17 | #define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x)) | |
| 18 | #define S5PC1XX_APLL_LOCK S5PC1XX_CLKREG(0x00) | 18 | |
| 19 | #define S5PC1XX_MPLL_LOCK S5PC1XX_CLKREG(0x04) | 19 | /* s5pc100 register for clock */ |
| 20 | #define S5PC1XX_EPLL_LOCK S5PC1XX_CLKREG(0x08) | 20 | #define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00) |
| 21 | #define S5PC100_HPLL_LOCK S5PC1XX_CLKREG(0x0C) | 21 | #define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04) |
| 22 | 22 | #define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08) | |
| 23 | #define S5PC1XX_APLL_CON S5PC1XX_CLKREG(0x100) | 23 | #define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C) |
| 24 | #define S5PC1XX_MPLL_CON S5PC1XX_CLKREG(0x104) | 24 | |
| 25 | #define S5PC1XX_EPLL_CON S5PC1XX_CLKREG(0x108) | 25 | #define S5PC100_APLL_CON S5PC100_CLKREG(0x100) |
| 26 | #define S5PC100_HPLL_CON S5PC1XX_CLKREG(0x10C) | 26 | #define S5PC100_MPLL_CON S5PC100_CLKREG(0x104) |
| 27 | 27 | #define S5PC100_EPLL_CON S5PC100_CLKREG(0x108) | |
| 28 | #define S5PC1XX_CLK_SRC0 S5PC1XX_CLKREG(0x200) | 28 | #define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C) |
| 29 | #define S5PC1XX_CLK_SRC1 S5PC1XX_CLKREG(0x204) | 29 | |
| 30 | #define S5PC1XX_CLK_SRC2 S5PC1XX_CLKREG(0x208) | 30 | #define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200) |
| 31 | #define S5PC1XX_CLK_SRC3 S5PC1XX_CLKREG(0x20C) | 31 | #define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204) |
| 32 | 32 | #define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208) | |
| 33 | #define S5PC1XX_CLK_DIV0 S5PC1XX_CLKREG(0x300) | 33 | #define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C) |
| 34 | #define S5PC1XX_CLK_DIV1 S5PC1XX_CLKREG(0x304) | 34 | |
| 35 | #define S5PC1XX_CLK_DIV2 S5PC1XX_CLKREG(0x308) | 35 | #define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300) |
| 36 | #define S5PC1XX_CLK_DIV3 S5PC1XX_CLKREG(0x30C) | 36 | #define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304) |
| 37 | #define S5PC1XX_CLK_DIV4 S5PC1XX_CLKREG(0x310) | 37 | #define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308) |
| 38 | 38 | #define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C) | |
| 39 | #define S5PC100_CLK_OUT S5PC1XX_CLKREG(0x400) | 39 | #define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310) |
| 40 | 40 | ||
| 41 | #define S5PC100_CLKGATE_D00 S5PC1XX_CLKREG(0x500) | 41 | #define S5PC100_CLK_OUT S5PC100_CLKREG(0x400) |
| 42 | #define S5PC100_CLKGATE_D01 S5PC1XX_CLKREG(0x504) | 42 | |
| 43 | #define S5PC100_CLKGATE_D02 S5PC1XX_CLKREG(0x508) | 43 | #define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500) |
| 44 | 44 | #define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504) | |
| 45 | #define S5PC100_CLKGATE_D10 S5PC1XX_CLKREG(0x520) | 45 | #define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508) |
| 46 | #define S5PC100_CLKGATE_D11 S5PC1XX_CLKREG(0x524) | 46 | |
| 47 | #define S5PC100_CLKGATE_D12 S5PC1XX_CLKREG(0x528) | 47 | #define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520) |
| 48 | #define S5PC100_CLKGATE_D13 S5PC1XX_CLKREG(0x52C) | 48 | #define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524) |
| 49 | #define S5PC100_CLKGATE_D14 S5PC1XX_CLKREG(0x530) | 49 | #define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528) |
| 50 | #define S5PC100_CLKGATE_D15 S5PC1XX_CLKREG(0x534) | 50 | #define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C) |
| 51 | 51 | #define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530) | |
| 52 | #define S5PC100_CLKGATE_D20 S5PC1XX_CLKREG(0x540) | 52 | #define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534) |
| 53 | 53 | ||
| 54 | #define S5PC100_SCLKGATE0 S5PC1XX_CLKREG(0x560) | 54 | #define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540) |
| 55 | #define S5PC100_SCLKGATE1 S5PC1XX_CLKREG(0x564) | 55 | |
| 56 | 56 | #define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560) | |
| 57 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) | 57 | #define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564) |
| 58 | 58 | ||
| 59 | #define S5PC1XX_EPLL_EN (1<<31) | 59 | /* EPLL_CON */ |
| 60 | #define S5PC1XX_EPLL_MASK 0xffffffff | 60 | #define S5PC100_EPLL_EN (1<<31) |
| 61 | #define S5PC1XX_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | 61 | #define S5PC100_EPLL_MASK 0xffffffff |
| 62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | ||
| 62 | 63 | ||
| 63 | /* CLKSRC0 */ | 64 | /* CLKSRC0 */ |
| 64 | #define S5PC1XX_CLKSRC0_APLL_MASK (0x1<<0) | 65 | #define S5PC100_CLKSRC0_APLL_MASK (0x1<<0) |
| 65 | #define S5PC1XX_CLKSRC0_APLL_SHIFT (0) | 66 | #define S5PC100_CLKSRC0_APLL_SHIFT (0) |
| 66 | #define S5PC1XX_CLKSRC0_MPLL_MASK (0x1<<4) | 67 | #define S5PC100_CLKSRC0_MPLL_MASK (0x1<<4) |
| 67 | #define S5PC1XX_CLKSRC0_MPLL_SHIFT (4) | 68 | #define S5PC100_CLKSRC0_MPLL_SHIFT (4) |
| 68 | #define S5PC1XX_CLKSRC0_EPLL_MASK (0x1<<8) | 69 | #define S5PC100_CLKSRC0_EPLL_MASK (0x1<<8) |
| 69 | #define S5PC1XX_CLKSRC0_EPLL_SHIFT (8) | 70 | #define S5PC100_CLKSRC0_EPLL_SHIFT (8) |
| 70 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) | 71 | #define S5PC100_CLKSRC0_HPLL_MASK (0x1<<12) |
| 71 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) | 72 | #define S5PC100_CLKSRC0_HPLL_SHIFT (12) |
| 72 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) | 73 | #define S5PC100_CLKSRC0_AMMUX_MASK (0x1<<16) |
| 73 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) | 74 | #define S5PC100_CLKSRC0_AMMUX_SHIFT (16) |
| 74 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) | 75 | #define S5PC100_CLKSRC0_HREF_MASK (0x1<<20) |
| 75 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) | 76 | #define S5PC100_CLKSRC0_HREF_SHIFT (20) |
| 76 | #define S5PC1XX_CLKSRC0_ONENAND_MASK (0x1<<24) | 77 | #define S5PC100_CLKSRC0_ONENAND_MASK (0x1<<24) |
| 77 | #define S5PC1XX_CLKSRC0_ONENAND_SHIFT (24) | 78 | #define S5PC100_CLKSRC0_ONENAND_SHIFT (24) |
| 78 | 79 | ||
| 79 | 80 | ||
| 80 | /* CLKSRC1 */ | 81 | /* CLKSRC1 */ |
| @@ -127,10 +128,9 @@ | |||
| 127 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) | 128 | #define S5PC100_CLKSRC3_SPDIF_MASK (0x3<<24) |
| 128 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) | 129 | #define S5PC100_CLKSRC3_SPDIF_SHIFT (24) |
| 129 | 130 | ||
| 130 | |||
| 131 | /* CLKDIV0 */ | 131 | /* CLKDIV0 */ |
| 132 | #define S5PC1XX_CLKDIV0_APLL_MASK (0x1<<0) | 132 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) |
| 133 | #define S5PC1XX_CLKDIV0_APLL_SHIFT (0) | 133 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) |
| 134 | #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) | 134 | #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) |
| 135 | #define S5PC100_CLKDIV0_ARM_SHIFT (4) | 135 | #define S5PC100_CLKDIV0_ARM_SHIFT (4) |
| 136 | #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) | 136 | #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) |
| @@ -141,8 +141,8 @@ | |||
| 141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) | 141 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) |
| 142 | 142 | ||
| 143 | /* CLKDIV1 */ | 143 | /* CLKDIV1 */ |
| 144 | #define S5PC100_CLKDIV1_AM_MASK (0x7<<0) | 144 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) |
| 145 | #define S5PC100_CLKDIV1_AM_SHIFT (0) | 145 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) |
| 146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) | 146 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) |
| 147 | #define S5PC100_CLKDIV1_MPLL_SHIFT (4) | 147 | #define S5PC100_CLKDIV1_MPLL_SHIFT (4) |
| 148 | #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) | 148 | #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) |
| @@ -202,7 +202,6 @@ | |||
| 202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) | 202 | #define S5PC100_CLKDIV4_AUDIO2_MASK (0xf<<20) |
| 203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) | 203 | #define S5PC100_CLKDIV4_AUDIO2_SHIFT (20) |
| 204 | 204 | ||
| 205 | |||
| 206 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ | 205 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ |
| 207 | #define S5PC100_CLKGATE_D00_INTC (1<<0) | 206 | #define S5PC100_CLKGATE_D00_INTC (1<<0) |
| 208 | #define S5PC100_CLKGATE_D00_TZIC (1<<1) | 207 | #define S5PC100_CLKGATE_D00_TZIC (1<<1) |
| @@ -295,8 +294,8 @@ | |||
| 295 | #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) | 294 | #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) |
| 296 | 295 | ||
| 297 | /* Special Clock Gate 0 Registers */ | 296 | /* Special Clock Gate 0 Registers */ |
| 298 | #define S5PC1XX_CLKGATE_SCLK0_HPM (1<<0) | 297 | #define S5PC100_CLKGATE_SCLK0_HPM (1<<0) |
| 299 | #define S5PC1XX_CLKGATE_SCLK0_PWI (1<<1) | 298 | #define S5PC100_CLKGATE_SCLK0_PWI (1<<1) |
| 300 | #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) | 299 | #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) |
| 301 | #define S5PC100_CLKGATE_SCLK0_UART (1<<3) | 300 | #define S5PC100_CLKGATE_SCLK0_UART (1<<3) |
| 302 | #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) | 301 | #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) |
| @@ -329,89 +328,28 @@ | |||
| 329 | #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) | 328 | #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) |
| 330 | #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) | 329 | #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) |
| 331 | 330 | ||
| 332 | /* register for power management */ | 331 | #define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000) |
| 333 | #define S5PC100_PWR_CFG S5PC1XX_CLKREG(0x8000) | 332 | #define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008) |
| 334 | #define S5PC100_EINT_WAKEUP_MASK S5PC1XX_CLKREG(0x8004) | 333 | #define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100) |
| 335 | #define S5PC100_NORMAL_CFG S5PC1XX_CLKREG(0x8010) | 334 | #define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104) |
| 336 | #define S5PC100_STOP_CFG S5PC1XX_CLKREG(0x8014) | 335 | #define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200) |
| 337 | #define S5PC100_SLEEP_CFG S5PC1XX_CLKREG(0x8018) | 336 | #define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300) |
| 338 | #define S5PC100_STOP_MEM_CFG S5PC1XX_CLKREG(0x801C) | 337 | #define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304) |
| 339 | #define S5PC100_OSC_FREQ S5PC1XX_CLKREG(0x8100) | 338 | #define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308) |
| 340 | #define S5PC100_OSC_STABLE S5PC1XX_CLKREG(0x8104) | 339 | #define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400) |
| 341 | #define S5PC100_PWR_STABLE S5PC1XX_CLKREG(0x8108) | 340 | #define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414) |
| 342 | #define S5PC100_MTC_STABLE S5PC1XX_CLKREG(0x8110) | 341 | #define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420) |
| 343 | #define S5PC100_CLAMP_STABLE S5PC1XX_CLKREG(0x8114) | 342 | |
| 344 | #define S5PC100_OTHERS S5PC1XX_CLKREG(0x8200) | 343 | #define S5PC100_SWRESET_RESETVAL 0xc100 |
| 345 | #define S5PC100_RST_STAT S5PC1XX_CLKREG(0x8300) | ||
| 346 | #define S5PC100_WAKEUP_STAT S5PC1XX_CLKREG(0x8304) | ||
| 347 | #define S5PC100_BLK_PWR_STAT S5PC1XX_CLKREG(0x8308) | ||
| 348 | #define S5PC100_INFORM0 S5PC1XX_CLKREG(0x8400) | ||
| 349 | #define S5PC100_INFORM1 S5PC1XX_CLKREG(0x8404) | ||
| 350 | #define S5PC100_INFORM2 S5PC1XX_CLKREG(0x8408) | ||
| 351 | #define S5PC100_INFORM3 S5PC1XX_CLKREG(0x840C) | ||
| 352 | #define S5PC100_INFORM4 S5PC1XX_CLKREG(0x8410) | ||
| 353 | #define S5PC100_INFORM5 S5PC1XX_CLKREG(0x8414) | ||
| 354 | #define S5PC100_INFORM6 S5PC1XX_CLKREG(0x8418) | ||
| 355 | #define S5PC100_INFORM7 S5PC1XX_CLKREG(0x841C) | ||
| 356 | #define S5PC100_DCGIDX_MAP0 S5PC1XX_CLKREG(0x8500) | ||
| 357 | #define S5PC100_DCGIDX_MAP1 S5PC1XX_CLKREG(0x8504) | ||
| 358 | #define S5PC100_DCGIDX_MAP2 S5PC1XX_CLKREG(0x8508) | ||
| 359 | #define S5PC100_DCGPERF_MAP0 S5PC1XX_CLKREG(0x850C) | ||
| 360 | #define S5PC100_DCGPERF_MAP1 S5PC1XX_CLKREG(0x8510) | ||
| 361 | #define S5PC100_DVCIDX_MAP S5PC1XX_CLKREG(0x8514) | ||
| 362 | #define S5PC100_FREQ_CPU S5PC1XX_CLKREG(0x8518) | ||
| 363 | #define S5PC100_FREQ_DPM S5PC1XX_CLKREG(0x851C) | ||
| 364 | #define S5PC100_DVSEMCLK_EN S5PC1XX_CLKREG(0x8520) | ||
| 365 | #define S5PC100_APLL_CON_L8 S5PC1XX_CLKREG(0x8600) | ||
| 366 | #define S5PC100_APLL_CON_L7 S5PC1XX_CLKREG(0x8604) | ||
| 367 | #define S5PC100_APLL_CON_L6 S5PC1XX_CLKREG(0x8608) | ||
| 368 | #define S5PC100_APLL_CON_L5 S5PC1XX_CLKREG(0x860C) | ||
| 369 | #define S5PC100_APLL_CON_L4 S5PC1XX_CLKREG(0x8610) | ||
| 370 | #define S5PC100_APLL_CON_L3 S5PC1XX_CLKREG(0x8614) | ||
| 371 | #define S5PC100_APLL_CON_L2 S5PC1XX_CLKREG(0x8618) | ||
| 372 | #define S5PC100_APLL_CON_L1 S5PC1XX_CLKREG(0x861C) | ||
| 373 | #define S5PC100_IEM_CONTROL S5PC1XX_CLKREG(0x8620) | ||
| 374 | #define S5PC100_CLKDIV_IEM_L8 S5PC1XX_CLKREG(0x8700) | ||
| 375 | #define S5PC100_CLKDIV_IEM_L7 S5PC1XX_CLKREG(0x8704) | ||
| 376 | #define S5PC100_CLKDIV_IEM_L6 S5PC1XX_CLKREG(0x8708) | ||
| 377 | #define S5PC100_CLKDIV_IEM_L5 S5PC1XX_CLKREG(0x870C) | ||
| 378 | #define S5PC100_CLKDIV_IEM_L4 S5PC1XX_CLKREG(0x8710) | ||
| 379 | #define S5PC100_CLKDIV_IEM_L3 S5PC1XX_CLKREG(0x8714) | ||
| 380 | #define S5PC100_CLKDIV_IEM_L2 S5PC1XX_CLKREG(0x8718) | ||
| 381 | #define S5PC100_CLKDIV_IEM_L1 S5PC1XX_CLKREG(0x871C) | ||
| 382 | #define S5PC100_IEM_HPMCLK_DIV S5PC1XX_CLKREG(0x8724) | ||
| 383 | |||
| 384 | #define S5PC100_SWRESET S5PC1XX_CLKREG(0x100000) | ||
| 385 | #define S5PC100_OND_SWRESET S5PC1XX_CLKREG(0x100008) | ||
| 386 | #define S5PC100_GEN_CTRL S5PC1XX_CLKREG(0x100100) | ||
| 387 | #define S5PC100_GEN_STATUS S5PC1XX_CLKREG(0x100104) | ||
| 388 | #define S5PC100_MEM_SYS_CFG S5PC1XX_CLKREG(0x100200) | ||
| 389 | #define S5PC100_CAM_MUX_SEL S5PC1XX_CLKREG(0x100300) | ||
| 390 | #define S5PC100_MIXER_OUT_SEL S5PC1XX_CLKREG(0x100304) | ||
| 391 | #define S5PC100_LPMP_MODE_SEL S5PC1XX_CLKREG(0x100308) | ||
| 392 | #define S5PC100_MIPI_PHY_CON0 S5PC1XX_CLKREG(0x100400) | ||
| 393 | #define S5PC100_MIPI_PHY_CON1 S5PC1XX_CLKREG(0x100414) | ||
| 394 | #define S5PC100_HDMI_PHY_CON0 S5PC1XX_CLKREG(0x100420) | ||
| 395 | |||
| 396 | #define S5PC100_CFG_WFI_CLEAN (~(3<<5)) | ||
| 397 | #define S5PC100_CFG_WFI_IDLE (1<<5) | ||
| 398 | #define S5PC100_CFG_WFI_STOP (2<<5) | ||
| 399 | #define S5PC100_CFG_WFI_SLEEP (3<<5) | ||
| 400 | |||
| 401 | #define S5PC100_OTHER_SYS_INT 24 | 344 | #define S5PC100_OTHER_SYS_INT 24 |
| 402 | #define S5PC100_OTHER_STA_TYPE 23 | 345 | #define S5PC100_OTHER_STA_TYPE 23 |
| 403 | #define STA_TYPE_EXPON 0 | 346 | #define STA_TYPE_EXPON 0 |
| 404 | #define STA_TYPE_SFR 1 | 347 | #define STA_TYPE_SFR 1 |
| 405 | 348 | ||
| 406 | #define S5PC100_PWR_STA_EXP_SCALE 0 | ||
| 407 | #define S5PC100_PWR_STA_CNT 4 | ||
| 408 | |||
| 409 | #define S5PC100_PWR_STABLE_COUNT 85500 | ||
| 410 | |||
| 411 | #define S5PC100_SLEEP_CFG_OSC_EN 0 | 349 | #define S5PC100_SLEEP_CFG_OSC_EN 0 |
| 412 | 350 | ||
| 413 | /* OTHERS Resgister */ | 351 | /* OTHERS Resgister */ |
| 414 | #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) | 352 | #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) |
| 415 | #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) | 353 | #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) |
| 416 | 354 | ||
| 417 | /* MIPI D-PHY Control Register 0 */ | 355 | /* MIPI D-PHY Control Register 0 */ |
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h new file mode 100644 index 000000000000..43c7bc8bf784 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX - GPIO register definitions | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H | ||
| 10 | #define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ | ||
| 11 | |||
| 12 | #include <mach/map.h> | ||
| 13 | |||
| 14 | /* S5PC100 */ | ||
| 15 | #define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO | ||
| 16 | #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) | ||
| 17 | #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) | ||
| 18 | #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) | ||
| 19 | #define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060) | ||
| 20 | #define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080) | ||
| 21 | #define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0) | ||
| 22 | #define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0) | ||
| 23 | #define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0) | ||
| 24 | #define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100) | ||
| 25 | #define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120) | ||
| 26 | #define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140) | ||
| 27 | #define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160) | ||
| 28 | #define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180) | ||
| 29 | #define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0) | ||
| 30 | #define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0) | ||
| 31 | #define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00) | ||
| 32 | #define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20) | ||
| 33 | #define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40) | ||
| 34 | #define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60) | ||
| 35 | #define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0) | ||
| 36 | #define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200) | ||
| 37 | #define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220) | ||
| 38 | #define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240) | ||
| 39 | #define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260) | ||
| 40 | #define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280) | ||
| 41 | #define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0) | ||
| 42 | #define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0) | ||
| 43 | #define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0) | ||
| 44 | #define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300) | ||
| 45 | #define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320) | ||
| 46 | #define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340) | ||
| 47 | #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) | ||
| 48 | #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) | ||
| 49 | #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) | ||
| 50 | #define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00) | ||
| 51 | |||
| 52 | #define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) | ||
| 53 | #define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) | ||
| 54 | |||
| 55 | /* PDNEN */ | ||
| 56 | #define S5PC100_PDNEN_CFG_PDNEN (1 << 1) | ||
| 57 | #define S5PC100_PDNEN_CFG_AUTO (0 << 1) | ||
| 58 | #define S5PC100_PDNEN_POWERDOWN (1 << 0) | ||
| 59 | #define S5PC100_PDNEN_NORMAL (0 << 0) | ||
| 60 | |||
| 61 | /* Common part */ | ||
| 62 | /* External interrupt base is same at both s5pc100 and s5pc110 */ | ||
| 63 | #define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE) | ||
| 64 | |||
| 65 | #define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
| 66 | #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
| 67 | #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
| 68 | |||
| 69 | #endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ | ||
| 70 | |||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h new file mode 100644 index 000000000000..02ffa491b53a --- /dev/null +++ b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Jongse Won <jongse.won@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX clock register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_REGS_PWR | ||
| 14 | #define __ASM_ARM_REGS_PWR __FILE__ | ||
| 15 | |||
| 16 | #define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x)) | ||
| 17 | |||
| 18 | /* s5pc100 (0xE0108000) register for power management */ | ||
| 19 | #define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0) | ||
| 20 | #define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4) | ||
| 21 | #define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10) | ||
| 22 | #define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14) | ||
| 23 | #define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18) | ||
| 24 | #define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C) | ||
| 25 | #define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100) | ||
| 26 | #define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104) | ||
| 27 | #define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108) | ||
| 28 | #define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110) | ||
| 29 | #define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114) | ||
| 30 | #define S5PC100_OTHERS S5PC1XX_PWRREG(0x200) | ||
| 31 | #define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300) | ||
| 32 | #define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304) | ||
| 33 | #define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308) | ||
| 34 | #define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400) | ||
| 35 | #define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404) | ||
| 36 | #define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408) | ||
| 37 | #define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C) | ||
| 38 | #define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410) | ||
| 39 | #define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414) | ||
| 40 | #define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418) | ||
| 41 | #define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C) | ||
| 42 | #define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500) | ||
| 43 | #define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504) | ||
| 44 | #define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508) | ||
| 45 | #define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C) | ||
| 46 | #define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510) | ||
| 47 | #define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514) | ||
| 48 | #define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518) | ||
| 49 | #define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C) | ||
| 50 | #define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520) | ||
| 51 | #define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600) | ||
| 52 | #define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604) | ||
| 53 | #define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608) | ||
| 54 | #define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C) | ||
| 55 | #define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610) | ||
| 56 | #define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614) | ||
| 57 | #define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618) | ||
| 58 | #define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C) | ||
| 59 | #define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620) | ||
| 60 | #define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700) | ||
| 61 | #define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704) | ||
| 62 | #define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708) | ||
| 63 | #define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C) | ||
| 64 | #define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710) | ||
| 65 | #define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714) | ||
| 66 | #define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718) | ||
| 67 | #define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C) | ||
| 68 | #define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724) | ||
| 69 | |||
| 70 | /* PWR_CFG */ | ||
| 71 | #define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31) | ||
| 72 | #define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5) | ||
| 73 | #define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5) | ||
| 74 | #define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5) | ||
| 75 | #define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5) | ||
| 76 | #define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5) | ||
| 77 | |||
| 78 | /* SLEEP_CFG */ | ||
| 79 | #define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0) | ||
| 80 | |||
| 81 | /* OTHERS */ | ||
| 82 | #define S5PC100_PMU_INT_DISABLE (1 << 24) | ||
| 83 | |||
| 84 | #endif /* __ASM_ARM_REGS_PWR */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h index 45e275131665..2531f34a56f3 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h +++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h | |||
| @@ -35,10 +35,9 @@ extern struct clk clk_hpll; | |||
| 35 | extern struct clk clk_hd0; | 35 | extern struct clk clk_hd0; |
| 36 | extern struct clk clk_pd0; | 36 | extern struct clk clk_pd0; |
| 37 | extern struct clk clk_54m; | 37 | extern struct clk clk_54m; |
| 38 | extern struct clk clk_dout_mpll2; | ||
| 39 | extern void s5pc1xx_register_clocks(void); | 38 | extern void s5pc1xx_register_clocks(void); |
| 40 | extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable); | 39 | extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable); |
| 41 | extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable); | 40 | extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable); |
| 42 | 41 | ||
| 43 | /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ | 42 | /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ |
| 44 | extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; | 43 | extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; |
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c new file mode 100644 index 000000000000..373122f57d56 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/irq-eint.c | |||
| @@ -0,0 +1,281 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-s5pc1xx/irq-eint.c | ||
| 3 | * | ||
| 4 | * Copyright 2009 Samsung Electronics Co. | ||
| 5 | * Byungho Min <bhmin@samsung.com> | ||
| 6 | * Kyungin Park <kyungmin.park@samsung.com> | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/irq-eint.c | ||
| 9 | * | ||
| 10 | * S5PC1XX - Interrupt handling for IRQ_EINT(x) | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <linux/sysdev.h> | ||
| 22 | #include <linux/pm.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | |||
| 25 | #include <asm/hardware/vic.h> | ||
| 26 | |||
| 27 | #include <mach/map.h> | ||
| 28 | |||
| 29 | #include <plat/gpio-cfg.h> | ||
| 30 | #include <plat/gpio-ext.h> | ||
| 31 | #include <plat/pm.h> | ||
| 32 | #include <plat/regs-gpio.h> | ||
| 33 | #include <plat/regs-irqtype.h> | ||
| 34 | |||
| 35 | /* | ||
| 36 | * bank is a group of external interrupt | ||
| 37 | * bank0 means EINT0 ... EINT7 | ||
| 38 | * bank1 means EINT8 ... EINT15 | ||
| 39 | * bank2 means EINT16 ... EINT23 | ||
| 40 | * bank3 means EINT24 ... EINT31 | ||
| 41 | */ | ||
| 42 | |||
| 43 | static inline int s3c_get_eint(unsigned int irq) | ||
| 44 | { | ||
| 45 | int real; | ||
| 46 | |||
| 47 | if (irq < IRQ_EINT16_31) | ||
| 48 | real = (irq - IRQ_EINT0); | ||
| 49 | else | ||
| 50 | real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0; | ||
| 51 | |||
| 52 | return real; | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline int s3c_get_bank(unsigned int irq) | ||
| 56 | { | ||
| 57 | return s3c_get_eint(irq) >> 3; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline int s3c_eint_to_bit(unsigned int irq) | ||
| 61 | { | ||
| 62 | int real, bit; | ||
| 63 | |||
| 64 | real = s3c_get_eint(irq); | ||
| 65 | bit = 1 << (real & (8 - 1)); | ||
| 66 | |||
| 67 | return bit; | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline void s3c_irq_eint_mask(unsigned int irq) | ||
| 71 | { | ||
| 72 | u32 mask; | ||
| 73 | u32 bank = s3c_get_bank(irq); | ||
| 74 | |||
| 75 | mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 76 | mask |= s3c_eint_to_bit(irq); | ||
| 77 | __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void s3c_irq_eint_unmask(unsigned int irq) | ||
| 81 | { | ||
| 82 | u32 mask; | ||
| 83 | u32 bank = s3c_get_bank(irq); | ||
| 84 | |||
| 85 | mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 86 | mask &= ~(s3c_eint_to_bit(irq)); | ||
| 87 | __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void s3c_irq_eint_ack(unsigned int irq) | ||
| 91 | { | ||
| 92 | u32 bank = s3c_get_bank(irq); | ||
| 93 | |||
| 94 | __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank)); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void s3c_irq_eint_maskack(unsigned int irq) | ||
| 98 | { | ||
| 99 | /* compiler should in-line these */ | ||
| 100 | s3c_irq_eint_mask(irq); | ||
| 101 | s3c_irq_eint_ack(irq); | ||
| 102 | } | ||
| 103 | |||
| 104 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | ||
| 105 | { | ||
| 106 | u32 bank = s3c_get_bank(irq); | ||
| 107 | int real = s3c_get_eint(irq); | ||
| 108 | int gpio, shift, sfn; | ||
| 109 | u32 ctrl, con = 0; | ||
| 110 | |||
| 111 | switch (type) { | ||
| 112 | case IRQ_TYPE_NONE: | ||
| 113 | printk(KERN_WARNING "No edge setting!\n"); | ||
| 114 | break; | ||
| 115 | |||
| 116 | case IRQ_TYPE_EDGE_RISING: | ||
| 117 | con = S5PC1XX_WKUP_INT_RISEEDGE; | ||
| 118 | break; | ||
| 119 | |||
| 120 | case IRQ_TYPE_EDGE_FALLING: | ||
| 121 | con = S5PC1XX_WKUP_INT_FALLEDGE; | ||
| 122 | break; | ||
| 123 | |||
| 124 | case IRQ_TYPE_EDGE_BOTH: | ||
| 125 | con = S5PC1XX_WKUP_INT_BOTHEDGE; | ||
| 126 | break; | ||
| 127 | |||
| 128 | case IRQ_TYPE_LEVEL_LOW: | ||
| 129 | con = S5PC1XX_WKUP_INT_LOWLEV; | ||
| 130 | break; | ||
| 131 | |||
| 132 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 133 | con = S5PC1XX_WKUP_INT_HILEV; | ||
| 134 | break; | ||
| 135 | |||
| 136 | default: | ||
| 137 | printk(KERN_ERR "No such irq type %d", type); | ||
| 138 | return -EINVAL; | ||
| 139 | } | ||
| 140 | |||
| 141 | gpio = real & (8 - 1); | ||
| 142 | shift = gpio << 2; | ||
| 143 | |||
| 144 | ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank)); | ||
| 145 | ctrl &= ~(0x7 << shift); | ||
| 146 | ctrl |= con << shift; | ||
| 147 | __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank)); | ||
| 148 | |||
| 149 | switch (real) { | ||
| 150 | case 0 ... 7: | ||
| 151 | gpio = S5PC100_GPH0(gpio); | ||
| 152 | break; | ||
| 153 | case 8 ... 15: | ||
| 154 | gpio = S5PC100_GPH1(gpio); | ||
| 155 | break; | ||
| 156 | case 16 ... 23: | ||
| 157 | gpio = S5PC100_GPH2(gpio); | ||
| 158 | break; | ||
| 159 | case 24 ... 31: | ||
| 160 | gpio = S5PC100_GPH3(gpio); | ||
| 161 | break; | ||
| 162 | default: | ||
| 163 | return -EINVAL; | ||
| 164 | } | ||
| 165 | |||
| 166 | sfn = S3C_GPIO_SFN(0x2); | ||
| 167 | s3c_gpio_cfgpin(gpio, sfn); | ||
| 168 | |||
| 169 | return 0; | ||
| 170 | } | ||
| 171 | |||
| 172 | static struct irq_chip s3c_irq_eint = { | ||
| 173 | .name = "EINT", | ||
| 174 | .mask = s3c_irq_eint_mask, | ||
| 175 | .unmask = s3c_irq_eint_unmask, | ||
| 176 | .mask_ack = s3c_irq_eint_maskack, | ||
| 177 | .ack = s3c_irq_eint_ack, | ||
| 178 | .set_type = s3c_irq_eint_set_type, | ||
| 179 | .set_wake = s3c_irqext_wake, | ||
| 180 | }; | ||
| 181 | |||
| 182 | /* s3c_irq_demux_eint | ||
| 183 | * | ||
| 184 | * This function demuxes the IRQ from external interrupts, | ||
| 185 | * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into | ||
| 186 | * the specific handlers s3c_irq_demux_eintX_Y. | ||
| 187 | */ | ||
| 188 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) | ||
| 189 | { | ||
| 190 | u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3))); | ||
| 191 | u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3))); | ||
| 192 | unsigned int irq; | ||
| 193 | |||
| 194 | status &= ~mask; | ||
| 195 | status &= (1 << (end - start + 1)) - 1; | ||
| 196 | |||
| 197 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | ||
| 198 | if (status & 1) | ||
| 199 | generic_handle_irq(irq); | ||
| 200 | |||
| 201 | status >>= 1; | ||
| 202 | } | ||
| 203 | } | ||
| 204 | |||
| 205 | static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | ||
| 206 | { | ||
| 207 | s3c_irq_demux_eint(16, 23); | ||
| 208 | s3c_irq_demux_eint(24, 31); | ||
| 209 | } | ||
| 210 | |||
| 211 | /* | ||
| 212 | * Handle EINT0 ... EINT15 at VIC directly | ||
| 213 | */ | ||
| 214 | static void s3c_irq_vic_eint_mask(unsigned int irq) | ||
| 215 | { | ||
| 216 | void __iomem *base = get_irq_chip_data(irq); | ||
| 217 | unsigned int real; | ||
| 218 | |||
| 219 | s3c_irq_eint_mask(irq); | ||
| 220 | real = s3c_get_eint(irq); | ||
| 221 | writel(1 << real, base + VIC_INT_ENABLE_CLEAR); | ||
| 222 | } | ||
| 223 | |||
| 224 | static void s3c_irq_vic_eint_unmask(unsigned int irq) | ||
| 225 | { | ||
| 226 | void __iomem *base = get_irq_chip_data(irq); | ||
| 227 | unsigned int real; | ||
| 228 | |||
| 229 | s3c_irq_eint_unmask(irq); | ||
| 230 | real = s3c_get_eint(irq); | ||
| 231 | writel(1 << real, base + VIC_INT_ENABLE); | ||
| 232 | } | ||
| 233 | |||
| 234 | static inline void s3c_irq_vic_eint_ack(unsigned int irq) | ||
| 235 | { | ||
| 236 | u32 bit; | ||
| 237 | u32 bank = s3c_get_bank(irq); | ||
| 238 | |||
| 239 | bit = s3c_eint_to_bit(irq); | ||
| 240 | __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank)); | ||
| 241 | } | ||
| 242 | |||
| 243 | static void s3c_irq_vic_eint_maskack(unsigned int irq) | ||
| 244 | { | ||
| 245 | /* compiler should in-line these */ | ||
| 246 | s3c_irq_vic_eint_mask(irq); | ||
| 247 | s3c_irq_vic_eint_ack(irq); | ||
| 248 | } | ||
| 249 | |||
| 250 | static struct irq_chip s3c_irq_vic_eint = { | ||
| 251 | .name = "EINT", | ||
| 252 | .mask = s3c_irq_vic_eint_mask, | ||
| 253 | .unmask = s3c_irq_vic_eint_unmask, | ||
| 254 | .mask_ack = s3c_irq_vic_eint_maskack, | ||
| 255 | .ack = s3c_irq_vic_eint_ack, | ||
| 256 | .set_type = s3c_irq_eint_set_type, | ||
| 257 | .set_wake = s3c_irqext_wake, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static int __init s5pc1xx_init_irq_eint(void) | ||
| 261 | { | ||
| 262 | int irq; | ||
| 263 | |||
| 264 | for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) { | ||
| 265 | set_irq_chip(irq, &s3c_irq_vic_eint); | ||
| 266 | set_irq_handler(irq, handle_level_irq); | ||
| 267 | set_irq_flags(irq, IRQF_VALID); | ||
| 268 | } | ||
| 269 | |||
| 270 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | ||
| 271 | set_irq_chip(irq, &s3c_irq_eint); | ||
| 272 | set_irq_handler(irq, handle_level_irq); | ||
| 273 | set_irq_flags(irq, IRQF_VALID); | ||
| 274 | } | ||
| 275 | |||
| 276 | set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31); | ||
| 277 | |||
| 278 | return 0; | ||
| 279 | } | ||
| 280 | |||
| 281 | arch_initcall(s5pc1xx_init_irq_eint); | ||
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/plat-s5pc1xx/irq-gpio.c new file mode 100644 index 000000000000..fecca7a679b0 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/irq-gpio.c | |||
| @@ -0,0 +1,266 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-s5pc1xx/irq-gpio.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Samsung Electronics | ||
| 5 | * | ||
| 6 | * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | |||
| 19 | #include <mach/map.h> | ||
| 20 | #include <plat/gpio-cfg.h> | ||
| 21 | |||
| 22 | #define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) | ||
| 23 | |||
| 24 | #define CON_OFFSET 0x700 | ||
| 25 | #define MASK_OFFSET 0x900 | ||
| 26 | #define PEND_OFFSET 0xA00 | ||
| 27 | #define CON_OFFSET_2 0xE00 | ||
| 28 | #define MASK_OFFSET_2 0xF00 | ||
| 29 | #define PEND_OFFSET_2 0xF40 | ||
| 30 | |||
| 31 | #define GPIOINT_LEVEL_LOW 0x0 | ||
| 32 | #define GPIOINT_LEVEL_HIGH 0x1 | ||
| 33 | #define GPIOINT_EDGE_FALLING 0x2 | ||
| 34 | #define GPIOINT_EDGE_RISING 0x3 | ||
| 35 | #define GPIOINT_EDGE_BOTH 0x4 | ||
| 36 | |||
| 37 | static int group_to_con_offset(int group) | ||
| 38 | { | ||
| 39 | return group << 2; | ||
| 40 | } | ||
| 41 | |||
| 42 | static int group_to_mask_offset(int group) | ||
| 43 | { | ||
| 44 | return group << 2; | ||
| 45 | } | ||
| 46 | |||
| 47 | static int group_to_pend_offset(int group) | ||
| 48 | { | ||
| 49 | return group << 2; | ||
| 50 | } | ||
| 51 | |||
| 52 | static int s5pc1xx_get_start(unsigned int group) | ||
| 53 | { | ||
| 54 | switch (group) { | ||
| 55 | case 0: return S5PC100_GPIO_A0_START; | ||
| 56 | case 1: return S5PC100_GPIO_A1_START; | ||
| 57 | case 2: return S5PC100_GPIO_B_START; | ||
| 58 | case 3: return S5PC100_GPIO_C_START; | ||
| 59 | case 4: return S5PC100_GPIO_D_START; | ||
| 60 | case 5: return S5PC100_GPIO_E0_START; | ||
| 61 | case 6: return S5PC100_GPIO_E1_START; | ||
| 62 | case 7: return S5PC100_GPIO_F0_START; | ||
| 63 | case 8: return S5PC100_GPIO_F1_START; | ||
| 64 | case 9: return S5PC100_GPIO_F2_START; | ||
| 65 | case 10: return S5PC100_GPIO_F3_START; | ||
| 66 | case 11: return S5PC100_GPIO_G0_START; | ||
| 67 | case 12: return S5PC100_GPIO_G1_START; | ||
| 68 | case 13: return S5PC100_GPIO_G2_START; | ||
| 69 | case 14: return S5PC100_GPIO_G3_START; | ||
| 70 | case 15: return S5PC100_GPIO_I_START; | ||
| 71 | case 16: return S5PC100_GPIO_J0_START; | ||
| 72 | case 17: return S5PC100_GPIO_J1_START; | ||
| 73 | case 18: return S5PC100_GPIO_J2_START; | ||
| 74 | case 19: return S5PC100_GPIO_J3_START; | ||
| 75 | case 20: return S5PC100_GPIO_J4_START; | ||
| 76 | default: | ||
| 77 | BUG(); | ||
| 78 | } | ||
| 79 | |||
| 80 | return -EINVAL; | ||
| 81 | } | ||
| 82 | |||
| 83 | static int s5pc1xx_get_group(unsigned int irq) | ||
| 84 | { | ||
| 85 | irq -= S3C_IRQ_GPIO(0); | ||
| 86 | |||
| 87 | switch (irq) { | ||
| 88 | case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1: | ||
| 89 | return 0; | ||
| 90 | case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1: | ||
| 91 | return 1; | ||
| 92 | case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1: | ||
| 93 | return 2; | ||
| 94 | case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1: | ||
| 95 | return 3; | ||
| 96 | case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1: | ||
| 97 | return 4; | ||
| 98 | case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1: | ||
| 99 | return 5; | ||
| 100 | case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1: | ||
| 101 | return 6; | ||
| 102 | case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1: | ||
| 103 | return 7; | ||
| 104 | case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1: | ||
| 105 | return 8; | ||
| 106 | case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1: | ||
| 107 | return 9; | ||
| 108 | case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1: | ||
| 109 | return 10; | ||
| 110 | case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1: | ||
| 111 | return 11; | ||
| 112 | case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1: | ||
| 113 | return 12; | ||
| 114 | case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1: | ||
| 115 | return 13; | ||
| 116 | case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1: | ||
| 117 | return 14; | ||
| 118 | case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1: | ||
| 119 | return 15; | ||
| 120 | case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1: | ||
| 121 | return 16; | ||
| 122 | case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1: | ||
| 123 | return 17; | ||
| 124 | case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1: | ||
| 125 | return 18; | ||
| 126 | case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1: | ||
| 127 | return 19; | ||
| 128 | case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1: | ||
| 129 | return 20; | ||
| 130 | default: | ||
| 131 | BUG(); | ||
| 132 | } | ||
| 133 | |||
| 134 | return -EINVAL; | ||
| 135 | } | ||
| 136 | |||
| 137 | static int s5pc1xx_get_offset(unsigned int irq) | ||
| 138 | { | ||
| 139 | struct gpio_chip *chip = get_irq_data(irq); | ||
| 140 | return irq - S3C_IRQ_GPIO(chip->base); | ||
| 141 | } | ||
| 142 | |||
| 143 | static void s5pc1xx_gpioint_ack(unsigned int irq) | ||
| 144 | { | ||
| 145 | int group, offset, pend_offset; | ||
| 146 | unsigned int value; | ||
| 147 | |||
| 148 | group = s5pc1xx_get_group(irq); | ||
| 149 | offset = s5pc1xx_get_offset(irq); | ||
| 150 | pend_offset = group_to_pend_offset(group); | ||
| 151 | |||
| 152 | value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | ||
| 153 | value |= 1 << offset; | ||
| 154 | __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | ||
| 155 | } | ||
| 156 | |||
| 157 | static void s5pc1xx_gpioint_mask(unsigned int irq) | ||
| 158 | { | ||
| 159 | int group, offset, mask_offset; | ||
| 160 | unsigned int value; | ||
| 161 | |||
| 162 | group = s5pc1xx_get_group(irq); | ||
| 163 | offset = s5pc1xx_get_offset(irq); | ||
| 164 | mask_offset = group_to_mask_offset(group); | ||
| 165 | |||
| 166 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | ||
| 167 | value |= 1 << offset; | ||
| 168 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | ||
| 169 | } | ||
| 170 | |||
| 171 | static void s5pc1xx_gpioint_unmask(unsigned int irq) | ||
| 172 | { | ||
| 173 | int group, offset, mask_offset; | ||
| 174 | unsigned int value; | ||
| 175 | |||
| 176 | group = s5pc1xx_get_group(irq); | ||
| 177 | offset = s5pc1xx_get_offset(irq); | ||
| 178 | mask_offset = group_to_mask_offset(group); | ||
| 179 | |||
| 180 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | ||
| 181 | value &= ~(1 << offset); | ||
| 182 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | ||
| 183 | } | ||
| 184 | |||
| 185 | static void s5pc1xx_gpioint_mask_ack(unsigned int irq) | ||
| 186 | { | ||
| 187 | s5pc1xx_gpioint_mask(irq); | ||
| 188 | s5pc1xx_gpioint_ack(irq); | ||
| 189 | } | ||
| 190 | |||
| 191 | static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) | ||
| 192 | { | ||
| 193 | int group, offset, con_offset; | ||
| 194 | unsigned int value; | ||
| 195 | |||
| 196 | group = s5pc1xx_get_group(irq); | ||
| 197 | offset = s5pc1xx_get_offset(irq); | ||
| 198 | con_offset = group_to_con_offset(group); | ||
| 199 | |||
| 200 | switch (type) { | ||
| 201 | case IRQ_TYPE_NONE: | ||
| 202 | printk(KERN_WARNING "No irq type\n"); | ||
| 203 | return -EINVAL; | ||
| 204 | case IRQ_TYPE_EDGE_RISING: | ||
| 205 | type = GPIOINT_EDGE_RISING; | ||
| 206 | break; | ||
| 207 | case IRQ_TYPE_EDGE_FALLING: | ||
| 208 | type = GPIOINT_EDGE_FALLING; | ||
| 209 | break; | ||
| 210 | case IRQ_TYPE_EDGE_BOTH: | ||
| 211 | type = GPIOINT_EDGE_BOTH; | ||
| 212 | break; | ||
| 213 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 214 | type = GPIOINT_LEVEL_HIGH; | ||
| 215 | break; | ||
| 216 | case IRQ_TYPE_LEVEL_LOW: | ||
| 217 | type = GPIOINT_LEVEL_LOW; | ||
| 218 | break; | ||
| 219 | default: | ||
| 220 | BUG(); | ||
| 221 | } | ||
| 222 | |||
| 223 | |||
| 224 | value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | ||
| 225 | value &= ~(0xf << (offset * 0x4)); | ||
| 226 | value |= (type << (offset * 0x4)); | ||
| 227 | __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | ||
| 228 | |||
| 229 | return 0; | ||
| 230 | } | ||
| 231 | |||
| 232 | struct irq_chip s5pc1xx_gpioint = { | ||
| 233 | .name = "GPIO", | ||
| 234 | .ack = s5pc1xx_gpioint_ack, | ||
| 235 | .mask = s5pc1xx_gpioint_mask, | ||
| 236 | .mask_ack = s5pc1xx_gpioint_mask_ack, | ||
| 237 | .unmask = s5pc1xx_gpioint_unmask, | ||
| 238 | .set_type = s5pc1xx_gpioint_set_type, | ||
| 239 | }; | ||
| 240 | |||
| 241 | void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | ||
| 242 | { | ||
| 243 | int group, offset, pend_offset, mask_offset; | ||
| 244 | int real_irq, group_end; | ||
| 245 | unsigned int pend, mask; | ||
| 246 | |||
| 247 | group_end = 21; | ||
| 248 | |||
| 249 | for (group = 0; group < group_end; group++) { | ||
| 250 | pend_offset = group_to_pend_offset(group); | ||
| 251 | pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | ||
| 252 | if (!pend) | ||
| 253 | continue; | ||
| 254 | |||
| 255 | mask_offset = group_to_mask_offset(group); | ||
| 256 | mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | ||
| 257 | pend &= ~mask; | ||
| 258 | |||
| 259 | for (offset = 0; offset < 8; offset++) { | ||
| 260 | if (pend & (1 << offset)) { | ||
| 261 | real_irq = s5pc1xx_get_start(group) + offset; | ||
| 262 | generic_handle_irq(S3C_IRQ_GPIO(real_irq)); | ||
| 263 | } | ||
| 264 | } | ||
| 265 | } | ||
| 266 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c index 80d6dd942cb8..e44fd04ef333 100644 --- a/arch/arm/plat-s5pc1xx/irq.c +++ b/arch/arm/plat-s5pc1xx/irq.c | |||
| @@ -79,7 +79,7 @@ static void s3c_irq_timer_ack(unsigned int irq) | |||
| 79 | { | 79 | { |
| 80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | 80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); |
| 81 | 81 | ||
| 82 | reg &= 0x1f; | 82 | reg &= 0x1f; /* mask out pending interrupts */ |
| 83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | 83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); |
| 84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | 84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); |
| 85 | } | 85 | } |
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c index 6b24035172fa..b436d44510c8 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c | |||
| @@ -49,6 +49,7 @@ static struct clk clk_ext_xtal_mux = { | |||
| 49 | #define clk_fin_hpll clk_ext_xtal_mux | 49 | #define clk_fin_hpll clk_ext_xtal_mux |
| 50 | 50 | ||
| 51 | #define clk_fout_mpll clk_mpll | 51 | #define clk_fout_mpll clk_mpll |
| 52 | #define clk_vclk_54m clk_54m | ||
| 52 | 53 | ||
| 53 | struct clk_sources { | 54 | struct clk_sources { |
| 54 | unsigned int nr_sources; | 55 | unsigned int nr_sources; |
| @@ -67,746 +68,327 @@ struct clksrc_clk { | |||
| 67 | void __iomem *reg_source; | 68 | void __iomem *reg_source; |
| 68 | }; | 69 | }; |
| 69 | 70 | ||
| 70 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | 71 | /* APLL */ |
| 71 | { | 72 | static struct clk clk_fout_apll = { |
| 72 | clk->rate = rate; | 73 | .name = "fout_apll", |
| 73 | return 1; | ||
| 74 | } | ||
| 75 | |||
| 76 | struct clk clk_27m = { | ||
| 77 | .name = "clk_27m", | ||
| 78 | .id = -1, | 74 | .id = -1, |
| 79 | .rate = 27000000, | 75 | .rate = 27000000, |
| 80 | }; | 76 | }; |
| 81 | 77 | ||
| 82 | static int clk_48m_ctrl(struct clk *clk, int enable) | 78 | static struct clk *clk_src_apll_list[] = { |
| 83 | { | 79 | [0] = &clk_fin_apll, |
| 84 | unsigned long flags; | 80 | [1] = &clk_fout_apll, |
| 85 | u32 val; | 81 | }; |
| 82 | |||
| 83 | static struct clk_sources clk_src_apll = { | ||
| 84 | .sources = clk_src_apll_list, | ||
| 85 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
| 86 | }; | ||
| 86 | 87 | ||
| 87 | /* can't rely on clock lock, this register has other usages */ | 88 | static struct clksrc_clk clk_mout_apll = { |
| 88 | local_irq_save(flags); | 89 | .clk = { |
| 90 | .name = "mout_apll", | ||
| 91 | .id = -1, | ||
| 92 | }, | ||
| 93 | .shift = S5PC100_CLKSRC0_APLL_SHIFT, | ||
| 94 | .mask = S5PC100_CLKSRC0_APLL_MASK, | ||
| 95 | .sources = &clk_src_apll, | ||
| 96 | .reg_source = S5PC100_CLKSRC0, | ||
| 97 | }; | ||
| 89 | 98 | ||
| 90 | val = __raw_readl(S5PC1XX_CLK_SRC1); | 99 | static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) |
| 91 | if (enable) | 100 | { |
| 92 | val |= S5PC100_CLKSRC1_CLK48M_MASK; | 101 | unsigned long rate = clk_get_rate(clk->parent); |
| 93 | else | 102 | unsigned int ratio; |
| 94 | val &= ~S5PC100_CLKSRC1_CLK48M_MASK; | ||
| 95 | 103 | ||
| 96 | __raw_writel(val, S5PC1XX_CLK_SRC1); | 104 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK; |
| 97 | local_irq_restore(flags); | 105 | ratio >>= S5PC100_CLKDIV0_APLL_SHIFT; |
| 98 | 106 | ||
| 99 | return 0; | 107 | return rate / (ratio + 1); |
| 100 | } | 108 | } |
| 101 | 109 | ||
| 102 | struct clk clk_48m = { | 110 | static struct clk clk_dout_apll = { |
| 103 | .name = "clk_48m", | 111 | .name = "dout_apll", |
| 104 | .id = -1, | 112 | .id = -1, |
| 105 | .rate = 48000000, | 113 | .parent = &clk_mout_apll.clk, |
| 106 | .enable = clk_48m_ctrl, | 114 | .get_rate = s5pc100_clk_dout_apll_get_rate, |
| 107 | }; | 115 | }; |
| 108 | 116 | ||
| 109 | struct clk clk_54m = { | 117 | static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) |
| 110 | .name = "clk_54m", | 118 | { |
| 111 | .id = -1, | 119 | unsigned long rate = clk_get_rate(clk->parent); |
| 112 | .rate = 54000000, | 120 | unsigned int ratio; |
| 113 | }; | ||
| 114 | |||
| 115 | struct clk clk_hpll = { | ||
| 116 | .name = "hpll", | ||
| 117 | .id = -1, | ||
| 118 | }; | ||
| 119 | 121 | ||
| 120 | struct clk clk_hd0 = { | 122 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK; |
| 121 | .name = "hclkd0", | 123 | ratio >>= S5PC100_CLKDIV0_ARM_SHIFT; |
| 122 | .id = -1, | ||
| 123 | .rate = 0, | ||
| 124 | .parent = NULL, | ||
| 125 | .ctrlbit = 0, | ||
| 126 | .set_rate = clk_default_setrate, | ||
| 127 | }; | ||
| 128 | 124 | ||
| 129 | struct clk clk_pd0 = { | 125 | return rate / (ratio + 1); |
| 130 | .name = "pclkd0", | 126 | } |
| 131 | .id = -1, | ||
| 132 | .rate = 0, | ||
| 133 | .parent = NULL, | ||
| 134 | .ctrlbit = 0, | ||
| 135 | .set_rate = clk_default_setrate, | ||
| 136 | }; | ||
| 137 | 127 | ||
| 138 | static int s5pc1xx_clk_gate(void __iomem *reg, | 128 | static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk, |
| 139 | struct clk *clk, | 129 | unsigned long rate) |
| 140 | int enable) | ||
| 141 | { | 130 | { |
| 142 | unsigned int ctrlbit = clk->ctrlbit; | 131 | unsigned long parent = clk_get_rate(clk->parent); |
| 143 | u32 con; | 132 | u32 div; |
| 144 | 133 | ||
| 145 | con = __raw_readl(reg); | 134 | if (parent < rate) |
| 135 | return rate; | ||
| 146 | 136 | ||
| 147 | if (enable) | 137 | div = (parent / rate) - 1; |
| 148 | con |= ctrlbit; | 138 | if (div > S5PC100_CLKDIV0_ARM_MASK) |
| 149 | else | 139 | div = S5PC100_CLKDIV0_ARM_MASK; |
| 150 | con &= ~ctrlbit; | ||
| 151 | 140 | ||
| 152 | __raw_writel(con, reg); | 141 | return parent / (div + 1); |
| 153 | return 0; | ||
| 154 | } | 142 | } |
| 155 | 143 | ||
| 156 | static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable) | 144 | static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate) |
| 157 | { | 145 | { |
| 158 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); | 146 | unsigned long parent = clk_get_rate(clk->parent); |
| 159 | } | 147 | u32 div; |
| 148 | u32 val; | ||
| 160 | 149 | ||
| 161 | static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable) | 150 | if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1)) |
| 162 | { | 151 | return -EINVAL; |
| 163 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); | ||
| 164 | } | ||
| 165 | 152 | ||
| 166 | static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable) | 153 | rate = clk_round_rate(clk, rate); |
| 167 | { | 154 | div = clk_get_rate(clk->parent) / rate; |
| 168 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); | ||
| 169 | } | ||
| 170 | 155 | ||
| 171 | static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable) | 156 | val = __raw_readl(S5PC100_CLKDIV0); |
| 172 | { | 157 | val &= S5PC100_CLKDIV0_ARM_MASK; |
| 173 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); | 158 | val |= (div - 1); |
| 174 | } | 159 | __raw_writel(val, S5PC100_CLKDIV0); |
| 175 | 160 | ||
| 176 | static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable) | 161 | return 0; |
| 177 | { | ||
| 178 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); | ||
| 179 | } | 162 | } |
| 180 | 163 | ||
| 181 | static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable) | 164 | static struct clk clk_arm = { |
| 182 | { | 165 | .name = "armclk", |
| 183 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); | 166 | .id = -1, |
| 184 | } | 167 | .parent = &clk_dout_apll, |
| 168 | .get_rate = s5pc100_clk_arm_get_rate, | ||
| 169 | .set_rate = s5pc100_clk_arm_set_rate, | ||
| 170 | .round_rate = s5pc100_clk_arm_round_rate, | ||
| 171 | }; | ||
| 185 | 172 | ||
| 186 | static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable) | 173 | static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) |
| 187 | { | 174 | { |
| 188 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); | 175 | unsigned long rate = clk_get_rate(clk->parent); |
| 189 | } | 176 | unsigned int ratio; |
| 190 | 177 | ||
| 191 | static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable) | 178 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK; |
| 192 | { | 179 | ratio >>= S5PC100_CLKDIV0_D0_SHIFT; |
| 193 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); | ||
| 194 | } | ||
| 195 | 180 | ||
| 196 | static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable) | 181 | return rate / (ratio + 1); |
| 197 | { | ||
| 198 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); | ||
| 199 | } | 182 | } |
| 200 | 183 | ||
| 201 | static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable) | 184 | static struct clk clk_dout_d0_bus = { |
| 202 | { | 185 | .name = "dout_d0_bus", |
| 203 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); | 186 | .id = -1, |
| 204 | } | 187 | .parent = &clk_arm, |
| 188 | .get_rate = s5pc100_clk_dout_d0_bus_get_rate, | ||
| 189 | }; | ||
| 205 | 190 | ||
| 206 | int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable) | 191 | static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) |
| 207 | { | 192 | { |
| 208 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); | 193 | unsigned long rate = clk_get_rate(clk->parent); |
| 194 | unsigned int ratio; | ||
| 195 | |||
| 196 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK; | ||
| 197 | ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT; | ||
| 198 | |||
| 199 | return rate / (ratio + 1); | ||
| 209 | } | 200 | } |
| 210 | 201 | ||
| 211 | int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable) | 202 | static struct clk clk_dout_pclkd0 = { |
| 203 | .name = "dout_pclkd0", | ||
| 204 | .id = -1, | ||
| 205 | .parent = &clk_dout_d0_bus, | ||
| 206 | .get_rate = s5pc100_clk_dout_pclkd0_get_rate, | ||
| 207 | }; | ||
| 208 | |||
| 209 | static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) | ||
| 212 | { | 210 | { |
| 213 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); | 211 | unsigned long rate = clk_get_rate(clk->parent); |
| 212 | unsigned int ratio; | ||
| 213 | |||
| 214 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK; | ||
| 215 | ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT; | ||
| 216 | |||
| 217 | return rate / (ratio + 1); | ||
| 214 | } | 218 | } |
| 215 | 219 | ||
| 216 | static struct clk init_clocks_disable[] = { | 220 | static struct clk clk_dout_apll2 = { |
| 217 | { | 221 | .name = "dout_apll2", |
| 218 | .name = "dsi", | 222 | .id = -1, |
| 219 | .id = -1, | 223 | .parent = &clk_mout_apll.clk, |
| 220 | .parent = &clk_p, | 224 | .get_rate = s5pc100_clk_dout_apll2_get_rate, |
| 221 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 222 | .ctrlbit = S5PC100_CLKGATE_D11_DSI, | ||
| 223 | }, { | ||
| 224 | .name = "csi", | ||
| 225 | .id = -1, | ||
| 226 | .parent = &clk_h, | ||
| 227 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 228 | .ctrlbit = S5PC100_CLKGATE_D11_CSI, | ||
| 229 | }, { | ||
| 230 | .name = "ccan0", | ||
| 231 | .id = 0, | ||
| 232 | .parent = &clk_p, | ||
| 233 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 234 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, | ||
| 235 | }, { | ||
| 236 | .name = "ccan1", | ||
| 237 | .id = 1, | ||
| 238 | .parent = &clk_p, | ||
| 239 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 240 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, | ||
| 241 | }, { | ||
| 242 | .name = "keypad", | ||
| 243 | .id = -1, | ||
| 244 | .parent = &clk_p, | ||
| 245 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 246 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
| 247 | }, { | ||
| 248 | .name = "hclkd2", | ||
| 249 | .id = -1, | ||
| 250 | .parent = NULL, | ||
| 251 | .enable = s5pc1xx_clk_d20_ctrl, | ||
| 252 | .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, | ||
| 253 | }, { | ||
| 254 | .name = "iis-d2", | ||
| 255 | .id = -1, | ||
| 256 | .parent = NULL, | ||
| 257 | .enable = s5pc1xx_clk_d20_ctrl, | ||
| 258 | .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, | ||
| 259 | }, { | ||
| 260 | .name = "otg", | ||
| 261 | .id = -1, | ||
| 262 | .parent = &clk_h, | ||
| 263 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 264 | .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, | ||
| 265 | }, | ||
| 266 | }; | 225 | }; |
| 267 | 226 | ||
| 268 | static struct clk init_clocks[] = { | 227 | /* MPLL */ |
| 269 | /* System1 (D0_0) devices */ | 228 | static struct clk *clk_src_mpll_list[] = { |
| 270 | { | 229 | [0] = &clk_fin_mpll, |
| 271 | .name = "intc", | 230 | [1] = &clk_fout_mpll, |
| 272 | .id = -1, | 231 | }; |
| 273 | .parent = &clk_hd0, | ||
| 274 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 275 | .ctrlbit = S5PC100_CLKGATE_D00_INTC, | ||
| 276 | }, { | ||
| 277 | .name = "tzic", | ||
| 278 | .id = -1, | ||
| 279 | .parent = &clk_hd0, | ||
| 280 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 281 | .ctrlbit = S5PC100_CLKGATE_D00_TZIC, | ||
| 282 | }, { | ||
| 283 | .name = "cf-ata", | ||
| 284 | .id = -1, | ||
| 285 | .parent = &clk_hd0, | ||
| 286 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 287 | .ctrlbit = S5PC100_CLKGATE_D00_CFCON, | ||
| 288 | }, { | ||
| 289 | .name = "mdma", | ||
| 290 | .id = -1, | ||
| 291 | .parent = &clk_hd0, | ||
| 292 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 293 | .ctrlbit = S5PC100_CLKGATE_D00_MDMA, | ||
| 294 | }, { | ||
| 295 | .name = "g2d", | ||
| 296 | .id = -1, | ||
| 297 | .parent = &clk_hd0, | ||
| 298 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 299 | .ctrlbit = S5PC100_CLKGATE_D00_G2D, | ||
| 300 | }, { | ||
| 301 | .name = "secss", | ||
| 302 | .id = -1, | ||
| 303 | .parent = &clk_hd0, | ||
| 304 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 305 | .ctrlbit = S5PC100_CLKGATE_D00_SECSS, | ||
| 306 | }, { | ||
| 307 | .name = "cssys", | ||
| 308 | .id = -1, | ||
| 309 | .parent = &clk_hd0, | ||
| 310 | .enable = s5pc1xx_clk_d00_ctrl, | ||
| 311 | .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, | ||
| 312 | }, | ||
| 313 | 232 | ||
| 314 | /* Memory (D0_1) devices */ | 233 | static struct clk_sources clk_src_mpll = { |
| 315 | { | 234 | .sources = clk_src_mpll_list, |
| 316 | .name = "dmc", | 235 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), |
| 317 | .id = -1, | 236 | }; |
| 318 | .parent = &clk_hd0, | ||
| 319 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 320 | .ctrlbit = S5PC100_CLKGATE_D01_DMC, | ||
| 321 | }, { | ||
| 322 | .name = "sromc", | ||
| 323 | .id = -1, | ||
| 324 | .parent = &clk_hd0, | ||
| 325 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 326 | .ctrlbit = S5PC100_CLKGATE_D01_SROMC, | ||
| 327 | }, { | ||
| 328 | .name = "onenand", | ||
| 329 | .id = -1, | ||
| 330 | .parent = &clk_hd0, | ||
| 331 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 332 | .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, | ||
| 333 | }, { | ||
| 334 | .name = "nand", | ||
| 335 | .id = -1, | ||
| 336 | .parent = &clk_hd0, | ||
| 337 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 338 | .ctrlbit = S5PC100_CLKGATE_D01_NFCON, | ||
| 339 | }, { | ||
| 340 | .name = "intmem", | ||
| 341 | .id = -1, | ||
| 342 | .parent = &clk_hd0, | ||
| 343 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 344 | .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, | ||
| 345 | }, { | ||
| 346 | .name = "ebi", | ||
| 347 | .id = -1, | ||
| 348 | .parent = &clk_hd0, | ||
| 349 | .enable = s5pc1xx_clk_d01_ctrl, | ||
| 350 | .ctrlbit = S5PC100_CLKGATE_D01_EBI, | ||
| 351 | }, | ||
| 352 | 237 | ||
| 353 | /* System2 (D0_2) devices */ | 238 | static struct clksrc_clk clk_mout_mpll = { |
| 354 | { | 239 | .clk = { |
| 355 | .name = "seckey", | 240 | .name = "mout_mpll", |
| 356 | .id = -1, | ||
| 357 | .parent = &clk_pd0, | ||
| 358 | .enable = s5pc1xx_clk_d02_ctrl, | ||
| 359 | .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, | ||
| 360 | }, { | ||
| 361 | .name = "sdm", | ||
| 362 | .id = -1, | 241 | .id = -1, |
| 363 | .parent = &clk_hd0, | ||
| 364 | .enable = s5pc1xx_clk_d02_ctrl, | ||
| 365 | .ctrlbit = S5PC100_CLKGATE_D02_SDM, | ||
| 366 | }, | 242 | }, |
| 243 | .shift = S5PC100_CLKSRC0_MPLL_SHIFT, | ||
| 244 | .mask = S5PC100_CLKSRC0_MPLL_MASK, | ||
| 245 | .sources = &clk_src_mpll, | ||
| 246 | .reg_source = S5PC100_CLKSRC0, | ||
| 247 | }; | ||
| 367 | 248 | ||
| 368 | /* File (D1_0) devices */ | 249 | static struct clk *clkset_am_list[] = { |
| 369 | { | 250 | [0] = &clk_mout_mpll.clk, |
| 370 | .name = "pdma0", | 251 | [1] = &clk_dout_apll2, |
| 371 | .id = -1, | 252 | }; |
| 372 | .parent = &clk_h, | ||
| 373 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 374 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, | ||
| 375 | }, { | ||
| 376 | .name = "pdma1", | ||
| 377 | .id = -1, | ||
| 378 | .parent = &clk_h, | ||
| 379 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 380 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, | ||
| 381 | }, { | ||
| 382 | .name = "usb-host", | ||
| 383 | .id = -1, | ||
| 384 | .parent = &clk_h, | ||
| 385 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 386 | .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, | ||
| 387 | }, { | ||
| 388 | .name = "modem", | ||
| 389 | .id = -1, | ||
| 390 | .parent = &clk_h, | ||
| 391 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 392 | .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, | ||
| 393 | }, { | ||
| 394 | .name = "hsmmc", | ||
| 395 | .id = 0, | ||
| 396 | .parent = &clk_h, | ||
| 397 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 398 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, | ||
| 399 | }, { | ||
| 400 | .name = "hsmmc", | ||
| 401 | .id = 1, | ||
| 402 | .parent = &clk_h, | ||
| 403 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 404 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, | ||
| 405 | }, { | ||
| 406 | .name = "hsmmc", | ||
| 407 | .id = 2, | ||
| 408 | .parent = &clk_h, | ||
| 409 | .enable = s5pc1xx_clk_d10_ctrl, | ||
| 410 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, | ||
| 411 | }, | ||
| 412 | 253 | ||
| 413 | /* Multimedia1 (D1_1) devices */ | 254 | static struct clk_sources clk_src_am = { |
| 414 | { | 255 | .sources = clkset_am_list, |
| 415 | .name = "lcd", | 256 | .nr_sources = ARRAY_SIZE(clkset_am_list), |
| 416 | .id = -1, | 257 | }; |
| 417 | .parent = &clk_h, | ||
| 418 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 419 | .ctrlbit = S5PC100_CLKGATE_D11_LCD, | ||
| 420 | }, { | ||
| 421 | .name = "rotator", | ||
| 422 | .id = -1, | ||
| 423 | .parent = &clk_h, | ||
| 424 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 425 | .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, | ||
| 426 | }, { | ||
| 427 | .name = "fimc", | ||
| 428 | .id = 0, | ||
| 429 | .parent = &clk_h, | ||
| 430 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 431 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, | ||
| 432 | }, { | ||
| 433 | .name = "fimc", | ||
| 434 | .id = 1, | ||
| 435 | .parent = &clk_h, | ||
| 436 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 437 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, | ||
| 438 | }, { | ||
| 439 | .name = "fimc", | ||
| 440 | .id = 2, | ||
| 441 | .parent = &clk_h, | ||
| 442 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 443 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, | ||
| 444 | }, { | ||
| 445 | .name = "jpeg", | ||
| 446 | .id = -1, | ||
| 447 | .parent = &clk_h, | ||
| 448 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 449 | .ctrlbit = S5PC100_CLKGATE_D11_JPEG, | ||
| 450 | }, { | ||
| 451 | .name = "g3d", | ||
| 452 | .id = -1, | ||
| 453 | .parent = &clk_h, | ||
| 454 | .enable = s5pc1xx_clk_d11_ctrl, | ||
| 455 | .ctrlbit = S5PC100_CLKGATE_D11_G3D, | ||
| 456 | }, | ||
| 457 | 258 | ||
| 458 | /* Multimedia2 (D1_2) devices */ | 259 | static struct clksrc_clk clk_mout_am = { |
| 459 | { | 260 | .clk = { |
| 460 | .name = "tv", | 261 | .name = "mout_am", |
| 461 | .id = -1, | ||
| 462 | .parent = &clk_h, | ||
| 463 | .enable = s5pc1xx_clk_d12_ctrl, | ||
| 464 | .ctrlbit = S5PC100_CLKGATE_D12_TV, | ||
| 465 | }, { | ||
| 466 | .name = "vp", | ||
| 467 | .id = -1, | ||
| 468 | .parent = &clk_h, | ||
| 469 | .enable = s5pc1xx_clk_d12_ctrl, | ||
| 470 | .ctrlbit = S5PC100_CLKGATE_D12_VP, | ||
| 471 | }, { | ||
| 472 | .name = "mixer", | ||
| 473 | .id = -1, | ||
| 474 | .parent = &clk_h, | ||
| 475 | .enable = s5pc1xx_clk_d12_ctrl, | ||
| 476 | .ctrlbit = S5PC100_CLKGATE_D12_MIXER, | ||
| 477 | }, { | ||
| 478 | .name = "hdmi", | ||
| 479 | .id = -1, | ||
| 480 | .parent = &clk_h, | ||
| 481 | .enable = s5pc1xx_clk_d12_ctrl, | ||
| 482 | .ctrlbit = S5PC100_CLKGATE_D12_HDMI, | ||
| 483 | }, { | ||
| 484 | .name = "mfc", | ||
| 485 | .id = -1, | 262 | .id = -1, |
| 486 | .parent = &clk_h, | ||
| 487 | .enable = s5pc1xx_clk_d12_ctrl, | ||
| 488 | .ctrlbit = S5PC100_CLKGATE_D12_MFC, | ||
| 489 | }, | 263 | }, |
| 264 | .shift = S5PC100_CLKSRC0_AMMUX_SHIFT, | ||
| 265 | .mask = S5PC100_CLKSRC0_AMMUX_MASK, | ||
| 266 | .sources = &clk_src_am, | ||
| 267 | .reg_source = S5PC100_CLKSRC0, | ||
| 268 | }; | ||
| 490 | 269 | ||
| 491 | /* System (D1_3) devices */ | 270 | static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) |
| 492 | { | 271 | { |
| 493 | .name = "chipid", | 272 | unsigned long rate = clk_get_rate(clk->parent); |
| 494 | .id = -1, | 273 | unsigned int ratio; |
| 495 | .parent = &clk_p, | ||
| 496 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 497 | .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, | ||
| 498 | }, { | ||
| 499 | .name = "gpio", | ||
| 500 | .id = -1, | ||
| 501 | .parent = &clk_p, | ||
| 502 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 503 | .ctrlbit = S5PC100_CLKGATE_D13_GPIO, | ||
| 504 | }, { | ||
| 505 | .name = "apc", | ||
| 506 | .id = -1, | ||
| 507 | .parent = &clk_p, | ||
| 508 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 509 | .ctrlbit = S5PC100_CLKGATE_D13_APC, | ||
| 510 | }, { | ||
| 511 | .name = "iec", | ||
| 512 | .id = -1, | ||
| 513 | .parent = &clk_p, | ||
| 514 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 515 | .ctrlbit = S5PC100_CLKGATE_D13_IEC, | ||
| 516 | }, { | ||
| 517 | .name = "timers", | ||
| 518 | .id = -1, | ||
| 519 | .parent = &clk_p, | ||
| 520 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 521 | .ctrlbit = S5PC100_CLKGATE_D13_PWM, | ||
| 522 | }, { | ||
| 523 | .name = "systimer", | ||
| 524 | .id = -1, | ||
| 525 | .parent = &clk_p, | ||
| 526 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 527 | .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, | ||
| 528 | }, { | ||
| 529 | .name = "watchdog", | ||
| 530 | .id = -1, | ||
| 531 | .parent = &clk_p, | ||
| 532 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 533 | .ctrlbit = S5PC100_CLKGATE_D13_WDT, | ||
| 534 | }, { | ||
| 535 | .name = "rtc", | ||
| 536 | .id = -1, | ||
| 537 | .parent = &clk_p, | ||
| 538 | .enable = s5pc1xx_clk_d13_ctrl, | ||
| 539 | .ctrlbit = S5PC100_CLKGATE_D13_RTC, | ||
| 540 | }, | ||
| 541 | 274 | ||
| 542 | /* Connectivity (D1_4) devices */ | 275 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); |
| 543 | { | ||
| 544 | .name = "uart", | ||
| 545 | .id = 0, | ||
| 546 | .parent = &clk_p, | ||
| 547 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 548 | .ctrlbit = S5PC100_CLKGATE_D14_UART0, | ||
| 549 | }, { | ||
| 550 | .name = "uart", | ||
| 551 | .id = 1, | ||
| 552 | .parent = &clk_p, | ||
| 553 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 554 | .ctrlbit = S5PC100_CLKGATE_D14_UART1, | ||
| 555 | }, { | ||
| 556 | .name = "uart", | ||
| 557 | .id = 2, | ||
| 558 | .parent = &clk_p, | ||
| 559 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 560 | .ctrlbit = S5PC100_CLKGATE_D14_UART2, | ||
| 561 | }, { | ||
| 562 | .name = "uart", | ||
| 563 | .id = 3, | ||
| 564 | .parent = &clk_p, | ||
| 565 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 566 | .ctrlbit = S5PC100_CLKGATE_D14_UART3, | ||
| 567 | }, { | ||
| 568 | .name = "i2c", | ||
| 569 | .id = -1, | ||
| 570 | .parent = &clk_p, | ||
| 571 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 572 | .ctrlbit = S5PC100_CLKGATE_D14_IIC, | ||
| 573 | }, { | ||
| 574 | .name = "hdmi-i2c", | ||
| 575 | .id = -1, | ||
| 576 | .parent = &clk_p, | ||
| 577 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 578 | .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, | ||
| 579 | }, { | ||
| 580 | .name = "spi", | ||
| 581 | .id = 0, | ||
| 582 | .parent = &clk_p, | ||
| 583 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 584 | .ctrlbit = S5PC100_CLKGATE_D14_SPI0, | ||
| 585 | }, { | ||
| 586 | .name = "spi", | ||
| 587 | .id = 1, | ||
| 588 | .parent = &clk_p, | ||
| 589 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 590 | .ctrlbit = S5PC100_CLKGATE_D14_SPI1, | ||
| 591 | }, { | ||
| 592 | .name = "spi", | ||
| 593 | .id = 2, | ||
| 594 | .parent = &clk_p, | ||
| 595 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 596 | .ctrlbit = S5PC100_CLKGATE_D14_SPI2, | ||
| 597 | }, { | ||
| 598 | .name = "irda", | ||
| 599 | .id = -1, | ||
| 600 | .parent = &clk_p, | ||
| 601 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 602 | .ctrlbit = S5PC100_CLKGATE_D14_IRDA, | ||
| 603 | }, { | ||
| 604 | .name = "hsitx", | ||
| 605 | .id = -1, | ||
| 606 | .parent = &clk_p, | ||
| 607 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 608 | .ctrlbit = S5PC100_CLKGATE_D14_HSITX, | ||
| 609 | }, { | ||
| 610 | .name = "hsirx", | ||
| 611 | .id = -1, | ||
| 612 | .parent = &clk_p, | ||
| 613 | .enable = s5pc1xx_clk_d14_ctrl, | ||
| 614 | .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, | ||
| 615 | }, | ||
| 616 | 276 | ||
| 617 | /* Audio (D1_5) devices */ | 277 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK; |
| 618 | { | 278 | ratio >>= S5PC100_CLKDIV1_D1_SHIFT; |
| 619 | .name = "iis", | ||
| 620 | .id = 0, | ||
| 621 | .parent = &clk_p, | ||
| 622 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 623 | .ctrlbit = S5PC100_CLKGATE_D15_IIS0, | ||
| 624 | }, { | ||
| 625 | .name = "iis", | ||
| 626 | .id = 1, | ||
| 627 | .parent = &clk_p, | ||
| 628 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 629 | .ctrlbit = S5PC100_CLKGATE_D15_IIS1, | ||
| 630 | }, { | ||
| 631 | .name = "iis", | ||
| 632 | .id = 2, | ||
| 633 | .parent = &clk_p, | ||
| 634 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 635 | .ctrlbit = S5PC100_CLKGATE_D15_IIS2, | ||
| 636 | }, { | ||
| 637 | .name = "ac97", | ||
| 638 | .id = -1, | ||
| 639 | .parent = &clk_p, | ||
| 640 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 641 | .ctrlbit = S5PC100_CLKGATE_D15_AC97, | ||
| 642 | }, { | ||
| 643 | .name = "pcm", | ||
| 644 | .id = 0, | ||
| 645 | .parent = &clk_p, | ||
| 646 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 647 | .ctrlbit = S5PC100_CLKGATE_D15_PCM0, | ||
| 648 | }, { | ||
| 649 | .name = "pcm", | ||
| 650 | .id = 1, | ||
| 651 | .parent = &clk_p, | ||
| 652 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 653 | .ctrlbit = S5PC100_CLKGATE_D15_PCM1, | ||
| 654 | }, { | ||
| 655 | .name = "spdif", | ||
| 656 | .id = -1, | ||
| 657 | .parent = &clk_p, | ||
| 658 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 659 | .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, | ||
| 660 | }, { | ||
| 661 | .name = "adc", | ||
| 662 | .id = -1, | ||
| 663 | .parent = &clk_p, | ||
| 664 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 665 | .ctrlbit = S5PC100_CLKGATE_D15_TSADC, | ||
| 666 | }, { | ||
| 667 | .name = "keyif", | ||
| 668 | .id = -1, | ||
| 669 | .parent = &clk_p, | ||
| 670 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 671 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
| 672 | }, { | ||
| 673 | .name = "cg", | ||
| 674 | .id = -1, | ||
| 675 | .parent = &clk_p, | ||
| 676 | .enable = s5pc1xx_clk_d15_ctrl, | ||
| 677 | .ctrlbit = S5PC100_CLKGATE_D15_CG, | ||
| 678 | }, | ||
| 679 | 279 | ||
| 680 | /* Audio (D2_0) devices: all disabled */ | 280 | return rate / (ratio + 1); |
| 281 | } | ||
| 681 | 282 | ||
| 682 | /* Special Clocks 1 */ | 283 | static struct clk clk_dout_d1_bus = { |
| 683 | { | 284 | .name = "dout_d1_bus", |
| 684 | .name = "sclk_hpm", | 285 | .id = -1, |
| 685 | .id = -1, | 286 | .parent = &clk_mout_am.clk, |
| 686 | .parent = NULL, | 287 | .get_rate = s5pc100_clk_dout_d1_bus_get_rate, |
| 687 | .enable = s5pc1xx_sclk0_ctrl, | 288 | }; |
| 688 | .ctrlbit = S5PC1XX_CLKGATE_SCLK0_HPM, | ||
| 689 | }, { | ||
| 690 | .name = "sclk_onenand", | ||
| 691 | .id = -1, | ||
| 692 | .parent = NULL, | ||
| 693 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 694 | .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, | ||
| 695 | }, { | ||
| 696 | .name = "sclk_spi_48", | ||
| 697 | .id = 0, | ||
| 698 | .parent = &clk_48m, | ||
| 699 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 700 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, | ||
| 701 | }, { | ||
| 702 | .name = "sclk_spi_48", | ||
| 703 | .id = 1, | ||
| 704 | .parent = &clk_48m, | ||
| 705 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 706 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, | ||
| 707 | }, { | ||
| 708 | .name = "sclk_spi_48", | ||
| 709 | .id = 2, | ||
| 710 | .parent = &clk_48m, | ||
| 711 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 712 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, | ||
| 713 | }, { | ||
| 714 | .name = "sclk_mmc_48", | ||
| 715 | .id = 0, | ||
| 716 | .parent = &clk_48m, | ||
| 717 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 718 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, | ||
| 719 | }, { | ||
| 720 | .name = "sclk_mmc_48", | ||
| 721 | .id = 1, | ||
| 722 | .parent = &clk_48m, | ||
| 723 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 724 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, | ||
| 725 | }, { | ||
| 726 | .name = "sclk_mmc_48", | ||
| 727 | .id = 2, | ||
| 728 | .parent = &clk_48m, | ||
| 729 | .enable = s5pc1xx_sclk0_ctrl, | ||
| 730 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, | ||
| 731 | }, | ||
| 732 | 289 | ||
| 733 | /* Special Clocks 2 */ | 290 | static struct clk *clkset_onenand_list[] = { |
| 734 | { | 291 | [0] = &clk_dout_d0_bus, |
| 735 | .name = "sclk_tv_54", | 292 | [1] = &clk_dout_d1_bus, |
| 736 | .id = -1, | 293 | }; |
| 737 | .parent = &clk_54m, | 294 | |
| 738 | .enable = s5pc1xx_sclk1_ctrl, | 295 | static struct clk_sources clk_src_onenand = { |
| 739 | .ctrlbit = S5PC100_CLKGATE_SCLK1_TV54, | 296 | .sources = clkset_onenand_list, |
| 740 | }, { | 297 | .nr_sources = ARRAY_SIZE(clkset_onenand_list), |
| 741 | .name = "sclk_vdac_54", | 298 | }; |
| 742 | .id = -1, | 299 | |
| 743 | .parent = &clk_54m, | 300 | static struct clksrc_clk clk_mout_onenand = { |
| 744 | .enable = s5pc1xx_sclk1_ctrl, | 301 | .clk = { |
| 745 | .ctrlbit = S5PC100_CLKGATE_SCLK1_VDAC54, | 302 | .name = "mout_onenand", |
| 746 | }, { | ||
| 747 | .name = "sclk_spdif", | ||
| 748 | .id = -1, | 303 | .id = -1, |
| 749 | .parent = NULL, | ||
| 750 | .enable = s5pc1xx_sclk1_ctrl, | ||
| 751 | .ctrlbit = S5PC100_CLKGATE_SCLK1_SPDIF, | ||
| 752 | }, | 304 | }, |
| 305 | .shift = S5PC100_CLKSRC0_ONENAND_SHIFT, | ||
| 306 | .mask = S5PC100_CLKSRC0_ONENAND_MASK, | ||
| 307 | .sources = &clk_src_onenand, | ||
| 308 | .reg_source = S5PC100_CLKSRC0, | ||
| 753 | }; | 309 | }; |
| 754 | 310 | ||
| 755 | void __init s5pc1xx_register_clocks(void) | 311 | static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) |
| 756 | { | 312 | { |
| 757 | struct clk *clkp; | 313 | unsigned long rate = clk_get_rate(clk->parent); |
| 758 | int ret; | 314 | unsigned int ratio; |
| 759 | int ptr; | ||
| 760 | 315 | ||
| 761 | clkp = init_clocks; | 316 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); |
| 762 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | ||
| 763 | ret = s3c24xx_register_clock(clkp); | ||
| 764 | if (ret < 0) { | ||
| 765 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 766 | clkp->name, ret); | ||
| 767 | } | ||
| 768 | } | ||
| 769 | 317 | ||
| 770 | clkp = init_clocks_disable; | 318 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK; |
| 771 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 319 | ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT; |
| 772 | 320 | ||
| 773 | ret = s3c24xx_register_clock(clkp); | 321 | return rate / (ratio + 1); |
| 774 | if (ret < 0) { | 322 | } |
| 775 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 776 | clkp->name, ret); | ||
| 777 | } | ||
| 778 | 323 | ||
| 779 | (clkp->enable)(clkp, 0); | 324 | static struct clk clk_dout_pclkd1 = { |
| 780 | } | 325 | .name = "dout_pclkd1", |
| 326 | .id = -1, | ||
| 327 | .parent = &clk_dout_d1_bus, | ||
| 328 | .get_rate = s5pc100_clk_dout_pclkd1_get_rate, | ||
| 329 | }; | ||
| 330 | |||
| 331 | static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) | ||
| 332 | { | ||
| 333 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 334 | unsigned int ratio; | ||
| 335 | |||
| 336 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 337 | |||
| 338 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; | ||
| 339 | ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT; | ||
| 781 | 340 | ||
| 782 | s3c_pwmclk_init(); | 341 | return rate / (ratio + 1); |
| 783 | } | 342 | } |
| 784 | static struct clk clk_fout_apll = { | 343 | |
| 785 | .name = "fout_apll", | 344 | static struct clk clk_dout_mpll2 = { |
| 345 | .name = "dout_mpll2", | ||
| 786 | .id = -1, | 346 | .id = -1, |
| 347 | .parent = &clk_mout_am.clk, | ||
| 348 | .get_rate = s5pc100_clk_dout_mpll2_get_rate, | ||
| 787 | }; | 349 | }; |
| 788 | 350 | ||
| 789 | static struct clk *clk_src_apll_list[] = { | 351 | static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) |
| 790 | [0] = &clk_fin_apll, | 352 | { |
| 791 | [1] = &clk_fout_apll, | 353 | unsigned long rate = clk_get_rate(clk->parent); |
| 792 | }; | 354 | unsigned int ratio; |
| 793 | 355 | ||
| 794 | static struct clk_sources clk_src_apll = { | 356 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); |
| 795 | .sources = clk_src_apll_list, | 357 | |
| 796 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | 358 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK; |
| 359 | ratio >>= S5PC100_CLKDIV1_CAM_SHIFT; | ||
| 360 | |||
| 361 | return rate / (ratio + 1); | ||
| 362 | } | ||
| 363 | |||
| 364 | static struct clk clk_dout_cam = { | ||
| 365 | .name = "dout_cam", | ||
| 366 | .id = -1, | ||
| 367 | .parent = &clk_dout_mpll2, | ||
| 368 | .get_rate = s5pc100_clk_dout_cam_get_rate, | ||
| 797 | }; | 369 | }; |
| 798 | 370 | ||
| 799 | static struct clksrc_clk clk_mout_apll = { | 371 | static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) |
| 800 | .clk = { | 372 | { |
| 801 | .name = "mout_apll", | 373 | unsigned long rate = clk_get_rate(clk->parent); |
| 802 | .id = -1, | 374 | unsigned int ratio; |
| 803 | }, | 375 | |
| 804 | .shift = S5PC1XX_CLKSRC0_APLL_SHIFT, | 376 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); |
| 805 | .mask = S5PC1XX_CLKSRC0_APLL_MASK, | 377 | |
| 806 | .sources = &clk_src_apll, | 378 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; |
| 807 | .reg_source = S5PC1XX_CLK_SRC0, | 379 | ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT; |
| 380 | |||
| 381 | return rate / (ratio + 1); | ||
| 382 | } | ||
| 383 | |||
| 384 | static struct clk clk_dout_mpll = { | ||
| 385 | .name = "dout_mpll", | ||
| 386 | .id = -1, | ||
| 387 | .parent = &clk_mout_am.clk, | ||
| 388 | .get_rate = s5pc100_clk_dout_mpll_get_rate, | ||
| 808 | }; | 389 | }; |
| 809 | 390 | ||
| 391 | /* EPLL */ | ||
| 810 | static struct clk clk_fout_epll = { | 392 | static struct clk clk_fout_epll = { |
| 811 | .name = "fout_epll", | 393 | .name = "fout_epll", |
| 812 | .id = -1, | 394 | .id = -1, |
| @@ -827,91 +409,57 @@ static struct clksrc_clk clk_mout_epll = { | |||
| 827 | .name = "mout_epll", | 409 | .name = "mout_epll", |
| 828 | .id = -1, | 410 | .id = -1, |
| 829 | }, | 411 | }, |
| 830 | .shift = S5PC1XX_CLKSRC0_EPLL_SHIFT, | 412 | .shift = S5PC100_CLKSRC0_EPLL_SHIFT, |
| 831 | .mask = S5PC1XX_CLKSRC0_EPLL_MASK, | 413 | .mask = S5PC100_CLKSRC0_EPLL_MASK, |
| 832 | .sources = &clk_src_epll, | 414 | .sources = &clk_src_epll, |
| 833 | .reg_source = S5PC1XX_CLK_SRC0, | 415 | .reg_source = S5PC100_CLKSRC0, |
| 834 | }; | 416 | }; |
| 835 | 417 | ||
| 836 | static struct clk *clk_src_mpll_list[] = { | 418 | /* HPLL */ |
| 837 | [0] = &clk_fin_mpll, | 419 | static struct clk clk_fout_hpll = { |
| 838 | [1] = &clk_fout_mpll, | 420 | .name = "fout_hpll", |
| 839 | }; | ||
| 840 | |||
| 841 | static struct clk_sources clk_src_mpll = { | ||
| 842 | .sources = clk_src_mpll_list, | ||
| 843 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
| 844 | }; | ||
| 845 | |||
| 846 | static struct clksrc_clk clk_mout_mpll = { | ||
| 847 | .clk = { | ||
| 848 | .name = "mout_mpll", | ||
| 849 | .id = -1, | ||
| 850 | }, | ||
| 851 | .shift = S5PC1XX_CLKSRC0_MPLL_SHIFT, | ||
| 852 | .mask = S5PC1XX_CLKSRC0_MPLL_MASK, | ||
| 853 | .sources = &clk_src_mpll, | ||
| 854 | .reg_source = S5PC1XX_CLK_SRC0, | ||
| 855 | }; | ||
| 856 | |||
| 857 | static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk) | ||
| 858 | { | ||
| 859 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 860 | unsigned long clkdiv; | ||
| 861 | |||
| 862 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 863 | |||
| 864 | clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK; | ||
| 865 | rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1; | ||
| 866 | |||
| 867 | return rate; | ||
| 868 | } | ||
| 869 | |||
| 870 | static struct clk clk_dout_mpll = { | ||
| 871 | .name = "dout_mpll", | ||
| 872 | .id = -1, | 421 | .id = -1, |
| 873 | .parent = &clk_mout_mpll.clk, | ||
| 874 | .get_rate = s5pc1xx_clk_doutmpll_get_rate, | ||
| 875 | }; | 422 | }; |
| 876 | 423 | ||
| 877 | static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk) | 424 | static struct clk *clk_src_hpll_list[] = { |
| 878 | { | 425 | [0] = &clk_27m, |
| 879 | unsigned long rate = clk_get_rate(clk->parent); | 426 | [1] = &clk_fout_hpll, |
| 880 | unsigned long clkdiv; | ||
| 881 | |||
| 882 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 883 | |||
| 884 | clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK; | ||
| 885 | rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1; | ||
| 886 | |||
| 887 | return rate; | ||
| 888 | } | ||
| 889 | |||
| 890 | struct clk clk_dout_mpll2 = { | ||
| 891 | .name = "dout_mpll2", | ||
| 892 | .id = -1, | ||
| 893 | .parent = &clk_mout_mpll.clk, | ||
| 894 | .get_rate = s5pc1xx_clk_doutmpll2_get_rate, | ||
| 895 | }; | 427 | }; |
| 896 | 428 | ||
| 897 | static struct clk *clkset_uart_list[] = { | 429 | static struct clk_sources clk_src_hpll = { |
| 898 | &clk_mout_epll.clk, | 430 | .sources = clk_src_hpll_list, |
| 899 | &clk_dout_mpll, | 431 | .nr_sources = ARRAY_SIZE(clk_src_hpll_list), |
| 900 | NULL, | ||
| 901 | NULL | ||
| 902 | }; | 432 | }; |
| 903 | 433 | ||
| 904 | static struct clk_sources clkset_uart = { | 434 | static struct clksrc_clk clk_mout_hpll = { |
| 905 | .sources = clkset_uart_list, | 435 | .clk = { |
| 906 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | 436 | .name = "mout_hpll", |
| 437 | .id = -1, | ||
| 438 | }, | ||
| 439 | .shift = S5PC100_CLKSRC0_HPLL_SHIFT, | ||
| 440 | .mask = S5PC100_CLKSRC0_HPLL_MASK, | ||
| 441 | .sources = &clk_src_hpll, | ||
| 442 | .reg_source = S5PC100_CLKSRC0, | ||
| 907 | }; | 443 | }; |
| 908 | 444 | ||
| 445 | /* Peripherals */ | ||
| 446 | /* | ||
| 447 | * The peripheral clocks are all controlled via clocksource followed | ||
| 448 | * by an optional divider and gate stage. We currently roll this into | ||
| 449 | * one clock which hides the intermediate clock from the mux. | ||
| 450 | * | ||
| 451 | * Note, the JPEG clock can only be an even divider... | ||
| 452 | * | ||
| 453 | * The scaler and LCD clocks depend on the S5PC100 version, and also | ||
| 454 | * have a common parent divisor so are not included here. | ||
| 455 | */ | ||
| 456 | |||
| 909 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | 457 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) |
| 910 | { | 458 | { |
| 911 | return container_of(clk, struct clksrc_clk, clk); | 459 | return container_of(clk, struct clksrc_clk, clk); |
| 912 | } | 460 | } |
| 913 | 461 | ||
| 914 | static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) | 462 | static unsigned long s5pc100_getrate_clksrc(struct clk *clk) |
| 915 | { | 463 | { |
| 916 | struct clksrc_clk *sclk = to_clksrc(clk); | 464 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 917 | unsigned long rate = clk_get_rate(clk->parent); | 465 | unsigned long rate = clk_get_rate(clk->parent); |
| @@ -925,7 +473,7 @@ static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk) | |||
| 925 | return rate; | 473 | return rate; |
| 926 | } | 474 | } |
| 927 | 475 | ||
| 928 | static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) | 476 | static int s5pc100_setrate_clksrc(struct clk *clk, unsigned long rate) |
| 929 | { | 477 | { |
| 930 | struct clksrc_clk *sclk = to_clksrc(clk); | 478 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 931 | void __iomem *reg = sclk->reg_divider; | 479 | void __iomem *reg = sclk->reg_divider; |
| @@ -938,14 +486,14 @@ static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate) | |||
| 938 | return -EINVAL; | 486 | return -EINVAL; |
| 939 | 487 | ||
| 940 | val = __raw_readl(reg); | 488 | val = __raw_readl(reg); |
| 941 | val &= ~(0xf << sclk->shift); | 489 | val &= ~(0xf << sclk->divider_shift); |
| 942 | val |= (div - 1) << sclk->shift; | 490 | val |= (div - 1) << sclk->divider_shift; |
| 943 | __raw_writel(val, reg); | 491 | __raw_writel(val, reg); |
| 944 | 492 | ||
| 945 | return 0; | 493 | return 0; |
| 946 | } | 494 | } |
| 947 | 495 | ||
| 948 | static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) | 496 | static int s5pc100_setparent_clksrc(struct clk *clk, struct clk *parent) |
| 949 | { | 497 | { |
| 950 | struct clksrc_clk *sclk = to_clksrc(clk); | 498 | struct clksrc_clk *sclk = to_clksrc(clk); |
| 951 | struct clk_sources *srcs = sclk->sources; | 499 | struct clk_sources *srcs = sclk->sources; |
| @@ -970,7 +518,7 @@ static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent) | |||
| 970 | return -EINVAL; | 518 | return -EINVAL; |
| 971 | } | 519 | } |
| 972 | 520 | ||
| 973 | static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, | 521 | static unsigned long s5pc100_roundrate_clksrc(struct clk *clk, |
| 974 | unsigned long rate) | 522 | unsigned long rate) |
| 975 | { | 523 | { |
| 976 | unsigned long parent_rate = clk_get_rate(clk->parent); | 524 | unsigned long parent_rate = clk_get_rate(clk->parent); |
| @@ -992,35 +540,466 @@ static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk, | |||
| 992 | return rate; | 540 | return rate; |
| 993 | } | 541 | } |
| 994 | 542 | ||
| 543 | static struct clk *clkset_spi_list[] = { | ||
| 544 | &clk_mout_epll.clk, | ||
| 545 | &clk_dout_mpll2, | ||
| 546 | &clk_fin_epll, | ||
| 547 | &clk_mout_hpll.clk, | ||
| 548 | }; | ||
| 549 | |||
| 550 | static struct clk_sources clkset_spi = { | ||
| 551 | .sources = clkset_spi_list, | ||
| 552 | .nr_sources = ARRAY_SIZE(clkset_spi_list), | ||
| 553 | }; | ||
| 554 | |||
| 555 | static struct clksrc_clk clk_spi0 = { | ||
| 556 | .clk = { | ||
| 557 | .name = "spi_bus", | ||
| 558 | .id = 0, | ||
| 559 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, | ||
| 560 | .enable = s5pc100_sclk0_ctrl, | ||
| 561 | .set_parent = s5pc100_setparent_clksrc, | ||
| 562 | .get_rate = s5pc100_getrate_clksrc, | ||
| 563 | .set_rate = s5pc100_setrate_clksrc, | ||
| 564 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 565 | }, | ||
| 566 | .shift = S5PC100_CLKSRC1_SPI0_SHIFT, | ||
| 567 | .mask = S5PC100_CLKSRC1_SPI0_MASK, | ||
| 568 | .sources = &clkset_spi, | ||
| 569 | .divider_shift = S5PC100_CLKDIV2_SPI0_SHIFT, | ||
| 570 | .reg_divider = S5PC100_CLKDIV2, | ||
| 571 | .reg_source = S5PC100_CLKSRC1, | ||
| 572 | }; | ||
| 573 | |||
| 574 | static struct clksrc_clk clk_spi1 = { | ||
| 575 | .clk = { | ||
| 576 | .name = "spi_bus", | ||
| 577 | .id = 1, | ||
| 578 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, | ||
| 579 | .enable = s5pc100_sclk0_ctrl, | ||
| 580 | .set_parent = s5pc100_setparent_clksrc, | ||
| 581 | .get_rate = s5pc100_getrate_clksrc, | ||
| 582 | .set_rate = s5pc100_setrate_clksrc, | ||
| 583 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 584 | }, | ||
| 585 | .shift = S5PC100_CLKSRC1_SPI1_SHIFT, | ||
| 586 | .mask = S5PC100_CLKSRC1_SPI1_MASK, | ||
| 587 | .sources = &clkset_spi, | ||
| 588 | .divider_shift = S5PC100_CLKDIV2_SPI1_SHIFT, | ||
| 589 | .reg_divider = S5PC100_CLKDIV2, | ||
| 590 | .reg_source = S5PC100_CLKSRC1, | ||
| 591 | }; | ||
| 592 | |||
| 593 | static struct clksrc_clk clk_spi2 = { | ||
| 594 | .clk = { | ||
| 595 | .name = "spi_bus", | ||
| 596 | .id = 2, | ||
| 597 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, | ||
| 598 | .enable = s5pc100_sclk0_ctrl, | ||
| 599 | .set_parent = s5pc100_setparent_clksrc, | ||
| 600 | .get_rate = s5pc100_getrate_clksrc, | ||
| 601 | .set_rate = s5pc100_setrate_clksrc, | ||
| 602 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 603 | }, | ||
| 604 | .shift = S5PC100_CLKSRC1_SPI2_SHIFT, | ||
| 605 | .mask = S5PC100_CLKSRC1_SPI2_MASK, | ||
| 606 | .sources = &clkset_spi, | ||
| 607 | .divider_shift = S5PC100_CLKDIV2_SPI2_SHIFT, | ||
| 608 | .reg_divider = S5PC100_CLKDIV2, | ||
| 609 | .reg_source = S5PC100_CLKSRC1, | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct clk *clkset_uart_list[] = { | ||
| 613 | &clk_mout_epll.clk, | ||
| 614 | &clk_dout_mpll, | ||
| 615 | }; | ||
| 616 | |||
| 617 | static struct clk_sources clkset_uart = { | ||
| 618 | .sources = clkset_uart_list, | ||
| 619 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
| 620 | }; | ||
| 621 | |||
| 995 | static struct clksrc_clk clk_uart_uclk1 = { | 622 | static struct clksrc_clk clk_uart_uclk1 = { |
| 996 | .clk = { | 623 | .clk = { |
| 997 | .name = "uclk1", | 624 | .name = "uclk1", |
| 998 | .id = -1, | 625 | .id = -1, |
| 999 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, | 626 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, |
| 1000 | .enable = s5pc1xx_sclk0_ctrl, | 627 | .enable = s5pc100_sclk0_ctrl, |
| 1001 | .set_parent = s5pc1xx_setparent_clksrc, | 628 | .set_parent = s5pc100_setparent_clksrc, |
| 1002 | .get_rate = s5pc1xx_getrate_clksrc, | 629 | .get_rate = s5pc100_getrate_clksrc, |
| 1003 | .set_rate = s5pc1xx_setrate_clksrc, | 630 | .set_rate = s5pc100_setrate_clksrc, |
| 1004 | .round_rate = s5pc1xx_roundrate_clksrc, | 631 | .round_rate = s5pc100_roundrate_clksrc, |
| 1005 | }, | 632 | }, |
| 1006 | .shift = S5PC100_CLKSRC1_UART_SHIFT, | 633 | .shift = S5PC100_CLKSRC1_UART_SHIFT, |
| 1007 | .mask = S5PC100_CLKSRC1_UART_MASK, | 634 | .mask = S5PC100_CLKSRC1_UART_MASK, |
| 1008 | .sources = &clkset_uart, | 635 | .sources = &clkset_uart, |
| 1009 | .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, | 636 | .divider_shift = S5PC100_CLKDIV2_UART_SHIFT, |
| 1010 | .reg_divider = S5PC1XX_CLK_DIV2, | 637 | .reg_divider = S5PC100_CLKDIV2, |
| 1011 | .reg_source = S5PC1XX_CLK_SRC1, | 638 | .reg_source = S5PC100_CLKSRC1, |
| 639 | }; | ||
| 640 | |||
| 641 | static struct clk clk_iis_cd0 = { | ||
| 642 | .name = "iis_cdclk0", | ||
| 643 | .id = -1, | ||
| 644 | }; | ||
| 645 | |||
| 646 | static struct clk clk_iis_cd1 = { | ||
| 647 | .name = "iis_cdclk1", | ||
| 648 | .id = -1, | ||
| 649 | }; | ||
| 650 | |||
| 651 | static struct clk clk_iis_cd2 = { | ||
| 652 | .name = "iis_cdclk2", | ||
| 653 | .id = -1, | ||
| 654 | }; | ||
| 655 | |||
| 656 | static struct clk clk_pcm_cd0 = { | ||
| 657 | .name = "pcm_cdclk0", | ||
| 658 | .id = -1, | ||
| 659 | }; | ||
| 660 | |||
| 661 | static struct clk clk_pcm_cd1 = { | ||
| 662 | .name = "pcm_cdclk1", | ||
| 663 | .id = -1, | ||
| 664 | }; | ||
| 665 | |||
| 666 | static struct clk *clkset_audio0_list[] = { | ||
| 667 | &clk_mout_epll.clk, | ||
| 668 | &clk_dout_mpll, | ||
| 669 | &clk_fin_epll, | ||
| 670 | &clk_iis_cd0, | ||
| 671 | &clk_pcm_cd0, | ||
| 672 | &clk_mout_hpll.clk, | ||
| 673 | }; | ||
| 674 | |||
| 675 | static struct clk_sources clkset_audio0 = { | ||
| 676 | .sources = clkset_audio0_list, | ||
| 677 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | ||
| 678 | }; | ||
| 679 | |||
| 680 | static struct clksrc_clk clk_audio0 = { | ||
| 681 | .clk = { | ||
| 682 | .name = "audio-bus", | ||
| 683 | .id = 0, | ||
| 684 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, | ||
| 685 | .enable = s5pc100_sclk1_ctrl, | ||
| 686 | .set_parent = s5pc100_setparent_clksrc, | ||
| 687 | .get_rate = s5pc100_getrate_clksrc, | ||
| 688 | .set_rate = s5pc100_setrate_clksrc, | ||
| 689 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 690 | }, | ||
| 691 | .shift = S5PC100_CLKSRC3_AUDIO0_SHIFT, | ||
| 692 | .mask = S5PC100_CLKSRC3_AUDIO0_MASK, | ||
| 693 | .sources = &clkset_audio0, | ||
| 694 | .divider_shift = S5PC100_CLKDIV4_AUDIO0_SHIFT, | ||
| 695 | .reg_divider = S5PC100_CLKDIV4, | ||
| 696 | .reg_source = S5PC100_CLKSRC3, | ||
| 697 | }; | ||
| 698 | |||
| 699 | static struct clk *clkset_audio1_list[] = { | ||
| 700 | &clk_mout_epll.clk, | ||
| 701 | &clk_dout_mpll, | ||
| 702 | &clk_fin_epll, | ||
| 703 | &clk_iis_cd1, | ||
| 704 | &clk_pcm_cd1, | ||
| 705 | &clk_mout_hpll.clk, | ||
| 706 | }; | ||
| 707 | |||
| 708 | static struct clk_sources clkset_audio1 = { | ||
| 709 | .sources = clkset_audio1_list, | ||
| 710 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | ||
| 711 | }; | ||
| 712 | |||
| 713 | static struct clksrc_clk clk_audio1 = { | ||
| 714 | .clk = { | ||
| 715 | .name = "audio-bus", | ||
| 716 | .id = 1, | ||
| 717 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, | ||
| 718 | .enable = s5pc100_sclk1_ctrl, | ||
| 719 | .set_parent = s5pc100_setparent_clksrc, | ||
| 720 | .get_rate = s5pc100_getrate_clksrc, | ||
| 721 | .set_rate = s5pc100_setrate_clksrc, | ||
| 722 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 723 | }, | ||
| 724 | .shift = S5PC100_CLKSRC3_AUDIO1_SHIFT, | ||
| 725 | .mask = S5PC100_CLKSRC3_AUDIO1_MASK, | ||
| 726 | .sources = &clkset_audio1, | ||
| 727 | .divider_shift = S5PC100_CLKDIV4_AUDIO1_SHIFT, | ||
| 728 | .reg_divider = S5PC100_CLKDIV4, | ||
| 729 | .reg_source = S5PC100_CLKSRC3, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct clk *clkset_audio2_list[] = { | ||
| 733 | &clk_mout_epll.clk, | ||
| 734 | &clk_dout_mpll, | ||
| 735 | &clk_fin_epll, | ||
| 736 | &clk_iis_cd2, | ||
| 737 | &clk_mout_hpll.clk, | ||
| 738 | }; | ||
| 739 | |||
| 740 | static struct clk_sources clkset_audio2 = { | ||
| 741 | .sources = clkset_audio2_list, | ||
| 742 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), | ||
| 743 | }; | ||
| 744 | |||
| 745 | static struct clksrc_clk clk_audio2 = { | ||
| 746 | .clk = { | ||
| 747 | .name = "audio-bus", | ||
| 748 | .id = 2, | ||
| 749 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, | ||
| 750 | .enable = s5pc100_sclk1_ctrl, | ||
| 751 | .set_parent = s5pc100_setparent_clksrc, | ||
| 752 | .get_rate = s5pc100_getrate_clksrc, | ||
| 753 | .set_rate = s5pc100_setrate_clksrc, | ||
| 754 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 755 | }, | ||
| 756 | .shift = S5PC100_CLKSRC3_AUDIO2_SHIFT, | ||
| 757 | .mask = S5PC100_CLKSRC3_AUDIO2_MASK, | ||
| 758 | .sources = &clkset_audio2, | ||
| 759 | .divider_shift = S5PC100_CLKDIV4_AUDIO2_SHIFT, | ||
| 760 | .reg_divider = S5PC100_CLKDIV4, | ||
| 761 | .reg_source = S5PC100_CLKSRC3, | ||
| 762 | }; | ||
| 763 | |||
| 764 | static struct clk *clkset_spdif_list[] = { | ||
| 765 | &clk_audio0.clk, | ||
| 766 | &clk_audio1.clk, | ||
| 767 | &clk_audio2.clk, | ||
| 768 | }; | ||
| 769 | |||
| 770 | static struct clk_sources clkset_spdif = { | ||
| 771 | .sources = clkset_spdif_list, | ||
| 772 | .nr_sources = ARRAY_SIZE(clkset_spdif_list), | ||
| 773 | }; | ||
| 774 | |||
| 775 | static struct clksrc_clk clk_spdif = { | ||
| 776 | .clk = { | ||
| 777 | .name = "spdif", | ||
| 778 | .id = -1, | ||
| 779 | }, | ||
| 780 | .shift = S5PC100_CLKSRC3_SPDIF_SHIFT, | ||
| 781 | .mask = S5PC100_CLKSRC3_SPDIF_MASK, | ||
| 782 | .sources = &clkset_spdif, | ||
| 783 | .reg_source = S5PC100_CLKSRC3, | ||
| 784 | }; | ||
| 785 | |||
| 786 | static struct clk *clkset_lcd_fimc_list[] = { | ||
| 787 | &clk_mout_epll.clk, | ||
| 788 | &clk_dout_mpll, | ||
| 789 | &clk_mout_hpll.clk, | ||
| 790 | &clk_vclk_54m, | ||
| 791 | }; | ||
| 792 | |||
| 793 | static struct clk_sources clkset_lcd_fimc = { | ||
| 794 | .sources = clkset_lcd_fimc_list, | ||
| 795 | .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), | ||
| 796 | }; | ||
| 797 | |||
| 798 | static struct clksrc_clk clk_lcd = { | ||
| 799 | .clk = { | ||
| 800 | .name = "lcd", | ||
| 801 | .id = -1, | ||
| 802 | .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, | ||
| 803 | .enable = s5pc100_sclk1_ctrl, | ||
| 804 | .set_parent = s5pc100_setparent_clksrc, | ||
| 805 | .get_rate = s5pc100_getrate_clksrc, | ||
| 806 | .set_rate = s5pc100_setrate_clksrc, | ||
| 807 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 808 | }, | ||
| 809 | .shift = S5PC100_CLKSRC2_LCD_SHIFT, | ||
| 810 | .mask = S5PC100_CLKSRC2_LCD_MASK, | ||
| 811 | .sources = &clkset_lcd_fimc, | ||
| 812 | .divider_shift = S5PC100_CLKDIV3_LCD_SHIFT, | ||
| 813 | .reg_divider = S5PC100_CLKDIV3, | ||
| 814 | .reg_source = S5PC100_CLKSRC2, | ||
| 815 | }; | ||
| 816 | |||
| 817 | static struct clksrc_clk clk_fimc0 = { | ||
| 818 | .clk = { | ||
| 819 | .name = "fimc", | ||
| 820 | .id = 0, | ||
| 821 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, | ||
| 822 | .enable = s5pc100_sclk1_ctrl, | ||
| 823 | .set_parent = s5pc100_setparent_clksrc, | ||
| 824 | .get_rate = s5pc100_getrate_clksrc, | ||
| 825 | .set_rate = s5pc100_setrate_clksrc, | ||
| 826 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 827 | }, | ||
| 828 | .shift = S5PC100_CLKSRC2_FIMC0_SHIFT, | ||
| 829 | .mask = S5PC100_CLKSRC2_FIMC0_MASK, | ||
| 830 | .sources = &clkset_lcd_fimc, | ||
| 831 | .divider_shift = S5PC100_CLKDIV3_FIMC0_SHIFT, | ||
| 832 | .reg_divider = S5PC100_CLKDIV3, | ||
| 833 | .reg_source = S5PC100_CLKSRC2, | ||
| 834 | }; | ||
| 835 | |||
| 836 | static struct clksrc_clk clk_fimc1 = { | ||
| 837 | .clk = { | ||
| 838 | .name = "fimc", | ||
| 839 | .id = 1, | ||
| 840 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, | ||
| 841 | .enable = s5pc100_sclk1_ctrl, | ||
| 842 | .set_parent = s5pc100_setparent_clksrc, | ||
| 843 | .get_rate = s5pc100_getrate_clksrc, | ||
| 844 | .set_rate = s5pc100_setrate_clksrc, | ||
| 845 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 846 | }, | ||
| 847 | .shift = S5PC100_CLKSRC2_FIMC1_SHIFT, | ||
| 848 | .mask = S5PC100_CLKSRC2_FIMC1_MASK, | ||
| 849 | .sources = &clkset_lcd_fimc, | ||
| 850 | .divider_shift = S5PC100_CLKDIV3_FIMC1_SHIFT, | ||
| 851 | .reg_divider = S5PC100_CLKDIV3, | ||
| 852 | .reg_source = S5PC100_CLKSRC2, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct clksrc_clk clk_fimc2 = { | ||
| 856 | .clk = { | ||
| 857 | .name = "fimc", | ||
| 858 | .id = 2, | ||
| 859 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, | ||
| 860 | .enable = s5pc100_sclk1_ctrl, | ||
| 861 | .set_parent = s5pc100_setparent_clksrc, | ||
| 862 | .get_rate = s5pc100_getrate_clksrc, | ||
| 863 | .set_rate = s5pc100_setrate_clksrc, | ||
| 864 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 865 | }, | ||
| 866 | .shift = S5PC100_CLKSRC2_FIMC2_SHIFT, | ||
| 867 | .mask = S5PC100_CLKSRC2_FIMC2_MASK, | ||
| 868 | .sources = &clkset_lcd_fimc, | ||
| 869 | .divider_shift = S5PC100_CLKDIV3_FIMC2_SHIFT, | ||
| 870 | .reg_divider = S5PC100_CLKDIV3, | ||
| 871 | .reg_source = S5PC100_CLKSRC2, | ||
| 872 | }; | ||
| 873 | |||
| 874 | static struct clk *clkset_mmc_list[] = { | ||
| 875 | &clk_mout_epll.clk, | ||
| 876 | &clk_dout_mpll, | ||
| 877 | &clk_fin_epll, | ||
| 878 | &clk_mout_hpll.clk , | ||
| 879 | }; | ||
| 880 | |||
| 881 | static struct clk_sources clkset_mmc = { | ||
| 882 | .sources = clkset_mmc_list, | ||
| 883 | .nr_sources = ARRAY_SIZE(clkset_mmc_list), | ||
| 884 | }; | ||
| 885 | |||
| 886 | static struct clksrc_clk clk_mmc0 = { | ||
| 887 | .clk = { | ||
| 888 | .name = "mmc_bus", | ||
| 889 | .id = 0, | ||
| 890 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, | ||
| 891 | .enable = s5pc100_sclk0_ctrl, | ||
| 892 | .set_parent = s5pc100_setparent_clksrc, | ||
| 893 | .get_rate = s5pc100_getrate_clksrc, | ||
| 894 | .set_rate = s5pc100_setrate_clksrc, | ||
| 895 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 896 | }, | ||
| 897 | .shift = S5PC100_CLKSRC2_MMC0_SHIFT, | ||
| 898 | .mask = S5PC100_CLKSRC2_MMC0_MASK, | ||
| 899 | .sources = &clkset_mmc, | ||
| 900 | .divider_shift = S5PC100_CLKDIV3_MMC0_SHIFT, | ||
| 901 | .reg_divider = S5PC100_CLKDIV3, | ||
| 902 | .reg_source = S5PC100_CLKSRC2, | ||
| 903 | }; | ||
| 904 | |||
| 905 | static struct clksrc_clk clk_mmc1 = { | ||
| 906 | .clk = { | ||
| 907 | .name = "mmc_bus", | ||
| 908 | .id = 1, | ||
| 909 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, | ||
| 910 | .enable = s5pc100_sclk0_ctrl, | ||
| 911 | .set_parent = s5pc100_setparent_clksrc, | ||
| 912 | .get_rate = s5pc100_getrate_clksrc, | ||
| 913 | .set_rate = s5pc100_setrate_clksrc, | ||
| 914 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 915 | }, | ||
| 916 | .shift = S5PC100_CLKSRC2_MMC1_SHIFT, | ||
| 917 | .mask = S5PC100_CLKSRC2_MMC1_MASK, | ||
| 918 | .sources = &clkset_mmc, | ||
| 919 | .divider_shift = S5PC100_CLKDIV3_MMC1_SHIFT, | ||
| 920 | .reg_divider = S5PC100_CLKDIV3, | ||
| 921 | .reg_source = S5PC100_CLKSRC2, | ||
| 922 | }; | ||
| 923 | |||
| 924 | static struct clksrc_clk clk_mmc2 = { | ||
| 925 | .clk = { | ||
| 926 | .name = "mmc_bus", | ||
| 927 | .id = 2, | ||
| 928 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, | ||
| 929 | .enable = s5pc100_sclk0_ctrl, | ||
| 930 | .set_parent = s5pc100_setparent_clksrc, | ||
| 931 | .get_rate = s5pc100_getrate_clksrc, | ||
| 932 | .set_rate = s5pc100_setrate_clksrc, | ||
| 933 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 934 | }, | ||
| 935 | .shift = S5PC100_CLKSRC2_MMC2_SHIFT, | ||
| 936 | .mask = S5PC100_CLKSRC2_MMC2_MASK, | ||
| 937 | .sources = &clkset_mmc, | ||
| 938 | .divider_shift = S5PC100_CLKDIV3_MMC2_SHIFT, | ||
| 939 | .reg_divider = S5PC100_CLKDIV3, | ||
| 940 | .reg_source = S5PC100_CLKSRC2, | ||
| 941 | }; | ||
| 942 | |||
| 943 | |||
| 944 | static struct clk *clkset_usbhost_list[] = { | ||
| 945 | &clk_mout_epll.clk, | ||
| 946 | &clk_dout_mpll, | ||
| 947 | &clk_mout_hpll.clk, | ||
| 948 | &clk_48m, | ||
| 949 | }; | ||
| 950 | |||
| 951 | static struct clk_sources clkset_usbhost = { | ||
| 952 | .sources = clkset_usbhost_list, | ||
| 953 | .nr_sources = ARRAY_SIZE(clkset_usbhost_list), | ||
| 954 | }; | ||
| 955 | |||
| 956 | static struct clksrc_clk clk_usbhost = { | ||
| 957 | .clk = { | ||
| 958 | .name = "usbhost", | ||
| 959 | .id = -1, | ||
| 960 | .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, | ||
| 961 | .enable = s5pc100_sclk0_ctrl, | ||
| 962 | .set_parent = s5pc100_setparent_clksrc, | ||
| 963 | .get_rate = s5pc100_getrate_clksrc, | ||
| 964 | .set_rate = s5pc100_setrate_clksrc, | ||
| 965 | .round_rate = s5pc100_roundrate_clksrc, | ||
| 966 | }, | ||
| 967 | .shift = S5PC100_CLKSRC1_UHOST_SHIFT, | ||
| 968 | .mask = S5PC100_CLKSRC1_UHOST_MASK, | ||
| 969 | .sources = &clkset_usbhost, | ||
| 970 | .divider_shift = S5PC100_CLKDIV2_UHOST_SHIFT, | ||
| 971 | .reg_divider = S5PC100_CLKDIV2, | ||
| 972 | .reg_source = S5PC100_CLKSRC1, | ||
| 1012 | }; | 973 | }; |
| 1013 | 974 | ||
| 1014 | /* Clock initialisation code */ | 975 | /* Clock initialisation code */ |
| 1015 | 976 | ||
| 1016 | static struct clksrc_clk *init_parents[] = { | 977 | static struct clksrc_clk *init_parents[] = { |
| 1017 | &clk_mout_apll, | 978 | &clk_mout_apll, |
| 1018 | &clk_mout_epll, | ||
| 1019 | &clk_mout_mpll, | 979 | &clk_mout_mpll, |
| 980 | &clk_mout_am, | ||
| 981 | &clk_mout_onenand, | ||
| 982 | &clk_mout_epll, | ||
| 983 | &clk_mout_hpll, | ||
| 984 | &clk_spi0, | ||
| 985 | &clk_spi1, | ||
| 986 | &clk_spi2, | ||
| 1020 | &clk_uart_uclk1, | 987 | &clk_uart_uclk1, |
| 988 | &clk_audio0, | ||
| 989 | &clk_audio1, | ||
| 990 | &clk_audio2, | ||
| 991 | &clk_spdif, | ||
| 992 | &clk_lcd, | ||
| 993 | &clk_fimc0, | ||
| 994 | &clk_fimc1, | ||
| 995 | &clk_fimc2, | ||
| 996 | &clk_mmc0, | ||
| 997 | &clk_mmc1, | ||
| 998 | &clk_mmc2, | ||
| 999 | &clk_usbhost, | ||
| 1021 | }; | 1000 | }; |
| 1022 | 1001 | ||
| 1023 | static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) | 1002 | static void __init_or_cpufreq s5pc100_set_clksrc(struct clksrc_clk *clk) |
| 1024 | { | 1003 | { |
| 1025 | struct clk_sources *srcs = clk->sources; | 1004 | struct clk_sources *srcs = clk->sources; |
| 1026 | u32 clksrc = __raw_readl(clk->reg_source); | 1005 | u32 clksrc = __raw_readl(clk->reg_source); |
| @@ -1036,9 +1015,9 @@ static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk) | |||
| 1036 | 1015 | ||
| 1037 | clk->clk.parent = srcs->sources[clksrc]; | 1016 | clk->clk.parent = srcs->sources[clksrc]; |
| 1038 | 1017 | ||
| 1039 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", | 1018 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld.%03ld MHz\n", |
| 1040 | clk->clk.name, clk->clk.parent->name, clksrc, | 1019 | clk->clk.name, clk->clk.parent->name, clksrc, |
| 1041 | clk_get_rate(&clk->clk)); | 1020 | print_mhz(clk_get_rate(&clk->clk))); |
| 1042 | } | 1021 | } |
| 1043 | 1022 | ||
| 1044 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | 1023 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
| @@ -1052,20 +1031,16 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) | |||
| 1052 | unsigned long hclk; | 1031 | unsigned long hclk; |
| 1053 | unsigned long pclkd0; | 1032 | unsigned long pclkd0; |
| 1054 | unsigned long pclk; | 1033 | unsigned long pclk; |
| 1055 | unsigned long apll; | 1034 | unsigned long apll, mpll, epll, hpll; |
| 1056 | unsigned long mpll; | ||
| 1057 | unsigned long hpll; | ||
| 1058 | unsigned long epll; | ||
| 1059 | unsigned int ptr; | 1035 | unsigned int ptr; |
| 1060 | u32 clkdiv0, clkdiv1; | 1036 | u32 clkdiv0, clkdiv1; |
| 1061 | 1037 | ||
| 1062 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | 1038 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); |
| 1063 | 1039 | ||
| 1064 | clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0); | 1040 | clkdiv0 = __raw_readl(S5PC100_CLKDIV0); |
| 1065 | clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1); | 1041 | clkdiv1 = __raw_readl(S5PC100_CLKDIV1); |
| 1066 | 1042 | ||
| 1067 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", | 1043 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); |
| 1068 | __func__, clkdiv0, clkdiv1); | ||
| 1069 | 1044 | ||
| 1070 | xtal_clk = clk_get(NULL, "xtal"); | 1045 | xtal_clk = clk_get(NULL, "xtal"); |
| 1071 | BUG_ON(IS_ERR(xtal_clk)); | 1046 | BUG_ON(IS_ERR(xtal_clk)); |
| @@ -1075,48 +1050,81 @@ void __init_or_cpufreq s5pc100_setup_clocks(void) | |||
| 1075 | 1050 | ||
| 1076 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | 1051 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); |
| 1077 | 1052 | ||
| 1078 | apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON)); | 1053 | apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON)); |
| 1079 | mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON)); | 1054 | mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON)); |
| 1080 | epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON)); | 1055 | epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); |
| 1081 | hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); | 1056 | hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); |
| 1082 | 1057 | ||
| 1083 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n", | 1058 | printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz" |
| 1084 | apll, mpll, epll, hpll); | 1059 | ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n", |
| 1060 | print_mhz(apll), print_mhz(mpll), | ||
| 1061 | print_mhz(epll), print_mhz(hpll)); | ||
| 1085 | 1062 | ||
| 1086 | armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL); | 1063 | armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); |
| 1087 | armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); | 1064 | armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); |
| 1088 | hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); | 1065 | hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); |
| 1089 | pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); | 1066 | pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); |
| 1090 | hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); | 1067 | hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); |
| 1091 | pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); | 1068 | pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); |
| 1092 | 1069 | ||
| 1093 | printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n", | 1070 | printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz," |
| 1094 | armclk, hclkd0, pclkd0, hclk, pclk); | 1071 | " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz," |
| 1072 | " PCLK=%ld.%03ld MHz\n", | ||
| 1073 | print_mhz(armclk), print_mhz(hclkd0), | ||
| 1074 | print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk)); | ||
| 1095 | 1075 | ||
| 1096 | clk_fout_apll.rate = apll; | 1076 | clk_fout_apll.rate = apll; |
| 1097 | clk_fout_mpll.rate = mpll; | 1077 | clk_fout_mpll.rate = mpll; |
| 1098 | clk_fout_epll.rate = epll; | 1078 | clk_fout_epll.rate = epll; |
| 1099 | clk_fout_apll.rate = apll; | 1079 | clk_fout_hpll.rate = hpll; |
| 1100 | 1080 | ||
| 1101 | clk_h.rate = hclk; | 1081 | clk_h.rate = hclk; |
| 1102 | clk_p.rate = pclk; | 1082 | clk_p.rate = pclk; |
| 1083 | clk_f.rate = armclk; | ||
| 1103 | 1084 | ||
| 1104 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | 1085 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) |
| 1105 | s5pc1xx_set_clksrc(init_parents[ptr]); | 1086 | s5pc100_set_clksrc(init_parents[ptr]); |
| 1106 | } | 1087 | } |
| 1107 | 1088 | ||
| 1108 | static struct clk *clks[] __initdata = { | 1089 | static struct clk *clks[] __initdata = { |
| 1109 | &clk_ext_xtal_mux, | 1090 | &clk_ext_xtal_mux, |
| 1110 | &clk_mout_epll.clk, | 1091 | &clk_mout_apll.clk, |
| 1111 | &clk_fout_epll, | 1092 | &clk_dout_apll, |
| 1093 | &clk_dout_d0_bus, | ||
| 1094 | &clk_dout_pclkd0, | ||
| 1095 | &clk_dout_apll2, | ||
| 1112 | &clk_mout_mpll.clk, | 1096 | &clk_mout_mpll.clk, |
| 1097 | &clk_mout_am.clk, | ||
| 1098 | &clk_dout_d1_bus, | ||
| 1099 | &clk_mout_onenand.clk, | ||
| 1100 | &clk_dout_pclkd1, | ||
| 1101 | &clk_dout_mpll2, | ||
| 1102 | &clk_dout_cam, | ||
| 1113 | &clk_dout_mpll, | 1103 | &clk_dout_mpll, |
| 1104 | &clk_mout_epll.clk, | ||
| 1105 | &clk_fout_epll, | ||
| 1106 | &clk_iis_cd0, | ||
| 1107 | &clk_iis_cd1, | ||
| 1108 | &clk_iis_cd2, | ||
| 1109 | &clk_pcm_cd0, | ||
| 1110 | &clk_pcm_cd1, | ||
| 1111 | &clk_spi0.clk, | ||
| 1112 | &clk_spi1.clk, | ||
| 1113 | &clk_spi2.clk, | ||
| 1114 | &clk_uart_uclk1.clk, | 1114 | &clk_uart_uclk1.clk, |
| 1115 | &clk_ext, | 1115 | &clk_audio0.clk, |
| 1116 | &clk_epll, | 1116 | &clk_audio1.clk, |
| 1117 | &clk_27m, | 1117 | &clk_audio2.clk, |
| 1118 | &clk_48m, | 1118 | &clk_spdif.clk, |
| 1119 | &clk_54m, | 1119 | &clk_lcd.clk, |
| 1120 | &clk_fimc0.clk, | ||
| 1121 | &clk_fimc1.clk, | ||
| 1122 | &clk_fimc2.clk, | ||
| 1123 | &clk_mmc0.clk, | ||
| 1124 | &clk_mmc1.clk, | ||
| 1125 | &clk_mmc2.clk, | ||
| 1126 | &clk_usbhost.clk, | ||
| 1127 | &clk_arm, | ||
| 1120 | }; | 1128 | }; |
| 1121 | 1129 | ||
| 1122 | void __init s5pc100_register_clocks(void) | 1130 | void __init s5pc100_register_clocks(void) |
| @@ -1133,7 +1141,4 @@ void __init s5pc100_register_clocks(void) | |||
| 1133 | clkp->name, ret); | 1141 | clkp->name, ret); |
| 1134 | } | 1142 | } |
| 1135 | } | 1143 | } |
| 1136 | |||
| 1137 | clk_mpll.parent = &clk_mout_mpll.clk; | ||
| 1138 | clk_epll.parent = &clk_mout_epll.clk; | ||
| 1139 | } | 1144 | } |
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c new file mode 100644 index 000000000000..1a63768a9a2e --- /dev/null +++ b/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c | |||
| @@ -0,0 +1,49 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c | ||
| 3 | * | ||
| 4 | * Copyright 2009 Samsung Electronics | ||
| 5 | * | ||
| 6 | * Base S5PC1XX setup information for 24bpp LCD framebuffer | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/fb.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | |||
| 18 | #include <mach/regs-fb.h> | ||
| 19 | #include <mach/map.h> | ||
| 20 | #include <plat/fb.h> | ||
| 21 | #include <plat/gpio-cfg.h> | ||
| 22 | #include <plat/gpio-cfg-s5pc1xx.h> | ||
| 23 | |||
| 24 | #define DISR_OFFSET 0x7008 | ||
| 25 | |||
| 26 | void s5pc100_fb_gpio_setup_24bpp(void) | ||
| 27 | { | ||
| 28 | unsigned int gpio = 0; | ||
| 29 | |||
| 30 | for (gpio = S5PC100_GPF0(0); gpio <= S5PC100_GPF0(7); gpio++) { | ||
| 31 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 32 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 33 | } | ||
| 34 | |||
| 35 | for (gpio = S5PC100_GPF1(0); gpio <= S5PC100_GPF1(7); gpio++) { | ||
| 36 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 37 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 38 | } | ||
| 39 | |||
| 40 | for (gpio = S5PC100_GPF2(0); gpio <= S5PC100_GPF2(7); gpio++) { | ||
| 41 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 43 | } | ||
| 44 | |||
| 45 | for (gpio = S5PC100_GPF3(0); gpio <= S5PC100_GPF3(3); gpio++) { | ||
| 46 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 47 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 48 | } | ||
| 49 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c index 3d00c025fffb..5e4a7c3a231e 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c0.c +++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c | |||
| @@ -17,9 +17,14 @@ | |||
| 17 | 17 | ||
| 18 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
| 19 | 19 | ||
| 20 | #include <linux/gpio.h> | ||
| 20 | #include <plat/iic.h> | 21 | #include <plat/iic.h> |
| 22 | #include <plat/gpio-cfg.h> | ||
| 21 | 23 | ||
| 22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) |
| 23 | { | 25 | { |
| 24 | /* Pin configuration would be needed */ | 26 | s3c_gpio_cfgpin(S5PC100_GPD(3), S3C_GPIO_SFN(2)); |
| 27 | s3c_gpio_setpull(S5PC100_GPD(3), S3C_GPIO_PULL_UP); | ||
| 28 | s3c_gpio_cfgpin(S5PC100_GPD(4), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_setpull(S5PC100_GPD(4), S3C_GPIO_PULL_UP); | ||
| 25 | } | 30 | } |
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c index c8f3ca42f51d..a0a8b4ae6ad8 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c1.c +++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c | |||
| @@ -17,9 +17,14 @@ | |||
| 17 | 17 | ||
| 18 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
| 19 | 19 | ||
| 20 | #include <linux/gpio.h> | ||
| 20 | #include <plat/iic.h> | 21 | #include <plat/iic.h> |
| 22 | #include <plat/gpio-cfg.h> | ||
| 21 | 23 | ||
| 22 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) |
| 23 | { | 25 | { |
| 24 | /* Pin configuration would be needed */ | 26 | s3c_gpio_cfgpin(S5PC100_GPD(5), S3C_GPIO_SFN(2)); |
| 27 | s3c_gpio_setpull(S5PC100_GPD(5), S3C_GPIO_PULL_UP); | ||
| 28 | s3c_gpio_cfgpin(S5PC100_GPD(6), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_setpull(S5PC100_GPD(6), S3C_GPIO_PULL_UP); | ||
| 25 | } | 30 | } |
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c new file mode 100644 index 000000000000..185c8941e644 --- /dev/null +++ b/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Eletronics | ||
| 4 | * | ||
| 5 | * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/types.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/mmc/host.h> | ||
| 19 | #include <linux/mmc/card.h> | ||
| 20 | |||
| 21 | #include <plat/gpio-cfg.h> | ||
| 22 | #include <plat/regs-sdhci.h> | ||
| 23 | |||
| 24 | void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | ||
| 25 | { | ||
| 26 | unsigned int gpio; | ||
| 27 | unsigned int end; | ||
| 28 | unsigned int num; | ||
| 29 | |||
| 30 | num = width; | ||
| 31 | /* In case of 8 width, we should decrease the 2 */ | ||
| 32 | if (width == 8) | ||
| 33 | num = width - 2; | ||
| 34 | |||
| 35 | end = S5PC100_GPG0(2 + num); | ||
| 36 | |||
| 37 | /* Set all the necessary GPG0/GPG1 pins to special-function 0 */ | ||
| 38 | for (gpio = S5PC100_GPG0(0); gpio < end; gpio++) { | ||
| 39 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 40 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 41 | } | ||
| 42 | |||
| 43 | if (width == 8) { | ||
| 44 | for (gpio = S5PC100_GPG1(0); gpio <= S5PC100_GPG1(1); gpio++) { | ||
| 45 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 46 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 47 | } | ||
| 48 | } | ||
| 49 | |||
| 50 | s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); | ||
| 51 | s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); | ||
| 52 | } | ||
| 53 | |||
| 54 | void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | ||
| 55 | { | ||
| 56 | unsigned int gpio; | ||
| 57 | unsigned int end; | ||
| 58 | |||
| 59 | end = S5PC100_GPG2(2 + width); | ||
| 60 | |||
| 61 | /* Set all the necessary GPG2 pins to special-function 2 */ | ||
| 62 | for (gpio = S5PC100_GPG2(0); gpio < end; gpio++) { | ||
| 63 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 64 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 65 | } | ||
| 66 | |||
| 67 | s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); | ||
| 68 | s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); | ||
| 69 | } | ||
| 70 | |||
| 71 | void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
| 72 | { | ||
| 73 | unsigned int gpio; | ||
| 74 | unsigned int end; | ||
| 75 | |||
| 76 | end = S5PC100_GPG3(2 + width); | ||
| 77 | |||
| 78 | /* Set all the necessary GPG3 pins to special-function 2 */ | ||
| 79 | for (gpio = S5PC100_GPG3(0); gpio < end; gpio++) { | ||
| 80 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 81 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 82 | } | ||
| 83 | |||
| 84 | s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); | ||
| 85 | s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); | ||
| 86 | } | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig new file mode 100644 index 000000000000..486a0d6301e7 --- /dev/null +++ b/arch/arm/plat-samsung/Kconfig | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | # arch/arm/plat-samsung/Kconfig | ||
| 2 | # | ||
| 3 | # Copyright 2009 Simtec Electronics | ||
| 4 | # | ||
| 5 | # Licensed under GPLv2 | ||
| 6 | |||
| 7 | config PLAT_SAMSUNG | ||
| 8 | bool | ||
| 9 | depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX | ||
| 10 | default y | ||
| 11 | help | ||
| 12 | Base platform code for all Samsung SoC based systems | ||
| 13 | |||
| 14 | if PLAT_SAMSUNG | ||
| 15 | |||
| 16 | |||
| 17 | endif | ||
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile new file mode 100644 index 000000000000..4478b9f7dc34 --- /dev/null +++ b/arch/arm/plat-samsung/Makefile | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | # arch/arm/plat-s3c64xx/Makefile | ||
| 2 | # | ||
| 3 | # Copyright 2009 Simtec Electronics | ||
| 4 | # | ||
| 5 | # Licensed under GPLv2 | ||
| 6 | |||
| 7 | obj-y := | ||
| 8 | obj-m := | ||
| 9 | obj-n := dummy.o | ||
| 10 | obj- := | ||
| 11 | |||
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig index 35e3bd9858df..d856354f4272 100644 --- a/arch/avr32/Kconfig +++ b/arch/avr32/Kconfig | |||
| @@ -92,6 +92,7 @@ config PLATFORM_AT32AP | |||
| 92 | select PERFORMANCE_COUNTERS | 92 | select PERFORMANCE_COUNTERS |
| 93 | select ARCH_REQUIRE_GPIOLIB | 93 | select ARCH_REQUIRE_GPIOLIB |
| 94 | select GENERIC_ALLOCATOR | 94 | select GENERIC_ALLOCATOR |
| 95 | select HAVE_FB_ATMEL | ||
| 95 | 96 | ||
| 96 | # | 97 | # |
| 97 | # CPU types | 98 | # CPU types |
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index b00d67319058..c85f6166056e 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c | |||
| @@ -43,6 +43,9 @@ | |||
| 43 | #define NR_SG 1 | 43 | #define NR_SG 1 |
| 44 | #define CLKRT_OFF (~0) | 44 | #define CLKRT_OFF (~0) |
| 45 | 45 | ||
| 46 | #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ | ||
| 47 | || cpu_is_pxa935()) | ||
| 48 | |||
| 46 | struct pxamci_host { | 49 | struct pxamci_host { |
| 47 | struct mmc_host *mmc; | 50 | struct mmc_host *mmc; |
| 48 | spinlock_t lock; | 51 | spinlock_t lock; |
| @@ -457,7 +460,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |||
| 457 | clk_enable(host->clk); | 460 | clk_enable(host->clk); |
| 458 | 461 | ||
| 459 | if (ios->clock == 26000000) { | 462 | if (ios->clock == 26000000) { |
| 460 | /* to support 26MHz on pxa300/pxa310 */ | 463 | /* to support 26MHz */ |
| 461 | host->clkrt = 7; | 464 | host->clkrt = 7; |
| 462 | } else { | 465 | } else { |
| 463 | /* to handle (19.5MHz, 26MHz) */ | 466 | /* to handle (19.5MHz, 26MHz) */ |
| @@ -608,8 +611,7 @@ static int pxamci_probe(struct platform_device *pdev) | |||
| 608 | * Calculate minimum clock rate, rounding up. | 611 | * Calculate minimum clock rate, rounding up. |
| 609 | */ | 612 | */ |
| 610 | mmc->f_min = (host->clkrate + 63) / 64; | 613 | mmc->f_min = (host->clkrate + 63) / 64; |
| 611 | mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 | 614 | mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; |
| 612 | : host->clkrate; | ||
| 613 | 615 | ||
| 614 | pxamci_init_ocr(host); | 616 | pxamci_init_ocr(host); |
| 615 | 617 | ||
| @@ -618,7 +620,7 @@ static int pxamci_probe(struct platform_device *pdev) | |||
| 618 | if (!cpu_is_pxa25x()) { | 620 | if (!cpu_is_pxa25x()) { |
| 619 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; | 621 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
| 620 | host->cmdat |= CMDAT_SDIO_INT_EN; | 622 | host->cmdat |= CMDAT_SDIO_INT_EN; |
| 621 | if (cpu_is_pxa300() || cpu_is_pxa310()) | 623 | if (mmc_has_26MHz()) |
| 622 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | | 624 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | |
| 623 | MMC_CAP_SD_HIGHSPEED; | 625 | MMC_CAP_SD_HIGHSPEED; |
| 624 | } | 626 | } |
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 2fda0b615246..8f8e87b7ed64 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig | |||
| @@ -358,7 +358,7 @@ endchoice | |||
| 358 | 358 | ||
| 359 | config MTD_NAND_PXA3xx | 359 | config MTD_NAND_PXA3xx |
| 360 | tristate "Support for NAND flash devices on PXA3xx" | 360 | tristate "Support for NAND flash devices on PXA3xx" |
| 361 | depends on MTD_NAND && PXA3xx | 361 | depends on MTD_NAND && (PXA3xx || ARCH_MMP) |
| 362 | help | 362 | help |
| 363 | This enables the driver for the NAND flash device found on | 363 | This enables the driver for the NAND flash device found on |
| 364 | PXA3xx processors | 364 | PXA3xx processors |
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 6ea520ae2410..1a5a0365c983 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c | |||
| @@ -9,6 +9,7 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/kernel.h> | ||
| 12 | #include <linux/module.h> | 13 | #include <linux/module.h> |
| 13 | #include <linux/interrupt.h> | 14 | #include <linux/interrupt.h> |
| 14 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| @@ -22,7 +23,7 @@ | |||
| 22 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
| 23 | 24 | ||
| 24 | #include <mach/dma.h> | 25 | #include <mach/dma.h> |
| 25 | #include <mach/pxa3xx_nand.h> | 26 | #include <plat/pxa3xx_nand.h> |
| 26 | 27 | ||
| 27 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | 28 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) |
| 28 | 29 | ||
| @@ -84,10 +85,6 @@ | |||
| 84 | #define NDCB0_CMD1_MASK (0xff) | 85 | #define NDCB0_CMD1_MASK (0xff) |
| 85 | #define NDCB0_ADDR_CYC_SHIFT (16) | 86 | #define NDCB0_ADDR_CYC_SHIFT (16) |
| 86 | 87 | ||
| 87 | /* dma-able I/O address for the NAND data and commands */ | ||
| 88 | #define NDCB0_DMA_ADDR (0x43100048) | ||
| 89 | #define NDDB_DMA_ADDR (0x43100040) | ||
| 90 | |||
| 91 | /* macros for registers read/write */ | 88 | /* macros for registers read/write */ |
| 92 | #define nand_writel(info, off, val) \ | 89 | #define nand_writel(info, off, val) \ |
| 93 | __raw_writel((val), (info)->mmio_base + (off)) | 90 | __raw_writel((val), (info)->mmio_base + (off)) |
| @@ -123,6 +120,7 @@ struct pxa3xx_nand_info { | |||
| 123 | 120 | ||
| 124 | struct clk *clk; | 121 | struct clk *clk; |
| 125 | void __iomem *mmio_base; | 122 | void __iomem *mmio_base; |
| 123 | unsigned long mmio_phys; | ||
| 126 | 124 | ||
| 127 | unsigned int buf_start; | 125 | unsigned int buf_start; |
| 128 | unsigned int buf_count; | 126 | unsigned int buf_count; |
| @@ -228,13 +226,35 @@ static struct pxa3xx_nand_flash samsung512MbX16 = { | |||
| 228 | .chip_id = 0x46ec, | 226 | .chip_id = 0x46ec, |
| 229 | }; | 227 | }; |
| 230 | 228 | ||
| 229 | static struct pxa3xx_nand_flash samsung2GbX8 = { | ||
| 230 | .timing = &samsung512MbX16_timing, | ||
| 231 | .cmdset = &smallpage_cmdset, | ||
| 232 | .page_per_block = 64, | ||
| 233 | .page_size = 2048, | ||
| 234 | .flash_width = 8, | ||
| 235 | .dfc_width = 8, | ||
| 236 | .num_blocks = 2048, | ||
| 237 | .chip_id = 0xdaec, | ||
| 238 | }; | ||
| 239 | |||
| 240 | static struct pxa3xx_nand_flash samsung32GbX8 = { | ||
| 241 | .timing = &samsung512MbX16_timing, | ||
| 242 | .cmdset = &smallpage_cmdset, | ||
| 243 | .page_per_block = 128, | ||
| 244 | .page_size = 4096, | ||
| 245 | .flash_width = 8, | ||
| 246 | .dfc_width = 8, | ||
| 247 | .num_blocks = 8192, | ||
| 248 | .chip_id = 0xd7ec, | ||
| 249 | }; | ||
| 250 | |||
| 231 | static struct pxa3xx_nand_timing micron_timing = { | 251 | static struct pxa3xx_nand_timing micron_timing = { |
| 232 | .tCH = 10, | 252 | .tCH = 10, |
| 233 | .tCS = 25, | 253 | .tCS = 25, |
| 234 | .tWH = 15, | 254 | .tWH = 15, |
| 235 | .tWP = 25, | 255 | .tWP = 25, |
| 236 | .tRH = 15, | 256 | .tRH = 15, |
| 237 | .tRP = 25, | 257 | .tRP = 30, |
| 238 | .tR = 25000, | 258 | .tR = 25000, |
| 239 | .tWHR = 60, | 259 | .tWHR = 60, |
| 240 | .tAR = 10, | 260 | .tAR = 10, |
| @@ -262,6 +282,28 @@ static struct pxa3xx_nand_flash micron1GbX16 = { | |||
| 262 | .chip_id = 0xb12c, | 282 | .chip_id = 0xb12c, |
| 263 | }; | 283 | }; |
| 264 | 284 | ||
| 285 | static struct pxa3xx_nand_flash micron4GbX8 = { | ||
| 286 | .timing = µn_timing, | ||
| 287 | .cmdset = &largepage_cmdset, | ||
| 288 | .page_per_block = 64, | ||
| 289 | .page_size = 2048, | ||
| 290 | .flash_width = 8, | ||
| 291 | .dfc_width = 8, | ||
| 292 | .num_blocks = 4096, | ||
| 293 | .chip_id = 0xdc2c, | ||
| 294 | }; | ||
| 295 | |||
| 296 | static struct pxa3xx_nand_flash micron4GbX16 = { | ||
| 297 | .timing = µn_timing, | ||
| 298 | .cmdset = &largepage_cmdset, | ||
| 299 | .page_per_block = 64, | ||
| 300 | .page_size = 2048, | ||
| 301 | .flash_width = 16, | ||
| 302 | .dfc_width = 16, | ||
| 303 | .num_blocks = 4096, | ||
| 304 | .chip_id = 0xcc2c, | ||
| 305 | }; | ||
| 306 | |||
| 265 | static struct pxa3xx_nand_timing stm2GbX16_timing = { | 307 | static struct pxa3xx_nand_timing stm2GbX16_timing = { |
| 266 | .tCH = 10, | 308 | .tCH = 10, |
| 267 | .tCS = 35, | 309 | .tCS = 35, |
| @@ -287,8 +329,12 @@ static struct pxa3xx_nand_flash stm2GbX16 = { | |||
| 287 | 329 | ||
| 288 | static struct pxa3xx_nand_flash *builtin_flash_types[] = { | 330 | static struct pxa3xx_nand_flash *builtin_flash_types[] = { |
| 289 | &samsung512MbX16, | 331 | &samsung512MbX16, |
| 332 | &samsung2GbX8, | ||
| 333 | &samsung32GbX8, | ||
| 290 | µn1GbX8, | 334 | µn1GbX8, |
| 291 | µn1GbX16, | 335 | µn1GbX16, |
| 336 | µn4GbX8, | ||
| 337 | µn4GbX16, | ||
| 292 | &stm2GbX16, | 338 | &stm2GbX16, |
| 293 | }; | 339 | }; |
| 294 | #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */ | 340 | #endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */ |
| @@ -489,7 +535,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info) | |||
| 489 | switch (info->state) { | 535 | switch (info->state) { |
| 490 | case STATE_PIO_WRITING: | 536 | case STATE_PIO_WRITING: |
| 491 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, | 537 | __raw_writesl(info->mmio_base + NDDB, info->data_buff, |
| 492 | info->data_size << 2); | 538 | DIV_ROUND_UP(info->data_size, 4)); |
| 493 | 539 | ||
| 494 | enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD); | 540 | enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD); |
| 495 | 541 | ||
| @@ -501,7 +547,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info) | |||
| 501 | break; | 547 | break; |
| 502 | case STATE_PIO_READING: | 548 | case STATE_PIO_READING: |
| 503 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, | 549 | __raw_readsl(info->mmio_base + NDDB, info->data_buff, |
| 504 | info->data_size << 2); | 550 | DIV_ROUND_UP(info->data_size, 4)); |
| 505 | break; | 551 | break; |
| 506 | default: | 552 | default: |
| 507 | printk(KERN_ERR "%s: invalid state %d\n", __func__, | 553 | printk(KERN_ERR "%s: invalid state %d\n", __func__, |
| @@ -523,11 +569,11 @@ static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out) | |||
| 523 | 569 | ||
| 524 | if (dir_out) { | 570 | if (dir_out) { |
| 525 | desc->dsadr = info->data_buff_phys; | 571 | desc->dsadr = info->data_buff_phys; |
| 526 | desc->dtadr = NDDB_DMA_ADDR; | 572 | desc->dtadr = info->mmio_phys + NDDB; |
| 527 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; | 573 | desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG; |
| 528 | } else { | 574 | } else { |
| 529 | desc->dtadr = info->data_buff_phys; | 575 | desc->dtadr = info->data_buff_phys; |
| 530 | desc->dsadr = NDDB_DMA_ADDR; | 576 | desc->dsadr = info->mmio_phys + NDDB; |
| 531 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; | 577 | desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; |
| 532 | } | 578 | } |
| 533 | 579 | ||
| @@ -669,6 +715,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, | |||
| 669 | /* disable HW ECC to get all the OOB data */ | 715 | /* disable HW ECC to get all the OOB data */ |
| 670 | info->buf_count = mtd->writesize + mtd->oobsize; | 716 | info->buf_count = mtd->writesize + mtd->oobsize; |
| 671 | info->buf_start = mtd->writesize + column; | 717 | info->buf_start = mtd->writesize + column; |
| 718 | memset(info->data_buff, 0xFF, info->buf_count); | ||
| 672 | 719 | ||
| 673 | if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr)) | 720 | if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr)) |
| 674 | break; | 721 | break; |
| @@ -1239,13 +1286,17 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) | |||
| 1239 | ret = -ENODEV; | 1286 | ret = -ENODEV; |
| 1240 | goto fail_free_res; | 1287 | goto fail_free_res; |
| 1241 | } | 1288 | } |
| 1289 | info->mmio_phys = r->start; | ||
| 1242 | 1290 | ||
| 1243 | ret = pxa3xx_nand_init_buff(info); | 1291 | ret = pxa3xx_nand_init_buff(info); |
| 1244 | if (ret) | 1292 | if (ret) |
| 1245 | goto fail_free_io; | 1293 | goto fail_free_io; |
| 1246 | 1294 | ||
| 1247 | ret = request_irq(IRQ_NAND, pxa3xx_nand_irq, IRQF_DISABLED, | 1295 | /* initialize all interrupts to be disabled */ |
| 1248 | pdev->name, info); | 1296 | disable_int(info, NDSR_MASK); |
| 1297 | |||
| 1298 | ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED, | ||
| 1299 | pdev->name, info); | ||
| 1249 | if (ret < 0) { | 1300 | if (ret < 0) { |
| 1250 | dev_err(&pdev->dev, "failed to request IRQ\n"); | 1301 | dev_err(&pdev->dev, "failed to request IRQ\n"); |
| 1251 | goto fail_free_buf; | 1302 | goto fail_free_buf; |
| @@ -1271,7 +1322,7 @@ static int pxa3xx_nand_probe(struct platform_device *pdev) | |||
| 1271 | return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); | 1322 | return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts); |
| 1272 | 1323 | ||
| 1273 | fail_free_irq: | 1324 | fail_free_irq: |
| 1274 | free_irq(IRQ_NAND, info); | 1325 | free_irq(irq, info); |
| 1275 | fail_free_buf: | 1326 | fail_free_buf: |
| 1276 | if (use_dma) { | 1327 | if (use_dma) { |
| 1277 | pxa_free_dma(info->data_dma_ch); | 1328 | pxa_free_dma(info->data_dma_ch); |
| @@ -1296,12 +1347,15 @@ static int pxa3xx_nand_remove(struct platform_device *pdev) | |||
| 1296 | struct mtd_info *mtd = platform_get_drvdata(pdev); | 1347 | struct mtd_info *mtd = platform_get_drvdata(pdev); |
| 1297 | struct pxa3xx_nand_info *info = mtd->priv; | 1348 | struct pxa3xx_nand_info *info = mtd->priv; |
| 1298 | struct resource *r; | 1349 | struct resource *r; |
| 1350 | int irq; | ||
| 1299 | 1351 | ||
| 1300 | platform_set_drvdata(pdev, NULL); | 1352 | platform_set_drvdata(pdev, NULL); |
| 1301 | 1353 | ||
| 1302 | del_mtd_device(mtd); | 1354 | del_mtd_device(mtd); |
| 1303 | del_mtd_partitions(mtd); | 1355 | del_mtd_partitions(mtd); |
| 1304 | free_irq(IRQ_NAND, info); | 1356 | irq = platform_get_irq(pdev, 0); |
| 1357 | if (irq >= 0) | ||
| 1358 | free_irq(irq, info); | ||
| 1305 | if (use_dma) { | 1359 | if (use_dma) { |
| 1306 | pxa_free_dma(info->data_dma_ch); | 1360 | pxa_free_dma(info->data_dma_ch); |
| 1307 | dma_free_writecombine(&pdev->dev, info->data_buff_size, | 1361 | dma_free_writecombine(&pdev->dev, info->data_buff_size, |
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 3c20dae43ce2..e11e1cda4ba2 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig | |||
| @@ -780,7 +780,7 @@ config RTC_DRV_TX4939 | |||
| 780 | 780 | ||
| 781 | config RTC_DRV_MV | 781 | config RTC_DRV_MV |
| 782 | tristate "Marvell SoC RTC" | 782 | tristate "Marvell SoC RTC" |
| 783 | depends on ARCH_KIRKWOOD | 783 | depends on ARCH_KIRKWOOD || ARCH_DOVE |
| 784 | help | 784 | help |
| 785 | If you say yes here you will get support for the in-chip RTC | 785 | If you say yes here you will get support for the in-chip RTC |
| 786 | that can be found in some of Marvell's SoC devices, such as | 786 | that can be found in some of Marvell's SoC devices, such as |
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c index c99f0821cae3..73f089d3efd6 100644 --- a/drivers/serial/s3c2410.c +++ b/drivers/serial/s3c2410.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * | 2 | * |
| 3 | * Driver for Samsung S3C2410 SoC onboard UARTs. | 3 | * Driver for Samsung S3C2410 SoC onboard UARTs. |
| 4 | * | 4 | * |
| 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/serial/s3c2412.c b/drivers/serial/s3c2412.c index 6e057d8809d3..ce75e28e36ef 100644 --- a/drivers/serial/s3c2412.c +++ b/drivers/serial/s3c2412.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * | 2 | * |
| 3 | * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs. | 3 | * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs. |
| 4 | * | 4 | * |
| 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/serial/s3c2440.c b/drivers/serial/s3c2440.c index 69ff5d340f04..094cc3904b13 100644 --- a/drivers/serial/s3c2440.c +++ b/drivers/serial/s3c2440.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * | 2 | * |
| 3 | * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs. | 3 | * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs. |
| 4 | * | 4 | * |
| 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/serial/s3c24a0.c b/drivers/serial/s3c24a0.c index 26c49e18bdd1..fad6083ca427 100644 --- a/drivers/serial/s3c24a0.c +++ b/drivers/serial/s3c24a0.c | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * | 6 | * |
| 7 | * Author: Sandeep Patil <sandeep.patil@azingo.com> | 7 | * Author: Sandeep Patil <sandeep.patil@azingo.com> |
| 8 | * | 8 | * |
| 9 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 9 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 10 | * http://armlinux.simtec.co.uk/ | 10 | * http://armlinux.simtec.co.uk/ |
| 11 | * | 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 12 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index 1523e8d9ae77..52e3df113ec0 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * | 2 | * |
| 3 | * Driver core for Samsung SoC onboard UARTs. | 3 | * Driver core for Samsung SoC onboard UARTs. |
| 4 | * | 4 | * |
| 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h index d3fe315969f6..1fb22343df42 100644 --- a/drivers/serial/samsung.h +++ b/drivers/serial/samsung.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * | 2 | * |
| 3 | * Driver for Samsung SoC onboard UARTs. | 3 | * Driver for Samsung SoC onboard UARTs. |
| 4 | * | 4 | * |
| 5 | * Ben Dooks, Copyright (c) 2003-2005,2008 Simtec Electronics | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
| 6 | * http://armlinux.simtec.co.uk/ | 6 | * http://armlinux.simtec.co.uk/ |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 188e1ba3b69f..6b89eb55ed32 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
| @@ -5,6 +5,9 @@ | |||
| 5 | menu "Graphics support" | 5 | menu "Graphics support" |
| 6 | depends on HAS_IOMEM | 6 | depends on HAS_IOMEM |
| 7 | 7 | ||
| 8 | config HAVE_FB_ATMEL | ||
| 9 | bool | ||
| 10 | |||
| 8 | source "drivers/char/agp/Kconfig" | 11 | source "drivers/char/agp/Kconfig" |
| 9 | 12 | ||
| 10 | source "drivers/gpu/vga/Kconfig" | 13 | source "drivers/gpu/vga/Kconfig" |
| @@ -937,7 +940,7 @@ config FB_S1D13XXX | |||
| 937 | 940 | ||
| 938 | config FB_ATMEL | 941 | config FB_ATMEL |
| 939 | tristate "AT91/AT32 LCD Controller support" | 942 | tristate "AT91/AT32 LCD Controller support" |
| 940 | depends on FB && (ARCH_AT91SAM9261 || ARCH_AT91SAM9G10 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 || AVR32) | 943 | depends on FB && HAVE_FB_ATMEL |
| 941 | select FB_CFB_FILLRECT | 944 | select FB_CFB_FILLRECT |
| 942 | select FB_CFB_COPYAREA | 945 | select FB_CFB_COPYAREA |
| 943 | select FB_CFB_IMAGEBLIT | 946 | select FB_CFB_IMAGEBLIT |
diff --git a/drivers/video/backlight/da903x_bl.c b/drivers/video/backlight/da903x_bl.c index 701a1081e199..7fcb0eb54c60 100644 --- a/drivers/video/backlight/da903x_bl.c +++ b/drivers/video/backlight/da903x_bl.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #define DA9034_WLED_CONTROL1 0x3C | 26 | #define DA9034_WLED_CONTROL1 0x3C |
| 27 | #define DA9034_WLED_CONTROL2 0x3D | 27 | #define DA9034_WLED_CONTROL2 0x3D |
| 28 | #define DA9034_WLED_ISET(x) ((x) & 0x1f) | ||
| 28 | 29 | ||
| 29 | #define DA9034_WLED_BOOST_EN (1 << 5) | 30 | #define DA9034_WLED_BOOST_EN (1 << 5) |
| 30 | 31 | ||
| @@ -101,6 +102,7 @@ static struct backlight_ops da903x_backlight_ops = { | |||
| 101 | 102 | ||
| 102 | static int da903x_backlight_probe(struct platform_device *pdev) | 103 | static int da903x_backlight_probe(struct platform_device *pdev) |
| 103 | { | 104 | { |
| 105 | struct da9034_backlight_pdata *pdata = pdev->dev.platform_data; | ||
| 104 | struct da903x_backlight_data *data; | 106 | struct da903x_backlight_data *data; |
| 105 | struct backlight_device *bl; | 107 | struct backlight_device *bl; |
| 106 | int max_brightness; | 108 | int max_brightness; |
| @@ -127,6 +129,11 @@ static int da903x_backlight_probe(struct platform_device *pdev) | |||
| 127 | data->da903x_dev = pdev->dev.parent; | 129 | data->da903x_dev = pdev->dev.parent; |
| 128 | data->current_brightness = 0; | 130 | data->current_brightness = 0; |
| 129 | 131 | ||
| 132 | /* adjust the WLED output current */ | ||
| 133 | if (pdata) | ||
| 134 | da903x_write(data->da903x_dev, DA9034_WLED_CONTROL2, | ||
| 135 | DA9034_WLED_ISET(pdata->output_current)); | ||
| 136 | |||
| 130 | bl = backlight_device_register(pdev->name, data->da903x_dev, | 137 | bl = backlight_device_register(pdev->name, data->da903x_dev, |
| 131 | data, &da903x_backlight_ops); | 138 | data, &da903x_backlight_ops); |
| 132 | if (IS_ERR(bl)) { | 139 | if (IS_ERR(bl)) { |
diff --git a/drivers/video/backlight/tdo24m.c b/drivers/video/backlight/tdo24m.c index bbfb502add67..4a3d46e08016 100644 --- a/drivers/video/backlight/tdo24m.c +++ b/drivers/video/backlight/tdo24m.c | |||
| @@ -367,6 +367,7 @@ static int __devinit tdo24m_probe(struct spi_device *spi) | |||
| 367 | 367 | ||
| 368 | spi_message_init(m); | 368 | spi_message_init(m); |
| 369 | 369 | ||
| 370 | x->cs_change = 1; | ||
| 370 | x->tx_buf = &lcd->buf[0]; | 371 | x->tx_buf = &lcd->buf[0]; |
| 371 | spi_message_add_tail(x, m); | 372 | spi_message_add_tail(x, m); |
| 372 | 373 | ||
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c index 84d8327e47db..75285d3f393c 100644 --- a/drivers/video/pxa168fb.c +++ b/drivers/video/pxa168fb.c | |||
| @@ -687,6 +687,7 @@ static int __init pxa168fb_probe(struct platform_device *pdev) | |||
| 687 | } | 687 | } |
| 688 | 688 | ||
| 689 | info->fix.smem_start = (unsigned long)fbi->fb_start_dma; | 689 | info->fix.smem_start = (unsigned long)fbi->fb_start_dma; |
| 690 | set_graphics_start(info, 0, 0); | ||
| 690 | 691 | ||
| 691 | /* | 692 | /* |
| 692 | * Set video mode according to platform data. | 693 | * Set video mode according to platform data. |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 1820c4a24434..f58a3aae6ea6 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
| @@ -80,7 +80,8 @@ | |||
| 80 | static int pxafb_activate_var(struct fb_var_screeninfo *var, | 80 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
| 81 | struct pxafb_info *); | 81 | struct pxafb_info *); |
| 82 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); | 82 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); |
| 83 | static void setup_base_frame(struct pxafb_info *fbi, int branch); | 83 | static void setup_base_frame(struct pxafb_info *fbi, |
| 84 | struct fb_var_screeninfo *var, int branch); | ||
| 84 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, | 85 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, |
| 85 | unsigned long offset, size_t size); | 86 | unsigned long offset, size_t size); |
| 86 | 87 | ||
| @@ -397,6 +398,7 @@ static void pxafb_setmode(struct fb_var_screeninfo *var, | |||
| 397 | var->lower_margin = mode->lower_margin; | 398 | var->lower_margin = mode->lower_margin; |
| 398 | var->sync = mode->sync; | 399 | var->sync = mode->sync; |
| 399 | var->grayscale = mode->cmap_greyscale; | 400 | var->grayscale = mode->cmap_greyscale; |
| 401 | var->transp.length = mode->transparency; | ||
| 400 | 402 | ||
| 401 | /* set the initial RGBA bitfields */ | 403 | /* set the initial RGBA bitfields */ |
| 402 | pxafb_set_pixfmt(var, mode->depth); | 404 | pxafb_set_pixfmt(var, mode->depth); |
| @@ -531,12 +533,22 @@ static int pxafb_pan_display(struct fb_var_screeninfo *var, | |||
| 531 | struct fb_info *info) | 533 | struct fb_info *info) |
| 532 | { | 534 | { |
| 533 | struct pxafb_info *fbi = (struct pxafb_info *)info; | 535 | struct pxafb_info *fbi = (struct pxafb_info *)info; |
| 536 | struct fb_var_screeninfo newvar; | ||
| 534 | int dma = DMA_MAX + DMA_BASE; | 537 | int dma = DMA_MAX + DMA_BASE; |
| 535 | 538 | ||
| 536 | if (fbi->state != C_ENABLE) | 539 | if (fbi->state != C_ENABLE) |
| 537 | return 0; | 540 | return 0; |
| 538 | 541 | ||
| 539 | setup_base_frame(fbi, 1); | 542 | /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what |
| 543 | * was passed in and copy the rest from the old screeninfo. | ||
| 544 | */ | ||
| 545 | memcpy(&newvar, &fbi->fb.var, sizeof(newvar)); | ||
| 546 | newvar.xoffset = var->xoffset; | ||
| 547 | newvar.yoffset = var->yoffset; | ||
| 548 | newvar.vmode &= ~FB_VMODE_YWRAP; | ||
| 549 | newvar.vmode |= var->vmode & FB_VMODE_YWRAP; | ||
| 550 | |||
| 551 | setup_base_frame(fbi, &newvar, 1); | ||
| 540 | 552 | ||
| 541 | if (fbi->lccr0 & LCCR0_SDS) | 553 | if (fbi->lccr0 & LCCR0_SDS) |
| 542 | lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); | 554 | lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1); |
| @@ -1052,9 +1064,10 @@ static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, | |||
| 1052 | return 0; | 1064 | return 0; |
| 1053 | } | 1065 | } |
| 1054 | 1066 | ||
| 1055 | static void setup_base_frame(struct pxafb_info *fbi, int branch) | 1067 | static void setup_base_frame(struct pxafb_info *fbi, |
| 1068 | struct fb_var_screeninfo *var, | ||
| 1069 | int branch) | ||
| 1056 | { | 1070 | { |
| 1057 | struct fb_var_screeninfo *var = &fbi->fb.var; | ||
| 1058 | struct fb_fix_screeninfo *fix = &fbi->fb.fix; | 1071 | struct fb_fix_screeninfo *fix = &fbi->fb.fix; |
| 1059 | int nbytes, dma, pal, bpp = var->bits_per_pixel; | 1072 | int nbytes, dma, pal, bpp = var->bits_per_pixel; |
| 1060 | unsigned long offset; | 1073 | unsigned long offset; |
| @@ -1332,7 +1345,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, | |||
| 1332 | #endif | 1345 | #endif |
| 1333 | setup_parallel_timing(fbi, var); | 1346 | setup_parallel_timing(fbi, var); |
| 1334 | 1347 | ||
| 1335 | setup_base_frame(fbi, 0); | 1348 | setup_base_frame(fbi, var, 0); |
| 1336 | 1349 | ||
| 1337 | fbi->reg_lccr0 = fbi->lccr0 | | 1350 | fbi->reg_lccr0 = fbi->lccr0 | |
| 1338 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | | 1351 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | |
diff --git a/include/linux/mfd/da903x.h b/include/linux/mfd/da903x.h index c63b65c94429..0aa3a1a49ee3 100644 --- a/include/linux/mfd/da903x.h +++ b/include/linux/mfd/da903x.h | |||
| @@ -96,6 +96,10 @@ struct da9034_touch_pdata { | |||
| 96 | int y_inverted; | 96 | int y_inverted; |
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | struct da9034_backlight_pdata { | ||
| 100 | int output_current; /* output current of WLED, from 0-31 (in mA) */ | ||
| 101 | }; | ||
| 102 | |||
| 99 | /* DA9030 battery charger data */ | 103 | /* DA9030 battery charger data */ |
| 100 | struct power_supply_info; | 104 | struct power_supply_info; |
| 101 | 105 | ||
diff --git a/include/video/pxa168fb.h b/include/video/pxa168fb.h index b5cc72fe0461..8c2f385a90ea 100644 --- a/include/video/pxa168fb.h +++ b/include/video/pxa168fb.h | |||
| @@ -117,8 +117,6 @@ struct pxa168fb_mach_info { | |||
| 117 | unsigned invert_composite_blank:1; | 117 | unsigned invert_composite_blank:1; |
| 118 | unsigned invert_pix_val_ena:1; | 118 | unsigned invert_pix_val_ena:1; |
| 119 | unsigned invert_pixclock:1; | 119 | unsigned invert_pixclock:1; |
| 120 | unsigned invert_vsync:1; | ||
| 121 | unsigned invert_hsync:1; | ||
| 122 | unsigned panel_rbswap:1; | 120 | unsigned panel_rbswap:1; |
| 123 | unsigned active:1; | 121 | unsigned active:1; |
| 124 | unsigned enable_lcd:1; | 122 | unsigned enable_lcd:1; |