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authorTony Lindgren <tony@atomide.com>2011-03-09 16:15:49 -0500
committerTony Lindgren <tony@atomide.com>2011-03-09 16:15:49 -0500
commit0dde52a9f5330eec240660191a94b51bd911ffcd (patch)
treeebd79ab294ac6fcda5e38a6f990f7c0a34283e37
parentc39bee8ac4aca750c85609ba0847599b36feb693 (diff)
parent2722e56de60390969cf118933842b3f2f3c8d6b8 (diff)
Merge branch 'omap-l3-for-next' of git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into omap-for-linus
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/devices.c64
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c22
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c38
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c253
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h132
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c314
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h338
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h2
9 files changed, 1165 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 1c3635d7f4cf..8ef8711eac94 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -135,6 +135,10 @@ obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
135# EMU peripherals 135# EMU peripherals
136obj-$(CONFIG_OMAP3_EMU) += emu.o 136obj-$(CONFIG_OMAP3_EMU) += emu.o
137 137
138# L3 interconnect
139obj-$(CONFIG_ARCH_OMAP3) += omap_l3_smx.o
140obj-$(CONFIG_ARCH_OMAP4) += omap_l3_noc.o
141
138obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o 142obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
139mailbox_mach-objs := mailbox.o 143mailbox_mach-objs := mailbox.o
140 144
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2cb720b5b12e..0d2d6a9c303c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -36,6 +36,70 @@
36#include "mux.h" 36#include "mux.h"
37#include "control.h" 37#include "control.h"
38 38
39#define L3_MODULES_MAX_LEN 12
40#define L3_MODULES 3
41
42static int __init omap3_l3_init(void)
43{
44 int l;
45 struct omap_hwmod *oh;
46 struct omap_device *od;
47 char oh_name[L3_MODULES_MAX_LEN];
48
49 /*
50 * To avoid code running on other OMAPs in
51 * multi-omap builds
52 */
53 if (!(cpu_is_omap34xx()))
54 return -ENODEV;
55
56 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
57
58 oh = omap_hwmod_lookup(oh_name);
59
60 if (!oh)
61 pr_err("could not look up %s\n", oh_name);
62
63 od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
64 NULL, 0, 0);
65
66 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
67
68 return PTR_ERR(od);
69}
70postcore_initcall(omap3_l3_init);
71
72static int __init omap4_l3_init(void)
73{
74 int l, i;
75 struct omap_hwmod *oh[3];
76 struct omap_device *od;
77 char oh_name[L3_MODULES_MAX_LEN];
78
79 /*
80 * To avoid code running on other OMAPs in
81 * multi-omap builds
82 */
83 if (!(cpu_is_omap44xx()))
84 return -ENODEV;
85
86 for (i = 0; i < L3_MODULES; i++) {
87 l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
88
89 oh[i] = omap_hwmod_lookup(oh_name);
90 if (!(oh[i]))
91 pr_err("could not look up %s\n", oh_name);
92 }
93
94 od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
95 0, NULL, 0, 0);
96
97 WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
98
99 return PTR_ERR(od);
100}
101postcore_initcall(omap4_l3_init);
102
39#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) 103#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
40 104
41static struct resource cam_resources[] = { 105static struct resource cam_resources[] = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index eb48b8c7723c..c4ca005f8bb5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -100,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
100 .user = OCP_USER_MPU | OCP_USER_SDMA, 100 .user = OCP_USER_MPU | OCP_USER_SDMA,
101}; 101};
102 102
103/* L3 taret configuration and error log registers */
104static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
105 { .irq = INT_34XX_L3_DBG_IRQ },
106 { .irq = INT_34XX_L3_APP_IRQ },
107};
108
109static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
110 {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
114 },
115};
116
103/* MPU -> L3 interface */ 117/* MPU -> L3 interface */
104static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = { 118static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
105 .master = &omap3xxx_mpu_hwmod, 119 .master = &omap3xxx_mpu_hwmod,
106 .slave = &omap3xxx_l3_main_hwmod, 120 .slave = &omap3xxx_l3_main_hwmod,
121 .addr = omap3xxx_l3_main_addrs,
122 .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
107 .user = OCP_USER_MPU, 123 .user = OCP_USER_MPU,
108}; 124};
109 125
@@ -135,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
135static struct omap_hwmod omap3xxx_l3_main_hwmod = { 151static struct omap_hwmod omap3xxx_l3_main_hwmod = {
136 .name = "l3_main", 152 .name = "l3_main",
137 .class = &l3_hwmod_class, 153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
138 .masters = omap3xxx_l3_main_masters, 156 .masters = omap3xxx_l3_main_masters,
139 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters), 157 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
140 .slaves = omap3xxx_l3_main_slaves, 158 .slaves = omap3xxx_l3_main_slaves,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7b72316781da..3e88dd3f8ef3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -264,11 +264,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
264 .user = OCP_USER_MPU | OCP_USER_SDMA, 264 .user = OCP_USER_MPU | OCP_USER_SDMA,
265}; 265};
266 266
267/* L3 target configuration and error log registers */
268static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
269 { .irq = 9 + OMAP44XX_IRQ_GIC_START },
270 { .irq = 10 + OMAP44XX_IRQ_GIC_START },
271};
272
273static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
274 {
275 .pa_start = 0x44000000,
276 .pa_end = 0x44000fff,
277 .flags = ADDR_TYPE_RT,
278 },
279};
280
267/* mpu -> l3_main_1 */ 281/* mpu -> l3_main_1 */
268static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { 282static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
269 .master = &omap44xx_mpu_hwmod, 283 .master = &omap44xx_mpu_hwmod,
270 .slave = &omap44xx_l3_main_1_hwmod, 284 .slave = &omap44xx_l3_main_1_hwmod,
271 .clk = "l3_div_ck", 285 .clk = "l3_div_ck",
286 .addr = omap44xx_l3_main_1_addrs,
287 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
272 .user = OCP_USER_MPU | OCP_USER_SDMA, 288 .user = OCP_USER_MPU | OCP_USER_SDMA,
273}; 289};
274 290
@@ -286,6 +302,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
286static struct omap_hwmod omap44xx_l3_main_1_hwmod = { 302static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
287 .name = "l3_main_1", 303 .name = "l3_main_1",
288 .class = &omap44xx_l3_hwmod_class, 304 .class = &omap44xx_l3_hwmod_class,
305 .mpu_irqs = omap44xx_l3_targ_irqs,
306 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
289 .slaves = omap44xx_l3_main_1_slaves, 307 .slaves = omap44xx_l3_main_1_slaves,
290 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves), 308 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
291 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 309 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -332,11 +350,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
332 .user = OCP_USER_MPU | OCP_USER_SDMA, 350 .user = OCP_USER_MPU | OCP_USER_SDMA,
333}; 351};
334 352
353static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
354 {
355 .pa_start = 0x44800000,
356 .pa_end = 0x44801fff,
357 .flags = ADDR_TYPE_RT,
358 },
359};
360
335/* l3_main_1 -> l3_main_2 */ 361/* l3_main_1 -> l3_main_2 */
336static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { 362static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
337 .master = &omap44xx_l3_main_1_hwmod, 363 .master = &omap44xx_l3_main_1_hwmod,
338 .slave = &omap44xx_l3_main_2_hwmod, 364 .slave = &omap44xx_l3_main_2_hwmod,
339 .clk = "l3_div_ck", 365 .clk = "l3_div_ck",
366 .addr = omap44xx_l3_main_2_addrs,
367 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
340 .user = OCP_USER_MPU | OCP_USER_SDMA, 368 .user = OCP_USER_MPU | OCP_USER_SDMA,
341}; 369};
342 370
@@ -377,11 +405,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
377}; 405};
378 406
379/* l3_main_3 interface data */ 407/* l3_main_3 interface data */
408static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
409 {
410 .pa_start = 0x45000000,
411 .pa_end = 0x45000fff,
412 .flags = ADDR_TYPE_RT,
413 },
414};
415
380/* l3_main_1 -> l3_main_3 */ 416/* l3_main_1 -> l3_main_3 */
381static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { 417static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
382 .master = &omap44xx_l3_main_1_hwmod, 418 .master = &omap44xx_l3_main_1_hwmod,
383 .slave = &omap44xx_l3_main_3_hwmod, 419 .slave = &omap44xx_l3_main_3_hwmod,
384 .clk = "l3_div_ck", 420 .clk = "l3_div_ck",
421 .addr = omap44xx_l3_main_3_addrs,
422 .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
385 .user = OCP_USER_MPU | OCP_USER_SDMA, 423 .user = OCP_USER_MPU | OCP_USER_SDMA,
386}; 424};
387 425
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 000000000000..82632c24076f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,253 @@
1/*
2 * OMAP4XXX L3 Interconnect error handling driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#include <linux/init.h>
24#include <linux/io.h>
25#include <linux/platform_device.h>
26#include <linux/interrupt.h>
27#include <linux/kernel.h>
28#include <linux/slab.h>
29
30#include "omap_l3_noc.h"
31
32/*
33 * Interrupt Handler for L3 error detection.
34 * 1) Identify the L3 clockdomain partition to which the error belongs to.
35 * 2) Identify the slave where the error information is logged
36 * 3) Print the logged information.
37 * 4) Add dump stack to provide kernel trace.
38 *
39 * Two Types of errors :
40 * 1) Custom errors in L3 :
41 * Target like DMM/FW/EMIF generates SRESP=ERR error
42 * 2) Standard L3 error:
43 * - Unsupported CMD.
44 * L3 tries to access target while it is idle
45 * - OCP disconnect.
46 * - Address hole error:
47 * If DSS/ISS/FDIF/USBHOSTFS access a target where they
48 * do not have connectivity, the error is logged in
49 * their default target which is DMM2.
50 *
51 * On High Secure devices, firewall errors are possible and those
52 * can be trapped as well. But the trapping is implemented as part
53 * secure software and hence need not be implemented here.
54 */
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{
57
58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j;
60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg;
62 u32 base, slave_addr, clear;
63 char *source_name;
64
65 /* Get the Type of interrupt */
66 if (irq == l3->app_irq)
67 inttype = L3_APPLICATION_ERROR;
68 else
69 inttype = L3_DEBUG_ERROR;
70
71 for (i = 0; i < L3_MODULES; i++) {
72 /*
73 * Read the regerr register of the clock domain
74 * to determine the source
75 */
76 base = (u32)l3->l3_base[i];
77 err_reg = readl(base + l3_flagmux[i] + (inttype << 3));
78
79 /* Get the corresponding error and analyse */
80 if (err_reg) {
81 /* Identify the source from control status register */
82 for (j = 0; !(err_reg & (1 << j)); j++)
83 ;
84
85 err_src = j;
86 /* Read the stderrlog_main_source from clk domain */
87 std_err_main_addr = base + (*(l3_targ[i] + err_src));
88 std_err_main = readl(std_err_main_addr);
89
90 switch ((std_err_main & CUSTOM_ERROR)) {
91 case STANDARD_ERROR:
92 source_name =
93 l3_targ_stderrlog_main_name[i][err_src];
94
95 slave_addr = std_err_main_addr +
96 L3_SLAVE_ADDRESS_OFFSET;
97 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
98 source_name, readl(slave_addr));
99 /* clear the std error log*/
100 clear = std_err_main | CLEAR_STDERR_LOG;
101 writel(clear, std_err_main_addr);
102 break;
103
104 case CUSTOM_ERROR:
105 source_name =
106 l3_targ_stderrlog_main_name[i][err_src];
107
108 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
109 source_name);
110 /* clear the std error log*/
111 clear = std_err_main | CLEAR_STDERR_LOG;
112 writel(clear, std_err_main_addr);
113 break;
114
115 default:
116 /* Nothing to be handled here as of now */
117 break;
118 }
119 /* Error found so break the for loop */
120 break;
121 }
122 }
123 return IRQ_HANDLED;
124}
125
126static int __init omap4_l3_probe(struct platform_device *pdev)
127{
128 static struct omap4_l3 *l3;
129 struct resource *res;
130 int ret;
131 int irq;
132
133 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
134 if (!l3)
135 ret = -ENOMEM;
136
137 platform_set_drvdata(pdev, l3);
138 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
139 if (!res) {
140 dev_err(&pdev->dev, "couldn't find resource 0\n");
141 ret = -ENODEV;
142 goto err1;
143 }
144
145 l3->l3_base[0] = ioremap(res->start, resource_size(res));
146 if (!(l3->l3_base[0])) {
147 dev_err(&pdev->dev, "ioremap failed\n");
148 ret = -ENOMEM;
149 goto err2;
150 }
151
152 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
153 if (!res) {
154 dev_err(&pdev->dev, "couldn't find resource 1\n");
155 ret = -ENODEV;
156 goto err3;
157 }
158
159 l3->l3_base[1] = ioremap(res->start, resource_size(res));
160 if (!(l3->l3_base[1])) {
161 dev_err(&pdev->dev, "ioremap failed\n");
162 ret = -ENOMEM;
163 goto err4;
164 }
165
166 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
167 if (!res) {
168 dev_err(&pdev->dev, "couldn't find resource 2\n");
169 ret = -ENODEV;
170 goto err5;
171 }
172
173 l3->l3_base[2] = ioremap(res->start, resource_size(res));
174 if (!(l3->l3_base[2])) {
175 dev_err(&pdev->dev, "ioremap failed\n");
176 ret = -ENOMEM;
177 goto err6;
178 }
179
180 /*
181 * Setup interrupt Handlers
182 */
183 irq = platform_get_irq(pdev, 0);
184 ret = request_irq(irq,
185 l3_interrupt_handler,
186 IRQF_DISABLED, "l3-dbg-irq", l3);
187 if (ret) {
188 pr_crit("L3: request_irq failed to register for 0x%x\n",
189 OMAP44XX_IRQ_L3_DBG);
190 goto err7;
191 }
192 l3->debug_irq = irq;
193
194 irq = platform_get_irq(pdev, 1);
195 ret = request_irq(irq,
196 l3_interrupt_handler,
197 IRQF_DISABLED, "l3-app-irq", l3);
198 if (ret) {
199 pr_crit("L3: request_irq failed to register for 0x%x\n",
200 OMAP44XX_IRQ_L3_APP);
201 goto err8;
202 }
203 l3->app_irq = irq;
204
205 goto err0;
206err8:
207err7:
208 iounmap(l3->l3_base[2]);
209err6:
210err5:
211 iounmap(l3->l3_base[1]);
212err4:
213err3:
214 iounmap(l3->l3_base[0]);
215err2:
216err1:
217 kfree(l3);
218err0:
219 return ret;
220}
221
222static int __exit omap4_l3_remove(struct platform_device *pdev)
223{
224 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
225
226 free_irq(l3->app_irq, l3);
227 free_irq(l3->debug_irq, l3);
228 iounmap(l3->l3_base[0]);
229 iounmap(l3->l3_base[1]);
230 iounmap(l3->l3_base[2]);
231 kfree(l3);
232
233 return 0;
234}
235
236static struct platform_driver omap4_l3_driver = {
237 .remove = __exit_p(omap4_l3_remove),
238 .driver = {
239 .name = "omap_l3_noc",
240 },
241};
242
243static int __init omap4_l3_init(void)
244{
245 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
246}
247postcore_initcall_sync(omap4_l3_init);
248
249static void __exit omap4_l3_exit(void)
250{
251 platform_driver_unregister(&omap4_l3_driver);
252}
253module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 000000000000..359b83348aed
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
1 /*
2 * OMAP4XXX L3 Interconnect error handling driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA
22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1
39
40u32 l3_flagmux[L3_MODULES] = {
41 0x50C,
42 0x100C,
43 0X020C
44};
45
46/*
47 * L3 Target standard Error register offsets
48 */
49u32 l3_targ_stderrlog_main_clk1[] = {
50 0x148, /* DMM1 */
51 0x248, /* DMM2 */
52 0x348, /* ABE */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55};
56
57u32 l3_targ_stderrlog_main_clk2[] = {
58 0x548, /* CORTEX M3 */
59 0x348, /* DSS */
60 0x148, /* GPMC */
61 0x448, /* ISS */
62 0x748, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/
65 0x248, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */
68 0x848, /* SL2 */
69 0x1648, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */
74 0xA48, /* L4 PER1*/
75 0xB48 /* L4 PER2*/
76};
77
78u32 l3_targ_stderrlog_main_clk3[] = {
79 0x0148 /* EMUSS */
80};
81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
83 {
84 "DMM1",
85 "DMM2",
86 "ABE",
87 "L4CFG",
88 "CLK2 PWR DISC",
89 },
90 {
91 "CORTEX M3" ,
92 "DSS ",
93 "GPMC ",
94 "ISS ",
95 "IVAHD ",
96 "AES1",
97 "L4 PER0",
98 "OCMRAM ",
99 "GPMC sERROR",
100 "SGX ",
101 "SL2 ",
102 "C2C ",
103 "PWR DISC CLK1",
104 "SHA1",
105 "AES2",
106 "L4 PER3",
107 "L4 PER1",
108 "L4 PER2",
109 },
110 {
111 "EMUSS",
112 },
113};
114
115u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1,
117 l3_targ_stderrlog_main_clk2,
118 l3_targ_stderrlog_main_clk3,
119};
120
121struct omap4_l3 {
122 struct device *dev;
123 struct clk *ick;
124
125 /* memory base */
126 void __iomem *l3_base[4];
127
128 int debug_irq;
129 int app_irq;
130};
131
132#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 000000000000..265bff3acb9e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,314 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include "omap_l3_smx.h"
31
32static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
33{
34 return __raw_readll(base + reg);
35}
36
37static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
38{
39 __raw_writell(value, base + reg);
40}
41
42static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
43{
44 return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
45}
46
47static inline u32 omap3_l3_decode_addr(u64 error_addr)
48{
49 return error_addr & 0xffffffff;
50}
51
52static inline unsigned omap3_l3_decode_cmd(u64 error)
53{
54 return (error & 0x07) >> L3_ERROR_LOG_CMD;
55}
56
57static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
58{
59 return (error & 0xff00) >> L3_ERROR_LOG_INITID;
60}
61
62static inline unsigned omap3_l3_decode_req_info(u64 error)
63{
64 return (error >> 32) & 0xffff;
65}
66
67static char *omap3_l3_code_string(u8 code)
68{
69 switch (code) {
70 case OMAP_L3_CODE_NOERROR:
71 return "No Error";
72 case OMAP_L3_CODE_UNSUP_CMD:
73 return "Unsupported Command";
74 case OMAP_L3_CODE_ADDR_HOLE:
75 return "Address Hole";
76 case OMAP_L3_CODE_PROTECT_VIOLATION:
77 return "Protection Violation";
78 case OMAP_L3_CODE_IN_BAND_ERR:
79 return "In-band Error";
80 case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
81 return "Request Timeout Not Accepted";
82 case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
83 return "Request Timeout, no response";
84 default:
85 return "UNKNOWN error";
86 }
87}
88
89static char *omap3_l3_initiator_string(u8 initid)
90{
91 switch (initid) {
92 case OMAP_L3_LCD:
93 return "LCD";
94 case OMAP_L3_SAD2D:
95 return "SAD2D";
96 case OMAP_L3_IA_MPU_SS_1:
97 case OMAP_L3_IA_MPU_SS_2:
98 case OMAP_L3_IA_MPU_SS_3:
99 case OMAP_L3_IA_MPU_SS_4:
100 case OMAP_L3_IA_MPU_SS_5:
101 return "MPU";
102 case OMAP_L3_IA_IVA_SS_1:
103 case OMAP_L3_IA_IVA_SS_2:
104 case OMAP_L3_IA_IVA_SS_3:
105 return "IVA_SS";
106 case OMAP_L3_IA_IVA_SS_DMA_1:
107 case OMAP_L3_IA_IVA_SS_DMA_2:
108 case OMAP_L3_IA_IVA_SS_DMA_3:
109 case OMAP_L3_IA_IVA_SS_DMA_4:
110 case OMAP_L3_IA_IVA_SS_DMA_5:
111 case OMAP_L3_IA_IVA_SS_DMA_6:
112 return "IVA_SS_DMA";
113 case OMAP_L3_IA_SGX:
114 return "SGX";
115 case OMAP_L3_IA_CAM_1:
116 case OMAP_L3_IA_CAM_2:
117 case OMAP_L3_IA_CAM_3:
118 return "CAM";
119 case OMAP_L3_IA_DAP:
120 return "DAP";
121 case OMAP_L3_SDMA_WR_1:
122 case OMAP_L3_SDMA_WR_2:
123 return "SDMA_WR";
124 case OMAP_L3_SDMA_RD_1:
125 case OMAP_L3_SDMA_RD_2:
126 case OMAP_L3_SDMA_RD_3:
127 case OMAP_L3_SDMA_RD_4:
128 return "SDMA_RD";
129 case OMAP_L3_USBOTG:
130 return "USB_OTG";
131 case OMAP_L3_USBHOST:
132 return "USB_HOST";
133 default:
134 return "UNKNOWN Initiator";
135 }
136}
137
138/**
139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 *
141 * @base: register block base address
142 * @error: L3_ERROR_LOG register of our block
143 *
144 * Called in hard-irq context. Caller should take care of locking
145 *
146 * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
147 * Analysis Sequence, we are following that sequence here, please
148 * refer to that Figure for more information on the subject.
149 */
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr)
152{
153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr);
157
158 WARN(true, "%s Error seen by %s %s at address %x\n",
159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "",
162 address);
163
164 return IRQ_HANDLED;
165}
166
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{
169 struct omap3_l3 *l3 = _l3;
170
171 u64 status, clear;
172 u64 error;
173 u64 error_addr;
174 u64 err_source = 0;
175 void __iomem *base;
176 int int_type;
177
178 irqreturn_t ret = IRQ_NONE;
179
180 if (irq == l3->app_irq)
181 int_type = L3_APPLICATION_ERROR;
182 else
183 int_type = L3_DEBUG_ERROR;
184
185 if (!int_type) {
186 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
187 /*
188 * if we have a timeout error, there's nothing we can
189 * do besides rebooting the board. So let's BUG on any
190 * of such errors and handle the others. timeout error
191 * is severe and not expected to occur.
192 */
193 BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
194 } else {
195 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
196 /* No timeout error for debug sources */
197 }
198
199 base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
200
201 /* identify the error source */
202 for (err_source = 0; !(status & (1 << err_source)); err_source++)
203 ;
204 error = omap3_l3_readll(base, L3_ERROR_LOG);
205
206 if (error) {
207 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
208
209 ret |= omap3_l3_block_irq(l3, error, error_addr);
210 }
211
212 /* Clear the status register */
213 clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
214 (L3_AGENT_STATUS_CLEAR_TA));
215
216 omap3_l3_writell(base, L3_AGENT_STATUS, clear);
217
218 /* clear the error log register */
219 omap3_l3_writell(base, L3_ERROR_LOG, error);
220
221 return ret;
222}
223
224static int __init omap3_l3_probe(struct platform_device *pdev)
225{
226 struct omap3_l3 *l3;
227 struct resource *res;
228 int ret;
229 int irq;
230
231 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
232 if (!l3) {
233 ret = -ENOMEM;
234 goto err0;
235 }
236
237 platform_set_drvdata(pdev, l3);
238
239 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
240 if (!res) {
241 dev_err(&pdev->dev, "couldn't find resource\n");
242 ret = -ENODEV;
243 goto err1;
244 }
245 l3->rt = ioremap(res->start, resource_size(res));
246 if (!(l3->rt)) {
247 dev_err(&pdev->dev, "ioremap failed\n");
248 ret = -ENOMEM;
249 goto err2;
250 }
251
252 irq = platform_get_irq(pdev, 0);
253 ret = request_irq(irq, omap3_l3_app_irq,
254 IRQF_DISABLED | IRQF_TRIGGER_RISING,
255 "l3-debug-irq", l3);
256 if (ret) {
257 dev_err(&pdev->dev, "couldn't request debug irq\n");
258 goto err3;
259 }
260 l3->debug_irq = irq;
261
262 irq = platform_get_irq(pdev, 1);
263 ret = request_irq(irq, omap3_l3_app_irq,
264 IRQF_DISABLED | IRQF_TRIGGER_RISING,
265 "l3-app-irq", l3);
266
267 if (ret) {
268 dev_err(&pdev->dev, "couldn't request app irq\n");
269 goto err4;
270 }
271
272 l3->app_irq = irq;
273 goto err0;
274
275err4:
276err3:
277 iounmap(l3->rt);
278err2:
279err1:
280 kfree(l3);
281err0:
282 return ret;
283}
284
285static int __exit omap3_l3_remove(struct platform_device *pdev)
286{
287 struct omap3_l3 *l3 = platform_get_drvdata(pdev);
288
289 free_irq(l3->app_irq, l3);
290 free_irq(l3->debug_irq, l3);
291 iounmap(l3->rt);
292 kfree(l3);
293
294 return 0;
295}
296
297static struct platform_driver omap3_l3_driver = {
298 .remove = __exit_p(omap3_l3_remove),
299 .driver = {
300 .name = "omap_l3_smx",
301 },
302};
303
304static int __init omap3_l3_init(void)
305{
306 return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
307}
308postcore_initcall_sync(omap3_l3_init);
309
310static void __exit omap3_l3_exit(void)
311{
312 platform_driver_unregister(&omap3_l3_driver);
313}
314module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 000000000000..ba2ed9a850cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
1 /*
2 * OMAP3XXX L3 Interconnect Driver header
3 *
4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA
23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26
27/* Register definitions. All 64-bit wide */
28#define L3_COMPONENT 0x000
29#define L3_CORE 0x018
30#define L3_AGENT_CONTROL 0x020
31#define L3_AGENT_STATUS 0x028
32#define L3_ERROR_LOG 0x058
33
34#define L3_ERROR_LOG_MULTI (1 << 31)
35#define L3_ERROR_LOG_SECONDARY (1 << 30)
36
37#define L3_ERROR_LOG_ADDR 0x060
38
39/* Register definitions for Sideband Interconnect */
40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510
42
43const u64 shift = 1;
44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
47#define L3_STATUS_0_MPUIA_INBAND (shift << 2)
48#define L3_STATUS_0_IVAIA_BRST (shift << 6)
49#define L3_STATUS_0_IVAIA_RSP (shift << 7)
50#define L3_STATUS_0_IVAIA_INBAND (shift << 8)
51#define L3_STATUS_0_SGXIA_BRST (shift << 9)
52#define L3_STATUS_0_SGXIA_RSP (shift << 10)
53#define L3_STATUS_0_SGXIA_MERROR (shift << 11)
54#define L3_STATUS_0_CAMIA_BRST (shift << 12)
55#define L3_STATUS_0_CAMIA_RSP (shift << 13)
56#define L3_STATUS_0_CAMIA_INBAND (shift << 14)
57#define L3_STATUS_0_DISPIA_BRST (shift << 15)
58#define L3_STATUS_0_DISPIA_RSP (shift << 16)
59#define L3_STATUS_0_DMARDIA_BRST (shift << 18)
60#define L3_STATUS_0_DMARDIA_RSP (shift << 19)
61#define L3_STATUS_0_DMAWRIA_BRST (shift << 21)
62#define L3_STATUS_0_DMAWRIA_RSP (shift << 22)
63#define L3_STATUS_0_USBOTGIA_BRST (shift << 24)
64#define L3_STATUS_0_USBOTGIA_RSP (shift << 25)
65#define L3_STATUS_0_USBOTGIA_INBAND (shift << 26)
66#define L3_STATUS_0_USBHOSTIA_BRST (shift << 27)
67#define L3_STATUS_0_USBHOSTIA_INBAND (shift << 28)
68#define L3_STATUS_0_SMSTA_REQ (shift << 48)
69#define L3_STATUS_0_GPMCTA_REQ (shift << 49)
70#define L3_STATUS_0_OCMRAMTA_REQ (shift << 50)
71#define L3_STATUS_0_OCMROMTA_REQ (shift << 51)
72#define L3_STATUS_0_IVATA_REQ (shift << 54)
73#define L3_STATUS_0_SGXTA_REQ (shift << 55)
74#define L3_STATUS_0_SGXTA_SERROR (shift << 56)
75#define L3_STATUS_0_GPMCTA_SERROR (shift << 57)
76#define L3_STATUS_0_L4CORETA_REQ (shift << 58)
77#define L3_STATUS_0_L4PERTA_REQ (shift << 59)
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ)
108
109#define L3_SI_FLAG_STATUS_1 0x530
110
111#define L3_STATUS_1_MPU_DATAIA (1 << 0)
112#define L3_STATUS_1_DAPIA0 (1 << 3)
113#define L3_STATUS_1_DAPIA1 (1 << 4)
114#define L3_STATUS_1_IVAIA (1 << 6)
115
116#define L3_PM_ERROR_LOG 0x020
117#define L3_PM_CONTROL 0x028
118#define L3_PM_ERROR_CLEAR_SINGLE 0x030
119#define L3_PM_ERROR_CLEAR_MULTI 0x038
120#define L3_PM_REQ_INFO_PERMISSION(n) (0x048 + (0x020 * n))
121#define L3_PM_READ_PERMISSION(n) (0x050 + (0x020 * n))
122#define L3_PM_WRITE_PERMISSION(n) (0x058 + (0x020 * n))
123#define L3_PM_ADDR_MATCH(n) (0x060 + (0x020 * n))
124
125/* L3 error log bit fields. Common for IA and TA */
126#define L3_ERROR_LOG_CODE 24
127#define L3_ERROR_LOG_INITID 8
128#define L3_ERROR_LOG_CMD 0
129
130/* L3 agent status bit fields. */
131#define L3_AGENT_STATUS_CLEAR_IA 0x10000000
132#define L3_AGENT_STATUS_CLEAR_TA 0x01000000
133
134#define OMAP34xx_IRQ_L3_APP 10
135#define L3_APPLICATION_ERROR 0x0
136#define L3_DEBUG_ERROR 0x1
137
138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
156 OMAP_L3_IA_IVA_SS_DMA_3 = 17,
157 OMAP_L3_IA_IVA_SS_DMA_4 = 16,
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1,
180};
181
182enum omap3_l3_code {
183 OMAP_L3_CODE_NOERROR = 0,
184 OMAP_L3_CODE_UNSUP_CMD = 1,
185 OMAP_L3_CODE_ADDR_HOLE = 2,
186 OMAP_L3_CODE_PROTECT_VIOLATION = 3,
187 OMAP_L3_CODE_IN_BAND_ERR = 4,
188 /* codes 5 and 6 are reserved */
189 OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
190 OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
191 /* codes 9 - 15 are also reserved */
192};
193
194struct omap3_l3 {
195 struct device *dev;
196 struct clk *ick;
197
198 /* memory base*/
199 void __iomem *rt;
200
201 int debug_irq;
202 int app_irq;
203
204 /* true when and inband functional error occurs */
205 unsigned inband:1;
206};
207
208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = {
210 /* MPU IA */
211 0x1400,
212 0x1400,
213 0x1400,
214 /* RESERVED */
215 0,
216 0,
217 0,
218 /* IVA 2.2 IA */
219 0x1800,
220 0x1800,
221 0x1800,
222 /* SGX IA */
223 0x1c00,
224 0x1c00,
225 /* RESERVED */
226 0,
227 /* CAMERA IA */
228 0x5800,
229 0x5800,
230 0x5800,
231 /* DISPLAY IA */
232 0x5400,
233 0x5400,
234 /* RESERVED */
235 0,
236 /*SDMA RD IA */
237 0x4c00,
238 0x4c00,
239 /* RESERVED */
240 0,
241 /* SDMA WR IA */
242 0x5000,
243 0x5000,
244 /* RESERVED */
245 0,
246 /* USB OTG IA */
247 0x4400,
248 0x4400,
249 0x4400,
250 /* USB HOST IA */
251 0x4000,
252 0x4000,
253 /* RESERVED */
254 0,
255 0,
256 0,
257 0,
258 /* SAD2D IA */
259 0x3000,
260 0x3000,
261 0x3000,
262 /* RESERVED */
263 0,
264 0,
265 0,
266 0,
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0,
275 /* SMA TA */
276 0x2000,
277 /* GPMC TA */
278 0x2400,
279 /* OCM RAM TA */
280 0x2800,
281 /* OCM ROM TA */
282 0x2C00,
283 /* L4 CORE TA */
284 0x6800,
285 /* L4 PER TA */
286 0x6c00,
287 /* IVA 2.2 TA */
288 0x6000,
289 /* SGX TA */
290 0x6400,
291 /* L4 EMU TA */
292 0x7000,
293 /* GPMC TA */
294 0x2400,
295 /* L4 CORE TA */
296 0x6800,
297 /* L4 PER TA */
298 0x6c00,
299 /* L4 EMU TA */
300 0x7000,
301 /* MAD2D TA */
302 0x3400,
303 /* RESERVED */
304 0,
305 0,
306};
307
308unsigned int __iomem omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */
310 0x1400,
311 /* RESERVED */
312 0,
313 0,
314 /* DAP IA */
315 0x5c00,
316 0x5c00,
317 /* RESERVED */
318 0,
319 /* IVA 2.2 IA */
320 0x1800,
321 /* REST RESERVED */
322};
323
324u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases,
326 omap3_l3_debug_bases,
327};
328
329/*
330 * REVISIT define __raw_readll/__raw_writell here, but move them to
331 * <asm/io.h> at some point
332 */
333#define __raw_writell(v, a) (__chk_io_ptr(a), \
334 *(volatile u64 __force *)(a) = (v))
335#define __raw_readll(a) (__chk_io_ptr(a), \
336 *(volatile u64 __force *)(a))
337
338#endif
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 1b911681e911..d77928370463 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,6 +315,8 @@
315#define INT_34XX_SSM_ABORT_IRQ 6 315#define INT_34XX_SSM_ABORT_IRQ 6
316#define INT_34XX_SYS_NIRQ 7 316#define INT_34XX_SYS_NIRQ 7
317#define INT_34XX_D2D_FW_IRQ 8 317#define INT_34XX_D2D_FW_IRQ 8
318#define INT_34XX_L3_DBG_IRQ 9
319#define INT_34XX_L3_APP_IRQ 10
318#define INT_34XX_PRCM_MPU_IRQ 11 320#define INT_34XX_PRCM_MPU_IRQ 11
319#define INT_34XX_MCBSP1_IRQ 16 321#define INT_34XX_MCBSP1_IRQ 16
320#define INT_34XX_MCBSP2_IRQ 17 322#define INT_34XX_MCBSP2_IRQ 17