diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-02-23 17:53:45 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-02-29 05:14:47 -0500 |
commit | f712812e1ba7f17a270f285c3e7e70c65186a8b4 (patch) | |
tree | 00b31997e1b369cca4dc7709b31a273fd9be3b3b | |
parent | dfb276f098e0e90319a346bae2f205f2690d6b42 (diff) |
drm/radeon/kms: make ring_start, ring_test, and ib_test per ring
Each ring type may need a different variant.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r100.c | 11 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r420.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r520.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 75 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs400.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs600.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rs690.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 2 |
15 files changed, 83 insertions, 65 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 4350a3fe4ec5..450b01d915e2 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1539,7 +1539,7 @@ int evergreen_cp_resume(struct radeon_device *rdev) | |||
1539 | 1539 | ||
1540 | evergreen_cp_start(rdev); | 1540 | evergreen_cp_start(rdev); |
1541 | ring->ready = true; | 1541 | ring->ready = true; |
1542 | r = radeon_ring_test(rdev, ring); | 1542 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
1543 | if (r) { | 1543 | if (r) { |
1544 | ring->ready = false; | 1544 | ring->ready = false; |
1545 | return r; | 1545 | return r; |
@@ -3237,7 +3237,7 @@ static int evergreen_startup(struct radeon_device *rdev) | |||
3237 | if (r) | 3237 | if (r) |
3238 | return r; | 3238 | return r; |
3239 | 3239 | ||
3240 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); | 3240 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
3241 | if (r) { | 3241 | if (r) { |
3242 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | 3242 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
3243 | rdev->accel_working = false; | 3243 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 6863a0538615..8ce7f9973a5c 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1318,7 +1318,7 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1318 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | 1318 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
1319 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; | 1319 | rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; |
1320 | /* this only test cp0 */ | 1320 | /* this only test cp0 */ |
1321 | r = radeon_ring_test(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); | 1321 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1322 | if (r) { | 1322 | if (r) { |
1323 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; | 1323 | rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; |
1324 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; | 1324 | rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; |
@@ -1518,7 +1518,7 @@ static int cayman_startup(struct radeon_device *rdev) | |||
1518 | if (r) | 1518 | if (r) |
1519 | return r; | 1519 | return r; |
1520 | 1520 | ||
1521 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); | 1521 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1522 | if (r) { | 1522 | if (r) { |
1523 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | 1523 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
1524 | rdev->accel_working = false; | 1524 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index 65fe8e092a18..844f20cf873d 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -970,9 +970,8 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev) | |||
970 | return -1; | 970 | return -1; |
971 | } | 971 | } |
972 | 972 | ||
973 | void r100_ring_start(struct radeon_device *rdev) | 973 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
974 | { | 974 | { |
975 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | ||
976 | int r; | 975 | int r; |
977 | 976 | ||
978 | r = radeon_ring_lock(rdev, ring, 2); | 977 | r = radeon_ring_lock(rdev, ring, 2); |
@@ -1183,8 +1182,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) | |||
1183 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); | 1182 | WREG32(RADEON_CP_RB_WPTR_DELAY, 0); |
1184 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); | 1183 | WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); |
1185 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); | 1184 | WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
1186 | radeon_ring_start(rdev); | 1185 | radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1187 | r = radeon_ring_test(rdev, ring); | 1186 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
1188 | if (r) { | 1187 | if (r) { |
1189 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); | 1188 | DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
1190 | return r; | 1189 | return r; |
@@ -3743,7 +3742,7 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |||
3743 | radeon_ring_write(ring, ib->length_dw); | 3742 | radeon_ring_write(ring, ib->length_dw); |
3744 | } | 3743 | } |
3745 | 3744 | ||
3746 | int r100_ib_test(struct radeon_device *rdev) | 3745 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
3747 | { | 3746 | { |
3748 | struct radeon_ib *ib; | 3747 | struct radeon_ib *ib; |
3749 | uint32_t scratch; | 3748 | uint32_t scratch; |
@@ -3968,7 +3967,7 @@ static int r100_startup(struct radeon_device *rdev) | |||
3968 | if (r) | 3967 | if (r) |
3969 | return r; | 3968 | return r; |
3970 | 3969 | ||
3971 | r = r100_ib_test(rdev); | 3970 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
3972 | if (r) { | 3971 | if (r) { |
3973 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 3972 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
3974 | rdev->accel_working = false; | 3973 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 3fc0d29a5f39..c42729456a07 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -206,9 +206,8 @@ void r300_fence_ring_emit(struct radeon_device *rdev, | |||
206 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); | 206 | radeon_ring_write(ring, RADEON_SW_INT_FIRE); |
207 | } | 207 | } |
208 | 208 | ||
209 | void r300_ring_start(struct radeon_device *rdev) | 209 | void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
210 | { | 210 | { |
211 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | ||
212 | unsigned gb_tile_config; | 211 | unsigned gb_tile_config; |
213 | int r; | 212 | int r; |
214 | 213 | ||
@@ -1419,7 +1418,7 @@ static int r300_startup(struct radeon_device *rdev) | |||
1419 | if (r) | 1418 | if (r) |
1420 | return r; | 1419 | return r; |
1421 | 1420 | ||
1422 | r = r100_ib_test(rdev); | 1421 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1423 | if (r) { | 1422 | if (r) { |
1424 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 1423 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
1425 | rdev->accel_working = false; | 1424 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 666e28fe509c..d0f2c0363c27 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -279,7 +279,7 @@ static int r420_startup(struct radeon_device *rdev) | |||
279 | if (r) | 279 | if (r) |
280 | return r; | 280 | return r; |
281 | 281 | ||
282 | r = r100_ib_test(rdev); | 282 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
283 | if (r) { | 283 | if (r) { |
284 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 284 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
285 | rdev->accel_working = false; | 285 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index 2e1087a2b973..422923ce70b6 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -207,7 +207,7 @@ static int r520_startup(struct radeon_device *rdev) | |||
207 | if (r) | 207 | if (r) |
208 | return r; | 208 | return r; |
209 | 209 | ||
210 | r = r100_ib_test(rdev); | 210 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
211 | if (r) { | 211 | if (r) { |
212 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 212 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
213 | rdev->accel_working = false; | 213 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 4cfb90be7241..8a6d68c028d3 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2226,7 +2226,7 @@ int r600_cp_resume(struct radeon_device *rdev) | |||
2226 | 2226 | ||
2227 | r600_cp_start(rdev); | 2227 | r600_cp_start(rdev); |
2228 | ring->ready = true; | 2228 | ring->ready = true; |
2229 | r = radeon_ring_test(rdev, ring); | 2229 | r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); |
2230 | if (r) { | 2230 | if (r) { |
2231 | ring->ready = false; | 2231 | ring->ready = false; |
2232 | return r; | 2232 | return r; |
@@ -2490,7 +2490,7 @@ int r600_startup(struct radeon_device *rdev) | |||
2490 | if (r) | 2490 | if (r) |
2491 | return r; | 2491 | return r; |
2492 | 2492 | ||
2493 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); | 2493 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
2494 | if (r) { | 2494 | if (r) { |
2495 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); | 2495 | DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
2496 | rdev->accel_working = false; | 2496 | rdev->accel_working = false; |
@@ -2697,13 +2697,14 @@ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) | |||
2697 | radeon_ring_write(ring, ib->length_dw); | 2697 | radeon_ring_write(ring, ib->length_dw); |
2698 | } | 2698 | } |
2699 | 2699 | ||
2700 | int r600_ib_test(struct radeon_device *rdev, int ring) | 2700 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) |
2701 | { | 2701 | { |
2702 | struct radeon_ib *ib; | 2702 | struct radeon_ib *ib; |
2703 | uint32_t scratch; | 2703 | uint32_t scratch; |
2704 | uint32_t tmp = 0; | 2704 | uint32_t tmp = 0; |
2705 | unsigned i; | 2705 | unsigned i; |
2706 | int r; | 2706 | int r; |
2707 | int ring_index = radeon_ring_index(rdev, ring); | ||
2707 | 2708 | ||
2708 | r = radeon_scratch_get(rdev, &scratch); | 2709 | r = radeon_scratch_get(rdev, &scratch); |
2709 | if (r) { | 2710 | if (r) { |
@@ -2711,7 +2712,7 @@ int r600_ib_test(struct radeon_device *rdev, int ring) | |||
2711 | return r; | 2712 | return r; |
2712 | } | 2713 | } |
2713 | WREG32(scratch, 0xCAFEDEAD); | 2714 | WREG32(scratch, 0xCAFEDEAD); |
2714 | r = radeon_ib_get(rdev, ring, &ib, 256); | 2715 | r = radeon_ib_get(rdev, ring_index, &ib, 256); |
2715 | if (r) { | 2716 | if (r) { |
2716 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); | 2717 | DRM_ERROR("radeon: failed to get ib (%d).\n", r); |
2717 | return r; | 2718 | return r; |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 29efb73af5de..619e200fbf1c 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -783,7 +783,6 @@ int radeon_ib_pool_init(struct radeon_device *rdev); | |||
783 | void radeon_ib_pool_fini(struct radeon_device *rdev); | 783 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
784 | int radeon_ib_pool_start(struct radeon_device *rdev); | 784 | int radeon_ib_pool_start(struct radeon_device *rdev); |
785 | int radeon_ib_pool_suspend(struct radeon_device *rdev); | 785 | int radeon_ib_pool_suspend(struct radeon_device *rdev); |
786 | int radeon_ib_test(struct radeon_device *rdev); | ||
787 | /* Ring access between begin & end cannot sleep */ | 786 | /* Ring access between begin & end cannot sleep */ |
788 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp); | 787 | int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp); |
789 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); | 788 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
@@ -1136,8 +1135,6 @@ struct radeon_asic { | |||
1136 | int (*asic_reset)(struct radeon_device *rdev); | 1135 | int (*asic_reset)(struct radeon_device *rdev); |
1137 | void (*gart_tlb_flush)(struct radeon_device *rdev); | 1136 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
1138 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); | 1137 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
1139 | void (*ring_start)(struct radeon_device *rdev); | ||
1140 | |||
1141 | struct { | 1138 | struct { |
1142 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); | 1139 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
1143 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); | 1140 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
@@ -1145,10 +1142,11 @@ struct radeon_asic { | |||
1145 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, | 1142 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
1146 | struct radeon_semaphore *semaphore, bool emit_wait); | 1143 | struct radeon_semaphore *semaphore, bool emit_wait); |
1147 | int (*cs_parse)(struct radeon_cs_parser *p); | 1144 | int (*cs_parse)(struct radeon_cs_parser *p); |
1145 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); | ||
1146 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | ||
1147 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); | ||
1148 | } ring[RADEON_NUM_RINGS]; | 1148 | } ring[RADEON_NUM_RINGS]; |
1149 | 1149 | ||
1150 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); | ||
1151 | |||
1152 | struct { | 1150 | struct { |
1153 | int (*set)(struct radeon_device *rdev); | 1151 | int (*set)(struct radeon_device *rdev); |
1154 | int (*process)(struct radeon_device *rdev); | 1152 | int (*process)(struct radeon_device *rdev); |
@@ -1677,8 +1675,9 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v); | |||
1677 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) | 1675 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
1678 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) | 1676 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1679 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) | 1677 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
1680 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) | 1678 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
1681 | #define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp)) | 1679 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) |
1680 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) | ||
1682 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) | 1681 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
1683 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) | 1682 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
1684 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) | 1683 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index a7b6c37d8fa4..85e13502e80f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -138,14 +138,15 @@ static struct radeon_asic r100_asic = { | |||
138 | .asic_reset = &r100_asic_reset, | 138 | .asic_reset = &r100_asic_reset, |
139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 139 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
140 | .gart_set_page = &r100_pci_gart_set_page, | 140 | .gart_set_page = &r100_pci_gart_set_page, |
141 | .ring_start = &r100_ring_start, | ||
142 | .ring_test = &r100_ring_test, | ||
143 | .ring = { | 141 | .ring = { |
144 | [RADEON_RING_TYPE_GFX_INDEX] = { | 142 | [RADEON_RING_TYPE_GFX_INDEX] = { |
145 | .ib_execute = &r100_ring_ib_execute, | 143 | .ib_execute = &r100_ring_ib_execute, |
146 | .emit_fence = &r100_fence_ring_emit, | 144 | .emit_fence = &r100_fence_ring_emit, |
147 | .emit_semaphore = &r100_semaphore_ring_emit, | 145 | .emit_semaphore = &r100_semaphore_ring_emit, |
148 | .cs_parse = &r100_cs_parse, | 146 | .cs_parse = &r100_cs_parse, |
147 | .ring_start = &r100_ring_start, | ||
148 | .ring_test = &r100_ring_test, | ||
149 | .ib_test = &r100_ib_test, | ||
149 | } | 150 | } |
150 | }, | 151 | }, |
151 | .irq = { | 152 | .irq = { |
@@ -205,14 +206,15 @@ static struct radeon_asic r200_asic = { | |||
205 | .asic_reset = &r100_asic_reset, | 206 | .asic_reset = &r100_asic_reset, |
206 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 207 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
207 | .gart_set_page = &r100_pci_gart_set_page, | 208 | .gart_set_page = &r100_pci_gart_set_page, |
208 | .ring_start = &r100_ring_start, | ||
209 | .ring_test = &r100_ring_test, | ||
210 | .ring = { | 209 | .ring = { |
211 | [RADEON_RING_TYPE_GFX_INDEX] = { | 210 | [RADEON_RING_TYPE_GFX_INDEX] = { |
212 | .ib_execute = &r100_ring_ib_execute, | 211 | .ib_execute = &r100_ring_ib_execute, |
213 | .emit_fence = &r100_fence_ring_emit, | 212 | .emit_fence = &r100_fence_ring_emit, |
214 | .emit_semaphore = &r100_semaphore_ring_emit, | 213 | .emit_semaphore = &r100_semaphore_ring_emit, |
215 | .cs_parse = &r100_cs_parse, | 214 | .cs_parse = &r100_cs_parse, |
215 | .ring_start = &r100_ring_start, | ||
216 | .ring_test = &r100_ring_test, | ||
217 | .ib_test = &r100_ib_test, | ||
216 | } | 218 | } |
217 | }, | 219 | }, |
218 | .irq = { | 220 | .irq = { |
@@ -271,14 +273,15 @@ static struct radeon_asic r300_asic = { | |||
271 | .asic_reset = &r300_asic_reset, | 273 | .asic_reset = &r300_asic_reset, |
272 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, | 274 | .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
273 | .gart_set_page = &r100_pci_gart_set_page, | 275 | .gart_set_page = &r100_pci_gart_set_page, |
274 | .ring_start = &r300_ring_start, | ||
275 | .ring_test = &r100_ring_test, | ||
276 | .ring = { | 276 | .ring = { |
277 | [RADEON_RING_TYPE_GFX_INDEX] = { | 277 | [RADEON_RING_TYPE_GFX_INDEX] = { |
278 | .ib_execute = &r100_ring_ib_execute, | 278 | .ib_execute = &r100_ring_ib_execute, |
279 | .emit_fence = &r300_fence_ring_emit, | 279 | .emit_fence = &r300_fence_ring_emit, |
280 | .emit_semaphore = &r100_semaphore_ring_emit, | 280 | .emit_semaphore = &r100_semaphore_ring_emit, |
281 | .cs_parse = &r300_cs_parse, | 281 | .cs_parse = &r300_cs_parse, |
282 | .ring_start = &r300_ring_start, | ||
283 | .ring_test = &r100_ring_test, | ||
284 | .ib_test = &r100_ib_test, | ||
282 | } | 285 | } |
283 | }, | 286 | }, |
284 | .irq = { | 287 | .irq = { |
@@ -338,14 +341,15 @@ static struct radeon_asic r300_asic_pcie = { | |||
338 | .asic_reset = &r300_asic_reset, | 341 | .asic_reset = &r300_asic_reset, |
339 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 342 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
340 | .gart_set_page = &rv370_pcie_gart_set_page, | 343 | .gart_set_page = &rv370_pcie_gart_set_page, |
341 | .ring_start = &r300_ring_start, | ||
342 | .ring_test = &r100_ring_test, | ||
343 | .ring = { | 344 | .ring = { |
344 | [RADEON_RING_TYPE_GFX_INDEX] = { | 345 | [RADEON_RING_TYPE_GFX_INDEX] = { |
345 | .ib_execute = &r100_ring_ib_execute, | 346 | .ib_execute = &r100_ring_ib_execute, |
346 | .emit_fence = &r300_fence_ring_emit, | 347 | .emit_fence = &r300_fence_ring_emit, |
347 | .emit_semaphore = &r100_semaphore_ring_emit, | 348 | .emit_semaphore = &r100_semaphore_ring_emit, |
348 | .cs_parse = &r300_cs_parse, | 349 | .cs_parse = &r300_cs_parse, |
350 | .ring_start = &r300_ring_start, | ||
351 | .ring_test = &r100_ring_test, | ||
352 | .ib_test = &r100_ib_test, | ||
349 | } | 353 | } |
350 | }, | 354 | }, |
351 | .irq = { | 355 | .irq = { |
@@ -404,14 +408,15 @@ static struct radeon_asic r420_asic = { | |||
404 | .asic_reset = &r300_asic_reset, | 408 | .asic_reset = &r300_asic_reset, |
405 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 409 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
406 | .gart_set_page = &rv370_pcie_gart_set_page, | 410 | .gart_set_page = &rv370_pcie_gart_set_page, |
407 | .ring_start = &r300_ring_start, | ||
408 | .ring_test = &r100_ring_test, | ||
409 | .ring = { | 411 | .ring = { |
410 | [RADEON_RING_TYPE_GFX_INDEX] = { | 412 | [RADEON_RING_TYPE_GFX_INDEX] = { |
411 | .ib_execute = &r100_ring_ib_execute, | 413 | .ib_execute = &r100_ring_ib_execute, |
412 | .emit_fence = &r300_fence_ring_emit, | 414 | .emit_fence = &r300_fence_ring_emit, |
413 | .emit_semaphore = &r100_semaphore_ring_emit, | 415 | .emit_semaphore = &r100_semaphore_ring_emit, |
414 | .cs_parse = &r300_cs_parse, | 416 | .cs_parse = &r300_cs_parse, |
417 | .ring_start = &r300_ring_start, | ||
418 | .ring_test = &r100_ring_test, | ||
419 | .ib_test = &r100_ib_test, | ||
415 | } | 420 | } |
416 | }, | 421 | }, |
417 | .irq = { | 422 | .irq = { |
@@ -471,14 +476,15 @@ static struct radeon_asic rs400_asic = { | |||
471 | .asic_reset = &r300_asic_reset, | 476 | .asic_reset = &r300_asic_reset, |
472 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 477 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
473 | .gart_set_page = &rs400_gart_set_page, | 478 | .gart_set_page = &rs400_gart_set_page, |
474 | .ring_start = &r300_ring_start, | ||
475 | .ring_test = &r100_ring_test, | ||
476 | .ring = { | 479 | .ring = { |
477 | [RADEON_RING_TYPE_GFX_INDEX] = { | 480 | [RADEON_RING_TYPE_GFX_INDEX] = { |
478 | .ib_execute = &r100_ring_ib_execute, | 481 | .ib_execute = &r100_ring_ib_execute, |
479 | .emit_fence = &r300_fence_ring_emit, | 482 | .emit_fence = &r300_fence_ring_emit, |
480 | .emit_semaphore = &r100_semaphore_ring_emit, | 483 | .emit_semaphore = &r100_semaphore_ring_emit, |
481 | .cs_parse = &r300_cs_parse, | 484 | .cs_parse = &r300_cs_parse, |
485 | .ring_start = &r300_ring_start, | ||
486 | .ring_test = &r100_ring_test, | ||
487 | .ib_test = &r100_ib_test, | ||
482 | } | 488 | } |
483 | }, | 489 | }, |
484 | .irq = { | 490 | .irq = { |
@@ -538,14 +544,15 @@ static struct radeon_asic rs600_asic = { | |||
538 | .asic_reset = &rs600_asic_reset, | 544 | .asic_reset = &rs600_asic_reset, |
539 | .gart_tlb_flush = &rs600_gart_tlb_flush, | 545 | .gart_tlb_flush = &rs600_gart_tlb_flush, |
540 | .gart_set_page = &rs600_gart_set_page, | 546 | .gart_set_page = &rs600_gart_set_page, |
541 | .ring_start = &r300_ring_start, | ||
542 | .ring_test = &r100_ring_test, | ||
543 | .ring = { | 547 | .ring = { |
544 | [RADEON_RING_TYPE_GFX_INDEX] = { | 548 | [RADEON_RING_TYPE_GFX_INDEX] = { |
545 | .ib_execute = &r100_ring_ib_execute, | 549 | .ib_execute = &r100_ring_ib_execute, |
546 | .emit_fence = &r300_fence_ring_emit, | 550 | .emit_fence = &r300_fence_ring_emit, |
547 | .emit_semaphore = &r100_semaphore_ring_emit, | 551 | .emit_semaphore = &r100_semaphore_ring_emit, |
548 | .cs_parse = &r300_cs_parse, | 552 | .cs_parse = &r300_cs_parse, |
553 | .ring_start = &r300_ring_start, | ||
554 | .ring_test = &r100_ring_test, | ||
555 | .ib_test = &r100_ib_test, | ||
549 | } | 556 | } |
550 | }, | 557 | }, |
551 | .irq = { | 558 | .irq = { |
@@ -605,14 +612,15 @@ static struct radeon_asic rs690_asic = { | |||
605 | .asic_reset = &rs600_asic_reset, | 612 | .asic_reset = &rs600_asic_reset, |
606 | .gart_tlb_flush = &rs400_gart_tlb_flush, | 613 | .gart_tlb_flush = &rs400_gart_tlb_flush, |
607 | .gart_set_page = &rs400_gart_set_page, | 614 | .gart_set_page = &rs400_gart_set_page, |
608 | .ring_start = &r300_ring_start, | ||
609 | .ring_test = &r100_ring_test, | ||
610 | .ring = { | 615 | .ring = { |
611 | [RADEON_RING_TYPE_GFX_INDEX] = { | 616 | [RADEON_RING_TYPE_GFX_INDEX] = { |
612 | .ib_execute = &r100_ring_ib_execute, | 617 | .ib_execute = &r100_ring_ib_execute, |
613 | .emit_fence = &r300_fence_ring_emit, | 618 | .emit_fence = &r300_fence_ring_emit, |
614 | .emit_semaphore = &r100_semaphore_ring_emit, | 619 | .emit_semaphore = &r100_semaphore_ring_emit, |
615 | .cs_parse = &r300_cs_parse, | 620 | .cs_parse = &r300_cs_parse, |
621 | .ring_start = &r300_ring_start, | ||
622 | .ring_test = &r100_ring_test, | ||
623 | .ib_test = &r100_ib_test, | ||
616 | } | 624 | } |
617 | }, | 625 | }, |
618 | .irq = { | 626 | .irq = { |
@@ -672,14 +680,15 @@ static struct radeon_asic rv515_asic = { | |||
672 | .asic_reset = &rs600_asic_reset, | 680 | .asic_reset = &rs600_asic_reset, |
673 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 681 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
674 | .gart_set_page = &rv370_pcie_gart_set_page, | 682 | .gart_set_page = &rv370_pcie_gart_set_page, |
675 | .ring_start = &rv515_ring_start, | ||
676 | .ring_test = &r100_ring_test, | ||
677 | .ring = { | 683 | .ring = { |
678 | [RADEON_RING_TYPE_GFX_INDEX] = { | 684 | [RADEON_RING_TYPE_GFX_INDEX] = { |
679 | .ib_execute = &r100_ring_ib_execute, | 685 | .ib_execute = &r100_ring_ib_execute, |
680 | .emit_fence = &r300_fence_ring_emit, | 686 | .emit_fence = &r300_fence_ring_emit, |
681 | .emit_semaphore = &r100_semaphore_ring_emit, | 687 | .emit_semaphore = &r100_semaphore_ring_emit, |
682 | .cs_parse = &r300_cs_parse, | 688 | .cs_parse = &r300_cs_parse, |
689 | .ring_start = &rv515_ring_start, | ||
690 | .ring_test = &r100_ring_test, | ||
691 | .ib_test = &r100_ib_test, | ||
683 | } | 692 | } |
684 | }, | 693 | }, |
685 | .irq = { | 694 | .irq = { |
@@ -739,14 +748,15 @@ static struct radeon_asic r520_asic = { | |||
739 | .asic_reset = &rs600_asic_reset, | 748 | .asic_reset = &rs600_asic_reset, |
740 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, | 749 | .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
741 | .gart_set_page = &rv370_pcie_gart_set_page, | 750 | .gart_set_page = &rv370_pcie_gart_set_page, |
742 | .ring_start = &rv515_ring_start, | ||
743 | .ring_test = &r100_ring_test, | ||
744 | .ring = { | 751 | .ring = { |
745 | [RADEON_RING_TYPE_GFX_INDEX] = { | 752 | [RADEON_RING_TYPE_GFX_INDEX] = { |
746 | .ib_execute = &r100_ring_ib_execute, | 753 | .ib_execute = &r100_ring_ib_execute, |
747 | .emit_fence = &r300_fence_ring_emit, | 754 | .emit_fence = &r300_fence_ring_emit, |
748 | .emit_semaphore = &r100_semaphore_ring_emit, | 755 | .emit_semaphore = &r100_semaphore_ring_emit, |
749 | .cs_parse = &r300_cs_parse, | 756 | .cs_parse = &r300_cs_parse, |
757 | .ring_start = &rv515_ring_start, | ||
758 | .ring_test = &r100_ring_test, | ||
759 | .ib_test = &r100_ib_test, | ||
750 | } | 760 | } |
751 | }, | 761 | }, |
752 | .irq = { | 762 | .irq = { |
@@ -806,13 +816,14 @@ static struct radeon_asic r600_asic = { | |||
806 | .asic_reset = &r600_asic_reset, | 816 | .asic_reset = &r600_asic_reset, |
807 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 817 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
808 | .gart_set_page = &rs600_gart_set_page, | 818 | .gart_set_page = &rs600_gart_set_page, |
809 | .ring_test = &r600_ring_test, | ||
810 | .ring = { | 819 | .ring = { |
811 | [RADEON_RING_TYPE_GFX_INDEX] = { | 820 | [RADEON_RING_TYPE_GFX_INDEX] = { |
812 | .ib_execute = &r600_ring_ib_execute, | 821 | .ib_execute = &r600_ring_ib_execute, |
813 | .emit_fence = &r600_fence_ring_emit, | 822 | .emit_fence = &r600_fence_ring_emit, |
814 | .emit_semaphore = &r600_semaphore_ring_emit, | 823 | .emit_semaphore = &r600_semaphore_ring_emit, |
815 | .cs_parse = &r600_cs_parse, | 824 | .cs_parse = &r600_cs_parse, |
825 | .ring_test = &r600_ring_test, | ||
826 | .ib_test = &r600_ib_test, | ||
816 | } | 827 | } |
817 | }, | 828 | }, |
818 | .irq = { | 829 | .irq = { |
@@ -872,13 +883,14 @@ static struct radeon_asic rs780_asic = { | |||
872 | .asic_reset = &r600_asic_reset, | 883 | .asic_reset = &r600_asic_reset, |
873 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 884 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
874 | .gart_set_page = &rs600_gart_set_page, | 885 | .gart_set_page = &rs600_gart_set_page, |
875 | .ring_test = &r600_ring_test, | ||
876 | .ring = { | 886 | .ring = { |
877 | [RADEON_RING_TYPE_GFX_INDEX] = { | 887 | [RADEON_RING_TYPE_GFX_INDEX] = { |
878 | .ib_execute = &r600_ring_ib_execute, | 888 | .ib_execute = &r600_ring_ib_execute, |
879 | .emit_fence = &r600_fence_ring_emit, | 889 | .emit_fence = &r600_fence_ring_emit, |
880 | .emit_semaphore = &r600_semaphore_ring_emit, | 890 | .emit_semaphore = &r600_semaphore_ring_emit, |
881 | .cs_parse = &r600_cs_parse, | 891 | .cs_parse = &r600_cs_parse, |
892 | .ring_test = &r600_ring_test, | ||
893 | .ib_test = &r600_ib_test, | ||
882 | } | 894 | } |
883 | }, | 895 | }, |
884 | .irq = { | 896 | .irq = { |
@@ -938,13 +950,14 @@ static struct radeon_asic rv770_asic = { | |||
938 | .vga_set_state = &r600_vga_set_state, | 950 | .vga_set_state = &r600_vga_set_state, |
939 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, | 951 | .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
940 | .gart_set_page = &rs600_gart_set_page, | 952 | .gart_set_page = &rs600_gart_set_page, |
941 | .ring_test = &r600_ring_test, | ||
942 | .ring = { | 953 | .ring = { |
943 | [RADEON_RING_TYPE_GFX_INDEX] = { | 954 | [RADEON_RING_TYPE_GFX_INDEX] = { |
944 | .ib_execute = &r600_ring_ib_execute, | 955 | .ib_execute = &r600_ring_ib_execute, |
945 | .emit_fence = &r600_fence_ring_emit, | 956 | .emit_fence = &r600_fence_ring_emit, |
946 | .emit_semaphore = &r600_semaphore_ring_emit, | 957 | .emit_semaphore = &r600_semaphore_ring_emit, |
947 | .cs_parse = &r600_cs_parse, | 958 | .cs_parse = &r600_cs_parse, |
959 | .ring_test = &r600_ring_test, | ||
960 | .ib_test = &r600_ib_test, | ||
948 | } | 961 | } |
949 | }, | 962 | }, |
950 | .irq = { | 963 | .irq = { |
@@ -1004,13 +1017,14 @@ static struct radeon_asic evergreen_asic = { | |||
1004 | .vga_set_state = &r600_vga_set_state, | 1017 | .vga_set_state = &r600_vga_set_state, |
1005 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1018 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1006 | .gart_set_page = &rs600_gart_set_page, | 1019 | .gart_set_page = &rs600_gart_set_page, |
1007 | .ring_test = &r600_ring_test, | ||
1008 | .ring = { | 1020 | .ring = { |
1009 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1021 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1010 | .ib_execute = &evergreen_ring_ib_execute, | 1022 | .ib_execute = &evergreen_ring_ib_execute, |
1011 | .emit_fence = &r600_fence_ring_emit, | 1023 | .emit_fence = &r600_fence_ring_emit, |
1012 | .emit_semaphore = &r600_semaphore_ring_emit, | 1024 | .emit_semaphore = &r600_semaphore_ring_emit, |
1013 | .cs_parse = &evergreen_cs_parse, | 1025 | .cs_parse = &evergreen_cs_parse, |
1026 | .ring_test = &r600_ring_test, | ||
1027 | .ib_test = &r600_ib_test, | ||
1014 | } | 1028 | } |
1015 | }, | 1029 | }, |
1016 | .irq = { | 1030 | .irq = { |
@@ -1070,13 +1084,14 @@ static struct radeon_asic sumo_asic = { | |||
1070 | .vga_set_state = &r600_vga_set_state, | 1084 | .vga_set_state = &r600_vga_set_state, |
1071 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1085 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1072 | .gart_set_page = &rs600_gart_set_page, | 1086 | .gart_set_page = &rs600_gart_set_page, |
1073 | .ring_test = &r600_ring_test, | ||
1074 | .ring = { | 1087 | .ring = { |
1075 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1088 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1076 | .ib_execute = &evergreen_ring_ib_execute, | 1089 | .ib_execute = &evergreen_ring_ib_execute, |
1077 | .emit_fence = &r600_fence_ring_emit, | 1090 | .emit_fence = &r600_fence_ring_emit, |
1078 | .emit_semaphore = &r600_semaphore_ring_emit, | 1091 | .emit_semaphore = &r600_semaphore_ring_emit, |
1079 | .cs_parse = &evergreen_cs_parse, | 1092 | .cs_parse = &evergreen_cs_parse, |
1093 | .ring_test = &r600_ring_test, | ||
1094 | .ib_test = &r600_ib_test, | ||
1080 | }, | 1095 | }, |
1081 | }, | 1096 | }, |
1082 | .irq = { | 1097 | .irq = { |
@@ -1136,13 +1151,14 @@ static struct radeon_asic btc_asic = { | |||
1136 | .vga_set_state = &r600_vga_set_state, | 1151 | .vga_set_state = &r600_vga_set_state, |
1137 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1152 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1138 | .gart_set_page = &rs600_gart_set_page, | 1153 | .gart_set_page = &rs600_gart_set_page, |
1139 | .ring_test = &r600_ring_test, | ||
1140 | .ring = { | 1154 | .ring = { |
1141 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1155 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1142 | .ib_execute = &evergreen_ring_ib_execute, | 1156 | .ib_execute = &evergreen_ring_ib_execute, |
1143 | .emit_fence = &r600_fence_ring_emit, | 1157 | .emit_fence = &r600_fence_ring_emit, |
1144 | .emit_semaphore = &r600_semaphore_ring_emit, | 1158 | .emit_semaphore = &r600_semaphore_ring_emit, |
1145 | .cs_parse = &evergreen_cs_parse, | 1159 | .cs_parse = &evergreen_cs_parse, |
1160 | .ring_test = &r600_ring_test, | ||
1161 | .ib_test = &r600_ib_test, | ||
1146 | } | 1162 | } |
1147 | }, | 1163 | }, |
1148 | .irq = { | 1164 | .irq = { |
@@ -1212,7 +1228,6 @@ static struct radeon_asic cayman_asic = { | |||
1212 | .vga_set_state = &r600_vga_set_state, | 1228 | .vga_set_state = &r600_vga_set_state, |
1213 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, | 1229 | .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
1214 | .gart_set_page = &rs600_gart_set_page, | 1230 | .gart_set_page = &rs600_gart_set_page, |
1215 | .ring_test = &r600_ring_test, | ||
1216 | .ring = { | 1231 | .ring = { |
1217 | [RADEON_RING_TYPE_GFX_INDEX] = { | 1232 | [RADEON_RING_TYPE_GFX_INDEX] = { |
1218 | .ib_execute = &cayman_ring_ib_execute, | 1233 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1220,6 +1235,8 @@ static struct radeon_asic cayman_asic = { | |||
1220 | .emit_fence = &cayman_fence_ring_emit, | 1235 | .emit_fence = &cayman_fence_ring_emit, |
1221 | .emit_semaphore = &r600_semaphore_ring_emit, | 1236 | .emit_semaphore = &r600_semaphore_ring_emit, |
1222 | .cs_parse = &evergreen_cs_parse, | 1237 | .cs_parse = &evergreen_cs_parse, |
1238 | .ring_test = &r600_ring_test, | ||
1239 | .ib_test = &r600_ib_test, | ||
1223 | }, | 1240 | }, |
1224 | [CAYMAN_RING_TYPE_CP1_INDEX] = { | 1241 | [CAYMAN_RING_TYPE_CP1_INDEX] = { |
1225 | .ib_execute = &cayman_ring_ib_execute, | 1242 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1227,6 +1244,8 @@ static struct radeon_asic cayman_asic = { | |||
1227 | .emit_fence = &cayman_fence_ring_emit, | 1244 | .emit_fence = &cayman_fence_ring_emit, |
1228 | .emit_semaphore = &r600_semaphore_ring_emit, | 1245 | .emit_semaphore = &r600_semaphore_ring_emit, |
1229 | .cs_parse = &evergreen_cs_parse, | 1246 | .cs_parse = &evergreen_cs_parse, |
1247 | .ring_test = &r600_ring_test, | ||
1248 | .ib_test = &r600_ib_test, | ||
1230 | }, | 1249 | }, |
1231 | [CAYMAN_RING_TYPE_CP2_INDEX] = { | 1250 | [CAYMAN_RING_TYPE_CP2_INDEX] = { |
1232 | .ib_execute = &cayman_ring_ib_execute, | 1251 | .ib_execute = &cayman_ring_ib_execute, |
@@ -1234,6 +1253,8 @@ static struct radeon_asic cayman_asic = { | |||
1234 | .emit_fence = &cayman_fence_ring_emit, | 1253 | .emit_fence = &cayman_fence_ring_emit, |
1235 | .emit_semaphore = &r600_semaphore_ring_emit, | 1254 | .emit_semaphore = &r600_semaphore_ring_emit, |
1236 | .cs_parse = &evergreen_cs_parse, | 1255 | .cs_parse = &evergreen_cs_parse, |
1256 | .ring_test = &r600_ring_test, | ||
1257 | .ib_test = &r600_ib_test, | ||
1237 | } | 1258 | } |
1238 | }, | 1259 | }, |
1239 | .irq = { | 1260 | .irq = { |
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index fd8d5dabdb6c..b8f0a16bf65f 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -63,7 +63,7 @@ int r100_asic_reset(struct radeon_device *rdev); | |||
63 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); | 63 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); |
64 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); | 64 | void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
65 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); | 65 | int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
66 | void r100_ring_start(struct radeon_device *rdev); | 66 | void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
67 | int r100_irq_set(struct radeon_device *rdev); | 67 | int r100_irq_set(struct radeon_device *rdev); |
68 | int r100_irq_process(struct radeon_device *rdev); | 68 | int r100_irq_process(struct radeon_device *rdev); |
69 | void r100_fence_ring_emit(struct radeon_device *rdev, | 69 | void r100_fence_ring_emit(struct radeon_device *rdev, |
@@ -109,7 +109,7 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, | |||
109 | struct r100_gpu_lockup *lockup, | 109 | struct r100_gpu_lockup *lockup, |
110 | struct radeon_ring *cp); | 110 | struct radeon_ring *cp); |
111 | void r100_ib_fini(struct radeon_device *rdev); | 111 | void r100_ib_fini(struct radeon_device *rdev); |
112 | int r100_ib_test(struct radeon_device *rdev); | 112 | int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
113 | void r100_irq_disable(struct radeon_device *rdev); | 113 | void r100_irq_disable(struct radeon_device *rdev); |
114 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); | 114 | void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); |
115 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); | 115 | void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); |
@@ -161,7 +161,7 @@ extern int r300_suspend(struct radeon_device *rdev); | |||
161 | extern int r300_resume(struct radeon_device *rdev); | 161 | extern int r300_resume(struct radeon_device *rdev); |
162 | extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); | 162 | extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); |
163 | extern int r300_asic_reset(struct radeon_device *rdev); | 163 | extern int r300_asic_reset(struct radeon_device *rdev); |
164 | extern void r300_ring_start(struct radeon_device *rdev); | 164 | extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
165 | extern void r300_fence_ring_emit(struct radeon_device *rdev, | 165 | extern void r300_fence_ring_emit(struct radeon_device *rdev, |
166 | struct radeon_fence *fence); | 166 | struct radeon_fence *fence); |
167 | extern int r300_cs_parse(struct radeon_cs_parser *p); | 167 | extern int r300_cs_parse(struct radeon_cs_parser *p); |
@@ -273,7 +273,7 @@ int rv515_init(struct radeon_device *rdev); | |||
273 | void rv515_fini(struct radeon_device *rdev); | 273 | void rv515_fini(struct radeon_device *rdev); |
274 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); | 274 | uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
275 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); | 275 | void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
276 | void rv515_ring_start(struct radeon_device *rdev); | 276 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring); |
277 | void rv515_bandwidth_update(struct radeon_device *rdev); | 277 | void rv515_bandwidth_update(struct radeon_device *rdev); |
278 | int rv515_resume(struct radeon_device *rdev); | 278 | int rv515_resume(struct radeon_device *rdev); |
279 | int rv515_suspend(struct radeon_device *rdev); | 279 | int rv515_suspend(struct radeon_device *rdev); |
@@ -319,7 +319,7 @@ int r600_set_surface_reg(struct radeon_device *rdev, int reg, | |||
319 | uint32_t tiling_flags, uint32_t pitch, | 319 | uint32_t tiling_flags, uint32_t pitch, |
320 | uint32_t offset, uint32_t obj_size); | 320 | uint32_t offset, uint32_t obj_size); |
321 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); | 321 | void r600_clear_surface_reg(struct radeon_device *rdev, int reg); |
322 | int r600_ib_test(struct radeon_device *rdev, int ring); | 322 | int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring); |
323 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); | 323 | void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
324 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); | 324 | int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
325 | int r600_copy_blit(struct radeon_device *rdev, | 325 | int r600_copy_blit(struct radeon_device *rdev, |
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index b0ce84a20a68..5280c87d5955 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -430,7 +430,7 @@ static int rs400_startup(struct radeon_device *rdev) | |||
430 | if (r) | 430 | if (r) |
431 | return r; | 431 | return r; |
432 | 432 | ||
433 | r = r100_ib_test(rdev); | 433 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
434 | if (r) { | 434 | if (r) { |
435 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 435 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
436 | rdev->accel_working = false; | 436 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index fdb56b44dcd0..b07d297b0b4f 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -885,7 +885,7 @@ static int rs600_startup(struct radeon_device *rdev) | |||
885 | if (r) | 885 | if (r) |
886 | return r; | 886 | return r; |
887 | 887 | ||
888 | r = r100_ib_test(rdev); | 888 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
889 | if (r) { | 889 | if (r) { |
890 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 890 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
891 | rdev->accel_working = false; | 891 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 29fc8b1506a4..6aa65032d3cb 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -647,7 +647,7 @@ static int rs690_startup(struct radeon_device *rdev) | |||
647 | if (r) | 647 | if (r) |
648 | return r; | 648 | return r; |
649 | 649 | ||
650 | r = r100_ib_test(rdev); | 650 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
651 | if (r) { | 651 | if (r) { |
652 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 652 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
653 | rdev->accel_working = false; | 653 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 880637fd1946..9e1b159bbb7f 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -53,9 +53,8 @@ void rv515_debugfs(struct radeon_device *rdev) | |||
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
56 | void rv515_ring_start(struct radeon_device *rdev) | 56 | void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring) |
57 | { | 57 | { |
58 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; | ||
59 | int r; | 58 | int r; |
60 | 59 | ||
61 | r = radeon_ring_lock(rdev, ring, 64); | 60 | r = radeon_ring_lock(rdev, ring, 64); |
@@ -413,7 +412,7 @@ static int rv515_startup(struct radeon_device *rdev) | |||
413 | if (r) | 412 | if (r) |
414 | return r; | 413 | return r; |
415 | 414 | ||
416 | r = r100_ib_test(rdev); | 415 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
417 | if (r) { | 416 | if (r) { |
418 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); | 417 | dev_err(rdev->dev, "failed testing IB (%d).\n", r); |
419 | rdev->accel_working = false; | 418 | rdev->accel_working = false; |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index a86698137df4..6f2cbfb18292 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1114,7 +1114,7 @@ static int rv770_startup(struct radeon_device *rdev) | |||
1114 | if (r) | 1114 | if (r) |
1115 | return r; | 1115 | return r; |
1116 | 1116 | ||
1117 | r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX); | 1117 | r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); |
1118 | if (r) { | 1118 | if (r) { |
1119 | dev_err(rdev->dev, "IB test failed (%d).\n", r); | 1119 | dev_err(rdev->dev, "IB test failed (%d).\n", r); |
1120 | rdev->accel_working = false; | 1120 | rdev->accel_working = false; |