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authorMauro Carvalho Chehab <mchehab@redhat.com>2011-10-20 17:18:01 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-11-01 08:01:53 -0400
commiteebf11a0166f011c5945dd30fd1779afca6c964e (patch)
tree4d7f4940ca6aff78ef29f7b94c94c176a8c42aae
parent5f032119d6f1cc48d0d1a28b8014f270ca4c4e47 (diff)
edac: Add an experimental new driver to support Sandy Bridge CPU's
This driver is known to work on mine and Tony's test environments, using software error injection, and a partial hardware/software error injection tool. There's no broader range test yet to double check if the error decoding logic will actually point to the right DIMM, so use it with care. More tests are required to be sure that the driver will work on all different types of memory configurations. If you're willing to risk using it, I suggest you to enable EDAC debugs for your test machines, as the debug logs helps to track what's going inside the driver. Please feed me with bug reports, if you notice that the driver is miss-behaving. Tested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/edac/sb_edac.c1894
1 files changed, 1894 insertions, 0 deletions
diff --git a/drivers/edac/sb_edac.c b/drivers/edac/sb_edac.c
new file mode 100644
index 000000000000..785c2769f05b
--- /dev/null
+++ b/drivers/edac/sb_edac.c
@@ -0,0 +1,1894 @@
1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *
9 * Copyright (c) 2011 by:
10 * Mauro Carvalho Chehab <mchehab@redhat.com>
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/pci_ids.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/edac.h>
20#include <linux/mmzone.h>
21#include <linux/edac_mce.h>
22#include <linux/smp.h>
23#include <linux/bitmap.h>
24#include <asm/processor.h>
25
26#include "edac_core.h"
27
28/* Static vars */
29static LIST_HEAD(sbridge_edac_list);
30static DEFINE_MUTEX(sbridge_edac_lock);
31static int probed;
32
33/*
34 * Alter this version for the module when modifications are made
35 */
36#define SBRIDGE_REVISION " Ver: 1.0.0 "
37#define EDAC_MOD_STR "sbridge_edac"
38
39/*
40 * Debug macros
41 */
42#define sbridge_printk(level, fmt, arg...) \
43 edac_printk(level, "sbridge", fmt, ##arg)
44
45#define sbridge_mc_printk(mci, level, fmt, arg...) \
46 edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg)
47
48/*
49 * Get a bit field at register value <v>, from bit <lo> to bit <hi>
50 */
51#define GET_BITFIELD(v, lo, hi) \
52 (((v) & ((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) >> (lo))
53
54/*
55 * sbridge Memory Controller Registers
56 */
57
58/*
59 * FIXME: For now, let's order by device function, as it makes
60 * easier for driver's development proccess. This table should be
61 * moved to pci_id.h when submitted upstream
62 */
63#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0 0x3cf4 /* 12.6 */
64#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1 0x3cf6 /* 12.7 */
65#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR 0x3cf5 /* 13.6 */
66#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0 0x3ca0 /* 14.0 */
67#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA 0x3ca8 /* 15.0 */
68#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS 0x3c71 /* 15.1 */
69#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0 0x3caa /* 15.2 */
70#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1 0x3cab /* 15.3 */
71#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2 0x3cac /* 15.4 */
72#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3 0x3cad /* 15.5 */
73#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO 0x3cb8 /* 17.0 */
74
75 /*
76 * Currently, unused, but will be needed in the future
77 * implementations, as they hold the error counters
78 */
79#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0 0x3c72 /* 16.2 */
80#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1 0x3c73 /* 16.3 */
81#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR2 0x3c76 /* 16.6 */
82#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR3 0x3c77 /* 16.7 */
83
84/* Devices 12 Function 6, Offsets 0x80 to 0xcc */
85static const u32 dram_rule[] = {
86 0x80, 0x88, 0x90, 0x98, 0xa0,
87 0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
88};
89#define MAX_SAD ARRAY_SIZE(dram_rule)
90
91#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
92#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
93#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
94#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
95
96static char *get_dram_attr(u32 reg)
97{
98 switch(DRAM_ATTR(reg)) {
99 case 0:
100 return "DRAM";
101 case 1:
102 return "MMCFG";
103 case 2:
104 return "NXM";
105 default:
106 return "unknown";
107 }
108}
109
110static const u32 interleave_list[] = {
111 0x84, 0x8c, 0x94, 0x9c, 0xa4,
112 0xac, 0xb4, 0xbc, 0xc4, 0xcc,
113};
114#define MAX_INTERLEAVE ARRAY_SIZE(interleave_list)
115
116#define SAD_PKG0(reg) GET_BITFIELD(reg, 0, 2)
117#define SAD_PKG1(reg) GET_BITFIELD(reg, 3, 5)
118#define SAD_PKG2(reg) GET_BITFIELD(reg, 8, 10)
119#define SAD_PKG3(reg) GET_BITFIELD(reg, 11, 13)
120#define SAD_PKG4(reg) GET_BITFIELD(reg, 16, 18)
121#define SAD_PKG5(reg) GET_BITFIELD(reg, 19, 21)
122#define SAD_PKG6(reg) GET_BITFIELD(reg, 24, 26)
123#define SAD_PKG7(reg) GET_BITFIELD(reg, 27, 29)
124
125static inline int sad_pkg(u32 reg, int interleave)
126{
127 switch (interleave) {
128 case 0:
129 return SAD_PKG0(reg);
130 case 1:
131 return SAD_PKG1(reg);
132 case 2:
133 return SAD_PKG2(reg);
134 case 3:
135 return SAD_PKG3(reg);
136 case 4:
137 return SAD_PKG4(reg);
138 case 5:
139 return SAD_PKG5(reg);
140 case 6:
141 return SAD_PKG6(reg);
142 case 7:
143 return SAD_PKG7(reg);
144 default:
145 return -EINVAL;
146 }
147}
148
149/* Devices 12 Function 7 */
150
151#define TOLM 0x80
152#define TOHM 0x84
153
154#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
155#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
156
157/* Device 13 Function 6 */
158
159#define SAD_TARGET 0xf0
160
161#define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11)
162
163#define SAD_CONTROL 0xf4
164
165#define NODE_ID(reg) GET_BITFIELD(reg, 0, 2)
166
167/* Device 14 function 0 */
168
169static const u32 tad_dram_rule[] = {
170 0x40, 0x44, 0x48, 0x4c,
171 0x50, 0x54, 0x58, 0x5c,
172 0x60, 0x64, 0x68, 0x6c,
173};
174#define MAX_TAD ARRAY_SIZE(tad_dram_rule)
175
176#define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff)
177#define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11)
178#define TAD_CH(reg) GET_BITFIELD(reg, 8, 9)
179#define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7)
180#define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5)
181#define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3)
182#define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1)
183
184/* Device 15, function 0 */
185
186#define MCMTR 0x7c
187
188#define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2)
189#define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1)
190#define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0)
191
192/* Device 15, function 1 */
193
194#define RASENABLES 0xac
195#define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0)
196
197/* Device 15, functions 2-5 */
198
199static const int mtr_regs[] = {
200 0x80, 0x84, 0x88,
201};
202
203#define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19)
204#define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14)
205#define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13)
206#define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4)
207#define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1)
208
209static const u32 tad_ch_nilv_offset[] = {
210 0x90, 0x94, 0x98, 0x9c,
211 0xa0, 0xa4, 0xa8, 0xac,
212 0xb0, 0xb4, 0xb8, 0xbc,
213};
214#define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29)
215#define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26)
216
217static const u32 rir_way_limit[] = {
218 0x108, 0x10c, 0x110, 0x114, 0x118,
219};
220#define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit)
221
222#define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31)
223#define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29)
224#define RIR_LIMIT(reg) ((GET_BITFIELD(reg, 1, 10) << 29)| 0x1fffffff)
225
226#define MAX_RIR_WAY 8
227
228static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = {
229 { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c },
230 { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c },
231 { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c },
232 { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c },
233 { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc },
234};
235
236#define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19)
237#define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14)
238
239/* Device 16, functions 2-7 */
240
241/*
242 * FIXME: Implement the error count reads directly
243 */
244
245static const u32 correrrcnt[] = {
246 0x104, 0x108, 0x10c, 0x110,
247};
248
249#define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31)
250#define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30)
251#define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15)
252#define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14)
253
254static const u32 correrrthrsld[] = {
255 0x11c, 0x120, 0x124, 0x128,
256};
257
258#define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30)
259#define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14)
260
261
262/* Device 17, function 0 */
263
264#define RANK_CFG_A 0x0328
265
266#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
267
268/*
269 * sbridge structs
270 */
271
272#define NUM_CHANNELS 4
273#define MAX_DIMMS 3 /* Max DIMMS per channel */
274
275struct sbridge_info {
276 u32 mcmtr;
277};
278
279struct sbridge_channel {
280 u32 ranks;
281 u32 dimms;
282};
283
284struct pci_id_descr {
285 int dev;
286 int func;
287 int dev_id;
288 int optional;
289};
290
291struct pci_id_table {
292 const struct pci_id_descr *descr;
293 int n_devs;
294};
295
296struct sbridge_dev {
297 struct list_head list;
298 u8 bus, mc;
299 u8 node_id, source_id;
300 struct pci_dev **pdev;
301 int n_devs;
302 struct mem_ctl_info *mci;
303};
304
305struct sbridge_pvt {
306 struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
307 struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
308 struct pci_dev *pci_br;
309 struct pci_dev *pci_tad[NUM_CHANNELS];
310
311 struct sbridge_dev *sbridge_dev;
312
313 struct sbridge_info info;
314 struct sbridge_channel channel[NUM_CHANNELS];
315
316 int csrow_map[NUM_CHANNELS][MAX_DIMMS];
317
318 /* Memory type detection */
319 bool is_mirrored, is_lockstep, is_close_pg;
320
321 /* mcelog glue */
322 struct edac_mce edac_mce;
323
324 /* Fifo double buffers */
325 struct mce mce_entry[MCE_LOG_LEN];
326 struct mce mce_outentry[MCE_LOG_LEN];
327
328 /* Fifo in/out counters */
329 unsigned mce_in, mce_out;
330
331 /* Count indicator to show errors not got */
332 unsigned mce_overrun;
333
334 /* Memory description */
335 u64 tolm, tohm;
336};
337
338#define PCI_DESCR(device, function, device_id) \
339 .dev = (device), \
340 .func = (function), \
341 .dev_id = (device_id)
342
343static const struct pci_id_descr pci_dev_descr_sbridge[] = {
344 /* Processor Home Agent */
345 { PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_HA0) },
346
347 /* Memory controller */
348 { PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA) },
349 { PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS) },
350 { PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD0) },
351 { PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1) },
352 { PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2) },
353 { PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3) },
354 { PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO) },
355
356 /* System Address Decoder */
357 { PCI_DESCR(12, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0) },
358 { PCI_DESCR(12, 7, PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1) },
359
360 /* Broadcast Registers */
361 { PCI_DESCR(13, 6, PCI_DEVICE_ID_INTEL_SBRIDGE_BR) },
362};
363
364#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
365static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
366 PCI_ID_TABLE_ENTRY(pci_dev_descr_sbridge),
367 {0,} /* 0 terminated list. */
368};
369
370/*
371 * pci_device_id table for which devices we are looking for
372 */
373static const struct pci_device_id sbridge_pci_tbl[] __devinitdata = {
374 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
375 {0,} /* 0 terminated list. */
376};
377
378
379/****************************************************************************
380 Anciliary status routines
381 ****************************************************************************/
382
383static inline int numrank(u32 mtr)
384{
385 int ranks = (1 << RANK_CNT_BITS(mtr));
386
387 if (ranks > 4) {
388 debugf0("Invalid number of ranks: %d (max = 4) raw value = %x (%04x)",
389 ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
390 return -EINVAL;
391 }
392
393 return ranks;
394}
395
396static inline int numrow(u32 mtr)
397{
398 int rows = (RANK_WIDTH_BITS(mtr) + 12);
399
400 if (rows < 13 || rows > 18) {
401 debugf0("Invalid number of rows: %d (should be between 14 and 17) raw value = %x (%04x)",
402 rows, (unsigned int)RANK_WIDTH_BITS(mtr), mtr);
403 return -EINVAL;
404 }
405
406 return 1 << rows;
407}
408
409static inline int numcol(u32 mtr)
410{
411 int cols = (COL_WIDTH_BITS(mtr) + 10);
412
413 if (cols > 12) {
414 debugf0("Invalid number of cols: %d (max = 4) raw value = %x (%04x)",
415 cols, (unsigned int)COL_WIDTH_BITS(mtr), mtr);
416 return -EINVAL;
417 }
418
419 return 1 << cols;
420}
421
422static struct sbridge_dev *get_sbridge_dev(u8 bus)
423{
424 struct sbridge_dev *sbridge_dev;
425
426 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
427 if (sbridge_dev->bus == bus)
428 return sbridge_dev;
429 }
430
431 return NULL;
432}
433
434static struct sbridge_dev *alloc_sbridge_dev(u8 bus,
435 const struct pci_id_table *table)
436{
437 struct sbridge_dev *sbridge_dev;
438
439 sbridge_dev = kzalloc(sizeof(*sbridge_dev), GFP_KERNEL);
440 if (!sbridge_dev)
441 return NULL;
442
443 sbridge_dev->pdev = kzalloc(sizeof(*sbridge_dev->pdev) * table->n_devs,
444 GFP_KERNEL);
445 if (!sbridge_dev->pdev) {
446 kfree(sbridge_dev);
447 return NULL;
448 }
449
450 sbridge_dev->bus = bus;
451 sbridge_dev->n_devs = table->n_devs;
452 list_add_tail(&sbridge_dev->list, &sbridge_edac_list);
453
454 return sbridge_dev;
455}
456
457static void free_sbridge_dev(struct sbridge_dev *sbridge_dev)
458{
459 list_del(&sbridge_dev->list);
460 kfree(sbridge_dev->pdev);
461 kfree(sbridge_dev);
462}
463
464/****************************************************************************
465 Memory check routines
466 ****************************************************************************/
467static struct pci_dev *get_pdev_slot_func(u8 bus, unsigned slot,
468 unsigned func)
469{
470 struct sbridge_dev *sbridge_dev = get_sbridge_dev(bus);
471 int i;
472
473 if (!sbridge_dev)
474 return NULL;
475
476 for (i = 0; i < sbridge_dev->n_devs; i++) {
477 if (!sbridge_dev->pdev[i])
478 continue;
479
480 if (PCI_SLOT(sbridge_dev->pdev[i]->devfn) == slot &&
481 PCI_FUNC(sbridge_dev->pdev[i]->devfn) == func) {
482 debugf1("Associated %02x.%02x.%d with %p\n",
483 bus, slot, func, sbridge_dev->pdev[i]);
484 return sbridge_dev->pdev[i];
485 }
486 }
487
488 return NULL;
489}
490
491/**
492 * sbridge_get_active_channels() - gets the number of channels and csrows
493 * bus: Device bus
494 * @channels: Number of channels that will be returned
495 * @csrows: Number of csrows found
496 *
497 * Since EDAC core needs to know in advance the number of available channels
498 * and csrows, in order to allocate memory for csrows/channels, it is needed
499 * to run two similar steps. At the first step, implemented on this function,
500 * it checks the number of csrows/channels present at one socket, identified
501 * by the associated PCI bus.
502 * this is used in order to properly allocate the size of mci components.
503 * Note: one csrow is one dimm.
504 */
505static int sbridge_get_active_channels(const u8 bus, unsigned *channels,
506 unsigned *csrows)
507{
508 struct pci_dev *pdev = NULL;
509 int i, j;
510 u32 mcmtr;
511
512 *channels = 0;
513 *csrows = 0;
514
515 pdev = get_pdev_slot_func(bus, 15, 0);
516 if (!pdev) {
517 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
518 "%2x.%02d.%d!!!\n",
519 bus, 15, 0);
520 return -ENODEV;
521 }
522
523 pci_read_config_dword(pdev, MCMTR, &mcmtr);
524 if (!IS_ECC_ENABLED(mcmtr)) {
525 sbridge_printk(KERN_ERR, "ECC is disabled. Aborting\n");
526 return -ENODEV;
527 }
528
529 for (i = 0; i < NUM_CHANNELS; i++) {
530 u32 mtr;
531
532 /* Device 15 functions 2 - 5 */
533 pdev = get_pdev_slot_func(bus, 15, 2 + i);
534 if (!pdev) {
535 sbridge_printk(KERN_ERR, "Couldn't find PCI device "
536 "%2x.%02d.%d!!!\n",
537 bus, 15, 2 + i);
538 return -ENODEV;
539 }
540 (*channels)++;
541
542 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
543 pci_read_config_dword(pdev, mtr_regs[j], &mtr);
544 debugf1("Bus#%02x channel #%d MTR%d = %x\n", bus, i, j, mtr);
545 if (IS_DIMM_PRESENT(mtr))
546 (*csrows)++;
547 }
548 }
549
550 debugf0("Number of active channels: %d, number of active dimms: %d\n",
551 *channels, *csrows);
552
553 return 0;
554}
555
556static int get_dimm_config(const struct mem_ctl_info *mci)
557{
558 struct sbridge_pvt *pvt = mci->pvt_info;
559 struct csrow_info *csr;
560 int i, j, banks, ranks, rows, cols, size, npages;
561 int csrow = 0;
562 unsigned long last_page = 0;
563 u32 reg;
564 enum edac_type mode;
565
566 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
567 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
568
569 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
570 pvt->sbridge_dev->node_id = NODE_ID(reg);
571 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
572 pvt->sbridge_dev->mc,
573 pvt->sbridge_dev->node_id,
574 pvt->sbridge_dev->source_id);
575
576 pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg);
577 if (IS_MIRROR_ENABLED(reg)) {
578 debugf0("Memory mirror is enabled\n");
579 pvt->is_mirrored = true;
580 } else {
581 debugf0("Memory mirror is disabled\n");
582 pvt->is_mirrored = false;
583 }
584
585 pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr);
586 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
587 debugf0("Lockstep is enabled\n");
588 mode = EDAC_S8ECD8ED;
589 pvt->is_lockstep = true;
590 } else {
591 debugf0("Lockstep is disabled\n");
592 mode = EDAC_S4ECD4ED;
593 pvt->is_lockstep = false;
594 }
595 if (IS_CLOSE_PG(pvt->info.mcmtr)) {
596 debugf0("address map is on closed page mode\n");
597 pvt->is_close_pg = true;
598 } else {
599 debugf0("address map is on open page mode\n");
600 pvt->is_close_pg = false;
601 }
602
603 pci_read_config_dword(pvt->pci_ta, RANK_CFG_A, &reg);
604 if (IS_RDIMM_ENABLED(reg)) {
605 /* FIXME: Can also be LRDIMM */
606 debugf0("Memory is registered\n");
607 mode = MEM_RDDR3;
608 } else {
609 debugf0("Memory is unregistered\n");
610 mode = MEM_DDR3;
611 }
612
613 /* On all supported DDR3 DIMM types, there are 8 banks available */
614 banks = 8;
615
616 for (i = 0; i < NUM_CHANNELS; i++) {
617 u32 mtr;
618
619 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
620 pci_read_config_dword(pvt->pci_tad[i],
621 mtr_regs[j], &mtr);
622 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
623 if (IS_DIMM_PRESENT(mtr)) {
624 pvt->channel[i].dimms++;
625
626 ranks = numrank(mtr);
627 rows = numrow(mtr);
628 cols = numcol(mtr);
629
630 /* DDR3 has 8 I/O banks */
631 size = (rows * cols * banks * ranks) >> (20 - 3);
632 npages = MiB_TO_PAGES(size);
633
634 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
635 pvt->sbridge_dev->mc, i, j,
636 size, npages,
637 banks, ranks, rows, cols);
638 csr = &mci->csrows[csrow];
639
640 csr->first_page = last_page;
641 csr->last_page = last_page + npages - 1;
642 csr->page_mask = 0UL; /* Unused */
643 csr->nr_pages = npages;
644 csr->grain = 32;
645 csr->csrow_idx = csrow;
646 csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
647 csr->ce_count = 0;
648 csr->ue_count = 0;
649 csr->mtype = mode;
650 csr->edac_mode = mode;
651 csr->nr_channels = 1;
652 csr->channels[0].chan_idx = i;
653 csr->channels[0].ce_count = 0;
654 pvt->csrow_map[i][j] = csrow;
655 snprintf(csr->channels[0].label,
656 sizeof(csr->channels[0].label),
657 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
658 pvt->sbridge_dev->source_id, i, j);
659 last_page += npages;
660 csrow++;
661 }
662 }
663 }
664
665 return 0;
666}
667
668static void get_memory_layout(const struct mem_ctl_info *mci)
669{
670 struct sbridge_pvt *pvt = mci->pvt_info;
671 int i, j, k, n_sads, n_tads, sad_interl;
672 u32 reg;
673 u64 limit, prv = 0;
674 u64 tmp_mb;
675 u32 rir_way;
676
677 /*
678 * Step 1) Get TOLM/TOHM ranges
679 */
680
681 /* Address range is 32:28 */
682 pci_read_config_dword(pvt->pci_sad1, TOLM,
683 &reg);
684 pvt->tolm = GET_TOLM(reg);
685 tmp_mb = (1 + pvt->tolm) >> 20;
686
687 debugf0("TOLM: %Lu.%03Lu GB (0x%016Lx)\n",
688 tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tolm);
689
690 /* Address range is already 45:25 */
691 pci_read_config_dword(pvt->pci_sad1, TOHM,
692 &reg);
693 pvt->tohm = GET_TOHM(reg);
694 tmp_mb = (1 + pvt->tohm) >> 20;
695
696 debugf0("TOHM: %Lu.%03Lu GB (0x%016Lx)",
697 tmp_mb / 1000, tmp_mb % 1000, (u64)pvt->tohm);
698
699 /*
700 * Step 2) Get SAD range and SAD Interleave list
701 * TAD registers contain the interleave wayness. However, it
702 * seems simpler to just discover it indirectly, with the
703 * algorithm bellow.
704 */
705 prv = 0;
706 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
707 /* SAD_LIMIT Address range is 45:26 */
708 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
709 &reg);
710 limit = SAD_LIMIT(reg);
711
712 if (!DRAM_RULE_ENABLE(reg))
713 continue;
714
715 if (limit <= prv)
716 break;
717
718 tmp_mb = (limit + 1) >> 20;
719 debugf0("SAD#%d %s up to %Lu.%03Lu GB (0x%016Lx) %s reg=0x%08x\n",
720 n_sads,
721 get_dram_attr(reg),
722 tmp_mb / 1000, tmp_mb % 1000,
723 ((u64)tmp_mb) << 20L,
724 INTERLEAVE_MODE(reg) ? "Interleave: 8:6" : "Interleave: [8:6]XOR[18:16]",
725 reg);
726 prv = limit;
727
728 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
729 &reg);
730 sad_interl = sad_pkg(reg, 0);
731 for (j = 0; j < 8; j++) {
732 if (j > 0 && sad_interl == sad_pkg(reg, j))
733 break;
734
735 debugf0("SAD#%d, interleave #%d: %d\n",
736 n_sads, j, sad_pkg(reg, j));
737 }
738 }
739
740 /*
741 * Step 3) Get TAD range
742 */
743 prv = 0;
744 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
745 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
746 &reg);
747 limit = TAD_LIMIT(reg);
748 if (limit <= prv)
749 break;
750 tmp_mb = (limit + 1) >> 20;
751
752 debugf0("TAD#%d: up to %Lu.%03Lu GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT: %d, %d, %d, %d, reg=0x%08x\n",
753 n_tads, tmp_mb / 1000, tmp_mb % 1000,
754 ((u64)tmp_mb) << 20L,
755 (u32)TAD_SOCK(reg),
756 (u32)TAD_CH(reg),
757 (u32)TAD_TGT0(reg),
758 (u32)TAD_TGT1(reg),
759 (u32)TAD_TGT2(reg),
760 (u32)TAD_TGT3(reg),
761 reg);
762 prv = tmp_mb;
763 }
764
765 /*
766 * Step 4) Get TAD offsets, per each channel
767 */
768 for (i = 0; i < NUM_CHANNELS; i++) {
769 if (!pvt->channel[i].dimms)
770 continue;
771 for (j = 0; j < n_tads; j++) {
772 pci_read_config_dword(pvt->pci_tad[i],
773 tad_ch_nilv_offset[j],
774 &reg);
775 tmp_mb = TAD_OFFSET(reg) >> 20;
776 debugf0("TAD CH#%d, offset #%d: %Lu.%03Lu GB (0x%016Lx), reg=0x%08x\n",
777 i, j,
778 tmp_mb / 1000, tmp_mb % 1000,
779 ((u64)tmp_mb) << 20L,
780 reg);
781 }
782 }
783
784 /*
785 * Step 6) Get RIR Wayness/Limit, per each channel
786 */
787 for (i = 0; i < NUM_CHANNELS; i++) {
788 if (!pvt->channel[i].dimms)
789 continue;
790 for (j = 0; j < MAX_RIR_RANGES; j++) {
791 pci_read_config_dword(pvt->pci_tad[i],
792 rir_way_limit[j],
793 &reg);
794
795 if (!IS_RIR_VALID(reg))
796 continue;
797
798 tmp_mb = RIR_LIMIT(reg) >> 20;
799 rir_way = 1 << RIR_WAY(reg);
800 debugf0("CH#%d RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d, reg=0x%08x\n",
801 i, j,
802 tmp_mb / 1000, tmp_mb % 1000,
803 ((u64)tmp_mb) << 20L,
804 rir_way,
805 reg);
806
807 for (k = 0; k < rir_way; k++) {
808 pci_read_config_dword(pvt->pci_tad[i],
809 rir_offset[j][k],
810 &reg);
811 tmp_mb = RIR_OFFSET(reg) << 6;
812
813 debugf0("CH#%d RIR#%d INTL#%d, offset %Lu.%03Lu GB (0x%016Lx), tgt: %d, reg=0x%08x\n",
814 i, j, k,
815 tmp_mb / 1000, tmp_mb % 1000,
816 ((u64)tmp_mb) << 20L,
817 (u32)RIR_RNK_TGT(reg),
818 reg);
819 }
820 }
821 }
822}
823
824struct mem_ctl_info *get_mci_for_node_id(u8 node_id)
825{
826 struct sbridge_dev *sbridge_dev;
827
828 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
829 if (sbridge_dev->node_id == node_id)
830 return sbridge_dev->mci;
831 }
832 return NULL;
833}
834
835static int get_memory_error_data(struct mem_ctl_info *mci,
836 u64 addr,
837 u8 *socket,
838 long *channel_mask,
839 u8 *rank,
840 char *area_type)
841{
842 struct mem_ctl_info *new_mci;
843 struct sbridge_pvt *pvt = mci->pvt_info;
844 char msg[256];
845 int n_rir, n_sads, n_tads, sad_way, sck_xch;
846 int sad_interl, idx, base_ch;
847 int interleave_mode;
848 unsigned sad_interleave[MAX_INTERLEAVE];
849 u32 reg;
850 u8 ch_way,sck_way;
851 u32 tad_offset;
852 u32 rir_way;
853 u64 ch_addr, offset, limit, prv = 0;
854
855
856 /*
857 * Step 0) Check if the address is at special memory ranges
858 * The check bellow is probably enough to fill all cases where
859 * the error is not inside a memory, except for the legacy
860 * range (e. g. VGA addresses). It is unlikely, however, that the
861 * memory controller would generate an error on that range.
862 */
863 if ((addr > (u64) pvt->tolm) && (addr < (1L << 32))) {
864 sprintf(msg, "Error at TOLM area, on addr 0x%08Lx", addr);
865 edac_mc_handle_ce_no_info(mci, msg);
866 return -EINVAL;
867 }
868 if (addr >= (u64)pvt->tohm) {
869 sprintf(msg, "Error at MMIOH area, on addr 0x%016Lx", addr);
870 edac_mc_handle_ce_no_info(mci, msg);
871 return -EINVAL;
872 }
873
874 /*
875 * Step 1) Get socket
876 */
877 for (n_sads = 0; n_sads < MAX_SAD; n_sads++) {
878 pci_read_config_dword(pvt->pci_sad0, dram_rule[n_sads],
879 &reg);
880
881 if (!DRAM_RULE_ENABLE(reg))
882 continue;
883
884 limit = SAD_LIMIT(reg);
885 if (limit <= prv) {
886 sprintf(msg, "Can't discover the memory socket");
887 edac_mc_handle_ce_no_info(mci, msg);
888 return -EINVAL;
889 }
890 if (addr <= limit)
891 break;
892 prv = limit;
893 }
894 if (n_sads == MAX_SAD) {
895 sprintf(msg, "Can't discover the memory socket");
896 edac_mc_handle_ce_no_info(mci, msg);
897 return -EINVAL;
898 }
899 area_type = get_dram_attr(reg);
900 interleave_mode = INTERLEAVE_MODE(reg);
901
902 pci_read_config_dword(pvt->pci_sad0, interleave_list[n_sads],
903 &reg);
904 sad_interl = sad_pkg(reg, 0);
905 for (sad_way = 0; sad_way < 8; sad_way++) {
906 if (sad_way > 0 && sad_interl == sad_pkg(reg, sad_way))
907 break;
908 sad_interleave[sad_way] = sad_pkg(reg, sad_way);
909 debugf0("SAD interleave #%d: %d\n",
910 sad_way, sad_interleave[sad_way]);
911 }
912 debugf0("mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
913 pvt->sbridge_dev->mc,
914 n_sads,
915 addr,
916 limit,
917 sad_way + 7,
918 INTERLEAVE_MODE(reg) ? "" : "XOR[18:16]");
919 if (interleave_mode)
920 idx = ((addr >> 6) ^ (addr >> 16)) & 7;
921 else
922 idx = (addr >> 6) & 7;
923 switch (sad_way) {
924 case 1:
925 idx = 0;
926 break;
927 case 2:
928 idx = idx & 1;
929 break;
930 case 4:
931 idx = idx & 3;
932 break;
933 case 8:
934 break;
935 default:
936 sprintf(msg, "Can't discover socket interleave");
937 edac_mc_handle_ce_no_info(mci, msg);
938 return -EINVAL;
939 }
940 *socket = sad_interleave[idx];
941 debugf0("SAD interleave index: %d (wayness %d) = CPU socket %d\n",
942 idx, sad_way, *socket);
943
944 /*
945 * Move to the proper node structure, in order to access the
946 * right PCI registers
947 */
948 new_mci = get_mci_for_node_id(*socket);
949 if (!new_mci) {
950 sprintf(msg, "Struct for socket #%u wasn't initialized",
951 *socket);
952 edac_mc_handle_ce_no_info(mci, msg);
953 return -EINVAL;
954 }
955 mci = new_mci;
956 pvt = mci->pvt_info;
957
958 /*
959 * Step 2) Get memory channel
960 */
961 prv = 0;
962 for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
963 pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
964 &reg);
965 limit = TAD_LIMIT(reg);
966 if (limit <= prv) {
967 sprintf(msg, "Can't discover the memory channel");
968 edac_mc_handle_ce_no_info(mci, msg);
969 return -EINVAL;
970 }
971 if (addr <= limit)
972 break;
973 prv = limit;
974 }
975 ch_way = TAD_CH(reg) + 1;
976 sck_way = TAD_SOCK(reg) + 1;
977 /*
978 * FIXME: Is it right to always use channel 0 for offsets?
979 */
980 pci_read_config_dword(pvt->pci_tad[0],
981 tad_ch_nilv_offset[n_tads],
982 &tad_offset);
983
984 if (ch_way == 3)
985 idx = addr >> 6;
986 else
987 idx = addr >> (6 + sck_way);
988 idx = idx % ch_way;
989
990 /*
991 * FIXME: Shouldn't we use CHN_IDX_OFFSET() here, when ch_way == 3 ???
992 */
993 switch (idx) {
994 case 0:
995 base_ch = TAD_TGT0(reg);
996 break;
997 case 1:
998 base_ch = TAD_TGT1(reg);
999 break;
1000 case 2:
1001 base_ch = TAD_TGT2(reg);
1002 break;
1003 case 3:
1004 base_ch = TAD_TGT3(reg);
1005 break;
1006 default:
1007 sprintf(msg, "Can't discover the TAD target");
1008 edac_mc_handle_ce_no_info(mci, msg);
1009 return -EINVAL;
1010 }
1011 *channel_mask = 1 << base_ch;
1012
1013 if (pvt->is_mirrored) {
1014 *channel_mask |= 1 << ((base_ch + 2) % 4);
1015 switch(ch_way) {
1016 case 2:
1017 case 4:
1018 sck_xch = 1 << sck_way * (ch_way >> 1);
1019 break;
1020 default:
1021 sprintf(msg, "Invalid mirror set. Can't decode addr");
1022 edac_mc_handle_ce_no_info(mci, msg);
1023 return -EINVAL;
1024 }
1025 } else
1026 sck_xch = (1 << sck_way) * ch_way;
1027
1028 if (pvt->is_lockstep)
1029 *channel_mask |= 1 << ((base_ch + 1) % 4);
1030
1031 offset = TAD_OFFSET(tad_offset);
1032
1033 debugf0("TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (offset 0x%08Lx), index %d, base ch: %d, ch mask: 0x%02lx\n",
1034 n_tads,
1035 addr,
1036 limit,
1037 (u32)TAD_SOCK(reg),
1038 ch_way,
1039 offset,
1040 idx,
1041 base_ch,
1042 *channel_mask);
1043
1044 /* Calculate channel address */
1045 /* Remove the TAD offset */
1046
1047 if (offset > addr) {
1048 sprintf(msg, "Can't calculate ch addr: TAD offset 0x%08Lx is too high for addr 0x%08Lx!",
1049 offset, addr);
1050 edac_mc_handle_ce_no_info(mci, msg);
1051 return -EINVAL;
1052 }
1053 addr -= offset;
1054 /* Store the low bits [0:6] of the addr */
1055 ch_addr = addr & 0x7f;
1056 /* Remove socket wayness and remove 6 bits */
1057 addr >>= 6;
1058 addr /= sck_xch;
1059#if 0
1060 /* Divide by channel way */
1061 addr = addr / ch_way;
1062#endif
1063 /* Recover the last 6 bits */
1064 ch_addr |= addr << 6;
1065
1066 /*
1067 * Step 3) Decode rank
1068 */
1069 for (n_rir = 0; n_rir < MAX_RIR_RANGES; n_rir++) {
1070 pci_read_config_dword(pvt->pci_tad[base_ch],
1071 rir_way_limit[n_rir],
1072 &reg);
1073
1074 if (!IS_RIR_VALID(reg))
1075 continue;
1076
1077 limit = RIR_LIMIT(reg);
1078
1079 debugf0("RIR#%d, limit: %Lu.%03Lu GB (0x%016Lx), way: %d\n",
1080 n_rir,
1081 (limit >> 20) / 1000, (limit >> 20) % 1000,
1082 limit,
1083 1 << RIR_WAY(reg));
1084 if (ch_addr <= limit)
1085 break;
1086 }
1087 if (n_rir == MAX_RIR_RANGES) {
1088 sprintf(msg, "Can't discover the memory rank for ch addr 0x%08Lx",
1089 ch_addr);
1090 edac_mc_handle_ce_no_info(mci, msg);
1091 return -EINVAL;
1092 }
1093 rir_way = RIR_WAY(reg);
1094 if (pvt->is_close_pg)
1095 idx = (ch_addr >> 6);
1096 else
1097 idx = (ch_addr >> 13); /* FIXME: Datasheet says to shift by 15 */
1098 idx %= 1 << rir_way;
1099
1100 pci_read_config_dword(pvt->pci_tad[base_ch],
1101 rir_offset[n_rir][idx],
1102 &reg);
1103 *rank = RIR_RNK_TGT(reg);
1104
1105 debugf0("RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n",
1106 n_rir,
1107 ch_addr,
1108 limit,
1109 rir_way,
1110 idx);
1111
1112 return 0;
1113}
1114
1115/****************************************************************************
1116 Device initialization routines: put/get, init/exit
1117 ****************************************************************************/
1118
1119/*
1120 * sbridge_put_all_devices 'put' all the devices that we have
1121 * reserved via 'get'
1122 */
1123static void sbridge_put_devices(struct sbridge_dev *sbridge_dev)
1124{
1125 int i;
1126
1127 debugf0(__FILE__ ": %s()\n", __func__);
1128 for (i = 0; i < sbridge_dev->n_devs; i++) {
1129 struct pci_dev *pdev = sbridge_dev->pdev[i];
1130 if (!pdev)
1131 continue;
1132 debugf0("Removing dev %02x:%02x.%d\n",
1133 pdev->bus->number,
1134 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1135 pci_dev_put(pdev);
1136 }
1137}
1138
1139static void sbridge_put_all_devices(void)
1140{
1141 struct sbridge_dev *sbridge_dev, *tmp;
1142
1143 list_for_each_entry_safe(sbridge_dev, tmp, &sbridge_edac_list, list) {
1144 sbridge_put_devices(sbridge_dev);
1145 free_sbridge_dev(sbridge_dev);
1146 }
1147}
1148
1149/*
1150 * sbridge_get_all_devices Find and perform 'get' operation on the MCH's
1151 * device/functions we want to reference for this driver
1152 *
1153 * Need to 'get' device 16 func 1 and func 2
1154 */
1155static int sbridge_get_onedevice(struct pci_dev **prev,
1156 u8 *num_mc,
1157 const struct pci_id_table *table,
1158 const unsigned devno)
1159{
1160 struct sbridge_dev *sbridge_dev;
1161 const struct pci_id_descr *dev_descr = &table->descr[devno];
1162
1163 struct pci_dev *pdev = NULL;
1164 u8 bus = 0;
1165
1166 sbridge_printk(KERN_INFO,
1167 "Seeking for: dev %02x.%d PCI ID %04x:%04x\n",
1168 dev_descr->dev, dev_descr->func,
1169 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1170
1171 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1172 dev_descr->dev_id, *prev);
1173
1174 if (!pdev) {
1175 if (*prev) {
1176 *prev = pdev;
1177 return 0;
1178 }
1179
1180 if (dev_descr->optional)
1181 return 0;
1182
1183 if (devno == 0)
1184 return -ENODEV;
1185
1186 sbridge_printk(KERN_INFO,
1187 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
1188 dev_descr->dev, dev_descr->func,
1189 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1190
1191 /* End of list, leave */
1192 return -ENODEV;
1193 }
1194 bus = pdev->bus->number;
1195
1196 sbridge_dev = get_sbridge_dev(bus);
1197 if (!sbridge_dev) {
1198 sbridge_dev = alloc_sbridge_dev(bus, table);
1199 if (!sbridge_dev) {
1200 pci_dev_put(pdev);
1201 return -ENOMEM;
1202 }
1203 (*num_mc)++;
1204 }
1205
1206 if (sbridge_dev->pdev[devno]) {
1207 sbridge_printk(KERN_ERR,
1208 "Duplicated device for "
1209 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1210 bus, dev_descr->dev, dev_descr->func,
1211 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1212 pci_dev_put(pdev);
1213 return -ENODEV;
1214 }
1215
1216 sbridge_dev->pdev[devno] = pdev;
1217
1218 /* Sanity check */
1219 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1220 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
1221 sbridge_printk(KERN_ERR,
1222 "Device PCI ID %04x:%04x "
1223 "has dev %02x:%d.%d instead of dev %02x:%02x.%d\n",
1224 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
1225 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1226 bus, dev_descr->dev, dev_descr->func);
1227 return -ENODEV;
1228 }
1229
1230 /* Be sure that the device is enabled */
1231 if (unlikely(pci_enable_device(pdev) < 0)) {
1232 sbridge_printk(KERN_ERR,
1233 "Couldn't enable "
1234 "dev %02x:%d.%d PCI ID %04x:%04x\n",
1235 bus, dev_descr->dev, dev_descr->func,
1236 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1237 return -ENODEV;
1238 }
1239
1240 debugf0("Detected dev %02x:%d.%d PCI ID %04x:%04x\n",
1241 bus, dev_descr->dev,
1242 dev_descr->func,
1243 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
1244
1245 /*
1246 * As stated on drivers/pci/search.c, the reference count for
1247 * @from is always decremented if it is not %NULL. So, as we need
1248 * to get all devices up to null, we need to do a get for the device
1249 */
1250 pci_dev_get(pdev);
1251
1252 *prev = pdev;
1253
1254 return 0;
1255}
1256
1257static int sbridge_get_all_devices(u8 *num_mc)
1258{
1259 int i, rc;
1260 struct pci_dev *pdev = NULL;
1261 const struct pci_id_table *table = pci_dev_descr_sbridge_table;
1262
1263 while (table && table->descr) {
1264 for (i = 0; i < table->n_devs; i++) {
1265 pdev = NULL;
1266 do {
1267 rc = sbridge_get_onedevice(&pdev, num_mc,
1268 table, i);
1269 if (rc < 0) {
1270 if (i == 0) {
1271 i = table->n_devs;
1272 break;
1273 }
1274 sbridge_put_all_devices();
1275 return -ENODEV;
1276 }
1277 } while (pdev);
1278 }
1279 table++;
1280 }
1281
1282 return 0;
1283}
1284
1285static int mci_bind_devs(struct mem_ctl_info *mci,
1286 struct sbridge_dev *sbridge_dev)
1287{
1288 struct sbridge_pvt *pvt = mci->pvt_info;
1289 struct pci_dev *pdev;
1290 int i, func, slot;
1291
1292 for (i = 0; i < sbridge_dev->n_devs; i++) {
1293 pdev = sbridge_dev->pdev[i];
1294 if (!pdev)
1295 continue;
1296 slot = PCI_SLOT(pdev->devfn);
1297 func = PCI_FUNC(pdev->devfn);
1298 switch (slot) {
1299 case 12:
1300 switch (func) {
1301 case 6:
1302 pvt->pci_sad0 = pdev;
1303 break;
1304 case 7:
1305 pvt->pci_sad1 = pdev;
1306 break;
1307 default:
1308 goto error;
1309 }
1310 break;
1311 case 13:
1312 switch (func) {
1313 case 6:
1314 pvt->pci_br = pdev;
1315 break;
1316 default:
1317 goto error;
1318 }
1319 break;
1320 case 14:
1321 switch (func) {
1322 case 0:
1323 pvt->pci_ha0 = pdev;
1324 break;
1325 default:
1326 goto error;
1327 }
1328 break;
1329 case 15:
1330 switch (func) {
1331 case 0:
1332 pvt->pci_ta = pdev;
1333 break;
1334 case 1:
1335 pvt->pci_ras = pdev;
1336 break;
1337 case 2:
1338 case 3:
1339 case 4:
1340 case 5:
1341 pvt->pci_tad[func - 2] = pdev;
1342 break;
1343 default:
1344 goto error;
1345 }
1346 break;
1347 case 17:
1348 switch (func) {
1349 case 0:
1350 pvt->pci_ddrio = pdev;
1351 break;
1352 default:
1353 goto error;
1354 }
1355 break;
1356 default:
1357 goto error;
1358 }
1359
1360 debugf0("Associated PCI %02x.%02d.%d with dev = %p\n",
1361 sbridge_dev->bus,
1362 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1363 pdev);
1364 }
1365
1366 /* Check if everything were registered */
1367 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha0 ||
1368 !pvt-> pci_tad || !pvt->pci_ras || !pvt->pci_ta ||
1369 !pvt->pci_ddrio)
1370 goto enodev;
1371
1372 for (i = 0; i < NUM_CHANNELS; i++) {
1373 if (!pvt->pci_tad[i])
1374 goto enodev;
1375 }
1376 return 0;
1377
1378enodev:
1379 sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
1380 return -ENODEV;
1381
1382error:
1383 sbridge_printk(KERN_ERR, "Device %d, function %d "
1384 "is out of the expected range\n",
1385 slot, func);
1386 return -EINVAL;
1387}
1388
1389/****************************************************************************
1390 Error check routines
1391 ****************************************************************************/
1392
1393/*
1394 * While Sandy Bridge has error count registers, SMI BIOS read values from
1395 * and resets the counters. So, they are not reliable for the OS to read
1396 * from them. So, we have no option but to just trust on whatever MCE is
1397 * telling us about the errors.
1398 */
1399static void sbridge_mce_output_error(struct mem_ctl_info *mci,
1400 const struct mce *m)
1401{
1402 struct mem_ctl_info *new_mci;
1403 struct sbridge_pvt *pvt = mci->pvt_info;
1404 char *type, *optype, *msg, *recoverable_msg;
1405 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
1406 bool overflow = GET_BITFIELD(m->status, 62, 62);
1407 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
1408 bool recoverable = GET_BITFIELD(m->status, 56, 56);
1409 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
1410 u32 mscod = GET_BITFIELD(m->status, 16, 31);
1411 u32 errcode = GET_BITFIELD(m->status, 0, 15);
1412 u32 channel = GET_BITFIELD(m->status, 0, 3);
1413 u32 optypenum = GET_BITFIELD(m->status, 4, 6);
1414 long channel_mask, first_channel;
1415 u8 rank, socket;
1416 int csrow, rc, dimm;
1417 char *area_type = "Unknown";
1418
1419 if (ripv)
1420 type = "NON_FATAL";
1421 else
1422 type = "FATAL";
1423
1424 /*
1425 * According with Table 15-9 of the Intel Archictecture spec vol 3A,
1426 * memory errors should fit in this mask:
1427 * 000f 0000 1mmm cccc (binary)
1428 * where:
1429 * f = Correction Report Filtering Bit. If 1, subsequent errors
1430 * won't be shown
1431 * mmm = error type
1432 * cccc = channel
1433 * If the mask doesn't match, report an error to the parsing logic
1434 */
1435 if (! ((errcode & 0xef80) == 0x80)) {
1436 optype = "Can't parse: it is not a mem";
1437 } else {
1438 switch (optypenum) {
1439 case 0:
1440 optype = "generic undef request";
1441 break;
1442 case 1:
1443 optype = "memory read";
1444 break;
1445 case 2:
1446 optype = "memory write";
1447 break;
1448 case 3:
1449 optype = "addr/cmd";
1450 break;
1451 case 4:
1452 optype = "memory scrubbing";
1453 break;
1454 default:
1455 optype = "reserved";
1456 break;
1457 }
1458 }
1459
1460 rc = get_memory_error_data(mci, m->addr, &socket,
1461 &channel_mask, &rank, area_type);
1462 if (rc < 0)
1463 return;
1464 new_mci = get_mci_for_node_id(socket);
1465 if (!new_mci) {
1466 edac_mc_handle_ce_no_info(mci, "Error: socket got corrupted!");
1467 return;
1468 }
1469 mci = new_mci;
1470 pvt = mci->pvt_info;
1471
1472 first_channel = find_first_bit(&channel_mask, NUM_CHANNELS);
1473
1474 if (rank < 4)
1475 dimm = 0;
1476 else if (rank < 8)
1477 dimm = 1;
1478 else
1479 dimm = 2;
1480
1481 csrow = pvt->csrow_map[first_channel][dimm];
1482
1483 if (uncorrected_error && recoverable)
1484 recoverable_msg = " recoverable";
1485 else
1486 recoverable_msg = "";
1487
1488 /*
1489 * FIXME: What should we do with "channel" information on mcelog?
1490 * Probably, we can just discard it, as the channel information
1491 * comes from the get_memory_error_data() address decoding
1492 */
1493 msg = kasprintf(GFP_ATOMIC,
1494 "%d %s error(s): %s on %s area %s%s: cpu=%d Err=%04x:%04x (ch=%d), "
1495 "addr = 0x%08llx => socket=%d, Channel=%ld(mask=%ld), rank=%d\n",
1496 core_err_cnt,
1497 area_type,
1498 optype,
1499 type,
1500 recoverable_msg,
1501 overflow ? "OVERFLOW" : "",
1502 m->cpu,
1503 mscod, errcode,
1504 channel, /* 1111b means not specified */
1505 (long long) m->addr,
1506 socket,
1507 first_channel, /* This is the real channel on SB */
1508 channel_mask,
1509 rank);
1510
1511 debugf0("%s", msg);
1512
1513 /* Call the helper to output message */
1514 if (uncorrected_error)
1515 edac_mc_handle_fbd_ue(mci, csrow, 0, 0, msg);
1516 else
1517 edac_mc_handle_fbd_ce(mci, csrow, 0, msg);
1518
1519 kfree(msg);
1520}
1521
1522/*
1523 * sbridge_check_error Retrieve and process errors reported by the
1524 * hardware. Called by the Core module.
1525 */
1526static void sbridge_check_error(struct mem_ctl_info *mci)
1527{
1528 struct sbridge_pvt *pvt = mci->pvt_info;
1529 int i;
1530 unsigned count = 0;
1531 struct mce *m;
1532
1533 /*
1534 * MCE first step: Copy all mce errors into a temporary buffer
1535 * We use a double buffering here, to reduce the risk of
1536 * loosing an error.
1537 */
1538 smp_rmb();
1539 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1540 % MCE_LOG_LEN;
1541 if (!count)
1542 return;
1543
1544 m = pvt->mce_outentry;
1545 if (pvt->mce_in + count > MCE_LOG_LEN) {
1546 unsigned l = MCE_LOG_LEN - pvt->mce_in;
1547
1548 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1549 smp_wmb();
1550 pvt->mce_in = 0;
1551 count -= l;
1552 m += l;
1553 }
1554 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1555 smp_wmb();
1556 pvt->mce_in += count;
1557
1558 smp_rmb();
1559 if (pvt->mce_overrun) {
1560 sbridge_printk(KERN_ERR, "Lost %d memory errors\n",
1561 pvt->mce_overrun);
1562 smp_wmb();
1563 pvt->mce_overrun = 0;
1564 }
1565
1566 /*
1567 * MCE second step: parse errors and display
1568 */
1569 for (i = 0; i < count; i++)
1570 sbridge_mce_output_error(mci, &pvt->mce_outentry[i]);
1571}
1572
1573/*
1574 * sbridge_mce_check_error Replicates mcelog routine to get errors
1575 * This routine simply queues mcelog errors, and
1576 * return. The error itself should be handled later
1577 * by sbridge_check_error.
1578 * WARNING: As this routine should be called at NMI time, extra care should
1579 * be taken to avoid deadlocks, and to be as fast as possible.
1580 */
1581static int sbridge_mce_check_error(void *priv, struct mce *mce)
1582{
1583 struct mem_ctl_info *mci = priv;
1584 struct sbridge_pvt *pvt = mci->pvt_info;
1585
1586 /*
1587 * Just let mcelog handle it if the error is
1588 * outside the memory controller. A memory error
1589 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
1590 * bit 12 has an special meaning.
1591 */
1592 if ((mce->status & 0xefff) >> 7 != 1)
1593 return 0;
1594
1595 printk("sbridge: HANDLING MCE MEMORY ERROR\n");
1596
1597 printk("CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
1598 mce->extcpu, mce->mcgstatus, mce->bank, mce->status);
1599 printk("TSC %llx ", mce->tsc);
1600 printk("ADDR %llx ", mce->addr);
1601 printk("MISC %llx ", mce->misc);
1602
1603 printk("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
1604 mce->cpuvendor, mce->cpuid, mce->time,
1605 mce->socketid, mce->apicid);
1606
1607#ifdef CONFIG_SMP
1608 /* Only handle if it is the right mc controller */
1609 if (cpu_data(mce->cpu).phys_proc_id != pvt->sbridge_dev->mc)
1610 return 0;
1611#endif
1612
1613 smp_rmb();
1614 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
1615 smp_wmb();
1616 pvt->mce_overrun++;
1617 return 0;
1618 }
1619
1620 /* Copy memory error at the ringbuffer */
1621 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
1622 smp_wmb();
1623 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
1624
1625 /* Handle fatal errors immediately */
1626 if (mce->mcgstatus & 1)
1627 sbridge_check_error(mci);
1628
1629 /* Advice mcelog that the error were handled */
1630 return 1;
1631}
1632
1633/****************************************************************************
1634 EDAC register/unregister logic
1635 ****************************************************************************/
1636
1637static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
1638{
1639 struct mem_ctl_info *mci = sbridge_dev->mci;
1640 struct sbridge_pvt *pvt;
1641
1642 if (unlikely(!mci || !mci->pvt_info)) {
1643 debugf0("MC: " __FILE__ ": %s(): dev = %p\n",
1644 __func__, &sbridge_dev->pdev[0]->dev);
1645
1646 sbridge_printk(KERN_ERR, "Couldn't find mci handler\n");
1647 return;
1648 }
1649
1650 pvt = mci->pvt_info;
1651
1652 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1653 __func__, mci, &sbridge_dev->pdev[0]->dev);
1654
1655 /* Disable MCE NMI handler */
1656 edac_mce_unregister(&pvt->edac_mce);
1657
1658 /* Remove MC sysfs nodes */
1659 edac_mc_del_mc(mci->dev);
1660
1661 debugf1("%s: free mci struct\n", mci->ctl_name);
1662 kfree(mci->ctl_name);
1663 edac_mc_free(mci);
1664 sbridge_dev->mci = NULL;
1665}
1666
1667static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
1668{
1669 struct mem_ctl_info *mci;
1670 struct sbridge_pvt *pvt;
1671 int rc, channels, csrows;
1672
1673 /* Check the number of active and not disabled channels */
1674 rc = sbridge_get_active_channels(sbridge_dev->bus, &channels, &csrows);
1675 if (unlikely(rc < 0))
1676 return rc;
1677
1678 /* allocate a new MC control structure */
1679 mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, sbridge_dev->mc);
1680 if (unlikely(!mci))
1681 return -ENOMEM;
1682
1683 debugf0("MC: " __FILE__ ": %s(): mci = %p, dev = %p\n",
1684 __func__, mci, &sbridge_dev->pdev[0]->dev);
1685
1686 pvt = mci->pvt_info;
1687 memset(pvt, 0, sizeof(*pvt));
1688
1689 /* Associate sbridge_dev and mci for future usage */
1690 pvt->sbridge_dev = sbridge_dev;
1691 sbridge_dev->mci = mci;
1692
1693 mci->mtype_cap = MEM_FLAG_DDR3;
1694 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1695 mci->edac_cap = EDAC_FLAG_NONE;
1696 mci->mod_name = "sbridge_edac.c";
1697 mci->mod_ver = SBRIDGE_REVISION;
1698 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
1699 mci->dev_name = pci_name(sbridge_dev->pdev[0]);
1700 mci->ctl_page_to_phys = NULL;
1701
1702 /* Set the function pointer to an actual operation function */
1703 mci->edac_check = sbridge_check_error;
1704
1705 /* Store pci devices at mci for faster access */
1706 rc = mci_bind_devs(mci, sbridge_dev);
1707 if (unlikely(rc < 0))
1708 goto fail0;
1709
1710 /* Get dimm basic config and the memory layout */
1711 get_dimm_config(mci);
1712 get_memory_layout(mci);
1713
1714 /* record ptr to the generic device */
1715 mci->dev = &sbridge_dev->pdev[0]->dev;
1716
1717 /* add this new MC control structure to EDAC's list of MCs */
1718 if (unlikely(edac_mc_add_mc(mci))) {
1719 debugf0("MC: " __FILE__
1720 ": %s(): failed edac_mc_add_mc()\n", __func__);
1721 rc = -EINVAL;
1722 goto fail0;
1723 }
1724
1725 /* Registers on edac_mce in order to receive memory errors */
1726 pvt->edac_mce.priv = mci;
1727 pvt->edac_mce.check_error = sbridge_mce_check_error;
1728 rc = edac_mce_register(&pvt->edac_mce);
1729 if (unlikely(rc < 0)) {
1730 debugf0("MC: " __FILE__
1731 ": %s(): failed edac_mce_register()\n", __func__);
1732 goto fail1;
1733 }
1734
1735 return 0;
1736fail1:
1737 edac_mc_del_mc(mci->dev);
1738
1739fail0:
1740 kfree(mci->ctl_name);
1741 edac_mc_free(mci);
1742 sbridge_dev->mci = NULL;
1743 return rc;
1744}
1745
1746/*
1747 * sbridge_probe Probe for ONE instance of device to see if it is
1748 * present.
1749 * return:
1750 * 0 for FOUND a device
1751 * < 0 for error code
1752 */
1753
1754static int __devinit sbridge_probe(struct pci_dev *pdev,
1755 const struct pci_device_id *id)
1756{
1757 int rc;
1758 u8 mc, num_mc = 0;
1759 struct sbridge_dev *sbridge_dev;
1760
1761 /* get the pci devices we want to reserve for our use */
1762 mutex_lock(&sbridge_edac_lock);
1763
1764 /*
1765 * All memory controllers are allocated at the first pass.
1766 */
1767 if (unlikely(probed >= 1)) {
1768 mutex_unlock(&sbridge_edac_lock);
1769 return -ENODEV;
1770 }
1771 probed++;
1772
1773 rc = sbridge_get_all_devices(&num_mc);
1774 if (unlikely(rc < 0))
1775 goto fail0;
1776 mc = 0;
1777
1778 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
1779 debugf0("Registering MC#%d (%d of %d)\n", mc, mc + 1, num_mc);
1780 sbridge_dev->mc = mc++;
1781 rc = sbridge_register_mci(sbridge_dev);
1782 if (unlikely(rc < 0))
1783 goto fail1;
1784 }
1785
1786 sbridge_printk(KERN_INFO, "Driver loaded.\n");
1787
1788 mutex_unlock(&sbridge_edac_lock);
1789 return 0;
1790
1791fail1:
1792 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1793 sbridge_unregister_mci(sbridge_dev);
1794
1795 sbridge_put_all_devices();
1796fail0:
1797 mutex_unlock(&sbridge_edac_lock);
1798 return rc;
1799}
1800
1801/*
1802 * sbridge_remove destructor for one instance of device
1803 *
1804 */
1805static void __devexit sbridge_remove(struct pci_dev *pdev)
1806{
1807 struct sbridge_dev *sbridge_dev;
1808
1809 debugf0(__FILE__ ": %s()\n", __func__);
1810
1811 /*
1812 * we have a trouble here: pdev value for removal will be wrong, since
1813 * it will point to the X58 register used to detect that the machine
1814 * is a Nehalem or upper design. However, due to the way several PCI
1815 * devices are grouped together to provide MC functionality, we need
1816 * to use a different method for releasing the devices
1817 */
1818
1819 mutex_lock(&sbridge_edac_lock);
1820
1821 if (unlikely(!probed)) {
1822 mutex_unlock(&sbridge_edac_lock);
1823 return;
1824 }
1825
1826 list_for_each_entry(sbridge_dev, &sbridge_edac_list, list)
1827 sbridge_unregister_mci(sbridge_dev);
1828
1829 /* Release PCI resources */
1830 sbridge_put_all_devices();
1831
1832 probed--;
1833
1834 mutex_unlock(&sbridge_edac_lock);
1835}
1836
1837MODULE_DEVICE_TABLE(pci, sbridge_pci_tbl);
1838
1839/*
1840 * sbridge_driver pci_driver structure for this module
1841 *
1842 */
1843static struct pci_driver sbridge_driver = {
1844 .name = "sbridge_edac",
1845 .probe = sbridge_probe,
1846 .remove = __devexit_p(sbridge_remove),
1847 .id_table = sbridge_pci_tbl,
1848};
1849
1850/*
1851 * sbridge_init Module entry function
1852 * Try to initialize this module for its devices
1853 */
1854static int __init sbridge_init(void)
1855{
1856 int pci_rc;
1857
1858 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1859
1860 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1861 opstate_init();
1862
1863 pci_rc = pci_register_driver(&sbridge_driver);
1864
1865 if (pci_rc >= 0)
1866 return 0;
1867
1868 sbridge_printk(KERN_ERR, "Failed to register device with error %d.\n",
1869 pci_rc);
1870
1871 return pci_rc;
1872}
1873
1874/*
1875 * sbridge_exit() Module exit function
1876 * Unregister the driver
1877 */
1878static void __exit sbridge_exit(void)
1879{
1880 debugf2("MC: " __FILE__ ": %s()\n", __func__);
1881 pci_unregister_driver(&sbridge_driver);
1882}
1883
1884module_init(sbridge_init);
1885module_exit(sbridge_exit);
1886
1887module_param(edac_op_state, int, 0444);
1888MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1889
1890MODULE_LICENSE("GPL");
1891MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
1892MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
1893MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
1894 SBRIDGE_REVISION);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 10:55:33 -0500