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authorMatt Carlson <mcarlson@broadcom.com>2011-11-21 10:01:20 -0500
committerDavid S. Miller <davem@davemloft.net>2011-11-22 16:01:34 -0500
commite348c5e7de4a759a94eed4d0303ba81a4939f8b9 (patch)
treec5e9e51da7bd1f5b00e01cb999422e5d2e7dbfe8
parentfa6b2aae6ab5ae1ce4b65c1872477c4b794d338e (diff)
tg3: Add MDI-X reporting
This patch adds MDI-X state reporting. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/broadcom/tg3.c24
-rw-r--r--drivers/net/ethernet/broadcom/tg3.h5
2 files changed, 28 insertions, 1 deletions
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 6a25e5860ba5..0acb279dcf5c 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -3932,6 +3932,7 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3932 current_link_up = 0; 3932 current_link_up = 0;
3933 current_speed = SPEED_INVALID; 3933 current_speed = SPEED_INVALID;
3934 current_duplex = DUPLEX_INVALID; 3934 current_duplex = DUPLEX_INVALID;
3935 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
3935 3936
3936 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { 3937 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3937 err = tg3_phy_auxctl_read(tp, 3938 err = tg3_phy_auxctl_read(tp,
@@ -4004,8 +4005,22 @@ static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4004 } 4005 }
4005 4006
4006 if (current_link_up == 1 && 4007 if (current_link_up == 1 &&
4007 tp->link_config.active_duplex == DUPLEX_FULL) 4008 tp->link_config.active_duplex == DUPLEX_FULL) {
4009 u32 reg, bit;
4010
4011 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4012 reg = MII_TG3_FET_GEN_STAT;
4013 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4014 } else {
4015 reg = MII_TG3_EXT_STAT;
4016 bit = MII_TG3_EXT_STAT_MDIX;
4017 }
4018
4019 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4020 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4021
4008 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); 4022 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4023 }
4009 } 4024 }
4010 4025
4011relink: 4026relink:
@@ -10290,9 +10305,16 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
10290 if (netif_running(dev)) { 10305 if (netif_running(dev)) {
10291 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed); 10306 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
10292 cmd->duplex = tp->link_config.active_duplex; 10307 cmd->duplex = tp->link_config.active_duplex;
10308 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
10309 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
10310 cmd->eth_tp_mdix = ETH_TP_MDI_X;
10311 else
10312 cmd->eth_tp_mdix = ETH_TP_MDI;
10313 }
10293 } else { 10314 } else {
10294 ethtool_cmd_speed_set(cmd, SPEED_INVALID); 10315 ethtool_cmd_speed_set(cmd, SPEED_INVALID);
10295 cmd->duplex = DUPLEX_INVALID; 10316 cmd->duplex = DUPLEX_INVALID;
10317 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
10296 } 10318 }
10297 cmd->phy_address = tp->phy_addr; 10319 cmd->phy_address = tp->phy_addr;
10298 cmd->transceiver = XCVR_INTERNAL; 10320 cmd->transceiver = XCVR_INTERNAL;
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 8e2f380f893a..9cc10a868dcd 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -2174,6 +2174,7 @@
2174#define MII_TG3_EXT_CTRL_TBI 0x8000 2174#define MII_TG3_EXT_CTRL_TBI 0x8000
2175 2175
2176#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2176#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2177#define MII_TG3_EXT_STAT_MDIX 0x2000
2177#define MII_TG3_EXT_STAT_LPASS 0x0100 2178#define MII_TG3_EXT_STAT_LPASS 0x0100
2178 2179
2179#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2180#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
@@ -2277,6 +2278,9 @@
2277#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2278#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2278#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2279#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2279 2280
2281#define MII_TG3_FET_GEN_STAT 0x1c
2282#define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2283
2280#define MII_TG3_FET_TEST 0x1f 2284#define MII_TG3_FET_TEST 0x1f
2281#define MII_TG3_FET_SHADOW_EN 0x0080 2285#define MII_TG3_FET_SHADOW_EN 0x0080
2282 2286
@@ -3135,6 +3139,7 @@ struct tg3 {
3135#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3139#define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3136#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3140#define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3137#define TG3_PHYFLG_EEE_CAP 0x00040000 3141#define TG3_PHYFLG_EEE_CAP 0x00040000
3142#define TG3_PHYFLG_MDIX_STATE 0x00200000
3138 3143
3139 u32 led_ctrl; 3144 u32 led_ctrl;
3140 u32 phy_otp; 3145 u32 phy_otp;