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authorAndrew Vasquez <andrew.vasquez@qlogic.com>2005-11-08 17:37:06 -0500
committerJames Bottomley <jejb@mulgrave.(none)>2005-11-09 16:17:25 -0500
commitdcb36ce9d9100eb821c6ea314b02f215cbdd8aca (patch)
treece088495c46bfb08410b9cecdacfeb5dde08e3fa
parent07ce5eba857cb7dc8f6ae39eda74b108efe4a3f8 (diff)
[SCSI] qla2xxx: Correct additional posting issues during NVRAM accesses.
On MMIO relaxed-order platforms, it is possible for the proper delay during NVRAM access to begin before the request passes through the PCI bus (via a MMIO write) to the ISP. Thus, causing a subsequent read to the NVRAM part to fail. Add a MMIO read, after the MMIO write to insure any posted writes are flushed. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
-rw-r--r--drivers/scsi/qla2xxx/qla_sup.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 4bec0b4fb6b4..d54d2a99c3d3 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -126,6 +126,7 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
126 126
127 /* Wait for NVRAM to become ready */ 127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(&reg->nvram, NVR_SELECT); 128 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
129 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
129 do { 130 do {
130 NVRAM_DELAY(); 131 NVRAM_DELAY();
131 word = RD_REG_WORD(&reg->nvram); 132 word = RD_REG_WORD(&reg->nvram);
@@ -178,6 +179,7 @@ qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
178 179
179 /* Wait for NVRAM to become ready */ 180 /* Wait for NVRAM to become ready */
180 WRT_REG_WORD(&reg->nvram, NVR_SELECT); 181 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
182 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
181 do { 183 do {
182 NVRAM_DELAY(); 184 NVRAM_DELAY();
183 word = RD_REG_WORD(&reg->nvram); 185 word = RD_REG_WORD(&reg->nvram);
@@ -235,6 +237,7 @@ qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
235 /* Read data from NVRAM. */ 237 /* Read data from NVRAM. */
236 for (cnt = 0; cnt < 16; cnt++) { 238 for (cnt = 0; cnt < 16; cnt++) {
237 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK); 239 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
240 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
238 NVRAM_DELAY(); 241 NVRAM_DELAY();
239 data <<= 1; 242 data <<= 1;
240 reg_data = RD_REG_WORD(&reg->nvram); 243 reg_data = RD_REG_WORD(&reg->nvram);
@@ -337,6 +340,7 @@ qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
337 340
338 /* Wait for NVRAM to become ready. */ 341 /* Wait for NVRAM to become ready. */
339 WRT_REG_WORD(&reg->nvram, NVR_SELECT); 342 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
343 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
340 do { 344 do {
341 NVRAM_DELAY(); 345 NVRAM_DELAY();
342 word = RD_REG_WORD(&reg->nvram); 346 word = RD_REG_WORD(&reg->nvram);
@@ -388,6 +392,7 @@ qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
388 392
389 /* Wait for NVRAM to become ready. */ 393 /* Wait for NVRAM to become ready. */
390 WRT_REG_WORD(&reg->nvram, NVR_SELECT); 394 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
395 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
391 do { 396 do {
392 NVRAM_DELAY(); 397 NVRAM_DELAY();
393 word = RD_REG_WORD(&reg->nvram); 398 word = RD_REG_WORD(&reg->nvram);