diff options
author | Guennadi Liakhovetski <g.liakhovetski@gmx.de> | 2010-11-04 10:14:29 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-11-07 19:35:28 -0500 |
commit | d0013c9e3bc75b3e1652bd5999a9a8d56a822ce4 (patch) | |
tree | 0bc50a3255a3ee37445a8183a3a530289fca70d7 | |
parent | 6af26c6c99f01e810f9944543df810e320284aa3 (diff) |
sh: make some needlessly global sh7724 clocks static
These clocks are currently only used inside one .c file and are not
declared in any headers, therefore having them global is useless.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index 2d9700c6b53a..0fe2e9329cb2 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c | |||
@@ -48,7 +48,7 @@ static struct clk r_clk = { | |||
48 | * Default rate for the root input clock, reset this with clk_set_rate() | 48 | * Default rate for the root input clock, reset this with clk_set_rate() |
49 | * from the platform code. | 49 | * from the platform code. |
50 | */ | 50 | */ |
51 | struct clk extal_clk = { | 51 | static struct clk extal_clk = { |
52 | .rate = 33333333, | 52 | .rate = 33333333, |
53 | }; | 53 | }; |
54 | 54 | ||
@@ -111,7 +111,7 @@ static struct clk div3_clk = { | |||
111 | .parent = &pll_clk, | 111 | .parent = &pll_clk, |
112 | }; | 112 | }; |
113 | 113 | ||
114 | struct clk *main_clks[] = { | 114 | static struct clk *main_clks[] = { |
115 | &r_clk, | 115 | &r_clk, |
116 | &extal_clk, | 116 | &extal_clk, |
117 | &fll_clk, | 117 | &fll_clk, |
@@ -156,7 +156,7 @@ struct clk div4_clks[DIV4_NR] = { | |||
156 | 156 | ||
157 | enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; | 157 | enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR }; |
158 | 158 | ||
159 | struct clk div6_clks[DIV6_NR] = { | 159 | static struct clk div6_clks[DIV6_NR] = { |
160 | [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), | 160 | [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0), |
161 | [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), | 161 | [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0), |
162 | [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), | 162 | [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0), |