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authorRalf Baechle <ralf@linux-mips.org>2008-10-30 09:38:45 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-30 10:44:34 -0400
commitcea7e2dfdef53fe55f359d00da562a268be06fd2 (patch)
treef5513224d9fb6e3fb086a3c629fb76f53ac6fea6
parent255a12fbf994664125983e389c975b4403aea167 (diff)
MIPS: Sort out CPU type to name translation.
As noticed by David Daney <ddaney@caviumnetworks.com>, the old long switch statement did not comply with the Linux C coding style. It was also yet another place of code to be changed when adding a new processor type leading to annoying bugs for example in /proc/cpuinfo. Fixed by moving the setting of the CPU type string into the core of the probing code and a few BUG_ON() test to ensure the CPU probing code indeed did its job and removing multiple now redundant tests. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/kernel/cpu-probe.c225
1 files changed, 98 insertions, 127 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 41a1d07b4750..c9207b5fd923 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -286,11 +286,12 @@ static inline int __cpu_has_fpu(void)
286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ 286#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
287 | MIPS_CPU_COUNTER) 287 | MIPS_CPU_COUNTER)
288 288
289static inline void cpu_probe_legacy(struct cpuinfo_mips *c) 289static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
290{ 290{
291 switch (c->processor_id & 0xff00) { 291 switch (c->processor_id & 0xff00) {
292 case PRID_IMP_R2000: 292 case PRID_IMP_R2000:
293 c->cputype = CPU_R2000; 293 c->cputype = CPU_R2000;
294 __cpu_name[cpu] = "R2000";
294 c->isa_level = MIPS_CPU_ISA_I; 295 c->isa_level = MIPS_CPU_ISA_I;
295 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 296 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
296 MIPS_CPU_NOFPUEX; 297 MIPS_CPU_NOFPUEX;
@@ -299,13 +300,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
299 c->tlbsize = 64; 300 c->tlbsize = 64;
300 break; 301 break;
301 case PRID_IMP_R3000: 302 case PRID_IMP_R3000:
302 if ((c->processor_id & 0xff) == PRID_REV_R3000A) 303 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
303 if (cpu_has_confreg()) 304 if (cpu_has_confreg()) {
304 c->cputype = CPU_R3081E; 305 c->cputype = CPU_R3081E;
305 else 306 __cpu_name[cpu] = "R3081";
307 } else {
306 c->cputype = CPU_R3000A; 308 c->cputype = CPU_R3000A;
307 else 309 __cpu_name[cpu] = "R3000A";
310 }
311 break;
312 } else {
308 c->cputype = CPU_R3000; 313 c->cputype = CPU_R3000;
314 __cpu_name[cpu] = "R3000";
315 }
309 c->isa_level = MIPS_CPU_ISA_I; 316 c->isa_level = MIPS_CPU_ISA_I;
310 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | 317 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
311 MIPS_CPU_NOFPUEX; 318 MIPS_CPU_NOFPUEX;
@@ -315,15 +322,21 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
315 break; 322 break;
316 case PRID_IMP_R4000: 323 case PRID_IMP_R4000:
317 if (read_c0_config() & CONF_SC) { 324 if (read_c0_config() & CONF_SC) {
318 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 325 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
319 c->cputype = CPU_R4400PC; 326 c->cputype = CPU_R4400PC;
320 else 327 __cpu_name[cpu] = "R4400PC";
328 } else {
321 c->cputype = CPU_R4000PC; 329 c->cputype = CPU_R4000PC;
330 __cpu_name[cpu] = "R4000PC";
331 }
322 } else { 332 } else {
323 if ((c->processor_id & 0xff) >= PRID_REV_R4400) 333 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
324 c->cputype = CPU_R4400SC; 334 c->cputype = CPU_R4400SC;
325 else 335 __cpu_name[cpu] = "R4400SC";
336 } else {
326 c->cputype = CPU_R4000SC; 337 c->cputype = CPU_R4000SC;
338 __cpu_name[cpu] = "R4000SC";
339 }
327 } 340 }
328 341
329 c->isa_level = MIPS_CPU_ISA_III; 342 c->isa_level = MIPS_CPU_ISA_III;
@@ -336,25 +349,34 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
336 switch (c->processor_id & 0xf0) { 349 switch (c->processor_id & 0xf0) {
337 case PRID_REV_VR4111: 350 case PRID_REV_VR4111:
338 c->cputype = CPU_VR4111; 351 c->cputype = CPU_VR4111;
352 __cpu_name[cpu] = "NEC VR4111";
339 break; 353 break;
340 case PRID_REV_VR4121: 354 case PRID_REV_VR4121:
341 c->cputype = CPU_VR4121; 355 c->cputype = CPU_VR4121;
356 __cpu_name[cpu] = "NEC VR4121";
342 break; 357 break;
343 case PRID_REV_VR4122: 358 case PRID_REV_VR4122:
344 if ((c->processor_id & 0xf) < 0x3) 359 if ((c->processor_id & 0xf) < 0x3) {
345 c->cputype = CPU_VR4122; 360 c->cputype = CPU_VR4122;
346 else 361 __cpu_name[cpu] = "NEC VR4122";
362 } else {
347 c->cputype = CPU_VR4181A; 363 c->cputype = CPU_VR4181A;
364 __cpu_name[cpu] = "NEC VR4181A";
365 }
348 break; 366 break;
349 case PRID_REV_VR4130: 367 case PRID_REV_VR4130:
350 if ((c->processor_id & 0xf) < 0x4) 368 if ((c->processor_id & 0xf) < 0x4) {
351 c->cputype = CPU_VR4131; 369 c->cputype = CPU_VR4131;
352 else 370 __cpu_name[cpu] = "NEC VR4131";
371 } else {
353 c->cputype = CPU_VR4133; 372 c->cputype = CPU_VR4133;
373 __cpu_name[cpu] = "NEC VR4133";
374 }
354 break; 375 break;
355 default: 376 default:
356 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); 377 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
357 c->cputype = CPU_VR41XX; 378 c->cputype = CPU_VR41XX;
379 __cpu_name[cpu] = "NEC Vr41xx";
358 break; 380 break;
359 } 381 }
360 c->isa_level = MIPS_CPU_ISA_III; 382 c->isa_level = MIPS_CPU_ISA_III;
@@ -363,6 +385,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
363 break; 385 break;
364 case PRID_IMP_R4300: 386 case PRID_IMP_R4300:
365 c->cputype = CPU_R4300; 387 c->cputype = CPU_R4300;
388 __cpu_name[cpu] = "R4300";
366 c->isa_level = MIPS_CPU_ISA_III; 389 c->isa_level = MIPS_CPU_ISA_III;
367 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 390 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
368 MIPS_CPU_LLSC; 391 MIPS_CPU_LLSC;
@@ -370,6 +393,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
370 break; 393 break;
371 case PRID_IMP_R4600: 394 case PRID_IMP_R4600:
372 c->cputype = CPU_R4600; 395 c->cputype = CPU_R4600;
396 __cpu_name[cpu] = "R4600";
373 c->isa_level = MIPS_CPU_ISA_III; 397 c->isa_level = MIPS_CPU_ISA_III;
374 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 398 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
375 MIPS_CPU_LLSC; 399 MIPS_CPU_LLSC;
@@ -384,6 +408,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
384 * it's c0_prid id number with the TX3900. 408 * it's c0_prid id number with the TX3900.
385 */ 409 */
386 c->cputype = CPU_R4650; 410 c->cputype = CPU_R4650;
411 __cpu_name[cpu] = "R4650";
387 c->isa_level = MIPS_CPU_ISA_III; 412 c->isa_level = MIPS_CPU_ISA_III;
388 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; 413 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
389 c->tlbsize = 48; 414 c->tlbsize = 48;
@@ -395,25 +420,26 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
395 420
396 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { 421 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
397 c->cputype = CPU_TX3927; 422 c->cputype = CPU_TX3927;
423 __cpu_name[cpu] = "TX3927";
398 c->tlbsize = 64; 424 c->tlbsize = 64;
399 } else { 425 } else {
400 switch (c->processor_id & 0xff) { 426 switch (c->processor_id & 0xff) {
401 case PRID_REV_TX3912: 427 case PRID_REV_TX3912:
402 c->cputype = CPU_TX3912; 428 c->cputype = CPU_TX3912;
429 __cpu_name[cpu] = "TX3912";
403 c->tlbsize = 32; 430 c->tlbsize = 32;
404 break; 431 break;
405 case PRID_REV_TX3922: 432 case PRID_REV_TX3922:
406 c->cputype = CPU_TX3922; 433 c->cputype = CPU_TX3922;
434 __cpu_name[cpu] = "TX3922";
407 c->tlbsize = 64; 435 c->tlbsize = 64;
408 break; 436 break;
409 default:
410 c->cputype = CPU_UNKNOWN;
411 break;
412 } 437 }
413 } 438 }
414 break; 439 break;
415 case PRID_IMP_R4700: 440 case PRID_IMP_R4700:
416 c->cputype = CPU_R4700; 441 c->cputype = CPU_R4700;
442 __cpu_name[cpu] = "R4700";
417 c->isa_level = MIPS_CPU_ISA_III; 443 c->isa_level = MIPS_CPU_ISA_III;
418 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 444 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
419 MIPS_CPU_LLSC; 445 MIPS_CPU_LLSC;
@@ -421,6 +447,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
421 break; 447 break;
422 case PRID_IMP_TX49: 448 case PRID_IMP_TX49:
423 c->cputype = CPU_TX49XX; 449 c->cputype = CPU_TX49XX;
450 __cpu_name[cpu] = "R49XX";
424 c->isa_level = MIPS_CPU_ISA_III; 451 c->isa_level = MIPS_CPU_ISA_III;
425 c->options = R4K_OPTS | MIPS_CPU_LLSC; 452 c->options = R4K_OPTS | MIPS_CPU_LLSC;
426 if (!(c->processor_id & 0x08)) 453 if (!(c->processor_id & 0x08))
@@ -429,6 +456,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
429 break; 456 break;
430 case PRID_IMP_R5000: 457 case PRID_IMP_R5000:
431 c->cputype = CPU_R5000; 458 c->cputype = CPU_R5000;
459 __cpu_name[cpu] = "R5000";
432 c->isa_level = MIPS_CPU_ISA_IV; 460 c->isa_level = MIPS_CPU_ISA_IV;
433 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 461 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
434 MIPS_CPU_LLSC; 462 MIPS_CPU_LLSC;
@@ -436,6 +464,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
436 break; 464 break;
437 case PRID_IMP_R5432: 465 case PRID_IMP_R5432:
438 c->cputype = CPU_R5432; 466 c->cputype = CPU_R5432;
467 __cpu_name[cpu] = "R5432";
439 c->isa_level = MIPS_CPU_ISA_IV; 468 c->isa_level = MIPS_CPU_ISA_IV;
440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 469 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
441 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 470 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -443,6 +472,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
443 break; 472 break;
444 case PRID_IMP_R5500: 473 case PRID_IMP_R5500:
445 c->cputype = CPU_R5500; 474 c->cputype = CPU_R5500;
475 __cpu_name[cpu] = "R5500";
446 c->isa_level = MIPS_CPU_ISA_IV; 476 c->isa_level = MIPS_CPU_ISA_IV;
447 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 477 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
448 MIPS_CPU_WATCH | MIPS_CPU_LLSC; 478 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
@@ -450,6 +480,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
450 break; 480 break;
451 case PRID_IMP_NEVADA: 481 case PRID_IMP_NEVADA:
452 c->cputype = CPU_NEVADA; 482 c->cputype = CPU_NEVADA;
483 __cpu_name[cpu] = "Nevada";
453 c->isa_level = MIPS_CPU_ISA_IV; 484 c->isa_level = MIPS_CPU_ISA_IV;
454 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 485 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
455 MIPS_CPU_DIVEC | MIPS_CPU_LLSC; 486 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
@@ -457,6 +488,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
457 break; 488 break;
458 case PRID_IMP_R6000: 489 case PRID_IMP_R6000:
459 c->cputype = CPU_R6000; 490 c->cputype = CPU_R6000;
491 __cpu_name[cpu] = "R6000";
460 c->isa_level = MIPS_CPU_ISA_II; 492 c->isa_level = MIPS_CPU_ISA_II;
461 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 493 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
462 MIPS_CPU_LLSC; 494 MIPS_CPU_LLSC;
@@ -464,6 +496,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
464 break; 496 break;
465 case PRID_IMP_R6000A: 497 case PRID_IMP_R6000A:
466 c->cputype = CPU_R6000A; 498 c->cputype = CPU_R6000A;
499 __cpu_name[cpu] = "R6000A";
467 c->isa_level = MIPS_CPU_ISA_II; 500 c->isa_level = MIPS_CPU_ISA_II;
468 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | 501 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
469 MIPS_CPU_LLSC; 502 MIPS_CPU_LLSC;
@@ -471,6 +504,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
471 break; 504 break;
472 case PRID_IMP_RM7000: 505 case PRID_IMP_RM7000:
473 c->cputype = CPU_RM7000; 506 c->cputype = CPU_RM7000;
507 __cpu_name[cpu] = "RM7000";
474 c->isa_level = MIPS_CPU_ISA_IV; 508 c->isa_level = MIPS_CPU_ISA_IV;
475 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 509 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
476 MIPS_CPU_LLSC; 510 MIPS_CPU_LLSC;
@@ -486,6 +520,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
486 break; 520 break;
487 case PRID_IMP_RM9000: 521 case PRID_IMP_RM9000:
488 c->cputype = CPU_RM9000; 522 c->cputype = CPU_RM9000;
523 __cpu_name[cpu] = "RM9000";
489 c->isa_level = MIPS_CPU_ISA_IV; 524 c->isa_level = MIPS_CPU_ISA_IV;
490 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | 525 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
491 MIPS_CPU_LLSC; 526 MIPS_CPU_LLSC;
@@ -500,6 +535,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
500 break; 535 break;
501 case PRID_IMP_R8000: 536 case PRID_IMP_R8000:
502 c->cputype = CPU_R8000; 537 c->cputype = CPU_R8000;
538 __cpu_name[cpu] = "RM8000";
503 c->isa_level = MIPS_CPU_ISA_IV; 539 c->isa_level = MIPS_CPU_ISA_IV;
504 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | 540 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
505 MIPS_CPU_FPU | MIPS_CPU_32FPR | 541 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -508,6 +544,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
508 break; 544 break;
509 case PRID_IMP_R10000: 545 case PRID_IMP_R10000:
510 c->cputype = CPU_R10000; 546 c->cputype = CPU_R10000;
547 __cpu_name[cpu] = "R10000";
511 c->isa_level = MIPS_CPU_ISA_IV; 548 c->isa_level = MIPS_CPU_ISA_IV;
512 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 549 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
513 MIPS_CPU_FPU | MIPS_CPU_32FPR | 550 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -517,6 +554,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
517 break; 554 break;
518 case PRID_IMP_R12000: 555 case PRID_IMP_R12000:
519 c->cputype = CPU_R12000; 556 c->cputype = CPU_R12000;
557 __cpu_name[cpu] = "R12000";
520 c->isa_level = MIPS_CPU_ISA_IV; 558 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 559 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
522 MIPS_CPU_FPU | MIPS_CPU_32FPR | 560 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -526,6 +564,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
526 break; 564 break;
527 case PRID_IMP_R14000: 565 case PRID_IMP_R14000:
528 c->cputype = CPU_R14000; 566 c->cputype = CPU_R14000;
567 __cpu_name[cpu] = "R14000";
529 c->isa_level = MIPS_CPU_ISA_IV; 568 c->isa_level = MIPS_CPU_ISA_IV;
530 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | 569 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
531 MIPS_CPU_FPU | MIPS_CPU_32FPR | 570 MIPS_CPU_FPU | MIPS_CPU_32FPR |
@@ -535,6 +574,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
535 break; 574 break;
536 case PRID_IMP_LOONGSON2: 575 case PRID_IMP_LOONGSON2:
537 c->cputype = CPU_LOONGSON2; 576 c->cputype = CPU_LOONGSON2;
577 __cpu_name[cpu] = "ICT Loongson-2";
538 c->isa_level = MIPS_CPU_ISA_III; 578 c->isa_level = MIPS_CPU_ISA_III;
539 c->options = R4K_OPTS | 579 c->options = R4K_OPTS |
540 MIPS_CPU_FPU | MIPS_CPU_LLSC | 580 MIPS_CPU_FPU | MIPS_CPU_LLSC |
@@ -678,51 +718,62 @@ extern void spram_config(void);
678static inline void spram_config(void) {} 718static inline void spram_config(void) {}
679#endif 719#endif
680 720
681static inline void cpu_probe_mips(struct cpuinfo_mips *c) 721static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
682{ 722{
683 decode_configs(c); 723 decode_configs(c);
684 switch (c->processor_id & 0xff00) { 724 switch (c->processor_id & 0xff00) {
685 case PRID_IMP_4KC: 725 case PRID_IMP_4KC:
686 c->cputype = CPU_4KC; 726 c->cputype = CPU_4KC;
727 __cpu_name[cpu] = "MIPS 4Kc";
687 break; 728 break;
688 case PRID_IMP_4KEC: 729 case PRID_IMP_4KEC:
689 c->cputype = CPU_4KEC; 730 c->cputype = CPU_4KEC;
731 __cpu_name[cpu] = "MIPS 4KEc";
690 break; 732 break;
691 case PRID_IMP_4KECR2: 733 case PRID_IMP_4KECR2:
692 c->cputype = CPU_4KEC; 734 c->cputype = CPU_4KEC;
735 __cpu_name[cpu] = "MIPS 4KEc";
693 break; 736 break;
694 case PRID_IMP_4KSC: 737 case PRID_IMP_4KSC:
695 case PRID_IMP_4KSD: 738 case PRID_IMP_4KSD:
696 c->cputype = CPU_4KSC; 739 c->cputype = CPU_4KSC;
740 __cpu_name[cpu] = "MIPS 4KSc";
697 break; 741 break;
698 case PRID_IMP_5KC: 742 case PRID_IMP_5KC:
699 c->cputype = CPU_5KC; 743 c->cputype = CPU_5KC;
744 __cpu_name[cpu] = "MIPS 5Kc";
700 break; 745 break;
701 case PRID_IMP_20KC: 746 case PRID_IMP_20KC:
702 c->cputype = CPU_20KC; 747 c->cputype = CPU_20KC;
748 __cpu_name[cpu] = "MIPS 20Kc";
703 break; 749 break;
704 case PRID_IMP_24K: 750 case PRID_IMP_24K:
705 case PRID_IMP_24KE: 751 case PRID_IMP_24KE:
706 c->cputype = CPU_24K; 752 c->cputype = CPU_24K;
753 __cpu_name[cpu] = "MIPS 24Kc";
707 break; 754 break;
708 case PRID_IMP_25KF: 755 case PRID_IMP_25KF:
709 c->cputype = CPU_25KF; 756 c->cputype = CPU_25KF;
757 __cpu_name[cpu] = "MIPS 25Kc";
710 break; 758 break;
711 case PRID_IMP_34K: 759 case PRID_IMP_34K:
712 c->cputype = CPU_34K; 760 c->cputype = CPU_34K;
761 __cpu_name[cpu] = "MIPS 34Kc";
713 break; 762 break;
714 case PRID_IMP_74K: 763 case PRID_IMP_74K:
715 c->cputype = CPU_74K; 764 c->cputype = CPU_74K;
765 __cpu_name[cpu] = "MIPS 74Kc";
716 break; 766 break;
717 case PRID_IMP_1004K: 767 case PRID_IMP_1004K:
718 c->cputype = CPU_1004K; 768 c->cputype = CPU_1004K;
769 __cpu_name[cpu] = "MIPS 1004Kc";
719 break; 770 break;
720 } 771 }
721 772
722 spram_config(); 773 spram_config();
723} 774}
724 775
725static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) 776static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
726{ 777{
727 decode_configs(c); 778 decode_configs(c);
728 switch (c->processor_id & 0xff00) { 779 switch (c->processor_id & 0xff00) {
@@ -731,23 +782,31 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
731 switch ((c->processor_id >> 24) & 0xff) { 782 switch ((c->processor_id >> 24) & 0xff) {
732 case 0: 783 case 0:
733 c->cputype = CPU_AU1000; 784 c->cputype = CPU_AU1000;
785 __cpu_name[cpu] = "Au1000";
734 break; 786 break;
735 case 1: 787 case 1:
736 c->cputype = CPU_AU1500; 788 c->cputype = CPU_AU1500;
789 __cpu_name[cpu] = "Au1500";
737 break; 790 break;
738 case 2: 791 case 2:
739 c->cputype = CPU_AU1100; 792 c->cputype = CPU_AU1100;
793 __cpu_name[cpu] = "Au1100";
740 break; 794 break;
741 case 3: 795 case 3:
742 c->cputype = CPU_AU1550; 796 c->cputype = CPU_AU1550;
797 __cpu_name[cpu] = "Au1550";
743 break; 798 break;
744 case 4: 799 case 4:
745 c->cputype = CPU_AU1200; 800 c->cputype = CPU_AU1200;
746 if (2 == (c->processor_id & 0xff)) 801 __cpu_name[cpu] = "Au1200";
802 if ((c->processor_id & 0xff) == 2) {
747 c->cputype = CPU_AU1250; 803 c->cputype = CPU_AU1250;
804 __cpu_name[cpu] = "Au1250";
805 }
748 break; 806 break;
749 case 5: 807 case 5:
750 c->cputype = CPU_AU1210; 808 c->cputype = CPU_AU1210;
809 __cpu_name[cpu] = "Au1210";
751 break; 810 break;
752 default: 811 default:
753 panic("Unknown Au Core!"); 812 panic("Unknown Au Core!");
@@ -757,154 +816,67 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
757 } 816 }
758} 817}
759 818
760static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) 819static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
761{ 820{
762 decode_configs(c); 821 decode_configs(c);
763 822
764 switch (c->processor_id & 0xff00) { 823 switch (c->processor_id & 0xff00) {
765 case PRID_IMP_SB1: 824 case PRID_IMP_SB1:
766 c->cputype = CPU_SB1; 825 c->cputype = CPU_SB1;
826 __cpu_name[cpu] = "SiByte SB1";
767 /* FPU in pass1 is known to have issues. */ 827 /* FPU in pass1 is known to have issues. */
768 if ((c->processor_id & 0xff) < 0x02) 828 if ((c->processor_id & 0xff) < 0x02)
769 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 829 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
770 break; 830 break;
771 case PRID_IMP_SB1A: 831 case PRID_IMP_SB1A:
772 c->cputype = CPU_SB1A; 832 c->cputype = CPU_SB1A;
833 __cpu_name[cpu] = "SiByte SB1A";
773 break; 834 break;
774 } 835 }
775} 836}
776 837
777static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c) 838static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
778{ 839{
779 decode_configs(c); 840 decode_configs(c);
780 switch (c->processor_id & 0xff00) { 841 switch (c->processor_id & 0xff00) {
781 case PRID_IMP_SR71000: 842 case PRID_IMP_SR71000:
782 c->cputype = CPU_SR71000; 843 c->cputype = CPU_SR71000;
844 __cpu_name[cpu] = "Sandcraft SR71000";
783 c->scache.ways = 8; 845 c->scache.ways = 8;
784 c->tlbsize = 64; 846 c->tlbsize = 64;
785 break; 847 break;
786 } 848 }
787} 849}
788 850
789static inline void cpu_probe_nxp(struct cpuinfo_mips *c) 851static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
790{ 852{
791 decode_configs(c); 853 decode_configs(c);
792 switch (c->processor_id & 0xff00) { 854 switch (c->processor_id & 0xff00) {
793 case PRID_IMP_PR4450: 855 case PRID_IMP_PR4450:
794 c->cputype = CPU_PR4450; 856 c->cputype = CPU_PR4450;
857 __cpu_name[cpu] = "Philips PR4450";
795 c->isa_level = MIPS_CPU_ISA_M32R1; 858 c->isa_level = MIPS_CPU_ISA_M32R1;
796 break; 859 break;
797 default:
798 panic("Unknown NXP Core!"); /* REVISIT: die? */
799 break;
800 } 860 }
801} 861}
802 862
803 863static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
804static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
805{ 864{
806 decode_configs(c); 865 decode_configs(c);
807 switch (c->processor_id & 0xff00) { 866 switch (c->processor_id & 0xff00) {
808 case PRID_IMP_BCM3302: 867 case PRID_IMP_BCM3302:
809 c->cputype = CPU_BCM3302; 868 c->cputype = CPU_BCM3302;
869 __cpu_name[cpu] = "Broadcom BCM3302";
810 break; 870 break;
811 case PRID_IMP_BCM4710: 871 case PRID_IMP_BCM4710:
812 c->cputype = CPU_BCM4710; 872 c->cputype = CPU_BCM4710;
813 break; 873 __cpu_name[cpu] = "Broadcom BCM4710";
814 default:
815 c->cputype = CPU_UNKNOWN;
816 break; 874 break;
817 } 875 }
818} 876}
819 877
820const char *__cpu_name[NR_CPUS]; 878const char *__cpu_name[NR_CPUS];
821 879
822/*
823 * Name a CPU
824 */
825static __cpuinit const char *cpu_to_name(struct cpuinfo_mips *c)
826{
827 const char *name = NULL;
828
829 switch (c->cputype) {
830 case CPU_UNKNOWN: name = "unknown"; break;
831 case CPU_R2000: name = "R2000"; break;
832 case CPU_R3000: name = "R3000"; break;
833 case CPU_R3000A: name = "R3000A"; break;
834 case CPU_R3041: name = "R3041"; break;
835 case CPU_R3051: name = "R3051"; break;
836 case CPU_R3052: name = "R3052"; break;
837 case CPU_R3081: name = "R3081"; break;
838 case CPU_R3081E: name = "R3081E"; break;
839 case CPU_R4000PC: name = "R4000PC"; break;
840 case CPU_R4000SC: name = "R4000SC"; break;
841 case CPU_R4000MC: name = "R4000MC"; break;
842 case CPU_R4200: name = "R4200"; break;
843 case CPU_R4400PC: name = "R4400PC"; break;
844 case CPU_R4400SC: name = "R4400SC"; break;
845 case CPU_R4400MC: name = "R4400MC"; break;
846 case CPU_R4600: name = "R4600"; break;
847 case CPU_R6000: name = "R6000"; break;
848 case CPU_R6000A: name = "R6000A"; break;
849 case CPU_R8000: name = "R8000"; break;
850 case CPU_R10000: name = "R10000"; break;
851 case CPU_R12000: name = "R12000"; break;
852 case CPU_R14000: name = "R14000"; break;
853 case CPU_R4300: name = "R4300"; break;
854 case CPU_R4650: name = "R4650"; break;
855 case CPU_R4700: name = "R4700"; break;
856 case CPU_R5000: name = "R5000"; break;
857 case CPU_R5000A: name = "R5000A"; break;
858 case CPU_R4640: name = "R4640"; break;
859 case CPU_NEVADA: name = "Nevada"; break;
860 case CPU_RM7000: name = "RM7000"; break;
861 case CPU_RM9000: name = "RM9000"; break;
862 case CPU_R5432: name = "R5432"; break;
863 case CPU_4KC: name = "MIPS 4Kc"; break;
864 case CPU_5KC: name = "MIPS 5Kc"; break;
865 case CPU_R4310: name = "R4310"; break;
866 case CPU_SB1: name = "SiByte SB1"; break;
867 case CPU_SB1A: name = "SiByte SB1A"; break;
868 case CPU_TX3912: name = "TX3912"; break;
869 case CPU_TX3922: name = "TX3922"; break;
870 case CPU_TX3927: name = "TX3927"; break;
871 case CPU_AU1000: name = "Au1000"; break;
872 case CPU_AU1500: name = "Au1500"; break;
873 case CPU_AU1100: name = "Au1100"; break;
874 case CPU_AU1550: name = "Au1550"; break;
875 case CPU_AU1200: name = "Au1200"; break;
876 case CPU_AU1210: name = "Au1210"; break;
877 case CPU_AU1250: name = "Au1250"; break;
878 case CPU_4KEC: name = "MIPS 4KEc"; break;
879 case CPU_4KSC: name = "MIPS 4KSc"; break;
880 case CPU_VR41XX: name = "NEC Vr41xx"; break;
881 case CPU_R5500: name = "R5500"; break;
882 case CPU_TX49XX: name = "TX49xx"; break;
883 case CPU_20KC: name = "MIPS 20Kc"; break;
884 case CPU_24K: name = "MIPS 24K"; break;
885 case CPU_25KF: name = "MIPS 25Kf"; break;
886 case CPU_34K: name = "MIPS 34K"; break;
887 case CPU_1004K: name = "MIPS 1004K"; break;
888 case CPU_74K: name = "MIPS 74K"; break;
889 case CPU_VR4111: name = "NEC VR4111"; break;
890 case CPU_VR4121: name = "NEC VR4121"; break;
891 case CPU_VR4122: name = "NEC VR4122"; break;
892 case CPU_VR4131: name = "NEC VR4131"; break;
893 case CPU_VR4133: name = "NEC VR4133"; break;
894 case CPU_VR4181: name = "NEC VR4181"; break;
895 case CPU_VR4181A: name = "NEC VR4181A"; break;
896 case CPU_SR71000: name = "Sandcraft SR71000"; break;
897 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
898 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
899 case CPU_PR4450: name = "Philips PR4450"; break;
900 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
901 default:
902 BUG();
903 }
904
905 return name;
906}
907
908__cpuinit void cpu_probe(void) 880__cpuinit void cpu_probe(void)
909{ 881{
910 struct cpuinfo_mips *c = &current_cpu_data; 882 struct cpuinfo_mips *c = &current_cpu_data;
@@ -917,30 +889,31 @@ __cpuinit void cpu_probe(void)
917 c->processor_id = read_c0_prid(); 889 c->processor_id = read_c0_prid();
918 switch (c->processor_id & 0xff0000) { 890 switch (c->processor_id & 0xff0000) {
919 case PRID_COMP_LEGACY: 891 case PRID_COMP_LEGACY:
920 cpu_probe_legacy(c); 892 cpu_probe_legacy(c, cpu);
921 break; 893 break;
922 case PRID_COMP_MIPS: 894 case PRID_COMP_MIPS:
923 cpu_probe_mips(c); 895 cpu_probe_mips(c, cpu);
924 break; 896 break;
925 case PRID_COMP_ALCHEMY: 897 case PRID_COMP_ALCHEMY:
926 cpu_probe_alchemy(c); 898 cpu_probe_alchemy(c, cpu);
927 break; 899 break;
928 case PRID_COMP_SIBYTE: 900 case PRID_COMP_SIBYTE:
929 cpu_probe_sibyte(c); 901 cpu_probe_sibyte(c, cpu);
930 break; 902 break;
931 case PRID_COMP_BROADCOM: 903 case PRID_COMP_BROADCOM:
932 cpu_probe_broadcom(c); 904 cpu_probe_broadcom(c, cpu);
933 break; 905 break;
934 case PRID_COMP_SANDCRAFT: 906 case PRID_COMP_SANDCRAFT:
935 cpu_probe_sandcraft(c); 907 cpu_probe_sandcraft(c, cpu);
936 break; 908 break;
937 case PRID_COMP_NXP: 909 case PRID_COMP_NXP:
938 cpu_probe_nxp(c); 910 cpu_probe_nxp(c, cpu);
939 break; 911 break;
940 default:
941 c->cputype = CPU_UNKNOWN;
942 } 912 }
943 913
914 BUG_ON(!__cpu_name[cpu]);
915 BUG_ON(c->cputype == CPU_UNKNOWN);
916
944 /* 917 /*
945 * Platform code can force the cpu type to optimize code 918 * Platform code can force the cpu type to optimize code
946 * generation. In that case be sure the cpu type is correctly 919 * generation. In that case be sure the cpu type is correctly
@@ -960,8 +933,6 @@ __cpuinit void cpu_probe(void)
960 } 933 }
961 } 934 }
962 935
963 __cpu_name[cpu] = cpu_to_name(c);
964
965 if (cpu_has_mips_r2) 936 if (cpu_has_mips_r2)
966 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 937 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
967 else 938 else
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 10:37:25 -0500