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authorKevin Corry <kevcorry@us.ibm.com>2006-11-20 12:45:13 -0500
committerPaul Mackerras <paulus@samba.org>2006-12-04 04:40:09 -0500
commitc93dfa0766bae3c92ec8311bddbbf16b8e661f59 (patch)
tree1ccfd56b93061c0d4b50b71ac05641d681cbc7f1
parent5231800c6fb99c106951a5e1a8e739ad9657e93f (diff)
[POWERPC] cell: PMU register macros
More macros for manipulating bits in the Cell PMU control registers. Signed-off-by: Kevin Corry <kevcorry@us.ibm.com> Signed-off-by: Carl Love <carll@us.ibm.com> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
-rw-r--r--arch/powerpc/platforms/cell/cbe_regs.h23
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/powerpc/platforms/cell/cbe_regs.h b/arch/powerpc/platforms/cell/cbe_regs.h
index 91083f51a0cb..bc94e664c617 100644
--- a/arch/powerpc/platforms/cell/cbe_regs.h
+++ b/arch/powerpc/platforms/cell/cbe_regs.h
@@ -38,7 +38,28 @@
38/* Macros for the pm_control register. */ 38/* Macros for the pm_control register. */
39#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1)))) 39#define CBE_PM_16BIT_CTR(ctr) (1 << (24 - ((ctr) & (NR_PHYS_CTRS - 1))))
40#define CBE_PM_ENABLE_PERF_MON 0x80000000 40#define CBE_PM_ENABLE_PERF_MON 0x80000000
41 41#define CBE_PM_STOP_AT_MAX 0x40000000
42#define CBE_PM_TRACE_MODE_GET(pm_control) (((pm_control) >> 28) & 0x3)
43#define CBE_PM_TRACE_MODE_SET(mode) (((mode) & 0x3) << 28)
44#define CBE_PM_COUNT_MODE_SET(count) (((count) & 0x3) << 18)
45#define CBE_PM_FREEZE_ALL_CTRS 0x00100000
46#define CBE_PM_ENABLE_EXT_TRACE 0x00008000
47
48/* Macros for the trace_address register. */
49#define CBE_PM_TRACE_BUF_FULL 0x00000800
50#define CBE_PM_TRACE_BUF_EMPTY 0x00000400
51#define CBE_PM_TRACE_BUF_DATA_COUNT(ta) ((ta) & 0x3ff)
52#define CBE_PM_TRACE_BUF_MAX_COUNT 0x400
53
54/* Macros for the pm07_control registers. */
55#define CBE_PM_CTR_INPUT_MUX(pm07_control) (((pm07_control) >> 26) & 0x3f)
56#define CBE_PM_CTR_INPUT_CONTROL 0x02000000
57#define CBE_PM_CTR_POLARITY 0x01000000
58#define CBE_PM_CTR_COUNT_CYCLES 0x00800000
59#define CBE_PM_CTR_ENABLE 0x00400000
60
61/* Macros for the pm_status register. */
62#define CBE_PM_CTR_OVERFLOW_INTR(ctr) (1 << (31 - ((ctr) & 7)))
42 63
43union spe_reg { 64union spe_reg {
44 u64 val; 65 u64 val;