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authorBen Cahill <ben.m.cahill@intel.com>2009-10-30 17:36:08 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-11-02 15:39:45 -0500
commitc72cd19fab7983e97a1a41b7158e0b9f87a7fe96 (patch)
tree848fbfa2d14143b0e3b0d40bae5dea5dd333f597
parenta6c5c731c3f783f60ed79dcf41efa8b5b3af2f22 (diff)
iwlagn: Clarify FH_TX interrupt
Add/clarify comments and debug messages for interrupt used only for uCode load Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-agn.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 6daaad1e4bc9..7751a75d4dc9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -1033,11 +1033,12 @@ static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1033 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 1033 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1034 } 1034 }
1035 1035
1036 /* This "Tx" DMA channel is used only for loading uCode */
1036 if (inta & CSR_INT_BIT_FH_TX) { 1037 if (inta & CSR_INT_BIT_FH_TX) {
1037 IWL_DEBUG_ISR(priv, "Tx interrupt\n"); 1038 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1038 priv->isr_stats.tx++; 1039 priv->isr_stats.tx++;
1039 handled |= CSR_INT_BIT_FH_TX; 1040 handled |= CSR_INT_BIT_FH_TX;
1040 /* FH finished to write, send event */ 1041 /* Wake up uCode load routine, now that load is complete */
1041 priv->ucode_write_complete = 1; 1042 priv->ucode_write_complete = 1;
1042 wake_up_interruptible(&priv->wait_command_queue); 1043 wake_up_interruptible(&priv->wait_command_queue);
1043 } 1044 }
@@ -1234,12 +1235,13 @@ static void iwl_irq_tasklet(struct iwl_priv *priv)
1234 iwl_leds_background(priv); 1235 iwl_leds_background(priv);
1235 } 1236 }
1236 1237
1238 /* This "Tx" DMA channel is used only for loading uCode */
1237 if (inta & CSR_INT_BIT_FH_TX) { 1239 if (inta & CSR_INT_BIT_FH_TX) {
1238 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK); 1240 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1239 IWL_DEBUG_ISR(priv, "Tx interrupt\n"); 1241 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1240 priv->isr_stats.tx++; 1242 priv->isr_stats.tx++;
1241 handled |= CSR_INT_BIT_FH_TX; 1243 handled |= CSR_INT_BIT_FH_TX;
1242 /* FH finished to write, send event */ 1244 /* Wake up uCode load routine, now that load is complete */
1243 priv->ucode_write_complete = 1; 1245 priv->ucode_write_complete = 1;
1244 wake_up_interruptible(&priv->wait_command_queue); 1246 wake_up_interruptible(&priv->wait_command_queue);
1245 } 1247 }