diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2011-07-12 11:53:23 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2011-07-13 02:47:13 -0400 |
commit | c61d0af9131976db150c40996a71387ba59edb67 (patch) | |
tree | df5b8699659928571cd839214f6cee688a943f53 | |
parent | 780d7cc44524cd396a34757127f51ecb8ccaf2da (diff) |
drm/radeon/kms/evergreen: emit SQ_LDS_RESOURCE_MGMT for blits
Compute drivers may change this, so make sure to emit it to
avoid errors in bo blits.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=39119
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_blit_kms.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index 57f3bc17b87e..2eb251858e72 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c | |||
@@ -252,7 +252,7 @@ draw_auto(struct radeon_device *rdev) | |||
252 | 252 | ||
253 | } | 253 | } |
254 | 254 | ||
255 | /* emits 36 */ | 255 | /* emits 39 */ |
256 | static void | 256 | static void |
257 | set_default_state(struct radeon_device *rdev) | 257 | set_default_state(struct radeon_device *rdev) |
258 | { | 258 | { |
@@ -531,6 +531,11 @@ set_default_state(struct radeon_device *rdev) | |||
531 | radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); | 531 | radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
532 | radeon_ring_write(rdev, 0); | 532 | radeon_ring_write(rdev, 0); |
533 | 533 | ||
534 | /* setup LDS */ | ||
535 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); | ||
536 | radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); | ||
537 | radeon_ring_write(rdev, 0x10001000); | ||
538 | |||
534 | /* SQ config */ | 539 | /* SQ config */ |
535 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); | 540 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
536 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); | 541 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
@@ -773,7 +778,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) | |||
773 | /* calculate number of loops correctly */ | 778 | /* calculate number of loops correctly */ |
774 | ring_size = num_loops * dwords_per_loop; | 779 | ring_size = num_loops * dwords_per_loop; |
775 | /* set default + shaders */ | 780 | /* set default + shaders */ |
776 | ring_size += 52; /* shaders + def state */ | 781 | ring_size += 55; /* shaders + def state */ |
777 | ring_size += 10; /* fence emit for VB IB */ | 782 | ring_size += 10; /* fence emit for VB IB */ |
778 | ring_size += 5; /* done copy */ | 783 | ring_size += 5; /* done copy */ |
779 | ring_size += 10; /* fence emit for done copy */ | 784 | ring_size += 10; /* fence emit for done copy */ |