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authorThomas Gleixner <tglx@linutronix.de>2008-01-30 07:30:35 -0500
committerIngo Molnar <mingo@elte.hu>2008-01-30 07:30:35 -0500
commitc2805aa1d8ae51c7582d2ccbd736afa545cf5cc4 (patch)
tree90ecc8370d0118300646f357a8e8d34a06df448a
parent64883ab0e3386d72112a9091d886352a7b4b8bf6 (diff)
x86: merge mpspec variants
The delta is now minimal. Merge them Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat
-rw-r--r--include/asm-x86/mpspec.h113
-rw-r--r--include/asm-x86/mpspec_32.h84
-rw-r--r--include/asm-x86/mpspec_64.h79
3 files changed, 111 insertions, 165 deletions
diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h
index 8f268e8fd2e9..a2a6b2ea4259 100644
--- a/include/asm-x86/mpspec.h
+++ b/include/asm-x86/mpspec.h
@@ -1,5 +1,114 @@
1#ifndef _AM_X86_MPSPEC_H
2#define _AM_X86_MPSPEC_H
3
4#include <asm/mpspec_def.h>
5
1#ifdef CONFIG_X86_32 6#ifdef CONFIG_X86_32
2# include "mpspec_32.h" 7#include <mach_mpspec.h>
8
9extern int mp_bus_id_to_type[MAX_MP_BUSSES];
10extern int mp_bus_id_to_node[MAX_MP_BUSSES];
11extern int mp_bus_id_to_local[MAX_MP_BUSSES];
12extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
13
14extern unsigned int def_to_bigsmp;
15extern int apic_version[MAX_APICS];
16extern int pic_mode;
17
3#else 18#else
4# include "mpspec_64.h" 19
20#define MAX_MP_BUSSES 256
21/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
22#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
23
24extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
25
26#endif
27
28extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
29
30extern unsigned int boot_cpu_physical_apicid;
31extern int smp_found_config;
32extern int nr_ioapics;
33extern int mp_irq_entries;
34extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
35extern int mpc_default_type;
36extern unsigned long mp_lapic_addr;
37
38extern void find_smp_config(void);
39extern void get_smp_config(void);
40
41#ifdef CONFIG_ACPI
42extern void mp_register_lapic(u8 id, u8 enabled);
43extern void mp_register_lapic_address(u64 address);
44extern void mp_register_ioapic(u8 id, u32 address, u32 gsi_base);
45extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
46 u32 gsi);
47extern void mp_config_acpi_legacy_irqs(void);
48extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
49#endif /* CONFIG_ACPI */
50
51#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
52
53struct physid_mask
54{
55 unsigned long mask[PHYSID_ARRAY_SIZE];
56};
57
58typedef struct physid_mask physid_mask_t;
59
60#define physid_set(physid, map) set_bit(physid, (map).mask)
61#define physid_clear(physid, map) clear_bit(physid, (map).mask)
62#define physid_isset(physid, map) test_bit(physid, (map).mask)
63#define physid_test_and_set(physid, map) \
64 test_and_set_bit(physid, (map).mask)
65
66#define physids_and(dst, src1, src2) \
67 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
68
69#define physids_or(dst, src1, src2) \
70 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
71
72#define physids_clear(map) \
73 bitmap_zero((map).mask, MAX_APICS)
74
75#define physids_complement(dst, src) \
76 bitmap_complement((dst).mask, (src).mask, MAX_APICS)
77
78#define physids_empty(map) \
79 bitmap_empty((map).mask, MAX_APICS)
80
81#define physids_equal(map1, map2) \
82 bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
83
84#define physids_weight(map) \
85 bitmap_weight((map).mask, MAX_APICS)
86
87#define physids_shift_right(d, s, n) \
88 bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
89
90#define physids_shift_left(d, s, n) \
91 bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
92
93#define physids_coerce(map) ((map).mask[0])
94
95#define physids_promote(physids) \
96 ({ \
97 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
98 __physid_mask.mask[0] = physids; \
99 __physid_mask; \
100 })
101
102#define physid_mask_of_physid(physid) \
103 ({ \
104 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
105 physid_set(physid, __physid_mask); \
106 __physid_mask; \
107 })
108
109#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
110#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
111
112extern physid_mask_t phys_cpu_present_map;
113
5#endif 114#endif
diff --git a/include/asm-x86/mpspec_32.h b/include/asm-x86/mpspec_32.h
deleted file mode 100644
index bb73185e6a7d..000000000000
--- a/include/asm-x86/mpspec_32.h
+++ /dev/null
@@ -1,84 +0,0 @@
1#ifndef __ASM_MPSPEC_H
2#define __ASM_MPSPEC_H
3
4#include <asm/mpspec_def.h>
5#include <mach_mpspec.h>
6
7extern int mp_bus_id_to_type[MAX_MP_BUSSES];
8extern int mp_bus_id_to_node[MAX_MP_BUSSES];
9extern int mp_bus_id_to_local[MAX_MP_BUSSES];
10extern int quad_local_to_mp_bus_id[NR_CPUS/4][4];
11
12extern unsigned int def_to_bigsmp;
13extern int apic_version[MAX_APICS];
14extern int pic_mode;
15
16extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
17
18extern unsigned int boot_cpu_physical_apicid;
19extern int smp_found_config;
20extern int nr_ioapics;
21extern int mp_irq_entries;
22extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
23extern int mpc_default_type;
24extern unsigned long mp_lapic_addr;
25
26extern void find_smp_config (void);
27extern void get_smp_config (void);
28
29#ifdef CONFIG_ACPI
30extern void mp_register_lapic (u8 id, u8 enabled);
31extern void mp_register_lapic_address (u64 address);
32extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
33extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
34 u32 gsi);
35extern void mp_config_acpi_legacy_irqs (void);
36extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
37#endif /* CONFIG_ACPI */
38
39#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
40
41struct physid_mask
42{
43 unsigned long mask[PHYSID_ARRAY_SIZE];
44};
45
46typedef struct physid_mask physid_mask_t;
47
48#define physid_set(physid, map) set_bit(physid, (map).mask)
49#define physid_clear(physid, map) clear_bit(physid, (map).mask)
50#define physid_isset(physid, map) test_bit(physid, (map).mask)
51#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
52
53#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
54#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
55#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
56#define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS)
57#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
58#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
59#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
60#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
61#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
62#define physids_coerce(map) ((map).mask[0])
63
64#define physids_promote(physids) \
65 ({ \
66 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
67 __physid_mask.mask[0] = physids; \
68 __physid_mask; \
69 })
70
71#define physid_mask_of_physid(physid) \
72 ({ \
73 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
74 physid_set(physid, __physid_mask); \
75 __physid_mask; \
76 })
77
78#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
79#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
80
81extern physid_mask_t phys_cpu_present_map;
82
83#endif
84
diff --git a/include/asm-x86/mpspec_64.h b/include/asm-x86/mpspec_64.h
deleted file mode 100644
index 16eab20667cd..000000000000
--- a/include/asm-x86/mpspec_64.h
+++ /dev/null
@@ -1,79 +0,0 @@
1#ifndef __ASM_MPSPEC_H
2#define __ASM_MPSPEC_H
3
4#include <asm/mpspec_def.h>
5
6#define MAX_MP_BUSSES 256
7/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
8#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
9extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
10
11extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
12
13extern unsigned int boot_cpu_physical_apicid;
14extern int smp_found_config;
15extern int nr_ioapics;
16extern int mp_irq_entries;
17extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
18extern int mpc_default_type;
19extern unsigned long mp_lapic_addr;
20
21extern void find_smp_config (void);
22extern void get_smp_config (void);
23
24#ifdef CONFIG_ACPI
25extern void mp_register_lapic (u8 id, u8 enabled);
26extern void mp_register_lapic_address (u64 address);
27extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base);
28extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger,
29 u32 gsi);
30extern void mp_config_acpi_legacy_irqs (void);
31extern int mp_register_gsi (u32 gsi, int edge_level, int active_high_low);
32#endif /* CONFIG_ACPI */
33
34#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
35
36struct physid_mask
37{
38 unsigned long mask[PHYSID_ARRAY_SIZE];
39};
40
41typedef struct physid_mask physid_mask_t;
42
43#define physid_set(physid, map) set_bit(physid, (map).mask)
44#define physid_clear(physid, map) clear_bit(physid, (map).mask)
45#define physid_isset(physid, map) test_bit(physid, (map).mask)
46#define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
47
48#define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
49#define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
50#define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
51#define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS)
52#define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
53#define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
54#define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
55#define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
56#define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
57#define physids_coerce(map) ((map).mask[0])
58
59#define physids_promote(physids) \
60 ({ \
61 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
62 __physid_mask.mask[0] = physids; \
63 __physid_mask; \
64 })
65
66#define physid_mask_of_physid(physid) \
67 ({ \
68 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
69 physid_set(physid, __physid_mask); \
70 __physid_mask; \
71 })
72
73#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
74#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
75
76extern physid_mask_t phys_cpu_present_map;
77
78#endif
79
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