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authorArchit Taneja <archit@ti.com>2012-01-30 00:22:39 -0500
committerTomi Valkeinen <tomi.valkeinen@ti.com>2012-02-21 02:39:20 -0500
commitc124f23dfdf7da890405dfa0efbeb015cab27b56 (patch)
tree4e1df2019228046168f47e8a9dc8dd0c399e05e8
parentcd3b34493f9b5de1d617e0be39f6cb5c59c9889c (diff)
OMAPDSS: Features: Maintain dss_feats as a list
The number of dss_feat_id members has increased to a large value, the current way of assigning a subset of these features (for a particular OMAP) as a mask is no longer feasible. Maintain the subset of features supported as lists. Make the function dss_has_feature() traverse through this list. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat
-rw-r--r--drivers/video/omap2/dss/dss_features.c140
-rw-r--r--drivers/video/omap2/dss/dss_features.h54
2 files changed, 128 insertions, 66 deletions
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index 419419ad0493..656cb69f4640 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -41,7 +41,8 @@ struct omap_dss_features {
41 const struct dss_reg_field *reg_fields; 41 const struct dss_reg_field *reg_fields;
42 const int num_reg_fields; 42 const int num_reg_fields;
43 43
44 const u32 has_feature; 44 const enum dss_feat_id *features;
45 const int num_features;
45 46
46 const int num_mgrs; 47 const int num_mgrs;
47 const int num_ovls; 48 const int num_ovls;
@@ -337,15 +338,92 @@ static const struct dss_param_range omap4_dss_param_range[] = {
337 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 }, 338 [FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
338}; 339};
339 340
341static const enum dss_feat_id omap2_dss_feat_list[] = {
342 FEAT_LCDENABLEPOL,
343 FEAT_LCDENABLESIGNAL,
344 FEAT_PCKFREEENABLE,
345 FEAT_FUNCGATED,
346 FEAT_ROWREPEATENABLE,
347 FEAT_RESIZECONF,
348};
349
350static const enum dss_feat_id omap3430_dss_feat_list[] = {
351 FEAT_LCDENABLEPOL,
352 FEAT_LCDENABLESIGNAL,
353 FEAT_PCKFREEENABLE,
354 FEAT_FUNCGATED,
355 FEAT_LINEBUFFERSPLIT,
356 FEAT_ROWREPEATENABLE,
357 FEAT_RESIZECONF,
358 FEAT_DSI_PLL_FREQSEL,
359 FEAT_DSI_REVERSE_TXCLKESC,
360 FEAT_VENC_REQUIRES_TV_DAC_CLK,
361 FEAT_CPR,
362 FEAT_PRELOAD,
363 FEAT_FIR_COEF_V,
364 FEAT_ALPHA_FIXED_ZORDER,
365 FEAT_FIFO_MERGE,
366 FEAT_OMAP3_DSI_FIFO_BUG,
367};
368
369static const enum dss_feat_id omap3630_dss_feat_list[] = {
370 FEAT_LCDENABLEPOL,
371 FEAT_LCDENABLESIGNAL,
372 FEAT_PCKFREEENABLE,
373 FEAT_FUNCGATED,
374 FEAT_LINEBUFFERSPLIT,
375 FEAT_ROWREPEATENABLE,
376 FEAT_RESIZECONF,
377 FEAT_DSI_PLL_PWR_BUG,
378 FEAT_DSI_PLL_FREQSEL,
379 FEAT_CPR,
380 FEAT_PRELOAD,
381 FEAT_FIR_COEF_V,
382 FEAT_ALPHA_FIXED_ZORDER,
383 FEAT_FIFO_MERGE,
384 FEAT_OMAP3_DSI_FIFO_BUG,
385};
386
387static const enum dss_feat_id omap4430_es1_0_dss_feat_list[] = {
388 FEAT_MGR_LCD2,
389 FEAT_CORE_CLK_DIV,
390 FEAT_LCD_CLK_SRC,
391 FEAT_DSI_DCS_CMD_CONFIG_VC,
392 FEAT_DSI_VC_OCP_WIDTH,
393 FEAT_DSI_GNQ,
394 FEAT_HANDLE_UV_SEPARATE,
395 FEAT_ATTR2,
396 FEAT_CPR,
397 FEAT_PRELOAD,
398 FEAT_FIR_COEF_V,
399 FEAT_ALPHA_FREE_ZORDER,
400 FEAT_FIFO_MERGE,
401};
402
403static const enum dss_feat_id omap4_dss_feat_list[] = {
404 FEAT_MGR_LCD2,
405 FEAT_CORE_CLK_DIV,
406 FEAT_LCD_CLK_SRC,
407 FEAT_DSI_DCS_CMD_CONFIG_VC,
408 FEAT_DSI_VC_OCP_WIDTH,
409 FEAT_DSI_GNQ,
410 FEAT_HDMI_CTS_SWMODE,
411 FEAT_HANDLE_UV_SEPARATE,
412 FEAT_ATTR2,
413 FEAT_CPR,
414 FEAT_PRELOAD,
415 FEAT_FIR_COEF_V,
416 FEAT_ALPHA_FREE_ZORDER,
417 FEAT_FIFO_MERGE,
418};
419
340/* OMAP2 DSS Features */ 420/* OMAP2 DSS Features */
341static const struct omap_dss_features omap2_dss_features = { 421static const struct omap_dss_features omap2_dss_features = {
342 .reg_fields = omap2_dss_reg_fields, 422 .reg_fields = omap2_dss_reg_fields,
343 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields), 423 .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
344 424
345 .has_feature = 425 .features = omap2_dss_feat_list,
346 FEAT_LCDENABLEPOL | FEAT_LCDENABLESIGNAL | 426 .num_features = ARRAY_SIZE(omap2_dss_feat_list),
347 FEAT_PCKFREEENABLE | FEAT_FUNCGATED |
348 FEAT_ROWREPEATENABLE | FEAT_RESIZECONF,
349 427
350 .num_mgrs = 2, 428 .num_mgrs = 2,
351 .num_ovls = 3, 429 .num_ovls = 3,
@@ -363,15 +441,8 @@ static const struct omap_dss_features omap3430_dss_features = {
363 .reg_fields = omap3_dss_reg_fields, 441 .reg_fields = omap3_dss_reg_fields,
364 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), 442 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
365 443
366 .has_feature = 444 .features = omap3430_dss_feat_list,
367 FEAT_LCDENABLEPOL | 445 .num_features = ARRAY_SIZE(omap3430_dss_feat_list),
368 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
369 FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
370 FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
371 FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC |
372 FEAT_VENC_REQUIRES_TV_DAC_CLK | FEAT_CPR | FEAT_PRELOAD |
373 FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
374 FEAT_OMAP3_DSI_FIFO_BUG,
375 446
376 .num_mgrs = 2, 447 .num_mgrs = 2,
377 .num_ovls = 3, 448 .num_ovls = 3,
@@ -388,15 +459,8 @@ static const struct omap_dss_features omap3630_dss_features = {
388 .reg_fields = omap3_dss_reg_fields, 459 .reg_fields = omap3_dss_reg_fields,
389 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), 460 .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
390 461
391 .has_feature = 462 .features = omap3630_dss_feat_list,
392 FEAT_LCDENABLEPOL | 463 .num_features = ARRAY_SIZE(omap3630_dss_feat_list),
393 FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
394 FEAT_FUNCGATED |
395 FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
396 FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
397 FEAT_DSI_PLL_FREQSEL | FEAT_CPR | FEAT_PRELOAD |
398 FEAT_FIR_COEF_V | FEAT_ALPHA_FIXED_ZORDER | FEAT_FIFO_MERGE |
399 FEAT_OMAP3_DSI_FIFO_BUG,
400 464
401 .num_mgrs = 2, 465 .num_mgrs = 2,
402 .num_ovls = 3, 466 .num_ovls = 3,
@@ -415,13 +479,8 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = {
415 .reg_fields = omap4_dss_reg_fields, 479 .reg_fields = omap4_dss_reg_fields,
416 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), 480 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
417 481
418 .has_feature = 482 .features = omap4430_es1_0_dss_feat_list,
419 FEAT_MGR_LCD2 | 483 .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list),
420 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
421 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
422 FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 |
423 FEAT_CPR | FEAT_PRELOAD | FEAT_FIR_COEF_V |
424 FEAT_ALPHA_FREE_ZORDER | FEAT_FIFO_MERGE,
425 484
426 .num_mgrs = 3, 485 .num_mgrs = 3,
427 .num_ovls = 4, 486 .num_ovls = 4,
@@ -439,14 +498,8 @@ static const struct omap_dss_features omap4_dss_features = {
439 .reg_fields = omap4_dss_reg_fields, 498 .reg_fields = omap4_dss_reg_fields,
440 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), 499 .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
441 500
442 .has_feature = 501 .features = omap4_dss_feat_list,
443 FEAT_MGR_LCD2 | 502 .num_features = ARRAY_SIZE(omap4_dss_feat_list),
444 FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
445 FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
446 FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
447 FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
448 FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER |
449 FEAT_FIFO_MERGE,
450 503
451 .num_mgrs = 3, 504 .num_mgrs = 3,
452 .num_ovls = 4, 505 .num_ovls = 4,
@@ -550,7 +603,16 @@ u32 dss_feat_get_burst_size_unit(void)
550/* DSS has_feature check */ 603/* DSS has_feature check */
551bool dss_has_feature(enum dss_feat_id id) 604bool dss_has_feature(enum dss_feat_id id)
552{ 605{
553 return omap_current_dss_features->has_feature & id; 606 int i;
607 const enum dss_feat_id *features = omap_current_dss_features->features;
608 const int num_features = omap_current_dss_features->num_features;
609
610 for (i = 0; i < num_features; i++) {
611 if (features[i] == id)
612 return true;
613 }
614
615 return false;
554} 616}
555 617
556void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end) 618void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end)
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 5f9b82156778..682f091cf02e 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -31,36 +31,36 @@
31 31
32/* DSS has feature id */ 32/* DSS has feature id */
33enum dss_feat_id { 33enum dss_feat_id {
34 FEAT_LCDENABLEPOL = 1 << 3, 34 FEAT_LCDENABLEPOL,
35 FEAT_LCDENABLESIGNAL = 1 << 4, 35 FEAT_LCDENABLESIGNAL,
36 FEAT_PCKFREEENABLE = 1 << 5, 36 FEAT_PCKFREEENABLE,
37 FEAT_FUNCGATED = 1 << 6, 37 FEAT_FUNCGATED,
38 FEAT_MGR_LCD2 = 1 << 7, 38 FEAT_MGR_LCD2,
39 FEAT_LINEBUFFERSPLIT = 1 << 8, 39 FEAT_LINEBUFFERSPLIT,
40 FEAT_ROWREPEATENABLE = 1 << 9, 40 FEAT_ROWREPEATENABLE,
41 FEAT_RESIZECONF = 1 << 10, 41 FEAT_RESIZECONF,
42 /* Independent core clk divider */ 42 /* Independent core clk divider */
43 FEAT_CORE_CLK_DIV = 1 << 11, 43 FEAT_CORE_CLK_DIV,
44 FEAT_LCD_CLK_SRC = 1 << 12, 44 FEAT_LCD_CLK_SRC,
45 /* DSI-PLL power command 0x3 is not working */ 45 /* DSI-PLL power command 0x3 is not working */
46 FEAT_DSI_PLL_PWR_BUG = 1 << 13, 46 FEAT_DSI_PLL_PWR_BUG,
47 FEAT_DSI_PLL_FREQSEL = 1 << 14, 47 FEAT_DSI_PLL_FREQSEL,
48 FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15, 48 FEAT_DSI_DCS_CMD_CONFIG_VC,
49 FEAT_DSI_VC_OCP_WIDTH = 1 << 16, 49 FEAT_DSI_VC_OCP_WIDTH,
50 FEAT_DSI_REVERSE_TXCLKESC = 1 << 17, 50 FEAT_DSI_REVERSE_TXCLKESC,
51 FEAT_DSI_GNQ = 1 << 18, 51 FEAT_DSI_GNQ,
52 FEAT_HDMI_CTS_SWMODE = 1 << 19, 52 FEAT_HDMI_CTS_SWMODE,
53 FEAT_HANDLE_UV_SEPARATE = 1 << 20, 53 FEAT_HANDLE_UV_SEPARATE,
54 FEAT_ATTR2 = 1 << 21, 54 FEAT_ATTR2,
55 FEAT_VENC_REQUIRES_TV_DAC_CLK = 1 << 22, 55 FEAT_VENC_REQUIRES_TV_DAC_CLK,
56 FEAT_CPR = 1 << 23, 56 FEAT_CPR,
57 FEAT_PRELOAD = 1 << 24, 57 FEAT_PRELOAD,
58 FEAT_FIR_COEF_V = 1 << 25, 58 FEAT_FIR_COEF_V,
59 FEAT_ALPHA_FIXED_ZORDER = 1 << 26, 59 FEAT_ALPHA_FIXED_ZORDER,
60 FEAT_ALPHA_FREE_ZORDER = 1 << 27, 60 FEAT_ALPHA_FREE_ZORDER,
61 FEAT_FIFO_MERGE = 1 << 28, 61 FEAT_FIFO_MERGE,
62 /* An unknown HW bug causing the normal FIFO thresholds not to work */ 62 /* An unknown HW bug causing the normal FIFO thresholds not to work */
63 FEAT_OMAP3_DSI_FIFO_BUG = 1 << 29, 63 FEAT_OMAP3_DSI_FIFO_BUG,
64}; 64};
65 65
66/* DSS register field id */ 66/* DSS register field id */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 14:37:49 -0500