diff options
author | Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | 2011-10-24 08:43:40 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-11-02 15:23:12 -0400 |
commit | 98fb2cc115b4ef1ea0a2d87a170c183bd395dd6c (patch) | |
tree | 31a8695c8b335360719de7260662b53963cf5c22 | |
parent | e3a4cc2f073739c9c9c2e97efc774703061f034a (diff) |
ath9k_hw: Update AR9485 initvals to fix system hang issue
This patch fixes system hang when resuming from S3 state
and lower rate sens failure issue.
Cc: stable@kernel.org
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9485_initvals.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h index 611ea6ce8508..d16d029f81a9 100644 --- a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h +++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h | |||
@@ -521,7 +521,7 @@ static const u32 ar9485_1_1_radio_postamble[][2] = { | |||
521 | {0x000160ac, 0x24611800}, | 521 | {0x000160ac, 0x24611800}, |
522 | {0x000160b0, 0x03284f3e}, | 522 | {0x000160b0, 0x03284f3e}, |
523 | {0x0001610c, 0x00170000}, | 523 | {0x0001610c, 0x00170000}, |
524 | {0x00016140, 0x10804008}, | 524 | {0x00016140, 0x50804008}, |
525 | }; | 525 | }; |
526 | 526 | ||
527 | static const u32 ar9485_1_1_mac_postamble[][5] = { | 527 | static const u32 ar9485_1_1_mac_postamble[][5] = { |
@@ -603,7 +603,7 @@ static const u32 ar9485_1_1_radio_core[][2] = { | |||
603 | 603 | ||
604 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { | 604 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = { |
605 | /* Addr allmodes */ | 605 | /* Addr allmodes */ |
606 | {0x00018c00, 0x10052e5e}, | 606 | {0x00018c00, 0x18052e5e}, |
607 | {0x00018c04, 0x000801d8}, | 607 | {0x00018c04, 0x000801d8}, |
608 | {0x00018c08, 0x0000080c}, | 608 | {0x00018c08, 0x0000080c}, |
609 | }; | 609 | }; |
@@ -776,7 +776,7 @@ static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = { | |||
776 | 776 | ||
777 | static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { | 777 | static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = { |
778 | /* Addr allmodes */ | 778 | /* Addr allmodes */ |
779 | {0x00018c00, 0x10013e5e}, | 779 | {0x00018c00, 0x18013e5e}, |
780 | {0x00018c04, 0x000801d8}, | 780 | {0x00018c04, 0x000801d8}, |
781 | {0x00018c08, 0x0000080c}, | 781 | {0x00018c08, 0x0000080c}, |
782 | }; | 782 | }; |
@@ -882,7 +882,7 @@ static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = { | |||
882 | 882 | ||
883 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { | 883 | static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = { |
884 | /* Addr allmodes */ | 884 | /* Addr allmodes */ |
885 | {0x00018c00, 0x10012e5e}, | 885 | {0x00018c00, 0x18012e5e}, |
886 | {0x00018c04, 0x000801d8}, | 886 | {0x00018c04, 0x000801d8}, |
887 | {0x00018c08, 0x0000080c}, | 887 | {0x00018c08, 0x0000080c}, |
888 | }; | 888 | }; |
@@ -1021,7 +1021,7 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = { | |||
1021 | 1021 | ||
1022 | static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { | 1022 | static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = { |
1023 | /* Addr allmodes */ | 1023 | /* Addr allmodes */ |
1024 | {0x00018c00, 0x10053e5e}, | 1024 | {0x00018c00, 0x18053e5e}, |
1025 | {0x00018c04, 0x000801d8}, | 1025 | {0x00018c04, 0x000801d8}, |
1026 | {0x00018c08, 0x0000080c}, | 1026 | {0x00018c08, 0x0000080c}, |
1027 | }; | 1027 | }; |