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authorKumar Gala <galak@kernel.crashing.org>2010-10-08 03:13:25 -0400
committerKumar Gala <galak@kernel.crashing.org>2010-10-14 01:55:09 -0400
commit988cf86d4f0da4150e808300c145ba87c0aad02f (patch)
treeb6b1c4ce5e06722bacff5b1fc852ae9de4f54530
parent4490c06b581ad7d6392bb398960ef86dfd203a91 (diff)
powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes
Update setup_page_sizes() to support for a MMU v1.0 FSL style MMU implementation. In such a processor, we don't have TLB0PS or EPTCFG registers (and access to these registers may cause exceptions). We need to parse the older format of TLBnCFG for page size support. Additionaly, assume since we are an FSL implementation that we have 2 TLB arrays and the second array contains the variable size pages. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/include/asm/mmu-book3e.h15
-rw-r--r--arch/powerpc/mm/tlb_nohash.c42
2 files changed, 54 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h
index 87a1d787c5b6..8eaed81ea642 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -114,6 +114,17 @@
114 114
115#define MAS7_RPN 0xFFFFFFFF 115#define MAS7_RPN 0xFFFFFFFF
116 116
117/* Bit definitions for MMUCFG */
118#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
119#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
120#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
121#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
122#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
123#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
124#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
125#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
126#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
127
117/* Bit definitions for MMUCSR0 */ 128/* Bit definitions for MMUCSR0 */
118#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 129#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
119#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 130#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
@@ -133,6 +144,10 @@
133#define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 144#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
134#define TLBnCFG_IND 0x00020000 /* IND entries supported */ 145#define TLBnCFG_IND 0x00020000 /* IND entries supported */
135#define TLBnCFG_PT 0x00040000 /* Can load from page table */ 146#define TLBnCFG_PT 0x00040000 /* Can load from page table */
147#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
148#define TLBnCFG_MINSIZE_SHIFT 20
149#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
150#define TLBnCFG_MAXSIZE_SHIFT 16
136#define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 151#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
137 152
138/* TLBnPS encoding */ 153/* TLBnPS encoding */
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index fe391e942521..665189920762 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -349,11 +349,47 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
349 349
350static void setup_page_sizes(void) 350static void setup_page_sizes(void)
351{ 351{
352 unsigned int tlb0cfg = mfspr(SPRN_TLB0CFG); 352 unsigned int tlb0cfg;
353 unsigned int tlb0ps = mfspr(SPRN_TLB0PS); 353 unsigned int tlb0ps;
354 unsigned int eptcfg = mfspr(SPRN_EPTCFG); 354 unsigned int eptcfg;
355 int i, psize; 355 int i, psize;
356 356
357#ifdef CONFIG_PPC_FSL_BOOK3E
358 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
359
360 if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
361 (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
362 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
363 unsigned int min_pg, max_pg;
364
365 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
366 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
367
368 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
369 struct mmu_psize_def *def;
370 unsigned int shift;
371
372 def = &mmu_psize_defs[psize];
373 shift = def->shift;
374
375 if (shift == 0)
376 continue;
377
378 /* adjust to be in terms of 4^shift Kb */
379 shift = (shift - 10) >> 1;
380
381 if ((shift >= min_pg) && (shift <= max_pg))
382 def->flags |= MMU_PAGE_SIZE_DIRECT;
383 }
384
385 goto no_indirect;
386 }
387#endif
388
389 tlb0cfg = mfspr(SPRN_TLB0CFG);
390 tlb0ps = mfspr(SPRN_TLB0PS);
391 eptcfg = mfspr(SPRN_EPTCFG);
392
357 /* Look for supported direct sizes */ 393 /* Look for supported direct sizes */
358 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) { 394 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
359 struct mmu_psize_def *def = &mmu_psize_defs[psize]; 395 struct mmu_psize_def *def = &mmu_psize_defs[psize];