ARM: 6794/1: SPEAr: Append UL to device address macros.

Reviewed-by: Stanley Miao <stanley.miao@windriver.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
author: Shiraz Hashim <shiraz.hashim@st.com> 2011-03-06 23:57:08 -0500
committer: Russell King <rmk+kernel@arm.linux.org.uk> 2011-03-09 04:50:04 -0500
commit: 981a95d37126cdf09e1dba3884305c2e25375bfb (patch)
tree: 280cad24a89b16dd91b392b50a6f7c141183c243
parent: 8fc4ef451eebc72d10c6987b59ec3316da62f02b (diff)
5 files changed, 126 insertions, 123 deletions
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index df60e3004aa5..63fd98356919 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -14,60 +14,61 @@
 #ifndef __MACH_SPEAR3XX_H
 #define __MACH_SPEAR3XX_H
+#include <asm/memory.h>
 #include <mach/spear300.h>
 #include <mach/spear310.h>
 #include <mach/spear320.h>
-#define SPEAR3XX_ML_SDRAM_BASE          0x00000000
+#define SPEAR3XX_ML_SDRAM_BASE          UL(0x00000000)
-#define SPEAR3XX_ICM9_BASE              0xC0000000
+#define SPEAR3XX_ICM9_BASE              UL(0xC0000000)
 /* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE            0xD0000000
+#define SPEAR3XX_ICM1_2_BASE            UL(0xD0000000)
-#define SPEAR3XX_ICM1_UART_BASE         0xD0000000
+#define SPEAR3XX_ICM1_UART_BASE         UL(0xD0000000)
 #define VA_SPEAR3XX_ICM1_UART_BASE      IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE          0xD0080000
+#define SPEAR3XX_ICM1_ADC_BASE          UL(0xD0080000)
-#define SPEAR3XX_ICM1_SSP_BASE          0xD0100000
+#define SPEAR3XX_ICM1_SSP_BASE          UL(0xD0100000)
-#define SPEAR3XX_ICM1_I2C_BASE          0xD0180000
+#define SPEAR3XX_ICM1_I2C_BASE          UL(0xD0180000)
-#define SPEAR3XX_ICM1_JPEG_BASE         0xD0800000
+#define SPEAR3XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR3XX_ICM1_IRDA_BASE         0xD1000000
+#define SPEAR3XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR3XX_ICM1_SRAM_BASE         0xD2800000
+#define SPEAR3XX_ICM1_SRAM_BASE         UL(0xD2800000)
 /* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE     0xD8800000
+#define SPEAR3XX_ICM2_HWACCEL0_BASE     UL(0xD8800000)
-#define SPEAR3XX_ICM2_HWACCEL1_BASE     0xD9000000
+#define SPEAR3XX_ICM2_HWACCEL1_BASE     UL(0xD9000000)
 /* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE              0xE0000000
+#define SPEAR3XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR3XX_ICM4_MII_BASE          0xE0800000
+#define SPEAR3XX_ICM4_MII_BASE          UL(0xE0800000)
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE    0xE1000000
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR3XX_ICM4_USBD_CSR_BASE     0xE1100000
+#define SPEAR3XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE    0xE1200000
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  0xE1800000
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE  UL(0xE1800000)
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE    0xE1900000
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE    0xE2100000
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR3XX_ICM4_USB_ARB_BASE      0xE2800000
+#define SPEAR3XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 /* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE        0xF0000000
+#define SPEAR3XX_ICM3_ML1_2_BASE        UL(0xF0000000)
-#define SPEAR3XX_ML1_TMR_BASE           0xF0000000
+#define SPEAR3XX_ML1_TMR_BASE           UL(0xF0000000)
-#define SPEAR3XX_ML1_VIC_BASE           0xF1100000
+#define SPEAR3XX_ML1_VIC_BASE           UL(0xF1100000)
 #define VA_SPEAR3XX_ML1_VIC_BASE        IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE         0xF8000000
+#define SPEAR3XX_ICM3_SMEM_BASE         UL(0xF8000000)
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE     0xFC000000
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR3XX_ICM3_DMA_BASE          0xFC400000
+#define SPEAR3XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   0xFC600000
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR3XX_ICM3_TMR0_BASE         0xFC800000
+#define SPEAR3XX_ICM3_TMR0_BASE         UL(0xFC800000)
-#define SPEAR3XX_ICM3_WDT_BASE          0xFC880000
+#define SPEAR3XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR3XX_ICM3_RTC_BASE          0xFC900000
+#define SPEAR3XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR3XX_ICM3_GPIO_BASE         0xFC980000
+#define SPEAR3XX_ICM3_GPIO_BASE         UL(0xFC980000)
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE     0xFCA00000
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_BASE     0xFCA80000
+#define SPEAR3XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE         0xFCB00000
+#define SPEAR3XX_ICM3_TMR1_BASE         UL(0xFCB00000)
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index 8f96cc569591..c723515f8853 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -17,7 +17,7 @@
 #define __MACH_SPEAR300_H
 /* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE           0x50000000
+#define SPEAR300_TELECOM_BASE           UL(0x50000000)
 /* Interrupt registers offsets and masks */
 #define INT_ENB_MASK_REG                0x54
@@ -34,20 +34,20 @@
 #define SHIRQ_RAS1_MASK                 0x1FF
-#define SPEAR300_CLCD_BASE              0x60000000
+#define SPEAR300_CLCD_BASE              UL(0x60000000)
-#define SPEAR300_SDHCI_BASE             0x70000000
+#define SPEAR300_SDHCI_BASE             UL(0x70000000)
-#define SPEAR300_NAND_0_BASE            0x80000000
+#define SPEAR300_NAND_0_BASE            UL(0x80000000)
-#define SPEAR300_NAND_1_BASE            0x84000000
+#define SPEAR300_NAND_1_BASE            UL(0x84000000)
-#define SPEAR300_NAND_2_BASE            0x88000000
+#define SPEAR300_NAND_2_BASE            UL(0x88000000)
-#define SPEAR300_NAND_3_BASE            0x8c000000
+#define SPEAR300_NAND_3_BASE            UL(0x8c000000)
-#define SPEAR300_NOR_0_BASE             0x90000000
+#define SPEAR300_NOR_0_BASE             UL(0x90000000)
-#define SPEAR300_NOR_1_BASE             0x91000000
+#define SPEAR300_NOR_1_BASE             UL(0x91000000)
-#define SPEAR300_NOR_2_BASE             0x92000000
+#define SPEAR300_NOR_2_BASE             UL(0x92000000)
-#define SPEAR300_NOR_3_BASE             0x93000000
+#define SPEAR300_NOR_3_BASE             UL(0x93000000)
-#define SPEAR300_FSMC_BASE              0x94000000
+#define SPEAR300_FSMC_BASE              UL(0x94000000)
-#define SPEAR300_SOC_CONFIG_BASE        0x99000000
+#define SPEAR300_SOC_CONFIG_BASE        UL(0x99000000)
-#define SPEAR300_KEYBOARD_BASE          0xA0000000
+#define SPEAR300_KEYBOARD_BASE          UL(0xA0000000)
-#define SPEAR300_GPIO_BASE              0xA9000000
+#define SPEAR300_GPIO_BASE              UL(0xA9000000)
 #endif /* __MACH_SPEAR300_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 4f58eb12cc58..1e853479b8cd 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,17 +16,17 @@
 #ifndef __MACH_SPEAR310_H
 #define __MACH_SPEAR310_H
-#define SPEAR310_NAND_BASE              0x40000000
+#define SPEAR310_NAND_BASE              UL(0x40000000)
-#define SPEAR310_FSMC_BASE              0x44000000
+#define SPEAR310_FSMC_BASE              UL(0x44000000)
-#define SPEAR310_UART1_BASE             0xB2000000
+#define SPEAR310_UART1_BASE             UL(0xB2000000)
-#define SPEAR310_UART2_BASE             0xB2080000
+#define SPEAR310_UART2_BASE             UL(0xB2080000)
-#define SPEAR310_UART3_BASE             0xB2100000
+#define SPEAR310_UART3_BASE             UL(0xB2100000)
-#define SPEAR310_UART4_BASE             0xB2180000
+#define SPEAR310_UART4_BASE             UL(0xB2180000)
-#define SPEAR310_UART5_BASE             0xB2200000
+#define SPEAR310_UART5_BASE             UL(0xB2200000)
-#define SPEAR310_HDLC_BASE              0xB2800000
+#define SPEAR310_HDLC_BASE              UL(0xB2800000)
-#define SPEAR310_RS485_0_BASE           0xB3000000
+#define SPEAR310_RS485_0_BASE           UL(0xB3000000)
-#define SPEAR310_RS485_1_BASE           0xB3800000
+#define SPEAR310_RS485_1_BASE           UL(0xB3800000)
-#define SPEAR310_SOC_CONFIG_BASE        0xB4000000
+#define SPEAR310_SOC_CONFIG_BASE        UL(0xB4000000)
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 95bdb2ea312a..940f0d85d959 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,23 +16,24 @@
 #ifndef __MACH_SPEAR320_H
 #define __MACH_SPEAR320_H
-#define SPEAR320_EMI_CTRL_BASE          0x40000000
+#define SPEAR320_EMI_CTRL_BASE          UL(0x40000000)
-#define SPEAR320_FSMC_BASE              0x4C000000
+#define SPEAR320_FSMC_BASE              UL(0x4C000000)
-#define SPEAR320_I2S_BASE               0x60000000
+#define SPEAR320_NAND_BASE              UL(0x50000000)
-#define SPEAR320_SDHCI_BASE             0x70000000
+#define SPEAR320_I2S_BASE               UL(0x60000000)
-#define SPEAR320_CLCD_BASE              0x90000000
+#define SPEAR320_SDHCI_BASE             UL(0x70000000)
-#define SPEAR320_PAR_PORT_BASE          0xA0000000
+#define SPEAR320_CLCD_BASE              UL(0x90000000)
-#define SPEAR320_CAN0_BASE              0xA1000000
+#define SPEAR320_PAR_PORT_BASE          UL(0xA0000000)
-#define SPEAR320_CAN1_BASE              0xA2000000
+#define SPEAR320_CAN0_BASE              UL(0xA1000000)
-#define SPEAR320_UART1_BASE             0xA3000000
+#define SPEAR320_CAN1_BASE              UL(0xA2000000)
-#define SPEAR320_UART2_BASE             0xA4000000
+#define SPEAR320_UART1_BASE             UL(0xA3000000)
-#define SPEAR320_SSP0_BASE              0xA5000000
+#define SPEAR320_UART2_BASE             UL(0xA4000000)
-#define SPEAR320_SSP1_BASE              0xA6000000
+#define SPEAR320_SSP0_BASE              UL(0xA5000000)
-#define SPEAR320_I2C_BASE               0xA7000000
+#define SPEAR320_SSP1_BASE              UL(0xA6000000)
-#define SPEAR320_PWM_BASE               0xA8000000
+#define SPEAR320_I2C_BASE               UL(0xA7000000)
-#define SPEAR320_SMII0_BASE             0xAA000000
+#define SPEAR320_PWM_BASE               UL(0xA8000000)
-#define SPEAR320_SMII1_BASE             0xAB000000
+#define SPEAR320_SMII0_BASE             UL(0xAA000000)
-#define SPEAR320_SOC_CONFIG_BASE        0xB3000000
+#define SPEAR320_SMII1_BASE             UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE        UL(0xB3000000)
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index c9bba39dddce..7fd621532def 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,69 +14,70 @@
 #ifndef __MACH_SPEAR6XX_H
 #define __MACH_SPEAR6XX_H
+#include <asm/memory.h>
 #include <mach/spear600.h>
-#define SPEAR6XX_ML_SDRAM_BASE          0x00000000
+#define SPEAR6XX_ML_SDRAM_BASE          UL(0x00000000)
 /* ICM1 - Low speed connection */
-#define SPEAR6XX_ICM1_BASE              0xD0000000
+#define SPEAR6XX_ICM1_BASE              UL(0xD0000000)
-#define SPEAR6XX_ICM1_UART0_BASE        0xD0000000
+#define SPEAR6XX_ICM1_UART0_BASE        UL(0xD0000000)
 #define VA_SPEAR6XX_ICM1_UART0_BASE     IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-#define SPEAR6XX_ICM1_UART1_BASE        0xD0080000
+#define SPEAR6XX_ICM1_UART1_BASE        UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE         0xD0100000
+#define SPEAR6XX_ICM1_SSP0_BASE         UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE         0xD0180000
+#define SPEAR6XX_ICM1_SSP1_BASE         UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE          0xD0200000
+#define SPEAR6XX_ICM1_I2C_BASE          UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE         0xD0800000
+#define SPEAR6XX_ICM1_JPEG_BASE         UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE         0xD1000000
+#define SPEAR6XX_ICM1_IRDA_BASE         UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE         0xD1800000
+#define SPEAR6XX_ICM1_FSMC_BASE         UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE         0xD2000000
+#define SPEAR6XX_ICM1_NAND_BASE         UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE         0xD2800000
+#define SPEAR6XX_ICM1_SRAM_BASE         UL(0xD2800000)
 /* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE              0xD8000000
+#define SPEAR6XX_ICM2_BASE              UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE         0xD8000000
+#define SPEAR6XX_ICM2_TMR0_BASE         UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE         0xD8080000
+#define SPEAR6XX_ICM2_TMR1_BASE         UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE         0xD8100000
+#define SPEAR6XX_ICM2_GPIO_BASE         UL(0xD8100000)
-#define SPEAR6XX_ICM2_SPI2_BASE         0xD8180000
+#define SPEAR6XX_ICM2_SSP2_BASE         UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE          0xD8200000
+#define SPEAR6XX_ICM2_ADC_BASE          UL(0xD8200000)
 /* ML-1, 2 - Multi Layer CPU Subsystem */
-#define SPEAR6XX_ML_CPU_BASE            0xF0000000
+#define SPEAR6XX_ML_CPU_BASE            UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE           0xF0000000
+#define SPEAR6XX_CPU_TMR_BASE           UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE          0xF0100000
+#define SPEAR6XX_CPU_GPIO_BASE          UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE       0xF1000000
+#define SPEAR6XX_CPU_VIC_SEC_BASE       UL(0xF1000000)
 #define VA_SPEAR6XX_CPU_VIC_SEC_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE       0xF1100000
+#define SPEAR6XX_CPU_VIC_PRI_BASE       UL(0xF1100000)
 #define VA_SPEAR6XX_CPU_VIC_PRI_BASE    IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE              0xF8000000
+#define SPEAR6XX_ICM3_BASE              UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE         0xF8000000
+#define SPEAR6XX_ICM3_SMEM_BASE         UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMI_CTRL_BASE     0xFC000000
+#define SPEAR6XX_ICM3_SMI_CTRL_BASE     UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE         0xFC200000
+#define SPEAR6XX_ICM3_CLCD_BASE         UL(0xFC200000)
-#define SPEAR6XX_ICM3_DMA_BASE          0xFC400000
+#define SPEAR6XX_ICM3_DMA_BASE          UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   0xFC600000
+#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE   UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE          0xFC800000
+#define SPEAR6XX_ICM3_TMR_BASE          UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE          0xFC880000
+#define SPEAR6XX_ICM3_WDT_BASE          UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE          0xFC900000
+#define SPEAR6XX_ICM3_RTC_BASE          UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE         0xFC980000
+#define SPEAR6XX_ICM3_GPIO_BASE         UL(0xFC980000)
-#define SPEAR6XX_ICM3_SYS_CTRL_BASE     0xFCA00000
+#define SPEAR6XX_ICM3_SYS_CTRL_BASE     UL(0xFCA00000)
 #define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE  IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR6XX_ICM3_MISC_REG_BASE     0xFCA80000
+#define SPEAR6XX_ICM3_MISC_REG_BASE     UL(0xFCA80000)
 #define VA_SPEAR6XX_ICM3_MISC_REG_BASE  IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
 /* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE              0xE0000000
+#define SPEAR6XX_ICM4_BASE              UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE         0xE0800000
+#define SPEAR6XX_ICM4_GMAC_BASE         UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE    0xE1000000
+#define SPEAR6XX_ICM4_USBD_FIFO_BASE    UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE     0xE1100000
+#define SPEAR6XX_ICM4_USBD_CSR_BASE     UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE    0xE1200000
+#define SPEAR6XX_ICM4_USBD_PLDT_BASE    UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE    0xE1800000
+#define SPEAR6XX_ICM4_USB_EHCI0_BASE    UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE    0xE1900000
+#define SPEAR6XX_ICM4_USB_OHCI0_BASE    UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE    0xE2000000
+#define SPEAR6XX_ICM4_USB_EHCI1_BASE    UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE    0xE2100000
+#define SPEAR6XX_ICM4_USB_OHCI1_BASE    UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE      0xE2800000
+#define SPEAR6XX_ICM4_USB_ARB_BASE      UL(0xE2800000)
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE             SPEAR6XX_ICM1_UART0_BASE
author	Shiraz Hashim <shiraz.hashim@st.com>	2011-03-06 23:57:08 -0500
committer	Russell King <rmk+kernel@arm.linux.org.uk>	2011-03-09 04:50:04 -0500
commit	981a95d37126cdf09e1dba3884305c2e25375bfb (patch)
tree	280cad24a89b16dd91b392b50a6f7c141183c243
parent	8fc4ef451eebc72d10c6987b59ec3316da62f02b (diff)

diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index df60e3004aa5..63fd98356919 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -14,60 +14,61 @@
14	#ifndef __MACH_SPEAR3XX_H	14	#ifndef __MACH_SPEAR3XX_H
15	#define __MACH_SPEAR3XX_H	15	#define __MACH_SPEAR3XX_H
16		16
		17	#include <asm/memory.h>
17	#include <mach/spear300.h>	18	#include <mach/spear300.h>
18	#include <mach/spear310.h>	19	#include <mach/spear310.h>
19	#include <mach/spear320.h>	20	#include <mach/spear320.h>
20		21
21	#define SPEAR3XX_ML_SDRAM_BASE 0x00000000	22	#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
22		23
23	#define SPEAR3XX_ICM9_BASE 0xC0000000	24	#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
24		25
25	/* ICM1 - Low speed connection */	26	/* ICM1 - Low speed connection */
26	#define SPEAR3XX_ICM1_2_BASE 0xD0000000	27	#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
27	#define SPEAR3XX_ICM1_UART_BASE 0xD0000000	28	#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
28	#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)	29	#define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
29	#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000	30	#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
30	#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000	31	#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
31	#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000	32	#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
32	#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000	33	#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
33	#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000	34	#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
34	#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000	35	#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
35		36
36	/* ICM2 - Application Subsystem */	37	/* ICM2 - Application Subsystem */
37	#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000	38	#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
38	#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000	39	#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
39		40
40	/* ICM4 - High Speed Connection */	41	/* ICM4 - High Speed Connection */
41	#define SPEAR3XX_ICM4_BASE 0xE0000000	42	#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
42	#define SPEAR3XX_ICM4_MII_BASE 0xE0800000	43	#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
43	#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000	44	#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
44	#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000	45	#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
45	#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000	46	#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
46	#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000	47	#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
47	#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000	48	#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
48	#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000	49	#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
49	#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000	50	#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
50		51
51	/* ML1 - Multi Layer CPU Subsystem */	52	/* ML1 - Multi Layer CPU Subsystem */
52	#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000	53	#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
53	#define SPEAR3XX_ML1_TMR_BASE 0xF0000000	54	#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000)
54	#define SPEAR3XX_ML1_VIC_BASE 0xF1100000	55	#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000)
55	#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)	56	#define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
56		57
57	/* ICM3 - Basic Subsystem */	58	/* ICM3 - Basic Subsystem */
58	#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000	59	#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
59	#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000	60	#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
60	#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000	61	#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
61	#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000	62	#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
62	#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000	63	#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
63	#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000	64	#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
64	#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000	65	#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
65	#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000	66	#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
66	#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000	67	#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
67	#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)	68	#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
68	#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000	69	#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
69	#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)	70	#define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
70	#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000	71	#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
71		72
72	/* Debug uart for linux, will be used for debug and uncompress messages */	73	/* Debug uart for linux, will be used for debug and uncompress messages */
73	#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE	74	#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE


diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index 8f96cc569591..c723515f8853 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -17,7 +17,7 @@
17	#define __MACH_SPEAR300_H	17	#define __MACH_SPEAR300_H
18		18
19	/* Base address of various IPs */	19	/* Base address of various IPs */
20	#define SPEAR300_TELECOM_BASE 0x50000000	20	#define SPEAR300_TELECOM_BASE UL(0x50000000)
21		21
22	/* Interrupt registers offsets and masks */	22	/* Interrupt registers offsets and masks */
23	#define INT_ENB_MASK_REG 0x54	23	#define INT_ENB_MASK_REG 0x54
@@ -34,20 +34,20 @@
34		34
35	#define SHIRQ_RAS1_MASK 0x1FF	35	#define SHIRQ_RAS1_MASK 0x1FF
36		36
37	#define SPEAR300_CLCD_BASE 0x60000000	37	#define SPEAR300_CLCD_BASE UL(0x60000000)
38	#define SPEAR300_SDHCI_BASE 0x70000000	38	#define SPEAR300_SDHCI_BASE UL(0x70000000)
39	#define SPEAR300_NAND_0_BASE 0x80000000	39	#define SPEAR300_NAND_0_BASE UL(0x80000000)
40	#define SPEAR300_NAND_1_BASE 0x84000000	40	#define SPEAR300_NAND_1_BASE UL(0x84000000)
41	#define SPEAR300_NAND_2_BASE 0x88000000	41	#define SPEAR300_NAND_2_BASE UL(0x88000000)
42	#define SPEAR300_NAND_3_BASE 0x8c000000	42	#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43	#define SPEAR300_NOR_0_BASE 0x90000000	43	#define SPEAR300_NOR_0_BASE UL(0x90000000)
44	#define SPEAR300_NOR_1_BASE 0x91000000	44	#define SPEAR300_NOR_1_BASE UL(0x91000000)
45	#define SPEAR300_NOR_2_BASE 0x92000000	45	#define SPEAR300_NOR_2_BASE UL(0x92000000)
46	#define SPEAR300_NOR_3_BASE 0x93000000	46	#define SPEAR300_NOR_3_BASE UL(0x93000000)
47	#define SPEAR300_FSMC_BASE 0x94000000	47	#define SPEAR300_FSMC_BASE UL(0x94000000)
48	#define SPEAR300_SOC_CONFIG_BASE 0x99000000	48	#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49	#define SPEAR300_KEYBOARD_BASE 0xA0000000	49	#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50	#define SPEAR300_GPIO_BASE 0xA9000000	50	#define SPEAR300_GPIO_BASE UL(0xA9000000)
51		51
52	#endif /* __MACH_SPEAR300_H */	52	#endif /* __MACH_SPEAR300_H */
53		53


diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 4f58eb12cc58..1e853479b8cd 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -16,17 +16,17 @@
16	#ifndef __MACH_SPEAR310_H	16	#ifndef __MACH_SPEAR310_H
17	#define __MACH_SPEAR310_H	17	#define __MACH_SPEAR310_H
18		18
19	#define SPEAR310_NAND_BASE 0x40000000	19	#define SPEAR310_NAND_BASE UL(0x40000000)
20	#define SPEAR310_FSMC_BASE 0x44000000	20	#define SPEAR310_FSMC_BASE UL(0x44000000)
21	#define SPEAR310_UART1_BASE 0xB2000000	21	#define SPEAR310_UART1_BASE UL(0xB2000000)
22	#define SPEAR310_UART2_BASE 0xB2080000	22	#define SPEAR310_UART2_BASE UL(0xB2080000)
23	#define SPEAR310_UART3_BASE 0xB2100000	23	#define SPEAR310_UART3_BASE UL(0xB2100000)
24	#define SPEAR310_UART4_BASE 0xB2180000	24	#define SPEAR310_UART4_BASE UL(0xB2180000)
25	#define SPEAR310_UART5_BASE 0xB2200000	25	#define SPEAR310_UART5_BASE UL(0xB2200000)
26	#define SPEAR310_HDLC_BASE 0xB2800000	26	#define SPEAR310_HDLC_BASE UL(0xB2800000)
27	#define SPEAR310_RS485_0_BASE 0xB3000000	27	#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28	#define SPEAR310_RS485_1_BASE 0xB3800000	28	#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29	#define SPEAR310_SOC_CONFIG_BASE 0xB4000000	29	#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30		30
31	/* Interrupt registers offsets and masks */	31	/* Interrupt registers offsets and masks */
32	#define INT_STS_MASK_REG 0x04	32	#define INT_STS_MASK_REG 0x04


diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 95bdb2ea312a..940f0d85d959 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -16,23 +16,24 @@
16	#ifndef __MACH_SPEAR320_H	16	#ifndef __MACH_SPEAR320_H
17	#define __MACH_SPEAR320_H	17	#define __MACH_SPEAR320_H
18		18
19	#define SPEAR320_EMI_CTRL_BASE 0x40000000	19	#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20	#define SPEAR320_FSMC_BASE 0x4C000000	20	#define SPEAR320_FSMC_BASE UL(0x4C000000)
21	#define SPEAR320_I2S_BASE 0x60000000	21	#define SPEAR320_NAND_BASE UL(0x50000000)
22	#define SPEAR320_SDHCI_BASE 0x70000000	22	#define SPEAR320_I2S_BASE UL(0x60000000)
23	#define SPEAR320_CLCD_BASE 0x90000000	23	#define SPEAR320_SDHCI_BASE UL(0x70000000)
24	#define SPEAR320_PAR_PORT_BASE 0xA0000000	24	#define SPEAR320_CLCD_BASE UL(0x90000000)
25	#define SPEAR320_CAN0_BASE 0xA1000000	25	#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26	#define SPEAR320_CAN1_BASE 0xA2000000	26	#define SPEAR320_CAN0_BASE UL(0xA1000000)
27	#define SPEAR320_UART1_BASE 0xA3000000	27	#define SPEAR320_CAN1_BASE UL(0xA2000000)
28	#define SPEAR320_UART2_BASE 0xA4000000	28	#define SPEAR320_UART1_BASE UL(0xA3000000)
29	#define SPEAR320_SSP0_BASE 0xA5000000	29	#define SPEAR320_UART2_BASE UL(0xA4000000)
30	#define SPEAR320_SSP1_BASE 0xA6000000	30	#define SPEAR320_SSP0_BASE UL(0xA5000000)
31	#define SPEAR320_I2C_BASE 0xA7000000	31	#define SPEAR320_SSP1_BASE UL(0xA6000000)
32	#define SPEAR320_PWM_BASE 0xA8000000	32	#define SPEAR320_I2C_BASE UL(0xA7000000)
33	#define SPEAR320_SMII0_BASE 0xAA000000	33	#define SPEAR320_PWM_BASE UL(0xA8000000)
34	#define SPEAR320_SMII1_BASE 0xAB000000	34	#define SPEAR320_SMII0_BASE UL(0xAA000000)
35	#define SPEAR320_SOC_CONFIG_BASE 0xB3000000	35	#define SPEAR320_SMII1_BASE UL(0xAB000000)
		36	#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
36		37
37	/* Interrupt registers offsets and masks */	38	/* Interrupt registers offsets and masks */
38	#define INT_STS_MASK_REG 0x04	39	#define INT_STS_MASK_REG 0x04


diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h index c9bba39dddce..7fd621532def 100644 --- a/arch/arm/mach-spear6xx/include/mach/spear.h +++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -14,69 +14,70 @@
14	#ifndef __MACH_SPEAR6XX_H	14	#ifndef __MACH_SPEAR6XX_H
15	#define __MACH_SPEAR6XX_H	15	#define __MACH_SPEAR6XX_H
16		16
		17	#include <asm/memory.h>
17	#include <mach/spear600.h>	18	#include <mach/spear600.h>
18		19
19	#define SPEAR6XX_ML_SDRAM_BASE 0x00000000	20	#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
20	/* ICM1 - Low speed connection */	21	/* ICM1 - Low speed connection */
21	#define SPEAR6XX_ICM1_BASE 0xD0000000	22	#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
22		23
23	#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000	24	#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
24	#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)	25	#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
25		26
26	#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000	27	#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
27	#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000	28	#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
28	#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000	29	#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
29	#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000	30	#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
30	#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000	31	#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
31	#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000	32	#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
32	#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000	33	#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
33	#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000	34	#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
34	#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000	35	#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
35		36
36	/* ICM2 - Application Subsystem */	37	/* ICM2 - Application Subsystem */
37	#define SPEAR6XX_ICM2_BASE 0xD8000000	38	#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
38	#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000	39	#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
39	#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000	40	#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
40	#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000	41	#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
41	#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000	42	#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
42	#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000	43	#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
43		44
44	/* ML-1, 2 - Multi Layer CPU Subsystem */	45	/* ML-1, 2 - Multi Layer CPU Subsystem */
45	#define SPEAR6XX_ML_CPU_BASE 0xF0000000	46	#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
46	#define SPEAR6XX_CPU_TMR_BASE 0xF0000000	47	#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
47	#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000	48	#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
48	#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000	49	#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
49	#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)	50	#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
50	#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000	51	#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
51	#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)	52	#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
52		53
53	/* ICM3 - Basic Subsystem */	54	/* ICM3 - Basic Subsystem */
54	#define SPEAR6XX_ICM3_BASE 0xF8000000	55	#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
55	#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000	56	#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
56	#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000	57	#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
57	#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000	58	#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000)
58	#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000	59	#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
59	#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000	60	#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
60	#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000	61	#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
61	#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000	62	#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
62	#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000	63	#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
63	#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000	64	#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
64	#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000	65	#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
65	#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)	66	#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
66	#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000	67	#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
67	#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)	68	#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
68		69
69	/* ICM4 - High Speed Connection */	70	/* ICM4 - High Speed Connection */
70	#define SPEAR6XX_ICM4_BASE 0xE0000000	71	#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
71	#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000	72	#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
72	#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000	73	#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
73	#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000	74	#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
74	#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000	75	#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
75	#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000	76	#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
76	#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000	77	#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
77	#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000	78	#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
78	#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000	79	#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
79	#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000	80	#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
80		81
81	/* Debug uart for linux, will be used for debug and uncompress messages */	82	/* Debug uart for linux, will be used for debug and uncompress messages */
82	#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE	83	#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE