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authorandrew.vasquez@qlogic.com <andrew.vasquez@qlogic.com>2006-01-31 19:05:17 -0500
committer <jejb@mulgrave.il.steeleye.com>2006-02-04 17:12:41 -0500
commit854165f4245c4a3b4a8cc363ba2050033151e196 (patch)
tree0f2a19b829eaca15d3d406cfae6b77660858c7ff
parent1b3f63659bd353ae460c35f5793a9fd46cc95014 (diff)
[SCSI] qla2xxx: Add support to retrieve/update HBA option-rom.
Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat
-rw-r--r--drivers/scsi/qla2xxx/qla_attr.c135
-rw-r--r--drivers/scsi/qla2xxx/qla_def.h17
-rw-r--r--drivers/scsi/qla2xxx/qla_gbl.h11
-rw-r--r--drivers/scsi/qla2xxx/qla_os.c15
-rw-r--r--drivers/scsi/qla2xxx/qla_sup.c669
5 files changed, 845 insertions, 2 deletions
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c
index 73d10b35091e..92b3e13e9061 100644
--- a/drivers/scsi/qla2xxx/qla_attr.c
+++ b/drivers/scsi/qla2xxx/qla_attr.c
@@ -179,6 +179,135 @@ static struct bin_attribute sysfs_nvram_attr = {
179 .write = qla2x00_sysfs_write_nvram, 179 .write = qla2x00_sysfs_write_nvram,
180}; 180};
181 181
182static ssize_t
183qla2x00_sysfs_read_optrom(struct kobject *kobj, char *buf, loff_t off,
184 size_t count)
185{
186 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
187 struct device, kobj)));
188
189 if (ha->optrom_state != QLA_SREADING)
190 return 0;
191 if (off > ha->optrom_size)
192 return 0;
193 if (off + count > ha->optrom_size)
194 count = ha->optrom_size - off;
195
196 memcpy(buf, &ha->optrom_buffer[off], count);
197
198 return count;
199}
200
201static ssize_t
202qla2x00_sysfs_write_optrom(struct kobject *kobj, char *buf, loff_t off,
203 size_t count)
204{
205 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
206 struct device, kobj)));
207
208 if (ha->optrom_state != QLA_SWRITING)
209 return -EINVAL;
210 if (off > ha->optrom_size)
211 return -ERANGE;
212 if (off + count > ha->optrom_size)
213 count = ha->optrom_size - off;
214
215 memcpy(&ha->optrom_buffer[off], buf, count);
216
217 return count;
218}
219
220static struct bin_attribute sysfs_optrom_attr = {
221 .attr = {
222 .name = "optrom",
223 .mode = S_IRUSR | S_IWUSR,
224 .owner = THIS_MODULE,
225 },
226 .size = OPTROM_SIZE_24XX,
227 .read = qla2x00_sysfs_read_optrom,
228 .write = qla2x00_sysfs_write_optrom,
229};
230
231static ssize_t
232qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, char *buf, loff_t off,
233 size_t count)
234{
235 struct scsi_qla_host *ha = to_qla_host(dev_to_shost(container_of(kobj,
236 struct device, kobj)));
237 int val;
238
239 if (off)
240 return 0;
241
242 if (sscanf(buf, "%d", &val) != 1)
243 return -EINVAL;
244
245 switch (val) {
246 case 0:
247 if (ha->optrom_state != QLA_SREADING &&
248 ha->optrom_state != QLA_SWRITING)
249 break;
250
251 ha->optrom_state = QLA_SWAITING;
252 vfree(ha->optrom_buffer);
253 ha->optrom_buffer = NULL;
254 break;
255 case 1:
256 if (ha->optrom_state != QLA_SWAITING)
257 break;
258
259 ha->optrom_state = QLA_SREADING;
260 ha->optrom_buffer = (uint8_t *)vmalloc(ha->optrom_size);
261 if (ha->optrom_buffer == NULL) {
262 qla_printk(KERN_WARNING, ha,
263 "Unable to allocate memory for optrom retrieval "
264 "(%x).\n", ha->optrom_size);
265
266 ha->optrom_state = QLA_SWAITING;
267 return count;
268 }
269
270 memset(ha->optrom_buffer, 0, ha->optrom_size);
271 ha->isp_ops.read_optrom(ha, ha->optrom_buffer, 0,
272 ha->optrom_size);
273 break;
274 case 2:
275 if (ha->optrom_state != QLA_SWAITING)
276 break;
277
278 ha->optrom_state = QLA_SWRITING;
279 ha->optrom_buffer = (uint8_t *)vmalloc(ha->optrom_size);
280 if (ha->optrom_buffer == NULL) {
281 qla_printk(KERN_WARNING, ha,
282 "Unable to allocate memory for optrom update "
283 "(%x).\n", ha->optrom_size);
284
285 ha->optrom_state = QLA_SWAITING;
286 return count;
287 }
288 memset(ha->optrom_buffer, 0, ha->optrom_size);
289 break;
290 case 3:
291 if (ha->optrom_state != QLA_SWRITING)
292 break;
293
294 ha->isp_ops.write_optrom(ha, ha->optrom_buffer, 0,
295 ha->optrom_size);
296 break;
297 }
298 return count;
299}
300
301static struct bin_attribute sysfs_optrom_ctl_attr = {
302 .attr = {
303 .name = "optrom_ctl",
304 .mode = S_IWUSR,
305 .owner = THIS_MODULE,
306 },
307 .size = 0,
308 .write = qla2x00_sysfs_write_optrom_ctl,
309};
310
182void 311void
183qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha) 312qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha)
184{ 313{
@@ -186,6 +315,9 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *ha)
186 315
187 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_fw_dump_attr); 316 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_fw_dump_attr);
188 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_nvram_attr); 317 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_nvram_attr);
318 sysfs_create_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr);
319 sysfs_create_bin_file(&host->shost_gendev.kobj,
320 &sysfs_optrom_ctl_attr);
189} 321}
190 322
191void 323void
@@ -195,6 +327,9 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *ha)
195 327
196 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_fw_dump_attr); 328 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_fw_dump_attr);
197 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_nvram_attr); 329 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_nvram_attr);
330 sysfs_remove_bin_file(&host->shost_gendev.kobj, &sysfs_optrom_attr);
331 sysfs_remove_bin_file(&host->shost_gendev.kobj,
332 &sysfs_optrom_ctl_attr);
198 333
199 if (ha->beacon_blink_led == 1) 334 if (ha->beacon_blink_led == 1)
200 ha->isp_ops.beacon_off(ha); 335 ha->isp_ops.beacon_off(ha);
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h
index 7cb8b5a5e659..b31a03bbd14f 100644
--- a/drivers/scsi/qla2xxx/qla_def.h
+++ b/drivers/scsi/qla2xxx/qla_def.h
@@ -2214,6 +2214,11 @@ struct isp_operations {
2214 int (*beacon_on) (struct scsi_qla_host *); 2214 int (*beacon_on) (struct scsi_qla_host *);
2215 int (*beacon_off) (struct scsi_qla_host *); 2215 int (*beacon_off) (struct scsi_qla_host *);
2216 void (*beacon_blink) (struct scsi_qla_host *); 2216 void (*beacon_blink) (struct scsi_qla_host *);
2217
2218 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2219 uint32_t, uint32_t);
2220 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2221 uint32_t);
2217}; 2222};
2218 2223
2219/* 2224/*
@@ -2505,6 +2510,14 @@ typedef struct scsi_qla_host {
2505 uint8_t *port_name; 2510 uint8_t *port_name;
2506 uint32_t isp_abort_cnt; 2511 uint32_t isp_abort_cnt;
2507 2512
2513 /* Option ROM information. */
2514 char *optrom_buffer;
2515 uint32_t optrom_size;
2516 int optrom_state;
2517#define QLA_SWAITING 0
2518#define QLA_SREADING 1
2519#define QLA_SWRITING 2
2520
2508 /* Needed for BEACON */ 2521 /* Needed for BEACON */
2509 uint16_t beacon_blink_led; 2522 uint16_t beacon_blink_led;
2510 uint8_t beacon_color_state; 2523 uint8_t beacon_color_state;
@@ -2582,7 +2595,9 @@ struct _qla2x00stats {
2582/* 2595/*
2583 * Flash support definitions 2596 * Flash support definitions
2584 */ 2597 */
2585#define FLASH_IMAGE_SIZE 131072 2598#define OPTROM_SIZE_2300 0x20000
2599#define OPTROM_SIZE_2322 0x100000
2600#define OPTROM_SIZE_24XX 0x100000
2586 2601
2587#include "qla_gbl.h" 2602#include "qla_gbl.h"
2588#include "qla_dbg.h" 2603#include "qla_dbg.h"
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h
index eb35198bc8cf..ffdc2680f049 100644
--- a/drivers/scsi/qla2xxx/qla_gbl.h
+++ b/drivers/scsi/qla2xxx/qla_gbl.h
@@ -79,6 +79,8 @@ extern int qla2x00_down_timeout(struct semaphore *, unsigned long);
79 79
80extern struct fw_blob *qla2x00_request_firmware(scsi_qla_host_t *); 80extern struct fw_blob *qla2x00_request_firmware(scsi_qla_host_t *);
81 81
82extern int qla2x00_wait_for_hba_online(scsi_qla_host_t *);
83
82/* 84/*
83 * Global Function Prototypes in qla_iocb.c source file. 85 * Global Function Prototypes in qla_iocb.c source file.
84 */ 86 */
@@ -240,6 +242,15 @@ extern int qla24xx_beacon_on(struct scsi_qla_host *);
240extern int qla24xx_beacon_off(struct scsi_qla_host *); 242extern int qla24xx_beacon_off(struct scsi_qla_host *);
241extern void qla24xx_beacon_blink(struct scsi_qla_host *); 243extern void qla24xx_beacon_blink(struct scsi_qla_host *);
242 244
245extern uint8_t *qla2x00_read_optrom_data(struct scsi_qla_host *, uint8_t *,
246 uint32_t, uint32_t);
247extern int qla2x00_write_optrom_data(struct scsi_qla_host *, uint8_t *,
248 uint32_t, uint32_t);
249extern uint8_t *qla24xx_read_optrom_data(struct scsi_qla_host *, uint8_t *,
250 uint32_t, uint32_t);
251extern int qla24xx_write_optrom_data(struct scsi_qla_host *, uint8_t *,
252 uint32_t, uint32_t);
253
243/* 254/*
244 * Global Function Prototypes in qla_dbg.c source file. 255 * Global Function Prototypes in qla_dbg.c source file.
245 */ 256 */
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c
index 57179dabcccf..495ccbc7f8cb 100644
--- a/drivers/scsi/qla2xxx/qla_os.c
+++ b/drivers/scsi/qla2xxx/qla_os.c
@@ -513,7 +513,7 @@ qla2x00_eh_wait_on_command(scsi_qla_host_t *ha, struct scsi_cmnd *cmd)
513 * Success (Adapter is online) : 0 513 * Success (Adapter is online) : 0
514 * Failed (Adapter is offline/disabled) : 1 514 * Failed (Adapter is offline/disabled) : 1
515 */ 515 */
516static int 516int
517qla2x00_wait_for_hba_online(scsi_qla_host_t *ha) 517qla2x00_wait_for_hba_online(scsi_qla_host_t *ha)
518{ 518{
519 int return_status; 519 int return_status;
@@ -1271,6 +1271,9 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1271 fc_port_t *fcport; 1271 fc_port_t *fcport;
1272 struct scsi_host_template *sht; 1272 struct scsi_host_template *sht;
1273 1273
1274if (PCI_FUNC(pdev->devfn))
1275 goto probe_out;
1276
1274 if (pci_enable_device(pdev)) 1277 if (pci_enable_device(pdev))
1275 goto probe_out; 1278 goto probe_out;
1276 1279
@@ -1313,6 +1316,7 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1313 ha->init_cb_size = sizeof(init_cb_t); 1316 ha->init_cb_size = sizeof(init_cb_t);
1314 ha->mgmt_svr_loop_id = MANAGEMENT_SERVER; 1317 ha->mgmt_svr_loop_id = MANAGEMENT_SERVER;
1315 ha->link_data_rate = LDR_UNKNOWN; 1318 ha->link_data_rate = LDR_UNKNOWN;
1319 ha->optrom_size = OPTROM_SIZE_2300;
1316 1320
1317 /* Assign ISP specific operations. */ 1321 /* Assign ISP specific operations. */
1318 ha->isp_ops.pci_config = qla2100_pci_config; 1322 ha->isp_ops.pci_config = qla2100_pci_config;
@@ -1340,6 +1344,8 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1340 ha->isp_ops.write_nvram = qla2x00_write_nvram_data; 1344 ha->isp_ops.write_nvram = qla2x00_write_nvram_data;
1341 ha->isp_ops.fw_dump = qla2100_fw_dump; 1345 ha->isp_ops.fw_dump = qla2100_fw_dump;
1342 ha->isp_ops.ascii_fw_dump = qla2100_ascii_fw_dump; 1346 ha->isp_ops.ascii_fw_dump = qla2100_ascii_fw_dump;
1347 ha->isp_ops.read_optrom = qla2x00_read_optrom_data;
1348 ha->isp_ops.write_optrom = qla2x00_write_optrom_data;
1343 if (IS_QLA2100(ha)) { 1349 if (IS_QLA2100(ha)) {
1344 host->max_id = MAX_TARGETS_2100; 1350 host->max_id = MAX_TARGETS_2100;
1345 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 1351 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
@@ -1369,6 +1375,8 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1369 ha->isp_ops.beacon_off = qla2x00_beacon_off; 1375 ha->isp_ops.beacon_off = qla2x00_beacon_off;
1370 ha->isp_ops.beacon_blink = qla2x00_beacon_blink; 1376 ha->isp_ops.beacon_blink = qla2x00_beacon_blink;
1371 ha->gid_list_info_size = 6; 1377 ha->gid_list_info_size = 6;
1378 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1379 ha->optrom_size = OPTROM_SIZE_2322;
1372 } else if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) { 1380 } else if (IS_QLA24XX(ha) || IS_QLA25XX(ha)) {
1373 host->max_id = MAX_TARGETS_2200; 1381 host->max_id = MAX_TARGETS_2200;
1374 ha->mbx_count = MAILBOX_REGISTER_COUNT; 1382 ha->mbx_count = MAILBOX_REGISTER_COUNT;
@@ -1404,10 +1412,13 @@ int qla2x00_probe_one(struct pci_dev *pdev, struct qla_board_info *brd_info)
1404 ha->isp_ops.write_nvram = qla24xx_write_nvram_data; 1412 ha->isp_ops.write_nvram = qla24xx_write_nvram_data;
1405 ha->isp_ops.fw_dump = qla24xx_fw_dump; 1413 ha->isp_ops.fw_dump = qla24xx_fw_dump;
1406 ha->isp_ops.ascii_fw_dump = qla24xx_ascii_fw_dump; 1414 ha->isp_ops.ascii_fw_dump = qla24xx_ascii_fw_dump;
1415 ha->isp_ops.read_optrom = qla24xx_read_optrom_data;
1416 ha->isp_ops.write_optrom = qla24xx_write_optrom_data;
1407 ha->isp_ops.beacon_on = qla24xx_beacon_on; 1417 ha->isp_ops.beacon_on = qla24xx_beacon_on;
1408 ha->isp_ops.beacon_off = qla24xx_beacon_off; 1418 ha->isp_ops.beacon_off = qla24xx_beacon_off;
1409 ha->isp_ops.beacon_blink = qla24xx_beacon_blink; 1419 ha->isp_ops.beacon_blink = qla24xx_beacon_blink;
1410 ha->gid_list_info_size = 8; 1420 ha->gid_list_info_size = 8;
1421 ha->optrom_size = OPTROM_SIZE_24XX;
1411 } 1422 }
1412 host->can_queue = ha->request_q_length + 128; 1423 host->can_queue = ha->request_q_length + 128;
1413 1424
@@ -2073,6 +2084,8 @@ qla2x00_mem_free(scsi_qla_host_t *ha)
2073 ha->fw_dumped = 0; 2084 ha->fw_dumped = 0;
2074 ha->fw_dump_reading = 0; 2085 ha->fw_dump_reading = 0;
2075 ha->fw_dump_buffer = NULL; 2086 ha->fw_dump_buffer = NULL;
2087
2088 vfree(ha->optrom_buffer);
2076} 2089}
2077 2090
2078/* 2091/*
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c
index 3105bb93cc19..3866a5760f15 100644
--- a/drivers/scsi/qla2xxx/qla_sup.c
+++ b/drivers/scsi/qla2xxx/qla_sup.c
@@ -989,3 +989,672 @@ qla24xx_beacon_off(struct scsi_qla_host *ha)
989 989
990 return QLA_SUCCESS; 990 return QLA_SUCCESS;
991} 991}
992
993
994/*
995 * Flash support routines
996 */
997
998/**
999 * qla2x00_flash_enable() - Setup flash for reading and writing.
1000 * @ha: HA context
1001 */
1002static void
1003qla2x00_flash_enable(scsi_qla_host_t *ha)
1004{
1005 uint16_t data;
1006 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1007
1008 data = RD_REG_WORD(&reg->ctrl_status);
1009 data |= CSR_FLASH_ENABLE;
1010 WRT_REG_WORD(&reg->ctrl_status, data);
1011 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1012}
1013
1014/**
1015 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1016 * @ha: HA context
1017 */
1018static void
1019qla2x00_flash_disable(scsi_qla_host_t *ha)
1020{
1021 uint16_t data;
1022 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1023
1024 data = RD_REG_WORD(&reg->ctrl_status);
1025 data &= ~(CSR_FLASH_ENABLE);
1026 WRT_REG_WORD(&reg->ctrl_status, data);
1027 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1028}
1029
1030/**
1031 * qla2x00_read_flash_byte() - Reads a byte from flash
1032 * @ha: HA context
1033 * @addr: Address in flash to read
1034 *
1035 * A word is read from the chip, but, only the lower byte is valid.
1036 *
1037 * Returns the byte read from flash @addr.
1038 */
1039static uint8_t
1040qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1041{
1042 uint16_t data;
1043 uint16_t bank_select;
1044 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1045
1046 bank_select = RD_REG_WORD(&reg->ctrl_status);
1047
1048 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1049 /* Specify 64K address range: */
1050 /* clear out Module Select and Flash Address bits [19:16]. */
1051 bank_select &= ~0xf8;
1052 bank_select |= addr >> 12 & 0xf0;
1053 bank_select |= CSR_FLASH_64K_BANK;
1054 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1055 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1056
1057 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1058 data = RD_REG_WORD(&reg->flash_data);
1059
1060 return (uint8_t)data;
1061 }
1062
1063 /* Setup bit 16 of flash address. */
1064 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1065 bank_select |= CSR_FLASH_64K_BANK;
1066 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1067 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1068 } else if (((addr & BIT_16) == 0) &&
1069 (bank_select & CSR_FLASH_64K_BANK)) {
1070 bank_select &= ~(CSR_FLASH_64K_BANK);
1071 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1072 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1073 }
1074
1075 /* Always perform IO mapped accesses to the FLASH registers. */
1076 if (ha->pio_address) {
1077 uint16_t data2;
1078
1079 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1080 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1081 do {
1082 data = RD_REG_WORD_PIO(&reg->flash_data);
1083 barrier();
1084 cpu_relax();
1085 data2 = RD_REG_WORD_PIO(&reg->flash_data);
1086 } while (data != data2);
1087 } else {
1088 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1089 data = qla2x00_debounce_register(&reg->flash_data);
1090 }
1091
1092 return (uint8_t)data;
1093}
1094
1095/**
1096 * qla2x00_write_flash_byte() - Write a byte to flash
1097 * @ha: HA context
1098 * @addr: Address in flash to write
1099 * @data: Data to write
1100 */
1101static void
1102qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1103{
1104 uint16_t bank_select;
1105 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1106
1107 bank_select = RD_REG_WORD(&reg->ctrl_status);
1108 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1109 /* Specify 64K address range: */
1110 /* clear out Module Select and Flash Address bits [19:16]. */
1111 bank_select &= ~0xf8;
1112 bank_select |= addr >> 12 & 0xf0;
1113 bank_select |= CSR_FLASH_64K_BANK;
1114 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1115 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1116
1117 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1118 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1119 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1120 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1121
1122 return;
1123 }
1124
1125 /* Setup bit 16 of flash address. */
1126 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1127 bank_select |= CSR_FLASH_64K_BANK;
1128 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1129 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1130 } else if (((addr & BIT_16) == 0) &&
1131 (bank_select & CSR_FLASH_64K_BANK)) {
1132 bank_select &= ~(CSR_FLASH_64K_BANK);
1133 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1134 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1135 }
1136
1137 /* Always perform IO mapped accesses to the FLASH registers. */
1138 if (ha->pio_address) {
1139 reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
1140 WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
1141 WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
1142 } else {
1143 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1144 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1145 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1146 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1147 }
1148}
1149
1150/**
1151 * qla2x00_poll_flash() - Polls flash for completion.
1152 * @ha: HA context
1153 * @addr: Address in flash to poll
1154 * @poll_data: Data to be polled
1155 * @man_id: Flash manufacturer ID
1156 * @flash_id: Flash ID
1157 *
1158 * This function polls the device until bit 7 of what is read matches data
1159 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1160 * out (a fatal error). The flash book recommeds reading bit 7 again after
1161 * reading bit 5 as a 1.
1162 *
1163 * Returns 0 on success, else non-zero.
1164 */
1165static int
1166qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1167 uint8_t man_id, uint8_t flash_id)
1168{
1169 int status;
1170 uint8_t flash_data;
1171 uint32_t cnt;
1172
1173 status = 1;
1174
1175 /* Wait for 30 seconds for command to finish. */
1176 poll_data &= BIT_7;
1177 for (cnt = 3000000; cnt; cnt--) {
1178 flash_data = qla2x00_read_flash_byte(ha, addr);
1179 if ((flash_data & BIT_7) == poll_data) {
1180 status = 0;
1181 break;
1182 }
1183
1184 if (man_id != 0x40 && man_id != 0xda) {
1185 if ((flash_data & BIT_5) && cnt > 2)
1186 cnt = 2;
1187 }
1188 udelay(10);
1189 barrier();
1190 }
1191 return status;
1192}
1193
1194#define IS_OEM_001(ha) \
1195 ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322 && \
1196 (ha)->pdev->subsystem_vendor == 0x1028 && \
1197 (ha)->pdev->subsystem_device == 0x0170)
1198
1199/**
1200 * qla2x00_program_flash_address() - Programs a flash address
1201 * @ha: HA context
1202 * @addr: Address in flash to program
1203 * @data: Data to be written in flash
1204 * @man_id: Flash manufacturer ID
1205 * @flash_id: Flash ID
1206 *
1207 * Returns 0 on success, else non-zero.
1208 */
1209static int
1210qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1211 uint8_t man_id, uint8_t flash_id)
1212{
1213 /* Write Program Command Sequence. */
1214 if (IS_OEM_001(ha)) {
1215 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1216 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1217 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1218 qla2x00_write_flash_byte(ha, addr, data);
1219 } else {
1220 if (man_id == 0xda && flash_id == 0xc1) {
1221 qla2x00_write_flash_byte(ha, addr, data);
1222 if (addr & 0x7e)
1223 return 0;
1224 } else {
1225 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1226 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1227 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1228 qla2x00_write_flash_byte(ha, addr, data);
1229 }
1230 }
1231
1232 udelay(150);
1233
1234 /* Wait for write to complete. */
1235 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1236}
1237
1238/**
1239 * qla2x00_erase_flash() - Erase the flash.
1240 * @ha: HA context
1241 * @man_id: Flash manufacturer ID
1242 * @flash_id: Flash ID
1243 *
1244 * Returns 0 on success, else non-zero.
1245 */
1246static int
1247qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1248{
1249 /* Individual Sector Erase Command Sequence */
1250 if (IS_OEM_001(ha)) {
1251 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1252 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1253 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1254 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1255 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1256 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1257 } else {
1258 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1259 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1260 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1261 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1262 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1263 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1264 }
1265
1266 udelay(150);
1267
1268 /* Wait for erase to complete. */
1269 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1270}
1271
1272/**
1273 * qla2x00_erase_flash_sector() - Erase a flash sector.
1274 * @ha: HA context
1275 * @addr: Flash sector to erase
1276 * @sec_mask: Sector address mask
1277 * @man_id: Flash manufacturer ID
1278 * @flash_id: Flash ID
1279 *
1280 * Returns 0 on success, else non-zero.
1281 */
1282static int
1283qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1284 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1285{
1286 /* Individual Sector Erase Command Sequence */
1287 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1288 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1289 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1290 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1291 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1292 if (man_id == 0x1f && flash_id == 0x13)
1293 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1294 else
1295 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1296
1297 udelay(150);
1298
1299 /* Wait for erase to complete. */
1300 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1301}
1302
1303/**
1304 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1305 * @man_id: Flash manufacturer ID
1306 * @flash_id: Flash ID
1307 */
1308static void
1309qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1310 uint8_t *flash_id)
1311{
1312 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1313 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1314 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1315 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1316 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1317 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1318 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1319 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1320}
1321
1322
1323static inline void
1324qla2x00_suspend_hba(struct scsi_qla_host *ha)
1325{
1326 int cnt;
1327 unsigned long flags;
1328 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1329
1330 /* Suspend HBA. */
1331 scsi_block_requests(ha->host);
1332 ha->isp_ops.disable_intrs(ha);
1333 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1334
1335 /* Pause RISC. */
1336 spin_lock_irqsave(&ha->hardware_lock, flags);
1337 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1338 RD_REG_WORD(&reg->hccr);
1339 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1340 for (cnt = 0; cnt < 30000; cnt++) {
1341 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1342 break;
1343 udelay(100);
1344 }
1345 } else {
1346 udelay(10);
1347 }
1348 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1349}
1350
1351static inline void
1352qla2x00_resume_hba(struct scsi_qla_host *ha)
1353{
1354 /* Resume HBA. */
1355 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1356 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1357 up(ha->dpc_wait);
1358 qla2x00_wait_for_hba_online(ha);
1359 scsi_unblock_requests(ha->host);
1360}
1361
1362uint8_t *
1363qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1364 uint32_t offset, uint32_t length)
1365{
1366 unsigned long flags;
1367 uint32_t addr, midpoint;
1368 uint8_t *data;
1369 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1370
1371 /* Suspend HBA. */
1372 qla2x00_suspend_hba(ha);
1373
1374 /* Go with read. */
1375 spin_lock_irqsave(&ha->hardware_lock, flags);
1376 midpoint = ha->optrom_size / 2;
1377
1378 qla2x00_flash_enable(ha);
1379 WRT_REG_WORD(&reg->nvram, 0);
1380 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1381 for (addr = offset, data = buf; addr < length; addr++, data++) {
1382 if (addr == midpoint) {
1383 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1384 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
1385 }
1386
1387 *data = qla2x00_read_flash_byte(ha, addr);
1388 }
1389 qla2x00_flash_disable(ha);
1390 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1391
1392 /* Resume HBA. */
1393 qla2x00_resume_hba(ha);
1394
1395 return buf;
1396}
1397
1398int
1399qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1400 uint32_t offset, uint32_t length)
1401{
1402
1403 int rval;
1404 unsigned long flags;
1405 uint8_t man_id, flash_id, sec_number, data;
1406 uint16_t wd;
1407 uint32_t addr, liter, sec_mask, rest_addr;
1408 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1409
1410 /* Suspend HBA. */
1411 qla2x00_suspend_hba(ha);
1412
1413 rval = QLA_SUCCESS;
1414 sec_number = 0;
1415
1416 /* Reset ISP chip. */
1417 spin_lock_irqsave(&ha->hardware_lock, flags);
1418 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1419 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1420
1421 /* Go with write. */
1422 qla2x00_flash_enable(ha);
1423 do { /* Loop once to provide quick error exit */
1424 /* Structure of flash memory based on manufacturer */
1425 if (IS_OEM_001(ha)) {
1426 /* OEM variant with special flash part. */
1427 man_id = flash_id = 0;
1428 rest_addr = 0xffff;
1429 sec_mask = 0x10000;
1430 goto update_flash;
1431 }
1432 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1433 switch (man_id) {
1434 case 0x20: /* ST flash. */
1435 if (flash_id == 0xd2 || flash_id == 0xe3) {
1436 /*
1437 * ST m29w008at part - 64kb sector size with
1438 * 32kb,8kb,8kb,16kb sectors at memory address
1439 * 0xf0000.
1440 */
1441 rest_addr = 0xffff;
1442 sec_mask = 0x10000;
1443 break;
1444 }
1445 /*
1446 * ST m29w010b part - 16kb sector size
1447 * Default to 16kb sectors
1448 */
1449 rest_addr = 0x3fff;
1450 sec_mask = 0x1c000;
1451 break;
1452 case 0x40: /* Mostel flash. */
1453 /* Mostel v29c51001 part - 512 byte sector size. */
1454 rest_addr = 0x1ff;
1455 sec_mask = 0x1fe00;
1456 break;
1457 case 0xbf: /* SST flash. */
1458 /* SST39sf10 part - 4kb sector size. */
1459 rest_addr = 0xfff;
1460 sec_mask = 0x1f000;
1461 break;
1462 case 0xda: /* Winbond flash. */
1463 /* Winbond W29EE011 part - 256 byte sector size. */
1464 rest_addr = 0x7f;
1465 sec_mask = 0x1ff80;
1466 break;
1467 case 0xc2: /* Macronix flash. */
1468 /* 64k sector size. */
1469 if (flash_id == 0x38 || flash_id == 0x4f) {
1470 rest_addr = 0xffff;
1471 sec_mask = 0x10000;
1472 break;
1473 }
1474 /* Fall through... */
1475
1476 case 0x1f: /* Atmel flash. */
1477 /* 512k sector size. */
1478 if (flash_id == 0x13) {
1479 rest_addr = 0x7fffffff;
1480 sec_mask = 0x80000000;
1481 break;
1482 }
1483 /* Fall through... */
1484
1485 case 0x01: /* AMD flash. */
1486 if (flash_id == 0x38 || flash_id == 0x40 ||
1487 flash_id == 0x4f) {
1488 /* Am29LV081 part - 64kb sector size. */
1489 /* Am29LV002BT part - 64kb sector size. */
1490 rest_addr = 0xffff;
1491 sec_mask = 0x10000;
1492 break;
1493 } else if (flash_id == 0x3e) {
1494 /*
1495 * Am29LV008b part - 64kb sector size with
1496 * 32kb,8kb,8kb,16kb sector at memory address
1497 * h0xf0000.
1498 */
1499 rest_addr = 0xffff;
1500 sec_mask = 0x10000;
1501 break;
1502 } else if (flash_id == 0x20 || flash_id == 0x6e) {
1503 /*
1504 * Am29LV010 part or AM29f010 - 16kb sector
1505 * size.
1506 */
1507 rest_addr = 0x3fff;
1508 sec_mask = 0x1c000;
1509 break;
1510 } else if (flash_id == 0x6d) {
1511 /* Am29LV001 part - 8kb sector size. */
1512 rest_addr = 0x1fff;
1513 sec_mask = 0x1e000;
1514 break;
1515 }
1516 default:
1517 /* Default to 16 kb sector size. */
1518 rest_addr = 0x3fff;
1519 sec_mask = 0x1c000;
1520 break;
1521 }
1522
1523update_flash:
1524 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1525 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1526 rval = QLA_FUNCTION_FAILED;
1527 break;
1528 }
1529 }
1530
1531 for (addr = offset, liter = 0; liter < length; liter++,
1532 addr++) {
1533 data = buf[liter];
1534 /* Are we at the beginning of a sector? */
1535 if ((addr & rest_addr) == 0) {
1536 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1537 if (addr >= 0x10000UL) {
1538 if (((addr >> 12) & 0xf0) &&
1539 ((man_id == 0x01 &&
1540 flash_id == 0x3e) ||
1541 (man_id == 0x20 &&
1542 flash_id == 0xd2))) {
1543 sec_number++;
1544 if (sec_number == 1) {
1545 rest_addr =
1546 0x7fff;
1547 sec_mask =
1548 0x18000;
1549 } else if (
1550 sec_number == 2 ||
1551 sec_number == 3) {
1552 rest_addr =
1553 0x1fff;
1554 sec_mask =
1555 0x1e000;
1556 } else if (
1557 sec_number == 4) {
1558 rest_addr =
1559 0x3fff;
1560 sec_mask =
1561 0x1c000;
1562 }
1563 }
1564 }
1565 } else if (addr == ha->optrom_size / 2) {
1566 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1567 RD_REG_WORD(&reg->nvram);
1568 }
1569
1570 if (flash_id == 0xda && man_id == 0xc1) {
1571 qla2x00_write_flash_byte(ha, 0x5555,
1572 0xaa);
1573 qla2x00_write_flash_byte(ha, 0x2aaa,
1574 0x55);
1575 qla2x00_write_flash_byte(ha, 0x5555,
1576 0xa0);
1577 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1578 /* Then erase it */
1579 if (qla2x00_erase_flash_sector(ha,
1580 addr, sec_mask, man_id,
1581 flash_id)) {
1582 rval = QLA_FUNCTION_FAILED;
1583 break;
1584 }
1585 if (man_id == 0x01 && flash_id == 0x6d)
1586 sec_number++;
1587 }
1588 }
1589
1590 if (man_id == 0x01 && flash_id == 0x6d) {
1591 if (sec_number == 1 &&
1592 addr == (rest_addr - 1)) {
1593 rest_addr = 0x0fff;
1594 sec_mask = 0x1f000;
1595 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1596 rest_addr = 0x3fff;
1597 sec_mask = 0x1c000;
1598 }
1599 }
1600
1601 if (qla2x00_program_flash_address(ha, addr, data,
1602 man_id, flash_id)) {
1603 rval = QLA_FUNCTION_FAILED;
1604 break;
1605 }
1606 }
1607 } while (0);
1608 qla2x00_flash_disable(ha);
1609 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1610
1611 /* Resume HBA. */
1612 qla2x00_resume_hba(ha);
1613
1614 return rval;
1615}
1616
1617uint8_t *
1618qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1619 uint32_t offset, uint32_t length)
1620{
1621 /* Suspend HBA. */
1622 scsi_block_requests(ha->host);
1623 ha->isp_ops.disable_intrs(ha);
1624 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1625
1626 /* Go with read. */
1627 qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1628
1629 /* Resume HBA. */
1630 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1631 ha->isp_ops.enable_intrs(ha);
1632 scsi_unblock_requests(ha->host);
1633
1634 return buf;
1635}
1636
1637int
1638qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1639 uint32_t offset, uint32_t length)
1640{
1641 int rval;
1642
1643 /* Suspend HBA. */
1644 scsi_block_requests(ha->host);
1645 ha->isp_ops.disable_intrs(ha);
1646 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1647
1648 /* Go with write. */
1649 rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1650 length >> 2);
1651
1652 /* Resume HBA -- RISC reset needed. */
1653 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1654 set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1655 up(ha->dpc_wait);
1656 qla2x00_wait_for_hba_online(ha);
1657 scsi_unblock_requests(ha->host);
1658
1659 return rval;
1660}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 02:02:47 -0500