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authorMike Frysinger <michael.frysinger@analog.com>2007-11-21 02:55:45 -0500
committerBryan Wu <bryan.wu@analog.com>2007-11-21 02:55:45 -0500
commit81a487a59f246a9eba24c3622e4c964e3347239d (patch)
treeeea510c54d09abcacf508ec473181162406cfc0b
parent9f2ff54d7291d4386dc02d6a153e6cc621f32aa8 (diff)
Blackfin arch: cleanup the cplb declares
- no need to declare their sizes in the common header - no need to tack on the section attribute as only the definition matters, not references Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
-rw-r--r--arch/blackfin/kernel/cplbinit.c27
-rw-r--r--include/asm-blackfin/cplbinit.h33
2 files changed, 22 insertions, 38 deletions
diff --git a/arch/blackfin/kernel/cplbinit.c b/arch/blackfin/kernel/cplbinit.c
index 7392ac2d2c29..959b510c5ffb 100644
--- a/arch/blackfin/kernel/cplbinit.c
+++ b/arch/blackfin/kernel/cplbinit.c
@@ -26,29 +26,22 @@
26#include <asm/cplb.h> 26#include <asm/cplb.h>
27#include <asm/cplbinit.h> 27#include <asm/cplbinit.h>
28 28
29u_long icplb_table[MAX_CPLBS+1]; 29u_long icplb_table[MAX_CPLBS + 1];
30u_long dcplb_table[MAX_CPLBS+1]; 30u_long dcplb_table[MAX_CPLBS + 1];
31 31
32#ifdef CONFIG_CPLB_SWITCH_TAB_L1 32#ifdef CONFIG_CPLB_SWITCH_TAB_L1
33u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); 33# define PDT_ATTR __attribute__((l1_data))
34u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
35
36#ifdef CONFIG_CPLB_INFO
37u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
38u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
39#endif /* CONFIG_CPLB_INFO */
40
41#else 34#else
35# define PDT_ATTR
36#endif
42 37
43u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]; 38u_long ipdt_table[MAX_SWITCH_I_CPLBS + 1] PDT_ATTR;
44u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]; 39u_long dpdt_table[MAX_SWITCH_D_CPLBS + 1] PDT_ATTR;
45 40
46#ifdef CONFIG_CPLB_INFO 41#ifdef CONFIG_CPLB_INFO
47u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; 42u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS] PDT_ATTR;
48u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; 43u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS] PDT_ATTR;
49#endif /* CONFIG_CPLB_INFO */ 44#endif
50
51#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
52 45
53struct s_cplb { 46struct s_cplb {
54 struct cplb_tab init_i; 47 struct cplb_tab init_i;
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bdb..c4d0596e8e9f 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,6 +27,9 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#ifndef __ASM_CPLBINIT_H__
31#define __ASM_CPLBINIT_H__
32
30#include <asm/blackfin.h> 33#include <asm/blackfin.h>
31#include <asm/cplb.h> 34#include <asm/cplb.h>
32 35
@@ -57,8 +60,8 @@ struct cplb_tab {
57 u16 size; 60 u16 size;
58}; 61};
59 62
60extern u_long icplb_table[MAX_CPLBS+1]; 63extern u_long icplb_table[];
61extern u_long dcplb_table[MAX_CPLBS+1]; 64extern u_long dcplb_table[];
62 65
63/* Till here we are discussing about the static memory management model. 66/* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB 67 * However, the operating envoronments commonly define more CPLB
@@ -69,28 +72,16 @@ extern u_long dcplb_table[MAX_CPLBS+1];
69 * This is how Page descriptor Table is implemented in uClinux/Blackfin. 72 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
70 */ 73 */
71 74
72#ifdef CONFIG_CPLB_SWITCH_TAB_L1 75extern u_long ipdt_table[];
73extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); 76extern u_long dpdt_table[];
74extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
75
76#ifdef CONFIG_CPLB_INFO
77extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
78extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
79#endif /* CONFIG_CPLB_INFO */
80
81#else
82
83extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
85
86#ifdef CONFIG_CPLB_INFO 77#ifdef CONFIG_CPLB_INFO
87extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; 78extern u_long ipdt_swapcount_table[];
88extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; 79extern u_long dpdt_swapcount_table[];
89#endif /* CONFIG_CPLB_INFO */ 80#endif
90
91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
92 81
93extern unsigned long reserved_mem_dcache_on; 82extern unsigned long reserved_mem_dcache_on;
94extern unsigned long reserved_mem_icache_on; 83extern unsigned long reserved_mem_icache_on;
95 84
96extern void generate_cpl_tables(void); 85extern void generate_cpl_tables(void);
86
87#endif