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authorMike Frysinger <vapier@gentoo.org>2009-04-10 17:20:19 -0400
committerMike Frysinger <vapier@gentoo.org>2009-06-12 06:03:48 -0400
commit78f28a0a83a86dfe021f7d8169208b9af2a23201 (patch)
tree8a97b224bdefba3c0ea057d8f5aa0af25760067a
parentf8b556514c4481a500ace4745731f04a77c08d54 (diff)
Blackfin: simplify the do_flush macro
Simplify the do_flush macro now that we don't need to take into account a second instruction being used together. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
-rw-r--r--arch/blackfin/mach-common/cache.S30
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index c295e8f837c0..d9666fe6c3d6 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -15,6 +15,13 @@
15 15
16.text 16.text
17 17
18/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
19#if ANOMALY_05000443
20# define BROK_FLUSH_INST "IFLUSH"
21#else
22# define BROK_FLUSH_INST "no anomaly! yeah!"
23#endif
24
18/* Since all L1 caches work the same way, we use the same method for flushing 25/* Since all L1 caches work the same way, we use the same method for flushing
19 * them. Only the actual flush instruction differs. We write this in asm as 26 * them. Only the actual flush instruction differs. We write this in asm as
20 * GCC can be hard to coax into writing nice hardware loops. 27 * GCC can be hard to coax into writing nice hardware loops.
@@ -23,7 +30,7 @@
23 * R0 = start address 30 * R0 = start address
24 * R1 = end address 31 * R1 = end address
25 */ 32 */
26.macro do_flush flushins:req optflushins optnopins label 33.macro do_flush flushins:req label
27 34
28 R2 = -L1_CACHE_BYTES; 35 R2 = -L1_CACHE_BYTES;
29 36
@@ -44,22 +51,15 @@
44\label : 51\label :
45.endif 52.endif
46 P0 = R0; 53 P0 = R0;
54
47 LSETUP (1f, 2f) LC1 = P1; 55 LSETUP (1f, 2f) LC1 = P1;
481: 561:
49.ifnb \optflushins 57.ifeqs "\flushins", BROK_FLUSH_INST
50 \optflushins [P0];
51.endif
52#if ANOMALY_05000443
53.ifb \optnopins
542:
55.endif
56 \flushins [P0++]; 58 \flushins [P0++];
57.ifnb \optnopins 592: nop;
582: \optnopins; 60.else
59.endif
60#else
612: \flushins [P0++]; 612: \flushins [P0++];
62#endif 62.endif
63 63
64 RTS; 64 RTS;
65.endm 65.endm
@@ -77,7 +77,7 @@ ENTRY(_blackfin_icache_flush_range)
77 */ 77 */
78 P0 = R0; 78 P0 = R0;
79 IFLUSH[P0]; 79 IFLUSH[P0];
80 do_flush IFLUSH, , nop 80 do_flush IFLUSH
81ENDPROC(_blackfin_icache_flush_range) 81ENDPROC(_blackfin_icache_flush_range)
82 82
83/* Throw away all D-cached data in specified region without any obligation to 83/* Throw away all D-cached data in specified region without any obligation to
@@ -91,7 +91,7 @@ ENDPROC(_blackfin_dcache_invalidate_range)
91 91
92/* Flush all data cache lines assocoiated with this memory area */ 92/* Flush all data cache lines assocoiated with this memory area */
93ENTRY(_blackfin_dcache_flush_range) 93ENTRY(_blackfin_dcache_flush_range)
94 do_flush FLUSH, , , .Ldfr 94 do_flush FLUSH, .Ldfr
95ENDPROC(_blackfin_dcache_flush_range) 95ENDPROC(_blackfin_dcache_flush_range)
96 96
97/* Our headers convert the page structure to an address, so just need to flush 97/* Our headers convert the page structure to an address, so just need to flush