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authorDenis Turischev <denis@compulab.co.il>2011-03-10 08:14:00 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2011-03-14 19:24:23 -0400
commit6ae705b23be8da52d3163be9d81e9b767876aaf9 (patch)
tree02d1343739ebbbccc0b0b75ceca9ec749c686917
parent1a738dcf6dac74a0ce10853a068d822f66f73268 (diff)
pch_uart: reference clock on CM-iTC
Default clock source for UARTs on Topcliff is external UART_CLK. On CM-iTC USB_48MHz is used instead. After VCO2PLL and DIV manipulations UARTs will receive 192 MHz. Clock manipulations on Topcliff are controlled in pch_phub.c v2: redone against the linux-next tree v3: redone against linux/kernel/git/next/linux-next.git snapshot Signed-off-by: Denis Turischev <denis@compulab.co.il> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/misc/pch_phub.c16
-rw-r--r--drivers/tty/serial/pch_uart.c9
2 files changed, 23 insertions, 2 deletions
diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c
index 98bffc471b17..5dd0b921bfc6 100644
--- a/drivers/misc/pch_phub.c
+++ b/drivers/misc/pch_phub.c
@@ -27,6 +27,7 @@
27#include <linux/mutex.h> 27#include <linux/mutex.h>
28#include <linux/if_ether.h> 28#include <linux/if_ether.h>
29#include <linux/ctype.h> 29#include <linux/ctype.h>
30#include <linux/dmi.h>
30 31
31#define PHUB_STATUS 0x00 /* Status Register offset */ 32#define PHUB_STATUS 0x00 /* Status Register offset */
32#define PHUB_CONTROL 0x04 /* Control Register offset */ 33#define PHUB_CONTROL 0x04 /* Control Register offset */
@@ -46,6 +47,13 @@
46#define PCH_MINOR_NOS 1 47#define PCH_MINOR_NOS 1
47#define CLKCFG_CAN_50MHZ 0x12000000 48#define CLKCFG_CAN_50MHZ 0x12000000
48#define CLKCFG_CANCLK_MASK 0xFF000000 49#define CLKCFG_CANCLK_MASK 0xFF000000
50#define CLKCFG_UART_MASK 0xFFFFFF
51
52/* CM-iTC */
53#define CLKCFG_UART_48MHZ (1 << 16)
54#define CLKCFG_BAUDDIV (2 << 20)
55#define CLKCFG_PLL2VCO (8 << 9)
56#define CLKCFG_UARTCLKSEL (1 << 18)
49 57
50/* Macros for ML7213 */ 58/* Macros for ML7213 */
51#define PCI_VENDOR_ID_ROHM 0x10db 59#define PCI_VENDOR_ID_ROHM 0x10db
@@ -618,6 +626,14 @@ static int __devinit pch_phub_probe(struct pci_dev *pdev,
618 CLKCFG_CAN_50MHZ, 626 CLKCFG_CAN_50MHZ,
619 CLKCFG_CANCLK_MASK); 627 CLKCFG_CANCLK_MASK);
620 628
629 /* quirk for CM-iTC board */
630 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
631 pch_phub_read_modify_write_reg(chip,
632 (unsigned int)CLKCFG_REG_OFFSET,
633 CLKCFG_UART_48MHZ | CLKCFG_BAUDDIV |
634 CLKCFG_PLL2VCO | CLKCFG_UARTCLKSEL,
635 CLKCFG_UART_MASK);
636
621 /* set the prefech value */ 637 /* set the prefech value */
622 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14); 638 iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
623 /* set the interrupt delay value */ 639 /* set the interrupt delay value */
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index a5ce9a5c018d..a9ad7f33526d 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -21,6 +21,7 @@
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/dmi.h>
24 25
25#include <linux/dmaengine.h> 26#include <linux/dmaengine.h>
26#include <linux/pch_dma.h> 27#include <linux/pch_dma.h>
@@ -1404,14 +1405,18 @@ static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1404 if (!rxbuf) 1405 if (!rxbuf)
1405 goto init_port_free_txbuf; 1406 goto init_port_free_txbuf;
1406 1407
1408 base_baud = 1843200; /* 1.8432MHz */
1409
1410 /* quirk for CM-iTC board */
1411 if (strstr(dmi_get_system_info(DMI_BOARD_NAME), "CM-iTC"))
1412 base_baud = 192000000; /* 192.0MHz */
1413
1407 switch (port_type) { 1414 switch (port_type) {
1408 case PORT_UNKNOWN: 1415 case PORT_UNKNOWN:
1409 fifosize = 256; /* EG20T/ML7213: UART0 */ 1416 fifosize = 256; /* EG20T/ML7213: UART0 */
1410 base_baud = 1843200; /* 1.8432MHz */
1411 break; 1417 break;
1412 case PORT_8250: 1418 case PORT_8250:
1413 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1419 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1414 base_baud = 1843200; /* 1.8432MHz */
1415 break; 1420 break;
1416 default: 1421 default:
1417 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1422 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);