diff options
author | Jakob Bornecrantz <jakob@vmware.com> | 2009-12-09 19:19:10 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-12-14 17:38:36 -0500 |
commit | 632f61178d0473861ba77e774bb654b37bc7eccc (patch) | |
tree | 7e74b697dc5e7aafcef843872b60608834bfbb89 | |
parent | be1cb8689c480228ffd2e4bfccc0dab7156cd9ea (diff) |
drm/vmwgfx: Add svga headers for vmwgfx driver
These headers are shared between multiple place where
different coding standards apply. They will be fixed
up at a later time.
Signed-off-by: Thomas Hellström <thellstrom@vmware.com>
Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga3d_reg.h | 1793 | ||||
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga_escape.h | 89 | ||||
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga_overlay.h | 201 | ||||
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga_reg.h | 1346 | ||||
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga_types.h | 45 |
5 files changed, 3474 insertions, 0 deletions
diff --git a/drivers/gpu/drm/vmwgfx/svga3d_reg.h b/drivers/gpu/drm/vmwgfx/svga3d_reg.h new file mode 100644 index 000000000000..77cb45331000 --- /dev/null +++ b/drivers/gpu/drm/vmwgfx/svga3d_reg.h | |||
@@ -0,0 +1,1793 @@ | |||
1 | /********************************************************** | ||
2 | * Copyright 1998-2009 VMware, Inc. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person | ||
5 | * obtaining a copy of this software and associated documentation | ||
6 | * files (the "Software"), to deal in the Software without | ||
7 | * restriction, including without limitation the rights to use, copy, | ||
8 | * modify, merge, publish, distribute, sublicense, and/or sell copies | ||
9 | * of the Software, and to permit persons to whom the Software is | ||
10 | * furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be | ||
13 | * included in all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
22 | * SOFTWARE. | ||
23 | * | ||
24 | **********************************************************/ | ||
25 | |||
26 | /* | ||
27 | * svga3d_reg.h -- | ||
28 | * | ||
29 | * SVGA 3D hardware definitions | ||
30 | */ | ||
31 | |||
32 | #ifndef _SVGA3D_REG_H_ | ||
33 | #define _SVGA3D_REG_H_ | ||
34 | |||
35 | #include "svga_reg.h" | ||
36 | |||
37 | |||
38 | /* | ||
39 | * 3D Hardware Version | ||
40 | * | ||
41 | * The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo | ||
42 | * register. Is set by the host and read by the guest. This lets | ||
43 | * us make new guest drivers which are backwards-compatible with old | ||
44 | * SVGA hardware revisions. It does not let us support old guest | ||
45 | * drivers. Good enough for now. | ||
46 | * | ||
47 | */ | ||
48 | |||
49 | #define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF)) | ||
50 | #define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16) | ||
51 | #define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF) | ||
52 | |||
53 | typedef enum { | ||
54 | SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1), | ||
55 | SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2), | ||
56 | SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3), | ||
57 | SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1), | ||
58 | SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4), | ||
59 | SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0), | ||
60 | SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS65_B1, | ||
61 | } SVGA3dHardwareVersion; | ||
62 | |||
63 | /* | ||
64 | * Generic Types | ||
65 | */ | ||
66 | |||
67 | typedef uint32 SVGA3dBool; /* 32-bit Bool definition */ | ||
68 | #define SVGA3D_NUM_CLIPPLANES 6 | ||
69 | #define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS 8 | ||
70 | |||
71 | |||
72 | /* | ||
73 | * Surface formats. | ||
74 | * | ||
75 | * If you modify this list, be sure to keep GLUtil.c in sync. It | ||
76 | * includes the internal format definition of each surface in | ||
77 | * GLUtil_ConvertSurfaceFormat, and it contains a table of | ||
78 | * human-readable names in GLUtil_GetFormatName. | ||
79 | */ | ||
80 | |||
81 | typedef enum SVGA3dSurfaceFormat { | ||
82 | SVGA3D_FORMAT_INVALID = 0, | ||
83 | |||
84 | SVGA3D_X8R8G8B8 = 1, | ||
85 | SVGA3D_A8R8G8B8 = 2, | ||
86 | |||
87 | SVGA3D_R5G6B5 = 3, | ||
88 | SVGA3D_X1R5G5B5 = 4, | ||
89 | SVGA3D_A1R5G5B5 = 5, | ||
90 | SVGA3D_A4R4G4B4 = 6, | ||
91 | |||
92 | SVGA3D_Z_D32 = 7, | ||
93 | SVGA3D_Z_D16 = 8, | ||
94 | SVGA3D_Z_D24S8 = 9, | ||
95 | SVGA3D_Z_D15S1 = 10, | ||
96 | |||
97 | SVGA3D_LUMINANCE8 = 11, | ||
98 | SVGA3D_LUMINANCE4_ALPHA4 = 12, | ||
99 | SVGA3D_LUMINANCE16 = 13, | ||
100 | SVGA3D_LUMINANCE8_ALPHA8 = 14, | ||
101 | |||
102 | SVGA3D_DXT1 = 15, | ||
103 | SVGA3D_DXT2 = 16, | ||
104 | SVGA3D_DXT3 = 17, | ||
105 | SVGA3D_DXT4 = 18, | ||
106 | SVGA3D_DXT5 = 19, | ||
107 | |||
108 | SVGA3D_BUMPU8V8 = 20, | ||
109 | SVGA3D_BUMPL6V5U5 = 21, | ||
110 | SVGA3D_BUMPX8L8V8U8 = 22, | ||
111 | SVGA3D_BUMPL8V8U8 = 23, | ||
112 | |||
113 | SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */ | ||
114 | SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */ | ||
115 | |||
116 | SVGA3D_A2R10G10B10 = 26, | ||
117 | |||
118 | /* signed formats */ | ||
119 | SVGA3D_V8U8 = 27, | ||
120 | SVGA3D_Q8W8V8U8 = 28, | ||
121 | SVGA3D_CxV8U8 = 29, | ||
122 | |||
123 | /* mixed formats */ | ||
124 | SVGA3D_X8L8V8U8 = 30, | ||
125 | SVGA3D_A2W10V10U10 = 31, | ||
126 | |||
127 | SVGA3D_ALPHA8 = 32, | ||
128 | |||
129 | /* Single- and dual-component floating point formats */ | ||
130 | SVGA3D_R_S10E5 = 33, | ||
131 | SVGA3D_R_S23E8 = 34, | ||
132 | SVGA3D_RG_S10E5 = 35, | ||
133 | SVGA3D_RG_S23E8 = 36, | ||
134 | |||
135 | /* | ||
136 | * Any surface can be used as a buffer object, but SVGA3D_BUFFER is | ||
137 | * the most efficient format to use when creating new surfaces | ||
138 | * expressly for index or vertex data. | ||
139 | */ | ||
140 | SVGA3D_BUFFER = 37, | ||
141 | |||
142 | SVGA3D_Z_D24X8 = 38, | ||
143 | |||
144 | SVGA3D_V16U16 = 39, | ||
145 | |||
146 | SVGA3D_G16R16 = 40, | ||
147 | SVGA3D_A16B16G16R16 = 41, | ||
148 | |||
149 | /* Packed Video formats */ | ||
150 | SVGA3D_UYVY = 42, | ||
151 | SVGA3D_YUY2 = 43, | ||
152 | |||
153 | SVGA3D_FORMAT_MAX | ||
154 | } SVGA3dSurfaceFormat; | ||
155 | |||
156 | typedef uint32 SVGA3dColor; /* a, r, g, b */ | ||
157 | |||
158 | /* | ||
159 | * These match the D3DFORMAT_OP definitions used by Direct3D. We need | ||
160 | * them so that we can query the host for what the supported surface | ||
161 | * operations are (when we're using the D3D backend, in particular), | ||
162 | * and so we can send those operations to the guest. | ||
163 | */ | ||
164 | typedef enum { | ||
165 | SVGA3DFORMAT_OP_TEXTURE = 0x00000001, | ||
166 | SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002, | ||
167 | SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004, | ||
168 | SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008, | ||
169 | SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010, | ||
170 | SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040, | ||
171 | SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080, | ||
172 | |||
173 | /* | ||
174 | * This format can be used as a render target if the current display mode | ||
175 | * is the same depth if the alpha channel is ignored. e.g. if the device | ||
176 | * can render to A8R8G8B8 when the display mode is X8R8G8B8, then the | ||
177 | * format op list entry for A8R8G8B8 should have this cap. | ||
178 | */ | ||
179 | SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100, | ||
180 | |||
181 | /* | ||
182 | * This format contains DirectDraw support (including Flip). This flag | ||
183 | * should not to be set on alpha formats. | ||
184 | */ | ||
185 | SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400, | ||
186 | |||
187 | /* | ||
188 | * The rasterizer can support some level of Direct3D support in this format | ||
189 | * and implies that the driver can create a Context in this mode (for some | ||
190 | * render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE | ||
191 | * flag must also be set. | ||
192 | */ | ||
193 | SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800, | ||
194 | |||
195 | /* | ||
196 | * This is set for a private format when the driver has put the bpp in | ||
197 | * the structure. | ||
198 | */ | ||
199 | SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000, | ||
200 | |||
201 | /* | ||
202 | * Indicates that this format can be converted to any RGB format for which | ||
203 | * SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified | ||
204 | */ | ||
205 | SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000, | ||
206 | |||
207 | /* | ||
208 | * Indicates that this format can be used to create offscreen plain surfaces. | ||
209 | */ | ||
210 | SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000, | ||
211 | |||
212 | /* | ||
213 | * Indicated that this format can be read as an SRGB texture (meaning that the | ||
214 | * sampler will linearize the looked up data) | ||
215 | */ | ||
216 | SVGA3DFORMAT_OP_SRGBREAD = 0x00008000, | ||
217 | |||
218 | /* | ||
219 | * Indicates that this format can be used in the bumpmap instructions | ||
220 | */ | ||
221 | SVGA3DFORMAT_OP_BUMPMAP = 0x00010000, | ||
222 | |||
223 | /* | ||
224 | * Indicates that this format can be sampled by the displacement map sampler | ||
225 | */ | ||
226 | SVGA3DFORMAT_OP_DMAP = 0x00020000, | ||
227 | |||
228 | /* | ||
229 | * Indicates that this format cannot be used with texture filtering | ||
230 | */ | ||
231 | SVGA3DFORMAT_OP_NOFILTER = 0x00040000, | ||
232 | |||
233 | /* | ||
234 | * Indicates that format conversions are supported to this RGB format if | ||
235 | * SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format. | ||
236 | */ | ||
237 | SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000, | ||
238 | |||
239 | /* | ||
240 | * Indicated that this format can be written as an SRGB target (meaning that the | ||
241 | * pixel pipe will DE-linearize data on output to format) | ||
242 | */ | ||
243 | SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000, | ||
244 | |||
245 | /* | ||
246 | * Indicates that this format cannot be used with alpha blending | ||
247 | */ | ||
248 | SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000, | ||
249 | |||
250 | /* | ||
251 | * Indicates that the device can auto-generated sublevels for resources | ||
252 | * of this format | ||
253 | */ | ||
254 | SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000, | ||
255 | |||
256 | /* | ||
257 | * Indicates that this format can be used by vertex texture sampler | ||
258 | */ | ||
259 | SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000, | ||
260 | |||
261 | /* | ||
262 | * Indicates that this format supports neither texture coordinate wrap | ||
263 | * modes, nor mipmapping | ||
264 | */ | ||
265 | SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000 | ||
266 | } SVGA3dFormatOp; | ||
267 | |||
268 | /* | ||
269 | * This structure is a conversion of SVGA3DFORMAT_OP_*. | ||
270 | * Entries must be located at the same position. | ||
271 | */ | ||
272 | typedef union { | ||
273 | uint32 value; | ||
274 | struct { | ||
275 | uint32 texture : 1; | ||
276 | uint32 volumeTexture : 1; | ||
277 | uint32 cubeTexture : 1; | ||
278 | uint32 offscreenRenderTarget : 1; | ||
279 | uint32 sameFormatRenderTarget : 1; | ||
280 | uint32 unknown1 : 1; | ||
281 | uint32 zStencil : 1; | ||
282 | uint32 zStencilArbitraryDepth : 1; | ||
283 | uint32 sameFormatUpToAlpha : 1; | ||
284 | uint32 unknown2 : 1; | ||
285 | uint32 displayMode : 1; | ||
286 | uint32 acceleration3d : 1; | ||
287 | uint32 pixelSize : 1; | ||
288 | uint32 convertToARGB : 1; | ||
289 | uint32 offscreenPlain : 1; | ||
290 | uint32 sRGBRead : 1; | ||
291 | uint32 bumpMap : 1; | ||
292 | uint32 dmap : 1; | ||
293 | uint32 noFilter : 1; | ||
294 | uint32 memberOfGroupARGB : 1; | ||
295 | uint32 sRGBWrite : 1; | ||
296 | uint32 noAlphaBlend : 1; | ||
297 | uint32 autoGenMipMap : 1; | ||
298 | uint32 vertexTexture : 1; | ||
299 | uint32 noTexCoordWrapNorMip : 1; | ||
300 | }; | ||
301 | } SVGA3dSurfaceFormatCaps; | ||
302 | |||
303 | /* | ||
304 | * SVGA_3D_CMD_SETRENDERSTATE Types. All value types | ||
305 | * must fit in a uint32. | ||
306 | */ | ||
307 | |||
308 | typedef enum { | ||
309 | SVGA3D_RS_INVALID = 0, | ||
310 | SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */ | ||
311 | SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */ | ||
312 | SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */ | ||
313 | SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */ | ||
314 | SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */ | ||
315 | SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */ | ||
316 | SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */ | ||
317 | SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */ | ||
318 | SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */ | ||
319 | SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */ | ||
320 | SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */ | ||
321 | SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */ | ||
322 | SVGA3D_RS_STENCILREF = 13, /* uint32 */ | ||
323 | SVGA3D_RS_STENCILMASK = 14, /* uint32 */ | ||
324 | SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */ | ||
325 | SVGA3D_RS_FOGSTART = 16, /* float */ | ||
326 | SVGA3D_RS_FOGEND = 17, /* float */ | ||
327 | SVGA3D_RS_FOGDENSITY = 18, /* float */ | ||
328 | SVGA3D_RS_POINTSIZE = 19, /* float */ | ||
329 | SVGA3D_RS_POINTSIZEMIN = 20, /* float */ | ||
330 | SVGA3D_RS_POINTSIZEMAX = 21, /* float */ | ||
331 | SVGA3D_RS_POINTSCALE_A = 22, /* float */ | ||
332 | SVGA3D_RS_POINTSCALE_B = 23, /* float */ | ||
333 | SVGA3D_RS_POINTSCALE_C = 24, /* float */ | ||
334 | SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */ | ||
335 | SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */ | ||
336 | SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */ | ||
337 | SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */ | ||
338 | SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */ | ||
339 | SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */ | ||
340 | SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */ | ||
341 | SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */ | ||
342 | SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */ | ||
343 | SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */ | ||
344 | SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */ | ||
345 | SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */ | ||
346 | SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */ | ||
347 | SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */ | ||
348 | SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */ | ||
349 | SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */ | ||
350 | SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */ | ||
351 | SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */ | ||
352 | SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */ | ||
353 | SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */ | ||
354 | SVGA3D_RS_ZBIAS = 45, /* float */ | ||
355 | SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */ | ||
356 | SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */ | ||
357 | SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */ | ||
358 | SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */ | ||
359 | SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */ | ||
360 | SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */ | ||
361 | SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */ | ||
362 | SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */ | ||
363 | SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */ | ||
364 | SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */ | ||
365 | SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */ | ||
366 | SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */ | ||
367 | SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */ | ||
368 | SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */ | ||
369 | SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */ | ||
370 | SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */ | ||
371 | SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */ | ||
372 | SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */ | ||
373 | SVGA3D_RS_DEPTHBIAS = 64, /* float */ | ||
374 | |||
375 | |||
376 | /* | ||
377 | * Output Gamma Level | ||
378 | * | ||
379 | * Output gamma effects the gamma curve of colors that are output from the | ||
380 | * rendering pipeline. A value of 1.0 specifies a linear color space. If the | ||
381 | * value is <= 0.0, gamma correction is ignored and linear color space is | ||
382 | * used. | ||
383 | */ | ||
384 | |||
385 | SVGA3D_RS_OUTPUTGAMMA = 65, /* float */ | ||
386 | SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */ | ||
387 | SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */ | ||
388 | SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */ | ||
389 | SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */ | ||
390 | SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */ | ||
391 | SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */ | ||
392 | SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */ | ||
393 | SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */ | ||
394 | SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */ | ||
395 | SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */ | ||
396 | SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */ | ||
397 | SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */ | ||
398 | SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */ | ||
399 | SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */ | ||
400 | SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */ | ||
401 | SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */ | ||
402 | SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */ | ||
403 | SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */ | ||
404 | SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */ | ||
405 | SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */ | ||
406 | SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */ | ||
407 | SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */ | ||
408 | SVGA3D_RS_TWEENFACTOR = 88, /* float */ | ||
409 | SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */ | ||
410 | SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */ | ||
411 | SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */ | ||
412 | SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */ | ||
413 | SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */ | ||
414 | SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */ | ||
415 | SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */ | ||
416 | SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */ | ||
417 | SVGA3D_RS_MAX | ||
418 | } SVGA3dRenderStateName; | ||
419 | |||
420 | typedef enum { | ||
421 | SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */ | ||
422 | SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */ | ||
423 | SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */ | ||
424 | } SVGA3dVertexMaterial; | ||
425 | |||
426 | typedef enum { | ||
427 | SVGA3D_FILLMODE_INVALID = 0, | ||
428 | SVGA3D_FILLMODE_POINT = 1, | ||
429 | SVGA3D_FILLMODE_LINE = 2, | ||
430 | SVGA3D_FILLMODE_FILL = 3, | ||
431 | SVGA3D_FILLMODE_MAX | ||
432 | } SVGA3dFillModeType; | ||
433 | |||
434 | |||
435 | typedef | ||
436 | union { | ||
437 | struct { | ||
438 | uint16 mode; /* SVGA3dFillModeType */ | ||
439 | uint16 face; /* SVGA3dFace */ | ||
440 | }; | ||
441 | uint32 uintValue; | ||
442 | } SVGA3dFillMode; | ||
443 | |||
444 | typedef enum { | ||
445 | SVGA3D_SHADEMODE_INVALID = 0, | ||
446 | SVGA3D_SHADEMODE_FLAT = 1, | ||
447 | SVGA3D_SHADEMODE_SMOOTH = 2, | ||
448 | SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */ | ||
449 | SVGA3D_SHADEMODE_MAX | ||
450 | } SVGA3dShadeMode; | ||
451 | |||
452 | typedef | ||
453 | union { | ||
454 | struct { | ||
455 | uint16 repeat; | ||
456 | uint16 pattern; | ||
457 | }; | ||
458 | uint32 uintValue; | ||
459 | } SVGA3dLinePattern; | ||
460 | |||
461 | typedef enum { | ||
462 | SVGA3D_BLENDOP_INVALID = 0, | ||
463 | SVGA3D_BLENDOP_ZERO = 1, | ||
464 | SVGA3D_BLENDOP_ONE = 2, | ||
465 | SVGA3D_BLENDOP_SRCCOLOR = 3, | ||
466 | SVGA3D_BLENDOP_INVSRCCOLOR = 4, | ||
467 | SVGA3D_BLENDOP_SRCALPHA = 5, | ||
468 | SVGA3D_BLENDOP_INVSRCALPHA = 6, | ||
469 | SVGA3D_BLENDOP_DESTALPHA = 7, | ||
470 | SVGA3D_BLENDOP_INVDESTALPHA = 8, | ||
471 | SVGA3D_BLENDOP_DESTCOLOR = 9, | ||
472 | SVGA3D_BLENDOP_INVDESTCOLOR = 10, | ||
473 | SVGA3D_BLENDOP_SRCALPHASAT = 11, | ||
474 | SVGA3D_BLENDOP_BLENDFACTOR = 12, | ||
475 | SVGA3D_BLENDOP_INVBLENDFACTOR = 13, | ||
476 | SVGA3D_BLENDOP_MAX | ||
477 | } SVGA3dBlendOp; | ||
478 | |||
479 | typedef enum { | ||
480 | SVGA3D_BLENDEQ_INVALID = 0, | ||
481 | SVGA3D_BLENDEQ_ADD = 1, | ||
482 | SVGA3D_BLENDEQ_SUBTRACT = 2, | ||
483 | SVGA3D_BLENDEQ_REVSUBTRACT = 3, | ||
484 | SVGA3D_BLENDEQ_MINIMUM = 4, | ||
485 | SVGA3D_BLENDEQ_MAXIMUM = 5, | ||
486 | SVGA3D_BLENDEQ_MAX | ||
487 | } SVGA3dBlendEquation; | ||
488 | |||
489 | typedef enum { | ||
490 | SVGA3D_FRONTWINDING_INVALID = 0, | ||
491 | SVGA3D_FRONTWINDING_CW = 1, | ||
492 | SVGA3D_FRONTWINDING_CCW = 2, | ||
493 | SVGA3D_FRONTWINDING_MAX | ||
494 | } SVGA3dFrontWinding; | ||
495 | |||
496 | typedef enum { | ||
497 | SVGA3D_FACE_INVALID = 0, | ||
498 | SVGA3D_FACE_NONE = 1, | ||
499 | SVGA3D_FACE_FRONT = 2, | ||
500 | SVGA3D_FACE_BACK = 3, | ||
501 | SVGA3D_FACE_FRONT_BACK = 4, | ||
502 | SVGA3D_FACE_MAX | ||
503 | } SVGA3dFace; | ||
504 | |||
505 | /* | ||
506 | * The order and the values should not be changed | ||
507 | */ | ||
508 | |||
509 | typedef enum { | ||
510 | SVGA3D_CMP_INVALID = 0, | ||
511 | SVGA3D_CMP_NEVER = 1, | ||
512 | SVGA3D_CMP_LESS = 2, | ||
513 | SVGA3D_CMP_EQUAL = 3, | ||
514 | SVGA3D_CMP_LESSEQUAL = 4, | ||
515 | SVGA3D_CMP_GREATER = 5, | ||
516 | SVGA3D_CMP_NOTEQUAL = 6, | ||
517 | SVGA3D_CMP_GREATEREQUAL = 7, | ||
518 | SVGA3D_CMP_ALWAYS = 8, | ||
519 | SVGA3D_CMP_MAX | ||
520 | } SVGA3dCmpFunc; | ||
521 | |||
522 | /* | ||
523 | * SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows | ||
524 | * the fog factor to be specified in the alpha component of the specular | ||
525 | * (a.k.a. secondary) vertex color. | ||
526 | */ | ||
527 | typedef enum { | ||
528 | SVGA3D_FOGFUNC_INVALID = 0, | ||
529 | SVGA3D_FOGFUNC_EXP = 1, | ||
530 | SVGA3D_FOGFUNC_EXP2 = 2, | ||
531 | SVGA3D_FOGFUNC_LINEAR = 3, | ||
532 | SVGA3D_FOGFUNC_PER_VERTEX = 4 | ||
533 | } SVGA3dFogFunction; | ||
534 | |||
535 | /* | ||
536 | * SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex | ||
537 | * or per-pixel basis. | ||
538 | */ | ||
539 | typedef enum { | ||
540 | SVGA3D_FOGTYPE_INVALID = 0, | ||
541 | SVGA3D_FOGTYPE_VERTEX = 1, | ||
542 | SVGA3D_FOGTYPE_PIXEL = 2, | ||
543 | SVGA3D_FOGTYPE_MAX = 3 | ||
544 | } SVGA3dFogType; | ||
545 | |||
546 | /* | ||
547 | * SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is | ||
548 | * computed using the eye Z value of each pixel (or vertex), whereas range- | ||
549 | * based fog is computed using the actual distance (range) to the eye. | ||
550 | */ | ||
551 | typedef enum { | ||
552 | SVGA3D_FOGBASE_INVALID = 0, | ||
553 | SVGA3D_FOGBASE_DEPTHBASED = 1, | ||
554 | SVGA3D_FOGBASE_RANGEBASED = 2, | ||
555 | SVGA3D_FOGBASE_MAX = 3 | ||
556 | } SVGA3dFogBase; | ||
557 | |||
558 | typedef enum { | ||
559 | SVGA3D_STENCILOP_INVALID = 0, | ||
560 | SVGA3D_STENCILOP_KEEP = 1, | ||
561 | SVGA3D_STENCILOP_ZERO = 2, | ||
562 | SVGA3D_STENCILOP_REPLACE = 3, | ||
563 | SVGA3D_STENCILOP_INCRSAT = 4, | ||
564 | SVGA3D_STENCILOP_DECRSAT = 5, | ||
565 | SVGA3D_STENCILOP_INVERT = 6, | ||
566 | SVGA3D_STENCILOP_INCR = 7, | ||
567 | SVGA3D_STENCILOP_DECR = 8, | ||
568 | SVGA3D_STENCILOP_MAX | ||
569 | } SVGA3dStencilOp; | ||
570 | |||
571 | typedef enum { | ||
572 | SVGA3D_CLIPPLANE_0 = (1 << 0), | ||
573 | SVGA3D_CLIPPLANE_1 = (1 << 1), | ||
574 | SVGA3D_CLIPPLANE_2 = (1 << 2), | ||
575 | SVGA3D_CLIPPLANE_3 = (1 << 3), | ||
576 | SVGA3D_CLIPPLANE_4 = (1 << 4), | ||
577 | SVGA3D_CLIPPLANE_5 = (1 << 5), | ||
578 | } SVGA3dClipPlanes; | ||
579 | |||
580 | typedef enum { | ||
581 | SVGA3D_CLEAR_COLOR = 0x1, | ||
582 | SVGA3D_CLEAR_DEPTH = 0x2, | ||
583 | SVGA3D_CLEAR_STENCIL = 0x4 | ||
584 | } SVGA3dClearFlag; | ||
585 | |||
586 | typedef enum { | ||
587 | SVGA3D_RT_DEPTH = 0, | ||
588 | SVGA3D_RT_STENCIL = 1, | ||
589 | SVGA3D_RT_COLOR0 = 2, | ||
590 | SVGA3D_RT_COLOR1 = 3, | ||
591 | SVGA3D_RT_COLOR2 = 4, | ||
592 | SVGA3D_RT_COLOR3 = 5, | ||
593 | SVGA3D_RT_COLOR4 = 6, | ||
594 | SVGA3D_RT_COLOR5 = 7, | ||
595 | SVGA3D_RT_COLOR6 = 8, | ||
596 | SVGA3D_RT_COLOR7 = 9, | ||
597 | SVGA3D_RT_MAX, | ||
598 | SVGA3D_RT_INVALID = ((uint32)-1), | ||
599 | } SVGA3dRenderTargetType; | ||
600 | |||
601 | #define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1) | ||
602 | |||
603 | typedef | ||
604 | union { | ||
605 | struct { | ||
606 | uint32 red : 1; | ||
607 | uint32 green : 1; | ||
608 | uint32 blue : 1; | ||
609 | uint32 alpha : 1; | ||
610 | }; | ||
611 | uint32 uintValue; | ||
612 | } SVGA3dColorMask; | ||
613 | |||
614 | typedef enum { | ||
615 | SVGA3D_VBLEND_DISABLE = 0, | ||
616 | SVGA3D_VBLEND_1WEIGHT = 1, | ||
617 | SVGA3D_VBLEND_2WEIGHT = 2, | ||
618 | SVGA3D_VBLEND_3WEIGHT = 3, | ||
619 | } SVGA3dVertexBlendFlags; | ||
620 | |||
621 | typedef enum { | ||
622 | SVGA3D_WRAPCOORD_0 = 1 << 0, | ||
623 | SVGA3D_WRAPCOORD_1 = 1 << 1, | ||
624 | SVGA3D_WRAPCOORD_2 = 1 << 2, | ||
625 | SVGA3D_WRAPCOORD_3 = 1 << 3, | ||
626 | SVGA3D_WRAPCOORD_ALL = 0xF, | ||
627 | } SVGA3dWrapFlags; | ||
628 | |||
629 | /* | ||
630 | * SVGA_3D_CMD_TEXTURESTATE Types. All value types | ||
631 | * must fit in a uint32. | ||
632 | */ | ||
633 | |||
634 | typedef enum { | ||
635 | SVGA3D_TS_INVALID = 0, | ||
636 | SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */ | ||
637 | SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */ | ||
638 | SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */ | ||
639 | SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */ | ||
640 | SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */ | ||
641 | SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */ | ||
642 | SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */ | ||
643 | SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */ | ||
644 | SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */ | ||
645 | SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */ | ||
646 | SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */ | ||
647 | SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */ | ||
648 | SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */ | ||
649 | SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */ | ||
650 | SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */ | ||
651 | SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */ | ||
652 | SVGA3D_TS_BUMPENVMAT00 = 17, /* float */ | ||
653 | SVGA3D_TS_BUMPENVMAT01 = 18, /* float */ | ||
654 | SVGA3D_TS_BUMPENVMAT10 = 19, /* float */ | ||
655 | SVGA3D_TS_BUMPENVMAT11 = 20, /* float */ | ||
656 | SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */ | ||
657 | SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */ | ||
658 | SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */ | ||
659 | SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */ | ||
660 | |||
661 | |||
662 | /* | ||
663 | * Sampler Gamma Level | ||
664 | * | ||
665 | * Sampler gamma effects the color of samples taken from the sampler. A | ||
666 | * value of 1.0 will produce linear samples. If the value is <= 0.0 the | ||
667 | * gamma value is ignored and a linear space is used. | ||
668 | */ | ||
669 | |||
670 | SVGA3D_TS_GAMMA = 25, /* float */ | ||
671 | SVGA3D_TS_BUMPENVLSCALE = 26, /* float */ | ||
672 | SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */ | ||
673 | SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */ | ||
674 | SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */ | ||
675 | SVGA3D_TS_MAX | ||
676 | } SVGA3dTextureStateName; | ||
677 | |||
678 | typedef enum { | ||
679 | SVGA3D_TC_INVALID = 0, | ||
680 | SVGA3D_TC_DISABLE = 1, | ||
681 | SVGA3D_TC_SELECTARG1 = 2, | ||
682 | SVGA3D_TC_SELECTARG2 = 3, | ||
683 | SVGA3D_TC_MODULATE = 4, | ||
684 | SVGA3D_TC_ADD = 5, | ||
685 | SVGA3D_TC_ADDSIGNED = 6, | ||
686 | SVGA3D_TC_SUBTRACT = 7, | ||
687 | SVGA3D_TC_BLENDTEXTUREALPHA = 8, | ||
688 | SVGA3D_TC_BLENDDIFFUSEALPHA = 9, | ||
689 | SVGA3D_TC_BLENDCURRENTALPHA = 10, | ||
690 | SVGA3D_TC_BLENDFACTORALPHA = 11, | ||
691 | SVGA3D_TC_MODULATE2X = 12, | ||
692 | SVGA3D_TC_MODULATE4X = 13, | ||
693 | SVGA3D_TC_DSDT = 14, | ||
694 | SVGA3D_TC_DOTPRODUCT3 = 15, | ||
695 | SVGA3D_TC_BLENDTEXTUREALPHAPM = 16, | ||
696 | SVGA3D_TC_ADDSIGNED2X = 17, | ||
697 | SVGA3D_TC_ADDSMOOTH = 18, | ||
698 | SVGA3D_TC_PREMODULATE = 19, | ||
699 | SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20, | ||
700 | SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21, | ||
701 | SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22, | ||
702 | SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23, | ||
703 | SVGA3D_TC_BUMPENVMAPLUMINANCE = 24, | ||
704 | SVGA3D_TC_MULTIPLYADD = 25, | ||
705 | SVGA3D_TC_LERP = 26, | ||
706 | SVGA3D_TC_MAX | ||
707 | } SVGA3dTextureCombiner; | ||
708 | |||
709 | #define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0) | ||
710 | |||
711 | typedef enum { | ||
712 | SVGA3D_TEX_ADDRESS_INVALID = 0, | ||
713 | SVGA3D_TEX_ADDRESS_WRAP = 1, | ||
714 | SVGA3D_TEX_ADDRESS_MIRROR = 2, | ||
715 | SVGA3D_TEX_ADDRESS_CLAMP = 3, | ||
716 | SVGA3D_TEX_ADDRESS_BORDER = 4, | ||
717 | SVGA3D_TEX_ADDRESS_MIRRORONCE = 5, | ||
718 | SVGA3D_TEX_ADDRESS_EDGE = 6, | ||
719 | SVGA3D_TEX_ADDRESS_MAX | ||
720 | } SVGA3dTextureAddress; | ||
721 | |||
722 | /* | ||
723 | * SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is | ||
724 | * disabled, and the rasterizer should use the magnification filter instead. | ||
725 | */ | ||
726 | typedef enum { | ||
727 | SVGA3D_TEX_FILTER_NONE = 0, | ||
728 | SVGA3D_TEX_FILTER_NEAREST = 1, | ||
729 | SVGA3D_TEX_FILTER_LINEAR = 2, | ||
730 | SVGA3D_TEX_FILTER_ANISOTROPIC = 3, | ||
731 | SVGA3D_TEX_FILTER_FLATCUBIC = 4, // Deprecated, not implemented | ||
732 | SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, // Deprecated, not implemented | ||
733 | SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, // Not currently implemented | ||
734 | SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, // Not currently implemented | ||
735 | SVGA3D_TEX_FILTER_MAX | ||
736 | } SVGA3dTextureFilter; | ||
737 | |||
738 | typedef enum { | ||
739 | SVGA3D_TEX_TRANSFORM_OFF = 0, | ||
740 | SVGA3D_TEX_TRANSFORM_S = (1 << 0), | ||
741 | SVGA3D_TEX_TRANSFORM_T = (1 << 1), | ||
742 | SVGA3D_TEX_TRANSFORM_R = (1 << 2), | ||
743 | SVGA3D_TEX_TRANSFORM_Q = (1 << 3), | ||
744 | SVGA3D_TEX_PROJECTED = (1 << 15), | ||
745 | } SVGA3dTexTransformFlags; | ||
746 | |||
747 | typedef enum { | ||
748 | SVGA3D_TEXCOORD_GEN_OFF = 0, | ||
749 | SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1, | ||
750 | SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2, | ||
751 | SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3, | ||
752 | SVGA3D_TEXCOORD_GEN_SPHERE = 4, | ||
753 | SVGA3D_TEXCOORD_GEN_MAX | ||
754 | } SVGA3dTextureCoordGen; | ||
755 | |||
756 | /* | ||
757 | * Texture argument constants for texture combiner | ||
758 | */ | ||
759 | typedef enum { | ||
760 | SVGA3D_TA_INVALID = 0, | ||
761 | SVGA3D_TA_CONSTANT = 1, | ||
762 | SVGA3D_TA_PREVIOUS = 2, | ||
763 | SVGA3D_TA_DIFFUSE = 3, | ||
764 | SVGA3D_TA_TEXTURE = 4, | ||
765 | SVGA3D_TA_SPECULAR = 5, | ||
766 | SVGA3D_TA_MAX | ||
767 | } SVGA3dTextureArgData; | ||
768 | |||
769 | #define SVGA3D_TM_MASK_LEN 4 | ||
770 | |||
771 | /* Modifiers for texture argument constants defined above. */ | ||
772 | typedef enum { | ||
773 | SVGA3D_TM_NONE = 0, | ||
774 | SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN), | ||
775 | SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN), | ||
776 | } SVGA3dTextureArgModifier; | ||
777 | |||
778 | #define SVGA3D_INVALID_ID ((uint32)-1) | ||
779 | #define SVGA3D_MAX_CLIP_PLANES 6 | ||
780 | |||
781 | /* | ||
782 | * This is the limit to the number of fixed-function texture | ||
783 | * transforms and texture coordinates we can support. It does *not* | ||
784 | * correspond to the number of texture image units (samplers) we | ||
785 | * support! | ||
786 | */ | ||
787 | #define SVGA3D_MAX_TEXTURE_COORDS 8 | ||
788 | |||
789 | /* | ||
790 | * Vertex declarations | ||
791 | * | ||
792 | * Notes: | ||
793 | * | ||
794 | * SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you | ||
795 | * draw with any POSITIONT vertex arrays, the programmable vertex | ||
796 | * pipeline will be implicitly disabled. Drawing will take place as if | ||
797 | * no vertex shader was bound. | ||
798 | */ | ||
799 | |||
800 | typedef enum { | ||
801 | SVGA3D_DECLUSAGE_POSITION = 0, | ||
802 | SVGA3D_DECLUSAGE_BLENDWEIGHT, // 1 | ||
803 | SVGA3D_DECLUSAGE_BLENDINDICES, // 2 | ||
804 | SVGA3D_DECLUSAGE_NORMAL, // 3 | ||
805 | SVGA3D_DECLUSAGE_PSIZE, // 4 | ||
806 | SVGA3D_DECLUSAGE_TEXCOORD, // 5 | ||
807 | SVGA3D_DECLUSAGE_TANGENT, // 6 | ||
808 | SVGA3D_DECLUSAGE_BINORMAL, // 7 | ||
809 | SVGA3D_DECLUSAGE_TESSFACTOR, // 8 | ||
810 | SVGA3D_DECLUSAGE_POSITIONT, // 9 | ||
811 | SVGA3D_DECLUSAGE_COLOR, // 10 | ||
812 | SVGA3D_DECLUSAGE_FOG, // 11 | ||
813 | SVGA3D_DECLUSAGE_DEPTH, // 12 | ||
814 | SVGA3D_DECLUSAGE_SAMPLE, // 13 | ||
815 | SVGA3D_DECLUSAGE_MAX | ||
816 | } SVGA3dDeclUsage; | ||
817 | |||
818 | typedef enum { | ||
819 | SVGA3D_DECLMETHOD_DEFAULT = 0, | ||
820 | SVGA3D_DECLMETHOD_PARTIALU, | ||
821 | SVGA3D_DECLMETHOD_PARTIALV, | ||
822 | SVGA3D_DECLMETHOD_CROSSUV, // Normal | ||
823 | SVGA3D_DECLMETHOD_UV, | ||
824 | SVGA3D_DECLMETHOD_LOOKUP, // Lookup a displacement map | ||
825 | SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, // Lookup a pre-sampled displacement map | ||
826 | } SVGA3dDeclMethod; | ||
827 | |||
828 | typedef enum { | ||
829 | SVGA3D_DECLTYPE_FLOAT1 = 0, | ||
830 | SVGA3D_DECLTYPE_FLOAT2 = 1, | ||
831 | SVGA3D_DECLTYPE_FLOAT3 = 2, | ||
832 | SVGA3D_DECLTYPE_FLOAT4 = 3, | ||
833 | SVGA3D_DECLTYPE_D3DCOLOR = 4, | ||
834 | SVGA3D_DECLTYPE_UBYTE4 = 5, | ||
835 | SVGA3D_DECLTYPE_SHORT2 = 6, | ||
836 | SVGA3D_DECLTYPE_SHORT4 = 7, | ||
837 | SVGA3D_DECLTYPE_UBYTE4N = 8, | ||
838 | SVGA3D_DECLTYPE_SHORT2N = 9, | ||
839 | SVGA3D_DECLTYPE_SHORT4N = 10, | ||
840 | SVGA3D_DECLTYPE_USHORT2N = 11, | ||
841 | SVGA3D_DECLTYPE_USHORT4N = 12, | ||
842 | SVGA3D_DECLTYPE_UDEC3 = 13, | ||
843 | SVGA3D_DECLTYPE_DEC3N = 14, | ||
844 | SVGA3D_DECLTYPE_FLOAT16_2 = 15, | ||
845 | SVGA3D_DECLTYPE_FLOAT16_4 = 16, | ||
846 | SVGA3D_DECLTYPE_MAX, | ||
847 | } SVGA3dDeclType; | ||
848 | |||
849 | /* | ||
850 | * This structure is used for the divisor for geometry instancing; | ||
851 | * it's a direct translation of the Direct3D equivalent. | ||
852 | */ | ||
853 | typedef union { | ||
854 | struct { | ||
855 | /* | ||
856 | * For index data, this number represents the number of instances to draw. | ||
857 | * For instance data, this number represents the number of | ||
858 | * instances/vertex in this stream | ||
859 | */ | ||
860 | uint32 count : 30; | ||
861 | |||
862 | /* | ||
863 | * This is 1 if this is supposed to be the data that is repeated for | ||
864 | * every instance. | ||
865 | */ | ||
866 | uint32 indexedData : 1; | ||
867 | |||
868 | /* | ||
869 | * This is 1 if this is supposed to be the per-instance data. | ||
870 | */ | ||
871 | uint32 instanceData : 1; | ||
872 | }; | ||
873 | |||
874 | uint32 value; | ||
875 | } SVGA3dVertexDivisor; | ||
876 | |||
877 | typedef enum { | ||
878 | SVGA3D_PRIMITIVE_INVALID = 0, | ||
879 | SVGA3D_PRIMITIVE_TRIANGLELIST = 1, | ||
880 | SVGA3D_PRIMITIVE_POINTLIST = 2, | ||
881 | SVGA3D_PRIMITIVE_LINELIST = 3, | ||
882 | SVGA3D_PRIMITIVE_LINESTRIP = 4, | ||
883 | SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5, | ||
884 | SVGA3D_PRIMITIVE_TRIANGLEFAN = 6, | ||
885 | SVGA3D_PRIMITIVE_MAX | ||
886 | } SVGA3dPrimitiveType; | ||
887 | |||
888 | typedef enum { | ||
889 | SVGA3D_COORDINATE_INVALID = 0, | ||
890 | SVGA3D_COORDINATE_LEFTHANDED = 1, | ||
891 | SVGA3D_COORDINATE_RIGHTHANDED = 2, | ||
892 | SVGA3D_COORDINATE_MAX | ||
893 | } SVGA3dCoordinateType; | ||
894 | |||
895 | typedef enum { | ||
896 | SVGA3D_TRANSFORM_INVALID = 0, | ||
897 | SVGA3D_TRANSFORM_WORLD = 1, | ||
898 | SVGA3D_TRANSFORM_VIEW = 2, | ||
899 | SVGA3D_TRANSFORM_PROJECTION = 3, | ||
900 | SVGA3D_TRANSFORM_TEXTURE0 = 4, | ||
901 | SVGA3D_TRANSFORM_TEXTURE1 = 5, | ||
902 | SVGA3D_TRANSFORM_TEXTURE2 = 6, | ||
903 | SVGA3D_TRANSFORM_TEXTURE3 = 7, | ||
904 | SVGA3D_TRANSFORM_TEXTURE4 = 8, | ||
905 | SVGA3D_TRANSFORM_TEXTURE5 = 9, | ||
906 | SVGA3D_TRANSFORM_TEXTURE6 = 10, | ||
907 | SVGA3D_TRANSFORM_TEXTURE7 = 11, | ||
908 | SVGA3D_TRANSFORM_WORLD1 = 12, | ||
909 | SVGA3D_TRANSFORM_WORLD2 = 13, | ||
910 | SVGA3D_TRANSFORM_WORLD3 = 14, | ||
911 | SVGA3D_TRANSFORM_MAX | ||
912 | } SVGA3dTransformType; | ||
913 | |||
914 | typedef enum { | ||
915 | SVGA3D_LIGHTTYPE_INVALID = 0, | ||
916 | SVGA3D_LIGHTTYPE_POINT = 1, | ||
917 | SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */ | ||
918 | SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */ | ||
919 | SVGA3D_LIGHTTYPE_DIRECTIONAL = 4, | ||
920 | SVGA3D_LIGHTTYPE_MAX | ||
921 | } SVGA3dLightType; | ||
922 | |||
923 | typedef enum { | ||
924 | SVGA3D_CUBEFACE_POSX = 0, | ||
925 | SVGA3D_CUBEFACE_NEGX = 1, | ||
926 | SVGA3D_CUBEFACE_POSY = 2, | ||
927 | SVGA3D_CUBEFACE_NEGY = 3, | ||
928 | SVGA3D_CUBEFACE_POSZ = 4, | ||
929 | SVGA3D_CUBEFACE_NEGZ = 5, | ||
930 | } SVGA3dCubeFace; | ||
931 | |||
932 | typedef enum { | ||
933 | SVGA3D_SHADERTYPE_COMPILED_DX8 = 0, | ||
934 | SVGA3D_SHADERTYPE_VS = 1, | ||
935 | SVGA3D_SHADERTYPE_PS = 2, | ||
936 | SVGA3D_SHADERTYPE_MAX | ||
937 | } SVGA3dShaderType; | ||
938 | |||
939 | typedef enum { | ||
940 | SVGA3D_CONST_TYPE_FLOAT = 0, | ||
941 | SVGA3D_CONST_TYPE_INT = 1, | ||
942 | SVGA3D_CONST_TYPE_BOOL = 2, | ||
943 | } SVGA3dShaderConstType; | ||
944 | |||
945 | #define SVGA3D_MAX_SURFACE_FACES 6 | ||
946 | |||
947 | typedef enum { | ||
948 | SVGA3D_STRETCH_BLT_POINT = 0, | ||
949 | SVGA3D_STRETCH_BLT_LINEAR = 1, | ||
950 | SVGA3D_STRETCH_BLT_MAX | ||
951 | } SVGA3dStretchBltMode; | ||
952 | |||
953 | typedef enum { | ||
954 | SVGA3D_QUERYTYPE_OCCLUSION = 0, | ||
955 | SVGA3D_QUERYTYPE_MAX | ||
956 | } SVGA3dQueryType; | ||
957 | |||
958 | typedef enum { | ||
959 | SVGA3D_QUERYSTATE_PENDING = 0, /* Waiting on the host (set by guest) */ | ||
960 | SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully (set by host) */ | ||
961 | SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully (set by host) */ | ||
962 | SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (For guest use only) */ | ||
963 | } SVGA3dQueryState; | ||
964 | |||
965 | typedef enum { | ||
966 | SVGA3D_WRITE_HOST_VRAM = 1, | ||
967 | SVGA3D_READ_HOST_VRAM = 2, | ||
968 | } SVGA3dTransferType; | ||
969 | |||
970 | /* | ||
971 | * The maximum number vertex arrays we're guaranteed to support in | ||
972 | * SVGA_3D_CMD_DRAWPRIMITIVES. | ||
973 | */ | ||
974 | #define SVGA3D_MAX_VERTEX_ARRAYS 32 | ||
975 | |||
976 | /* | ||
977 | * Identifiers for commands in the command FIFO. | ||
978 | * | ||
979 | * IDs between 1000 and 1039 (inclusive) were used by obsolete versions of | ||
980 | * the SVGA3D protocol and remain reserved; they should not be used in the | ||
981 | * future. | ||
982 | * | ||
983 | * IDs between 1040 and 1999 (inclusive) are available for use by the | ||
984 | * current SVGA3D protocol. | ||
985 | * | ||
986 | * FIFO clients other than SVGA3D should stay below 1000, or at 2000 | ||
987 | * and up. | ||
988 | */ | ||
989 | |||
990 | #define SVGA_3D_CMD_LEGACY_BASE 1000 | ||
991 | #define SVGA_3D_CMD_BASE 1040 | ||
992 | |||
993 | #define SVGA_3D_CMD_SURFACE_DEFINE SVGA_3D_CMD_BASE + 0 | ||
994 | #define SVGA_3D_CMD_SURFACE_DESTROY SVGA_3D_CMD_BASE + 1 | ||
995 | #define SVGA_3D_CMD_SURFACE_COPY SVGA_3D_CMD_BASE + 2 | ||
996 | #define SVGA_3D_CMD_SURFACE_STRETCHBLT SVGA_3D_CMD_BASE + 3 | ||
997 | #define SVGA_3D_CMD_SURFACE_DMA SVGA_3D_CMD_BASE + 4 | ||
998 | #define SVGA_3D_CMD_CONTEXT_DEFINE SVGA_3D_CMD_BASE + 5 | ||
999 | #define SVGA_3D_CMD_CONTEXT_DESTROY SVGA_3D_CMD_BASE + 6 | ||
1000 | #define SVGA_3D_CMD_SETTRANSFORM SVGA_3D_CMD_BASE + 7 | ||
1001 | #define SVGA_3D_CMD_SETZRANGE SVGA_3D_CMD_BASE + 8 | ||
1002 | #define SVGA_3D_CMD_SETRENDERSTATE SVGA_3D_CMD_BASE + 9 | ||
1003 | #define SVGA_3D_CMD_SETRENDERTARGET SVGA_3D_CMD_BASE + 10 | ||
1004 | #define SVGA_3D_CMD_SETTEXTURESTATE SVGA_3D_CMD_BASE + 11 | ||
1005 | #define SVGA_3D_CMD_SETMATERIAL SVGA_3D_CMD_BASE + 12 | ||
1006 | #define SVGA_3D_CMD_SETLIGHTDATA SVGA_3D_CMD_BASE + 13 | ||
1007 | #define SVGA_3D_CMD_SETLIGHTENABLED SVGA_3D_CMD_BASE + 14 | ||
1008 | #define SVGA_3D_CMD_SETVIEWPORT SVGA_3D_CMD_BASE + 15 | ||
1009 | #define SVGA_3D_CMD_SETCLIPPLANE SVGA_3D_CMD_BASE + 16 | ||
1010 | #define SVGA_3D_CMD_CLEAR SVGA_3D_CMD_BASE + 17 | ||
1011 | #define SVGA_3D_CMD_PRESENT SVGA_3D_CMD_BASE + 18 // Deprecated | ||
1012 | #define SVGA_3D_CMD_SHADER_DEFINE SVGA_3D_CMD_BASE + 19 | ||
1013 | #define SVGA_3D_CMD_SHADER_DESTROY SVGA_3D_CMD_BASE + 20 | ||
1014 | #define SVGA_3D_CMD_SET_SHADER SVGA_3D_CMD_BASE + 21 | ||
1015 | #define SVGA_3D_CMD_SET_SHADER_CONST SVGA_3D_CMD_BASE + 22 | ||
1016 | #define SVGA_3D_CMD_DRAW_PRIMITIVES SVGA_3D_CMD_BASE + 23 | ||
1017 | #define SVGA_3D_CMD_SETSCISSORRECT SVGA_3D_CMD_BASE + 24 | ||
1018 | #define SVGA_3D_CMD_BEGIN_QUERY SVGA_3D_CMD_BASE + 25 | ||
1019 | #define SVGA_3D_CMD_END_QUERY SVGA_3D_CMD_BASE + 26 | ||
1020 | #define SVGA_3D_CMD_WAIT_FOR_QUERY SVGA_3D_CMD_BASE + 27 | ||
1021 | #define SVGA_3D_CMD_PRESENT_READBACK SVGA_3D_CMD_BASE + 28 // Deprecated | ||
1022 | #define SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN SVGA_3D_CMD_BASE + 29 | ||
1023 | #define SVGA_3D_CMD_MAX SVGA_3D_CMD_BASE + 30 | ||
1024 | |||
1025 | #define SVGA_3D_CMD_FUTURE_MAX 2000 | ||
1026 | |||
1027 | /* | ||
1028 | * Common substructures used in multiple FIFO commands: | ||
1029 | */ | ||
1030 | |||
1031 | typedef struct { | ||
1032 | union { | ||
1033 | struct { | ||
1034 | uint16 function; // SVGA3dFogFunction | ||
1035 | uint8 type; // SVGA3dFogType | ||
1036 | uint8 base; // SVGA3dFogBase | ||
1037 | }; | ||
1038 | uint32 uintValue; | ||
1039 | }; | ||
1040 | } SVGA3dFogMode; | ||
1041 | |||
1042 | /* | ||
1043 | * Uniquely identify one image (a 1D/2D/3D array) from a surface. This | ||
1044 | * is a surface ID as well as face/mipmap indices. | ||
1045 | */ | ||
1046 | |||
1047 | typedef | ||
1048 | struct SVGA3dSurfaceImageId { | ||
1049 | uint32 sid; | ||
1050 | uint32 face; | ||
1051 | uint32 mipmap; | ||
1052 | } SVGA3dSurfaceImageId; | ||
1053 | |||
1054 | typedef | ||
1055 | struct SVGA3dGuestImage { | ||
1056 | SVGAGuestPtr ptr; | ||
1057 | |||
1058 | /* | ||
1059 | * A note on interpretation of pitch: This value of pitch is the | ||
1060 | * number of bytes between vertically adjacent image | ||
1061 | * blocks. Normally this is the number of bytes between the first | ||
1062 | * pixel of two adjacent scanlines. With compressed textures, | ||
1063 | * however, this may represent the number of bytes between | ||
1064 | * compression blocks rather than between rows of pixels. | ||
1065 | * | ||
1066 | * XXX: Compressed textures currently must be tightly packed in guest memory. | ||
1067 | * | ||
1068 | * If the image is 1-dimensional, pitch is ignored. | ||
1069 | * | ||
1070 | * If 'pitch' is zero, the SVGA3D device calculates a pitch value | ||
1071 | * assuming each row of blocks is tightly packed. | ||
1072 | */ | ||
1073 | uint32 pitch; | ||
1074 | } SVGA3dGuestImage; | ||
1075 | |||
1076 | |||
1077 | /* | ||
1078 | * FIFO command format definitions: | ||
1079 | */ | ||
1080 | |||
1081 | /* | ||
1082 | * The data size header following cmdNum for every 3d command | ||
1083 | */ | ||
1084 | typedef | ||
1085 | struct { | ||
1086 | uint32 id; | ||
1087 | uint32 size; | ||
1088 | } SVGA3dCmdHeader; | ||
1089 | |||
1090 | /* | ||
1091 | * A surface is a hierarchy of host VRAM surfaces: 1D, 2D, or 3D, with | ||
1092 | * optional mipmaps and cube faces. | ||
1093 | */ | ||
1094 | |||
1095 | typedef | ||
1096 | struct { | ||
1097 | uint32 width; | ||
1098 | uint32 height; | ||
1099 | uint32 depth; | ||
1100 | } SVGA3dSize; | ||
1101 | |||
1102 | typedef enum { | ||
1103 | SVGA3D_SURFACE_CUBEMAP = (1 << 0), | ||
1104 | SVGA3D_SURFACE_HINT_STATIC = (1 << 1), | ||
1105 | SVGA3D_SURFACE_HINT_DYNAMIC = (1 << 2), | ||
1106 | SVGA3D_SURFACE_HINT_INDEXBUFFER = (1 << 3), | ||
1107 | SVGA3D_SURFACE_HINT_VERTEXBUFFER = (1 << 4), | ||
1108 | SVGA3D_SURFACE_HINT_TEXTURE = (1 << 5), | ||
1109 | SVGA3D_SURFACE_HINT_RENDERTARGET = (1 << 6), | ||
1110 | SVGA3D_SURFACE_HINT_DEPTHSTENCIL = (1 << 7), | ||
1111 | SVGA3D_SURFACE_HINT_WRITEONLY = (1 << 8), | ||
1112 | } SVGA3dSurfaceFlags; | ||
1113 | |||
1114 | typedef | ||
1115 | struct { | ||
1116 | uint32 numMipLevels; | ||
1117 | } SVGA3dSurfaceFace; | ||
1118 | |||
1119 | typedef | ||
1120 | struct { | ||
1121 | uint32 sid; | ||
1122 | SVGA3dSurfaceFlags surfaceFlags; | ||
1123 | SVGA3dSurfaceFormat format; | ||
1124 | SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES]; | ||
1125 | /* | ||
1126 | * Followed by an SVGA3dSize structure for each mip level in each face. | ||
1127 | * | ||
1128 | * A note on surface sizes: Sizes are always specified in pixels, | ||
1129 | * even if the true surface size is not a multiple of the minimum | ||
1130 | * block size of the surface's format. For example, a 3x3x1 DXT1 | ||
1131 | * compressed texture would actually be stored as a 4x4x1 image in | ||
1132 | * memory. | ||
1133 | */ | ||
1134 | } SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */ | ||
1135 | |||
1136 | typedef | ||
1137 | struct { | ||
1138 | uint32 sid; | ||
1139 | } SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */ | ||
1140 | |||
1141 | typedef | ||
1142 | struct { | ||
1143 | uint32 cid; | ||
1144 | } SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */ | ||
1145 | |||
1146 | typedef | ||
1147 | struct { | ||
1148 | uint32 cid; | ||
1149 | } SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */ | ||
1150 | |||
1151 | typedef | ||
1152 | struct { | ||
1153 | uint32 cid; | ||
1154 | SVGA3dClearFlag clearFlag; | ||
1155 | uint32 color; | ||
1156 | float depth; | ||
1157 | uint32 stencil; | ||
1158 | /* Followed by variable number of SVGA3dRect structures */ | ||
1159 | } SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */ | ||
1160 | |||
1161 | typedef | ||
1162 | struct SVGA3dCopyRect { | ||
1163 | uint32 x; | ||
1164 | uint32 y; | ||
1165 | uint32 w; | ||
1166 | uint32 h; | ||
1167 | uint32 srcx; | ||
1168 | uint32 srcy; | ||
1169 | } SVGA3dCopyRect; | ||
1170 | |||
1171 | typedef | ||
1172 | struct SVGA3dCopyBox { | ||
1173 | uint32 x; | ||
1174 | uint32 y; | ||
1175 | uint32 z; | ||
1176 | uint32 w; | ||
1177 | uint32 h; | ||
1178 | uint32 d; | ||
1179 | uint32 srcx; | ||
1180 | uint32 srcy; | ||
1181 | uint32 srcz; | ||
1182 | } SVGA3dCopyBox; | ||
1183 | |||
1184 | typedef | ||
1185 | struct { | ||
1186 | uint32 x; | ||
1187 | uint32 y; | ||
1188 | uint32 w; | ||
1189 | uint32 h; | ||
1190 | } SVGA3dRect; | ||
1191 | |||
1192 | typedef | ||
1193 | struct { | ||
1194 | uint32 x; | ||
1195 | uint32 y; | ||
1196 | uint32 z; | ||
1197 | uint32 w; | ||
1198 | uint32 h; | ||
1199 | uint32 d; | ||
1200 | } SVGA3dBox; | ||
1201 | |||
1202 | typedef | ||
1203 | struct { | ||
1204 | uint32 x; | ||
1205 | uint32 y; | ||
1206 | uint32 z; | ||
1207 | } SVGA3dPoint; | ||
1208 | |||
1209 | typedef | ||
1210 | struct { | ||
1211 | SVGA3dLightType type; | ||
1212 | SVGA3dBool inWorldSpace; | ||
1213 | float diffuse[4]; | ||
1214 | float specular[4]; | ||
1215 | float ambient[4]; | ||
1216 | float position[4]; | ||
1217 | float direction[4]; | ||
1218 | float range; | ||
1219 | float falloff; | ||
1220 | float attenuation0; | ||
1221 | float attenuation1; | ||
1222 | float attenuation2; | ||
1223 | float theta; | ||
1224 | float phi; | ||
1225 | } SVGA3dLightData; | ||
1226 | |||
1227 | typedef | ||
1228 | struct { | ||
1229 | uint32 sid; | ||
1230 | /* Followed by variable number of SVGA3dCopyRect structures */ | ||
1231 | } SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */ | ||
1232 | |||
1233 | typedef | ||
1234 | struct { | ||
1235 | SVGA3dRenderStateName state; | ||
1236 | union { | ||
1237 | uint32 uintValue; | ||
1238 | float floatValue; | ||
1239 | }; | ||
1240 | } SVGA3dRenderState; | ||
1241 | |||
1242 | typedef | ||
1243 | struct { | ||
1244 | uint32 cid; | ||
1245 | /* Followed by variable number of SVGA3dRenderState structures */ | ||
1246 | } SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */ | ||
1247 | |||
1248 | typedef | ||
1249 | struct { | ||
1250 | uint32 cid; | ||
1251 | SVGA3dRenderTargetType type; | ||
1252 | SVGA3dSurfaceImageId target; | ||
1253 | } SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */ | ||
1254 | |||
1255 | typedef | ||
1256 | struct { | ||
1257 | SVGA3dSurfaceImageId src; | ||
1258 | SVGA3dSurfaceImageId dest; | ||
1259 | /* Followed by variable number of SVGA3dCopyBox structures */ | ||
1260 | } SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */ | ||
1261 | |||
1262 | typedef | ||
1263 | struct { | ||
1264 | SVGA3dSurfaceImageId src; | ||
1265 | SVGA3dSurfaceImageId dest; | ||
1266 | SVGA3dBox boxSrc; | ||
1267 | SVGA3dBox boxDest; | ||
1268 | SVGA3dStretchBltMode mode; | ||
1269 | } SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */ | ||
1270 | |||
1271 | typedef | ||
1272 | struct { | ||
1273 | /* | ||
1274 | * If the discard flag is present in a surface DMA operation, the host may | ||
1275 | * discard the contents of the current mipmap level and face of the target | ||
1276 | * surface before applying the surface DMA contents. | ||
1277 | */ | ||
1278 | uint32 discard : 1; | ||
1279 | |||
1280 | /* | ||
1281 | * If the unsynchronized flag is present, the host may perform this upload | ||
1282 | * without syncing to pending reads on this surface. | ||
1283 | */ | ||
1284 | uint32 unsynchronized : 1; | ||
1285 | |||
1286 | /* | ||
1287 | * Guests *MUST* set the reserved bits to 0 before submitting the command | ||
1288 | * suffix as future flags may occupy these bits. | ||
1289 | */ | ||
1290 | uint32 reserved : 30; | ||
1291 | } SVGA3dSurfaceDMAFlags; | ||
1292 | |||
1293 | typedef | ||
1294 | struct { | ||
1295 | SVGA3dGuestImage guest; | ||
1296 | SVGA3dSurfaceImageId host; | ||
1297 | SVGA3dTransferType transfer; | ||
1298 | /* | ||
1299 | * Followed by variable number of SVGA3dCopyBox structures. For consistency | ||
1300 | * in all clipping logic and coordinate translation, we define the | ||
1301 | * "source" in each copyBox as the guest image and the | ||
1302 | * "destination" as the host image, regardless of transfer | ||
1303 | * direction. | ||
1304 | * | ||
1305 | * For efficiency, the SVGA3D device is free to copy more data than | ||
1306 | * specified. For example, it may round copy boxes outwards such | ||
1307 | * that they lie on particular alignment boundaries. | ||
1308 | */ | ||
1309 | } SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */ | ||
1310 | |||
1311 | /* | ||
1312 | * SVGA3dCmdSurfaceDMASuffix -- | ||
1313 | * | ||
1314 | * This is a command suffix that will appear after a SurfaceDMA command in | ||
1315 | * the FIFO. It contains some extra information that hosts may use to | ||
1316 | * optimize performance or protect the guest. This suffix exists to preserve | ||
1317 | * backwards compatibility while also allowing for new functionality to be | ||
1318 | * implemented. | ||
1319 | */ | ||
1320 | |||
1321 | typedef | ||
1322 | struct { | ||
1323 | uint32 suffixSize; | ||
1324 | |||
1325 | /* | ||
1326 | * The maximum offset is used to determine the maximum offset from the | ||
1327 | * guestPtr base address that will be accessed or written to during this | ||
1328 | * surfaceDMA. If the suffix is supported, the host will respect this | ||
1329 | * boundary while performing surface DMAs. | ||
1330 | * | ||
1331 | * Defaults to MAX_UINT32 | ||
1332 | */ | ||
1333 | uint32 maximumOffset; | ||
1334 | |||
1335 | /* | ||
1336 | * A set of flags that describes optimizations that the host may perform | ||
1337 | * while performing this surface DMA operation. The guest should never rely | ||
1338 | * on behaviour that is different when these flags are set for correctness. | ||
1339 | * | ||
1340 | * Defaults to 0 | ||
1341 | */ | ||
1342 | SVGA3dSurfaceDMAFlags flags; | ||
1343 | } SVGA3dCmdSurfaceDMASuffix; | ||
1344 | |||
1345 | /* | ||
1346 | * SVGA_3D_CMD_DRAW_PRIMITIVES -- | ||
1347 | * | ||
1348 | * This command is the SVGA3D device's generic drawing entry point. | ||
1349 | * It can draw multiple ranges of primitives, optionally using an | ||
1350 | * index buffer, using an arbitrary collection of vertex buffers. | ||
1351 | * | ||
1352 | * Each SVGA3dVertexDecl defines a distinct vertex array to bind | ||
1353 | * during this draw call. The declarations specify which surface | ||
1354 | * the vertex data lives in, what that vertex data is used for, | ||
1355 | * and how to interpret it. | ||
1356 | * | ||
1357 | * Each SVGA3dPrimitiveRange defines a collection of primitives | ||
1358 | * to render using the same vertex arrays. An index buffer is | ||
1359 | * optional. | ||
1360 | */ | ||
1361 | |||
1362 | typedef | ||
1363 | struct { | ||
1364 | /* | ||
1365 | * A range hint is an optional specification for the range of indices | ||
1366 | * in an SVGA3dArray that will be used. If 'last' is zero, it is assumed | ||
1367 | * that the entire array will be used. | ||
1368 | * | ||
1369 | * These are only hints. The SVGA3D device may use them for | ||
1370 | * performance optimization if possible, but it's also allowed to | ||
1371 | * ignore these values. | ||
1372 | */ | ||
1373 | uint32 first; | ||
1374 | uint32 last; | ||
1375 | } SVGA3dArrayRangeHint; | ||
1376 | |||
1377 | typedef | ||
1378 | struct { | ||
1379 | /* | ||
1380 | * Define the origin and shape of a vertex or index array. Both | ||
1381 | * 'offset' and 'stride' are in bytes. The provided surface will be | ||
1382 | * reinterpreted as a flat array of bytes in the same format used | ||
1383 | * by surface DMA operations. To avoid unnecessary conversions, the | ||
1384 | * surface should be created with the SVGA3D_BUFFER format. | ||
1385 | * | ||
1386 | * Index 0 in the array starts 'offset' bytes into the surface. | ||
1387 | * Index 1 begins at byte 'offset + stride', etc. Array indices may | ||
1388 | * not be negative. | ||
1389 | */ | ||
1390 | uint32 surfaceId; | ||
1391 | uint32 offset; | ||
1392 | uint32 stride; | ||
1393 | } SVGA3dArray; | ||
1394 | |||
1395 | typedef | ||
1396 | struct { | ||
1397 | /* | ||
1398 | * Describe a vertex array's data type, and define how it is to be | ||
1399 | * used by the fixed function pipeline or the vertex shader. It | ||
1400 | * isn't useful to have two VertexDecls with the same | ||
1401 | * VertexArrayIdentity in one draw call. | ||
1402 | */ | ||
1403 | SVGA3dDeclType type; | ||
1404 | SVGA3dDeclMethod method; | ||
1405 | SVGA3dDeclUsage usage; | ||
1406 | uint32 usageIndex; | ||
1407 | } SVGA3dVertexArrayIdentity; | ||
1408 | |||
1409 | typedef | ||
1410 | struct { | ||
1411 | SVGA3dVertexArrayIdentity identity; | ||
1412 | SVGA3dArray array; | ||
1413 | SVGA3dArrayRangeHint rangeHint; | ||
1414 | } SVGA3dVertexDecl; | ||
1415 | |||
1416 | typedef | ||
1417 | struct { | ||
1418 | /* | ||
1419 | * Define a group of primitives to render, from sequential indices. | ||
1420 | * | ||
1421 | * The value of 'primitiveType' and 'primitiveCount' imply the | ||
1422 | * total number of vertices that will be rendered. | ||
1423 | */ | ||
1424 | SVGA3dPrimitiveType primType; | ||
1425 | uint32 primitiveCount; | ||
1426 | |||
1427 | /* | ||
1428 | * Optional index buffer. If indexArray.surfaceId is | ||
1429 | * SVGA3D_INVALID_ID, we render without an index buffer. Rendering | ||
1430 | * without an index buffer is identical to rendering with an index | ||
1431 | * buffer containing the sequence [0, 1, 2, 3, ...]. | ||
1432 | * | ||
1433 | * If an index buffer is in use, indexWidth specifies the width in | ||
1434 | * bytes of each index value. It must be less than or equal to | ||
1435 | * indexArray.stride. | ||
1436 | * | ||
1437 | * (Currently, the SVGA3D device requires index buffers to be tightly | ||
1438 | * packed. In other words, indexWidth == indexArray.stride) | ||
1439 | */ | ||
1440 | SVGA3dArray indexArray; | ||
1441 | uint32 indexWidth; | ||
1442 | |||
1443 | /* | ||
1444 | * Optional index bias. This number is added to all indices from | ||
1445 | * indexArray before they are used as vertex array indices. This | ||
1446 | * can be used in multiple ways: | ||
1447 | * | ||
1448 | * - When not using an indexArray, this bias can be used to | ||
1449 | * specify where in the vertex arrays to begin rendering. | ||
1450 | * | ||
1451 | * - A positive number here is equivalent to increasing the | ||
1452 | * offset in each vertex array. | ||
1453 | * | ||
1454 | * - A negative number can be used to render using a small | ||
1455 | * vertex array and an index buffer that contains large | ||
1456 | * values. This may be used by some applications that | ||
1457 | * crop a vertex buffer without modifying their index | ||
1458 | * buffer. | ||
1459 | * | ||
1460 | * Note that rendering with a negative bias value may be slower and | ||
1461 | * use more memory than rendering with a positive or zero bias. | ||
1462 | */ | ||
1463 | int32 indexBias; | ||
1464 | } SVGA3dPrimitiveRange; | ||
1465 | |||
1466 | typedef | ||
1467 | struct { | ||
1468 | uint32 cid; | ||
1469 | uint32 numVertexDecls; | ||
1470 | uint32 numRanges; | ||
1471 | |||
1472 | /* | ||
1473 | * There are two variable size arrays after the | ||
1474 | * SVGA3dCmdDrawPrimitives structure. In order, | ||
1475 | * they are: | ||
1476 | * | ||
1477 | * 1. SVGA3dVertexDecl, quantity 'numVertexDecls' | ||
1478 | * 2. SVGA3dPrimitiveRange, quantity 'numRanges' | ||
1479 | * 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains | ||
1480 | * the frequency divisor for this the corresponding vertex decl) | ||
1481 | */ | ||
1482 | } SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */ | ||
1483 | |||
1484 | typedef | ||
1485 | struct { | ||
1486 | uint32 stage; | ||
1487 | SVGA3dTextureStateName name; | ||
1488 | union { | ||
1489 | uint32 value; | ||
1490 | float floatValue; | ||
1491 | }; | ||
1492 | } SVGA3dTextureState; | ||
1493 | |||
1494 | typedef | ||
1495 | struct { | ||
1496 | uint32 cid; | ||
1497 | /* Followed by variable number of SVGA3dTextureState structures */ | ||
1498 | } SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */ | ||
1499 | |||
1500 | typedef | ||
1501 | struct { | ||
1502 | uint32 cid; | ||
1503 | SVGA3dTransformType type; | ||
1504 | float matrix[16]; | ||
1505 | } SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */ | ||
1506 | |||
1507 | typedef | ||
1508 | struct { | ||
1509 | float min; | ||
1510 | float max; | ||
1511 | } SVGA3dZRange; | ||
1512 | |||
1513 | typedef | ||
1514 | struct { | ||
1515 | uint32 cid; | ||
1516 | SVGA3dZRange zRange; | ||
1517 | } SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */ | ||
1518 | |||
1519 | typedef | ||
1520 | struct { | ||
1521 | float diffuse[4]; | ||
1522 | float ambient[4]; | ||
1523 | float specular[4]; | ||
1524 | float emissive[4]; | ||
1525 | float shininess; | ||
1526 | } SVGA3dMaterial; | ||
1527 | |||
1528 | typedef | ||
1529 | struct { | ||
1530 | uint32 cid; | ||
1531 | SVGA3dFace face; | ||
1532 | SVGA3dMaterial material; | ||
1533 | } SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */ | ||
1534 | |||
1535 | typedef | ||
1536 | struct { | ||
1537 | uint32 cid; | ||
1538 | uint32 index; | ||
1539 | SVGA3dLightData data; | ||
1540 | } SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */ | ||
1541 | |||
1542 | typedef | ||
1543 | struct { | ||
1544 | uint32 cid; | ||
1545 | uint32 index; | ||
1546 | uint32 enabled; | ||
1547 | } SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */ | ||
1548 | |||
1549 | typedef | ||
1550 | struct { | ||
1551 | uint32 cid; | ||
1552 | SVGA3dRect rect; | ||
1553 | } SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */ | ||
1554 | |||
1555 | typedef | ||
1556 | struct { | ||
1557 | uint32 cid; | ||
1558 | SVGA3dRect rect; | ||
1559 | } SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */ | ||
1560 | |||
1561 | typedef | ||
1562 | struct { | ||
1563 | uint32 cid; | ||
1564 | uint32 index; | ||
1565 | float plane[4]; | ||
1566 | } SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */ | ||
1567 | |||
1568 | typedef | ||
1569 | struct { | ||
1570 | uint32 cid; | ||
1571 | uint32 shid; | ||
1572 | SVGA3dShaderType type; | ||
1573 | /* Followed by variable number of DWORDs for shader bycode */ | ||
1574 | } SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */ | ||
1575 | |||
1576 | typedef | ||
1577 | struct { | ||
1578 | uint32 cid; | ||
1579 | uint32 shid; | ||
1580 | SVGA3dShaderType type; | ||
1581 | } SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */ | ||
1582 | |||
1583 | typedef | ||
1584 | struct { | ||
1585 | uint32 cid; | ||
1586 | uint32 reg; /* register number */ | ||
1587 | SVGA3dShaderType type; | ||
1588 | SVGA3dShaderConstType ctype; | ||
1589 | uint32 values[4]; | ||
1590 | } SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */ | ||
1591 | |||
1592 | typedef | ||
1593 | struct { | ||
1594 | uint32 cid; | ||
1595 | SVGA3dShaderType type; | ||
1596 | uint32 shid; | ||
1597 | } SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */ | ||
1598 | |||
1599 | typedef | ||
1600 | struct { | ||
1601 | uint32 cid; | ||
1602 | SVGA3dQueryType type; | ||
1603 | } SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */ | ||
1604 | |||
1605 | typedef | ||
1606 | struct { | ||
1607 | uint32 cid; | ||
1608 | SVGA3dQueryType type; | ||
1609 | SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */ | ||
1610 | } SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */ | ||
1611 | |||
1612 | typedef | ||
1613 | struct { | ||
1614 | uint32 cid; /* Same parameters passed to END_QUERY */ | ||
1615 | SVGA3dQueryType type; | ||
1616 | SVGAGuestPtr guestResult; | ||
1617 | } SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */ | ||
1618 | |||
1619 | typedef | ||
1620 | struct { | ||
1621 | uint32 totalSize; /* Set by guest before query is ended. */ | ||
1622 | SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */ | ||
1623 | union { /* Set by host on exit from PENDING state */ | ||
1624 | uint32 result32; | ||
1625 | }; | ||
1626 | } SVGA3dQueryResult; | ||
1627 | |||
1628 | /* | ||
1629 | * SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN -- | ||
1630 | * | ||
1631 | * This is a blit from an SVGA3D surface to a Screen Object. Just | ||
1632 | * like GMR-to-screen blits, this blit may be directed at a | ||
1633 | * specific screen or to the virtual coordinate space. | ||
1634 | * | ||
1635 | * The blit copies from a rectangular region of an SVGA3D surface | ||
1636 | * image to a rectangular region of a screen or screens. | ||
1637 | * | ||
1638 | * This command takes an optional variable-length list of clipping | ||
1639 | * rectangles after the body of the command. If no rectangles are | ||
1640 | * specified, there is no clipping region. The entire destRect is | ||
1641 | * drawn to. If one or more rectangles are included, they describe | ||
1642 | * a clipping region. The clip rectangle coordinates are measured | ||
1643 | * relative to the top-left corner of destRect. | ||
1644 | * | ||
1645 | * This clipping region serves multiple purposes: | ||
1646 | * | ||
1647 | * - It can be used to perform an irregularly shaped blit more | ||
1648 | * efficiently than by issuing many separate blit commands. | ||
1649 | * | ||
1650 | * - It is equivalent to allowing blits with non-integer | ||
1651 | * source coordinates. You could blit just one half-pixel | ||
1652 | * of a source, for example, by specifying a larger | ||
1653 | * destination rectangle than you need, then removing | ||
1654 | * part of it using a clip rectangle. | ||
1655 | * | ||
1656 | * Availability: | ||
1657 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1658 | * | ||
1659 | * Limitations: | ||
1660 | * | ||
1661 | * - Currently, no backend supports blits from a mipmap or face | ||
1662 | * other than the first one. | ||
1663 | */ | ||
1664 | |||
1665 | typedef | ||
1666 | struct { | ||
1667 | SVGA3dSurfaceImageId srcImage; | ||
1668 | SVGASignedRect srcRect; | ||
1669 | uint32 destScreenId; /* Screen ID or SVGA_ID_INVALID for virt. coords */ | ||
1670 | SVGASignedRect destRect; /* Supports scaling if src/rest different size */ | ||
1671 | /* Clipping: zero or more SVGASignedRects follow */ | ||
1672 | } SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */ | ||
1673 | |||
1674 | |||
1675 | /* | ||
1676 | * Capability query index. | ||
1677 | * | ||
1678 | * Notes: | ||
1679 | * | ||
1680 | * 1. SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of | ||
1681 | * fixed-function texture units available. Each of these units | ||
1682 | * work in both FFP and Shader modes, and they support texture | ||
1683 | * transforms and texture coordinates. The host may have additional | ||
1684 | * texture image units that are only usable with shaders. | ||
1685 | * | ||
1686 | * 2. The BUFFER_FORMAT capabilities are deprecated, and they always | ||
1687 | * return TRUE. Even on physical hardware that does not support | ||
1688 | * these formats natively, the SVGA3D device will provide an emulation | ||
1689 | * which should be invisible to the guest OS. | ||
1690 | * | ||
1691 | * In general, the SVGA3D device should support any operation on | ||
1692 | * any surface format, it just may perform some of these | ||
1693 | * operations in software depending on the capabilities of the | ||
1694 | * available physical hardware. | ||
1695 | * | ||
1696 | * XXX: In the future, we will add capabilities that describe in | ||
1697 | * detail what formats are supported in hardware for what kinds | ||
1698 | * of operations. | ||
1699 | */ | ||
1700 | |||
1701 | typedef enum { | ||
1702 | SVGA3D_DEVCAP_3D = 0, | ||
1703 | SVGA3D_DEVCAP_MAX_LIGHTS = 1, | ||
1704 | SVGA3D_DEVCAP_MAX_TEXTURES = 2, /* See note (1) */ | ||
1705 | SVGA3D_DEVCAP_MAX_CLIP_PLANES = 3, | ||
1706 | SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = 4, | ||
1707 | SVGA3D_DEVCAP_VERTEX_SHADER = 5, | ||
1708 | SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = 6, | ||
1709 | SVGA3D_DEVCAP_FRAGMENT_SHADER = 7, | ||
1710 | SVGA3D_DEVCAP_MAX_RENDER_TARGETS = 8, | ||
1711 | SVGA3D_DEVCAP_S23E8_TEXTURES = 9, | ||
1712 | SVGA3D_DEVCAP_S10E5_TEXTURES = 10, | ||
1713 | SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = 11, | ||
1714 | SVGA3D_DEVCAP_D16_BUFFER_FORMAT = 12, /* See note (2) */ | ||
1715 | SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = 13, /* See note (2) */ | ||
1716 | SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = 14, /* See note (2) */ | ||
1717 | SVGA3D_DEVCAP_QUERY_TYPES = 15, | ||
1718 | SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = 16, | ||
1719 | SVGA3D_DEVCAP_MAX_POINT_SIZE = 17, | ||
1720 | SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = 18, | ||
1721 | SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = 19, | ||
1722 | SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = 20, | ||
1723 | SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = 21, | ||
1724 | SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = 22, | ||
1725 | SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = 23, | ||
1726 | SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = 24, | ||
1727 | SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = 25, | ||
1728 | SVGA3D_DEVCAP_MAX_VERTEX_INDEX = 26, | ||
1729 | SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = 27, | ||
1730 | SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = 28, | ||
1731 | SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = 29, | ||
1732 | SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = 30, | ||
1733 | SVGA3D_DEVCAP_TEXTURE_OPS = 31, | ||
1734 | SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = 32, | ||
1735 | SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = 33, | ||
1736 | SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = 34, | ||
1737 | SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = 35, | ||
1738 | SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = 36, | ||
1739 | SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = 37, | ||
1740 | SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = 38, | ||
1741 | SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = 39, | ||
1742 | SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = 40, | ||
1743 | SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = 41, | ||
1744 | SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = 42, | ||
1745 | SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = 43, | ||
1746 | SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = 44, | ||
1747 | SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = 45, | ||
1748 | SVGA3D_DEVCAP_SURFACEFMT_DXT1 = 46, | ||
1749 | SVGA3D_DEVCAP_SURFACEFMT_DXT2 = 47, | ||
1750 | SVGA3D_DEVCAP_SURFACEFMT_DXT3 = 48, | ||
1751 | SVGA3D_DEVCAP_SURFACEFMT_DXT4 = 49, | ||
1752 | SVGA3D_DEVCAP_SURFACEFMT_DXT5 = 50, | ||
1753 | SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = 51, | ||
1754 | SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = 52, | ||
1755 | SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = 53, | ||
1756 | SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = 54, | ||
1757 | SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = 55, | ||
1758 | SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = 56, | ||
1759 | SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = 57, | ||
1760 | SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = 58, | ||
1761 | SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = 59, | ||
1762 | SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = 60, | ||
1763 | SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = 61, | ||
1764 | SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = 63, | ||
1765 | |||
1766 | /* | ||
1767 | * Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color | ||
1768 | * render targets. This does no include the depth or stencil targets. | ||
1769 | */ | ||
1770 | SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = 64, | ||
1771 | |||
1772 | SVGA3D_DEVCAP_SURFACEFMT_V16U16 = 65, | ||
1773 | SVGA3D_DEVCAP_SURFACEFMT_G16R16 = 66, | ||
1774 | SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = 67, | ||
1775 | SVGA3D_DEVCAP_SURFACEFMT_UYVY = 68, | ||
1776 | SVGA3D_DEVCAP_SURFACEFMT_YUY2 = 69, | ||
1777 | |||
1778 | /* | ||
1779 | * Don't add new caps into the previous section; the values in this | ||
1780 | * enumeration must not change. You can put new values right before | ||
1781 | * SVGA3D_DEVCAP_MAX. | ||
1782 | */ | ||
1783 | SVGA3D_DEVCAP_MAX /* This must be the last index. */ | ||
1784 | } SVGA3dDevCapIndex; | ||
1785 | |||
1786 | typedef union { | ||
1787 | Bool b; | ||
1788 | uint32 u; | ||
1789 | int32 i; | ||
1790 | float f; | ||
1791 | } SVGA3dDevCapResult; | ||
1792 | |||
1793 | #endif /* _SVGA3D_REG_H_ */ | ||
diff --git a/drivers/gpu/drm/vmwgfx/svga_escape.h b/drivers/gpu/drm/vmwgfx/svga_escape.h new file mode 100644 index 000000000000..7b85e9b8c854 --- /dev/null +++ b/drivers/gpu/drm/vmwgfx/svga_escape.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /********************************************************** | ||
2 | * Copyright 2007-2009 VMware, Inc. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person | ||
5 | * obtaining a copy of this software and associated documentation | ||
6 | * files (the "Software"), to deal in the Software without | ||
7 | * restriction, including without limitation the rights to use, copy, | ||
8 | * modify, merge, publish, distribute, sublicense, and/or sell copies | ||
9 | * of the Software, and to permit persons to whom the Software is | ||
10 | * furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be | ||
13 | * included in all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
22 | * SOFTWARE. | ||
23 | * | ||
24 | **********************************************************/ | ||
25 | |||
26 | /* | ||
27 | * svga_escape.h -- | ||
28 | * | ||
29 | * Definitions for our own (vendor-specific) SVGA Escape commands. | ||
30 | */ | ||
31 | |||
32 | #ifndef _SVGA_ESCAPE_H_ | ||
33 | #define _SVGA_ESCAPE_H_ | ||
34 | |||
35 | |||
36 | /* | ||
37 | * Namespace IDs for the escape command | ||
38 | */ | ||
39 | |||
40 | #define SVGA_ESCAPE_NSID_VMWARE 0x00000000 | ||
41 | #define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF | ||
42 | |||
43 | |||
44 | /* | ||
45 | * Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to | ||
46 | * the first DWORD of escape data (after the nsID and size). As a | ||
47 | * guideline we're using the high word and low word as a major and | ||
48 | * minor command number, respectively. | ||
49 | * | ||
50 | * Major command number allocation: | ||
51 | * | ||
52 | * 0000: Reserved | ||
53 | * 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h) | ||
54 | * 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h) | ||
55 | * 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h) | ||
56 | */ | ||
57 | |||
58 | #define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000 | ||
59 | |||
60 | |||
61 | /* | ||
62 | * SVGA Hint commands. | ||
63 | * | ||
64 | * These escapes let the SVGA driver provide optional information to | ||
65 | * he host about the state of the guest or guest applications. The | ||
66 | * host can use these hints to make user interface or performance | ||
67 | * decisions. | ||
68 | * | ||
69 | * Notes: | ||
70 | * | ||
71 | * - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests | ||
72 | * that use the SVGA Screen Object extension. Instead of sending | ||
73 | * this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your | ||
74 | * Screen Object. | ||
75 | */ | ||
76 | |||
77 | #define SVGA_ESCAPE_VMWARE_HINT 0x00030000 | ||
78 | #define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 // Deprecated | ||
79 | |||
80 | typedef | ||
81 | struct { | ||
82 | uint32 command; | ||
83 | uint32 fullscreen; | ||
84 | struct { | ||
85 | int32 x, y; | ||
86 | } monitorPosition; | ||
87 | } SVGAEscapeHintFullscreen; | ||
88 | |||
89 | #endif /* _SVGA_ESCAPE_H_ */ | ||
diff --git a/drivers/gpu/drm/vmwgfx/svga_overlay.h b/drivers/gpu/drm/vmwgfx/svga_overlay.h new file mode 100644 index 000000000000..f753d73c14b4 --- /dev/null +++ b/drivers/gpu/drm/vmwgfx/svga_overlay.h | |||
@@ -0,0 +1,201 @@ | |||
1 | /********************************************************** | ||
2 | * Copyright 2007-2009 VMware, Inc. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person | ||
5 | * obtaining a copy of this software and associated documentation | ||
6 | * files (the "Software"), to deal in the Software without | ||
7 | * restriction, including without limitation the rights to use, copy, | ||
8 | * modify, merge, publish, distribute, sublicense, and/or sell copies | ||
9 | * of the Software, and to permit persons to whom the Software is | ||
10 | * furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be | ||
13 | * included in all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
22 | * SOFTWARE. | ||
23 | * | ||
24 | **********************************************************/ | ||
25 | |||
26 | /* | ||
27 | * svga_overlay.h -- | ||
28 | * | ||
29 | * Definitions for video-overlay support. | ||
30 | */ | ||
31 | |||
32 | #ifndef _SVGA_OVERLAY_H_ | ||
33 | #define _SVGA_OVERLAY_H_ | ||
34 | |||
35 | #include "svga_reg.h" | ||
36 | |||
37 | /* | ||
38 | * Video formats we support | ||
39 | */ | ||
40 | |||
41 | #define VMWARE_FOURCC_YV12 0x32315659 // 'Y' 'V' '1' '2' | ||
42 | #define VMWARE_FOURCC_YUY2 0x32595559 // 'Y' 'U' 'Y' '2' | ||
43 | #define VMWARE_FOURCC_UYVY 0x59565955 // 'U' 'Y' 'V' 'Y' | ||
44 | |||
45 | typedef enum { | ||
46 | SVGA_OVERLAY_FORMAT_INVALID = 0, | ||
47 | SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12, | ||
48 | SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2, | ||
49 | SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY, | ||
50 | } SVGAOverlayFormat; | ||
51 | |||
52 | #define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff | ||
53 | |||
54 | #define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000 | ||
55 | |||
56 | #define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001 | ||
57 | /* FIFO escape layout: | ||
58 | * Type, Stream Id, (Register Id, Value) pairs */ | ||
59 | |||
60 | #define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002 | ||
61 | /* FIFO escape layout: | ||
62 | * Type, Stream Id */ | ||
63 | |||
64 | typedef | ||
65 | struct SVGAEscapeVideoSetRegs { | ||
66 | struct { | ||
67 | uint32 cmdType; | ||
68 | uint32 streamId; | ||
69 | } header; | ||
70 | |||
71 | // May include zero or more items. | ||
72 | struct { | ||
73 | uint32 registerId; | ||
74 | uint32 value; | ||
75 | } items[1]; | ||
76 | } SVGAEscapeVideoSetRegs; | ||
77 | |||
78 | typedef | ||
79 | struct SVGAEscapeVideoFlush { | ||
80 | uint32 cmdType; | ||
81 | uint32 streamId; | ||
82 | } SVGAEscapeVideoFlush; | ||
83 | |||
84 | |||
85 | /* | ||
86 | * Struct definitions for the video overlay commands built on | ||
87 | * SVGAFifoCmdEscape. | ||
88 | */ | ||
89 | typedef | ||
90 | struct { | ||
91 | uint32 command; | ||
92 | uint32 overlay; | ||
93 | } SVGAFifoEscapeCmdVideoBase; | ||
94 | |||
95 | typedef | ||
96 | struct { | ||
97 | SVGAFifoEscapeCmdVideoBase videoCmd; | ||
98 | } SVGAFifoEscapeCmdVideoFlush; | ||
99 | |||
100 | typedef | ||
101 | struct { | ||
102 | SVGAFifoEscapeCmdVideoBase videoCmd; | ||
103 | struct { | ||
104 | uint32 regId; | ||
105 | uint32 value; | ||
106 | } items[1]; | ||
107 | } SVGAFifoEscapeCmdVideoSetRegs; | ||
108 | |||
109 | typedef | ||
110 | struct { | ||
111 | SVGAFifoEscapeCmdVideoBase videoCmd; | ||
112 | struct { | ||
113 | uint32 regId; | ||
114 | uint32 value; | ||
115 | } items[SVGA_VIDEO_NUM_REGS]; | ||
116 | } SVGAFifoEscapeCmdVideoSetAllRegs; | ||
117 | |||
118 | |||
119 | /* | ||
120 | *---------------------------------------------------------------------- | ||
121 | * | ||
122 | * VMwareVideoGetAttributes -- | ||
123 | * | ||
124 | * Computes the size, pitches and offsets for YUV frames. | ||
125 | * | ||
126 | * Results: | ||
127 | * TRUE on success; otherwise FALSE on failure. | ||
128 | * | ||
129 | * Side effects: | ||
130 | * Pitches and offsets for the given YUV frame are put in 'pitches' | ||
131 | * and 'offsets' respectively. They are both optional though. | ||
132 | * | ||
133 | *---------------------------------------------------------------------- | ||
134 | */ | ||
135 | |||
136 | static inline bool | ||
137 | VMwareVideoGetAttributes(const SVGAOverlayFormat format, // IN | ||
138 | uint32 *width, // IN / OUT | ||
139 | uint32 *height, // IN / OUT | ||
140 | uint32 *size, // OUT | ||
141 | uint32 *pitches, // OUT (optional) | ||
142 | uint32 *offsets) // OUT (optional) | ||
143 | { | ||
144 | int tmp; | ||
145 | |||
146 | *width = (*width + 1) & ~1; | ||
147 | |||
148 | if (offsets) { | ||
149 | offsets[0] = 0; | ||
150 | } | ||
151 | |||
152 | switch (format) { | ||
153 | case VMWARE_FOURCC_YV12: | ||
154 | *height = (*height + 1) & ~1; | ||
155 | *size = (*width + 3) & ~3; | ||
156 | |||
157 | if (pitches) { | ||
158 | pitches[0] = *size; | ||
159 | } | ||
160 | |||
161 | *size *= *height; | ||
162 | |||
163 | if (offsets) { | ||
164 | offsets[1] = *size; | ||
165 | } | ||
166 | |||
167 | tmp = ((*width >> 1) + 3) & ~3; | ||
168 | |||
169 | if (pitches) { | ||
170 | pitches[1] = pitches[2] = tmp; | ||
171 | } | ||
172 | |||
173 | tmp *= (*height >> 1); | ||
174 | *size += tmp; | ||
175 | |||
176 | if (offsets) { | ||
177 | offsets[2] = *size; | ||
178 | } | ||
179 | |||
180 | *size += tmp; | ||
181 | break; | ||
182 | |||
183 | case VMWARE_FOURCC_YUY2: | ||
184 | case VMWARE_FOURCC_UYVY: | ||
185 | *size = *width * 2; | ||
186 | |||
187 | if (pitches) { | ||
188 | pitches[0] = *size; | ||
189 | } | ||
190 | |||
191 | *size *= *height; | ||
192 | break; | ||
193 | |||
194 | default: | ||
195 | return false; | ||
196 | } | ||
197 | |||
198 | return true; | ||
199 | } | ||
200 | |||
201 | #endif // _SVGA_OVERLAY_H_ | ||
diff --git a/drivers/gpu/drm/vmwgfx/svga_reg.h b/drivers/gpu/drm/vmwgfx/svga_reg.h new file mode 100644 index 000000000000..1b96c2ec07dd --- /dev/null +++ b/drivers/gpu/drm/vmwgfx/svga_reg.h | |||
@@ -0,0 +1,1346 @@ | |||
1 | /********************************************************** | ||
2 | * Copyright 1998-2009 VMware, Inc. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person | ||
5 | * obtaining a copy of this software and associated documentation | ||
6 | * files (the "Software"), to deal in the Software without | ||
7 | * restriction, including without limitation the rights to use, copy, | ||
8 | * modify, merge, publish, distribute, sublicense, and/or sell copies | ||
9 | * of the Software, and to permit persons to whom the Software is | ||
10 | * furnished to do so, subject to the following conditions: | ||
11 | * | ||
12 | * The above copyright notice and this permission notice shall be | ||
13 | * included in all copies or substantial portions of the Software. | ||
14 | * | ||
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | ||
16 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | ||
17 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | ||
18 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | ||
19 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | ||
20 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | ||
21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | ||
22 | * SOFTWARE. | ||
23 | * | ||
24 | **********************************************************/ | ||
25 | |||
26 | /* | ||
27 | * svga_reg.h -- | ||
28 | * | ||
29 | * Virtual hardware definitions for the VMware SVGA II device. | ||
30 | */ | ||
31 | |||
32 | #ifndef _SVGA_REG_H_ | ||
33 | #define _SVGA_REG_H_ | ||
34 | |||
35 | /* | ||
36 | * PCI device IDs. | ||
37 | */ | ||
38 | #define PCI_VENDOR_ID_VMWARE 0x15AD | ||
39 | #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405 | ||
40 | |||
41 | /* | ||
42 | * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned | ||
43 | * cursor bypass mode. This is still supported, but no new guest | ||
44 | * drivers should use it. | ||
45 | */ | ||
46 | #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */ | ||
47 | #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */ | ||
48 | #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */ | ||
49 | #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */ | ||
50 | |||
51 | /* | ||
52 | * The maximum framebuffer size that can traced for e.g. guests in VESA mode. | ||
53 | * The changeMap in the monitor is proportional to this number. Therefore, we'd | ||
54 | * like to keep it as small as possible to reduce monitor overhead (using | ||
55 | * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over | ||
56 | * 4k!). | ||
57 | * | ||
58 | * NB: For compatibility reasons, this value must be greater than 0xff0000. | ||
59 | * See bug 335072. | ||
60 | */ | ||
61 | #define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000 | ||
62 | |||
63 | #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8 | ||
64 | #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH) | ||
65 | #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS) | ||
66 | |||
67 | #define SVGA_MAGIC 0x900000UL | ||
68 | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) | ||
69 | |||
70 | /* Version 2 let the address of the frame buffer be unsigned on Win32 */ | ||
71 | #define SVGA_VERSION_2 2 | ||
72 | #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2) | ||
73 | |||
74 | /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so | ||
75 | PALETTE_BASE has moved */ | ||
76 | #define SVGA_VERSION_1 1 | ||
77 | #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1) | ||
78 | |||
79 | /* Version 0 is the initial version */ | ||
80 | #define SVGA_VERSION_0 0 | ||
81 | #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0) | ||
82 | |||
83 | /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */ | ||
84 | #define SVGA_ID_INVALID 0xFFFFFFFF | ||
85 | |||
86 | /* Port offsets, relative to BAR0 */ | ||
87 | #define SVGA_INDEX_PORT 0x0 | ||
88 | #define SVGA_VALUE_PORT 0x1 | ||
89 | #define SVGA_BIOS_PORT 0x2 | ||
90 | #define SVGA_IRQSTATUS_PORT 0x8 | ||
91 | |||
92 | /* | ||
93 | * Interrupt source flags for IRQSTATUS_PORT and IRQMASK. | ||
94 | * | ||
95 | * Interrupts are only supported when the | ||
96 | * SVGA_CAP_IRQMASK capability is present. | ||
97 | */ | ||
98 | #define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */ | ||
99 | #define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */ | ||
100 | #define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */ | ||
101 | |||
102 | /* | ||
103 | * Registers | ||
104 | */ | ||
105 | |||
106 | enum { | ||
107 | SVGA_REG_ID = 0, | ||
108 | SVGA_REG_ENABLE = 1, | ||
109 | SVGA_REG_WIDTH = 2, | ||
110 | SVGA_REG_HEIGHT = 3, | ||
111 | SVGA_REG_MAX_WIDTH = 4, | ||
112 | SVGA_REG_MAX_HEIGHT = 5, | ||
113 | SVGA_REG_DEPTH = 6, | ||
114 | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ | ||
115 | SVGA_REG_PSEUDOCOLOR = 8, | ||
116 | SVGA_REG_RED_MASK = 9, | ||
117 | SVGA_REG_GREEN_MASK = 10, | ||
118 | SVGA_REG_BLUE_MASK = 11, | ||
119 | SVGA_REG_BYTES_PER_LINE = 12, | ||
120 | SVGA_REG_FB_START = 13, /* (Deprecated) */ | ||
121 | SVGA_REG_FB_OFFSET = 14, | ||
122 | SVGA_REG_VRAM_SIZE = 15, | ||
123 | SVGA_REG_FB_SIZE = 16, | ||
124 | |||
125 | /* ID 0 implementation only had the above registers, then the palette */ | ||
126 | |||
127 | SVGA_REG_CAPABILITIES = 17, | ||
128 | SVGA_REG_MEM_START = 18, /* (Deprecated) */ | ||
129 | SVGA_REG_MEM_SIZE = 19, | ||
130 | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ | ||
131 | SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */ | ||
132 | SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */ | ||
133 | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ | ||
134 | SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */ | ||
135 | SVGA_REG_CURSOR_X = 25, /* (Deprecated) */ | ||
136 | SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */ | ||
137 | SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */ | ||
138 | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */ | ||
139 | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ | ||
140 | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ | ||
141 | SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */ | ||
142 | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ | ||
143 | SVGA_REG_IRQMASK = 33, /* Interrupt mask */ | ||
144 | |||
145 | /* Legacy multi-monitor support */ | ||
146 | SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */ | ||
147 | SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */ | ||
148 | SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */ | ||
149 | SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */ | ||
150 | SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */ | ||
151 | SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */ | ||
152 | SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */ | ||
153 | |||
154 | /* See "Guest memory regions" below. */ | ||
155 | SVGA_REG_GMR_ID = 41, | ||
156 | SVGA_REG_GMR_DESCRIPTOR = 42, | ||
157 | SVGA_REG_GMR_MAX_IDS = 43, | ||
158 | SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44, | ||
159 | |||
160 | SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ | ||
161 | SVGA_REG_TOP = 46, /* Must be 1 more than the last register */ | ||
162 | |||
163 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | ||
164 | /* Next 768 (== 256*3) registers exist for colormap */ | ||
165 | |||
166 | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS | ||
167 | /* Base of scratch registers */ | ||
168 | /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage: | ||
169 | First 4 are reserved for VESA BIOS Extension; any remaining are for | ||
170 | the use of the current SVGA driver. */ | ||
171 | }; | ||
172 | |||
173 | |||
174 | /* | ||
175 | * Guest memory regions (GMRs): | ||
176 | * | ||
177 | * This is a new memory mapping feature available in SVGA devices | ||
178 | * which have the SVGA_CAP_GMR bit set. Previously, there were two | ||
179 | * fixed memory regions available with which to share data between the | ||
180 | * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs | ||
181 | * are our name for an extensible way of providing arbitrary DMA | ||
182 | * buffers for use between the driver and the SVGA device. They are a | ||
183 | * new alternative to framebuffer memory, usable for both 2D and 3D | ||
184 | * graphics operations. | ||
185 | * | ||
186 | * Since GMR mapping must be done synchronously with guest CPU | ||
187 | * execution, we use a new pair of SVGA registers: | ||
188 | * | ||
189 | * SVGA_REG_GMR_ID -- | ||
190 | * | ||
191 | * Read/write. | ||
192 | * This register holds the 32-bit ID (a small positive integer) | ||
193 | * of a GMR to create, delete, or redefine. Writing this register | ||
194 | * has no side-effects. | ||
195 | * | ||
196 | * SVGA_REG_GMR_DESCRIPTOR -- | ||
197 | * | ||
198 | * Write-only. | ||
199 | * Writing this register will create, delete, or redefine the GMR | ||
200 | * specified by the above ID register. If this register is zero, | ||
201 | * the GMR is deleted. Any pointers into this GMR (including those | ||
202 | * currently being processed by FIFO commands) will be | ||
203 | * synchronously invalidated. | ||
204 | * | ||
205 | * If this register is nonzero, it must be the physical page | ||
206 | * number (PPN) of a data structure which describes the physical | ||
207 | * layout of the memory region this GMR should describe. The | ||
208 | * descriptor structure will be read synchronously by the SVGA | ||
209 | * device when this register is written. The descriptor need not | ||
210 | * remain allocated for the lifetime of the GMR. | ||
211 | * | ||
212 | * The guest driver should write SVGA_REG_GMR_ID first, then | ||
213 | * SVGA_REG_GMR_DESCRIPTOR. | ||
214 | * | ||
215 | * SVGA_REG_GMR_MAX_IDS -- | ||
216 | * | ||
217 | * Read-only. | ||
218 | * The SVGA device may choose to support a maximum number of | ||
219 | * user-defined GMR IDs. This register holds the number of supported | ||
220 | * IDs. (The maximum supported ID plus 1) | ||
221 | * | ||
222 | * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH -- | ||
223 | * | ||
224 | * Read-only. | ||
225 | * The SVGA device may choose to put a limit on the total number | ||
226 | * of SVGAGuestMemDescriptor structures it will read when defining | ||
227 | * a single GMR. | ||
228 | * | ||
229 | * The descriptor structure is an array of SVGAGuestMemDescriptor | ||
230 | * structures. Each structure may do one of three things: | ||
231 | * | ||
232 | * - Terminate the GMR descriptor list. | ||
233 | * (ppn==0, numPages==0) | ||
234 | * | ||
235 | * - Add a PPN or range of PPNs to the GMR's virtual address space. | ||
236 | * (ppn != 0, numPages != 0) | ||
237 | * | ||
238 | * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to | ||
239 | * support multi-page GMR descriptor tables without forcing the | ||
240 | * driver to allocate physically contiguous memory. | ||
241 | * (ppn != 0, numPages == 0) | ||
242 | * | ||
243 | * Note that each physical page of SVGAGuestMemDescriptor structures | ||
244 | * can describe at least 2MB of guest memory. If the driver needs to | ||
245 | * use more than one page of descriptor structures, it must use one of | ||
246 | * its SVGAGuestMemDescriptors to point to an additional page. The | ||
247 | * device will never automatically cross a page boundary. | ||
248 | * | ||
249 | * Once the driver has described a GMR, it is immediately available | ||
250 | * for use via any FIFO command that uses an SVGAGuestPtr structure. | ||
251 | * These pointers include a GMR identifier plus an offset into that | ||
252 | * GMR. | ||
253 | * | ||
254 | * The driver must check the SVGA_CAP_GMR bit before using the GMR | ||
255 | * registers. | ||
256 | */ | ||
257 | |||
258 | /* | ||
259 | * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer | ||
260 | * memory as well. In the future, these IDs could even be used to | ||
261 | * allow legacy memory regions to be redefined by the guest as GMRs. | ||
262 | * | ||
263 | * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA | ||
264 | * is being phased out. Please try to use user-defined GMRs whenever | ||
265 | * possible. | ||
266 | */ | ||
267 | #define SVGA_GMR_NULL ((uint32) -1) | ||
268 | #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) // Guest Framebuffer (GFB) | ||
269 | |||
270 | typedef | ||
271 | struct SVGAGuestMemDescriptor { | ||
272 | uint32 ppn; | ||
273 | uint32 numPages; | ||
274 | } SVGAGuestMemDescriptor; | ||
275 | |||
276 | typedef | ||
277 | struct SVGAGuestPtr { | ||
278 | uint32 gmrId; | ||
279 | uint32 offset; | ||
280 | } SVGAGuestPtr; | ||
281 | |||
282 | |||
283 | /* | ||
284 | * SVGAGMRImageFormat -- | ||
285 | * | ||
286 | * This is a packed representation of the source 2D image format | ||
287 | * for a GMR-to-screen blit. Currently it is defined as an encoding | ||
288 | * of the screen's color depth and bits-per-pixel, however, 16 bits | ||
289 | * are reserved for future use to identify other encodings (such as | ||
290 | * RGBA or higher-precision images). | ||
291 | * | ||
292 | * Currently supported formats: | ||
293 | * | ||
294 | * bpp depth Format Name | ||
295 | * --- ----- ----------- | ||
296 | * 32 24 32-bit BGRX | ||
297 | * 24 24 24-bit BGR | ||
298 | * 16 16 RGB 5-6-5 | ||
299 | * 16 15 RGB 5-5-5 | ||
300 | * | ||
301 | */ | ||
302 | |||
303 | typedef | ||
304 | struct SVGAGMRImageFormat { | ||
305 | union { | ||
306 | struct { | ||
307 | uint32 bitsPerPixel : 8; | ||
308 | uint32 colorDepth : 8; | ||
309 | uint32 reserved : 16; // Must be zero | ||
310 | }; | ||
311 | |||
312 | uint32 value; | ||
313 | }; | ||
314 | } SVGAGMRImageFormat; | ||
315 | |||
316 | /* | ||
317 | * SVGAColorBGRX -- | ||
318 | * | ||
319 | * A 24-bit color format (BGRX), which does not depend on the | ||
320 | * format of the legacy guest framebuffer (GFB) or the current | ||
321 | * GMRFB state. | ||
322 | */ | ||
323 | |||
324 | typedef | ||
325 | struct SVGAColorBGRX { | ||
326 | union { | ||
327 | struct { | ||
328 | uint32 b : 8; | ||
329 | uint32 g : 8; | ||
330 | uint32 r : 8; | ||
331 | uint32 x : 8; // Unused | ||
332 | }; | ||
333 | |||
334 | uint32 value; | ||
335 | }; | ||
336 | } SVGAColorBGRX; | ||
337 | |||
338 | |||
339 | /* | ||
340 | * SVGASignedRect -- | ||
341 | * SVGASignedPoint -- | ||
342 | * | ||
343 | * Signed rectangle and point primitives. These are used by the new | ||
344 | * 2D primitives for drawing to Screen Objects, which can occupy a | ||
345 | * signed virtual coordinate space. | ||
346 | * | ||
347 | * SVGASignedRect specifies a half-open interval: the (left, top) | ||
348 | * pixel is part of the rectangle, but the (right, bottom) pixel is | ||
349 | * not. | ||
350 | */ | ||
351 | |||
352 | typedef | ||
353 | struct SVGASignedRect { | ||
354 | int32 left; | ||
355 | int32 top; | ||
356 | int32 right; | ||
357 | int32 bottom; | ||
358 | } SVGASignedRect; | ||
359 | |||
360 | typedef | ||
361 | struct SVGASignedPoint { | ||
362 | int32 x; | ||
363 | int32 y; | ||
364 | } SVGASignedPoint; | ||
365 | |||
366 | |||
367 | /* | ||
368 | * Capabilities | ||
369 | * | ||
370 | * Note the holes in the bitfield. Missing bits have been deprecated, | ||
371 | * and must not be reused. Those capabilities will never be reported | ||
372 | * by new versions of the SVGA device. | ||
373 | */ | ||
374 | |||
375 | #define SVGA_CAP_NONE 0x00000000 | ||
376 | #define SVGA_CAP_RECT_COPY 0x00000002 | ||
377 | #define SVGA_CAP_CURSOR 0x00000020 | ||
378 | #define SVGA_CAP_CURSOR_BYPASS 0x00000040 // Legacy (Use Cursor Bypass 3 instead) | ||
379 | #define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 // Legacy (Use Cursor Bypass 3 instead) | ||
380 | #define SVGA_CAP_8BIT_EMULATION 0x00000100 | ||
381 | #define SVGA_CAP_ALPHA_CURSOR 0x00000200 | ||
382 | #define SVGA_CAP_3D 0x00004000 | ||
383 | #define SVGA_CAP_EXTENDED_FIFO 0x00008000 | ||
384 | #define SVGA_CAP_MULTIMON 0x00010000 // Legacy multi-monitor support | ||
385 | #define SVGA_CAP_PITCHLOCK 0x00020000 | ||
386 | #define SVGA_CAP_IRQMASK 0x00040000 | ||
387 | #define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 // Legacy multi-monitor support | ||
388 | #define SVGA_CAP_GMR 0x00100000 | ||
389 | #define SVGA_CAP_TRACES 0x00200000 | ||
390 | |||
391 | |||
392 | /* | ||
393 | * FIFO register indices. | ||
394 | * | ||
395 | * The FIFO is a chunk of device memory mapped into guest physmem. It | ||
396 | * is always treated as 32-bit words. | ||
397 | * | ||
398 | * The guest driver gets to decide how to partition it between | ||
399 | * - FIFO registers (there are always at least 4, specifying where the | ||
400 | * following data area is and how much data it contains; there may be | ||
401 | * more registers following these, depending on the FIFO protocol | ||
402 | * version in use) | ||
403 | * - FIFO data, written by the guest and slurped out by the VMX. | ||
404 | * These indices are 32-bit word offsets into the FIFO. | ||
405 | */ | ||
406 | |||
407 | enum { | ||
408 | /* | ||
409 | * Block 1 (basic registers): The originally defined FIFO registers. | ||
410 | * These exist and are valid for all versions of the FIFO protocol. | ||
411 | */ | ||
412 | |||
413 | SVGA_FIFO_MIN = 0, | ||
414 | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ | ||
415 | SVGA_FIFO_NEXT_CMD, | ||
416 | SVGA_FIFO_STOP, | ||
417 | |||
418 | /* | ||
419 | * Block 2 (extended registers): Mandatory registers for the extended | ||
420 | * FIFO. These exist if the SVGA caps register includes | ||
421 | * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their | ||
422 | * associated capability bit is enabled. | ||
423 | * | ||
424 | * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied | ||
425 | * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE. | ||
426 | * This means that the guest has to test individually (in most cases | ||
427 | * using FIFO caps) for the presence of registers after this; the VMX | ||
428 | * can define "extended FIFO" to mean whatever it wants, and currently | ||
429 | * won't enable it unless there's room for that set and much more. | ||
430 | */ | ||
431 | |||
432 | SVGA_FIFO_CAPABILITIES = 4, | ||
433 | SVGA_FIFO_FLAGS, | ||
434 | // Valid with SVGA_FIFO_CAP_FENCE: | ||
435 | SVGA_FIFO_FENCE, | ||
436 | |||
437 | /* | ||
438 | * Block 3a (optional extended registers): Additional registers for the | ||
439 | * extended FIFO, whose presence isn't actually implied by | ||
440 | * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to | ||
441 | * leave room for them. | ||
442 | * | ||
443 | * These in block 3a, the VMX currently considers mandatory for the | ||
444 | * extended FIFO. | ||
445 | */ | ||
446 | |||
447 | // Valid if exists (i.e. if extended FIFO enabled): | ||
448 | SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */ | ||
449 | // Valid with SVGA_FIFO_CAP_PITCHLOCK: | ||
450 | SVGA_FIFO_PITCHLOCK, | ||
451 | |||
452 | // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: | ||
453 | SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */ | ||
454 | SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */ | ||
455 | SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */ | ||
456 | SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */ | ||
457 | SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */ | ||
458 | |||
459 | // Valid with SVGA_FIFO_CAP_RESERVE: | ||
460 | SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */ | ||
461 | |||
462 | /* | ||
463 | * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT: | ||
464 | * | ||
465 | * By default this is SVGA_ID_INVALID, to indicate that the cursor | ||
466 | * coordinates are specified relative to the virtual root. If this | ||
467 | * is set to a specific screen ID, cursor position is reinterpreted | ||
468 | * as a signed offset relative to that screen's origin. This is the | ||
469 | * only way to place the cursor on a non-rooted screen. | ||
470 | */ | ||
471 | SVGA_FIFO_CURSOR_SCREEN_ID, | ||
472 | |||
473 | /* | ||
474 | * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new | ||
475 | * registers, but this must be done carefully and with judicious use of | ||
476 | * capability bits, since comparisons based on SVGA_FIFO_MIN aren't | ||
477 | * enough to tell you whether the register exists: we've shipped drivers | ||
478 | * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of | ||
479 | * the earlier ones. The actual order of introduction was: | ||
480 | * - PITCHLOCK | ||
481 | * - 3D_CAPS | ||
482 | * - CURSOR_* (cursor bypass 3) | ||
483 | * - RESERVED | ||
484 | * So, code that wants to know whether it can use any of the | ||
485 | * aforementioned registers, or anything else added after PITCHLOCK and | ||
486 | * before 3D_CAPS, needs to reason about something other than | ||
487 | * SVGA_FIFO_MIN. | ||
488 | */ | ||
489 | |||
490 | /* | ||
491 | * 3D caps block space; valid with 3D hardware version >= | ||
492 | * SVGA3D_HWVERSION_WS6_B1. | ||
493 | */ | ||
494 | SVGA_FIFO_3D_CAPS = 32, | ||
495 | SVGA_FIFO_3D_CAPS_LAST = 32 + 255, | ||
496 | |||
497 | /* | ||
498 | * End of VMX's current definition of "extended-FIFO registers". | ||
499 | * Registers before here are always enabled/disabled as a block; either | ||
500 | * the extended FIFO is enabled and includes all preceding registers, or | ||
501 | * it's disabled entirely. | ||
502 | * | ||
503 | * Block 3b (truly optional extended registers): Additional registers for | ||
504 | * the extended FIFO, which the VMX already knows how to enable and | ||
505 | * disable with correct granularity. | ||
506 | * | ||
507 | * Registers after here exist if and only if the guest SVGA driver | ||
508 | * sets SVGA_FIFO_MIN high enough to leave room for them. | ||
509 | */ | ||
510 | |||
511 | // Valid if register exists: | ||
512 | SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */ | ||
513 | SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */ | ||
514 | SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */ | ||
515 | |||
516 | /* | ||
517 | * Always keep this last. This defines the maximum number of | ||
518 | * registers we know about. At power-on, this value is placed in | ||
519 | * the SVGA_REG_MEM_REGS register, and we expect the guest driver | ||
520 | * to allocate this much space in FIFO memory for registers. | ||
521 | */ | ||
522 | SVGA_FIFO_NUM_REGS | ||
523 | }; | ||
524 | |||
525 | |||
526 | /* | ||
527 | * Definition of registers included in extended FIFO support. | ||
528 | * | ||
529 | * The guest SVGA driver gets to allocate the FIFO between registers | ||
530 | * and data. It must always allocate at least 4 registers, but old | ||
531 | * drivers stopped there. | ||
532 | * | ||
533 | * The VMX will enable extended FIFO support if and only if the guest | ||
534 | * left enough room for all registers defined as part of the mandatory | ||
535 | * set for the extended FIFO. | ||
536 | * | ||
537 | * Note that the guest drivers typically allocate the FIFO only at | ||
538 | * initialization time, not at mode switches, so it's likely that the | ||
539 | * number of FIFO registers won't change without a reboot. | ||
540 | * | ||
541 | * All registers less than this value are guaranteed to be present if | ||
542 | * svgaUser->fifo.extended is set. Any later registers must be tested | ||
543 | * individually for compatibility at each use (in the VMX). | ||
544 | * | ||
545 | * This value is used only by the VMX, so it can change without | ||
546 | * affecting driver compatibility; keep it that way? | ||
547 | */ | ||
548 | #define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1) | ||
549 | |||
550 | |||
551 | /* | ||
552 | * FIFO Synchronization Registers | ||
553 | * | ||
554 | * This explains the relationship between the various FIFO | ||
555 | * sync-related registers in IOSpace and in FIFO space. | ||
556 | * | ||
557 | * SVGA_REG_SYNC -- | ||
558 | * | ||
559 | * The SYNC register can be used in two different ways by the guest: | ||
560 | * | ||
561 | * 1. If the guest wishes to fully sync (drain) the FIFO, | ||
562 | * it will write once to SYNC then poll on the BUSY | ||
563 | * register. The FIFO is sync'ed once BUSY is zero. | ||
564 | * | ||
565 | * 2. If the guest wants to asynchronously wake up the host, | ||
566 | * it will write once to SYNC without polling on BUSY. | ||
567 | * Ideally it will do this after some new commands have | ||
568 | * been placed in the FIFO, and after reading a zero | ||
569 | * from SVGA_FIFO_BUSY. | ||
570 | * | ||
571 | * (1) is the original behaviour that SYNC was designed to | ||
572 | * support. Originally, a write to SYNC would implicitly | ||
573 | * trigger a read from BUSY. This causes us to synchronously | ||
574 | * process the FIFO. | ||
575 | * | ||
576 | * This behaviour has since been changed so that writing SYNC | ||
577 | * will *not* implicitly cause a read from BUSY. Instead, it | ||
578 | * makes a channel call which asynchronously wakes up the MKS | ||
579 | * thread. | ||
580 | * | ||
581 | * New guests can use this new behaviour to implement (2) | ||
582 | * efficiently. This lets guests get the host's attention | ||
583 | * without waiting for the MKS to poll, which gives us much | ||
584 | * better CPU utilization on SMP hosts and on UP hosts while | ||
585 | * we're blocked on the host GPU. | ||
586 | * | ||
587 | * Old guests shouldn't notice the behaviour change. SYNC was | ||
588 | * never guaranteed to process the entire FIFO, since it was | ||
589 | * bounded to a particular number of CPU cycles. Old guests will | ||
590 | * still loop on the BUSY register until the FIFO is empty. | ||
591 | * | ||
592 | * Writing to SYNC currently has the following side-effects: | ||
593 | * | ||
594 | * - Sets SVGA_REG_BUSY to TRUE (in the monitor) | ||
595 | * - Asynchronously wakes up the MKS thread for FIFO processing | ||
596 | * - The value written to SYNC is recorded as a "reason", for | ||
597 | * stats purposes. | ||
598 | * | ||
599 | * If SVGA_FIFO_BUSY is available, drivers are advised to only | ||
600 | * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set | ||
601 | * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will | ||
602 | * eventually set SVGA_FIFO_BUSY on its own, but this approach | ||
603 | * lets the driver avoid sending multiple asynchronous wakeup | ||
604 | * messages to the MKS thread. | ||
605 | * | ||
606 | * SVGA_REG_BUSY -- | ||
607 | * | ||
608 | * This register is set to TRUE when SVGA_REG_SYNC is written, | ||
609 | * and it reads as FALSE when the FIFO has been completely | ||
610 | * drained. | ||
611 | * | ||
612 | * Every read from this register causes us to synchronously | ||
613 | * process FIFO commands. There is no guarantee as to how many | ||
614 | * commands each read will process. | ||
615 | * | ||
616 | * CPU time spent processing FIFO commands will be billed to | ||
617 | * the guest. | ||
618 | * | ||
619 | * New drivers should avoid using this register unless they | ||
620 | * need to guarantee that the FIFO is completely drained. It | ||
621 | * is overkill for performing a sync-to-fence. Older drivers | ||
622 | * will use this register for any type of synchronization. | ||
623 | * | ||
624 | * SVGA_FIFO_BUSY -- | ||
625 | * | ||
626 | * This register is a fast way for the guest driver to check | ||
627 | * whether the FIFO is already being processed. It reads and | ||
628 | * writes at normal RAM speeds, with no monitor intervention. | ||
629 | * | ||
630 | * If this register reads as TRUE, the host is guaranteeing that | ||
631 | * any new commands written into the FIFO will be noticed before | ||
632 | * the MKS goes back to sleep. | ||
633 | * | ||
634 | * If this register reads as FALSE, no such guarantee can be | ||
635 | * made. | ||
636 | * | ||
637 | * The guest should use this register to quickly determine | ||
638 | * whether or not it needs to wake up the host. If the guest | ||
639 | * just wrote a command or group of commands that it would like | ||
640 | * the host to begin processing, it should: | ||
641 | * | ||
642 | * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further | ||
643 | * action is necessary. | ||
644 | * | ||
645 | * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest | ||
646 | * code that we've already sent a SYNC to the host and we | ||
647 | * don't need to send a duplicate. | ||
648 | * | ||
649 | * 3. Write a reason to SVGA_REG_SYNC. This will send an | ||
650 | * asynchronous wakeup to the MKS thread. | ||
651 | */ | ||
652 | |||
653 | |||
654 | /* | ||
655 | * FIFO Capabilities | ||
656 | * | ||
657 | * Fence -- Fence register and command are supported | ||
658 | * Accel Front -- Front buffer only commands are supported | ||
659 | * Pitch Lock -- Pitch lock register is supported | ||
660 | * Video -- SVGA Video overlay units are supported | ||
661 | * Escape -- Escape command is supported | ||
662 | * | ||
663 | * XXX: Add longer descriptions for each capability, including a list | ||
664 | * of the new features that each capability provides. | ||
665 | * | ||
666 | * SVGA_FIFO_CAP_SCREEN_OBJECT -- | ||
667 | * | ||
668 | * Provides dynamic multi-screen rendering, for improved Unity and | ||
669 | * multi-monitor modes. With Screen Object, the guest can | ||
670 | * dynamically create and destroy 'screens', which can represent | ||
671 | * Unity windows or virtual monitors. Screen Object also provides | ||
672 | * strong guarantees that DMA operations happen only when | ||
673 | * guest-initiated. Screen Object deprecates the BAR1 guest | ||
674 | * framebuffer (GFB) and all commands that work only with the GFB. | ||
675 | * | ||
676 | * New registers: | ||
677 | * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID | ||
678 | * | ||
679 | * New 2D commands: | ||
680 | * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN, | ||
681 | * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY | ||
682 | * | ||
683 | * New 3D commands: | ||
684 | * BLIT_SURFACE_TO_SCREEN | ||
685 | * | ||
686 | * New guarantees: | ||
687 | * | ||
688 | * - The host will not read or write guest memory, including the GFB, | ||
689 | * except when explicitly initiated by a DMA command. | ||
690 | * | ||
691 | * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK, | ||
692 | * is guaranteed to complete before any subsequent FENCEs. | ||
693 | * | ||
694 | * - All legacy commands which affect a Screen (UPDATE, PRESENT, | ||
695 | * PRESENT_READBACK) as well as new Screen blit commands will | ||
696 | * all behave consistently as blits, and memory will be read | ||
697 | * or written in FIFO order. | ||
698 | * | ||
699 | * For example, if you PRESENT from one SVGA3D surface to multiple | ||
700 | * places on the screen, the data copied will always be from the | ||
701 | * SVGA3D surface at the time the PRESENT was issued in the FIFO. | ||
702 | * This was not necessarily true on devices without Screen Object. | ||
703 | * | ||
704 | * This means that on devices that support Screen Object, the | ||
705 | * PRESENT_READBACK command should not be necessary unless you | ||
706 | * actually want to read back the results of 3D rendering into | ||
707 | * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB | ||
708 | * command provides a strict superset of functionality.) | ||
709 | * | ||
710 | * - When a screen is resized, either using Screen Object commands or | ||
711 | * legacy multimon registers, its contents are preserved. | ||
712 | */ | ||
713 | |||
714 | #define SVGA_FIFO_CAP_NONE 0 | ||
715 | #define SVGA_FIFO_CAP_FENCE (1<<0) | ||
716 | #define SVGA_FIFO_CAP_ACCELFRONT (1<<1) | ||
717 | #define SVGA_FIFO_CAP_PITCHLOCK (1<<2) | ||
718 | #define SVGA_FIFO_CAP_VIDEO (1<<3) | ||
719 | #define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4) | ||
720 | #define SVGA_FIFO_CAP_ESCAPE (1<<5) | ||
721 | #define SVGA_FIFO_CAP_RESERVE (1<<6) | ||
722 | #define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7) | ||
723 | |||
724 | |||
725 | /* | ||
726 | * FIFO Flags | ||
727 | * | ||
728 | * Accel Front -- Driver should use front buffer only commands | ||
729 | */ | ||
730 | |||
731 | #define SVGA_FIFO_FLAG_NONE 0 | ||
732 | #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0) | ||
733 | #define SVGA_FIFO_FLAG_RESERVED (1<<31) // Internal use only | ||
734 | |||
735 | /* | ||
736 | * FIFO reservation sentinel value | ||
737 | */ | ||
738 | |||
739 | #define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff | ||
740 | |||
741 | |||
742 | /* | ||
743 | * Video overlay support | ||
744 | */ | ||
745 | |||
746 | #define SVGA_NUM_OVERLAY_UNITS 32 | ||
747 | |||
748 | |||
749 | /* | ||
750 | * Video capabilities that the guest is currently using | ||
751 | */ | ||
752 | |||
753 | #define SVGA_VIDEO_FLAG_COLORKEY 0x0001 | ||
754 | |||
755 | |||
756 | /* | ||
757 | * Offsets for the video overlay registers | ||
758 | */ | ||
759 | |||
760 | enum { | ||
761 | SVGA_VIDEO_ENABLED = 0, | ||
762 | SVGA_VIDEO_FLAGS, | ||
763 | SVGA_VIDEO_DATA_OFFSET, | ||
764 | SVGA_VIDEO_FORMAT, | ||
765 | SVGA_VIDEO_COLORKEY, | ||
766 | SVGA_VIDEO_SIZE, // Deprecated | ||
767 | SVGA_VIDEO_WIDTH, | ||
768 | SVGA_VIDEO_HEIGHT, | ||
769 | SVGA_VIDEO_SRC_X, | ||
770 | SVGA_VIDEO_SRC_Y, | ||
771 | SVGA_VIDEO_SRC_WIDTH, | ||
772 | SVGA_VIDEO_SRC_HEIGHT, | ||
773 | SVGA_VIDEO_DST_X, // Signed int32 | ||
774 | SVGA_VIDEO_DST_Y, // Signed int32 | ||
775 | SVGA_VIDEO_DST_WIDTH, | ||
776 | SVGA_VIDEO_DST_HEIGHT, | ||
777 | SVGA_VIDEO_PITCH_1, | ||
778 | SVGA_VIDEO_PITCH_2, | ||
779 | SVGA_VIDEO_PITCH_3, | ||
780 | SVGA_VIDEO_DATA_GMRID, // Optional, defaults to SVGA_GMR_FRAMEBUFFER | ||
781 | SVGA_VIDEO_DST_SCREEN_ID, // Optional, defaults to virtual coords (SVGA_ID_INVALID) | ||
782 | SVGA_VIDEO_NUM_REGS | ||
783 | }; | ||
784 | |||
785 | |||
786 | /* | ||
787 | * SVGA Overlay Units | ||
788 | * | ||
789 | * width and height relate to the entire source video frame. | ||
790 | * srcX, srcY, srcWidth and srcHeight represent subset of the source | ||
791 | * video frame to be displayed. | ||
792 | */ | ||
793 | |||
794 | typedef struct SVGAOverlayUnit { | ||
795 | uint32 enabled; | ||
796 | uint32 flags; | ||
797 | uint32 dataOffset; | ||
798 | uint32 format; | ||
799 | uint32 colorKey; | ||
800 | uint32 size; | ||
801 | uint32 width; | ||
802 | uint32 height; | ||
803 | uint32 srcX; | ||
804 | uint32 srcY; | ||
805 | uint32 srcWidth; | ||
806 | uint32 srcHeight; | ||
807 | int32 dstX; | ||
808 | int32 dstY; | ||
809 | uint32 dstWidth; | ||
810 | uint32 dstHeight; | ||
811 | uint32 pitches[3]; | ||
812 | uint32 dataGMRId; | ||
813 | uint32 dstScreenId; | ||
814 | } SVGAOverlayUnit; | ||
815 | |||
816 | |||
817 | /* | ||
818 | * SVGAScreenObject -- | ||
819 | * | ||
820 | * This is a new way to represent a guest's multi-monitor screen or | ||
821 | * Unity window. Screen objects are only supported if the | ||
822 | * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set. | ||
823 | * | ||
824 | * If Screen Objects are supported, they can be used to fully | ||
825 | * replace the functionality provided by the framebuffer registers | ||
826 | * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY. | ||
827 | * | ||
828 | * The screen object is a struct with guaranteed binary | ||
829 | * compatibility. New flags can be added, and the struct may grow, | ||
830 | * but existing fields must retain their meaning. | ||
831 | * | ||
832 | */ | ||
833 | |||
834 | #define SVGA_SCREEN_HAS_ROOT (1 << 0) // Screen is present in the virtual coord space | ||
835 | #define SVGA_SCREEN_IS_PRIMARY (1 << 1) // Guest considers this screen to be 'primary' | ||
836 | #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) // Guest is running a fullscreen app here | ||
837 | |||
838 | typedef | ||
839 | struct SVGAScreenObject { | ||
840 | uint32 structSize; // sizeof(SVGAScreenObject) | ||
841 | uint32 id; | ||
842 | uint32 flags; | ||
843 | struct { | ||
844 | uint32 width; | ||
845 | uint32 height; | ||
846 | } size; | ||
847 | struct { | ||
848 | int32 x; | ||
849 | int32 y; | ||
850 | } root; // Only used if SVGA_SCREEN_HAS_ROOT is set. | ||
851 | } SVGAScreenObject; | ||
852 | |||
853 | |||
854 | /* | ||
855 | * Commands in the command FIFO: | ||
856 | * | ||
857 | * Command IDs defined below are used for the traditional 2D FIFO | ||
858 | * communication (not all commands are available for all versions of the | ||
859 | * SVGA FIFO protocol). | ||
860 | * | ||
861 | * Note the holes in the command ID numbers: These commands have been | ||
862 | * deprecated, and the old IDs must not be reused. | ||
863 | * | ||
864 | * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D | ||
865 | * protocol. | ||
866 | * | ||
867 | * Each command's parameters are described by the comments and | ||
868 | * structs below. | ||
869 | */ | ||
870 | |||
871 | typedef enum { | ||
872 | SVGA_CMD_INVALID_CMD = 0, | ||
873 | SVGA_CMD_UPDATE = 1, | ||
874 | SVGA_CMD_RECT_COPY = 3, | ||
875 | SVGA_CMD_DEFINE_CURSOR = 19, | ||
876 | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22, | ||
877 | SVGA_CMD_UPDATE_VERBOSE = 25, | ||
878 | SVGA_CMD_FRONT_ROP_FILL = 29, | ||
879 | SVGA_CMD_FENCE = 30, | ||
880 | SVGA_CMD_ESCAPE = 33, | ||
881 | SVGA_CMD_DEFINE_SCREEN = 34, | ||
882 | SVGA_CMD_DESTROY_SCREEN = 35, | ||
883 | SVGA_CMD_DEFINE_GMRFB = 36, | ||
884 | SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37, | ||
885 | SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38, | ||
886 | SVGA_CMD_ANNOTATION_FILL = 39, | ||
887 | SVGA_CMD_ANNOTATION_COPY = 40, | ||
888 | SVGA_CMD_MAX | ||
889 | } SVGAFifoCmdId; | ||
890 | |||
891 | #define SVGA_CMD_MAX_ARGS 64 | ||
892 | |||
893 | |||
894 | /* | ||
895 | * SVGA_CMD_UPDATE -- | ||
896 | * | ||
897 | * This is a DMA transfer which copies from the Guest Framebuffer | ||
898 | * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which | ||
899 | * intersect with the provided virtual rectangle. | ||
900 | * | ||
901 | * This command does not support using arbitrary guest memory as a | ||
902 | * data source- it only works with the pre-defined GFB memory. | ||
903 | * This command also does not support signed virtual coordinates. | ||
904 | * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with | ||
905 | * negative root x/y coordinates, the negative portion of those | ||
906 | * screens will not be reachable by this command. | ||
907 | * | ||
908 | * This command is not necessary when using framebuffer | ||
909 | * traces. Traces are automatically enabled if the SVGA FIFO is | ||
910 | * disabled, and you may explicitly enable/disable traces using | ||
911 | * SVGA_REG_TRACES. With traces enabled, any write to the GFB will | ||
912 | * automatically act as if a subsequent SVGA_CMD_UPDATE was issued. | ||
913 | * | ||
914 | * Traces and SVGA_CMD_UPDATE are the only supported ways to render | ||
915 | * pseudocolor screen updates. The newer Screen Object commands | ||
916 | * only support true color formats. | ||
917 | * | ||
918 | * Availability: | ||
919 | * Always available. | ||
920 | */ | ||
921 | |||
922 | typedef | ||
923 | struct { | ||
924 | uint32 x; | ||
925 | uint32 y; | ||
926 | uint32 width; | ||
927 | uint32 height; | ||
928 | } SVGAFifoCmdUpdate; | ||
929 | |||
930 | |||
931 | /* | ||
932 | * SVGA_CMD_RECT_COPY -- | ||
933 | * | ||
934 | * Perform a rectangular DMA transfer from one area of the GFB to | ||
935 | * another, and copy the result to any screens which intersect it. | ||
936 | * | ||
937 | * Availability: | ||
938 | * SVGA_CAP_RECT_COPY | ||
939 | */ | ||
940 | |||
941 | typedef | ||
942 | struct { | ||
943 | uint32 srcX; | ||
944 | uint32 srcY; | ||
945 | uint32 destX; | ||
946 | uint32 destY; | ||
947 | uint32 width; | ||
948 | uint32 height; | ||
949 | } SVGAFifoCmdRectCopy; | ||
950 | |||
951 | |||
952 | /* | ||
953 | * SVGA_CMD_DEFINE_CURSOR -- | ||
954 | * | ||
955 | * Provide a new cursor image, as an AND/XOR mask. | ||
956 | * | ||
957 | * The recommended way to position the cursor overlay is by using | ||
958 | * the SVGA_FIFO_CURSOR_* registers, supported by the | ||
959 | * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. | ||
960 | * | ||
961 | * Availability: | ||
962 | * SVGA_CAP_CURSOR | ||
963 | */ | ||
964 | |||
965 | typedef | ||
966 | struct { | ||
967 | uint32 id; // Reserved, must be zero. | ||
968 | uint32 hotspotX; | ||
969 | uint32 hotspotY; | ||
970 | uint32 width; | ||
971 | uint32 height; | ||
972 | uint32 andMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL | ||
973 | uint32 xorMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL | ||
974 | /* | ||
975 | * Followed by scanline data for AND mask, then XOR mask. | ||
976 | * Each scanline is padded to a 32-bit boundary. | ||
977 | */ | ||
978 | } SVGAFifoCmdDefineCursor; | ||
979 | |||
980 | |||
981 | /* | ||
982 | * SVGA_CMD_DEFINE_ALPHA_CURSOR -- | ||
983 | * | ||
984 | * Provide a new cursor image, in 32-bit BGRA format. | ||
985 | * | ||
986 | * The recommended way to position the cursor overlay is by using | ||
987 | * the SVGA_FIFO_CURSOR_* registers, supported by the | ||
988 | * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability. | ||
989 | * | ||
990 | * Availability: | ||
991 | * SVGA_CAP_ALPHA_CURSOR | ||
992 | */ | ||
993 | |||
994 | typedef | ||
995 | struct { | ||
996 | uint32 id; // Reserved, must be zero. | ||
997 | uint32 hotspotX; | ||
998 | uint32 hotspotY; | ||
999 | uint32 width; | ||
1000 | uint32 height; | ||
1001 | /* Followed by scanline data */ | ||
1002 | } SVGAFifoCmdDefineAlphaCursor; | ||
1003 | |||
1004 | |||
1005 | /* | ||
1006 | * SVGA_CMD_UPDATE_VERBOSE -- | ||
1007 | * | ||
1008 | * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle | ||
1009 | * 'reason' value, an opaque cookie which is used by internal | ||
1010 | * debugging tools. Third party drivers should not use this | ||
1011 | * command. | ||
1012 | * | ||
1013 | * Availability: | ||
1014 | * SVGA_CAP_EXTENDED_FIFO | ||
1015 | */ | ||
1016 | |||
1017 | typedef | ||
1018 | struct { | ||
1019 | uint32 x; | ||
1020 | uint32 y; | ||
1021 | uint32 width; | ||
1022 | uint32 height; | ||
1023 | uint32 reason; | ||
1024 | } SVGAFifoCmdUpdateVerbose; | ||
1025 | |||
1026 | |||
1027 | /* | ||
1028 | * SVGA_CMD_FRONT_ROP_FILL -- | ||
1029 | * | ||
1030 | * This is a hint which tells the SVGA device that the driver has | ||
1031 | * just filled a rectangular region of the GFB with a solid | ||
1032 | * color. Instead of reading these pixels from the GFB, the device | ||
1033 | * can assume that they all equal 'color'. This is primarily used | ||
1034 | * for remote desktop protocols. | ||
1035 | * | ||
1036 | * Availability: | ||
1037 | * SVGA_FIFO_CAP_ACCELFRONT | ||
1038 | */ | ||
1039 | |||
1040 | #define SVGA_ROP_COPY 0x03 | ||
1041 | |||
1042 | typedef | ||
1043 | struct { | ||
1044 | uint32 color; // In the same format as the GFB | ||
1045 | uint32 x; | ||
1046 | uint32 y; | ||
1047 | uint32 width; | ||
1048 | uint32 height; | ||
1049 | uint32 rop; // Must be SVGA_ROP_COPY | ||
1050 | } SVGAFifoCmdFrontRopFill; | ||
1051 | |||
1052 | |||
1053 | /* | ||
1054 | * SVGA_CMD_FENCE -- | ||
1055 | * | ||
1056 | * Insert a synchronization fence. When the SVGA device reaches | ||
1057 | * this command, it will copy the 'fence' value into the | ||
1058 | * SVGA_FIFO_FENCE register. It will also compare the fence against | ||
1059 | * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the | ||
1060 | * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will | ||
1061 | * raise this interrupt. | ||
1062 | * | ||
1063 | * Availability: | ||
1064 | * SVGA_FIFO_FENCE for this command, | ||
1065 | * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL. | ||
1066 | */ | ||
1067 | |||
1068 | typedef | ||
1069 | struct { | ||
1070 | uint32 fence; | ||
1071 | } SVGAFifoCmdFence; | ||
1072 | |||
1073 | |||
1074 | /* | ||
1075 | * SVGA_CMD_ESCAPE -- | ||
1076 | * | ||
1077 | * Send an extended or vendor-specific variable length command. | ||
1078 | * This is used for video overlay, third party plugins, and | ||
1079 | * internal debugging tools. See svga_escape.h | ||
1080 | * | ||
1081 | * Availability: | ||
1082 | * SVGA_FIFO_CAP_ESCAPE | ||
1083 | */ | ||
1084 | |||
1085 | typedef | ||
1086 | struct { | ||
1087 | uint32 nsid; | ||
1088 | uint32 size; | ||
1089 | /* followed by 'size' bytes of data */ | ||
1090 | } SVGAFifoCmdEscape; | ||
1091 | |||
1092 | |||
1093 | /* | ||
1094 | * SVGA_CMD_DEFINE_SCREEN -- | ||
1095 | * | ||
1096 | * Define or redefine an SVGAScreenObject. See the description of | ||
1097 | * SVGAScreenObject above. The video driver is responsible for | ||
1098 | * generating new screen IDs. They should be small positive | ||
1099 | * integers. The virtual device will have an implementation | ||
1100 | * specific upper limit on the number of screen IDs | ||
1101 | * supported. Drivers are responsible for recycling IDs. The first | ||
1102 | * valid ID is zero. | ||
1103 | * | ||
1104 | * - Interaction with other registers: | ||
1105 | * | ||
1106 | * For backwards compatibility, when the GFB mode registers (WIDTH, | ||
1107 | * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device | ||
1108 | * deletes all screens other than screen #0, and redefines screen | ||
1109 | * #0 according to the specified mode. Drivers that use | ||
1110 | * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0. | ||
1111 | * | ||
1112 | * If you use screen objects, do not use the legacy multi-mon | ||
1113 | * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*). | ||
1114 | * | ||
1115 | * Availability: | ||
1116 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1117 | */ | ||
1118 | |||
1119 | typedef | ||
1120 | struct { | ||
1121 | SVGAScreenObject screen; // Variable-length according to version | ||
1122 | } SVGAFifoCmdDefineScreen; | ||
1123 | |||
1124 | |||
1125 | /* | ||
1126 | * SVGA_CMD_DESTROY_SCREEN -- | ||
1127 | * | ||
1128 | * Destroy an SVGAScreenObject. Its ID is immediately available for | ||
1129 | * re-use. | ||
1130 | * | ||
1131 | * Availability: | ||
1132 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1133 | */ | ||
1134 | |||
1135 | typedef | ||
1136 | struct { | ||
1137 | uint32 screenId; | ||
1138 | } SVGAFifoCmdDestroyScreen; | ||
1139 | |||
1140 | |||
1141 | /* | ||
1142 | * SVGA_CMD_DEFINE_GMRFB -- | ||
1143 | * | ||
1144 | * This command sets a piece of SVGA device state called the | ||
1145 | * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a | ||
1146 | * piece of light-weight state which identifies the location and | ||
1147 | * format of an image in guest memory or in BAR1. The GMRFB has | ||
1148 | * an arbitrary size, and it doesn't need to match the geometry | ||
1149 | * of the GFB or any screen object. | ||
1150 | * | ||
1151 | * The GMRFB can be redefined as often as you like. You could | ||
1152 | * always use the same GMRFB, you could redefine it before | ||
1153 | * rendering from a different guest screen, or you could even | ||
1154 | * redefine it before every blit. | ||
1155 | * | ||
1156 | * There are multiple ways to use this command. The simplest way is | ||
1157 | * to use it to move the framebuffer either to elsewhere in the GFB | ||
1158 | * (BAR1) memory region, or to a user-defined GMR. This lets a | ||
1159 | * driver use a framebuffer allocated entirely out of normal system | ||
1160 | * memory, which we encourage. | ||
1161 | * | ||
1162 | * Another way to use this command is to set up a ring buffer of | ||
1163 | * updates in GFB memory. If a driver wants to ensure that no | ||
1164 | * frames are skipped by the SVGA device, it is important that the | ||
1165 | * driver not modify the source data for a blit until the device is | ||
1166 | * done processing the command. One efficient way to accomplish | ||
1167 | * this is to use a ring of small DMA buffers. Each buffer is used | ||
1168 | * for one blit, then we move on to the next buffer in the | ||
1169 | * ring. The FENCE mechanism is used to protect each buffer from | ||
1170 | * re-use until the device is finished with that buffer's | ||
1171 | * corresponding blit. | ||
1172 | * | ||
1173 | * This command does not affect the meaning of SVGA_CMD_UPDATE. | ||
1174 | * UPDATEs always occur from the legacy GFB memory area. This | ||
1175 | * command has no support for pseudocolor GMRFBs. Currently only | ||
1176 | * true-color 15, 16, and 24-bit depths are supported. Future | ||
1177 | * devices may expose capabilities for additional framebuffer | ||
1178 | * formats. | ||
1179 | * | ||
1180 | * The default GMRFB value is undefined. Drivers must always send | ||
1181 | * this command at least once before performing any blit from the | ||
1182 | * GMRFB. | ||
1183 | * | ||
1184 | * Availability: | ||
1185 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1186 | */ | ||
1187 | |||
1188 | typedef | ||
1189 | struct { | ||
1190 | SVGAGuestPtr ptr; | ||
1191 | uint32 bytesPerLine; | ||
1192 | SVGAGMRImageFormat format; | ||
1193 | } SVGAFifoCmdDefineGMRFB; | ||
1194 | |||
1195 | |||
1196 | /* | ||
1197 | * SVGA_CMD_BLIT_GMRFB_TO_SCREEN -- | ||
1198 | * | ||
1199 | * This is a guest-to-host blit. It performs a DMA operation to | ||
1200 | * copy a rectangular region of pixels from the current GMRFB to | ||
1201 | * one or more Screen Objects. | ||
1202 | * | ||
1203 | * The destination coordinate may be specified relative to a | ||
1204 | * screen's origin (if a screen ID is specified) or relative to the | ||
1205 | * virtual coordinate system's origin (if the screen ID is | ||
1206 | * SVGA_ID_INVALID). The actual destination may span zero or more | ||
1207 | * screens, in the case of a virtual destination rect or a rect | ||
1208 | * which extends off the edge of the specified screen. | ||
1209 | * | ||
1210 | * This command writes to the screen's "base layer": the underlying | ||
1211 | * framebuffer which exists below any cursor or video overlays. No | ||
1212 | * action is necessary to explicitly hide or update any overlays | ||
1213 | * which exist on top of the updated region. | ||
1214 | * | ||
1215 | * The SVGA device is guaranteed to finish reading from the GMRFB | ||
1216 | * by the time any subsequent FENCE commands are reached. | ||
1217 | * | ||
1218 | * This command consumes an annotation. See the | ||
1219 | * SVGA_CMD_ANNOTATION_* commands for details. | ||
1220 | * | ||
1221 | * Availability: | ||
1222 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1223 | */ | ||
1224 | |||
1225 | typedef | ||
1226 | struct { | ||
1227 | SVGASignedPoint srcOrigin; | ||
1228 | SVGASignedRect destRect; | ||
1229 | uint32 destScreenId; | ||
1230 | } SVGAFifoCmdBlitGMRFBToScreen; | ||
1231 | |||
1232 | |||
1233 | /* | ||
1234 | * SVGA_CMD_BLIT_SCREEN_TO_GMRFB -- | ||
1235 | * | ||
1236 | * This is a host-to-guest blit. It performs a DMA operation to | ||
1237 | * copy a rectangular region of pixels from a single Screen Object | ||
1238 | * back to the current GMRFB. | ||
1239 | * | ||
1240 | * Usage note: This command should be used rarely. It will | ||
1241 | * typically be inefficient, but it is necessary for some types of | ||
1242 | * synchronization between 3D (GPU) and 2D (CPU) rendering into | ||
1243 | * overlapping areas of a screen. | ||
1244 | * | ||
1245 | * The source coordinate is specified relative to a screen's | ||
1246 | * origin. The provided screen ID must be valid. If any parameters | ||
1247 | * are invalid, the resulting pixel values are undefined. | ||
1248 | * | ||
1249 | * This command reads the screen's "base layer". Overlays like | ||
1250 | * video and cursor are not included, but any data which was sent | ||
1251 | * using a blit-to-screen primitive will be available, no matter | ||
1252 | * whether the data's original source was the GMRFB or the 3D | ||
1253 | * acceleration hardware. | ||
1254 | * | ||
1255 | * Note that our guest-to-host blits and host-to-guest blits aren't | ||
1256 | * symmetric in their current implementation. While the parameters | ||
1257 | * are identical, host-to-guest blits are a lot less featureful. | ||
1258 | * They do not support clipping: If the source parameters don't | ||
1259 | * fully fit within a screen, the blit fails. They must originate | ||
1260 | * from exactly one screen. Virtual coordinates are not directly | ||
1261 | * supported. | ||
1262 | * | ||
1263 | * Host-to-guest blits do support the same set of GMRFB formats | ||
1264 | * offered by guest-to-host blits. | ||
1265 | * | ||
1266 | * The SVGA device is guaranteed to finish writing to the GMRFB by | ||
1267 | * the time any subsequent FENCE commands are reached. | ||
1268 | * | ||
1269 | * Availability: | ||
1270 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1271 | */ | ||
1272 | |||
1273 | typedef | ||
1274 | struct { | ||
1275 | SVGASignedPoint destOrigin; | ||
1276 | SVGASignedRect srcRect; | ||
1277 | uint32 srcScreenId; | ||
1278 | } SVGAFifoCmdBlitScreenToGMRFB; | ||
1279 | |||
1280 | |||
1281 | /* | ||
1282 | * SVGA_CMD_ANNOTATION_FILL -- | ||
1283 | * | ||
1284 | * This is a blit annotation. This command stores a small piece of | ||
1285 | * device state which is consumed by the next blit-to-screen | ||
1286 | * command. The state is only cleared by commands which are | ||
1287 | * specifically documented as consuming an annotation. Other | ||
1288 | * commands (such as ESCAPEs for debugging) may intervene between | ||
1289 | * the annotation and its associated blit. | ||
1290 | * | ||
1291 | * This annotation is a promise about the contents of the next | ||
1292 | * blit: The video driver is guaranteeing that all pixels in that | ||
1293 | * blit will have the same value, specified here as a color in | ||
1294 | * SVGAColorBGRX format. | ||
1295 | * | ||
1296 | * The SVGA device can still render the blit correctly even if it | ||
1297 | * ignores this annotation, but the annotation may allow it to | ||
1298 | * perform the blit more efficiently, for example by ignoring the | ||
1299 | * source data and performing a fill in hardware. | ||
1300 | * | ||
1301 | * This annotation is most important for performance when the | ||
1302 | * user's display is being remoted over a network connection. | ||
1303 | * | ||
1304 | * Availability: | ||
1305 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1306 | */ | ||
1307 | |||
1308 | typedef | ||
1309 | struct { | ||
1310 | SVGAColorBGRX color; | ||
1311 | } SVGAFifoCmdAnnotationFill; | ||
1312 | |||
1313 | |||
1314 | /* | ||
1315 | * SVGA_CMD_ANNOTATION_COPY -- | ||
1316 | * | ||
1317 | * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more | ||
1318 | * information about annotations. | ||
1319 | * | ||
1320 | * This annotation is a promise about the contents of the next | ||
1321 | * blit: The video driver is guaranteeing that all pixels in that | ||
1322 | * blit will have the same value as those which already exist at an | ||
1323 | * identically-sized region on the same or a different screen. | ||
1324 | * | ||
1325 | * Note that the source pixels for the COPY in this annotation are | ||
1326 | * sampled before applying the anqnotation's associated blit. They | ||
1327 | * are allowed to overlap with the blit's destination pixels. | ||
1328 | * | ||
1329 | * The copy source rectangle is specified the same way as the blit | ||
1330 | * destination: it can be a rectangle which spans zero or more | ||
1331 | * screens, specified relative to either a screen or to the virtual | ||
1332 | * coordinate system's origin. If the source rectangle includes | ||
1333 | * pixels which are not from exactly one screen, the results are | ||
1334 | * undefined. | ||
1335 | * | ||
1336 | * Availability: | ||
1337 | * SVGA_FIFO_CAP_SCREEN_OBJECT | ||
1338 | */ | ||
1339 | |||
1340 | typedef | ||
1341 | struct { | ||
1342 | SVGASignedPoint srcOrigin; | ||
1343 | uint32 srcScreenId; | ||
1344 | } SVGAFifoCmdAnnotationCopy; | ||
1345 | |||
1346 | #endif | ||
diff --git a/drivers/gpu/drm/vmwgfx/svga_types.h b/drivers/gpu/drm/vmwgfx/svga_types.h new file mode 100644 index 000000000000..55836dedcfc2 --- /dev/null +++ b/drivers/gpu/drm/vmwgfx/svga_types.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /************************************************************************** | ||
2 | * | ||
3 | * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA | ||
4 | * All Rights Reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the | ||
8 | * "Software"), to deal in the Software without restriction, including | ||
9 | * without limitation the rights to use, copy, modify, merge, publish, | ||
10 | * distribute, sub license, and/or sell copies of the Software, and to | ||
11 | * permit persons to whom the Software is furnished to do so, subject to | ||
12 | * the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice (including the | ||
15 | * next paragraph) shall be included in all copies or substantial portions | ||
16 | * of the Software. | ||
17 | * | ||
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
21 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
22 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
23 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
24 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
25 | * | ||
26 | **************************************************************************/ | ||
27 | |||
28 | /** | ||
29 | * Silly typedefs for the svga headers. Currently the headers are shared | ||
30 | * between all components that talk to svga. And as such the headers are | ||
31 | * are in a completely different style and use weird defines. | ||
32 | * | ||
33 | * This file lets all the ugly be prefixed with svga*. | ||
34 | */ | ||
35 | |||
36 | #ifndef _SVGA_TYPES_H_ | ||
37 | #define _SVGA_TYPES_H_ | ||
38 | |||
39 | typedef uint16_t uint16; | ||
40 | typedef uint32_t uint32; | ||
41 | typedef uint8_t uint8; | ||
42 | typedef int32_t int32; | ||
43 | typedef bool Bool; | ||
44 | |||
45 | #endif | ||