diff options
| author | H. Peter Anvin <hpa@zytor.com> | 2007-05-02 13:27:12 -0400 |
|---|---|---|
| committer | Andi Kleen <andi@basil.nowhere.org> | 2007-05-02 13:27:12 -0400 |
| commit | 4bc5aa91fb1e544ad37805520030a0d9fc6e11d3 (patch) | |
| tree | 207870aad2f53fcec914ea5084de4fdfe1a02a23 | |
| parent | b6e3590f8145c77b8fcef3247e2412335221412f (diff) | |
[PATCH] x86: Clean up x86 control register and MSR macros (corrected)
This patch is based on Rusty's recent cleanup of the EFLAGS-related
macros; it extends the same kind of cleanup to control registers and
MSRs.
It also unifies these between i386 and x86-64; at least with regards
to MSRs, the two had definitely gotten out of sync.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Andi Kleen <ak@suse.de>
| -rw-r--r-- | include/asm-i386/Kbuild | 2 | ||||
| -rw-r--r-- | include/asm-i386/msr-index.h | 273 | ||||
| -rw-r--r-- | include/asm-i386/msr.h | 237 | ||||
| -rw-r--r-- | include/asm-i386/processor-flags.h | 65 | ||||
| -rw-r--r-- | include/asm-i386/processor.h | 35 | ||||
| -rw-r--r-- | include/asm-x86_64/Kbuild | 3 | ||||
| -rw-r--r-- | include/asm-x86_64/msr-index.h | 1 | ||||
| -rw-r--r-- | include/asm-x86_64/msr.h | 274 | ||||
| -rw-r--r-- | include/asm-x86_64/processor-flags.h | 27 | ||||
| -rw-r--r-- | include/asm-x86_64/processor.h | 31 |
10 files changed, 356 insertions, 592 deletions
diff --git a/include/asm-i386/Kbuild b/include/asm-i386/Kbuild index 5ae93afc67e1..cbf6e8f1087b 100644 --- a/include/asm-i386/Kbuild +++ b/include/asm-i386/Kbuild | |||
| @@ -3,8 +3,10 @@ include include/asm-generic/Kbuild.asm | |||
| 3 | header-y += boot.h | 3 | header-y += boot.h |
| 4 | header-y += debugreg.h | 4 | header-y += debugreg.h |
| 5 | header-y += ldt.h | 5 | header-y += ldt.h |
| 6 | header-y += msr-index.h | ||
| 6 | header-y += ptrace-abi.h | 7 | header-y += ptrace-abi.h |
| 7 | header-y += ucontext.h | 8 | header-y += ucontext.h |
| 8 | 9 | ||
| 10 | unifdef-y += msr.h | ||
| 9 | unifdef-y += mtrr.h | 11 | unifdef-y += mtrr.h |
| 10 | unifdef-y += vm86.h | 12 | unifdef-y += vm86.h |
diff --git a/include/asm-i386/msr-index.h b/include/asm-i386/msr-index.h new file mode 100644 index 000000000000..f1190802283d --- /dev/null +++ b/include/asm-i386/msr-index.h | |||
| @@ -0,0 +1,273 @@ | |||
| 1 | #ifndef __ASM_MSR_INDEX_H | ||
| 2 | #define __ASM_MSR_INDEX_H | ||
| 3 | |||
| 4 | /* CPU model specific register (MSR) numbers */ | ||
| 5 | |||
| 6 | /* x86-64 specific MSRs */ | ||
| 7 | #define MSR_EFER 0xc0000080 /* extended feature register */ | ||
| 8 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ | ||
| 9 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | ||
| 10 | #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ | ||
| 11 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | ||
| 12 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ | ||
| 13 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ | ||
| 14 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ | ||
| 15 | |||
| 16 | /* EFER bits: */ | ||
| 17 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | ||
| 18 | #define _EFER_LME 8 /* Long mode enable */ | ||
| 19 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | ||
| 20 | #define _EFER_NX 11 /* No execute enable */ | ||
| 21 | |||
| 22 | #define EFER_SCE (1<<_EFER_SCE) | ||
| 23 | #define EFER_LME (1<<_EFER_LME) | ||
| 24 | #define EFER_LMA (1<<_EFER_LMA) | ||
| 25 | #define EFER_NX (1<<_EFER_NX) | ||
| 26 | |||
| 27 | /* Intel MSRs. Some also available on other CPUs */ | ||
| 28 | #define MSR_IA32_PERFCTR0 0x000000c1 | ||
| 29 | #define MSR_IA32_PERFCTR1 0x000000c2 | ||
| 30 | #define MSR_FSB_FREQ 0x000000cd | ||
| 31 | |||
| 32 | #define MSR_MTRRcap 0x000000fe | ||
| 33 | #define MSR_IA32_BBL_CR_CTL 0x00000119 | ||
| 34 | |||
| 35 | #define MSR_IA32_SYSENTER_CS 0x00000174 | ||
| 36 | #define MSR_IA32_SYSENTER_ESP 0x00000175 | ||
| 37 | #define MSR_IA32_SYSENTER_EIP 0x00000176 | ||
| 38 | |||
| 39 | #define MSR_IA32_MCG_CAP 0x00000179 | ||
| 40 | #define MSR_IA32_MCG_STATUS 0x0000017a | ||
| 41 | #define MSR_IA32_MCG_CTL 0x0000017b | ||
| 42 | |||
| 43 | #define MSR_IA32_PEBS_ENABLE 0x000003f1 | ||
| 44 | #define MSR_IA32_DS_AREA 0x00000600 | ||
| 45 | #define MSR_IA32_PERF_CAPABILITIES 0x00000345 | ||
| 46 | |||
| 47 | #define MSR_MTRRfix64K_00000 0x00000250 | ||
| 48 | #define MSR_MTRRfix16K_80000 0x00000258 | ||
| 49 | #define MSR_MTRRfix16K_A0000 0x00000259 | ||
| 50 | #define MSR_MTRRfix4K_C0000 0x00000268 | ||
| 51 | #define MSR_MTRRfix4K_C8000 0x00000269 | ||
| 52 | #define MSR_MTRRfix4K_D0000 0x0000026a | ||
| 53 | #define MSR_MTRRfix4K_D8000 0x0000026b | ||
| 54 | #define MSR_MTRRfix4K_E0000 0x0000026c | ||
| 55 | #define MSR_MTRRfix4K_E8000 0x0000026d | ||
| 56 | #define MSR_MTRRfix4K_F0000 0x0000026e | ||
| 57 | #define MSR_MTRRfix4K_F8000 0x0000026f | ||
| 58 | #define MSR_MTRRdefType 0x000002ff | ||
| 59 | |||
| 60 | #define MSR_IA32_DEBUGCTLMSR 0x000001d9 | ||
| 61 | #define MSR_IA32_LASTBRANCHFROMIP 0x000001db | ||
| 62 | #define MSR_IA32_LASTBRANCHTOIP 0x000001dc | ||
| 63 | #define MSR_IA32_LASTINTFROMIP 0x000001dd | ||
| 64 | #define MSR_IA32_LASTINTTOIP 0x000001de | ||
| 65 | |||
| 66 | #define MSR_IA32_MC0_CTL 0x00000400 | ||
| 67 | #define MSR_IA32_MC0_STATUS 0x00000401 | ||
| 68 | #define MSR_IA32_MC0_ADDR 0x00000402 | ||
| 69 | #define MSR_IA32_MC0_MISC 0x00000403 | ||
| 70 | |||
| 71 | #define MSR_P6_PERFCTR0 0x000000c1 | ||
| 72 | #define MSR_P6_PERFCTR1 0x000000c2 | ||
| 73 | #define MSR_P6_EVNTSEL0 0x00000186 | ||
| 74 | #define MSR_P6_EVNTSEL1 0x00000187 | ||
| 75 | |||
| 76 | /* K7/K8 MSRs. Not complete. See the architecture manual for a more | ||
| 77 | complete list. */ | ||
| 78 | #define MSR_K7_EVNTSEL0 0xc0010000 | ||
| 79 | #define MSR_K7_PERFCTR0 0xc0010004 | ||
| 80 | #define MSR_K7_EVNTSEL1 0xc0010001 | ||
| 81 | #define MSR_K7_PERFCTR1 0xc0010005 | ||
| 82 | #define MSR_K7_EVNTSEL2 0xc0010002 | ||
| 83 | #define MSR_K7_PERFCTR2 0xc0010006 | ||
| 84 | #define MSR_K7_EVNTSEL3 0xc0010003 | ||
| 85 | #define MSR_K7_PERFCTR3 0xc0010007 | ||
| 86 | #define MSR_K8_TOP_MEM1 0xc001001a | ||
| 87 | #define MSR_K7_CLK_CTL 0xc001001b | ||
| 88 | #define MSR_K8_TOP_MEM2 0xc001001d | ||
| 89 | #define MSR_K8_SYSCFG 0xc0010010 | ||
| 90 | #define MSR_K7_HWCR 0xc0010015 | ||
| 91 | #define MSR_K8_HWCR 0xc0010015 | ||
| 92 | #define MSR_K7_FID_VID_CTL 0xc0010041 | ||
| 93 | #define MSR_K7_FID_VID_STATUS 0xc0010042 | ||
| 94 | #define MSR_K8_ENABLE_C1E 0xc0010055 | ||
| 95 | |||
| 96 | /* K6 MSRs */ | ||
| 97 | #define MSR_K6_EFER 0xc0000080 | ||
| 98 | #define MSR_K6_STAR 0xc0000081 | ||
| 99 | #define MSR_K6_WHCR 0xc0000082 | ||
| 100 | #define MSR_K6_UWCCR 0xc0000085 | ||
| 101 | #define MSR_K6_EPMR 0xc0000086 | ||
| 102 | #define MSR_K6_PSOR 0xc0000087 | ||
| 103 | #define MSR_K6_PFIR 0xc0000088 | ||
| 104 | |||
| 105 | /* Centaur-Hauls/IDT defined MSRs. */ | ||
| 106 | #define MSR_IDT_FCR1 0x00000107 | ||
| 107 | #define MSR_IDT_FCR2 0x00000108 | ||
| 108 | #define MSR_IDT_FCR3 0x00000109 | ||
| 109 | #define MSR_IDT_FCR4 0x0000010a | ||
| 110 | |||
| 111 | #define MSR_IDT_MCR0 0x00000110 | ||
| 112 | #define MSR_IDT_MCR1 0x00000111 | ||
| 113 | #define MSR_IDT_MCR2 0x00000112 | ||
| 114 | #define MSR_IDT_MCR3 0x00000113 | ||
| 115 | #define MSR_IDT_MCR4 0x00000114 | ||
| 116 | #define MSR_IDT_MCR5 0x00000115 | ||
| 117 | #define MSR_IDT_MCR6 0x00000116 | ||
| 118 | #define MSR_IDT_MCR7 0x00000117 | ||
| 119 | #define MSR_IDT_MCR_CTRL 0x00000120 | ||
| 120 | |||
| 121 | /* VIA Cyrix defined MSRs*/ | ||
| 122 | #define MSR_VIA_FCR 0x00001107 | ||
| 123 | #define MSR_VIA_LONGHAUL 0x0000110a | ||
| 124 | #define MSR_VIA_RNG 0x0000110b | ||
| 125 | #define MSR_VIA_BCR2 0x00001147 | ||
| 126 | |||
| 127 | /* Transmeta defined MSRs */ | ||
| 128 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 | ||
| 129 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 | ||
| 130 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | ||
| 131 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | ||
| 132 | |||
| 133 | /* Intel defined MSRs. */ | ||
| 134 | #define MSR_IA32_P5_MC_ADDR 0x00000000 | ||
| 135 | #define MSR_IA32_P5_MC_TYPE 0x00000001 | ||
| 136 | #define MSR_IA32_TSC 0x00000010 | ||
| 137 | #define MSR_IA32_PLATFORM_ID 0x00000017 | ||
| 138 | #define MSR_IA32_EBL_CR_POWERON 0x0000002a | ||
| 139 | |||
| 140 | #define MSR_IA32_APICBASE 0x0000001b | ||
| 141 | #define MSR_IA32_APICBASE_BSP (1<<8) | ||
| 142 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | ||
| 143 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | ||
| 144 | |||
| 145 | #define MSR_IA32_UCODE_WRITE 0x00000079 | ||
| 146 | #define MSR_IA32_UCODE_REV 0x0000008b | ||
| 147 | |||
| 148 | #define MSR_IA32_PERF_STATUS 0x00000198 | ||
| 149 | #define MSR_IA32_PERF_CTL 0x00000199 | ||
| 150 | |||
| 151 | #define MSR_IA32_MPERF 0x000000e7 | ||
| 152 | #define MSR_IA32_APERF 0x000000e8 | ||
| 153 | |||
| 154 | #define MSR_IA32_THERM_CONTROL 0x0000019a | ||
| 155 | #define MSR_IA32_THERM_INTERRUPT 0x0000019b | ||
| 156 | #define MSR_IA32_THERM_STATUS 0x0000019c | ||
| 157 | #define MSR_IA32_MISC_ENABLE 0x000001a0 | ||
| 158 | |||
| 159 | /* Intel Model 6 */ | ||
| 160 | #define MSR_P6_EVNTSEL0 0x00000186 | ||
| 161 | #define MSR_P6_EVNTSEL1 0x00000187 | ||
| 162 | |||
| 163 | /* P4/Xeon+ specific */ | ||
| 164 | #define MSR_IA32_MCG_EAX 0x00000180 | ||
| 165 | #define MSR_IA32_MCG_EBX 0x00000181 | ||
| 166 | #define MSR_IA32_MCG_ECX 0x00000182 | ||
| 167 | #define MSR_IA32_MCG_EDX 0x00000183 | ||
| 168 | #define MSR_IA32_MCG_ESI 0x00000184 | ||
| 169 | #define MSR_IA32_MCG_EDI 0x00000185 | ||
| 170 | #define MSR_IA32_MCG_EBP 0x00000186 | ||
| 171 | #define MSR_IA32_MCG_ESP 0x00000187 | ||
| 172 | #define MSR_IA32_MCG_EFLAGS 0x00000188 | ||
| 173 | #define MSR_IA32_MCG_EIP 0x00000189 | ||
| 174 | #define MSR_IA32_MCG_RESERVED 0x0000018a | ||
| 175 | |||
| 176 | /* Pentium IV performance counter MSRs */ | ||
| 177 | #define MSR_P4_BPU_PERFCTR0 0x00000300 | ||
| 178 | #define MSR_P4_BPU_PERFCTR1 0x00000301 | ||
| 179 | #define MSR_P4_BPU_PERFCTR2 0x00000302 | ||
| 180 | #define MSR_P4_BPU_PERFCTR3 0x00000303 | ||
| 181 | #define MSR_P4_MS_PERFCTR0 0x00000304 | ||
| 182 | #define MSR_P4_MS_PERFCTR1 0x00000305 | ||
| 183 | #define MSR_P4_MS_PERFCTR2 0x00000306 | ||
| 184 | #define MSR_P4_MS_PERFCTR3 0x00000307 | ||
| 185 | #define MSR_P4_FLAME_PERFCTR0 0x00000308 | ||
| 186 | #define MSR_P4_FLAME_PERFCTR1 0x00000309 | ||
| 187 | #define MSR_P4_FLAME_PERFCTR2 0x0000030a | ||
| 188 | #define MSR_P4_FLAME_PERFCTR3 0x0000030b | ||
| 189 | #define MSR_P4_IQ_PERFCTR0 0x0000030c | ||
| 190 | #define MSR_P4_IQ_PERFCTR1 0x0000030d | ||
| 191 | #define MSR_P4_IQ_PERFCTR2 0x0000030e | ||
| 192 | #define MSR_P4_IQ_PERFCTR3 0x0000030f | ||
| 193 | #define MSR_P4_IQ_PERFCTR4 0x00000310 | ||
| 194 | #define MSR_P4_IQ_PERFCTR5 0x00000311 | ||
| 195 | #define MSR_P4_BPU_CCCR0 0x00000360 | ||
| 196 | #define MSR_P4_BPU_CCCR1 0x00000361 | ||
| 197 | #define MSR_P4_BPU_CCCR2 0x00000362 | ||
| 198 | #define MSR_P4_BPU_CCCR3 0x00000363 | ||
| 199 | #define MSR_P4_MS_CCCR0 0x00000364 | ||
| 200 | #define MSR_P4_MS_CCCR1 0x00000365 | ||
| 201 | #define MSR_P4_MS_CCCR2 0x00000366 | ||
| 202 | #define MSR_P4_MS_CCCR3 0x00000367 | ||
| 203 | #define MSR_P4_FLAME_CCCR0 0x00000368 | ||
| 204 | #define MSR_P4_FLAME_CCCR1 0x00000369 | ||
| 205 | #define MSR_P4_FLAME_CCCR2 0x0000036a | ||
| 206 | #define MSR_P4_FLAME_CCCR3 0x0000036b | ||
| 207 | #define MSR_P4_IQ_CCCR0 0x0000036c | ||
| 208 | #define MSR_P4_IQ_CCCR1 0x0000036d | ||
| 209 | #define MSR_P4_IQ_CCCR2 0x0000036e | ||
| 210 | #define MSR_P4_IQ_CCCR3 0x0000036f | ||
| 211 | #define MSR_P4_IQ_CCCR4 0x00000370 | ||
| 212 | #define MSR_P4_IQ_CCCR5 0x00000371 | ||
| 213 | #define MSR_P4_ALF_ESCR0 0x000003ca | ||
| 214 | #define MSR_P4_ALF_ESCR1 0x000003cb | ||
| 215 | #define MSR_P4_BPU_ESCR0 0x000003b2 | ||
| 216 | #define MSR_P4_BPU_ESCR1 0x000003b3 | ||
| 217 | #define MSR_P4_BSU_ESCR0 0x000003a0 | ||
| 218 | #define MSR_P4_BSU_ESCR1 0x000003a1 | ||
| 219 | #define MSR_P4_CRU_ESCR0 0x000003b8 | ||
| 220 | #define MSR_P4_CRU_ESCR1 0x000003b9 | ||
| 221 | #define MSR_P4_CRU_ESCR2 0x000003cc | ||
| 222 | #define MSR_P4_CRU_ESCR3 0x000003cd | ||
| 223 | #define MSR_P4_CRU_ESCR4 0x000003e0 | ||
| 224 | #define MSR_P4_CRU_ESCR5 0x000003e1 | ||
| 225 | #define MSR_P4_DAC_ESCR0 0x000003a8 | ||
| 226 | #define MSR_P4_DAC_ESCR1 0x000003a9 | ||
| 227 | #define MSR_P4_FIRM_ESCR0 0x000003a4 | ||
| 228 | #define MSR_P4_FIRM_ESCR1 0x000003a5 | ||
| 229 | #define MSR_P4_FLAME_ESCR0 0x000003a6 | ||
| 230 | #define MSR_P4_FLAME_ESCR1 0x000003a7 | ||
| 231 | #define MSR_P4_FSB_ESCR0 0x000003a2 | ||
| 232 | #define MSR_P4_FSB_ESCR1 0x000003a3 | ||
| 233 | #define MSR_P4_IQ_ESCR0 0x000003ba | ||
| 234 | #define MSR_P4_IQ_ESCR1 0x000003bb | ||
| 235 | #define MSR_P4_IS_ESCR0 0x000003b4 | ||
| 236 | #define MSR_P4_IS_ESCR1 0x000003b5 | ||
| 237 | #define MSR_P4_ITLB_ESCR0 0x000003b6 | ||
| 238 | #define MSR_P4_ITLB_ESCR1 0x000003b7 | ||
| 239 | #define MSR_P4_IX_ESCR0 0x000003c8 | ||
| 240 | #define MSR_P4_IX_ESCR1 0x000003c9 | ||
| 241 | #define MSR_P4_MOB_ESCR0 0x000003aa | ||
| 242 | #define MSR_P4_MOB_ESCR1 0x000003ab | ||
| 243 | #define MSR_P4_MS_ESCR0 0x000003c0 | ||
| 244 | #define MSR_P4_MS_ESCR1 0x000003c1 | ||
| 245 | #define MSR_P4_PMH_ESCR0 0x000003ac | ||
| 246 | #define MSR_P4_PMH_ESCR1 0x000003ad | ||
| 247 | #define MSR_P4_RAT_ESCR0 0x000003bc | ||
| 248 | #define MSR_P4_RAT_ESCR1 0x000003bd | ||
| 249 | #define MSR_P4_SAAT_ESCR0 0x000003ae | ||
| 250 | #define MSR_P4_SAAT_ESCR1 0x000003af | ||
| 251 | #define MSR_P4_SSU_ESCR0 0x000003be | ||
| 252 | #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ | ||
| 253 | |||
| 254 | #define MSR_P4_TBPU_ESCR0 0x000003c2 | ||
| 255 | #define MSR_P4_TBPU_ESCR1 0x000003c3 | ||
| 256 | #define MSR_P4_TC_ESCR0 0x000003c4 | ||
| 257 | #define MSR_P4_TC_ESCR1 0x000003c5 | ||
| 258 | #define MSR_P4_U2L_ESCR0 0x000003b0 | ||
| 259 | #define MSR_P4_U2L_ESCR1 0x000003b1 | ||
| 260 | |||
| 261 | /* Intel Core-based CPU performance counters */ | ||
| 262 | #define MSR_CORE_PERF_FIXED_CTR0 0x00000309 | ||
| 263 | #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a | ||
| 264 | #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b | ||
| 265 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d | ||
| 266 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e | ||
| 267 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f | ||
| 268 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 | ||
| 269 | |||
| 270 | /* Geode defined MSRs */ | ||
| 271 | #define MSR_GEODE_BUSCONT_CONF0 0x00001900 | ||
| 272 | |||
| 273 | #endif /* __ASM_MSR_INDEX_H */ | ||
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index 00acaa8b36bb..9559894c7658 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h | |||
| @@ -1,6 +1,11 @@ | |||
| 1 | #ifndef __ASM_MSR_H | 1 | #ifndef __ASM_MSR_H |
| 2 | #define __ASM_MSR_H | 2 | #define __ASM_MSR_H |
| 3 | 3 | ||
| 4 | #include <asm/msr-index.h> | ||
| 5 | |||
| 6 | #ifdef __KERNEL__ | ||
| 7 | #ifndef __ASSEMBLY__ | ||
| 8 | |||
| 4 | #include <asm/errno.h> | 9 | #include <asm/errno.h> |
| 5 | 10 | ||
| 6 | static inline unsigned long long native_read_msr(unsigned int msr) | 11 | static inline unsigned long long native_read_msr(unsigned int msr) |
| @@ -153,234 +158,6 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |||
| 153 | wrmsr(msr_no, l, h); | 158 | wrmsr(msr_no, l, h); |
| 154 | } | 159 | } |
| 155 | #endif /* CONFIG_SMP */ | 160 | #endif /* CONFIG_SMP */ |
| 156 | 161 | #endif | |
| 157 | /* symbolic names for some interesting MSRs */ | 162 | #endif |
| 158 | /* Intel defined MSRs. */ | ||
| 159 | #define MSR_IA32_P5_MC_ADDR 0 | ||
| 160 | #define MSR_IA32_P5_MC_TYPE 1 | ||
| 161 | #define MSR_IA32_PLATFORM_ID 0x17 | ||
| 162 | #define MSR_IA32_EBL_CR_POWERON 0x2a | ||
| 163 | |||
| 164 | #define MSR_IA32_APICBASE 0x1b | ||
| 165 | #define MSR_IA32_APICBASE_BSP (1<<8) | ||
| 166 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | ||
| 167 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | ||
| 168 | |||
| 169 | #define MSR_IA32_UCODE_WRITE 0x79 | ||
| 170 | #define MSR_IA32_UCODE_REV 0x8b | ||
| 171 | |||
| 172 | #define MSR_P6_PERFCTR0 0xc1 | ||
| 173 | #define MSR_P6_PERFCTR1 0xc2 | ||
| 174 | #define MSR_FSB_FREQ 0xcd | ||
| 175 | |||
| 176 | |||
| 177 | #define MSR_IA32_BBL_CR_CTL 0x119 | ||
| 178 | |||
| 179 | #define MSR_IA32_SYSENTER_CS 0x174 | ||
| 180 | #define MSR_IA32_SYSENTER_ESP 0x175 | ||
| 181 | #define MSR_IA32_SYSENTER_EIP 0x176 | ||
| 182 | |||
| 183 | #define MSR_IA32_MCG_CAP 0x179 | ||
| 184 | #define MSR_IA32_MCG_STATUS 0x17a | ||
| 185 | #define MSR_IA32_MCG_CTL 0x17b | ||
| 186 | |||
| 187 | /* P4/Xeon+ specific */ | ||
| 188 | #define MSR_IA32_MCG_EAX 0x180 | ||
| 189 | #define MSR_IA32_MCG_EBX 0x181 | ||
| 190 | #define MSR_IA32_MCG_ECX 0x182 | ||
| 191 | #define MSR_IA32_MCG_EDX 0x183 | ||
| 192 | #define MSR_IA32_MCG_ESI 0x184 | ||
| 193 | #define MSR_IA32_MCG_EDI 0x185 | ||
| 194 | #define MSR_IA32_MCG_EBP 0x186 | ||
| 195 | #define MSR_IA32_MCG_ESP 0x187 | ||
| 196 | #define MSR_IA32_MCG_EFLAGS 0x188 | ||
| 197 | #define MSR_IA32_MCG_EIP 0x189 | ||
| 198 | #define MSR_IA32_MCG_RESERVED 0x18A | ||
| 199 | |||
| 200 | #define MSR_P6_EVNTSEL0 0x186 | ||
| 201 | #define MSR_P6_EVNTSEL1 0x187 | ||
| 202 | |||
| 203 | #define MSR_IA32_PERF_STATUS 0x198 | ||
| 204 | #define MSR_IA32_PERF_CTL 0x199 | ||
| 205 | |||
| 206 | #define MSR_IA32_MPERF 0xE7 | ||
| 207 | #define MSR_IA32_APERF 0xE8 | ||
| 208 | |||
| 209 | #define MSR_IA32_THERM_CONTROL 0x19a | ||
| 210 | #define MSR_IA32_THERM_INTERRUPT 0x19b | ||
| 211 | #define MSR_IA32_THERM_STATUS 0x19c | ||
| 212 | #define MSR_IA32_MISC_ENABLE 0x1a0 | ||
| 213 | |||
| 214 | #define MSR_IA32_DEBUGCTLMSR 0x1d9 | ||
| 215 | #define MSR_IA32_LASTBRANCHFROMIP 0x1db | ||
| 216 | #define MSR_IA32_LASTBRANCHTOIP 0x1dc | ||
| 217 | #define MSR_IA32_LASTINTFROMIP 0x1dd | ||
| 218 | #define MSR_IA32_LASTINTTOIP 0x1de | ||
| 219 | |||
| 220 | #define MSR_IA32_MC0_CTL 0x400 | ||
| 221 | #define MSR_IA32_MC0_STATUS 0x401 | ||
| 222 | #define MSR_IA32_MC0_ADDR 0x402 | ||
| 223 | #define MSR_IA32_MC0_MISC 0x403 | ||
| 224 | |||
| 225 | #define MSR_IA32_PEBS_ENABLE 0x3f1 | ||
| 226 | #define MSR_IA32_DS_AREA 0x600 | ||
| 227 | #define MSR_IA32_PERF_CAPABILITIES 0x345 | ||
| 228 | |||
| 229 | /* Pentium IV performance counter MSRs */ | ||
| 230 | #define MSR_P4_BPU_PERFCTR0 0x300 | ||
| 231 | #define MSR_P4_BPU_PERFCTR1 0x301 | ||
| 232 | #define MSR_P4_BPU_PERFCTR2 0x302 | ||
| 233 | #define MSR_P4_BPU_PERFCTR3 0x303 | ||
| 234 | #define MSR_P4_MS_PERFCTR0 0x304 | ||
| 235 | #define MSR_P4_MS_PERFCTR1 0x305 | ||
| 236 | #define MSR_P4_MS_PERFCTR2 0x306 | ||
| 237 | #define MSR_P4_MS_PERFCTR3 0x307 | ||
| 238 | #define MSR_P4_FLAME_PERFCTR0 0x308 | ||
| 239 | #define MSR_P4_FLAME_PERFCTR1 0x309 | ||
| 240 | #define MSR_P4_FLAME_PERFCTR2 0x30a | ||
| 241 | #define MSR_P4_FLAME_PERFCTR3 0x30b | ||
| 242 | #define MSR_P4_IQ_PERFCTR0 0x30c | ||
| 243 | #define MSR_P4_IQ_PERFCTR1 0x30d | ||
| 244 | #define MSR_P4_IQ_PERFCTR2 0x30e | ||
| 245 | #define MSR_P4_IQ_PERFCTR3 0x30f | ||
| 246 | #define MSR_P4_IQ_PERFCTR4 0x310 | ||
| 247 | #define MSR_P4_IQ_PERFCTR5 0x311 | ||
| 248 | #define MSR_P4_BPU_CCCR0 0x360 | ||
| 249 | #define MSR_P4_BPU_CCCR1 0x361 | ||
| 250 | #define MSR_P4_BPU_CCCR2 0x362 | ||
| 251 | #define MSR_P4_BPU_CCCR3 0x363 | ||
| 252 | #define MSR_P4_MS_CCCR0 0x364 | ||
| 253 | #define MSR_P4_MS_CCCR1 0x365 | ||
| 254 | #define MSR_P4_MS_CCCR2 0x366 | ||
| 255 | #define MSR_P4_MS_CCCR3 0x367 | ||
| 256 | #define MSR_P4_FLAME_CCCR0 0x368 | ||
| 257 | #define MSR_P4_FLAME_CCCR1 0x369 | ||
| 258 | #define MSR_P4_FLAME_CCCR2 0x36a | ||
| 259 | #define MSR_P4_FLAME_CCCR3 0x36b | ||
| 260 | #define MSR_P4_IQ_CCCR0 0x36c | ||
| 261 | #define MSR_P4_IQ_CCCR1 0x36d | ||
| 262 | #define MSR_P4_IQ_CCCR2 0x36e | ||
| 263 | #define MSR_P4_IQ_CCCR3 0x36f | ||
| 264 | #define MSR_P4_IQ_CCCR4 0x370 | ||
| 265 | #define MSR_P4_IQ_CCCR5 0x371 | ||
| 266 | #define MSR_P4_ALF_ESCR0 0x3ca | ||
| 267 | #define MSR_P4_ALF_ESCR1 0x3cb | ||
| 268 | #define MSR_P4_BPU_ESCR0 0x3b2 | ||
| 269 | #define MSR_P4_BPU_ESCR1 0x3b3 | ||
| 270 | #define MSR_P4_BSU_ESCR0 0x3a0 | ||
| 271 | #define MSR_P4_BSU_ESCR1 0x3a1 | ||
| 272 | #define MSR_P4_CRU_ESCR0 0x3b8 | ||
| 273 | #define MSR_P4_CRU_ESCR1 0x3b9 | ||
| 274 | #define MSR_P4_CRU_ESCR2 0x3cc | ||
| 275 | #define MSR_P4_CRU_ESCR3 0x3cd | ||
| 276 | #define MSR_P4_CRU_ESCR4 0x3e0 | ||
| 277 | #define MSR_P4_CRU_ESCR5 0x3e1 | ||
| 278 | #define MSR_P4_DAC_ESCR0 0x3a8 | ||
| 279 | #define MSR_P4_DAC_ESCR1 0x3a9 | ||
| 280 | #define MSR_P4_FIRM_ESCR0 0x3a4 | ||
| 281 | #define MSR_P4_FIRM_ESCR1 0x3a5 | ||
| 282 | #define MSR_P4_FLAME_ESCR0 0x3a6 | ||
| 283 | #define MSR_P4_FLAME_ESCR1 0x3a7 | ||
| 284 | #define MSR_P4_FSB_ESCR0 0x3a2 | ||
| 285 | #define MSR_P4_FSB_ESCR1 0x3a3 | ||
| 286 | #define MSR_P4_IQ_ESCR0 0x3ba | ||
| 287 | #define MSR_P4_IQ_ESCR1 0x3bb | ||
| 288 | #define MSR_P4_IS_ESCR0 0x3b4 | ||
| 289 | #define MSR_P4_IS_ESCR1 0x3b5 | ||
| 290 | #define MSR_P4_ITLB_ESCR0 0x3b6 | ||
| 291 | #define MSR_P4_ITLB_ESCR1 0x3b7 | ||
| 292 | #define MSR_P4_IX_ESCR0 0x3c8 | ||
| 293 | #define MSR_P4_IX_ESCR1 0x3c9 | ||
| 294 | #define MSR_P4_MOB_ESCR0 0x3aa | ||
| 295 | #define MSR_P4_MOB_ESCR1 0x3ab | ||
| 296 | #define MSR_P4_MS_ESCR0 0x3c0 | ||
| 297 | #define MSR_P4_MS_ESCR1 0x3c1 | ||
| 298 | #define MSR_P4_PMH_ESCR0 0x3ac | ||
| 299 | #define MSR_P4_PMH_ESCR1 0x3ad | ||
| 300 | #define MSR_P4_RAT_ESCR0 0x3bc | ||
| 301 | #define MSR_P4_RAT_ESCR1 0x3bd | ||
| 302 | #define MSR_P4_SAAT_ESCR0 0x3ae | ||
| 303 | #define MSR_P4_SAAT_ESCR1 0x3af | ||
| 304 | #define MSR_P4_SSU_ESCR0 0x3be | ||
| 305 | #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */ | ||
| 306 | #define MSR_P4_TBPU_ESCR0 0x3c2 | ||
| 307 | #define MSR_P4_TBPU_ESCR1 0x3c3 | ||
| 308 | #define MSR_P4_TC_ESCR0 0x3c4 | ||
| 309 | #define MSR_P4_TC_ESCR1 0x3c5 | ||
| 310 | #define MSR_P4_U2L_ESCR0 0x3b0 | ||
| 311 | #define MSR_P4_U2L_ESCR1 0x3b1 | ||
| 312 | |||
| 313 | /* AMD Defined MSRs */ | ||
| 314 | #define MSR_K6_EFER 0xC0000080 | ||
| 315 | #define MSR_K6_STAR 0xC0000081 | ||
| 316 | #define MSR_K6_WHCR 0xC0000082 | ||
| 317 | #define MSR_K6_UWCCR 0xC0000085 | ||
| 318 | #define MSR_K6_EPMR 0xC0000086 | ||
| 319 | #define MSR_K6_PSOR 0xC0000087 | ||
| 320 | #define MSR_K6_PFIR 0xC0000088 | ||
| 321 | |||
| 322 | #define MSR_K7_EVNTSEL0 0xC0010000 | ||
| 323 | #define MSR_K7_EVNTSEL1 0xC0010001 | ||
| 324 | #define MSR_K7_EVNTSEL2 0xC0010002 | ||
| 325 | #define MSR_K7_EVNTSEL3 0xC0010003 | ||
| 326 | #define MSR_K7_PERFCTR0 0xC0010004 | ||
| 327 | #define MSR_K7_PERFCTR1 0xC0010005 | ||
| 328 | #define MSR_K7_PERFCTR2 0xC0010006 | ||
| 329 | #define MSR_K7_PERFCTR3 0xC0010007 | ||
| 330 | #define MSR_K7_HWCR 0xC0010015 | ||
| 331 | #define MSR_K7_CLK_CTL 0xC001001b | ||
| 332 | #define MSR_K7_FID_VID_CTL 0xC0010041 | ||
| 333 | #define MSR_K7_FID_VID_STATUS 0xC0010042 | ||
| 334 | |||
| 335 | #define MSR_K8_ENABLE_C1E 0xC0010055 | ||
| 336 | |||
| 337 | /* extended feature register */ | ||
| 338 | #define MSR_EFER 0xc0000080 | ||
| 339 | |||
| 340 | /* EFER bits: */ | ||
| 341 | |||
| 342 | /* Execute Disable enable */ | ||
| 343 | #define _EFER_NX 11 | ||
| 344 | #define EFER_NX (1<<_EFER_NX) | ||
| 345 | |||
| 346 | /* Centaur-Hauls/IDT defined MSRs. */ | ||
| 347 | #define MSR_IDT_FCR1 0x107 | ||
| 348 | #define MSR_IDT_FCR2 0x108 | ||
| 349 | #define MSR_IDT_FCR3 0x109 | ||
| 350 | #define MSR_IDT_FCR4 0x10a | ||
| 351 | |||
| 352 | #define MSR_IDT_MCR0 0x110 | ||
| 353 | #define MSR_IDT_MCR1 0x111 | ||
| 354 | #define MSR_IDT_MCR2 0x112 | ||
| 355 | #define MSR_IDT_MCR3 0x113 | ||
| 356 | #define MSR_IDT_MCR4 0x114 | ||
| 357 | #define MSR_IDT_MCR5 0x115 | ||
| 358 | #define MSR_IDT_MCR6 0x116 | ||
| 359 | #define MSR_IDT_MCR7 0x117 | ||
| 360 | #define MSR_IDT_MCR_CTRL 0x120 | ||
| 361 | |||
| 362 | /* VIA Cyrix defined MSRs*/ | ||
| 363 | #define MSR_VIA_FCR 0x1107 | ||
| 364 | #define MSR_VIA_LONGHAUL 0x110a | ||
| 365 | #define MSR_VIA_RNG 0x110b | ||
| 366 | #define MSR_VIA_BCR2 0x1147 | ||
| 367 | |||
| 368 | /* Transmeta defined MSRs */ | ||
| 369 | #define MSR_TMTA_LONGRUN_CTRL 0x80868010 | ||
| 370 | #define MSR_TMTA_LONGRUN_FLAGS 0x80868011 | ||
| 371 | #define MSR_TMTA_LRTI_READOUT 0x80868018 | ||
| 372 | #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a | ||
| 373 | |||
| 374 | /* Intel Core-based CPU performance counters */ | ||
| 375 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | ||
| 376 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | ||
| 377 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | ||
| 378 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | ||
| 379 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | ||
| 380 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | ||
| 381 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | ||
| 382 | |||
| 383 | /* Geode defined MSRs */ | ||
| 384 | #define MSR_GEODE_BUSCONT_CONF0 0x1900 | ||
| 385 | |||
| 386 | #endif /* __ASM_MSR_H */ | 163 | #endif /* __ASM_MSR_H */ |
diff --git a/include/asm-i386/processor-flags.h b/include/asm-i386/processor-flags.h index b4711c222e2b..5404e90edd57 100644 --- a/include/asm-i386/processor-flags.h +++ b/include/asm-i386/processor-flags.h | |||
| @@ -23,4 +23,69 @@ | |||
| 23 | #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ | 23 | #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ |
| 24 | #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ | 24 | #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ |
| 25 | 25 | ||
| 26 | /* | ||
| 27 | * Basic CPU control in CR0 | ||
| 28 | */ | ||
| 29 | #define X86_CR0_PE 0x00000001 /* Protection Enable */ | ||
| 30 | #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor */ | ||
| 31 | #define X86_CR0_EM 0x00000004 /* Emulation */ | ||
| 32 | #define X86_CR0_TS 0x00000008 /* Task Switched */ | ||
| 33 | #define X86_CR0_ET 0x00000010 /* Extension Type */ | ||
| 34 | #define X86_CR0_NE 0x00000020 /* Numeric Error */ | ||
| 35 | #define X86_CR0_WP 0x00010000 /* Write Protect */ | ||
| 36 | #define X86_CR0_AM 0x00040000 /* Alignment Mask */ | ||
| 37 | #define X86_CR0_NW 0x20000000 /* Not Write-through */ | ||
| 38 | #define X86_CR0_CD 0x40000000 /* Cache Disable */ | ||
| 39 | #define X86_CR0_PG 0x80000000 /* Paging */ | ||
| 40 | |||
| 41 | /* | ||
| 42 | * Paging options in CR3 | ||
| 43 | */ | ||
| 44 | #define X86_CR3_PWT 0x00000008 /* Page Write Through */ | ||
| 45 | #define X86_CR3_PCD 0x00000010 /* Page Cache Disable */ | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Intel CPU features in CR4 | ||
| 49 | */ | ||
| 50 | #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ | ||
| 51 | #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ | ||
| 52 | #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ | ||
| 53 | #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ | ||
| 54 | #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ | ||
| 55 | #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ | ||
| 56 | #define X86_CR4_MCE 0x00000040 /* Machine check enable */ | ||
| 57 | #define X86_CR4_PGE 0x00000080 /* enable global pages */ | ||
| 58 | #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ | ||
| 59 | #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ | ||
| 60 | #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ | ||
| 61 | #define X86_CR4_VMXE 0x00002000 /* enable VMX virtualization */ | ||
| 62 | |||
| 63 | /* | ||
| 64 | * x86-64 Task Priority Register, CR8 | ||
| 65 | */ | ||
| 66 | #define X86_CR8_TPR 0x00000007 /* task priority register */ | ||
| 67 | |||
| 68 | /* | ||
| 69 | * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> | ||
| 70 | */ | ||
| 71 | |||
| 72 | /* | ||
| 73 | * NSC/Cyrix CPU configuration register indexes | ||
| 74 | */ | ||
| 75 | #define CX86_PCR0 0x20 | ||
| 76 | #define CX86_GCR 0xb8 | ||
| 77 | #define CX86_CCR0 0xc0 | ||
| 78 | #define CX86_CCR1 0xc1 | ||
| 79 | #define CX86_CCR2 0xc2 | ||
| 80 | #define CX86_CCR3 0xc3 | ||
| 81 | #define CX86_CCR4 0xe8 | ||
| 82 | #define CX86_CCR5 0xe9 | ||
| 83 | #define CX86_CCR6 0xea | ||
| 84 | #define CX86_CCR7 0xeb | ||
| 85 | #define CX86_PCR1 0xf0 | ||
| 86 | #define CX86_DIR0 0xfe | ||
| 87 | #define CX86_DIR1 0xff | ||
| 88 | #define CX86_ARR_BASE 0xc4 | ||
| 89 | #define CX86_RCR_BASE 0xdc | ||
| 90 | |||
| 26 | #endif /* __ASM_I386_PROCESSOR_FLAGS_H */ | 91 | #endif /* __ASM_I386_PROCESSOR_FLAGS_H */ |
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index 882d3f8fbbac..77e263267aa6 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h | |||
| @@ -143,21 +143,6 @@ static inline void native_cpuid(unsigned int *eax, unsigned int *ebx, | |||
| 143 | #define load_cr3(pgdir) write_cr3(__pa(pgdir)) | 143 | #define load_cr3(pgdir) write_cr3(__pa(pgdir)) |
| 144 | 144 | ||
| 145 | /* | 145 | /* |
| 146 | * Intel CPU features in CR4 | ||
| 147 | */ | ||
| 148 | #define X86_CR4_VME 0x0001 /* enable vm86 extensions */ | ||
| 149 | #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */ | ||
| 150 | #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */ | ||
| 151 | #define X86_CR4_DE 0x0008 /* enable debugging extensions */ | ||
| 152 | #define X86_CR4_PSE 0x0010 /* enable page size extensions */ | ||
| 153 | #define X86_CR4_PAE 0x0020 /* enable physical address extensions */ | ||
| 154 | #define X86_CR4_MCE 0x0040 /* Machine check enable */ | ||
| 155 | #define X86_CR4_PGE 0x0080 /* enable global pages */ | ||
| 156 | #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */ | ||
| 157 | #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */ | ||
| 158 | #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ | ||
| 159 | |||
| 160 | /* | ||
| 161 | * Save the cr4 feature set we're using (ie | 146 | * Save the cr4 feature set we're using (ie |
| 162 | * Pentium 4MB enable and PPro Global page | 147 | * Pentium 4MB enable and PPro Global page |
| 163 | * enable), so that any CPU's that boot up | 148 | * enable), so that any CPU's that boot up |
| @@ -184,26 +169,6 @@ static inline void clear_in_cr4 (unsigned long mask) | |||
| 184 | } | 169 | } |
| 185 | 170 | ||
| 186 | /* | 171 | /* |
| 187 | * NSC/Cyrix CPU configuration register indexes | ||
| 188 | */ | ||
| 189 | |||
| 190 | #define CX86_PCR0 0x20 | ||
| 191 | #define CX86_GCR 0xb8 | ||
| 192 | #define CX86_CCR0 0xc0 | ||
| 193 | #define CX86_CCR1 0xc1 | ||
| 194 | #define CX86_CCR2 0xc2 | ||
| 195 | #define CX86_CCR3 0xc3 | ||
| 196 | #define CX86_CCR4 0xe8 | ||
| 197 | #define CX86_CCR5 0xe9 | ||
| 198 | #define CX86_CCR6 0xea | ||
| 199 | #define CX86_CCR7 0xeb | ||
| 200 | #define CX86_PCR1 0xf0 | ||
| 201 | #define CX86_DIR0 0xfe | ||
| 202 | #define CX86_DIR1 0xff | ||
| 203 | #define CX86_ARR_BASE 0xc4 | ||
| 204 | #define CX86_RCR_BASE 0xdc | ||
| 205 | |||
| 206 | /* | ||
| 207 | * NSC/Cyrix CPU indexed register access macros | 172 | * NSC/Cyrix CPU indexed register access macros |
| 208 | */ | 173 | */ |
| 209 | 174 | ||
diff --git a/include/asm-x86_64/Kbuild b/include/asm-x86_64/Kbuild index 242296ede3dd..89ad1fc27c8b 100644 --- a/include/asm-x86_64/Kbuild +++ b/include/asm-x86_64/Kbuild | |||
| @@ -8,7 +8,7 @@ header-y += boot.h | |||
| 8 | header-y += bootsetup.h | 8 | header-y += bootsetup.h |
| 9 | header-y += debugreg.h | 9 | header-y += debugreg.h |
| 10 | header-y += ldt.h | 10 | header-y += ldt.h |
| 11 | header-y += msr.h | 11 | header-y += msr-index.h |
| 12 | header-y += prctl.h | 12 | header-y += prctl.h |
| 13 | header-y += ptrace-abi.h | 13 | header-y += ptrace-abi.h |
| 14 | header-y += sigcontext32.h | 14 | header-y += sigcontext32.h |
| @@ -16,6 +16,7 @@ header-y += ucontext.h | |||
| 16 | header-y += vsyscall32.h | 16 | header-y += vsyscall32.h |
| 17 | 17 | ||
| 18 | unifdef-y += mce.h | 18 | unifdef-y += mce.h |
| 19 | unifdef-y += msr.h | ||
| 19 | unifdef-y += mtrr.h | 20 | unifdef-y += mtrr.h |
| 20 | unifdef-y += vsyscall.h | 21 | unifdef-y += vsyscall.h |
| 21 | unifdef-y += const.h | 22 | unifdef-y += const.h |
diff --git a/include/asm-x86_64/msr-index.h b/include/asm-x86_64/msr-index.h new file mode 100644 index 000000000000..d77a63f1ddf2 --- /dev/null +++ b/include/asm-x86_64/msr-index.h | |||
| @@ -0,0 +1 @@ | |||
| #include <asm-i386/msr-index.h> | |||
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h index 902f9a58617e..a524f0325673 100644 --- a/include/asm-x86_64/msr.h +++ b/include/asm-x86_64/msr.h | |||
| @@ -1,6 +1,8 @@ | |||
| 1 | #ifndef X86_64_MSR_H | 1 | #ifndef X86_64_MSR_H |
| 2 | #define X86_64_MSR_H 1 | 2 | #define X86_64_MSR_H 1 |
| 3 | 3 | ||
| 4 | #include <asm/msr-index.h> | ||
| 5 | |||
| 4 | #ifndef __ASSEMBLY__ | 6 | #ifndef __ASSEMBLY__ |
| 5 | /* | 7 | /* |
| 6 | * Access to machine-specific registers (available on 586 and better only) | 8 | * Access to machine-specific registers (available on 586 and better only) |
| @@ -157,9 +159,6 @@ static inline unsigned int cpuid_edx(unsigned int op) | |||
| 157 | return edx; | 159 | return edx; |
| 158 | } | 160 | } |
| 159 | 161 | ||
| 160 | #define MSR_IA32_UCODE_WRITE 0x79 | ||
| 161 | #define MSR_IA32_UCODE_REV 0x8b | ||
| 162 | |||
| 163 | #ifdef CONFIG_SMP | 162 | #ifdef CONFIG_SMP |
| 164 | void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); | 163 | void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
| 165 | void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); | 164 | void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
| @@ -172,269 +171,6 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) | |||
| 172 | { | 171 | { |
| 173 | wrmsr(msr_no, l, h); | 172 | wrmsr(msr_no, l, h); |
| 174 | } | 173 | } |
| 175 | #endif /* CONFIG_SMP */ | 174 | #endif /* CONFIG_SMP */ |
| 176 | 175 | #endif /* __ASSEMBLY__ */ | |
| 177 | #endif | 176 | #endif /* X86_64_MSR_H */ |
| 178 | |||
| 179 | /* AMD/K8 specific MSRs */ | ||
| 180 | #define MSR_EFER 0xc0000080 /* extended feature register */ | ||
| 181 | #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ | ||
| 182 | #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ | ||
| 183 | #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */ | ||
| 184 | #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ | ||
| 185 | #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ | ||
| 186 | #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ | ||
| 187 | #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow (or USER_GS from kernel) */ | ||
| 188 | /* EFER bits: */ | ||
| 189 | #define _EFER_SCE 0 /* SYSCALL/SYSRET */ | ||
| 190 | #define _EFER_LME 8 /* Long mode enable */ | ||
| 191 | #define _EFER_LMA 10 /* Long mode active (read-only) */ | ||
| 192 | #define _EFER_NX 11 /* No execute enable */ | ||
| 193 | |||
| 194 | #define EFER_SCE (1<<_EFER_SCE) | ||
| 195 | #define EFER_LME (1<<_EFER_LME) | ||
| 196 | #define EFER_LMA (1<<_EFER_LMA) | ||
| 197 | #define EFER_NX (1<<_EFER_NX) | ||
| 198 | |||
| 199 | /* Intel MSRs. Some also available on other CPUs */ | ||
| 200 | #define MSR_IA32_TSC 0x10 | ||
| 201 | #define MSR_IA32_PLATFORM_ID 0x17 | ||
| 202 | |||
| 203 | #define MSR_IA32_PERFCTR0 0xc1 | ||
| 204 | #define MSR_IA32_PERFCTR1 0xc2 | ||
| 205 | #define MSR_FSB_FREQ 0xcd | ||
| 206 | |||
| 207 | #define MSR_MTRRcap 0x0fe | ||
| 208 | #define MSR_IA32_BBL_CR_CTL 0x119 | ||
| 209 | |||
| 210 | #define MSR_IA32_SYSENTER_CS 0x174 | ||
| 211 | #define MSR_IA32_SYSENTER_ESP 0x175 | ||
| 212 | #define MSR_IA32_SYSENTER_EIP 0x176 | ||
| 213 | |||
| 214 | #define MSR_IA32_MCG_CAP 0x179 | ||
| 215 | #define MSR_IA32_MCG_STATUS 0x17a | ||
| 216 | #define MSR_IA32_MCG_CTL 0x17b | ||
| 217 | |||
| 218 | #define MSR_IA32_EVNTSEL0 0x186 | ||
| 219 | #define MSR_IA32_EVNTSEL1 0x187 | ||
| 220 | |||
| 221 | #define MSR_IA32_DEBUGCTLMSR 0x1d9 | ||
| 222 | #define MSR_IA32_LASTBRANCHFROMIP 0x1db | ||
| 223 | #define MSR_IA32_LASTBRANCHTOIP 0x1dc | ||
| 224 | #define MSR_IA32_LASTINTFROMIP 0x1dd | ||
| 225 | #define MSR_IA32_LASTINTTOIP 0x1de | ||
| 226 | |||
| 227 | #define MSR_IA32_PEBS_ENABLE 0x3f1 | ||
| 228 | #define MSR_IA32_DS_AREA 0x600 | ||
| 229 | #define MSR_IA32_PERF_CAPABILITIES 0x345 | ||
| 230 | |||
| 231 | #define MSR_MTRRfix64K_00000 0x250 | ||
| 232 | #define MSR_MTRRfix16K_80000 0x258 | ||
| 233 | #define MSR_MTRRfix16K_A0000 0x259 | ||
| 234 | #define MSR_MTRRfix4K_C0000 0x268 | ||
| 235 | #define MSR_MTRRfix4K_C8000 0x269 | ||
| 236 | #define MSR_MTRRfix4K_D0000 0x26a | ||
| 237 | #define MSR_MTRRfix4K_D8000 0x26b | ||
| 238 | #define MSR_MTRRfix4K_E0000 0x26c | ||
| 239 | #define MSR_MTRRfix4K_E8000 0x26d | ||
| 240 | #define MSR_MTRRfix4K_F0000 0x26e | ||
| 241 | #define MSR_MTRRfix4K_F8000 0x26f | ||
| 242 | #define MSR_MTRRdefType 0x2ff | ||
| 243 | |||
| 244 | #define MSR_IA32_MC0_CTL 0x400 | ||
| 245 | #define MSR_IA32_MC0_STATUS 0x401 | ||
| 246 | #define MSR_IA32_MC0_ADDR 0x402 | ||
| 247 | #define MSR_IA32_MC0_MISC 0x403 | ||
| 248 | |||
| 249 | #define MSR_P6_PERFCTR0 0xc1 | ||
| 250 | #define MSR_P6_PERFCTR1 0xc2 | ||
| 251 | #define MSR_P6_EVNTSEL0 0x186 | ||
| 252 | #define MSR_P6_EVNTSEL1 0x187 | ||
| 253 | |||
| 254 | /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */ | ||
| 255 | #define MSR_K7_EVNTSEL0 0xC0010000 | ||
| 256 | #define MSR_K7_PERFCTR0 0xC0010004 | ||
| 257 | #define MSR_K7_EVNTSEL1 0xC0010001 | ||
| 258 | #define MSR_K7_PERFCTR1 0xC0010005 | ||
| 259 | #define MSR_K7_EVNTSEL2 0xC0010002 | ||
| 260 | #define MSR_K7_PERFCTR2 0xC0010006 | ||
| 261 | #define MSR_K7_EVNTSEL3 0xC0010003 | ||
| 262 | #define MSR_K7_PERFCTR3 0xC0010007 | ||
| 263 | #define MSR_K8_TOP_MEM1 0xC001001A | ||
| 264 | #define MSR_K8_TOP_MEM2 0xC001001D | ||
| 265 | #define MSR_K8_SYSCFG 0xC0010010 | ||
| 266 | #define MSR_K8_HWCR 0xC0010015 | ||
| 267 | |||
| 268 | /* K6 MSRs */ | ||
| 269 | #define MSR_K6_EFER 0xC0000080 | ||
| 270 | #define MSR_K6_STAR 0xC0000081 | ||
| 271 | #define MSR_K6_WHCR 0xC0000082 | ||
| 272 | #define MSR_K6_UWCCR 0xC0000085 | ||
| 273 | #define MSR_K6_PSOR 0xC0000087 | ||
| 274 | #define MSR_K6_PFIR 0xC0000088 | ||
| 275 | |||
| 276 | /* Centaur-Hauls/IDT defined MSRs. */ | ||
| 277 | #define MSR_IDT_FCR1 0x107 | ||
| 278 | #define MSR_IDT_FCR2 0x108 | ||
| 279 | #define MSR_IDT_FCR3 0x109 | ||
| 280 | #define MSR_IDT_FCR4 0x10a | ||
| 281 | |||
| 282 | #define MSR_IDT_MCR0 0x110 | ||
| 283 | #define MSR_IDT_MCR1 0x111 | ||
| 284 | #define MSR_IDT_MCR2 0x112 | ||
| 285 | #define MSR_IDT_MCR3 0x113 | ||
| 286 | #define MSR_IDT_MCR4 0x114 | ||
| 287 | #define MSR_IDT_MCR5 0x115 | ||
| 288 | #define MSR_IDT_MCR6 0x116 | ||
| 289 | #define MSR_IDT_MCR7 0x117 | ||
| 290 | #define MSR_IDT_MCR_CTRL 0x120 | ||
| 291 | |||
| 292 | /* VIA Cyrix defined MSRs*/ | ||
| 293 | #define MSR_VIA_FCR 0x1107 | ||
| 294 | #define MSR_VIA_LONGHAUL 0x110a | ||
| 295 | #define MSR_VIA_RNG 0x110b | ||
| 296 | #define MSR_VIA_BCR2 0x1147 | ||
| 297 | |||
| 298 | /* Intel defined MSRs. */ | ||
| 299 | #define MSR_IA32_P5_MC_ADDR 0 | ||
| 300 | #define MSR_IA32_P5_MC_TYPE 1 | ||
| 301 | #define MSR_IA32_PLATFORM_ID 0x17 | ||
| 302 | #define MSR_IA32_EBL_CR_POWERON 0x2a | ||
| 303 | |||
| 304 | #define MSR_IA32_APICBASE 0x1b | ||
| 305 | #define MSR_IA32_APICBASE_BSP (1<<8) | ||
| 306 | #define MSR_IA32_APICBASE_ENABLE (1<<11) | ||
| 307 | #define MSR_IA32_APICBASE_BASE (0xfffff<<12) | ||
| 308 | |||
| 309 | /* P4/Xeon+ specific */ | ||
| 310 | #define MSR_IA32_MCG_EAX 0x180 | ||
| 311 | #define MSR_IA32_MCG_EBX 0x181 | ||
| 312 | #define MSR_IA32_MCG_ECX 0x182 | ||
| 313 | #define MSR_IA32_MCG_EDX 0x183 | ||
| 314 | #define MSR_IA32_MCG_ESI 0x184 | ||
| 315 | #define MSR_IA32_MCG_EDI 0x185 | ||
| 316 | #define MSR_IA32_MCG_EBP 0x186 | ||
| 317 | #define MSR_IA32_MCG_ESP 0x187 | ||
| 318 | #define MSR_IA32_MCG_EFLAGS 0x188 | ||
| 319 | #define MSR_IA32_MCG_EIP 0x189 | ||
| 320 | #define MSR_IA32_MCG_RESERVED 0x18A | ||
| 321 | |||
| 322 | #define MSR_P6_EVNTSEL0 0x186 | ||
| 323 | #define MSR_P6_EVNTSEL1 0x187 | ||
| 324 | |||
| 325 | #define MSR_IA32_PERF_STATUS 0x198 | ||
| 326 | #define MSR_IA32_PERF_CTL 0x199 | ||
| 327 | |||
| 328 | #define MSR_IA32_MPERF 0xE7 | ||
| 329 | #define MSR_IA32_APERF 0xE8 | ||
| 330 | |||
| 331 | #define MSR_IA32_THERM_CONTROL 0x19a | ||
| 332 | #define MSR_IA32_THERM_INTERRUPT 0x19b | ||
| 333 | #define MSR_IA32_THERM_STATUS 0x19c | ||
| 334 | #define MSR_IA32_MISC_ENABLE 0x1a0 | ||
| 335 | |||
| 336 | #define MSR_IA32_DEBUGCTLMSR 0x1d9 | ||
| 337 | #define MSR_IA32_LASTBRANCHFROMIP 0x1db | ||
| 338 | #define MSR_IA32_LASTBRANCHTOIP 0x1dc | ||
| 339 | #define MSR_IA32_LASTINTFROMIP 0x1dd | ||
| 340 | #define MSR_IA32_LASTINTTOIP 0x1de | ||
| 341 | |||
| 342 | #define MSR_IA32_MC0_CTL 0x400 | ||
| 343 | #define MSR_IA32_MC0_STATUS 0x401 | ||
| 344 | #define MSR_IA32_MC0_ADDR 0x402 | ||
| 345 | #define MSR_IA32_MC0_MISC 0x403 | ||
| 346 | |||
| 347 | /* Pentium IV performance counter MSRs */ | ||
| 348 | #define MSR_P4_BPU_PERFCTR0 0x300 | ||
| 349 | #define MSR_P4_BPU_PERFCTR1 0x301 | ||
| 350 | #define MSR_P4_BPU_PERFCTR2 0x302 | ||
| 351 | #define MSR_P4_BPU_PERFCTR3 0x303 | ||
| 352 | #define MSR_P4_MS_PERFCTR0 0x304 | ||
| 353 | #define MSR_P4_MS_PERFCTR1 0x305 | ||
| 354 | #define MSR_P4_MS_PERFCTR2 0x306 | ||
| 355 | #define MSR_P4_MS_PERFCTR3 0x307 | ||
| 356 | #define MSR_P4_FLAME_PERFCTR0 0x308 | ||
| 357 | #define MSR_P4_FLAME_PERFCTR1 0x309 | ||
| 358 | #define MSR_P4_FLAME_PERFCTR2 0x30a | ||
| 359 | #define MSR_P4_FLAME_PERFCTR3 0x30b | ||
| 360 | #define MSR_P4_IQ_PERFCTR0 0x30c | ||
| 361 | #define MSR_P4_IQ_PERFCTR1 0x30d | ||
| 362 | #define MSR_P4_IQ_PERFCTR2 0x30e | ||
| 363 | #define MSR_P4_IQ_PERFCTR3 0x30f | ||
| 364 | #define MSR_P4_IQ_PERFCTR4 0x310 | ||
| 365 | #define MSR_P4_IQ_PERFCTR5 0x311 | ||
| 366 | #define MSR_P4_BPU_CCCR0 0x360 | ||
| 367 | #define MSR_P4_BPU_CCCR1 0x361 | ||
| 368 | #define MSR_P4_BPU_CCCR2 0x362 | ||
| 369 | #define MSR_P4_BPU_CCCR3 0x363 | ||
| 370 | #define MSR_P4_MS_CCCR0 0x364 | ||
| 371 | #define MSR_P4_MS_CCCR1 0x365 | ||
| 372 | #define MSR_P4_MS_CCCR2 0x366 | ||
| 373 | #define MSR_P4_MS_CCCR3 0x367 | ||
| 374 | #define MSR_P4_FLAME_CCCR0 0x368 | ||
| 375 | #define MSR_P4_FLAME_CCCR1 0x369 | ||
| 376 | #define MSR_P4_FLAME_CCCR2 0x36a | ||
| 377 | #define MSR_P4_FLAME_CCCR3 0x36b | ||
| 378 | #define MSR_P4_IQ_CCCR0 0x36c | ||
| 379 | #define MSR_P4_IQ_CCCR1 0x36d | ||
| 380 | #define MSR_P4_IQ_CCCR2 0x36e | ||
| 381 | #define MSR_P4_IQ_CCCR3 0x36f | ||
| 382 | #define MSR_P4_IQ_CCCR4 0x370 | ||
| 383 | #define MSR_P4_IQ_CCCR5 0x371 | ||
| 384 | #define MSR_P4_ALF_ESCR0 0x3ca | ||
| 385 | #define MSR_P4_ALF_ESCR1 0x3cb | ||
| 386 | #define MSR_P4_BPU_ESCR0 0x3b2 | ||
| 387 | #define MSR_P4_BPU_ESCR1 0x3b3 | ||
| 388 | #define MSR_P4_BSU_ESCR0 0x3a0 | ||
| 389 | #define MSR_P4_BSU_ESCR1 0x3a1 | ||
| 390 | #define MSR_P4_CRU_ESCR0 0x3b8 | ||
| 391 | #define MSR_P4_CRU_ESCR1 0x3b9 | ||
| 392 | #define MSR_P4_CRU_ESCR2 0x3cc | ||
| 393 | #define MSR_P4_CRU_ESCR3 0x3cd | ||
| 394 | #define MSR_P4_CRU_ESCR4 0x3e0 | ||
| 395 | #define MSR_P4_CRU_ESCR5 0x3e1 | ||
| 396 | #define MSR_P4_DAC_ESCR0 0x3a8 | ||
| 397 | #define MSR_P4_DAC_ESCR1 0x3a9 | ||
| 398 | #define MSR_P4_FIRM_ESCR0 0x3a4 | ||
| 399 | #define MSR_P4_FIRM_ESCR1 0x3a5 | ||
| 400 | #define MSR_P4_FLAME_ESCR0 0x3a6 | ||
| 401 | #define MSR_P4_FLAME_ESCR1 0x3a7 | ||
| 402 | #define MSR_P4_FSB_ESCR0 0x3a2 | ||
| 403 | #define MSR_P4_FSB_ESCR1 0x3a3 | ||
| 404 | #define MSR_P4_IQ_ESCR0 0x3ba | ||
| 405 | #define MSR_P4_IQ_ESCR1 0x3bb | ||
| 406 | #define MSR_P4_IS_ESCR0 0x3b4 | ||
| 407 | #define MSR_P4_IS_ESCR1 0x3b5 | ||
| 408 | #define MSR_P4_ITLB_ESCR0 0x3b6 | ||
| 409 | #define MSR_P4_ITLB_ESCR1 0x3b7 | ||
| 410 | #define MSR_P4_IX_ESCR0 0x3c8 | ||
| 411 | #define MSR_P4_IX_ESCR1 0x3c9 | ||
| 412 | #define MSR_P4_MOB_ESCR0 0x3aa | ||
| 413 | #define MSR_P4_MOB_ESCR1 0x3ab | ||
| 414 | #define MSR_P4_MS_ESCR0 0x3c0 | ||
| 415 | #define MSR_P4_MS_ESCR1 0x3c1 | ||
| 416 | #define MSR_P4_PMH_ESCR0 0x3ac | ||
| 417 | #define MSR_P4_PMH_ESCR1 0x3ad | ||
| 418 | #define MSR_P4_RAT_ESCR0 0x3bc | ||
| 419 | #define MSR_P4_RAT_ESCR1 0x3bd | ||
| 420 | #define MSR_P4_SAAT_ESCR0 0x3ae | ||
| 421 | #define MSR_P4_SAAT_ESCR1 0x3af | ||
| 422 | #define MSR_P4_SSU_ESCR0 0x3be | ||
| 423 | #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */ | ||
| 424 | #define MSR_P4_TBPU_ESCR0 0x3c2 | ||
| 425 | #define MSR_P4_TBPU_ESCR1 0x3c3 | ||
| 426 | #define MSR_P4_TC_ESCR0 0x3c4 | ||
| 427 | #define MSR_P4_TC_ESCR1 0x3c5 | ||
| 428 | #define MSR_P4_U2L_ESCR0 0x3b0 | ||
| 429 | #define MSR_P4_U2L_ESCR1 0x3b1 | ||
| 430 | |||
| 431 | /* Intel Core-based CPU performance counters */ | ||
| 432 | #define MSR_CORE_PERF_FIXED_CTR0 0x309 | ||
| 433 | #define MSR_CORE_PERF_FIXED_CTR1 0x30a | ||
| 434 | #define MSR_CORE_PERF_FIXED_CTR2 0x30b | ||
| 435 | #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d | ||
| 436 | #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e | ||
| 437 | #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f | ||
| 438 | #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 | ||
| 439 | |||
| 440 | #endif | ||
diff --git a/include/asm-x86_64/processor-flags.h b/include/asm-x86_64/processor-flags.h index 806112fb7985..ec99a57b2c6a 100644 --- a/include/asm-x86_64/processor-flags.h +++ b/include/asm-x86_64/processor-flags.h | |||
| @@ -1,26 +1 @@ | |||
| 1 | #ifndef __ASM_X86_64_PROCESSOR_FLAGS_H | #include <asm-i386/processor-flags.h> | |
| 2 | #define __ASM_X86_64_PROCESSOR_FLAGS_H | ||
| 3 | /* Various flags defined: can be included from assembler. */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * EFLAGS bits | ||
| 7 | */ | ||
| 8 | #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ | ||
| 9 | #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ | ||
| 10 | #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ | ||
| 11 | #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ | ||
| 12 | #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ | ||
| 13 | #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ | ||
| 14 | #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ | ||
| 15 | #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ | ||
| 16 | #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ | ||
| 17 | #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ | ||
| 18 | #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ | ||
| 19 | #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ | ||
| 20 | #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ | ||
| 21 | #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ | ||
| 22 | #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ | ||
| 23 | #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ | ||
| 24 | #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ | ||
| 25 | |||
| 26 | #endif /* __ASM_X86_64_PROCESSOR_FLAGS_H */ | ||
diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index 6a117349a5de..461ffe4c1fcc 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h | |||
| @@ -104,21 +104,6 @@ extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c); | |||
| 104 | extern unsigned short num_cache_leaves; | 104 | extern unsigned short num_cache_leaves; |
| 105 | 105 | ||
| 106 | /* | 106 | /* |
| 107 | * Intel CPU features in CR4 | ||
| 108 | */ | ||
| 109 | #define X86_CR4_VME 0x0001 /* enable vm86 extensions */ | ||
| 110 | #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */ | ||
| 111 | #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */ | ||
| 112 | #define X86_CR4_DE 0x0008 /* enable debugging extensions */ | ||
| 113 | #define X86_CR4_PSE 0x0010 /* enable page size extensions */ | ||
| 114 | #define X86_CR4_PAE 0x0020 /* enable physical address extensions */ | ||
| 115 | #define X86_CR4_MCE 0x0040 /* Machine check enable */ | ||
| 116 | #define X86_CR4_PGE 0x0080 /* enable global pages */ | ||
| 117 | #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */ | ||
| 118 | #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */ | ||
| 119 | #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */ | ||
| 120 | |||
| 121 | /* | ||
| 122 | * Save the cr4 feature set we're using (ie | 107 | * Save the cr4 feature set we're using (ie |
| 123 | * Pentium 4MB enable and PPro Global page | 108 | * Pentium 4MB enable and PPro Global page |
| 124 | * enable), so that any CPU's that boot up | 109 | * enable), so that any CPU's that boot up |
| @@ -407,22 +392,6 @@ static inline void prefetchw(void *x) | |||
| 407 | #define cpu_relax() rep_nop() | 392 | #define cpu_relax() rep_nop() |
| 408 | 393 | ||
| 409 | /* | 394 | /* |
| 410 | * NSC/Cyrix CPU configuration register indexes | ||
| 411 | */ | ||
| 412 | #define CX86_CCR0 0xc0 | ||
| 413 | #define CX86_CCR1 0xc1 | ||
| 414 | #define CX86_CCR2 0xc2 | ||
| 415 | #define CX86_CCR3 0xc3 | ||
| 416 | #define CX86_CCR4 0xe8 | ||
| 417 | #define CX86_CCR5 0xe9 | ||
| 418 | #define CX86_CCR6 0xea | ||
| 419 | #define CX86_CCR7 0xeb | ||
| 420 | #define CX86_DIR0 0xfe | ||
| 421 | #define CX86_DIR1 0xff | ||
| 422 | #define CX86_ARR_BASE 0xc4 | ||
| 423 | #define CX86_RCR_BASE 0xdc | ||
| 424 | |||
| 425 | /* | ||
| 426 | * NSC/Cyrix CPU indexed register access macros | 395 | * NSC/Cyrix CPU indexed register access macros |
| 427 | */ | 396 | */ |
| 428 | 397 | ||