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authorYitchak Gertner <gertner@broadcom.com>2008-08-13 18:50:23 -0400
committerDavid S. Miller <davem@davemloft.net>2008-08-13 19:02:32 -0400
commit4a37fb660c5505e0ee7ae16d80a06e85affe3055 (patch)
tree712f0e5d8288a095cf2b17674ad07ca44762abf3
parentda5a662a2326931bef25f0e534c9c1702f862399 (diff)
bnx2x: HW lock mechanism
HW lock mechanism Enhancing the HW lock to work per function and not only per port - this is needed for the next patch that protects races over HW attention detection between the different functions. At this chance, changing the functions names to be more inline with the current naming convention Signed-off-by: Yitchak Gertner <gertner@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/bnx2x_main.c102
-rw-r--r--drivers/net/bnx2x_reg.h17
2 files changed, 75 insertions, 44 deletions
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c
index dfa8c7b00cb7..3e86ff4f4d45 100644
--- a/drivers/net/bnx2x_main.c
+++ b/drivers/net/bnx2x_main.c
@@ -1693,11 +1693,12 @@ static void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event);
1693 * General service functions 1693 * General service functions
1694 */ 1694 */
1695 1695
1696static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource) 1696static int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1697{ 1697{
1698 u32 lock_status; 1698 u32 lock_status;
1699 u32 resource_bit = (1 << resource); 1699 u32 resource_bit = (1 << resource);
1700 u8 port = BP_PORT(bp); 1700 int func = BP_FUNC(bp);
1701 u32 hw_lock_control_reg;
1701 int cnt; 1702 int cnt;
1702 1703
1703 /* Validating that the resource is within range */ 1704 /* Validating that the resource is within range */
@@ -1708,8 +1709,15 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1708 return -EINVAL; 1709 return -EINVAL;
1709 } 1710 }
1710 1711
1712 if (func <= 5) {
1713 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1714 } else {
1715 hw_lock_control_reg =
1716 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1717 }
1718
1711 /* Validating that the resource is not already taken */ 1719 /* Validating that the resource is not already taken */
1712 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1720 lock_status = REG_RD(bp, hw_lock_control_reg);
1713 if (lock_status & resource_bit) { 1721 if (lock_status & resource_bit) {
1714 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1722 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1715 lock_status, resource_bit); 1723 lock_status, resource_bit);
@@ -1719,9 +1727,8 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1719 /* Try for 1 second every 5ms */ 1727 /* Try for 1 second every 5ms */
1720 for (cnt = 0; cnt < 200; cnt++) { 1728 for (cnt = 0; cnt < 200; cnt++) {
1721 /* Try to acquire the lock */ 1729 /* Try to acquire the lock */
1722 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8 + 4, 1730 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1723 resource_bit); 1731 lock_status = REG_RD(bp, hw_lock_control_reg);
1724 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8);
1725 if (lock_status & resource_bit) 1732 if (lock_status & resource_bit)
1726 return 0; 1733 return 0;
1727 1734
@@ -1731,11 +1738,12 @@ static int bnx2x_hw_lock(struct bnx2x *bp, u32 resource)
1731 return -EAGAIN; 1738 return -EAGAIN;
1732} 1739}
1733 1740
1734static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource) 1741static int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1735{ 1742{
1736 u32 lock_status; 1743 u32 lock_status;
1737 u32 resource_bit = (1 << resource); 1744 u32 resource_bit = (1 << resource);
1738 u8 port = BP_PORT(bp); 1745 int func = BP_FUNC(bp);
1746 u32 hw_lock_control_reg;
1739 1747
1740 /* Validating that the resource is within range */ 1748 /* Validating that the resource is within range */
1741 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1749 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
@@ -1745,20 +1753,27 @@ static int bnx2x_hw_unlock(struct bnx2x *bp, u32 resource)
1745 return -EINVAL; 1753 return -EINVAL;
1746 } 1754 }
1747 1755
1756 if (func <= 5) {
1757 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1758 } else {
1759 hw_lock_control_reg =
1760 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1761 }
1762
1748 /* Validating that the resource is currently taken */ 1763 /* Validating that the resource is currently taken */
1749 lock_status = REG_RD(bp, MISC_REG_DRIVER_CONTROL_1 + port*8); 1764 lock_status = REG_RD(bp, hw_lock_control_reg);
1750 if (!(lock_status & resource_bit)) { 1765 if (!(lock_status & resource_bit)) {
1751 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1766 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1752 lock_status, resource_bit); 1767 lock_status, resource_bit);
1753 return -EFAULT; 1768 return -EFAULT;
1754 } 1769 }
1755 1770
1756 REG_WR(bp, MISC_REG_DRIVER_CONTROL_1 + port*8, resource_bit); 1771 REG_WR(bp, hw_lock_control_reg, resource_bit);
1757 return 0; 1772 return 0;
1758} 1773}
1759 1774
1760/* HW Lock for shared dual port PHYs */ 1775/* HW Lock for shared dual port PHYs */
1761static void bnx2x_phy_hw_lock(struct bnx2x *bp) 1776static void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1762{ 1777{
1763 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1778 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1764 1779
@@ -1766,16 +1781,16 @@ static void bnx2x_phy_hw_lock(struct bnx2x *bp)
1766 1781
1767 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1782 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1768 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1783 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1769 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1784 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1770} 1785}
1771 1786
1772static void bnx2x_phy_hw_unlock(struct bnx2x *bp) 1787static void bnx2x_release_phy_lock(struct bnx2x *bp)
1773{ 1788{
1774 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config); 1789 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
1775 1790
1776 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) || 1791 if ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) ||
1777 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) 1792 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))
1778 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_8072_MDIO); 1793 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_8072_MDIO);
1779 1794
1780 mutex_unlock(&bp->port.phy_mutex); 1795 mutex_unlock(&bp->port.phy_mutex);
1781} 1796}
@@ -1795,7 +1810,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1795 return -EINVAL; 1810 return -EINVAL;
1796 } 1811 }
1797 1812
1798 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); 1813 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1799 /* read GPIO and mask except the float bits */ 1814 /* read GPIO and mask except the float bits */
1800 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1815 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1801 1816
@@ -1828,7 +1843,7 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode)
1828 } 1843 }
1829 1844
1830 REG_WR(bp, MISC_REG_GPIO, gpio_reg); 1845 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1831 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_GPIO); 1846 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1832 1847
1833 return 0; 1848 return 0;
1834} 1849}
@@ -1844,7 +1859,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1844 return -EINVAL; 1859 return -EINVAL;
1845 } 1860 }
1846 1861
1847 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); 1862 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1848 /* read SPIO and mask except the float bits */ 1863 /* read SPIO and mask except the float bits */
1849 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT); 1864 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1850 1865
@@ -1874,7 +1889,7 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1874 } 1889 }
1875 1890
1876 REG_WR(bp, MISC_REG_SPIO, spio_reg); 1891 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1877 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_SPIO); 1892 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1878 1893
1879 return 0; 1894 return 0;
1880} 1895}
@@ -1940,9 +1955,9 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1940 /* Initialize link parameters structure variables */ 1955 /* Initialize link parameters structure variables */
1941 bp->link_params.mtu = bp->dev->mtu; 1956 bp->link_params.mtu = bp->dev->mtu;
1942 1957
1943 bnx2x_phy_hw_lock(bp); 1958 bnx2x_acquire_phy_lock(bp);
1944 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1959 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1945 bnx2x_phy_hw_unlock(bp); 1960 bnx2x_release_phy_lock(bp);
1946 1961
1947 if (bp->link_vars.link_up) 1962 if (bp->link_vars.link_up)
1948 bnx2x_link_report(bp); 1963 bnx2x_link_report(bp);
@@ -1958,9 +1973,9 @@ static u8 bnx2x_initial_phy_init(struct bnx2x *bp)
1958static void bnx2x_link_set(struct bnx2x *bp) 1973static void bnx2x_link_set(struct bnx2x *bp)
1959{ 1974{
1960 if (!BP_NOMCP(bp)) { 1975 if (!BP_NOMCP(bp)) {
1961 bnx2x_phy_hw_lock(bp); 1976 bnx2x_acquire_phy_lock(bp);
1962 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1977 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1963 bnx2x_phy_hw_unlock(bp); 1978 bnx2x_release_phy_lock(bp);
1964 1979
1965 bnx2x_calc_fc_adv(bp); 1980 bnx2x_calc_fc_adv(bp);
1966 } else 1981 } else
@@ -1970,9 +1985,9 @@ static void bnx2x_link_set(struct bnx2x *bp)
1970static void bnx2x__link_reset(struct bnx2x *bp) 1985static void bnx2x__link_reset(struct bnx2x *bp)
1971{ 1986{
1972 if (!BP_NOMCP(bp)) { 1987 if (!BP_NOMCP(bp)) {
1973 bnx2x_phy_hw_lock(bp); 1988 bnx2x_acquire_phy_lock(bp);
1974 bnx2x_link_reset(&bp->link_params, &bp->link_vars); 1989 bnx2x_link_reset(&bp->link_params, &bp->link_vars);
1975 bnx2x_phy_hw_unlock(bp); 1990 bnx2x_release_phy_lock(bp);
1976 } else 1991 } else
1977 BNX2X_ERR("Bootcode is missing -not resetting link\n"); 1992 BNX2X_ERR("Bootcode is missing -not resetting link\n");
1978} 1993}
@@ -1981,9 +1996,9 @@ static u8 bnx2x_link_test(struct bnx2x *bp)
1981{ 1996{
1982 u8 rc; 1997 u8 rc;
1983 1998
1984 bnx2x_phy_hw_lock(bp); 1999 bnx2x_acquire_phy_lock(bp);
1985 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars); 2000 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars);
1986 bnx2x_phy_hw_unlock(bp); 2001 bnx2x_release_phy_lock(bp);
1987 2002
1988 return rc; 2003 return rc;
1989} 2004}
@@ -2207,9 +2222,9 @@ static void bnx2x_link_attn(struct bnx2x *bp)
2207 /* Make sure that we are synced with the current statistics */ 2222 /* Make sure that we are synced with the current statistics */
2208 bnx2x_stats_handle(bp, STATS_EVENT_STOP); 2223 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2209 2224
2210 bnx2x_phy_hw_lock(bp); 2225 bnx2x_acquire_phy_lock(bp);
2211 bnx2x_link_update(&bp->link_params, &bp->link_vars); 2226 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2212 bnx2x_phy_hw_unlock(bp); 2227 bnx2x_release_phy_lock(bp);
2213 2228
2214 if (bp->link_vars.link_up) { 2229 if (bp->link_vars.link_up) {
2215 2230
@@ -2361,7 +2376,7 @@ static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2361} 2376}
2362 2377
2363/* acquire split MCP access lock register */ 2378/* acquire split MCP access lock register */
2364static int bnx2x_lock_alr(struct bnx2x *bp) 2379static int bnx2x_acquire_alr(struct bnx2x *bp)
2365{ 2380{
2366 u32 i, j, val; 2381 u32 i, j, val;
2367 int rc = 0; 2382 int rc = 0;
@@ -2385,8 +2400,8 @@ static int bnx2x_lock_alr(struct bnx2x *bp)
2385 return rc; 2400 return rc;
2386} 2401}
2387 2402
2388/* Release split MCP access lock register */ 2403/* release split MCP access lock register */
2389static void bnx2x_unlock_alr(struct bnx2x *bp) 2404static void bnx2x_release_alr(struct bnx2x *bp)
2390{ 2405{
2391 u32 val = 0; 2406 u32 val = 0;
2392 2407
@@ -2399,7 +2414,6 @@ static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2399 u16 rc = 0; 2414 u16 rc = 0;
2400 2415
2401 barrier(); /* status block is written to by the chip */ 2416 barrier(); /* status block is written to by the chip */
2402
2403 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 2417 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2404 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; 2418 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2405 rc |= 1; 2419 rc |= 1;
@@ -2706,7 +2720,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2706 2720
2707 /* need to take HW lock because MCP or other port might also 2721 /* need to take HW lock because MCP or other port might also
2708 try to handle this event */ 2722 try to handle this event */
2709 bnx2x_lock_alr(bp); 2723 bnx2x_acquire_alr(bp);
2710 2724
2711 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 2725 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
2712 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 2726 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
@@ -2742,7 +2756,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
2742 } 2756 }
2743 } 2757 }
2744 2758
2745 bnx2x_unlock_alr(bp); 2759 bnx2x_release_alr(bp);
2746 2760
2747 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8; 2761 reg_addr = (IGU_ADDR_ATTN_BITS_CLR + IGU_FUNC_BASE * BP_FUNC(bp)) * 8;
2748 2762
@@ -6767,7 +6781,7 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6767 /* Check if it is the UNDI driver 6781 /* Check if it is the UNDI driver
6768 * UNDI driver initializes CID offset for normal bell to 0x7 6782 * UNDI driver initializes CID offset for normal bell to 0x7
6769 */ 6783 */
6770 bnx2x_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); 6784 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6771 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); 6785 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
6772 if (val == 0x7) { 6786 if (val == 0x7) {
6773 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 6787 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
@@ -6846,7 +6860,7 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
6846 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) & 6860 (SHMEM_RD(bp, func_mb[bp->func].drv_mb_header) &
6847 DRV_MSG_SEQ_NUMBER_MASK); 6861 DRV_MSG_SEQ_NUMBER_MASK);
6848 } 6862 }
6849 bnx2x_hw_unlock(bp, HW_LOCK_RESOURCE_UNDI); 6863 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
6850 } 6864 }
6851} 6865}
6852 6866
@@ -7703,11 +7717,11 @@ static void bnx2x_get_drvinfo(struct net_device *dev,
7703 7717
7704 phy_fw_ver[0] = '\0'; 7718 phy_fw_ver[0] = '\0';
7705 if (bp->port.pmf) { 7719 if (bp->port.pmf) {
7706 bnx2x_phy_hw_lock(bp); 7720 bnx2x_acquire_phy_lock(bp);
7707 bnx2x_get_ext_phy_fw_version(&bp->link_params, 7721 bnx2x_get_ext_phy_fw_version(&bp->link_params,
7708 (bp->state != BNX2X_STATE_CLOSED), 7722 (bp->state != BNX2X_STATE_CLOSED),
7709 phy_fw_ver, PHY_FW_VER_LEN); 7723 phy_fw_ver, PHY_FW_VER_LEN);
7710 bnx2x_phy_hw_unlock(bp); 7724 bnx2x_release_phy_lock(bp);
7711 } 7725 }
7712 7726
7713 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s", 7727 snprintf(info->fw_version, 32, "%d.%d.%d:%d BC:%x%s%s",
@@ -8165,7 +8179,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8165 if (eeprom->magic == 0x00504859) 8179 if (eeprom->magic == 0x00504859)
8166 if (bp->port.pmf) { 8180 if (bp->port.pmf) {
8167 8181
8168 bnx2x_phy_hw_lock(bp); 8182 bnx2x_acquire_phy_lock(bp);
8169 rc = bnx2x_flash_download(bp, BP_PORT(bp), 8183 rc = bnx2x_flash_download(bp, BP_PORT(bp),
8170 bp->link_params.ext_phy_config, 8184 bp->link_params.ext_phy_config,
8171 (bp->state != BNX2X_STATE_CLOSED), 8185 (bp->state != BNX2X_STATE_CLOSED),
@@ -8177,7 +8191,7 @@ static int bnx2x_set_eeprom(struct net_device *dev,
8177 rc |= bnx2x_phy_init(&bp->link_params, 8191 rc |= bnx2x_phy_init(&bp->link_params,
8178 &bp->link_vars); 8192 &bp->link_vars);
8179 } 8193 }
8180 bnx2x_phy_hw_unlock(bp); 8194 bnx2x_release_phy_lock(bp);
8181 8195
8182 } else /* Only the PMF can access the PHY */ 8196 } else /* Only the PMF can access the PHY */
8183 return -EINVAL; 8197 return -EINVAL;
@@ -8601,15 +8615,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
8601 8615
8602 if (loopback_mode == BNX2X_MAC_LOOPBACK) { 8616 if (loopback_mode == BNX2X_MAC_LOOPBACK) {
8603 bp->link_params.loopback_mode = LOOPBACK_BMAC; 8617 bp->link_params.loopback_mode = LOOPBACK_BMAC;
8604 bnx2x_phy_hw_lock(bp); 8618 bnx2x_acquire_phy_lock(bp);
8605 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8619 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8606 bnx2x_phy_hw_unlock(bp); 8620 bnx2x_release_phy_lock(bp);
8607 8621
8608 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) { 8622 } else if (loopback_mode == BNX2X_PHY_LOOPBACK) {
8609 bp->link_params.loopback_mode = LOOPBACK_XGXS_10; 8623 bp->link_params.loopback_mode = LOOPBACK_XGXS_10;
8610 bnx2x_phy_hw_lock(bp); 8624 bnx2x_acquire_phy_lock(bp);
8611 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 8625 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
8612 bnx2x_phy_hw_unlock(bp); 8626 bnx2x_release_phy_lock(bp);
8613 /* wait until link state is restored */ 8627 /* wait until link state is restored */
8614 bnx2x_wait_for_link(bp, link_up); 8628 bnx2x_wait_for_link(bp, link_up);
8615 8629
diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index b5313c209caa..3f65dffb6d76 100644
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -1372,6 +1372,23 @@
1372 be asserted). */ 1372 be asserted). */
1373#define MISC_REG_DRIVER_CONTROL_16 0xa5f0 1373#define MISC_REG_DRIVER_CONTROL_16 0xa5f0
1374#define MISC_REG_DRIVER_CONTROL_16_SIZE 2 1374#define MISC_REG_DRIVER_CONTROL_16_SIZE 2
1375/* [RW 32] The following driver registers(1...16) represent 16 drivers and
1376 32 clients. Each client can be controlled by one driver only. One in each
1377 bit represent that this driver control the appropriate client (Ex: bit 5
1378 is set means this driver control client number 5). addr1 = set; addr0 =
1379 clear; read from both addresses will give the same result = status. write
1380 to address 1 will set a request to control all the clients that their
1381 appropriate bit (in the write command) is set. if the client is free (the
1382 appropriate bit in all the other drivers is clear) one will be written to
1383 that driver register; if the client isn't free the bit will remain zero.
1384 if the appropriate bit is set (the driver request to gain control on a
1385 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1386 interrupt will be asserted). write to address 0 will set a request to
1387 free all the clients that their appropriate bit (in the write command) is
1388 set. if the appropriate bit is clear (the driver request to free a client
1389 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1390 be asserted). */
1391#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1375/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1392/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1376 only. */ 1393 only. */
1377#define MISC_REG_E1HMF_MODE 0xa5f8 1394#define MISC_REG_E1HMF_MODE 0xa5f8