diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-19 14:49:33 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-19 14:49:33 -0400 |
commit | 349e1fba7e63b1067b5915337986060c13d9edd0 (patch) | |
tree | 7450f8355fb7f050066aab3fb94c1073e2080f7a | |
parent | fa9dc265ace9774e62f0e31108e5f47911124bda (diff) | |
parent | 504d36e91ac12ccdb0e1193cee7bef9831a1c99e (diff) |
Merge branch 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux
* 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux: (98 commits)
Input: s3c24xx_ts - depend on SAMSUNG_DEV_TS and update menu entry
Input: s3c24xx_ts - Add FEAT for Samsung touchscreen support
Input: s3c24xx_ts - Implement generic GPIO configuration callback
ARM: SAMSUNG: Move s3c64xx dev-ts.c to plat-samsung and rename configuration
ARM: SAMSUNG: Implements cfg_gpio function for Samsung touchscreen
ARM: S3C64XX: Add touchscreen platform device definition
ARM: SAMSUNG: Move mach/ts.h to plat/ts.h
ARM: S5PC100: Move i2c helpers from plat-s5pc1xx to mach-s5pc100
ARM: S5PC100: Move frame buffer helpers from plat-s5pc1xx to mach-s5pc100
ARM: S5PC100: gpio.h cleanup
ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100
ARM: S5PC100: Use common functions for gpiolib implementation
drivers: serial: S5PC100 serial driver cleanup
ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move
ARM: SAMSUNG: Copy common I2C0 device helpers to machine directories
ARM: SAMSUNG: move driver strength gpio configuration helper to common dir
ARM: S5PV210: Add GPIOlib support
ARM: SAMSUNGy: fix broken timer irq base
ARM: SMDK6440: Add audio devices on board
ARM: S5P6440: Add audio platform devices
...
124 files changed, 6649 insertions, 717 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index d5af3b024300..4b857fbe4314 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__ | |||
110 | head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o | 110 | head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o |
111 | textofs-y := 0x00008000 | 111 | textofs-y := 0x00008000 |
112 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 | 112 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 |
113 | # We don't want the htc bootloader to corrupt kernel during resume | ||
114 | textofs-$(CONFIG_PM_H1940) := 0x00108000 | ||
113 | # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory | 115 | # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory |
114 | ifeq ($(CONFIG_ARCH_SA1100),y) | 116 | ifeq ($(CONFIG_ARCH_SA1100),y) |
115 | textofs-$(CONFIG_SA1111) := 0x00208000 | 117 | textofs-$(CONFIG_SA1111) := 0x00208000 |
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 9e5e96f12d86..7245a55795dc 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
@@ -77,6 +77,7 @@ config ARCH_H1940 | |||
77 | select PM_H1940 if PM | 77 | select PM_H1940 if PM |
78 | select S3C_DEV_USB_HOST | 78 | select S3C_DEV_USB_HOST |
79 | select S3C_DEV_NAND | 79 | select S3C_DEV_NAND |
80 | select S3C2410_SETUP_TS | ||
80 | help | 81 | help |
81 | Say Y here if you are using the HP IPAQ H1940 | 82 | Say Y here if you are using the HP IPAQ H1940 |
82 | 83 | ||
@@ -96,12 +97,19 @@ config PM_H1940 | |||
96 | config MACH_N30 | 97 | config MACH_N30 |
97 | bool "Acer N30 family" | 98 | bool "Acer N30 family" |
98 | select CPU_S3C2410 | 99 | select CPU_S3C2410 |
100 | select MACH_N35 | ||
99 | select S3C_DEV_USB_HOST | 101 | select S3C_DEV_USB_HOST |
100 | select S3C_DEV_NAND | 102 | select S3C_DEV_NAND |
101 | help | 103 | help |
102 | Say Y here if you want suppt for the Acer N30, Acer N35, | 104 | Say Y here if you want suppt for the Acer N30, Acer N35, |
103 | Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. | 105 | Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. |
104 | 106 | ||
107 | config MACH_N35 | ||
108 | bool | ||
109 | help | ||
110 | Internal node in order to enable support for Acer N35 if Acer N30 is | ||
111 | selected. | ||
112 | |||
105 | config ARCH_BAST | 113 | config ARCH_BAST |
106 | bool "Simtec Electronics BAST (EB2410ITX)" | 114 | bool "Simtec Electronics BAST (EB2410ITX)" |
107 | select CPU_S3C2410 | 115 | select CPU_S3C2410 |
@@ -111,6 +119,7 @@ config ARCH_BAST | |||
111 | select MACH_BAST_IDE | 119 | select MACH_BAST_IDE |
112 | select S3C24XX_DCLK | 120 | select S3C24XX_DCLK |
113 | select ISA | 121 | select ISA |
122 | select S3C_DEV_HWMON | ||
114 | select S3C_DEV_USB_HOST | 123 | select S3C_DEV_USB_HOST |
115 | select S3C_DEV_NAND | 124 | select S3C_DEV_NAND |
116 | help | 125 | help |
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot index 7dab2a0325b5..58c1dd7f8e1d 100644 --- a/arch/arm/mach-s3c2410/Makefile.boot +++ b/arch/arm/mach-s3c2410/Makefile.boot | |||
@@ -1,3 +1,7 @@ | |||
1 | zreladdr-y := 0x30008000 | 1 | ifeq ($(CONFIG_PM_H1940),y) |
2 | params_phys-y := 0x30000100 | 2 | zreladdr-y := 0x30108000 |
3 | 3 | params_phys-y := 0x30100100 | |
4 | else | ||
5 | zreladdr-y := 0x30008000 | ||
6 | params_phys-y := 0x30000100 | ||
7 | endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h index f3182ff847cb..4f7bf3272e87 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | |||
@@ -16,15 +16,28 @@ | |||
16 | 16 | ||
17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | 17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) |
18 | 18 | ||
19 | #define S3C2410_GPIO_BANKA (32*0) | ||
20 | #define S3C2410_GPIO_BANKB (32*1) | ||
21 | #define S3C2410_GPIO_BANKC (32*2) | ||
22 | #define S3C2410_GPIO_BANKD (32*3) | ||
23 | #define S3C2410_GPIO_BANKE (32*4) | ||
24 | #define S3C2410_GPIO_BANKF (32*5) | ||
25 | #define S3C2410_GPIO_BANKG (32*6) | 19 | #define S3C2410_GPIO_BANKG (32*6) |
26 | #define S3C2410_GPIO_BANKH (32*7) | 20 | #define S3C2410_GPIO_BANKH (32*7) |
27 | 21 | ||
22 | /* GPIO sizes for various SoCs: | ||
23 | * | ||
24 | * 2442 | ||
25 | * 2410 2412 2440 2443 2416 | ||
26 | * ---- ---- ---- ---- ---- | ||
27 | * A 23 22 25 16 25 | ||
28 | * B 11 11 11 11 9 | ||
29 | * C 16 15 16 16 16 | ||
30 | * D 16 16 16 16 16 | ||
31 | * E 16 16 16 16 16 | ||
32 | * F 8 8 8 8 8 | ||
33 | * G 16 16 16 16 8 | ||
34 | * H 11 11 9 15 15 | ||
35 | * J -- -- 13 16 -- | ||
36 | * K -- -- -- -- 16 | ||
37 | * L -- -- -- 15 7 | ||
38 | * M -- -- -- 2 2 | ||
39 | */ | ||
40 | |||
28 | /* GPIO bank sizes */ | 41 | /* GPIO bank sizes */ |
29 | #define S3C2410_GPIO_A_NR (32) | 42 | #define S3C2410_GPIO_A_NR (32) |
30 | #define S3C2410_GPIO_B_NR (32) | 43 | #define S3C2410_GPIO_B_NR (32) |
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index acb259103808..d67819dde42a 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h | |||
@@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) | |||
23 | { | 23 | { |
24 | struct s3c_gpio_chip *chip; | 24 | struct s3c_gpio_chip *chip; |
25 | 25 | ||
26 | if (pin > S3C2410_GPG(10)) | 26 | if (pin > S3C_GPIO_END) |
27 | return NULL; | 27 | return NULL; |
28 | 28 | ||
29 | chip = &s3c24xx_gpios[pin/32]; | 29 | chip = &s3c24xx_gpios[pin/32]; |
30 | return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL; | 30 | return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL; |
31 | } | 31 | } |
32 | 32 | ||
33 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | 33 | #endif /* __ASM_ARCH_GPIO_CORE_H */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 15f0b3e7ce69..b649bf2ccd5c 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h | |||
@@ -20,10 +20,18 @@ | |||
20 | * devices that need GPIO. | 20 | * devices that need GPIO. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifdef CONFIG_CPU_S3C244X | ||
24 | #define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA) | ||
25 | #else | ||
23 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) | 26 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) |
27 | #endif | ||
24 | 28 | ||
25 | #include <asm-generic/gpio.h> | 29 | #include <asm-generic/gpio.h> |
26 | #include <mach/gpio-nrs.h> | 30 | #include <mach/gpio-nrs.h> |
27 | #include <mach/gpio-fns.h> | 31 | #include <mach/gpio-fns.h> |
28 | 32 | ||
33 | #ifdef CONFIG_CPU_S3C24XX | ||
34 | #define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32) | ||
35 | #else | ||
29 | #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) | 36 | #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) |
37 | #endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 877c15e1b154..11bb0f08fe6a 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
@@ -187,6 +187,9 @@ | |||
187 | #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 | 187 | #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 |
188 | #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 | 188 | #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 |
189 | 189 | ||
190 | #define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3 | ||
191 | #define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2 | ||
192 | |||
190 | #ifdef CONFIG_CPU_S3C2440 | 193 | #ifdef CONFIG_CPU_S3C2440 |
191 | #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 | 194 | #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 |
192 | #else | 195 | #else |
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index f07d68066d7e..091c98a639d9 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h | |||
@@ -67,6 +67,8 @@ | |||
67 | #define S3C2443_PA_HSMMC (0x4A800000) | 67 | #define S3C2443_PA_HSMMC (0x4A800000) |
68 | #define S3C2416_PA_HSMMC0 (0x4AC00000) | 68 | #define S3C2416_PA_HSMMC0 (0x4AC00000) |
69 | 69 | ||
70 | #define S3C2443_PA_FB (0x4C800000) | ||
71 | |||
70 | /* S3C2412 memory and IO controls */ | 72 | /* S3C2412 memory and IO controls */ |
71 | #define S3C2412_PA_SSMC (0x4F000000) | 73 | #define S3C2412_PA_SSMC (0x4F000000) |
72 | #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) | 74 | #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) |
@@ -106,6 +108,7 @@ | |||
106 | #define S3C24XX_PA_SDI S3C2410_PA_SDI | 108 | #define S3C24XX_PA_SDI S3C2410_PA_SDI |
107 | #define S3C24XX_PA_NAND S3C2410_PA_NAND | 109 | #define S3C24XX_PA_NAND S3C2410_PA_NAND |
108 | 110 | ||
111 | #define S3C_PA_FB S3C2443_PA_FB | ||
109 | #define S3C_PA_IIC S3C2410_PA_IIC | 112 | #define S3C_PA_IIC S3C2410_PA_IIC |
110 | #define S3C_PA_UART S3C24XX_PA_UART | 113 | #define S3C_PA_UART S3C24XX_PA_UART |
111 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST | 114 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index a6384239eddf..a0a89d429296 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -17,29 +17,11 @@ | |||
17 | #include <mach/gpio-nrs.h> | 17 | #include <mach/gpio-nrs.h> |
18 | 18 | ||
19 | #ifdef CONFIG_CPU_S3C2400 | 19 | #ifdef CONFIG_CPU_S3C2400 |
20 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | 20 | #define S3C24XX_MISCCR S3C2400_MISCCR |
21 | #define S3C24XX_MISCCR S3C2400_MISCCR | ||
22 | #else | 21 | #else |
23 | #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) | 22 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) |
24 | #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80) | ||
25 | #endif /* CONFIG_CPU_S3C2400 */ | 23 | #endif /* CONFIG_CPU_S3C2400 */ |
26 | 24 | ||
27 | |||
28 | /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */ | ||
29 | |||
30 | #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32) | ||
31 | #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2)) | ||
32 | #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \ | ||
33 | (2 * (S3C2400_BANKNUM(pin)-2))) | ||
34 | |||
35 | #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \ | ||
36 | S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \ | ||
37 | S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO) | ||
38 | |||
39 | |||
40 | #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO) | ||
41 | #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31) | ||
42 | |||
43 | /* general configuration options */ | 25 | /* general configuration options */ |
44 | 26 | ||
45 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) | 27 | #define S3C2410_GPIO_LEAVE (0xFFFFFFFF) |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h index d87ebe0cb625..08ab9dfb6ae6 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h | |||
@@ -83,8 +83,7 @@ | |||
83 | #define S3C2443_HCLKCON_DMA4 (1<<4) | 83 | #define S3C2443_HCLKCON_DMA4 (1<<4) |
84 | #define S3C2443_HCLKCON_DMA5 (1<<5) | 84 | #define S3C2443_HCLKCON_DMA5 (1<<5) |
85 | #define S3C2443_HCLKCON_CAMIF (1<<8) | 85 | #define S3C2443_HCLKCON_CAMIF (1<<8) |
86 | #define S3C2443_HCLKCON_DISP (1<<9) | 86 | #define S3C2443_HCLKCON_LCDC (1<<9) |
87 | #define S3C2443_HCLKCON_LCDC (1<<10) | ||
88 | #define S3C2443_HCLKCON_USBH (1<<11) | 87 | #define S3C2443_HCLKCON_USBH (1<<11) |
89 | #define S3C2443_HCLKCON_USBD (1<<12) | 88 | #define S3C2443_HCLKCON_USBD (1<<12) |
90 | #define S3C2443_HCLKCON_HSMMC (1<<16) | 89 | #define S3C2443_HCLKCON_HSMMC (1<<16) |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index b061ddcf3067..c1f90f6fab42 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
@@ -633,7 +633,7 @@ static void __init bast_map_io(void) | |||
633 | 633 | ||
634 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); | 634 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
635 | 635 | ||
636 | s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; | 636 | s3c_hwmon_set_platdata(&bast_hwmon_info); |
637 | 637 | ||
638 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | 638 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
639 | s3c24xx_init_clocks(0); | 639 | s3c24xx_init_clocks(0); |
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 9531b4c41deb..779b45b3f80f 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
@@ -46,7 +46,6 @@ | |||
46 | #include <mach/h1940.h> | 46 | #include <mach/h1940.h> |
47 | #include <mach/h1940-latch.h> | 47 | #include <mach/h1940-latch.h> |
48 | #include <mach/fb.h> | 48 | #include <mach/fb.h> |
49 | #include <mach/ts.h> | ||
50 | #include <plat/udc.h> | 49 | #include <plat/udc.h> |
51 | #include <plat/iic.h> | 50 | #include <plat/iic.h> |
52 | 51 | ||
@@ -57,6 +56,7 @@ | |||
57 | #include <plat/pll.h> | 56 | #include <plat/pll.h> |
58 | #include <plat/pm.h> | 57 | #include <plat/pm.h> |
59 | #include <plat/mci.h> | 58 | #include <plat/mci.h> |
59 | #include <plat/ts.h> | ||
60 | 60 | ||
61 | static struct map_desc h1940_iodesc[] __initdata = { | 61 | static struct map_desc h1940_iodesc[] __initdata = { |
62 | [0] = { | 62 | [0] = { |
@@ -146,6 +146,7 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { | |||
146 | .delay = 10000, | 146 | .delay = 10000, |
147 | .presc = 49, | 147 | .presc = 49, |
148 | .oversampling_shift = 2, | 148 | .oversampling_shift = 2, |
149 | .cfg_gpio = s3c24xx_ts_cfg_gpio, | ||
149 | }; | 150 | }; |
150 | 151 | ||
151 | /** | 152 | /** |
@@ -163,8 +164,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = { | |||
163 | .xres = 240, | 164 | .xres = 240, |
164 | .yres = 320, | 165 | .yres = 320, |
165 | .bpp = 16, | 166 | .bpp = 16, |
166 | .left_margin = 20, | 167 | .left_margin = 8, |
167 | .right_margin = 8, | 168 | .right_margin = 20, |
168 | .hsync_len = 4, | 169 | .hsync_len = 4, |
169 | .upper_margin = 8, | 170 | .upper_margin = 8, |
170 | .lower_margin = 7, | 171 | .lower_margin = 7, |
@@ -272,7 +273,6 @@ static struct platform_device h1940_lcd_powerdev = { | |||
272 | }; | 273 | }; |
273 | 274 | ||
274 | static struct platform_device *h1940_devices[] __initdata = { | 275 | static struct platform_device *h1940_devices[] __initdata = { |
275 | &s3c_device_ts, | ||
276 | &s3c_device_ohci, | 276 | &s3c_device_ohci, |
277 | &s3c_device_lcd, | 277 | &s3c_device_lcd, |
278 | &s3c_device_wdt, | 278 | &s3c_device_wdt, |
@@ -286,6 +286,8 @@ static struct platform_device *h1940_devices[] __initdata = { | |||
286 | &s3c_device_timer[0], | 286 | &s3c_device_timer[0], |
287 | &h1940_backlight, | 287 | &h1940_backlight, |
288 | &h1940_lcd_powerdev, | 288 | &h1940_lcd_powerdev, |
289 | &s3c_device_adc, | ||
290 | &s3c_device_ts, | ||
289 | }; | 291 | }; |
290 | 292 | ||
291 | static void __init h1940_map_io(void) | 293 | static void __init h1940_map_io(void) |
@@ -339,7 +341,7 @@ static void __init h1940_init(void) | |||
339 | } | 341 | } |
340 | 342 | ||
341 | MACHINE_START(H1940, "IPAQ-H1940") | 343 | MACHINE_START(H1940, "IPAQ-H1940") |
342 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 344 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
343 | .phys_io = S3C2410_PA_UART, | 345 | .phys_io = S3C2410_PA_UART, |
344 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 346 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
345 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 347 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 75a9fd37a467..41f299d983eb 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/serial_core.h> | 26 | #include <linux/serial_core.h> |
27 | #include <linux/timer.h> | 27 | #include <linux/timer.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/mmc/host.h> | ||
29 | 30 | ||
30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
@@ -46,6 +47,7 @@ | |||
46 | #include <plat/clock.h> | 47 | #include <plat/clock.h> |
47 | #include <plat/cpu.h> | 48 | #include <plat/cpu.h> |
48 | #include <plat/devs.h> | 49 | #include <plat/devs.h> |
50 | #include <plat/mci.h> | ||
49 | #include <plat/s3c2410.h> | 51 | #include <plat/s3c2410.h> |
50 | #include <plat/udc.h> | 52 | #include <plat/udc.h> |
51 | 53 | ||
@@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = { | |||
172 | { | 174 | { |
173 | .gpio = S3C2410_GPF(0), | 175 | .gpio = S3C2410_GPF(0), |
174 | .code = KEY_POWER, | 176 | .code = KEY_POWER, |
177 | .type = EV_PWR, | ||
175 | .desc = "Power", | 178 | .desc = "Power", |
176 | .active_low = 0, | 179 | .active_low = 0, |
180 | .wakeup = 1, | ||
177 | }, | 181 | }, |
178 | { | 182 | { |
179 | .gpio = S3C2410_GPG(9), | 183 | .gpio = S3C2410_GPG(9), |
@@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { | |||
264 | .def_trigger = "", | 268 | .def_trigger = "", |
265 | }; | 269 | }; |
266 | 270 | ||
271 | /* This is the blue LED on the device. Originaly used to indicate GPS activity | ||
272 | * by flashing. */ | ||
273 | static struct s3c24xx_led_platdata n35_blue_led_pdata = { | ||
274 | .name = "blue_led", | ||
275 | .gpio = S3C2410_GPD(8), | ||
276 | .def_trigger = "", | ||
277 | }; | ||
278 | |||
267 | /* This LED is driven by the battery microcontroller, and is blinking | 279 | /* This LED is driven by the battery microcontroller, and is blinking |
268 | * red, blinking green or solid green when the battery is low, | 280 | * red, blinking green or solid green when the battery is low, |
269 | * charging or full respectively. By driving GPD9 low, it's possible | 281 | * charging or full respectively. By driving GPD9 low, it's possible |
@@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = { | |||
275 | .def_trigger = "", | 287 | .def_trigger = "", |
276 | }; | 288 | }; |
277 | 289 | ||
290 | static struct s3c24xx_led_platdata n35_warning_led_pdata = { | ||
291 | .name = "warning_led", | ||
292 | .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE, | ||
293 | .gpio = S3C2410_GPD(9), | ||
294 | .def_trigger = "", | ||
295 | }; | ||
296 | |||
278 | static struct platform_device n30_blue_led = { | 297 | static struct platform_device n30_blue_led = { |
279 | .name = "s3c24xx_led", | 298 | .name = "s3c24xx_led", |
280 | .id = 1, | 299 | .id = 1, |
@@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = { | |||
283 | }, | 302 | }, |
284 | }; | 303 | }; |
285 | 304 | ||
305 | static struct platform_device n35_blue_led = { | ||
306 | .name = "s3c24xx_led", | ||
307 | .id = 1, | ||
308 | .dev = { | ||
309 | .platform_data = &n35_blue_led_pdata, | ||
310 | }, | ||
311 | }; | ||
312 | |||
286 | static struct platform_device n30_warning_led = { | 313 | static struct platform_device n30_warning_led = { |
287 | .name = "s3c24xx_led", | 314 | .name = "s3c24xx_led", |
288 | .id = 2, | 315 | .id = 2, |
@@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = { | |||
291 | }, | 318 | }, |
292 | }; | 319 | }; |
293 | 320 | ||
321 | static struct platform_device n35_warning_led = { | ||
322 | .name = "s3c24xx_led", | ||
323 | .id = 2, | ||
324 | .dev = { | ||
325 | .platform_data = &n35_warning_led_pdata, | ||
326 | }, | ||
327 | }; | ||
328 | |||
294 | static struct s3c2410fb_display n30_display __initdata = { | 329 | static struct s3c2410fb_display n30_display __initdata = { |
295 | .type = S3C2410_LCDCON1_TFT, | 330 | .type = S3C2410_LCDCON1_TFT, |
296 | .width = 240, | 331 | .width = 240, |
@@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { | |||
317 | .lpcsel = 0x06, | 352 | .lpcsel = 0x06, |
318 | }; | 353 | }; |
319 | 354 | ||
355 | static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd) | ||
356 | { | ||
357 | switch (power_mode) { | ||
358 | case MMC_POWER_ON: | ||
359 | case MMC_POWER_UP: | ||
360 | gpio_set_value(S3C2410_GPG(4), 1); | ||
361 | break; | ||
362 | case MMC_POWER_OFF: | ||
363 | default: | ||
364 | gpio_set_value(S3C2410_GPG(4), 0); | ||
365 | break; | ||
366 | } | ||
367 | } | ||
368 | |||
369 | static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = { | ||
370 | .gpio_detect = S3C2410_GPF(1), | ||
371 | .gpio_wprotect = S3C2410_GPG(10), | ||
372 | .ocr_avail = MMC_VDD_32_33, | ||
373 | .set_power = n30_sdi_set_power, | ||
374 | }; | ||
375 | |||
320 | static struct platform_device *n30_devices[] __initdata = { | 376 | static struct platform_device *n30_devices[] __initdata = { |
321 | &s3c_device_lcd, | 377 | &s3c_device_lcd, |
322 | &s3c_device_wdt, | 378 | &s3c_device_wdt, |
323 | &s3c_device_i2c0, | 379 | &s3c_device_i2c0, |
324 | &s3c_device_iis, | 380 | &s3c_device_iis, |
325 | &s3c_device_ohci, | 381 | &s3c_device_ohci, |
382 | &s3c_device_rtc, | ||
326 | &s3c_device_usbgadget, | 383 | &s3c_device_usbgadget, |
384 | &s3c_device_sdi, | ||
327 | &n30_button_device, | 385 | &n30_button_device, |
328 | &n30_blue_led, | 386 | &n30_blue_led, |
329 | &n30_warning_led, | 387 | &n30_warning_led, |
@@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = { | |||
334 | &s3c_device_wdt, | 392 | &s3c_device_wdt, |
335 | &s3c_device_i2c0, | 393 | &s3c_device_i2c0, |
336 | &s3c_device_iis, | 394 | &s3c_device_iis, |
395 | &s3c_device_rtc, | ||
337 | &s3c_device_usbgadget, | 396 | &s3c_device_usbgadget, |
397 | &s3c_device_sdi, | ||
338 | &n35_button_device, | 398 | &n35_button_device, |
399 | &n35_blue_led, | ||
400 | &n35_warning_led, | ||
339 | }; | 401 | }; |
340 | 402 | ||
341 | static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { | 403 | static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { |
@@ -490,17 +552,15 @@ static void __init n30_map_io(void) | |||
490 | s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); | 552 | s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); |
491 | } | 553 | } |
492 | 554 | ||
493 | static void __init n30_init_irq(void) | ||
494 | { | ||
495 | s3c24xx_init_irq(); | ||
496 | } | ||
497 | |||
498 | /* GPB3 is the line that controls the pull-up for the USB D+ line */ | 555 | /* GPB3 is the line that controls the pull-up for the USB D+ line */ |
499 | 556 | ||
500 | static void __init n30_init(void) | 557 | static void __init n30_init(void) |
501 | { | 558 | { |
559 | WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power")); | ||
560 | |||
502 | s3c24xx_fb_set_platdata(&n30_fb_info); | 561 | s3c24xx_fb_set_platdata(&n30_fb_info); |
503 | s3c24xx_udc_set_platdata(&n30_udc_cfg); | 562 | s3c24xx_udc_set_platdata(&n30_udc_cfg); |
563 | s3c24xx_mci_set_platdata(&n30_mci_cfg); | ||
504 | s3c_i2c0_set_platdata(&n30_i2ccfg); | 564 | s3c_i2c0_set_platdata(&n30_i2ccfg); |
505 | 565 | ||
506 | /* Turn off suspend on both USB ports, and switch the | 566 | /* Turn off suspend on both USB ports, and switch the |
@@ -532,7 +592,7 @@ static void __init n30_init(void) | |||
532 | s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | | 592 | s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | |
533 | S3C2410_MISCCR_USBSUSPND0 | | 593 | S3C2410_MISCCR_USBSUSPND0 | |
534 | S3C2410_MISCCR_USBSUSPND1, | 594 | S3C2410_MISCCR_USBSUSPND1, |
535 | S3C2410_MISCCR_USBSUSPND1); | 595 | S3C2410_MISCCR_USBSUSPND0); |
536 | 596 | ||
537 | platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); | 597 | platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); |
538 | } | 598 | } |
@@ -550,7 +610,7 @@ MACHINE_START(N30, "Acer-N30") | |||
550 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 610 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
551 | .timer = &s3c24xx_timer, | 611 | .timer = &s3c24xx_timer, |
552 | .init_machine = n30_init, | 612 | .init_machine = n30_init, |
553 | .init_irq = n30_init_irq, | 613 | .init_irq = s3c24xx_init_irq, |
554 | .map_io = n30_map_io, | 614 | .map_io = n30_map_io, |
555 | MACHINE_END | 615 | MACHINE_END |
556 | 616 | ||
@@ -562,6 +622,6 @@ MACHINE_START(N35, "Acer-N35") | |||
562 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 622 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
563 | .timer = &s3c24xx_timer, | 623 | .timer = &s3c24xx_timer, |
564 | .init_machine = n30_init, | 624 | .init_machine = n30_init, |
565 | .init_irq = n30_init_irq, | 625 | .init_irq = s3c24xx_init_irq, |
566 | .map_io = n30_map_io, | 626 | .map_io = n30_map_io, |
567 | MACHINE_END | 627 | MACHINE_END |
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 966119c8efee..725636fc4dc3 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
@@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void) | |||
60 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); | 60 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
61 | } | 61 | } |
62 | 62 | ||
63 | /* the RX3715 uses similar code and the same H1940 and the | 63 | /* RX3715 and RX1950 use similar to H1940 code and the |
64 | * same offsets for resume and checksum pointers */ | 64 | * same offsets for resume and checksum pointers */ |
65 | 65 | ||
66 | if (machine_is_rx3715()) { | 66 | if (machine_is_rx3715() || machine_is_rx1950()) { |
67 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | 67 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); |
68 | unsigned long ptr; | 68 | unsigned long ptr; |
69 | unsigned long calc = 0; | 69 | unsigned long calc = 0; |
@@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void) | |||
79 | if ( machine_is_aml_m5900() ) | 79 | if ( machine_is_aml_m5900() ) |
80 | s3c2410_gpio_setpin(S3C2410_GPF(2), 1); | 80 | s3c2410_gpio_setpin(S3C2410_GPF(2), 1); |
81 | 81 | ||
82 | if (machine_is_rx1950()) { | ||
83 | /* According to S3C2442 user's manual, page 7-17, | ||
84 | * when the system is operating in NAND boot mode, | ||
85 | * the hardware pin configuration - EINT[23:21] – | ||
86 | * must be set as input for starting up after | ||
87 | * wakeup from sleep mode | ||
88 | */ | ||
89 | s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT); | ||
90 | s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT); | ||
91 | s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT); | ||
92 | } | ||
82 | } | 93 | } |
83 | 94 | ||
84 | static int s3c2410_pm_resume(struct sys_device *dev) | 95 | static int s3c2410_pm_resume(struct sys_device *dev) |
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c index f7afece7fc38..3404a876b33e 100644 --- a/arch/arm/mach-s3c2412/gpio.c +++ b/arch/arm/mach-s3c2412/gpio.c | |||
@@ -16,41 +16,43 @@ | |||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
18 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
19 | #include <linux/gpio.h> | ||
19 | 20 | ||
20 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
21 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
22 | 23 | ||
23 | #include <mach/regs-gpio.h> | 24 | #include <mach/regs-gpio.h> |
24 | |||
25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
26 | 26 | ||
27 | #include <plat/gpio-core.h> | ||
28 | |||
27 | int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) | 29 | int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) |
28 | { | 30 | { |
29 | void __iomem *base = S3C24XX_GPIO_BASE(pin); | 31 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); |
30 | unsigned long offs = S3C2410_GPIO_OFFSET(pin); | 32 | unsigned long offs = pin - chip->chip.base; |
31 | unsigned long flags; | 33 | unsigned long flags; |
32 | unsigned long slpcon; | 34 | unsigned long slpcon; |
33 | 35 | ||
34 | offs *= 2; | 36 | offs *= 2; |
35 | 37 | ||
36 | if (pin < S3C2410_GPIO_BANKB) | 38 | if (pin < S3C2410_GPB(0)) |
37 | return -EINVAL; | 39 | return -EINVAL; |
38 | 40 | ||
39 | if (pin >= S3C2410_GPIO_BANKF && | 41 | if (pin >= S3C2410_GPF(0) && |
40 | pin <= S3C2410_GPIO_BANKG) | 42 | pin <= S3C2410_GPG(16)) |
41 | return -EINVAL; | 43 | return -EINVAL; |
42 | 44 | ||
43 | if (pin > (S3C2410_GPIO_BANKH + 32)) | 45 | if (pin > S3C2410_GPH(16)) |
44 | return -EINVAL; | 46 | return -EINVAL; |
45 | 47 | ||
46 | local_irq_save(flags); | 48 | local_irq_save(flags); |
47 | 49 | ||
48 | slpcon = __raw_readl(base + 0x0C); | 50 | slpcon = __raw_readl(chip->base + 0x0C); |
49 | 51 | ||
50 | slpcon &= ~(3 << offs); | 52 | slpcon &= ~(3 << offs); |
51 | slpcon |= state << offs; | 53 | slpcon |= state << offs; |
52 | 54 | ||
53 | __raw_writel(slpcon, base + 0x0C); | 55 | __raw_writel(slpcon, chip->base + 0x0C); |
54 | 56 | ||
55 | local_irq_restore(flags); | 57 | local_irq_restore(flags); |
56 | 58 | ||
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 43160183571a..478f4b4606c2 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
@@ -674,7 +674,7 @@ static void __init jive_machine_init(void) | |||
674 | } | 674 | } |
675 | 675 | ||
676 | MACHINE_START(JIVE, "JIVE") | 676 | MACHINE_START(JIVE, "JIVE") |
677 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 677 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
678 | .phys_io = S3C2410_PA_UART, | 678 | .phys_io = S3C2410_PA_UART, |
679 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 679 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
680 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 680 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index faddb36ed23b..ba93a356a839 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c | |||
@@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void) | |||
150 | } | 150 | } |
151 | 151 | ||
152 | MACHINE_START(S3C2413, "S3C2413") | 152 | MACHINE_START(S3C2413, "S3C2413") |
153 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 153 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
154 | .phys_io = S3C2410_PA_UART, | 154 | .phys_io = S3C2410_PA_UART, |
155 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 155 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
156 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 156 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
@@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413") | |||
163 | MACHINE_END | 163 | MACHINE_END |
164 | 164 | ||
165 | MACHINE_START(SMDK2412, "SMDK2412") | 165 | MACHINE_START(SMDK2412, "SMDK2412") |
166 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 166 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
167 | .phys_io = S3C2410_PA_UART, | 167 | .phys_io = S3C2410_PA_UART, |
168 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 168 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
169 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 169 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
@@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412") | |||
176 | MACHINE_END | 176 | MACHINE_END |
177 | 177 | ||
178 | MACHINE_START(SMDK2413, "SMDK2413") | 178 | MACHINE_START(SMDK2413, "SMDK2413") |
179 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 179 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
180 | .phys_io = S3C2410_PA_UART, | 180 | .phys_io = S3C2410_PA_UART, |
181 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 181 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
182 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 182 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig index 29103a6047de..657e4fe17f39 100644 --- a/arch/arm/mach-s3c2416/Kconfig +++ b/arch/arm/mach-s3c2416/Kconfig | |||
@@ -30,6 +30,7 @@ menu "S3C2416 Machines" | |||
30 | config MACH_SMDK2416 | 30 | config MACH_SMDK2416 |
31 | bool "SMDK2416" | 31 | bool "SMDK2416" |
32 | select CPU_S3C2416 | 32 | select CPU_S3C2416 |
33 | select S3C_DEV_FB | ||
33 | select S3C_DEV_HSMMC | 34 | select S3C_DEV_HSMMC |
34 | select S3C_DEV_HSMMC1 | 35 | select S3C_DEV_HSMMC1 |
35 | help | 36 | help |
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c index 99d24c44f30f..5fc3f67ef265 100644 --- a/arch/arm/mach-s3c2416/mach-smdk2416.c +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/mtd/partitions.h> | 23 | #include <linux/mtd/partitions.h> |
24 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
25 | #include <linux/fb.h> | ||
25 | 26 | ||
26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
@@ -36,16 +37,19 @@ | |||
36 | #include <mach/regs-lcd.h> | 37 | #include <mach/regs-lcd.h> |
37 | 38 | ||
38 | #include <mach/idle.h> | 39 | #include <mach/idle.h> |
39 | #include <mach/fb.h> | ||
40 | #include <mach/leds-gpio.h> | 40 | #include <mach/leds-gpio.h> |
41 | #include <plat/iic.h> | 41 | #include <plat/iic.h> |
42 | 42 | ||
43 | #include <plat/s3c2416.h> | 43 | #include <plat/s3c2416.h> |
44 | #include <plat/gpio-cfg.h> | ||
44 | #include <plat/clock.h> | 45 | #include <plat/clock.h> |
45 | #include <plat/devs.h> | 46 | #include <plat/devs.h> |
46 | #include <plat/cpu.h> | 47 | #include <plat/cpu.h> |
47 | #include <plat/nand.h> | 48 | #include <plat/nand.h> |
48 | 49 | ||
50 | #include <plat/regs-fb-v4.h> | ||
51 | #include <plat/fb.h> | ||
52 | |||
49 | #include <plat/common-smdk.h> | 53 | #include <plat/common-smdk.h> |
50 | 54 | ||
51 | static struct map_desc smdk2416_iodesc[] __initdata = { | 55 | static struct map_desc smdk2416_iodesc[] __initdata = { |
@@ -109,7 +113,54 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { | |||
109 | } | 113 | } |
110 | }; | 114 | }; |
111 | 115 | ||
116 | struct s3c_fb_pd_win smdk2416_fb_win[] = { | ||
117 | [0] = { | ||
118 | /* think this is the same as the smdk6410 */ | ||
119 | .win_mode = { | ||
120 | .pixclock = 41094, | ||
121 | .left_margin = 8, | ||
122 | .right_margin = 13, | ||
123 | .upper_margin = 7, | ||
124 | .lower_margin = 5, | ||
125 | .hsync_len = 3, | ||
126 | .vsync_len = 1, | ||
127 | .xres = 800, | ||
128 | .yres = 480, | ||
129 | }, | ||
130 | .default_bpp = 16, | ||
131 | .max_bpp = 32, | ||
132 | }, | ||
133 | }; | ||
134 | |||
135 | static void s3c2416_fb_gpio_setup_24bpp(void) | ||
136 | { | ||
137 | unsigned int gpio; | ||
138 | |||
139 | for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) { | ||
140 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
141 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
142 | } | ||
143 | |||
144 | for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) { | ||
145 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
146 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
147 | } | ||
148 | |||
149 | for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) { | ||
150 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
151 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
152 | } | ||
153 | } | ||
154 | |||
155 | static struct s3c_fb_platdata smdk2416_fb_platdata = { | ||
156 | .win[0] = &smdk2416_fb_win[0], | ||
157 | .setup_gpio = s3c2416_fb_gpio_setup_24bpp, | ||
158 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
159 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
160 | }; | ||
161 | |||
112 | static struct platform_device *smdk2416_devices[] __initdata = { | 162 | static struct platform_device *smdk2416_devices[] __initdata = { |
163 | &s3c_device_fb, | ||
113 | &s3c_device_wdt, | 164 | &s3c_device_wdt, |
114 | &s3c_device_ohci, | 165 | &s3c_device_ohci, |
115 | &s3c_device_i2c0, | 166 | &s3c_device_i2c0, |
@@ -119,20 +170,25 @@ static struct platform_device *smdk2416_devices[] __initdata = { | |||
119 | 170 | ||
120 | static void __init smdk2416_map_io(void) | 171 | static void __init smdk2416_map_io(void) |
121 | { | 172 | { |
122 | |||
123 | s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); | 173 | s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); |
124 | s3c24xx_init_clocks(12000000); | 174 | s3c24xx_init_clocks(12000000); |
125 | s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); | 175 | s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); |
126 | |||
127 | } | 176 | } |
128 | 177 | ||
129 | static void __init smdk2416_machine_init(void) | 178 | static void __init smdk2416_machine_init(void) |
130 | { | 179 | { |
131 | s3c_i2c0_set_platdata(NULL); | 180 | s3c_i2c0_set_platdata(NULL); |
181 | s3c_fb_set_platdata(&smdk2416_fb_platdata); | ||
132 | 182 | ||
133 | gpio_request(S3C2410_GPB(4), "USBHost Power"); | 183 | gpio_request(S3C2410_GPB(4), "USBHost Power"); |
134 | gpio_direction_output(S3C2410_GPB(4), 1); | 184 | gpio_direction_output(S3C2410_GPB(4), 1); |
135 | 185 | ||
186 | gpio_request(S3C2410_GPB(3), "Display Power"); | ||
187 | gpio_direction_output(S3C2410_GPB(3), 1); | ||
188 | |||
189 | gpio_request(S3C2410_GPB(1), "Display Reset"); | ||
190 | gpio_direction_output(S3C2410_GPB(1), 1); | ||
191 | |||
136 | platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices)); | 192 | platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices)); |
137 | smdk_machine_init(); | 193 | smdk_machine_init(); |
138 | } | 194 | } |
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 3bff05745d0b..35dabccd0ac2 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c | |||
@@ -90,6 +90,8 @@ int __init s3c2416_init(void) | |||
90 | s3c_i2c0_setname("s3c2440-i2c"); | 90 | s3c_i2c0_setname("s3c2440-i2c"); |
91 | s3c_i2c1_setname("s3c2440-i2c"); | 91 | s3c_i2c1_setname("s3c2440-i2c"); |
92 | 92 | ||
93 | s3c_device_fb.name = "s3c2443-fb"; | ||
94 | |||
93 | return sysdev_register(&s3c2416_sysdev); | 95 | return sysdev_register(&s3c2416_sysdev); |
94 | } | 96 | } |
95 | 97 | ||
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 9d102b912091..cd8e7de388f0 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig | |||
@@ -188,4 +188,17 @@ config MACH_MINI2440 | |||
188 | Say Y here to select support for the MINI2440. Is a 10cm x 10cm board | 188 | Say Y here to select support for the MINI2440. Is a 10cm x 10cm board |
189 | available via various sources. It can come with a 3.5" or 7" touch LCD. | 189 | available via various sources. It can come with a 3.5" or 7" touch LCD. |
190 | 190 | ||
191 | config MACH_RX1950 | ||
192 | bool "HP iPAQ rx1950" | ||
193 | select CPU_S3C2442 | ||
194 | select S3C24XX_DCLK | ||
195 | select PM_H1940 if PM | ||
196 | select I2C | ||
197 | select S3C2410_PWM | ||
198 | select S3C_DEV_NAND | ||
199 | select S3C2410_IOTIMING if S3C2440_CPUFREQ | ||
200 | select S3C2440_XTAL_16934400 | ||
201 | help | ||
202 | Say Y here if you're using HP iPAQ rx1950 | ||
203 | |||
191 | endmenu | 204 | endmenu |
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile index c85ba32d8956..d5440fa34b04 100644 --- a/arch/arm/mach-s3c2440/Makefile +++ b/arch/arm/mach-s3c2440/Makefile | |||
@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o | |||
34 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o | 34 | obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o |
35 | obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o | 35 | obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o |
36 | obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o | 36 | obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o |
37 | obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o | ||
37 | 38 | ||
38 | # extra machine support | 39 | # extra machine support |
39 | 40 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c new file mode 100644 index 000000000000..8603b577a24b --- /dev/null +++ b/arch/arm/mach-s3c2440/mach-rx1950.c | |||
@@ -0,0 +1,582 @@ | |||
1 | /* linux/arch/arm/mach-s3c2440/mach-rx1950.c | ||
2 | * | ||
3 | * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev, | ||
4 | * Copyright (c) 2007-2010 Vasily Khoruzhick | ||
5 | * | ||
6 | * based on smdk2440 written by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/delay.h> | ||
19 | #include <linux/timer.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/gpio.h> | ||
22 | #include <linux/platform_device.h> | ||
23 | #include <linux/serial_core.h> | ||
24 | #include <linux/input.h> | ||
25 | #include <linux/gpio_keys.h> | ||
26 | #include <linux/sysdev.h> | ||
27 | #include <linux/pwm_backlight.h> | ||
28 | #include <linux/pwm.h> | ||
29 | |||
30 | #include <linux/mtd/mtd.h> | ||
31 | #include <linux/mtd/partitions.h> | ||
32 | |||
33 | #include <linux/mmc/host.h> | ||
34 | |||
35 | #include <asm/mach/arch.h> | ||
36 | #include <asm/mach/map.h> | ||
37 | #include <asm/mach-types.h> | ||
38 | |||
39 | #include <mach/regs-gpio.h> | ||
40 | #include <mach/regs-gpioj.h> | ||
41 | #include <mach/h1940.h> | ||
42 | #include <mach/fb.h> | ||
43 | |||
44 | #include <plat/clock.h> | ||
45 | #include <plat/regs-serial.h> | ||
46 | #include <plat/regs-iic.h> | ||
47 | #include <plat/mci.h> | ||
48 | #include <plat/udc.h> | ||
49 | #include <plat/nand.h> | ||
50 | #include <plat/iic.h> | ||
51 | #include <plat/devs.h> | ||
52 | #include <plat/cpu.h> | ||
53 | #include <plat/pm.h> | ||
54 | #include <plat/irq.h> | ||
55 | #include <plat/ts.h> | ||
56 | |||
57 | #define LCD_PWM_PERIOD 192960 | ||
58 | #define LCD_PWM_DUTY 127353 | ||
59 | |||
60 | static struct map_desc rx1950_iodesc[] __initdata = { | ||
61 | }; | ||
62 | |||
63 | static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { | ||
64 | [0] = { | ||
65 | .name = "fclk", | ||
66 | .divisor = 0x0a, | ||
67 | .min_baud = 0, | ||
68 | .max_baud = 0, | ||
69 | }, | ||
70 | }; | ||
71 | |||
72 | static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { | ||
73 | [0] = { | ||
74 | .hwport = 0, | ||
75 | .flags = 0, | ||
76 | .ucon = 0x3c5, | ||
77 | .ulcon = 0x03, | ||
78 | .ufcon = 0x51, | ||
79 | .clocks = rx1950_serial_clocks, | ||
80 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
81 | }, | ||
82 | [1] = { | ||
83 | .hwport = 1, | ||
84 | .flags = 0, | ||
85 | .ucon = 0x3c5, | ||
86 | .ulcon = 0x03, | ||
87 | .ufcon = 0x51, | ||
88 | .clocks = rx1950_serial_clocks, | ||
89 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
90 | }, | ||
91 | /* IR port */ | ||
92 | [2] = { | ||
93 | .hwport = 2, | ||
94 | .flags = 0, | ||
95 | .ucon = 0x3c5, | ||
96 | .ulcon = 0x43, | ||
97 | .ufcon = 0xf1, | ||
98 | .clocks = rx1950_serial_clocks, | ||
99 | .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | static struct s3c2410fb_display rx1950_display = { | ||
104 | .type = S3C2410_LCDCON1_TFT, | ||
105 | .width = 240, | ||
106 | .height = 320, | ||
107 | .xres = 240, | ||
108 | .yres = 320, | ||
109 | .bpp = 16, | ||
110 | |||
111 | .pixclock = 260000, | ||
112 | .left_margin = 10, | ||
113 | .right_margin = 20, | ||
114 | .hsync_len = 10, | ||
115 | .upper_margin = 2, | ||
116 | .lower_margin = 2, | ||
117 | .vsync_len = 2, | ||
118 | |||
119 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | | ||
120 | S3C2410_LCDCON5_INVVCLK | | ||
121 | S3C2410_LCDCON5_INVVLINE | | ||
122 | S3C2410_LCDCON5_INVVFRAME | | ||
123 | S3C2410_LCDCON5_HWSWP | | ||
124 | (0x02 << 13) | | ||
125 | (0x02 << 15), | ||
126 | |||
127 | }; | ||
128 | |||
129 | static struct s3c2410fb_mach_info rx1950_lcd_cfg = { | ||
130 | .displays = &rx1950_display, | ||
131 | .num_displays = 1, | ||
132 | .default_display = 0, | ||
133 | |||
134 | .lpcsel = 0x02, | ||
135 | .gpccon = 0xaa9556a9, | ||
136 | .gpccon_mask = 0xffc003fc, | ||
137 | .gpcup = 0x0000ffff, | ||
138 | .gpcup_mask = 0xffffffff, | ||
139 | |||
140 | .gpdcon = 0xaa90aaa1, | ||
141 | .gpdcon_mask = 0xffc0fff0, | ||
142 | .gpdup = 0x0000fcfd, | ||
143 | .gpdup_mask = 0xffffffff, | ||
144 | |||
145 | }; | ||
146 | |||
147 | static struct pwm_device *lcd_pwm; | ||
148 | |||
149 | void rx1950_lcd_power(int enable) | ||
150 | { | ||
151 | int i; | ||
152 | static int enabled; | ||
153 | if (enabled == enable) | ||
154 | return; | ||
155 | if (!enable) { | ||
156 | |||
157 | /* GPC11-GPC15->OUTPUT */ | ||
158 | for (i = 11; i < 16; i++) | ||
159 | gpio_direction_output(S3C2410_GPC(i), 1); | ||
160 | |||
161 | /* Wait a bit here... */ | ||
162 | mdelay(100); | ||
163 | |||
164 | /* GPD2-GPD7->OUTPUT */ | ||
165 | /* GPD11-GPD15->OUTPUT */ | ||
166 | /* GPD2-GPD7->1, GPD11-GPD15->1 */ | ||
167 | for (i = 2; i < 8; i++) | ||
168 | gpio_direction_output(S3C2410_GPD(i), 1); | ||
169 | for (i = 11; i < 16; i++) | ||
170 | gpio_direction_output(S3C2410_GPD(i), 1); | ||
171 | |||
172 | /* Wait a bit here...*/ | ||
173 | mdelay(100); | ||
174 | |||
175 | /* GPB0->OUTPUT, GPB0->0 */ | ||
176 | gpio_direction_output(S3C2410_GPB(0), 0); | ||
177 | |||
178 | /* GPC1-GPC4->OUTPUT, GPC1-4->0 */ | ||
179 | for (i = 1; i < 5; i++) | ||
180 | gpio_direction_output(S3C2410_GPC(i), 0); | ||
181 | |||
182 | /* GPC15-GPC11->0 */ | ||
183 | for (i = 11; i < 16; i++) | ||
184 | gpio_direction_output(S3C2410_GPC(i), 0); | ||
185 | |||
186 | /* GPD15-GPD11->0, GPD2->GPD7->0 */ | ||
187 | for (i = 11; i < 16; i++) | ||
188 | gpio_direction_output(S3C2410_GPD(i), 0); | ||
189 | |||
190 | for (i = 2; i < 8; i++) | ||
191 | gpio_direction_output(S3C2410_GPD(i), 0); | ||
192 | |||
193 | /* GPC6->0, GPC7->0, GPC5->0 */ | ||
194 | gpio_direction_output(S3C2410_GPC(6), 0); | ||
195 | gpio_direction_output(S3C2410_GPC(7), 0); | ||
196 | gpio_direction_output(S3C2410_GPC(5), 0); | ||
197 | |||
198 | /* GPB1->OUTPUT, GPB1->0 */ | ||
199 | gpio_direction_output(S3C2410_GPB(1), 0); | ||
200 | pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD); | ||
201 | pwm_disable(lcd_pwm); | ||
202 | |||
203 | /* GPC0->0, GPC10->0 */ | ||
204 | gpio_direction_output(S3C2410_GPC(0), 0); | ||
205 | gpio_direction_output(S3C2410_GPC(10), 0); | ||
206 | } else { | ||
207 | pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD); | ||
208 | pwm_enable(lcd_pwm); | ||
209 | |||
210 | gpio_direction_output(S3C2410_GPC(0), 1); | ||
211 | gpio_direction_output(S3C2410_GPC(5), 1); | ||
212 | |||
213 | s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1); | ||
214 | gpio_direction_output(S3C2410_GPC(7), 1); | ||
215 | |||
216 | for (i = 1; i < 5; i++) | ||
217 | s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2)); | ||
218 | |||
219 | for (i = 11; i < 16; i++) | ||
220 | s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2)); | ||
221 | |||
222 | for (i = 2; i < 8; i++) | ||
223 | s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2)); | ||
224 | |||
225 | for (i = 11; i < 16; i++) | ||
226 | s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2)); | ||
227 | |||
228 | gpio_direction_output(S3C2410_GPC(10), 1); | ||
229 | gpio_direction_output(S3C2410_GPC(6), 1); | ||
230 | } | ||
231 | enabled = enable; | ||
232 | } | ||
233 | |||
234 | static void rx1950_bl_power(int enable) | ||
235 | { | ||
236 | static int enabled; | ||
237 | if (enabled == enable) | ||
238 | return; | ||
239 | if (!enable) { | ||
240 | gpio_direction_output(S3C2410_GPB(0), 0); | ||
241 | } else { | ||
242 | /* LED driver need a "push" to power on */ | ||
243 | gpio_direction_output(S3C2410_GPB(0), 1); | ||
244 | /* Warm up backlight for one period of PWM. | ||
245 | * Without this trick its almost impossible to | ||
246 | * enable backlight with low brightness value | ||
247 | */ | ||
248 | ndelay(48000); | ||
249 | s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0); | ||
250 | } | ||
251 | enabled = enable; | ||
252 | } | ||
253 | |||
254 | static int rx1950_backlight_init(struct device *dev) | ||
255 | { | ||
256 | WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight")); | ||
257 | lcd_pwm = pwm_request(1, "RX1950 LCD"); | ||
258 | if (IS_ERR(lcd_pwm)) { | ||
259 | dev_err(dev, "Unable to request PWM for LCD power!\n"); | ||
260 | return PTR_ERR(lcd_pwm); | ||
261 | } | ||
262 | |||
263 | rx1950_lcd_power(1); | ||
264 | rx1950_bl_power(1); | ||
265 | |||
266 | return 0; | ||
267 | } | ||
268 | |||
269 | static void rx1950_backlight_exit(struct device *dev) | ||
270 | { | ||
271 | rx1950_bl_power(0); | ||
272 | rx1950_lcd_power(0); | ||
273 | |||
274 | pwm_free(lcd_pwm); | ||
275 | gpio_free(S3C2410_GPB(0)); | ||
276 | } | ||
277 | |||
278 | |||
279 | static int rx1950_backlight_notify(struct device *dev, int brightness) | ||
280 | { | ||
281 | if (!brightness) { | ||
282 | rx1950_bl_power(0); | ||
283 | rx1950_lcd_power(0); | ||
284 | } else { | ||
285 | rx1950_lcd_power(1); | ||
286 | rx1950_bl_power(1); | ||
287 | } | ||
288 | return brightness; | ||
289 | } | ||
290 | |||
291 | static struct platform_pwm_backlight_data rx1950_backlight_data = { | ||
292 | .pwm_id = 0, | ||
293 | .max_brightness = 24, | ||
294 | .dft_brightness = 4, | ||
295 | .pwm_period_ns = 48000, | ||
296 | .init = rx1950_backlight_init, | ||
297 | .notify = rx1950_backlight_notify, | ||
298 | .exit = rx1950_backlight_exit, | ||
299 | }; | ||
300 | |||
301 | static struct platform_device rx1950_backlight = { | ||
302 | .name = "pwm-backlight", | ||
303 | .dev = { | ||
304 | .parent = &s3c_device_timer[0].dev, | ||
305 | .platform_data = &rx1950_backlight_data, | ||
306 | }, | ||
307 | }; | ||
308 | |||
309 | static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd) | ||
310 | { | ||
311 | switch (power_mode) { | ||
312 | case MMC_POWER_OFF: | ||
313 | gpio_direction_output(S3C2410_GPJ(1), 0); | ||
314 | break; | ||
315 | case MMC_POWER_UP: | ||
316 | case MMC_POWER_ON: | ||
317 | gpio_direction_output(S3C2410_GPJ(1), 1); | ||
318 | break; | ||
319 | default: | ||
320 | break; | ||
321 | } | ||
322 | } | ||
323 | |||
324 | static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = { | ||
325 | .gpio_detect = S3C2410_GPF(5), | ||
326 | .gpio_wprotect = S3C2410_GPH(8), | ||
327 | .set_power = rx1950_set_mmc_power, | ||
328 | .ocr_avail = MMC_VDD_32_33, | ||
329 | }; | ||
330 | |||
331 | static struct mtd_partition rx1950_nand_part[] = { | ||
332 | [0] = { | ||
333 | .name = "Boot0", | ||
334 | .offset = 0, | ||
335 | .size = 0x4000, | ||
336 | .mask_flags = MTD_WRITEABLE, | ||
337 | }, | ||
338 | [1] = { | ||
339 | .name = "Boot1", | ||
340 | .offset = MTDPART_OFS_APPEND, | ||
341 | .size = 0x40000, | ||
342 | .mask_flags = MTD_WRITEABLE, | ||
343 | }, | ||
344 | [2] = { | ||
345 | .name = "Kernel", | ||
346 | .offset = MTDPART_OFS_APPEND, | ||
347 | .size = 0x300000, | ||
348 | .mask_flags = 0, | ||
349 | }, | ||
350 | [3] = { | ||
351 | .name = "Filesystem", | ||
352 | .offset = MTDPART_OFS_APPEND, | ||
353 | .size = MTDPART_SIZ_FULL, | ||
354 | .mask_flags = 0, | ||
355 | }, | ||
356 | }; | ||
357 | |||
358 | static struct s3c2410_nand_set rx1950_nand_sets[] = { | ||
359 | [0] = { | ||
360 | .name = "Internal", | ||
361 | .nr_chips = 1, | ||
362 | .nr_partitions = ARRAY_SIZE(rx1950_nand_part), | ||
363 | .partitions = rx1950_nand_part, | ||
364 | }, | ||
365 | }; | ||
366 | |||
367 | static struct s3c2410_platform_nand rx1950_nand_info = { | ||
368 | .tacls = 25, | ||
369 | .twrph0 = 50, | ||
370 | .twrph1 = 15, | ||
371 | .nr_sets = ARRAY_SIZE(rx1950_nand_sets), | ||
372 | .sets = rx1950_nand_sets, | ||
373 | }; | ||
374 | |||
375 | static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd) | ||
376 | { | ||
377 | switch (cmd) { | ||
378 | case S3C2410_UDC_P_ENABLE: | ||
379 | gpio_direction_output(S3C2410_GPJ(5), 1); | ||
380 | break; | ||
381 | case S3C2410_UDC_P_DISABLE: | ||
382 | gpio_direction_output(S3C2410_GPJ(5), 0); | ||
383 | break; | ||
384 | case S3C2410_UDC_P_RESET: | ||
385 | break; | ||
386 | default: | ||
387 | break; | ||
388 | } | ||
389 | } | ||
390 | |||
391 | static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = { | ||
392 | .udc_command = rx1950_udc_pullup, | ||
393 | .vbus_pin = S3C2410_GPG(5), | ||
394 | .vbus_pin_inverted = 1, | ||
395 | }; | ||
396 | |||
397 | static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = { | ||
398 | .delay = 10000, | ||
399 | .presc = 49, | ||
400 | .oversampling_shift = 3, | ||
401 | }; | ||
402 | |||
403 | static struct gpio_keys_button rx1950_gpio_keys_table[] = { | ||
404 | { | ||
405 | .code = KEY_POWER, | ||
406 | .gpio = S3C2410_GPF(0), | ||
407 | .active_low = 1, | ||
408 | .desc = "Power button", | ||
409 | .wakeup = 1, | ||
410 | }, | ||
411 | { | ||
412 | .code = KEY_F5, | ||
413 | .gpio = S3C2410_GPF(7), | ||
414 | .active_low = 1, | ||
415 | .desc = "Record button", | ||
416 | }, | ||
417 | { | ||
418 | .code = KEY_F1, | ||
419 | .gpio = S3C2410_GPG(0), | ||
420 | .active_low = 1, | ||
421 | .desc = "Calendar button", | ||
422 | }, | ||
423 | { | ||
424 | .code = KEY_F2, | ||
425 | .gpio = S3C2410_GPG(2), | ||
426 | .active_low = 1, | ||
427 | .desc = "Contacts button", | ||
428 | }, | ||
429 | { | ||
430 | .code = KEY_F3, | ||
431 | .gpio = S3C2410_GPG(3), | ||
432 | .active_low = 1, | ||
433 | .desc = "Mail button", | ||
434 | }, | ||
435 | { | ||
436 | .code = KEY_F4, | ||
437 | .gpio = S3C2410_GPG(7), | ||
438 | .active_low = 1, | ||
439 | .desc = "WLAN button", | ||
440 | }, | ||
441 | { | ||
442 | .code = KEY_LEFT, | ||
443 | .gpio = S3C2410_GPG(10), | ||
444 | .active_low = 1, | ||
445 | .desc = "Left button", | ||
446 | }, | ||
447 | { | ||
448 | .code = KEY_RIGHT, | ||
449 | .gpio = S3C2410_GPG(11), | ||
450 | .active_low = 1, | ||
451 | .desc = "Right button", | ||
452 | }, | ||
453 | { | ||
454 | .code = KEY_UP, | ||
455 | .gpio = S3C2410_GPG(4), | ||
456 | .active_low = 1, | ||
457 | .desc = "Up button", | ||
458 | }, | ||
459 | { | ||
460 | .code = KEY_DOWN, | ||
461 | .gpio = S3C2410_GPG(6), | ||
462 | .active_low = 1, | ||
463 | .desc = "Down button", | ||
464 | }, | ||
465 | { | ||
466 | .code = KEY_ENTER, | ||
467 | .gpio = S3C2410_GPG(9), | ||
468 | .active_low = 1, | ||
469 | .desc = "Ok button" | ||
470 | }, | ||
471 | }; | ||
472 | |||
473 | static struct gpio_keys_platform_data rx1950_gpio_keys_data = { | ||
474 | .buttons = rx1950_gpio_keys_table, | ||
475 | .nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table), | ||
476 | }; | ||
477 | |||
478 | static struct platform_device rx1950_device_gpiokeys = { | ||
479 | .name = "gpio-keys", | ||
480 | .dev.platform_data = &rx1950_gpio_keys_data, | ||
481 | }; | ||
482 | |||
483 | static struct s3c2410_platform_i2c rx1950_i2c_data = { | ||
484 | .flags = 0, | ||
485 | .slave_addr = 0x42, | ||
486 | .frequency = 400 * 1000, | ||
487 | .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, | ||
488 | }; | ||
489 | |||
490 | static struct platform_device *rx1950_devices[] __initdata = { | ||
491 | &s3c_device_lcd, | ||
492 | &s3c_device_wdt, | ||
493 | &s3c_device_i2c0, | ||
494 | &s3c_device_iis, | ||
495 | &s3c_device_usbgadget, | ||
496 | &s3c_device_rtc, | ||
497 | &s3c_device_nand, | ||
498 | &s3c_device_sdi, | ||
499 | &s3c_device_adc, | ||
500 | &s3c_device_ts, | ||
501 | &s3c_device_timer[0], | ||
502 | &s3c_device_timer[1], | ||
503 | &rx1950_backlight, | ||
504 | &rx1950_device_gpiokeys, | ||
505 | }; | ||
506 | |||
507 | static struct clk *rx1950_clocks[] __initdata = { | ||
508 | &s3c24xx_clkout0, | ||
509 | &s3c24xx_clkout1, | ||
510 | }; | ||
511 | |||
512 | static void __init rx1950_map_io(void) | ||
513 | { | ||
514 | s3c24xx_clkout0.parent = &clk_h; | ||
515 | s3c24xx_clkout1.parent = &clk_f; | ||
516 | |||
517 | s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks)); | ||
518 | |||
519 | s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc)); | ||
520 | s3c24xx_init_clocks(16934000); | ||
521 | s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs)); | ||
522 | |||
523 | /* setup PM */ | ||
524 | |||
525 | #ifdef CONFIG_PM_H1940 | ||
526 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8); | ||
527 | #endif | ||
528 | |||
529 | s3c_pm_init(); | ||
530 | } | ||
531 | |||
532 | static void __init rx1950_init_machine(void) | ||
533 | { | ||
534 | int i; | ||
535 | |||
536 | s3c24xx_fb_set_platdata(&rx1950_lcd_cfg); | ||
537 | s3c24xx_udc_set_platdata(&rx1950_udc_cfg); | ||
538 | s3c24xx_ts_set_platdata(&rx1950_ts_cfg); | ||
539 | s3c24xx_mci_set_platdata(&rx1950_mmc_cfg); | ||
540 | s3c_i2c0_set_platdata(&rx1950_i2c_data); | ||
541 | s3c_nand_set_platdata(&rx1950_nand_info); | ||
542 | |||
543 | /* Turn off suspend on both USB ports, and switch the | ||
544 | * selectable USB port to USB device mode. */ | ||
545 | s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | | ||
546 | S3C2410_MISCCR_USBSUSPND0 | | ||
547 | S3C2410_MISCCR_USBSUSPND1, 0x0); | ||
548 | |||
549 | WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup")); | ||
550 | gpio_direction_output(S3C2410_GPJ(5), 0); | ||
551 | |||
552 | /* mmc power is disabled by default */ | ||
553 | WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power")); | ||
554 | gpio_direction_output(S3C2410_GPJ(1), 0); | ||
555 | |||
556 | for (i = 0; i < 8; i++) | ||
557 | WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power")); | ||
558 | |||
559 | for (i = 10; i < 16; i++) | ||
560 | WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power")); | ||
561 | |||
562 | for (i = 2; i < 8; i++) | ||
563 | WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power")); | ||
564 | |||
565 | for (i = 11; i < 16; i++) | ||
566 | WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power")); | ||
567 | |||
568 | WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power")); | ||
569 | |||
570 | platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices)); | ||
571 | } | ||
572 | |||
573 | MACHINE_START(RX1950, "HP iPAQ RX1950") | ||
574 | /* Maintainers: Vasily Khoruzhick */ | ||
575 | .phys_io = S3C2410_PA_UART, | ||
576 | .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc, | ||
577 | .boot_params = S3C2410_SDRAM_PA + 0x100, | ||
578 | .map_io = rx1950_map_io, | ||
579 | .init_irq = s3c24xx_init_irq, | ||
580 | .init_machine = rx1950_init_machine, | ||
581 | .timer = &s3c24xx_timer, | ||
582 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 1e836e506f8b..d2946de3f365 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
@@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void) | |||
209 | } | 209 | } |
210 | 210 | ||
211 | MACHINE_START(RX3715, "IPAQ-RX3715") | 211 | MACHINE_START(RX3715, "IPAQ-RX3715") |
212 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 212 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
213 | .phys_io = S3C2410_PA_UART, | 213 | .phys_io = S3C2410_PA_UART, |
214 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 214 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
215 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 215 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index 3ac3d636d615..df83276d85ae 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c | |||
@@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void) | |||
174 | } | 174 | } |
175 | 175 | ||
176 | MACHINE_START(S3C2440, "SMDK2440") | 176 | MACHINE_START(S3C2440, "SMDK2440") |
177 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 177 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
178 | .phys_io = S3C2410_PA_UART, | 178 | .phys_io = S3C2410_PA_UART, |
179 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 179 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
180 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 180 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index e2e362bda9b7..4c863d3a52f4 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c | |||
@@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void) | |||
131 | } | 131 | } |
132 | 132 | ||
133 | MACHINE_START(SMDK2443, "SMDK2443") | 133 | MACHINE_START(SMDK2443, "SMDK2443") |
134 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 134 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
135 | .phys_io = S3C2410_PA_UART, | 135 | .phys_io = S3C2410_PA_UART, |
136 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, | 136 | .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, |
137 | .boot_params = S3C2410_SDRAM_PA + 0x100, | 137 | .boot_params = S3C2410_SDRAM_PA + 0x100, |
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 959df3840de5..69e9fbfea917 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig | |||
@@ -85,6 +85,7 @@ config MACH_ANW6410 | |||
85 | config MACH_SMDK6410 | 85 | config MACH_SMDK6410 |
86 | bool "SMDK6410" | 86 | bool "SMDK6410" |
87 | select CPU_S3C6410 | 87 | select CPU_S3C6410 |
88 | select SAMSUNG_DEV_ADC | ||
88 | select S3C_DEV_HSMMC | 89 | select S3C_DEV_HSMMC |
89 | select S3C_DEV_HSMMC1 | 90 | select S3C_DEV_HSMMC1 |
90 | select S3C_DEV_I2C1 | 91 | select S3C_DEV_I2C1 |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 3758e15086be..a10f1fc6b023 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
@@ -56,7 +56,6 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o | |||
56 | # device support | 56 | # device support |
57 | 57 | ||
58 | obj-y += dev-uart.o | 58 | obj-y += dev-uart.o |
59 | obj-y += dev-rtc.o | ||
60 | obj-y += dev-audio.o | 59 | obj-y += dev-audio.o |
61 | obj-$(CONFIG_S3C_ADC) += dev-adc.o | ||
62 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | 60 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o |
61 | obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o | ||
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 2ac2e7d73e53..7a4138beb665 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c | |||
@@ -88,6 +88,12 @@ struct clk clk_48m = { | |||
88 | .enable = clk_48m_ctrl, | 88 | .enable = clk_48m_ctrl, |
89 | }; | 89 | }; |
90 | 90 | ||
91 | struct clk clk_xusbxti = { | ||
92 | .name = "xusbxti", | ||
93 | .id = -1, | ||
94 | .rate = 48000000, | ||
95 | }; | ||
96 | |||
91 | static int inline s3c64xx_gate(void __iomem *reg, | 97 | static int inline s3c64xx_gate(void __iomem *reg, |
92 | struct clk *clk, | 98 | struct clk *clk, |
93 | int enable) | 99 | int enable) |
@@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = { | |||
518 | .id = -1, | 524 | .id = -1, |
519 | }; | 525 | }; |
520 | 526 | ||
527 | static struct clk clk_iisv4_cd = { | ||
528 | .name = "iis_cdclk_v4", | ||
529 | .id = -1, | ||
530 | }; | ||
531 | |||
521 | static struct clk clk_pcm_cd = { | 532 | static struct clk clk_pcm_cd = { |
522 | .name = "pcm_cdclk", | 533 | .name = "pcm_cdclk", |
523 | .id = -1, | 534 | .id = -1, |
@@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = { | |||
549 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | 560 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), |
550 | }; | 561 | }; |
551 | 562 | ||
563 | static struct clk *clkset_audio2_list[] = { | ||
564 | [0] = &clk_mout_epll.clk, | ||
565 | [1] = &clk_dout_mpll, | ||
566 | [2] = &clk_fin_epll, | ||
567 | [3] = &clk_iisv4_cd, | ||
568 | [4] = &clk_pcm_cd, | ||
569 | }; | ||
570 | |||
571 | static struct clksrc_sources clkset_audio2 = { | ||
572 | .sources = clkset_audio2_list, | ||
573 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), | ||
574 | }; | ||
575 | |||
552 | static struct clk *clkset_camif_list[] = { | 576 | static struct clk *clkset_camif_list[] = { |
553 | &clk_h2, | 577 | &clk_h2, |
554 | }; | 578 | }; |
@@ -652,6 +676,16 @@ static struct clksrc_clk clksrcs[] = { | |||
652 | .sources = &clkset_audio1, | 676 | .sources = &clkset_audio1, |
653 | }, { | 677 | }, { |
654 | .clk = { | 678 | .clk = { |
679 | .name = "audio-bus", | ||
680 | .id = -1, /* There's only one IISv4 port */ | ||
681 | .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2, | ||
682 | .enable = s3c64xx_sclk_ctrl, | ||
683 | }, | ||
684 | .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 }, | ||
685 | .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 }, | ||
686 | .sources = &clkset_audio2, | ||
687 | }, { | ||
688 | .clk = { | ||
655 | .name = "irda-bus", | 689 | .name = "irda-bus", |
656 | .id = 0, | 690 | .id = 0, |
657 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | 691 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, |
@@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = { | |||
749 | &clk_ext_xtal_mux, | 783 | &clk_ext_xtal_mux, |
750 | &clk_iis_cd0, | 784 | &clk_iis_cd0, |
751 | &clk_iis_cd1, | 785 | &clk_iis_cd1, |
786 | &clk_iisv4_cd, | ||
752 | &clk_pcm_cd, | 787 | &clk_pcm_cd, |
753 | &clk_mout_epll.clk, | 788 | &clk_mout_epll.clk, |
754 | &clk_mout_mpll.clk, | 789 | &clk_mout_mpll.clk, |
@@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = { | |||
762 | &clk_27m, | 797 | &clk_27m, |
763 | &clk_48m, | 798 | &clk_48m, |
764 | &clk_h2, | 799 | &clk_h2, |
800 | &clk_xusbxti, | ||
765 | }; | 801 | }; |
766 | 802 | ||
767 | /** | 803 | /** |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 33ccf7bf766a..5567e037b0d1 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c | |||
@@ -414,7 +414,7 @@ err_buff: | |||
414 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | 414 | EXPORT_SYMBOL(s3c2410_dma_enqueue); |
415 | 415 | ||
416 | 416 | ||
417 | int s3c2410_dma_devconfig(int channel, | 417 | int s3c2410_dma_devconfig(unsigned int channel, |
418 | enum s3c2410_dmasrc source, | 418 | enum s3c2410_dmasrc source, |
419 | unsigned long devaddr) | 419 | unsigned long devaddr) |
420 | { | 420 | { |
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 801c1c0f3a95..9fdd50c8c767 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h | |||
@@ -103,5 +103,8 @@ | |||
103 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST | 103 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST |
104 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG | 104 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG |
105 | #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY | 105 | #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY |
106 | #define S3C_PA_RTC S3C64XX_PA_RTC | ||
107 | |||
108 | #define SAMSUNG_PA_ADC S3C64XX_PA_ADC | ||
106 | 109 | ||
107 | #endif /* __ASM_ARCH_6400_MAP_H */ | 110 | #endif /* __ASM_ARCH_6400_MAP_H */ |
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h index 3ef62741e5d1..0114eb0c1fe7 100644 --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h | |||
@@ -33,6 +33,7 @@ | |||
33 | #define S3C_PCLK_GATE S3C_CLKREG(0x34) | 33 | #define S3C_PCLK_GATE S3C_CLKREG(0x34) |
34 | #define S3C_SCLK_GATE S3C_CLKREG(0x38) | 34 | #define S3C_SCLK_GATE S3C_CLKREG(0x38) |
35 | #define S3C_MEM0_GATE S3C_CLKREG(0x3C) | 35 | #define S3C_MEM0_GATE S3C_CLKREG(0x3C) |
36 | #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C) | ||
36 | 37 | ||
37 | /* CLKDIV0 */ | 38 | /* CLKDIV0 */ |
38 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) | 39 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c index f7b18983950c..59916676d8d2 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6400.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c | |||
@@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void) | |||
84 | } | 84 | } |
85 | 85 | ||
86 | MACHINE_START(SMDK6400, "SMDK6400") | 86 | MACHINE_START(SMDK6400, "SMDK6400") |
87 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 87 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
88 | .phys_io = S3C_PA_UART & 0xfff00000, | 88 | .phys_io = S3C_PA_UART & 0xfff00000, |
89 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | 89 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, |
90 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | 90 | .boot_params = S3C64XX_PA_SDRAM + 0x100, |
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 2d5afd221d77..9d51455feb31 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c | |||
@@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void) | |||
656 | } | 656 | } |
657 | 657 | ||
658 | MACHINE_START(SMDK6410, "SMDK6410") | 658 | MACHINE_START(SMDK6410, "SMDK6410") |
659 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | 659 | /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ |
660 | .phys_io = S3C_PA_UART & 0xfff00000, | 660 | .phys_io = S3C_PA_UART & 0xfff00000, |
661 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | 661 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, |
662 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | 662 | .boot_params = S3C64XX_PA_SDRAM + 0x100, |
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 59635d19466a..3ab695c691ee 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <plat/clock.h> | 38 | #include <plat/clock.h> |
39 | #include <plat/sdhci.h> | 39 | #include <plat/sdhci.h> |
40 | #include <plat/iic-core.h> | 40 | #include <plat/iic-core.h> |
41 | #include <plat/adc.h> | ||
41 | #include <mach/s3c6400.h> | 42 | #include <mach/s3c6400.h> |
42 | #include <mach/s3c6410.h> | 43 | #include <mach/s3c6410.h> |
43 | 44 | ||
@@ -52,6 +53,7 @@ void __init s3c6410_map_io(void) | |||
52 | s3c_i2c0_setname("s3c2440-i2c"); | 53 | s3c_i2c0_setname("s3c2440-i2c"); |
53 | s3c_i2c1_setname("s3c2440-i2c"); | 54 | s3c_i2c1_setname("s3c2440-i2c"); |
54 | 55 | ||
56 | s3c_device_adc.name = "s3c64xx-adc"; | ||
55 | s3c_device_nand.name = "s3c6400-nand"; | 57 | s3c_device_nand.name = "s3c6400-nand"; |
56 | } | 58 | } |
57 | 59 | ||
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index 4c29ff8b07de..77aeffd17330 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig | |||
@@ -9,6 +9,7 @@ if ARCH_S5P6440 | |||
9 | 9 | ||
10 | config CPU_S5P6440 | 10 | config CPU_S5P6440 |
11 | bool | 11 | bool |
12 | select S3C_PL330_DMA | ||
12 | help | 13 | help |
13 | Enable S5P6440 CPU support | 14 | Enable S5P6440 CPU support |
14 | 15 | ||
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index 1ad894b1d3ab..44facf43d59f 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile | |||
@@ -12,8 +12,12 @@ obj- := | |||
12 | 12 | ||
13 | # Core support for S5P6440 system | 13 | # Core support for S5P6440 system |
14 | 14 | ||
15 | obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o | 15 | obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o |
16 | obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o | ||
16 | 17 | ||
17 | # machine support | 18 | # machine support |
18 | 19 | ||
19 | obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o | 20 | obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o |
21 | |||
22 | # device support | ||
23 | obj-y += dev-audio.o | ||
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c index b2672e16e7aa..ca6e48dce777 100644 --- a/arch/arm/mach-s5p6440/clock.c +++ b/arch/arm/mach-s5p6440/clock.c | |||
@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = { | |||
134 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, | 134 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, |
135 | }; | 135 | }; |
136 | 136 | ||
137 | static struct clk clk_h_low = { | ||
138 | .name = "hclk_low", | ||
139 | .id = -1, | ||
140 | .rate = 0, | ||
141 | .parent = NULL, | ||
142 | .ctrlbit = 0, | ||
143 | .ops = &clk_ops_def_setrate, | ||
144 | }; | ||
145 | |||
146 | static struct clk clk_p_low = { | ||
147 | .name = "pclk_low", | ||
148 | .id = -1, | ||
149 | .rate = 0, | ||
150 | .parent = NULL, | ||
151 | .ctrlbit = 0, | ||
152 | .ops = &clk_ops_def_setrate, | ||
153 | }; | ||
154 | |||
155 | enum perf_level { | 137 | enum perf_level { |
156 | L0 = 532*1000, | 138 | L0 = 532*1000, |
157 | L1 = 266*1000, | 139 | L1 = 266*1000, |
@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = { | |||
247 | .round_rate = s5p6440_armclk_round_rate, | 229 | .round_rate = s5p6440_armclk_round_rate, |
248 | }; | 230 | }; |
249 | 231 | ||
250 | static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) | 232 | static struct clksrc_clk clk_armclk = { |
251 | { | 233 | .clk = { |
252 | unsigned long rate = clk_get_rate(clk->parent); | 234 | .name = "armclk", |
235 | .id = 1, | ||
236 | .parent = &clk_mout_apll.clk, | ||
237 | .ops = &s5p6440_clkarm_ops, | ||
238 | }, | ||
239 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 }, | ||
240 | }; | ||
253 | 241 | ||
254 | if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) | 242 | static struct clksrc_clk clk_dout_mpll = { |
255 | rate /= 2; | 243 | .clk = { |
244 | .name = "dout_mpll", | ||
245 | .id = -1, | ||
246 | .parent = &clk_mout_mpll.clk, | ||
247 | }, | ||
248 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, | ||
249 | }; | ||
256 | 250 | ||
257 | return rate; | 251 | static struct clksrc_clk clk_hclk = { |
258 | } | 252 | .clk = { |
253 | .name = "clk_hclk", | ||
254 | .id = -1, | ||
255 | .parent = &clk_armclk.clk, | ||
256 | }, | ||
257 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, | ||
258 | }; | ||
259 | 259 | ||
260 | static struct clk clk_dout_mpll = { | 260 | static struct clksrc_clk clk_pclk = { |
261 | .name = "dout_mpll", | 261 | .clk = { |
262 | .id = -1, | 262 | .name = "clk_pclk", |
263 | .parent = &clk_mout_mpll.clk, | 263 | .id = -1, |
264 | .ops = &(struct clk_ops) { | 264 | .parent = &clk_hclk.clk, |
265 | .get_rate = s5p6440_clk_doutmpll_get_rate, | ||
266 | }, | 265 | }, |
266 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 }, | ||
267 | }; | ||
268 | |||
269 | static struct clk *clkset_hclklow_list[] = { | ||
270 | &clk_mout_apll.clk, | ||
271 | &clk_mout_mpll.clk, | ||
272 | }; | ||
273 | |||
274 | static struct clksrc_sources clkset_hclklow = { | ||
275 | .sources = clkset_hclklow_list, | ||
276 | .nr_sources = ARRAY_SIZE(clkset_hclklow_list), | ||
277 | }; | ||
278 | |||
279 | static struct clksrc_clk clk_hclk_low = { | ||
280 | .clk = { | ||
281 | .name = "hclk_low", | ||
282 | .id = -1, | ||
283 | }, | ||
284 | .sources = &clkset_hclklow, | ||
285 | .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 }, | ||
286 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | ||
287 | }; | ||
288 | |||
289 | static struct clksrc_clk clk_pclk_low = { | ||
290 | .clk = { | ||
291 | .name = "pclk_low", | ||
292 | .id = -1, | ||
293 | .parent = &clk_hclk_low.clk, | ||
294 | }, | ||
295 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | ||
267 | }; | 296 | }; |
268 | 297 | ||
269 | int s5p6440_clk48m_ctrl(struct clk *clk, int enable) | 298 | int s5p6440_clk48m_ctrl(struct clk *clk, int enable) |
@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable) | |||
307 | return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); | 336 | return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); |
308 | } | 337 | } |
309 | 338 | ||
339 | static int s5p6440_sclk1_ctrl(struct clk *clk, int enable) | ||
340 | { | ||
341 | return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable); | ||
342 | } | ||
343 | |||
310 | static int s5p6440_mem_ctrl(struct clk *clk, int enable) | 344 | static int s5p6440_mem_ctrl(struct clk *clk, int enable) |
311 | { | 345 | { |
312 | return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); | 346 | return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); |
@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = { | |||
321 | { | 355 | { |
322 | .name = "nand", | 356 | .name = "nand", |
323 | .id = -1, | 357 | .id = -1, |
324 | .parent = &clk_h, | 358 | .parent = &clk_hclk.clk, |
325 | .enable = s5p6440_mem_ctrl, | 359 | .enable = s5p6440_mem_ctrl, |
326 | .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, | 360 | .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, |
327 | }, { | 361 | }, { |
328 | .name = "adc", | 362 | .name = "adc", |
329 | .id = -1, | 363 | .id = -1, |
330 | .parent = &clk_p_low, | 364 | .parent = &clk_pclk_low.clk, |
331 | .enable = s5p6440_pclk_ctrl, | 365 | .enable = s5p6440_pclk_ctrl, |
332 | .ctrlbit = S5P_CLKCON_PCLK_TSADC, | 366 | .ctrlbit = S5P_CLKCON_PCLK_TSADC, |
333 | }, { | 367 | }, { |
334 | .name = "i2c", | 368 | .name = "i2c", |
335 | .id = -1, | 369 | .id = -1, |
336 | .parent = &clk_p_low, | 370 | .parent = &clk_pclk_low.clk, |
337 | .enable = s5p6440_pclk_ctrl, | 371 | .enable = s5p6440_pclk_ctrl, |
338 | .ctrlbit = S5P_CLKCON_PCLK_IIC0, | 372 | .ctrlbit = S5P_CLKCON_PCLK_IIC0, |
339 | }, { | 373 | }, { |
340 | .name = "i2s_v40", | 374 | .name = "i2s_v40", |
341 | .id = 0, | 375 | .id = 0, |
342 | .parent = &clk_p_low, | 376 | .parent = &clk_pclk_low.clk, |
343 | .enable = s5p6440_pclk_ctrl, | 377 | .enable = s5p6440_pclk_ctrl, |
344 | .ctrlbit = S5P_CLKCON_PCLK_IIS2, | 378 | .ctrlbit = S5P_CLKCON_PCLK_IIS2, |
345 | }, { | 379 | }, { |
346 | .name = "spi", | 380 | .name = "spi", |
347 | .id = 0, | 381 | .id = 0, |
348 | .parent = &clk_p_low, | 382 | .parent = &clk_pclk_low.clk, |
349 | .enable = s5p6440_pclk_ctrl, | 383 | .enable = s5p6440_pclk_ctrl, |
350 | .ctrlbit = S5P_CLKCON_PCLK_SPI0, | 384 | .ctrlbit = S5P_CLKCON_PCLK_SPI0, |
351 | }, { | 385 | }, { |
352 | .name = "spi", | 386 | .name = "spi", |
353 | .id = 1, | 387 | .id = 1, |
354 | .parent = &clk_p_low, | 388 | .parent = &clk_pclk_low.clk, |
355 | .enable = s5p6440_pclk_ctrl, | 389 | .enable = s5p6440_pclk_ctrl, |
356 | .ctrlbit = S5P_CLKCON_PCLK_SPI1, | 390 | .ctrlbit = S5P_CLKCON_PCLK_SPI1, |
357 | }, { | 391 | }, { |
@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = { | |||
387 | }, { | 421 | }, { |
388 | .name = "otg", | 422 | .name = "otg", |
389 | .id = -1, | 423 | .id = -1, |
390 | .parent = &clk_h_low, | 424 | .parent = &clk_hclk_low.clk, |
391 | .enable = s5p6440_hclk0_ctrl, | 425 | .enable = s5p6440_hclk0_ctrl, |
392 | .ctrlbit = S5P_CLKCON_HCLK0_USB | 426 | .ctrlbit = S5P_CLKCON_HCLK0_USB |
393 | }, { | 427 | }, { |
394 | .name = "post", | 428 | .name = "post", |
395 | .id = -1, | 429 | .id = -1, |
396 | .parent = &clk_h_low, | 430 | .parent = &clk_hclk_low.clk, |
397 | .enable = s5p6440_hclk0_ctrl, | 431 | .enable = s5p6440_hclk0_ctrl, |
398 | .ctrlbit = S5P_CLKCON_HCLK0_POST0 | 432 | .ctrlbit = S5P_CLKCON_HCLK0_POST0 |
399 | }, { | 433 | }, { |
400 | .name = "lcd", | 434 | .name = "lcd", |
401 | .id = -1, | 435 | .id = -1, |
402 | .parent = &clk_h_low, | 436 | .parent = &clk_hclk_low.clk, |
403 | .enable = s5p6440_hclk1_ctrl, | 437 | .enable = s5p6440_hclk1_ctrl, |
404 | .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, | 438 | .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, |
405 | }, { | 439 | }, { |
406 | .name = "hsmmc", | 440 | .name = "hsmmc", |
407 | .id = 0, | 441 | .id = 0, |
408 | .parent = &clk_h_low, | 442 | .parent = &clk_hclk_low.clk, |
409 | .enable = s5p6440_hclk0_ctrl, | 443 | .enable = s5p6440_hclk0_ctrl, |
410 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, | 444 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, |
411 | }, { | 445 | }, { |
412 | .name = "hsmmc", | 446 | .name = "hsmmc", |
413 | .id = 1, | 447 | .id = 1, |
414 | .parent = &clk_h_low, | 448 | .parent = &clk_hclk_low.clk, |
415 | .enable = s5p6440_hclk0_ctrl, | 449 | .enable = s5p6440_hclk0_ctrl, |
416 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, | 450 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, |
417 | }, { | 451 | }, { |
418 | .name = "hsmmc", | 452 | .name = "hsmmc", |
419 | .id = 2, | 453 | .id = 2, |
420 | .parent = &clk_h_low, | 454 | .parent = &clk_hclk_low.clk, |
421 | .enable = s5p6440_hclk0_ctrl, | 455 | .enable = s5p6440_hclk0_ctrl, |
422 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, | 456 | .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, |
423 | }, { | 457 | }, { |
424 | .name = "rtc", | 458 | .name = "rtc", |
425 | .id = -1, | 459 | .id = -1, |
426 | .parent = &clk_p_low, | 460 | .parent = &clk_pclk_low.clk, |
427 | .enable = s5p6440_pclk_ctrl, | 461 | .enable = s5p6440_pclk_ctrl, |
428 | .ctrlbit = S5P_CLKCON_PCLK_RTC, | 462 | .ctrlbit = S5P_CLKCON_PCLK_RTC, |
429 | }, { | 463 | }, { |
430 | .name = "watchdog", | 464 | .name = "watchdog", |
431 | .id = -1, | 465 | .id = -1, |
432 | .parent = &clk_p_low, | 466 | .parent = &clk_pclk_low.clk, |
433 | .enable = s5p6440_pclk_ctrl, | 467 | .enable = s5p6440_pclk_ctrl, |
434 | .ctrlbit = S5P_CLKCON_PCLK_WDT, | 468 | .ctrlbit = S5P_CLKCON_PCLK_WDT, |
435 | }, { | 469 | }, { |
436 | .name = "timers", | 470 | .name = "timers", |
437 | .id = -1, | 471 | .id = -1, |
438 | .parent = &clk_p_low, | 472 | .parent = &clk_pclk_low.clk, |
439 | .enable = s5p6440_pclk_ctrl, | 473 | .enable = s5p6440_pclk_ctrl, |
440 | .ctrlbit = S5P_CLKCON_PCLK_PWM, | 474 | .ctrlbit = S5P_CLKCON_PCLK_PWM, |
441 | } | 475 | }, { |
476 | .name = "hclk_fimgvg", | ||
477 | .id = -1, | ||
478 | .parent = &clk_hclk.clk, | ||
479 | .enable = s5p6440_hclk1_ctrl, | ||
480 | .ctrlbit = (1 << 2), | ||
481 | }, { | ||
482 | .name = "tsi", | ||
483 | .id = -1, | ||
484 | .parent = &clk_hclk_low.clk, | ||
485 | .enable = s5p6440_hclk1_ctrl, | ||
486 | .ctrlbit = (1 << 0), | ||
487 | }, { | ||
488 | .name = "pclk_fimgvg", | ||
489 | .id = -1, | ||
490 | .parent = &clk_pclk.clk, | ||
491 | .enable = s5p6440_pclk_ctrl, | ||
492 | .ctrlbit = (1 << 31), | ||
493 | }, { | ||
494 | .name = "dmc0", | ||
495 | .id = -1, | ||
496 | .parent = &clk_pclk.clk, | ||
497 | .enable = s5p6440_pclk_ctrl, | ||
498 | .ctrlbit = (1 << 30), | ||
499 | }, { | ||
500 | .name = "etm", | ||
501 | .id = -1, | ||
502 | .parent = &clk_pclk.clk, | ||
503 | .enable = s5p6440_pclk_ctrl, | ||
504 | .ctrlbit = (1 << 29), | ||
505 | }, { | ||
506 | .name = "dsim", | ||
507 | .id = -1, | ||
508 | .parent = &clk_pclk_low.clk, | ||
509 | .enable = s5p6440_pclk_ctrl, | ||
510 | .ctrlbit = (1 << 28), | ||
511 | }, { | ||
512 | .name = "gps", | ||
513 | .id = -1, | ||
514 | .parent = &clk_pclk_low.clk, | ||
515 | .enable = s5p6440_pclk_ctrl, | ||
516 | .ctrlbit = (1 << 25), | ||
517 | }, { | ||
518 | .name = "pcm", | ||
519 | .id = -1, | ||
520 | .parent = &clk_pclk_low.clk, | ||
521 | .enable = s5p6440_pclk_ctrl, | ||
522 | .ctrlbit = (1 << 8), | ||
523 | }, { | ||
524 | .name = "irom", | ||
525 | .id = -1, | ||
526 | .parent = &clk_hclk.clk, | ||
527 | .enable = s5p6440_hclk0_ctrl, | ||
528 | .ctrlbit = (1 << 25), | ||
529 | }, { | ||
530 | .name = "dma", | ||
531 | .id = -1, | ||
532 | .parent = &clk_hclk_low.clk, | ||
533 | .enable = s5p6440_hclk0_ctrl, | ||
534 | .ctrlbit = (1 << 12), | ||
535 | }, { | ||
536 | .name = "2d", | ||
537 | .id = -1, | ||
538 | .parent = &clk_hclk.clk, | ||
539 | .enable = s5p6440_hclk0_ctrl, | ||
540 | .ctrlbit = (1 << 8), | ||
541 | }, | ||
442 | }; | 542 | }; |
443 | 543 | ||
444 | /* | 544 | /* |
@@ -448,34 +548,46 @@ static struct clk init_clocks[] = { | |||
448 | { | 548 | { |
449 | .name = "gpio", | 549 | .name = "gpio", |
450 | .id = -1, | 550 | .id = -1, |
451 | .parent = &clk_p_low, | 551 | .parent = &clk_pclk_low.clk, |
452 | .enable = s5p6440_pclk_ctrl, | 552 | .enable = s5p6440_pclk_ctrl, |
453 | .ctrlbit = S5P_CLKCON_PCLK_GPIO, | 553 | .ctrlbit = S5P_CLKCON_PCLK_GPIO, |
454 | }, { | 554 | }, { |
455 | .name = "uart", | 555 | .name = "uart", |
456 | .id = 0, | 556 | .id = 0, |
457 | .parent = &clk_p_low, | 557 | .parent = &clk_pclk_low.clk, |
458 | .enable = s5p6440_pclk_ctrl, | 558 | .enable = s5p6440_pclk_ctrl, |
459 | .ctrlbit = S5P_CLKCON_PCLK_UART0, | 559 | .ctrlbit = S5P_CLKCON_PCLK_UART0, |
460 | }, { | 560 | }, { |
461 | .name = "uart", | 561 | .name = "uart", |
462 | .id = 1, | 562 | .id = 1, |
463 | .parent = &clk_p_low, | 563 | .parent = &clk_pclk_low.clk, |
464 | .enable = s5p6440_pclk_ctrl, | 564 | .enable = s5p6440_pclk_ctrl, |
465 | .ctrlbit = S5P_CLKCON_PCLK_UART1, | 565 | .ctrlbit = S5P_CLKCON_PCLK_UART1, |
466 | }, { | 566 | }, { |
467 | .name = "uart", | 567 | .name = "uart", |
468 | .id = 2, | 568 | .id = 2, |
469 | .parent = &clk_p_low, | 569 | .parent = &clk_pclk_low.clk, |
470 | .enable = s5p6440_pclk_ctrl, | 570 | .enable = s5p6440_pclk_ctrl, |
471 | .ctrlbit = S5P_CLKCON_PCLK_UART2, | 571 | .ctrlbit = S5P_CLKCON_PCLK_UART2, |
472 | }, { | 572 | }, { |
473 | .name = "uart", | 573 | .name = "uart", |
474 | .id = 3, | 574 | .id = 3, |
475 | .parent = &clk_p_low, | 575 | .parent = &clk_pclk_low.clk, |
476 | .enable = s5p6440_pclk_ctrl, | 576 | .enable = s5p6440_pclk_ctrl, |
477 | .ctrlbit = S5P_CLKCON_PCLK_UART3, | 577 | .ctrlbit = S5P_CLKCON_PCLK_UART3, |
478 | } | 578 | }, { |
579 | .name = "mem", | ||
580 | .id = -1, | ||
581 | .parent = &clk_hclk.clk, | ||
582 | .enable = s5p6440_hclk0_ctrl, | ||
583 | .ctrlbit = (1 << 21), | ||
584 | }, { | ||
585 | .name = "intc", | ||
586 | .id = -1, | ||
587 | .parent = &clk_hclk.clk, | ||
588 | .enable = s5p6440_hclk0_ctrl, | ||
589 | .ctrlbit = (1 << 1), | ||
590 | }, | ||
479 | }; | 591 | }; |
480 | 592 | ||
481 | static struct clk clk_iis_cd_v40 = { | 593 | static struct clk clk_iis_cd_v40 = { |
@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = { | |||
488 | .id = -1, | 600 | .id = -1, |
489 | }; | 601 | }; |
490 | 602 | ||
491 | static struct clk *clkset_spi_mmc_list[] = { | 603 | static struct clk *clkset_group1_list[] = { |
492 | &clk_mout_epll.clk, | 604 | &clk_mout_epll.clk, |
493 | &clk_dout_mpll, | 605 | &clk_dout_mpll.clk, |
494 | &clk_fin_epll, | 606 | &clk_fin_epll, |
495 | }; | 607 | }; |
496 | 608 | ||
497 | static struct clksrc_sources clkset_spi_mmc = { | 609 | static struct clksrc_sources clkset_group1 = { |
498 | .sources = clkset_spi_mmc_list, | 610 | .sources = clkset_group1_list, |
499 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), | 611 | .nr_sources = ARRAY_SIZE(clkset_group1_list), |
500 | }; | 612 | }; |
501 | 613 | ||
502 | static struct clk *clkset_uart_list[] = { | 614 | static struct clk *clkset_uart_list[] = { |
503 | &clk_mout_epll.clk, | 615 | &clk_mout_epll.clk, |
504 | &clk_dout_mpll | 616 | &clk_dout_mpll.clk, |
505 | }; | 617 | }; |
506 | 618 | ||
507 | static struct clksrc_sources clkset_uart = { | 619 | static struct clksrc_sources clkset_uart = { |
@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = { | |||
509 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | 621 | .nr_sources = ARRAY_SIZE(clkset_uart_list), |
510 | }; | 622 | }; |
511 | 623 | ||
624 | static struct clk *clkset_audio_list[] = { | ||
625 | &clk_mout_epll.clk, | ||
626 | &clk_dout_mpll.clk, | ||
627 | &clk_fin_epll, | ||
628 | &clk_iis_cd_v40, | ||
629 | &clk_pcm_cd, | ||
630 | }; | ||
631 | |||
632 | static struct clksrc_sources clkset_audio = { | ||
633 | .sources = clkset_audio_list, | ||
634 | .nr_sources = ARRAY_SIZE(clkset_audio_list), | ||
635 | }; | ||
636 | |||
512 | static struct clksrc_clk clksrcs[] = { | 637 | static struct clksrc_clk clksrcs[] = { |
513 | { | 638 | { |
514 | .clk = { | 639 | .clk = { |
@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = { | |||
517 | .ctrlbit = S5P_CLKCON_SCLK0_MMC0, | 642 | .ctrlbit = S5P_CLKCON_SCLK0_MMC0, |
518 | .enable = s5p6440_sclk_ctrl, | 643 | .enable = s5p6440_sclk_ctrl, |
519 | }, | 644 | }, |
520 | .sources = &clkset_spi_mmc, | 645 | .sources = &clkset_group1, |
521 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, | 646 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, |
522 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, | 647 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, |
523 | }, { | 648 | }, { |
@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = { | |||
527 | .ctrlbit = S5P_CLKCON_SCLK0_MMC1, | 652 | .ctrlbit = S5P_CLKCON_SCLK0_MMC1, |
528 | .enable = s5p6440_sclk_ctrl, | 653 | .enable = s5p6440_sclk_ctrl, |
529 | }, | 654 | }, |
530 | .sources = &clkset_spi_mmc, | 655 | .sources = &clkset_group1, |
531 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, | 656 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, |
532 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, | 657 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, |
533 | }, { | 658 | }, { |
@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = { | |||
537 | .ctrlbit = S5P_CLKCON_SCLK0_MMC2, | 662 | .ctrlbit = S5P_CLKCON_SCLK0_MMC2, |
538 | .enable = s5p6440_sclk_ctrl, | 663 | .enable = s5p6440_sclk_ctrl, |
539 | }, | 664 | }, |
540 | .sources = &clkset_spi_mmc, | 665 | .sources = &clkset_group1, |
541 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, | 666 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, |
542 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, | 667 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, |
543 | }, { | 668 | }, { |
@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = { | |||
557 | .ctrlbit = S5P_CLKCON_SCLK0_SPI0, | 682 | .ctrlbit = S5P_CLKCON_SCLK0_SPI0, |
558 | .enable = s5p6440_sclk_ctrl, | 683 | .enable = s5p6440_sclk_ctrl, |
559 | }, | 684 | }, |
560 | .sources = &clkset_spi_mmc, | 685 | .sources = &clkset_group1, |
561 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, | 686 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, |
562 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | 687 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, |
563 | }, { | 688 | }, { |
@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = { | |||
567 | .ctrlbit = S5P_CLKCON_SCLK0_SPI1, | 692 | .ctrlbit = S5P_CLKCON_SCLK0_SPI1, |
568 | .enable = s5p6440_sclk_ctrl, | 693 | .enable = s5p6440_sclk_ctrl, |
569 | }, | 694 | }, |
570 | .sources = &clkset_spi_mmc, | 695 | .sources = &clkset_group1, |
571 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, | 696 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, |
572 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | 697 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, |
573 | } | 698 | }, { |
699 | .clk = { | ||
700 | .name = "sclk_post", | ||
701 | .id = -1, | ||
702 | .ctrlbit = (1 << 10), | ||
703 | .enable = s5p6440_sclk_ctrl, | ||
704 | }, | ||
705 | .sources = &clkset_group1, | ||
706 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 }, | ||
707 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, | ||
708 | }, { | ||
709 | .clk = { | ||
710 | .name = "sclk_dispcon", | ||
711 | .id = -1, | ||
712 | .ctrlbit = (1 << 1), | ||
713 | .enable = s5p6440_sclk1_ctrl, | ||
714 | }, | ||
715 | .sources = &clkset_group1, | ||
716 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, | ||
717 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, | ||
718 | }, { | ||
719 | .clk = { | ||
720 | .name = "sclk_fimgvg", | ||
721 | .id = -1, | ||
722 | .ctrlbit = (1 << 2), | ||
723 | .enable = s5p6440_sclk1_ctrl, | ||
724 | }, | ||
725 | .sources = &clkset_group1, | ||
726 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, | ||
727 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, | ||
728 | }, { | ||
729 | .clk = { | ||
730 | .name = "sclk_audio2", | ||
731 | .id = -1, | ||
732 | .ctrlbit = (1 << 11), | ||
733 | .enable = s5p6440_sclk_ctrl, | ||
734 | }, | ||
735 | .sources = &clkset_audio, | ||
736 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 }, | ||
737 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 }, | ||
738 | }, | ||
574 | }; | 739 | }; |
575 | 740 | ||
576 | /* Clock initialisation code */ | 741 | /* Clock initialisation code */ |
577 | static struct clksrc_clk *init_parents[] = { | 742 | static struct clksrc_clk *sysclks[] = { |
578 | &clk_mout_apll, | 743 | &clk_mout_apll, |
579 | &clk_mout_epll, | 744 | &clk_mout_epll, |
580 | &clk_mout_mpll, | 745 | &clk_mout_mpll, |
746 | &clk_dout_mpll, | ||
747 | &clk_armclk, | ||
748 | &clk_hclk, | ||
749 | &clk_pclk, | ||
750 | &clk_hclk_low, | ||
751 | &clk_pclk_low, | ||
581 | }; | 752 | }; |
582 | 753 | ||
583 | void __init_or_cpufreq s5p6440_setup_clocks(void) | 754 | void __init_or_cpufreq s5p6440_setup_clocks(void) |
@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) | |||
593 | unsigned long apll; | 764 | unsigned long apll; |
594 | unsigned long mpll; | 765 | unsigned long mpll; |
595 | unsigned int ptr; | 766 | unsigned int ptr; |
596 | u32 clkdiv0; | ||
597 | u32 clkdiv3; | ||
598 | 767 | ||
599 | /* Set S5P6440 functions for clk_fout_epll */ | 768 | /* Set S5P6440 functions for clk_fout_epll */ |
600 | clk_fout_epll.enable = s5p6440_epll_enable; | 769 | clk_fout_epll.enable = s5p6440_epll_enable; |
601 | clk_fout_epll.ops = &s5p6440_epll_ops; | 770 | clk_fout_epll.ops = &s5p6440_epll_ops; |
602 | 771 | ||
603 | /* Set S5P6440 functions for arm clock */ | ||
604 | clk_arm.parent = &clk_mout_apll.clk; | ||
605 | clk_arm.ops = &s5p6440_clkarm_ops; | ||
606 | clk_48m.enable = s5p6440_clk48m_ctrl; | 772 | clk_48m.enable = s5p6440_clk48m_ctrl; |
607 | 773 | ||
608 | clkdiv0 = __raw_readl(S5P_CLK_DIV0); | ||
609 | clkdiv3 = __raw_readl(S5P_CLK_DIV3); | ||
610 | |||
611 | xtal_clk = clk_get(NULL, "ext_xtal"); | 774 | xtal_clk = clk_get(NULL, "ext_xtal"); |
612 | BUG_ON(IS_ERR(xtal_clk)); | 775 | BUG_ON(IS_ERR(xtal_clk)); |
613 | 776 | ||
@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) | |||
619 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | 782 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); |
620 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); | 783 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); |
621 | 784 | ||
785 | clk_fout_mpll.rate = mpll; | ||
786 | clk_fout_epll.rate = epll; | ||
787 | clk_fout_apll.rate = apll; | ||
788 | |||
622 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | 789 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ |
623 | " E=%ld.%ldMHz\n", | 790 | " E=%ld.%ldMHz\n", |
624 | print_mhz(apll), print_mhz(mpll), print_mhz(epll)); | 791 | print_mhz(apll), print_mhz(mpll), print_mhz(epll)); |
625 | 792 | ||
626 | fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); | 793 | fclk = clk_get_rate(&clk_armclk.clk); |
627 | hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); | 794 | hclk = clk_get_rate(&clk_hclk.clk); |
628 | pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); | 795 | pclk = clk_get_rate(&clk_pclk.clk); |
629 | 796 | hclk_low = clk_get_rate(&clk_hclk_low.clk); | |
630 | if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { | 797 | pclk_low = clk_get_rate(&clk_pclk_low.clk); |
631 | /* Asynchronous mode */ | ||
632 | hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); | ||
633 | } else { | ||
634 | /* Synchronous mode */ | ||
635 | hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW); | ||
636 | } | ||
637 | |||
638 | pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW); | ||
639 | 798 | ||
640 | printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | 799 | printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ |
641 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | 800 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", |
642 | print_mhz(hclk), print_mhz(hclk_low), | 801 | print_mhz(hclk), print_mhz(hclk_low), |
643 | print_mhz(pclk), print_mhz(pclk_low)); | 802 | print_mhz(pclk), print_mhz(pclk_low)); |
644 | 803 | ||
645 | clk_fout_mpll.rate = mpll; | ||
646 | clk_fout_epll.rate = epll; | ||
647 | clk_fout_apll.rate = apll; | ||
648 | |||
649 | clk_f.rate = fclk; | 804 | clk_f.rate = fclk; |
650 | clk_h.rate = hclk; | 805 | clk_h.rate = hclk; |
651 | clk_p.rate = pclk; | 806 | clk_p.rate = pclk; |
652 | clk_h_low.rate = hclk_low; | ||
653 | clk_p_low.rate = pclk_low; | ||
654 | |||
655 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
656 | s3c_set_clksrc(init_parents[ptr], true); | ||
657 | 807 | ||
658 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | 808 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
659 | s3c_set_clksrc(&clksrcs[ptr], true); | 809 | s3c_set_clksrc(&clksrcs[ptr], true); |
@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) | |||
661 | 811 | ||
662 | static struct clk *clks[] __initdata = { | 812 | static struct clk *clks[] __initdata = { |
663 | &clk_ext, | 813 | &clk_ext, |
664 | &clk_mout_epll.clk, | ||
665 | &clk_mout_mpll.clk, | ||
666 | &clk_dout_mpll, | ||
667 | &clk_iis_cd_v40, | 814 | &clk_iis_cd_v40, |
668 | &clk_pcm_cd, | 815 | &clk_pcm_cd, |
669 | &clk_p_low, | ||
670 | &clk_h_low, | ||
671 | }; | 816 | }; |
672 | 817 | ||
673 | void __init s5p6440_register_clocks(void) | 818 | void __init s5p6440_register_clocks(void) |
@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void) | |||
680 | if (ret > 0) | 825 | if (ret > 0) |
681 | printk(KERN_ERR "Failed to register %u clocks\n", ret); | 826 | printk(KERN_ERR "Failed to register %u clocks\n", ret); |
682 | 827 | ||
828 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
829 | s3c_register_clksrc(sysclks[ptr], 1); | ||
830 | |||
683 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 831 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
684 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 832 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
685 | 833 | ||
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index 1794131aeacb..ca3b3206e6f8 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c | |||
@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void) | |||
88 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | 88 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
89 | } | 89 | } |
90 | 90 | ||
91 | static struct sysdev_class s5p6440_sysclass = { | 91 | struct sysdev_class s5p6440_sysclass = { |
92 | .name = "s5p6440-core", | 92 | .name = "s5p6440-core", |
93 | }; | 93 | }; |
94 | 94 | ||
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c new file mode 100644 index 000000000000..0c5367962830 --- /dev/null +++ b/arch/arm/mach-s5p6440/dev-audio.c | |||
@@ -0,0 +1,127 @@ | |||
1 | /* linux/arch/arm/mach-s5p6440/dev-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | ||
15 | #include <plat/audio.h> | ||
16 | |||
17 | #include <mach/gpio.h> | ||
18 | #include <mach/map.h> | ||
19 | #include <mach/dma.h> | ||
20 | #include <mach/irqs.h> | ||
21 | |||
22 | static int s5p6440_cfg_i2s(struct platform_device *pdev) | ||
23 | { | ||
24 | /* configure GPIO for i2s port */ | ||
25 | switch (pdev->id) { | ||
26 | case -1: | ||
27 | s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5)); | ||
28 | s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5)); | ||
29 | s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5)); | ||
30 | s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5)); | ||
31 | s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5)); | ||
32 | s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5)); | ||
33 | s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5)); | ||
34 | break; | ||
35 | |||
36 | default: | ||
37 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
38 | return -EINVAL; | ||
39 | } | ||
40 | |||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | static struct s3c_audio_pdata s3c_i2s_pdata = { | ||
45 | .cfg_gpio = s5p6440_cfg_i2s, | ||
46 | }; | ||
47 | |||
48 | static struct resource s5p6440_iis0_resource[] = { | ||
49 | [0] = { | ||
50 | .start = S5P6440_PA_I2S, | ||
51 | .end = S5P6440_PA_I2S + 0x100 - 1, | ||
52 | .flags = IORESOURCE_MEM, | ||
53 | }, | ||
54 | [1] = { | ||
55 | .start = DMACH_I2S0_TX, | ||
56 | .end = DMACH_I2S0_TX, | ||
57 | .flags = IORESOURCE_DMA, | ||
58 | }, | ||
59 | [2] = { | ||
60 | .start = DMACH_I2S0_RX, | ||
61 | .end = DMACH_I2S0_RX, | ||
62 | .flags = IORESOURCE_DMA, | ||
63 | }, | ||
64 | }; | ||
65 | |||
66 | struct platform_device s5p6440_device_iis = { | ||
67 | .name = "s3c64xx-iis-v4", | ||
68 | .id = -1, | ||
69 | .num_resources = ARRAY_SIZE(s5p6440_iis0_resource), | ||
70 | .resource = s5p6440_iis0_resource, | ||
71 | .dev = { | ||
72 | .platform_data = &s3c_i2s_pdata, | ||
73 | }, | ||
74 | }; | ||
75 | |||
76 | /* PCM Controller platform_devices */ | ||
77 | |||
78 | static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev) | ||
79 | { | ||
80 | switch (pdev->id) { | ||
81 | case 0: | ||
82 | s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2)); | ||
83 | s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2)); | ||
84 | s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2)); | ||
85 | s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2)); | ||
86 | s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2)); | ||
87 | break; | ||
88 | |||
89 | default: | ||
90 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
91 | return -EINVAL; | ||
92 | } | ||
93 | |||
94 | return 0; | ||
95 | } | ||
96 | |||
97 | static struct s3c_audio_pdata s3c_pcm_pdata = { | ||
98 | .cfg_gpio = s5p6440_pcm_cfg_gpio, | ||
99 | }; | ||
100 | |||
101 | static struct resource s5p6440_pcm0_resource[] = { | ||
102 | [0] = { | ||
103 | .start = S5P6440_PA_PCM, | ||
104 | .end = S5P6440_PA_PCM + 0x100 - 1, | ||
105 | .flags = IORESOURCE_MEM, | ||
106 | }, | ||
107 | [1] = { | ||
108 | .start = DMACH_PCM0_TX, | ||
109 | .end = DMACH_PCM0_TX, | ||
110 | .flags = IORESOURCE_DMA, | ||
111 | }, | ||
112 | [2] = { | ||
113 | .start = DMACH_PCM0_RX, | ||
114 | .end = DMACH_PCM0_RX, | ||
115 | .flags = IORESOURCE_DMA, | ||
116 | }, | ||
117 | }; | ||
118 | |||
119 | struct platform_device s5p6440_device_pcm = { | ||
120 | .name = "samsung-pcm", | ||
121 | .id = 0, | ||
122 | .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource), | ||
123 | .resource = s5p6440_pcm0_resource, | ||
124 | .dev = { | ||
125 | .platform_data = &s3c_pcm_pdata, | ||
126 | }, | ||
127 | }; | ||
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p6440/dma.c new file mode 100644 index 000000000000..07606ad57519 --- /dev/null +++ b/arch/arm/mach-s5p6440/dma.c | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/dma-mapping.h> | ||
22 | |||
23 | #include <plat/devs.h> | ||
24 | #include <plat/irqs.h> | ||
25 | |||
26 | #include <mach/map.h> | ||
27 | #include <mach/irqs.h> | ||
28 | |||
29 | #include <plat/s3c-pl330-pdata.h> | ||
30 | |||
31 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
32 | |||
33 | static struct resource s5p6440_pdma_resource[] = { | ||
34 | [0] = { | ||
35 | .start = S5P6440_PA_PDMA, | ||
36 | .end = S5P6440_PA_PDMA + SZ_4K, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, | ||
39 | [1] = { | ||
40 | .start = IRQ_DMA0, | ||
41 | .end = IRQ_DMA0, | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | }; | ||
45 | |||
46 | static struct s3c_pl330_platdata s5p6440_pdma_pdata = { | ||
47 | .peri = { | ||
48 | [0] = DMACH_UART0_RX, | ||
49 | [1] = DMACH_UART0_TX, | ||
50 | [2] = DMACH_UART1_RX, | ||
51 | [3] = DMACH_UART1_TX, | ||
52 | [4] = DMACH_UART2_RX, | ||
53 | [5] = DMACH_UART2_TX, | ||
54 | [6] = DMACH_UART3_RX, | ||
55 | [7] = DMACH_UART3_TX, | ||
56 | [8] = DMACH_MAX, | ||
57 | [9] = DMACH_MAX, | ||
58 | [10] = DMACH_PCM0_TX, | ||
59 | [11] = DMACH_PCM0_RX, | ||
60 | [12] = DMACH_I2S0_TX, | ||
61 | [13] = DMACH_I2S0_RX, | ||
62 | [14] = DMACH_SPI0_TX, | ||
63 | [15] = DMACH_SPI0_RX, | ||
64 | [16] = DMACH_MAX, | ||
65 | [17] = DMACH_MAX, | ||
66 | [18] = DMACH_MAX, | ||
67 | [19] = DMACH_MAX, | ||
68 | [20] = DMACH_SPI1_TX, | ||
69 | [21] = DMACH_SPI1_RX, | ||
70 | [22] = DMACH_MAX, | ||
71 | [23] = DMACH_MAX, | ||
72 | [24] = DMACH_MAX, | ||
73 | [25] = DMACH_MAX, | ||
74 | [26] = DMACH_MAX, | ||
75 | [27] = DMACH_MAX, | ||
76 | [28] = DMACH_MAX, | ||
77 | [29] = DMACH_PWM, | ||
78 | [30] = DMACH_MAX, | ||
79 | [31] = DMACH_MAX, | ||
80 | }, | ||
81 | }; | ||
82 | |||
83 | static struct platform_device s5p6440_device_pdma = { | ||
84 | .name = "s3c-pl330", | ||
85 | .id = 1, | ||
86 | .num_resources = ARRAY_SIZE(s5p6440_pdma_resource), | ||
87 | .resource = s5p6440_pdma_resource, | ||
88 | .dev = { | ||
89 | .dma_mask = &dma_dmamask, | ||
90 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
91 | .platform_data = &s5p6440_pdma_pdata, | ||
92 | }, | ||
93 | }; | ||
94 | |||
95 | static struct platform_device *s5p6440_dmacs[] __initdata = { | ||
96 | &s5p6440_device_pdma, | ||
97 | }; | ||
98 | |||
99 | static int __init s5p6440_dma_init(void) | ||
100 | { | ||
101 | platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs)); | ||
102 | |||
103 | return 0; | ||
104 | } | ||
105 | arch_initcall(s5p6440_dma_init); | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p6440/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/dma.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_DMA_H | ||
21 | #define __MACH_DMA_H | ||
22 | |||
23 | /* This platform uses the common S3C DMA API driver for PL330 */ | ||
24 | #include <plat/s3c-dma-pl330.h> | ||
25 | |||
26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 8924e5a4d6a6..72aedadd412c 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h | |||
@@ -29,6 +29,8 @@ | |||
29 | #define S5P6440_PA_VIC0 (0xE4000000) | 29 | #define S5P6440_PA_VIC0 (0xE4000000) |
30 | #define S5P_PA_VIC0 S5P6440_PA_VIC0 | 30 | #define S5P_PA_VIC0 S5P6440_PA_VIC0 |
31 | 31 | ||
32 | #define S5P6440_PA_PDMA 0xE9000000 | ||
33 | |||
32 | #define S5P6440_PA_VIC1 (0xE4100000) | 34 | #define S5P6440_PA_VIC1 (0xE4100000) |
33 | #define S5P_PA_VIC1 S5P6440_PA_VIC1 | 35 | #define S5P_PA_VIC1 S5P6440_PA_VIC1 |
34 | 36 | ||
@@ -61,6 +63,12 @@ | |||
61 | #define S5P6440_PA_SDRAM (0x20000000) | 63 | #define S5P6440_PA_SDRAM (0x20000000) |
62 | #define S5P_PA_SDRAM S5P6440_PA_SDRAM | 64 | #define S5P_PA_SDRAM S5P6440_PA_SDRAM |
63 | 65 | ||
66 | /* I2S */ | ||
67 | #define S5P6440_PA_I2S 0xF2000000 | ||
68 | |||
69 | /* PCM */ | ||
70 | #define S5P6440_PA_PCM 0xF2100000 | ||
71 | |||
64 | /* compatibiltiy defines. */ | 72 | /* compatibiltiy defines. */ |
65 | #define S3C_PA_UART S5P6440_PA_UART | 73 | #define S3C_PA_UART S5P6440_PA_UART |
66 | #define S3C_PA_IIC S5P6440_PA_IIC0 | 74 | #define S3C_PA_IIC S5P6440_PA_IIC0 |
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h index c4bb7c555477..6a2a02fdf12a 100644 --- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h | |||
@@ -1,11 +1,14 @@ | |||
1 | /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h | 1 | /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h |
2 | * | 2 | * |
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Copyright 2008 Openmoko, Inc. | ||
3 | * Copyright 2008 Simtec Electronics | 7 | * Copyright 2008 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 8 | * Ben Dooks <ben@simtec.co.uk> |
5 | * http://armlinux.simtec.co.uk/ | 9 | * http://armlinux.simtec.co.uk/ |
6 | * | 10 | * |
7 | * Copyright 2009 Samsung Electronics Co., Ltd. | 11 | * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h |
8 | * http://www.samsung.com/ | ||
9 | * | 12 | * |
10 | * S5P6440 - pwm clock and timer support | 13 | * S5P6440 - pwm clock and timer support |
11 | * | 14 | * |
@@ -14,16 +17,19 @@ | |||
14 | * published by the Free Software Foundation. | 17 | * published by the Free Software Foundation. |
15 | */ | 18 | */ |
16 | 19 | ||
20 | #ifndef __ASM_ARCH_PWMCLK_H | ||
21 | #define __ASM_ARCH_PWMCLK_H __FILE__ | ||
22 | |||
17 | /** | 23 | /** |
18 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | 24 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk |
19 | * @cfg: The timer TCFG1 register bits shifted down to 0. | 25 | * @tcfg: The timer TCFG1 register bits shifted down to 0. |
20 | * | 26 | * |
21 | * Return true if the given configuration from TCFG1 is a TCLK instead | 27 | * Return true if the given configuration from TCFG1 is a TCLK instead |
22 | * any of the TDIV clocks. | 28 | * any of the TDIV clocks. |
23 | */ | 29 | */ |
24 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | 30 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) |
25 | { | 31 | { |
26 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | 32 | return 0; |
27 | } | 33 | } |
28 | 34 | ||
29 | /** | 35 | /** |
@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | |||
35 | */ | 41 | */ |
36 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | 42 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) |
37 | { | 43 | { |
38 | return 1 << (1 + tcfg1); | 44 | return 1 << tcfg1; |
39 | } | 45 | } |
40 | 46 | ||
41 | /** | 47 | /** |
@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | |||
45 | */ | 51 | */ |
46 | static inline unsigned int pwm_tdiv_has_div1(void) | 52 | static inline unsigned int pwm_tdiv_has_div1(void) |
47 | { | 53 | { |
48 | return 0; | 54 | return 1; |
49 | } | 55 | } |
50 | 56 | ||
51 | /** | 57 | /** |
@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) | |||
56 | */ | 62 | */ |
57 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | 63 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) |
58 | { | 64 | { |
59 | return ilog2(div) - 1; | 65 | return ilog2(div); |
60 | } | 66 | } |
61 | 67 | ||
62 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | 68 | #define S3C_TCFG1_MUX_TCLK 0 |
69 | |||
70 | #endif /* __ASM_ARCH_PWMCLK_H */ | ||
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index 3ae88f2c7c77..d7fede971ca6 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c | |||
@@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { | |||
84 | }; | 84 | }; |
85 | 85 | ||
86 | static struct platform_device *smdk6440_devices[] __initdata = { | 86 | static struct platform_device *smdk6440_devices[] __initdata = { |
87 | &s5p6440_device_iis, | ||
87 | }; | 88 | }; |
88 | 89 | ||
89 | static void __init smdk6440_map_io(void) | 90 | static void __init smdk6440_map_io(void) |
diff --git a/arch/arm/plat-s5p/setup-i2c0.c b/arch/arm/mach-s5p6440/setup-i2c0.c index 67a66e02a97a..69e8a664aedb 100644 --- a/arch/arm/plat-s5p/setup-i2c0.c +++ b/arch/arm/mach-s5p6440/setup-i2c0.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* linux/arch/arm/plat-s5p/setup-i2c0.c | 1 | /* linux/arch/arm/mach-s5p6440/setup-i2c0.c |
2 | * | 2 | * |
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com/ | 4 | * http://www.samsung.com/ |
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig index 4f3f6de6a013..0fd41b447915 100644 --- a/arch/arm/mach-s5p6442/Kconfig +++ b/arch/arm/mach-s5p6442/Kconfig | |||
@@ -12,6 +12,7 @@ if ARCH_S5P6442 | |||
12 | config CPU_S5P6442 | 12 | config CPU_S5P6442 |
13 | bool | 13 | bool |
14 | select PLAT_S5P | 14 | select PLAT_S5P |
15 | select S3C_PL330_DMA | ||
15 | help | 16 | help |
16 | Enable S5P6442 CPU support | 17 | Enable S5P6442 CPU support |
17 | 18 | ||
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index dde39a6ce6bc..e30a7f76aee6 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile | |||
@@ -12,8 +12,12 @@ obj- := | |||
12 | 12 | ||
13 | # Core support for S5P6442 system | 13 | # Core support for S5P6442 system |
14 | 14 | ||
15 | obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o | 15 | obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o |
16 | obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o | ||
16 | 17 | ||
17 | # machine support | 18 | # machine support |
18 | 19 | ||
19 | obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o | 20 | obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o |
21 | |||
22 | # device support | ||
23 | obj-y += dev-audio.o | ||
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c index bc2524df89b3..a48fb553fd01 100644 --- a/arch/arm/mach-s5p6442/cpu.c +++ b/arch/arm/mach-s5p6442/cpu.c | |||
@@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void) | |||
95 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | 95 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
96 | } | 96 | } |
97 | 97 | ||
98 | static struct sysdev_class s5p6442_sysclass = { | 98 | struct sysdev_class s5p6442_sysclass = { |
99 | .name = "s5p6442-core", | 99 | .name = "s5p6442-core", |
100 | }; | 100 | }; |
101 | 101 | ||
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c new file mode 100644 index 000000000000..cb801e1f5e23 --- /dev/null +++ b/arch/arm/mach-s5p6442/dev-audio.c | |||
@@ -0,0 +1,197 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/dev-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | ||
15 | #include <plat/audio.h> | ||
16 | |||
17 | #include <mach/gpio.h> | ||
18 | #include <mach/map.h> | ||
19 | #include <mach/dma.h> | ||
20 | #include <mach/irqs.h> | ||
21 | |||
22 | static int s5p6442_cfg_i2s(struct platform_device *pdev) | ||
23 | { | ||
24 | /* configure GPIO for i2s port */ | ||
25 | switch (pdev->id) { | ||
26 | case 1: | ||
27 | s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2)); | ||
28 | s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2)); | ||
29 | s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2)); | ||
30 | s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2)); | ||
31 | s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2)); | ||
32 | break; | ||
33 | |||
34 | case -1: | ||
35 | s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2)); | ||
36 | s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2)); | ||
37 | s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2)); | ||
38 | s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2)); | ||
39 | s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2)); | ||
40 | break; | ||
41 | |||
42 | default: | ||
43 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
44 | return -EINVAL; | ||
45 | } | ||
46 | |||
47 | return 0; | ||
48 | } | ||
49 | |||
50 | static struct s3c_audio_pdata s3c_i2s_pdata = { | ||
51 | .cfg_gpio = s5p6442_cfg_i2s, | ||
52 | }; | ||
53 | |||
54 | static struct resource s5p6442_iis0_resource[] = { | ||
55 | [0] = { | ||
56 | .start = S5P6442_PA_I2S0, | ||
57 | .end = S5P6442_PA_I2S0 + 0x100 - 1, | ||
58 | .flags = IORESOURCE_MEM, | ||
59 | }, | ||
60 | [1] = { | ||
61 | .start = DMACH_I2S0_TX, | ||
62 | .end = DMACH_I2S0_TX, | ||
63 | .flags = IORESOURCE_DMA, | ||
64 | }, | ||
65 | [2] = { | ||
66 | .start = DMACH_I2S0_RX, | ||
67 | .end = DMACH_I2S0_RX, | ||
68 | .flags = IORESOURCE_DMA, | ||
69 | }, | ||
70 | }; | ||
71 | |||
72 | struct platform_device s5p6442_device_iis0 = { | ||
73 | .name = "s3c64xx-iis-v4", | ||
74 | .id = -1, | ||
75 | .num_resources = ARRAY_SIZE(s5p6442_iis0_resource), | ||
76 | .resource = s5p6442_iis0_resource, | ||
77 | .dev = { | ||
78 | .platform_data = &s3c_i2s_pdata, | ||
79 | }, | ||
80 | }; | ||
81 | |||
82 | static struct resource s5p6442_iis1_resource[] = { | ||
83 | [0] = { | ||
84 | .start = S5P6442_PA_I2S1, | ||
85 | .end = S5P6442_PA_I2S1 + 0x100 - 1, | ||
86 | .flags = IORESOURCE_MEM, | ||
87 | }, | ||
88 | [1] = { | ||
89 | .start = DMACH_I2S1_TX, | ||
90 | .end = DMACH_I2S1_TX, | ||
91 | .flags = IORESOURCE_DMA, | ||
92 | }, | ||
93 | [2] = { | ||
94 | .start = DMACH_I2S1_RX, | ||
95 | .end = DMACH_I2S1_RX, | ||
96 | .flags = IORESOURCE_DMA, | ||
97 | }, | ||
98 | }; | ||
99 | |||
100 | struct platform_device s5p6442_device_iis1 = { | ||
101 | .name = "s3c64xx-iis", | ||
102 | .id = 1, | ||
103 | .num_resources = ARRAY_SIZE(s5p6442_iis1_resource), | ||
104 | .resource = s5p6442_iis1_resource, | ||
105 | .dev = { | ||
106 | .platform_data = &s3c_i2s_pdata, | ||
107 | }, | ||
108 | }; | ||
109 | |||
110 | /* PCM Controller platform_devices */ | ||
111 | |||
112 | static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev) | ||
113 | { | ||
114 | switch (pdev->id) { | ||
115 | case 0: | ||
116 | s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3)); | ||
117 | s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3)); | ||
118 | s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3)); | ||
119 | s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3)); | ||
120 | s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3)); | ||
121 | break; | ||
122 | |||
123 | case 1: | ||
124 | s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3)); | ||
125 | s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3)); | ||
126 | s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3)); | ||
127 | s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3)); | ||
128 | s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3)); | ||
129 | break; | ||
130 | |||
131 | default: | ||
132 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
133 | return -EINVAL; | ||
134 | } | ||
135 | |||
136 | return 0; | ||
137 | } | ||
138 | |||
139 | static struct s3c_audio_pdata s3c_pcm_pdata = { | ||
140 | .cfg_gpio = s5p6442_pcm_cfg_gpio, | ||
141 | }; | ||
142 | |||
143 | static struct resource s5p6442_pcm0_resource[] = { | ||
144 | [0] = { | ||
145 | .start = S5P6442_PA_PCM0, | ||
146 | .end = S5P6442_PA_PCM0 + 0x100 - 1, | ||
147 | .flags = IORESOURCE_MEM, | ||
148 | }, | ||
149 | [1] = { | ||
150 | .start = DMACH_PCM0_TX, | ||
151 | .end = DMACH_PCM0_TX, | ||
152 | .flags = IORESOURCE_DMA, | ||
153 | }, | ||
154 | [2] = { | ||
155 | .start = DMACH_PCM0_RX, | ||
156 | .end = DMACH_PCM0_RX, | ||
157 | .flags = IORESOURCE_DMA, | ||
158 | }, | ||
159 | }; | ||
160 | |||
161 | struct platform_device s5p6442_device_pcm0 = { | ||
162 | .name = "samsung-pcm", | ||
163 | .id = 0, | ||
164 | .num_resources = ARRAY_SIZE(s5p6442_pcm0_resource), | ||
165 | .resource = s5p6442_pcm0_resource, | ||
166 | .dev = { | ||
167 | .platform_data = &s3c_pcm_pdata, | ||
168 | }, | ||
169 | }; | ||
170 | |||
171 | static struct resource s5p6442_pcm1_resource[] = { | ||
172 | [0] = { | ||
173 | .start = S5P6442_PA_PCM1, | ||
174 | .end = S5P6442_PA_PCM1 + 0x100 - 1, | ||
175 | .flags = IORESOURCE_MEM, | ||
176 | }, | ||
177 | [1] = { | ||
178 | .start = DMACH_PCM1_TX, | ||
179 | .end = DMACH_PCM1_TX, | ||
180 | .flags = IORESOURCE_DMA, | ||
181 | }, | ||
182 | [2] = { | ||
183 | .start = DMACH_PCM1_RX, | ||
184 | .end = DMACH_PCM1_RX, | ||
185 | .flags = IORESOURCE_DMA, | ||
186 | }, | ||
187 | }; | ||
188 | |||
189 | struct platform_device s5p6442_device_pcm1 = { | ||
190 | .name = "samsung-pcm", | ||
191 | .id = 1, | ||
192 | .num_resources = ARRAY_SIZE(s5p6442_pcm1_resource), | ||
193 | .resource = s5p6442_pcm1_resource, | ||
194 | .dev = { | ||
195 | .platform_data = &s3c_pcm_pdata, | ||
196 | }, | ||
197 | }; | ||
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c new file mode 100644 index 000000000000..ad4f8704b93d --- /dev/null +++ b/arch/arm/mach-s5p6442/dma.c | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/dma-mapping.h> | ||
22 | |||
23 | #include <plat/devs.h> | ||
24 | #include <plat/irqs.h> | ||
25 | |||
26 | #include <mach/map.h> | ||
27 | #include <mach/irqs.h> | ||
28 | |||
29 | #include <plat/s3c-pl330-pdata.h> | ||
30 | |||
31 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
32 | |||
33 | static struct resource s5p6442_pdma_resource[] = { | ||
34 | [0] = { | ||
35 | .start = S5P6442_PA_PDMA, | ||
36 | .end = S5P6442_PA_PDMA + SZ_4K, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, | ||
39 | [1] = { | ||
40 | .start = IRQ_PDMA, | ||
41 | .end = IRQ_PDMA, | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | }; | ||
45 | |||
46 | static struct s3c_pl330_platdata s5p6442_pdma_pdata = { | ||
47 | .peri = { | ||
48 | [0] = DMACH_UART0_RX, | ||
49 | [1] = DMACH_UART0_TX, | ||
50 | [2] = DMACH_UART1_RX, | ||
51 | [3] = DMACH_UART1_TX, | ||
52 | [4] = DMACH_UART2_RX, | ||
53 | [5] = DMACH_UART2_TX, | ||
54 | [6] = DMACH_MAX, | ||
55 | [7] = DMACH_MAX, | ||
56 | [8] = DMACH_MAX, | ||
57 | [9] = DMACH_I2S0_RX, | ||
58 | [10] = DMACH_I2S0_TX, | ||
59 | [11] = DMACH_I2S0S_TX, | ||
60 | [12] = DMACH_I2S1_RX, | ||
61 | [13] = DMACH_I2S1_TX, | ||
62 | [14] = DMACH_MAX, | ||
63 | [15] = DMACH_MAX, | ||
64 | [16] = DMACH_SPI0_RX, | ||
65 | [17] = DMACH_SPI0_TX, | ||
66 | [18] = DMACH_MAX, | ||
67 | [19] = DMACH_MAX, | ||
68 | [20] = DMACH_PCM0_RX, | ||
69 | [21] = DMACH_PCM0_TX, | ||
70 | [22] = DMACH_PCM1_RX, | ||
71 | [23] = DMACH_PCM1_TX, | ||
72 | [24] = DMACH_MAX, | ||
73 | [25] = DMACH_MAX, | ||
74 | [26] = DMACH_MAX, | ||
75 | [27] = DMACH_MSM_REQ0, | ||
76 | [28] = DMACH_MSM_REQ1, | ||
77 | [29] = DMACH_MSM_REQ2, | ||
78 | [30] = DMACH_MSM_REQ3, | ||
79 | [31] = DMACH_MAX, | ||
80 | }, | ||
81 | }; | ||
82 | |||
83 | static struct platform_device s5p6442_device_pdma = { | ||
84 | .name = "s3c-pl330", | ||
85 | .id = 1, | ||
86 | .num_resources = ARRAY_SIZE(s5p6442_pdma_resource), | ||
87 | .resource = s5p6442_pdma_resource, | ||
88 | .dev = { | ||
89 | .dma_mask = &dma_dmamask, | ||
90 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
91 | .platform_data = &s5p6442_pdma_pdata, | ||
92 | }, | ||
93 | }; | ||
94 | |||
95 | static struct platform_device *s5p6442_dmacs[] __initdata = { | ||
96 | &s5p6442_device_pdma, | ||
97 | }; | ||
98 | |||
99 | static int __init s5p6442_dma_init(void) | ||
100 | { | ||
101 | platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs)); | ||
102 | |||
103 | return 0; | ||
104 | } | ||
105 | arch_initcall(s5p6442_dma_init); | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/dma.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_DMA_H | ||
21 | #define __MACH_DMA_H | ||
22 | |||
23 | /* This platform uses the common S3C DMA API driver for PL330 */ | ||
24 | #include <plat/s3c-dma-pl330.h> | ||
25 | |||
26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 685277d792fb..7568dc0d6be0 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h | |||
@@ -34,6 +34,9 @@ | |||
34 | #define S5P6442_PA_VIC2 (0xE4200000) | 34 | #define S5P6442_PA_VIC2 (0xE4200000) |
35 | #define S5P_PA_VIC2 S5P6442_PA_VIC2 | 35 | #define S5P_PA_VIC2 S5P6442_PA_VIC2 |
36 | 36 | ||
37 | #define S5P6442_PA_MDMA 0xE8000000 | ||
38 | #define S5P6442_PA_PDMA 0xE9000000 | ||
39 | |||
37 | #define S5P6442_PA_TIMER (0xEA000000) | 40 | #define S5P6442_PA_TIMER (0xEA000000) |
38 | #define S5P_PA_TIMER S5P6442_PA_TIMER | 41 | #define S5P_PA_TIMER S5P6442_PA_TIMER |
39 | 42 | ||
@@ -51,6 +54,14 @@ | |||
51 | #define S5P6442_PA_SDRAM (0x20000000) | 54 | #define S5P6442_PA_SDRAM (0x20000000) |
52 | #define S5P_PA_SDRAM S5P6442_PA_SDRAM | 55 | #define S5P_PA_SDRAM S5P6442_PA_SDRAM |
53 | 56 | ||
57 | /* I2S */ | ||
58 | #define S5P6442_PA_I2S0 0xC0B00000 | ||
59 | #define S5P6442_PA_I2S1 0xF2200000 | ||
60 | |||
61 | /* PCM */ | ||
62 | #define S5P6442_PA_PCM0 0xF2400000 | ||
63 | #define S5P6442_PA_PCM1 0xF2500000 | ||
64 | |||
54 | /* compatibiltiy defines. */ | 65 | /* compatibiltiy defines. */ |
55 | #define S3C_PA_UART S5P6442_PA_UART | 66 | #define S3C_PA_UART S5P6442_PA_UART |
56 | #define S3C_PA_IIC S5P6442_PA_IIC0 | 67 | #define S3C_PA_IIC S5P6442_PA_IIC0 |
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h index 15e8525da0f1..2724b37def31 100644 --- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h | |||
@@ -1,13 +1,14 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h | 1 | /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h |
2 | * | 2 | * |
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Copyright 2008 Openmoko, Inc. | ||
3 | * Copyright 2008 Simtec Electronics | 7 | * Copyright 2008 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 8 | * Ben Dooks <ben@simtec.co.uk> |
5 | * http://armlinux.simtec.co.uk/ | 9 | * http://armlinux.simtec.co.uk/ |
6 | * | 10 | * |
7 | * Copyright 2010 Samsung Electronics Co., Ltd. | 11 | * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h |
8 | * http://www.samsung.com/ | ||
9 | * | ||
10 | * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
11 | * | 12 | * |
12 | * S5P6442 - pwm clock and timer support | 13 | * S5P6442 - pwm clock and timer support |
13 | * | 14 | * |
@@ -21,14 +22,14 @@ | |||
21 | 22 | ||
22 | /** | 23 | /** |
23 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | 24 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk |
24 | * @cfg: The timer TCFG1 register bits shifted down to 0. | 25 | * @tcfg: The timer TCFG1 register bits shifted down to 0. |
25 | * | 26 | * |
26 | * Return true if the given configuration from TCFG1 is a TCLK instead | 27 | * Return true if the given configuration from TCFG1 is a TCLK instead |
27 | * any of the TDIV clocks. | 28 | * any of the TDIV clocks. |
28 | */ | 29 | */ |
29 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | 30 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) |
30 | { | 31 | { |
31 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | 32 | return tcfg == S3C64XX_TCFG1_MUX_TCLK; |
32 | } | 33 | } |
33 | 34 | ||
34 | /** | 35 | /** |
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | |||
40 | */ | 41 | */ |
41 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | 42 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) |
42 | { | 43 | { |
43 | return 1 << (1 + tcfg1); | 44 | return 1 << tcfg1; |
44 | } | 45 | } |
45 | 46 | ||
46 | /** | 47 | /** |
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | |||
50 | */ | 51 | */ |
51 | static inline unsigned int pwm_tdiv_has_div1(void) | 52 | static inline unsigned int pwm_tdiv_has_div1(void) |
52 | { | 53 | { |
53 | return 0; | 54 | return 1; |
54 | } | 55 | } |
55 | 56 | ||
56 | /** | 57 | /** |
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) | |||
61 | */ | 62 | */ |
62 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | 63 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) |
63 | { | 64 | { |
64 | return ilog2(div) - 1; | 65 | return ilog2(div); |
65 | } | 66 | } |
66 | 67 | ||
67 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | 68 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK |
68 | 69 | ||
69 | #endif /* __ASM_ARCH_PWMCLK_H */ | 70 | #endif /* __ASM_ARCH_PWMCLK_H */ |
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c index 0d63371ce07c..ebcf99777259 100644 --- a/arch/arm/mach-s5p6442/mach-smdk6442.c +++ b/arch/arm/mach-s5p6442/mach-smdk6442.c | |||
@@ -65,6 +65,7 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { | |||
65 | }; | 65 | }; |
66 | 66 | ||
67 | static struct platform_device *smdk6442_devices[] __initdata = { | 67 | static struct platform_device *smdk6442_devices[] __initdata = { |
68 | &s5p6442_device_iis0, | ||
68 | }; | 69 | }; |
69 | 70 | ||
70 | static void __init smdk6442_map_io(void) | 71 | static void __init smdk6442_map_io(void) |
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c new file mode 100644 index 000000000000..662695dd7761 --- /dev/null +++ b/arch/arm/mach-s5p6442/setup-i2c0.c | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/mach-s5p6442/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * I2C0 GPIO configuration. | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <plat/iic.h> | ||
21 | |||
22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
23 | { | ||
24 | /* Will be populated later */ | ||
25 | } | ||
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 27ec167d2808..8593337784e1 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig | |||
@@ -12,12 +12,22 @@ config CPU_S5PC100 | |||
12 | help | 12 | help |
13 | Enable S5PC100 CPU support | 13 | Enable S5PC100 CPU support |
14 | 14 | ||
15 | config S5PC100_SETUP_FB_24BPP | ||
16 | bool | ||
17 | help | ||
18 | Common setup code for S5PC1XX with an 24bpp RGB display helper. | ||
19 | |||
15 | config S5PC100_SETUP_SDHCI | 20 | config S5PC100_SETUP_SDHCI |
16 | bool | 21 | bool |
17 | select S5PC1XX_SETUP_SDHCI_GPIO | 22 | select S5PC1XX_SETUP_SDHCI_GPIO |
18 | help | 23 | help |
19 | Internal helper functions for S5PC100 based SDHCI systems | 24 | Internal helper functions for S5PC100 based SDHCI systems |
20 | 25 | ||
26 | config S5PC100_SETUP_I2C1 | ||
27 | bool | ||
28 | help | ||
29 | Common setup code for i2c bus 1. | ||
30 | |||
21 | config MACH_SMDKC100 | 31 | config MACH_SMDKC100 |
22 | bool "SMDKC100" | 32 | bool "SMDKC100" |
23 | select CPU_S5PC100 | 33 | select CPU_S5PC100 |
@@ -26,9 +36,8 @@ config MACH_SMDKC100 | |||
26 | select S3C_DEV_HSMMC | 36 | select S3C_DEV_HSMMC |
27 | select S3C_DEV_HSMMC1 | 37 | select S3C_DEV_HSMMC1 |
28 | select S3C_DEV_HSMMC2 | 38 | select S3C_DEV_HSMMC2 |
29 | select S5PC1XX_SETUP_I2C0 | 39 | select S5PC100_SETUP_FB_24BPP |
30 | select S5PC1XX_SETUP_I2C1 | 40 | select S5PC100_SETUP_I2C1 |
31 | select S5PC1XX_SETUP_FB_24BPP | ||
32 | select S5PC100_SETUP_SDHCI | 41 | select S5PC100_SETUP_SDHCI |
33 | help | 42 | help |
34 | Machine support for the Samsung SMDKC100 | 43 | Machine support for the Samsung SMDKC100 |
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 809ff10f768f..373bc546eae8 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile | |||
@@ -11,10 +11,13 @@ obj- := | |||
11 | 11 | ||
12 | # Core support for S5PC100 system | 12 | # Core support for S5PC100 system |
13 | 13 | ||
14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o | 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o |
15 | obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o | ||
15 | 16 | ||
16 | # Helper and device support | 17 | # Helper and device support |
17 | 18 | ||
19 | obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
20 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o | ||
18 | obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o | 21 | obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o |
19 | 22 | ||
20 | # machine support | 23 | # machine support |
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c new file mode 100644 index 000000000000..e3fed4cfe7ad --- /dev/null +++ b/arch/arm/mach-s5pc100/clock.c | |||
@@ -0,0 +1,1358 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PC100 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <mach/map.h> | ||
22 | |||
23 | #include <plat/cpu-freq.h> | ||
24 | #include <mach/regs-clock.h> | ||
25 | #include <plat/clock.h> | ||
26 | #include <plat/cpu.h> | ||
27 | #include <plat/pll.h> | ||
28 | #include <plat/s5p-clock.h> | ||
29 | #include <plat/clock-clksrc.h> | ||
30 | #include <plat/s5pc100.h> | ||
31 | |||
32 | static struct clk s5p_clk_otgphy = { | ||
33 | .name = "otg_phy", | ||
34 | .id = -1, | ||
35 | }; | ||
36 | |||
37 | static struct clk *clk_src_mout_href_list[] = { | ||
38 | [0] = &s5p_clk_27m, | ||
39 | [1] = &clk_fin_hpll, | ||
40 | }; | ||
41 | |||
42 | static struct clksrc_sources clk_src_mout_href = { | ||
43 | .sources = clk_src_mout_href_list, | ||
44 | .nr_sources = ARRAY_SIZE(clk_src_mout_href_list), | ||
45 | }; | ||
46 | |||
47 | static struct clksrc_clk clk_mout_href = { | ||
48 | .clk = { | ||
49 | .name = "mout_href", | ||
50 | .id = -1, | ||
51 | }, | ||
52 | .sources = &clk_src_mout_href, | ||
53 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | ||
54 | }; | ||
55 | |||
56 | static struct clk *clk_src_mout_48m_list[] = { | ||
57 | [0] = &clk_xusbxti, | ||
58 | [1] = &s5p_clk_otgphy, | ||
59 | }; | ||
60 | |||
61 | static struct clksrc_sources clk_src_mout_48m = { | ||
62 | .sources = clk_src_mout_48m_list, | ||
63 | .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list), | ||
64 | }; | ||
65 | |||
66 | static struct clksrc_clk clk_mout_48m = { | ||
67 | .clk = { | ||
68 | .name = "mout_48m", | ||
69 | .id = -1, | ||
70 | }, | ||
71 | .sources = &clk_src_mout_48m, | ||
72 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, | ||
73 | }; | ||
74 | |||
75 | static struct clksrc_clk clk_mout_mpll = { | ||
76 | .clk = { | ||
77 | .name = "mout_mpll", | ||
78 | .id = -1, | ||
79 | }, | ||
80 | .sources = &clk_src_mpll, | ||
81 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | ||
82 | }; | ||
83 | |||
84 | |||
85 | static struct clksrc_clk clk_mout_apll = { | ||
86 | .clk = { | ||
87 | .name = "mout_apll", | ||
88 | .id = -1, | ||
89 | }, | ||
90 | .sources = &clk_src_apll, | ||
91 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
92 | }; | ||
93 | |||
94 | static struct clksrc_clk clk_mout_epll = { | ||
95 | .clk = { | ||
96 | .name = "mout_epll", | ||
97 | .id = -1, | ||
98 | }, | ||
99 | .sources = &clk_src_epll, | ||
100 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | ||
101 | }; | ||
102 | |||
103 | static struct clk *clk_src_mout_hpll_list[] = { | ||
104 | [0] = &s5p_clk_27m, | ||
105 | }; | ||
106 | |||
107 | static struct clksrc_sources clk_src_mout_hpll = { | ||
108 | .sources = clk_src_mout_hpll_list, | ||
109 | .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list), | ||
110 | }; | ||
111 | |||
112 | static struct clksrc_clk clk_mout_hpll = { | ||
113 | .clk = { | ||
114 | .name = "mout_hpll", | ||
115 | .id = -1, | ||
116 | }, | ||
117 | .sources = &clk_src_mout_hpll, | ||
118 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | ||
119 | }; | ||
120 | |||
121 | static struct clksrc_clk clk_div_apll = { | ||
122 | .clk = { | ||
123 | .name = "div_apll", | ||
124 | .id = -1, | ||
125 | .parent = &clk_mout_apll.clk, | ||
126 | }, | ||
127 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, | ||
128 | }; | ||
129 | |||
130 | static struct clksrc_clk clk_div_arm = { | ||
131 | .clk = { | ||
132 | .name = "div_arm", | ||
133 | .id = -1, | ||
134 | .parent = &clk_div_apll.clk, | ||
135 | }, | ||
136 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | ||
137 | }; | ||
138 | |||
139 | static struct clksrc_clk clk_div_d0_bus = { | ||
140 | .clk = { | ||
141 | .name = "div_d0_bus", | ||
142 | .id = -1, | ||
143 | .parent = &clk_div_arm.clk, | ||
144 | }, | ||
145 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | ||
146 | }; | ||
147 | |||
148 | static struct clksrc_clk clk_div_pclkd0 = { | ||
149 | .clk = { | ||
150 | .name = "div_pclkd0", | ||
151 | .id = -1, | ||
152 | .parent = &clk_div_d0_bus.clk, | ||
153 | }, | ||
154 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | ||
155 | }; | ||
156 | |||
157 | static struct clksrc_clk clk_div_secss = { | ||
158 | .clk = { | ||
159 | .name = "div_secss", | ||
160 | .id = -1, | ||
161 | .parent = &clk_div_d0_bus.clk, | ||
162 | }, | ||
163 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, | ||
164 | }; | ||
165 | |||
166 | static struct clksrc_clk clk_div_apll2 = { | ||
167 | .clk = { | ||
168 | .name = "div_apll2", | ||
169 | .id = -1, | ||
170 | .parent = &clk_mout_apll.clk, | ||
171 | }, | ||
172 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, | ||
173 | }; | ||
174 | |||
175 | static struct clk *clk_src_mout_am_list[] = { | ||
176 | [0] = &clk_mout_mpll.clk, | ||
177 | [1] = &clk_div_apll2.clk, | ||
178 | }; | ||
179 | |||
180 | struct clksrc_sources clk_src_mout_am = { | ||
181 | .sources = clk_src_mout_am_list, | ||
182 | .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), | ||
183 | }; | ||
184 | |||
185 | static struct clksrc_clk clk_mout_am = { | ||
186 | .clk = { | ||
187 | .name = "mout_am", | ||
188 | .id = -1, | ||
189 | }, | ||
190 | .sources = &clk_src_mout_am, | ||
191 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | ||
192 | }; | ||
193 | |||
194 | static struct clksrc_clk clk_div_d1_bus = { | ||
195 | .clk = { | ||
196 | .name = "div_d1_bus", | ||
197 | .id = -1, | ||
198 | .parent = &clk_mout_am.clk, | ||
199 | }, | ||
200 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, | ||
201 | }; | ||
202 | |||
203 | static struct clksrc_clk clk_div_mpll2 = { | ||
204 | .clk = { | ||
205 | .name = "div_mpll2", | ||
206 | .id = -1, | ||
207 | .parent = &clk_mout_am.clk, | ||
208 | }, | ||
209 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, | ||
210 | }; | ||
211 | |||
212 | static struct clksrc_clk clk_div_mpll = { | ||
213 | .clk = { | ||
214 | .name = "div_mpll", | ||
215 | .id = -1, | ||
216 | .parent = &clk_mout_am.clk, | ||
217 | }, | ||
218 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, | ||
219 | }; | ||
220 | |||
221 | static struct clk *clk_src_mout_onenand_list[] = { | ||
222 | [0] = &clk_div_d0_bus.clk, | ||
223 | [1] = &clk_div_d1_bus.clk, | ||
224 | }; | ||
225 | |||
226 | struct clksrc_sources clk_src_mout_onenand = { | ||
227 | .sources = clk_src_mout_onenand_list, | ||
228 | .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), | ||
229 | }; | ||
230 | |||
231 | static struct clksrc_clk clk_mout_onenand = { | ||
232 | .clk = { | ||
233 | .name = "mout_onenand", | ||
234 | .id = -1, | ||
235 | }, | ||
236 | .sources = &clk_src_mout_onenand, | ||
237 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | ||
238 | }; | ||
239 | |||
240 | static struct clksrc_clk clk_div_onenand = { | ||
241 | .clk = { | ||
242 | .name = "div_onenand", | ||
243 | .id = -1, | ||
244 | .parent = &clk_mout_onenand.clk, | ||
245 | }, | ||
246 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, | ||
247 | }; | ||
248 | |||
249 | static struct clksrc_clk clk_div_pclkd1 = { | ||
250 | .clk = { | ||
251 | .name = "div_pclkd1", | ||
252 | .id = -1, | ||
253 | .parent = &clk_div_d1_bus.clk, | ||
254 | }, | ||
255 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, | ||
256 | }; | ||
257 | |||
258 | static struct clksrc_clk clk_div_cam = { | ||
259 | .clk = { | ||
260 | .name = "div_cam", | ||
261 | .id = -1, | ||
262 | .parent = &clk_div_mpll2.clk, | ||
263 | }, | ||
264 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, | ||
265 | }; | ||
266 | |||
267 | static struct clksrc_clk clk_div_hdmi = { | ||
268 | .clk = { | ||
269 | .name = "div_hdmi", | ||
270 | .id = -1, | ||
271 | .parent = &clk_mout_hpll.clk, | ||
272 | }, | ||
273 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | ||
274 | }; | ||
275 | |||
276 | static int s5pc100_epll_enable(struct clk *clk, int enable) | ||
277 | { | ||
278 | unsigned int ctrlbit = clk->ctrlbit; | ||
279 | unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit; | ||
280 | |||
281 | if (enable) | ||
282 | __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON); | ||
283 | else | ||
284 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
285 | |||
286 | return 0; | ||
287 | } | ||
288 | |||
289 | static unsigned long s5pc100_epll_get_rate(struct clk *clk) | ||
290 | { | ||
291 | return clk->rate; | ||
292 | } | ||
293 | |||
294 | static u32 epll_div[][4] = { | ||
295 | { 32750000, 131, 3, 4 }, | ||
296 | { 32768000, 131, 3, 4 }, | ||
297 | { 36000000, 72, 3, 3 }, | ||
298 | { 45000000, 90, 3, 3 }, | ||
299 | { 45158000, 90, 3, 3 }, | ||
300 | { 45158400, 90, 3, 3 }, | ||
301 | { 48000000, 96, 3, 3 }, | ||
302 | { 49125000, 131, 4, 3 }, | ||
303 | { 49152000, 131, 4, 3 }, | ||
304 | { 60000000, 120, 3, 3 }, | ||
305 | { 67737600, 226, 5, 3 }, | ||
306 | { 67738000, 226, 5, 3 }, | ||
307 | { 73800000, 246, 5, 3 }, | ||
308 | { 73728000, 246, 5, 3 }, | ||
309 | { 72000000, 144, 3, 3 }, | ||
310 | { 84000000, 168, 3, 3 }, | ||
311 | { 96000000, 96, 3, 2 }, | ||
312 | { 144000000, 144, 3, 2 }, | ||
313 | { 192000000, 96, 3, 1 } | ||
314 | }; | ||
315 | |||
316 | static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) | ||
317 | { | ||
318 | unsigned int epll_con; | ||
319 | unsigned int i; | ||
320 | |||
321 | if (clk->rate == rate) /* Return if nothing changed */ | ||
322 | return 0; | ||
323 | |||
324 | epll_con = __raw_readl(S5P_EPLL_CON); | ||
325 | |||
326 | epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK); | ||
327 | |||
328 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | ||
329 | if (epll_div[i][0] == rate) { | ||
330 | epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) | | ||
331 | (epll_div[i][2] << PLL65XX_PDIV_SHIFT) | | ||
332 | (epll_div[i][3] << PLL65XX_SDIV_SHIFT); | ||
333 | break; | ||
334 | } | ||
335 | } | ||
336 | |||
337 | if (i == ARRAY_SIZE(epll_div)) { | ||
338 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | ||
339 | return -EINVAL; | ||
340 | } | ||
341 | |||
342 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
343 | |||
344 | clk->rate = rate; | ||
345 | |||
346 | return 0; | ||
347 | } | ||
348 | |||
349 | static struct clk_ops s5pc100_epll_ops = { | ||
350 | .get_rate = s5pc100_epll_get_rate, | ||
351 | .set_rate = s5pc100_epll_set_rate, | ||
352 | }; | ||
353 | |||
354 | static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) | ||
355 | { | ||
356 | return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable); | ||
357 | } | ||
358 | |||
359 | static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) | ||
360 | { | ||
361 | return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable); | ||
362 | } | ||
363 | |||
364 | static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) | ||
365 | { | ||
366 | return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable); | ||
367 | } | ||
368 | |||
369 | static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) | ||
370 | { | ||
371 | return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable); | ||
372 | } | ||
373 | |||
374 | static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) | ||
375 | { | ||
376 | return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable); | ||
377 | } | ||
378 | |||
379 | static int s5pc100_d1_2_ctrl(struct clk *clk, int enable) | ||
380 | { | ||
381 | return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable); | ||
382 | } | ||
383 | |||
384 | static int s5pc100_d1_3_ctrl(struct clk *clk, int enable) | ||
385 | { | ||
386 | return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable); | ||
387 | } | ||
388 | |||
389 | static int s5pc100_d1_4_ctrl(struct clk *clk, int enable) | ||
390 | { | ||
391 | return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable); | ||
392 | } | ||
393 | |||
394 | static int s5pc100_d1_5_ctrl(struct clk *clk, int enable) | ||
395 | { | ||
396 | return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable); | ||
397 | } | ||
398 | |||
399 | static int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | ||
400 | { | ||
401 | return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable); | ||
402 | } | ||
403 | |||
404 | static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | ||
405 | { | ||
406 | return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable); | ||
407 | } | ||
408 | |||
409 | /* | ||
410 | * The following clocks will be disabled during clock initialization. It is | ||
411 | * recommended to keep the following clocks disabled until the driver requests | ||
412 | * for enabling the clock. | ||
413 | */ | ||
414 | static struct clk init_clocks_disable[] = { | ||
415 | { | ||
416 | .name = "cssys", | ||
417 | .id = -1, | ||
418 | .parent = &clk_div_d0_bus.clk, | ||
419 | .enable = s5pc100_d0_0_ctrl, | ||
420 | .ctrlbit = (1 << 6), | ||
421 | }, { | ||
422 | .name = "secss", | ||
423 | .id = -1, | ||
424 | .parent = &clk_div_d0_bus.clk, | ||
425 | .enable = s5pc100_d0_0_ctrl, | ||
426 | .ctrlbit = (1 << 5), | ||
427 | }, { | ||
428 | .name = "g2d", | ||
429 | .id = -1, | ||
430 | .parent = &clk_div_d0_bus.clk, | ||
431 | .enable = s5pc100_d0_0_ctrl, | ||
432 | .ctrlbit = (1 << 4), | ||
433 | }, { | ||
434 | .name = "mdma", | ||
435 | .id = -1, | ||
436 | .parent = &clk_div_d0_bus.clk, | ||
437 | .enable = s5pc100_d0_0_ctrl, | ||
438 | .ctrlbit = (1 << 3), | ||
439 | }, { | ||
440 | .name = "cfcon", | ||
441 | .id = -1, | ||
442 | .parent = &clk_div_d0_bus.clk, | ||
443 | .enable = s5pc100_d0_0_ctrl, | ||
444 | .ctrlbit = (1 << 2), | ||
445 | }, { | ||
446 | .name = "nfcon", | ||
447 | .id = -1, | ||
448 | .parent = &clk_div_d0_bus.clk, | ||
449 | .enable = s5pc100_d0_1_ctrl, | ||
450 | .ctrlbit = (1 << 3), | ||
451 | }, { | ||
452 | .name = "onenandc", | ||
453 | .id = -1, | ||
454 | .parent = &clk_div_d0_bus.clk, | ||
455 | .enable = s5pc100_d0_1_ctrl, | ||
456 | .ctrlbit = (1 << 2), | ||
457 | }, { | ||
458 | .name = "sdm", | ||
459 | .id = -1, | ||
460 | .parent = &clk_div_d0_bus.clk, | ||
461 | .enable = s5pc100_d0_2_ctrl, | ||
462 | .ctrlbit = (1 << 2), | ||
463 | }, { | ||
464 | .name = "seckey", | ||
465 | .id = -1, | ||
466 | .parent = &clk_div_d0_bus.clk, | ||
467 | .enable = s5pc100_d0_2_ctrl, | ||
468 | .ctrlbit = (1 << 1), | ||
469 | }, { | ||
470 | .name = "hsmmc", | ||
471 | .id = 2, | ||
472 | .parent = &clk_div_d1_bus.clk, | ||
473 | .enable = s5pc100_d1_0_ctrl, | ||
474 | .ctrlbit = (1 << 7), | ||
475 | }, { | ||
476 | .name = "hsmmc", | ||
477 | .id = 1, | ||
478 | .parent = &clk_div_d1_bus.clk, | ||
479 | .enable = s5pc100_d1_0_ctrl, | ||
480 | .ctrlbit = (1 << 6), | ||
481 | }, { | ||
482 | .name = "hsmmc", | ||
483 | .id = 0, | ||
484 | .parent = &clk_div_d1_bus.clk, | ||
485 | .enable = s5pc100_d1_0_ctrl, | ||
486 | .ctrlbit = (1 << 5), | ||
487 | }, { | ||
488 | .name = "modemif", | ||
489 | .id = -1, | ||
490 | .parent = &clk_div_d1_bus.clk, | ||
491 | .enable = s5pc100_d1_0_ctrl, | ||
492 | .ctrlbit = (1 << 4), | ||
493 | }, { | ||
494 | .name = "otg", | ||
495 | .id = -1, | ||
496 | .parent = &clk_div_d1_bus.clk, | ||
497 | .enable = s5pc100_d1_0_ctrl, | ||
498 | .ctrlbit = (1 << 3), | ||
499 | }, { | ||
500 | .name = "usbhost", | ||
501 | .id = -1, | ||
502 | .parent = &clk_div_d1_bus.clk, | ||
503 | .enable = s5pc100_d1_0_ctrl, | ||
504 | .ctrlbit = (1 << 2), | ||
505 | }, { | ||
506 | .name = "pdma", | ||
507 | .id = 1, | ||
508 | .parent = &clk_div_d1_bus.clk, | ||
509 | .enable = s5pc100_d1_0_ctrl, | ||
510 | .ctrlbit = (1 << 1), | ||
511 | }, { | ||
512 | .name = "pdma", | ||
513 | .id = 0, | ||
514 | .parent = &clk_div_d1_bus.clk, | ||
515 | .enable = s5pc100_d1_0_ctrl, | ||
516 | .ctrlbit = (1 << 0), | ||
517 | }, { | ||
518 | .name = "lcd", | ||
519 | .id = -1, | ||
520 | .parent = &clk_div_d1_bus.clk, | ||
521 | .enable = s5pc100_d1_1_ctrl, | ||
522 | .ctrlbit = (1 << 0), | ||
523 | }, { | ||
524 | .name = "rotator", | ||
525 | .id = -1, | ||
526 | .parent = &clk_div_d1_bus.clk, | ||
527 | .enable = s5pc100_d1_1_ctrl, | ||
528 | .ctrlbit = (1 << 1), | ||
529 | }, { | ||
530 | .name = "fimc", | ||
531 | .id = 0, | ||
532 | .parent = &clk_div_d1_bus.clk, | ||
533 | .enable = s5pc100_d1_1_ctrl, | ||
534 | .ctrlbit = (1 << 2), | ||
535 | }, { | ||
536 | .name = "fimc", | ||
537 | .id = 1, | ||
538 | .parent = &clk_div_d1_bus.clk, | ||
539 | .enable = s5pc100_d1_1_ctrl, | ||
540 | .ctrlbit = (1 << 3), | ||
541 | }, { | ||
542 | .name = "fimc", | ||
543 | .id = 2, | ||
544 | .parent = &clk_div_d1_bus.clk, | ||
545 | .enable = s5pc100_d1_1_ctrl, | ||
546 | .ctrlbit = (1 << 4), | ||
547 | }, { | ||
548 | .name = "jpeg", | ||
549 | .id = -1, | ||
550 | .parent = &clk_div_d1_bus.clk, | ||
551 | .enable = s5pc100_d1_1_ctrl, | ||
552 | .ctrlbit = (1 << 5), | ||
553 | }, { | ||
554 | .name = "mipi-dsim", | ||
555 | .id = -1, | ||
556 | .parent = &clk_div_d1_bus.clk, | ||
557 | .enable = s5pc100_d1_1_ctrl, | ||
558 | .ctrlbit = (1 << 6), | ||
559 | }, { | ||
560 | .name = "mipi-csis", | ||
561 | .id = -1, | ||
562 | .parent = &clk_div_d1_bus.clk, | ||
563 | .enable = s5pc100_d1_1_ctrl, | ||
564 | .ctrlbit = (1 << 7), | ||
565 | }, { | ||
566 | .name = "g3d", | ||
567 | .id = 0, | ||
568 | .parent = &clk_div_d1_bus.clk, | ||
569 | .enable = s5pc100_d1_0_ctrl, | ||
570 | .ctrlbit = (1 << 8), | ||
571 | }, { | ||
572 | .name = "tv", | ||
573 | .id = -1, | ||
574 | .parent = &clk_div_d1_bus.clk, | ||
575 | .enable = s5pc100_d1_2_ctrl, | ||
576 | .ctrlbit = (1 << 0), | ||
577 | }, { | ||
578 | .name = "vp", | ||
579 | .id = -1, | ||
580 | .parent = &clk_div_d1_bus.clk, | ||
581 | .enable = s5pc100_d1_2_ctrl, | ||
582 | .ctrlbit = (1 << 1), | ||
583 | }, { | ||
584 | .name = "mixer", | ||
585 | .id = -1, | ||
586 | .parent = &clk_div_d1_bus.clk, | ||
587 | .enable = s5pc100_d1_2_ctrl, | ||
588 | .ctrlbit = (1 << 2), | ||
589 | }, { | ||
590 | .name = "hdmi", | ||
591 | .id = -1, | ||
592 | .parent = &clk_div_d1_bus.clk, | ||
593 | .enable = s5pc100_d1_2_ctrl, | ||
594 | .ctrlbit = (1 << 3), | ||
595 | }, { | ||
596 | .name = "mfc", | ||
597 | .id = -1, | ||
598 | .parent = &clk_div_d1_bus.clk, | ||
599 | .enable = s5pc100_d1_2_ctrl, | ||
600 | .ctrlbit = (1 << 4), | ||
601 | }, { | ||
602 | .name = "apc", | ||
603 | .id = -1, | ||
604 | .parent = &clk_div_d1_bus.clk, | ||
605 | .enable = s5pc100_d1_3_ctrl, | ||
606 | .ctrlbit = (1 << 2), | ||
607 | }, { | ||
608 | .name = "iec", | ||
609 | .id = -1, | ||
610 | .parent = &clk_div_d1_bus.clk, | ||
611 | .enable = s5pc100_d1_3_ctrl, | ||
612 | .ctrlbit = (1 << 3), | ||
613 | }, { | ||
614 | .name = "systimer", | ||
615 | .id = -1, | ||
616 | .parent = &clk_div_d1_bus.clk, | ||
617 | .enable = s5pc100_d1_3_ctrl, | ||
618 | .ctrlbit = (1 << 7), | ||
619 | }, { | ||
620 | .name = "watchdog", | ||
621 | .id = -1, | ||
622 | .parent = &clk_div_d1_bus.clk, | ||
623 | .enable = s5pc100_d1_3_ctrl, | ||
624 | .ctrlbit = (1 << 8), | ||
625 | }, { | ||
626 | .name = "rtc", | ||
627 | .id = -1, | ||
628 | .parent = &clk_div_d1_bus.clk, | ||
629 | .enable = s5pc100_d1_3_ctrl, | ||
630 | .ctrlbit = (1 << 9), | ||
631 | }, { | ||
632 | .name = "i2c", | ||
633 | .id = 0, | ||
634 | .parent = &clk_div_d1_bus.clk, | ||
635 | .enable = s5pc100_d1_4_ctrl, | ||
636 | .ctrlbit = (1 << 4), | ||
637 | }, { | ||
638 | .name = "i2c", | ||
639 | .id = 1, | ||
640 | .parent = &clk_div_d1_bus.clk, | ||
641 | .enable = s5pc100_d1_4_ctrl, | ||
642 | .ctrlbit = (1 << 5), | ||
643 | }, { | ||
644 | .name = "spi", | ||
645 | .id = 0, | ||
646 | .parent = &clk_div_d1_bus.clk, | ||
647 | .enable = s5pc100_d1_4_ctrl, | ||
648 | .ctrlbit = (1 << 6), | ||
649 | }, { | ||
650 | .name = "spi", | ||
651 | .id = 1, | ||
652 | .parent = &clk_div_d1_bus.clk, | ||
653 | .enable = s5pc100_d1_4_ctrl, | ||
654 | .ctrlbit = (1 << 7), | ||
655 | }, { | ||
656 | .name = "spi", | ||
657 | .id = 2, | ||
658 | .parent = &clk_div_d1_bus.clk, | ||
659 | .enable = s5pc100_d1_4_ctrl, | ||
660 | .ctrlbit = (1 << 8), | ||
661 | }, { | ||
662 | .name = "irda", | ||
663 | .id = -1, | ||
664 | .parent = &clk_div_d1_bus.clk, | ||
665 | .enable = s5pc100_d1_4_ctrl, | ||
666 | .ctrlbit = (1 << 9), | ||
667 | }, { | ||
668 | .name = "ccan", | ||
669 | .id = 0, | ||
670 | .parent = &clk_div_d1_bus.clk, | ||
671 | .enable = s5pc100_d1_4_ctrl, | ||
672 | .ctrlbit = (1 << 10), | ||
673 | }, { | ||
674 | .name = "ccan", | ||
675 | .id = 1, | ||
676 | .parent = &clk_div_d1_bus.clk, | ||
677 | .enable = s5pc100_d1_4_ctrl, | ||
678 | .ctrlbit = (1 << 11), | ||
679 | }, { | ||
680 | .name = "hsitx", | ||
681 | .id = -1, | ||
682 | .parent = &clk_div_d1_bus.clk, | ||
683 | .enable = s5pc100_d1_4_ctrl, | ||
684 | .ctrlbit = (1 << 12), | ||
685 | }, { | ||
686 | .name = "hsirx", | ||
687 | .id = -1, | ||
688 | .parent = &clk_div_d1_bus.clk, | ||
689 | .enable = s5pc100_d1_4_ctrl, | ||
690 | .ctrlbit = (1 << 13), | ||
691 | }, { | ||
692 | .name = "iis", | ||
693 | .id = 0, | ||
694 | .parent = &clk_div_d1_bus.clk, | ||
695 | .enable = s5pc100_d1_5_ctrl, | ||
696 | .ctrlbit = (1 << 0), | ||
697 | }, { | ||
698 | .name = "iis", | ||
699 | .id = 1, | ||
700 | .parent = &clk_div_d1_bus.clk, | ||
701 | .enable = s5pc100_d1_5_ctrl, | ||
702 | .ctrlbit = (1 << 1), | ||
703 | }, { | ||
704 | .name = "iis", | ||
705 | .id = 2, | ||
706 | .parent = &clk_div_d1_bus.clk, | ||
707 | .enable = s5pc100_d1_5_ctrl, | ||
708 | .ctrlbit = (1 << 2), | ||
709 | }, { | ||
710 | .name = "ac97", | ||
711 | .id = -1, | ||
712 | .parent = &clk_div_d1_bus.clk, | ||
713 | .enable = s5pc100_d1_5_ctrl, | ||
714 | .ctrlbit = (1 << 3), | ||
715 | }, { | ||
716 | .name = "pcm", | ||
717 | .id = 0, | ||
718 | .parent = &clk_div_d1_bus.clk, | ||
719 | .enable = s5pc100_d1_5_ctrl, | ||
720 | .ctrlbit = (1 << 4), | ||
721 | }, { | ||
722 | .name = "pcm", | ||
723 | .id = 1, | ||
724 | .parent = &clk_div_d1_bus.clk, | ||
725 | .enable = s5pc100_d1_5_ctrl, | ||
726 | .ctrlbit = (1 << 5), | ||
727 | }, { | ||
728 | .name = "spdif", | ||
729 | .id = -1, | ||
730 | .parent = &clk_div_d1_bus.clk, | ||
731 | .enable = s5pc100_d1_5_ctrl, | ||
732 | .ctrlbit = (1 << 6), | ||
733 | }, { | ||
734 | .name = "adc", | ||
735 | .id = -1, | ||
736 | .parent = &clk_div_d1_bus.clk, | ||
737 | .enable = s5pc100_d1_5_ctrl, | ||
738 | .ctrlbit = (1 << 7), | ||
739 | }, { | ||
740 | .name = "keyif", | ||
741 | .id = -1, | ||
742 | .parent = &clk_div_d1_bus.clk, | ||
743 | .enable = s5pc100_d1_5_ctrl, | ||
744 | .ctrlbit = (1 << 8), | ||
745 | }, { | ||
746 | .name = "spi_48m", | ||
747 | .id = 0, | ||
748 | .parent = &clk_mout_48m.clk, | ||
749 | .enable = s5pc100_sclk0_ctrl, | ||
750 | .ctrlbit = (1 << 7), | ||
751 | }, { | ||
752 | .name = "spi_48m", | ||
753 | .id = 1, | ||
754 | .parent = &clk_mout_48m.clk, | ||
755 | .enable = s5pc100_sclk0_ctrl, | ||
756 | .ctrlbit = (1 << 8), | ||
757 | }, { | ||
758 | .name = "spi_48m", | ||
759 | .id = 2, | ||
760 | .parent = &clk_mout_48m.clk, | ||
761 | .enable = s5pc100_sclk0_ctrl, | ||
762 | .ctrlbit = (1 << 9), | ||
763 | }, { | ||
764 | .name = "mmc_48m", | ||
765 | .id = 0, | ||
766 | .parent = &clk_mout_48m.clk, | ||
767 | .enable = s5pc100_sclk0_ctrl, | ||
768 | .ctrlbit = (1 << 15), | ||
769 | }, { | ||
770 | .name = "mmc_48m", | ||
771 | .id = 1, | ||
772 | .parent = &clk_mout_48m.clk, | ||
773 | .enable = s5pc100_sclk0_ctrl, | ||
774 | .ctrlbit = (1 << 16), | ||
775 | }, { | ||
776 | .name = "mmc_48m", | ||
777 | .id = 2, | ||
778 | .parent = &clk_mout_48m.clk, | ||
779 | .enable = s5pc100_sclk0_ctrl, | ||
780 | .ctrlbit = (1 << 17), | ||
781 | }, | ||
782 | }; | ||
783 | |||
784 | static struct clk clk_vclk54m = { | ||
785 | .name = "vclk_54m", | ||
786 | .id = -1, | ||
787 | .rate = 54000000, | ||
788 | }; | ||
789 | |||
790 | static struct clk clk_i2scdclk0 = { | ||
791 | .name = "i2s_cdclk0", | ||
792 | .id = -1, | ||
793 | }; | ||
794 | |||
795 | static struct clk clk_i2scdclk1 = { | ||
796 | .name = "i2s_cdclk1", | ||
797 | .id = -1, | ||
798 | }; | ||
799 | |||
800 | static struct clk clk_i2scdclk2 = { | ||
801 | .name = "i2s_cdclk2", | ||
802 | .id = -1, | ||
803 | }; | ||
804 | |||
805 | static struct clk clk_pcmcdclk0 = { | ||
806 | .name = "pcm_cdclk0", | ||
807 | .id = -1, | ||
808 | }; | ||
809 | |||
810 | static struct clk clk_pcmcdclk1 = { | ||
811 | .name = "pcm_cdclk1", | ||
812 | .id = -1, | ||
813 | }; | ||
814 | |||
815 | static struct clk *clk_src_group1_list[] = { | ||
816 | [0] = &clk_mout_epll.clk, | ||
817 | [1] = &clk_div_mpll2.clk, | ||
818 | [2] = &clk_fin_epll, | ||
819 | [3] = &clk_mout_hpll.clk, | ||
820 | }; | ||
821 | |||
822 | struct clksrc_sources clk_src_group1 = { | ||
823 | .sources = clk_src_group1_list, | ||
824 | .nr_sources = ARRAY_SIZE(clk_src_group1_list), | ||
825 | }; | ||
826 | |||
827 | static struct clk *clk_src_group2_list[] = { | ||
828 | [0] = &clk_mout_epll.clk, | ||
829 | [1] = &clk_div_mpll.clk, | ||
830 | }; | ||
831 | |||
832 | struct clksrc_sources clk_src_group2 = { | ||
833 | .sources = clk_src_group2_list, | ||
834 | .nr_sources = ARRAY_SIZE(clk_src_group2_list), | ||
835 | }; | ||
836 | |||
837 | static struct clk *clk_src_group3_list[] = { | ||
838 | [0] = &clk_mout_epll.clk, | ||
839 | [1] = &clk_div_mpll.clk, | ||
840 | [2] = &clk_fin_epll, | ||
841 | [3] = &clk_i2scdclk0, | ||
842 | [4] = &clk_pcmcdclk0, | ||
843 | [5] = &clk_mout_hpll.clk, | ||
844 | }; | ||
845 | |||
846 | struct clksrc_sources clk_src_group3 = { | ||
847 | .sources = clk_src_group3_list, | ||
848 | .nr_sources = ARRAY_SIZE(clk_src_group3_list), | ||
849 | }; | ||
850 | |||
851 | static struct clk *clk_src_group4_list[] = { | ||
852 | [0] = &clk_mout_epll.clk, | ||
853 | [1] = &clk_div_mpll.clk, | ||
854 | [2] = &clk_fin_epll, | ||
855 | [3] = &clk_i2scdclk1, | ||
856 | [4] = &clk_pcmcdclk1, | ||
857 | [5] = &clk_mout_hpll.clk, | ||
858 | }; | ||
859 | |||
860 | struct clksrc_sources clk_src_group4 = { | ||
861 | .sources = clk_src_group4_list, | ||
862 | .nr_sources = ARRAY_SIZE(clk_src_group4_list), | ||
863 | }; | ||
864 | |||
865 | static struct clk *clk_src_group5_list[] = { | ||
866 | [0] = &clk_mout_epll.clk, | ||
867 | [1] = &clk_div_mpll.clk, | ||
868 | [2] = &clk_fin_epll, | ||
869 | [3] = &clk_i2scdclk2, | ||
870 | [4] = &clk_mout_hpll.clk, | ||
871 | }; | ||
872 | |||
873 | struct clksrc_sources clk_src_group5 = { | ||
874 | .sources = clk_src_group5_list, | ||
875 | .nr_sources = ARRAY_SIZE(clk_src_group5_list), | ||
876 | }; | ||
877 | |||
878 | static struct clk *clk_src_group6_list[] = { | ||
879 | [0] = &s5p_clk_27m, | ||
880 | [1] = &clk_vclk54m, | ||
881 | [2] = &clk_div_hdmi.clk, | ||
882 | }; | ||
883 | |||
884 | struct clksrc_sources clk_src_group6 = { | ||
885 | .sources = clk_src_group6_list, | ||
886 | .nr_sources = ARRAY_SIZE(clk_src_group6_list), | ||
887 | }; | ||
888 | |||
889 | static struct clk *clk_src_group7_list[] = { | ||
890 | [0] = &clk_mout_epll.clk, | ||
891 | [1] = &clk_div_mpll.clk, | ||
892 | [2] = &clk_mout_hpll.clk, | ||
893 | [3] = &clk_vclk54m, | ||
894 | }; | ||
895 | |||
896 | struct clksrc_sources clk_src_group7 = { | ||
897 | .sources = clk_src_group7_list, | ||
898 | .nr_sources = ARRAY_SIZE(clk_src_group7_list), | ||
899 | }; | ||
900 | |||
901 | static struct clk *clk_src_mmc0_list[] = { | ||
902 | [0] = &clk_mout_epll.clk, | ||
903 | [1] = &clk_div_mpll.clk, | ||
904 | [2] = &clk_fin_epll, | ||
905 | }; | ||
906 | |||
907 | struct clksrc_sources clk_src_mmc0 = { | ||
908 | .sources = clk_src_mmc0_list, | ||
909 | .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), | ||
910 | }; | ||
911 | |||
912 | static struct clk *clk_src_mmc12_list[] = { | ||
913 | [0] = &clk_mout_epll.clk, | ||
914 | [1] = &clk_div_mpll.clk, | ||
915 | [2] = &clk_fin_epll, | ||
916 | [3] = &clk_mout_hpll.clk, | ||
917 | }; | ||
918 | |||
919 | struct clksrc_sources clk_src_mmc12 = { | ||
920 | .sources = clk_src_mmc12_list, | ||
921 | .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), | ||
922 | }; | ||
923 | |||
924 | static struct clk *clk_src_irda_usb_list[] = { | ||
925 | [0] = &clk_mout_epll.clk, | ||
926 | [1] = &clk_div_mpll.clk, | ||
927 | [2] = &clk_fin_epll, | ||
928 | [3] = &clk_mout_hpll.clk, | ||
929 | }; | ||
930 | |||
931 | struct clksrc_sources clk_src_irda_usb = { | ||
932 | .sources = clk_src_irda_usb_list, | ||
933 | .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), | ||
934 | }; | ||
935 | |||
936 | static struct clk *clk_src_pwi_list[] = { | ||
937 | [0] = &clk_fin_epll, | ||
938 | [1] = &clk_mout_epll.clk, | ||
939 | [2] = &clk_div_mpll.clk, | ||
940 | }; | ||
941 | |||
942 | struct clksrc_sources clk_src_pwi = { | ||
943 | .sources = clk_src_pwi_list, | ||
944 | .nr_sources = ARRAY_SIZE(clk_src_pwi_list), | ||
945 | }; | ||
946 | |||
947 | static struct clksrc_clk clksrcs[] = { | ||
948 | { | ||
949 | .clk = { | ||
950 | .name = "sclk_spi", | ||
951 | .id = 0, | ||
952 | .ctrlbit = (1 << 4), | ||
953 | .enable = s5pc100_sclk0_ctrl, | ||
954 | |||
955 | }, | ||
956 | .sources = &clk_src_group1, | ||
957 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, | ||
958 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | ||
959 | }, { | ||
960 | .clk = { | ||
961 | .name = "sclk_spi", | ||
962 | .id = 1, | ||
963 | .ctrlbit = (1 << 5), | ||
964 | .enable = s5pc100_sclk0_ctrl, | ||
965 | |||
966 | }, | ||
967 | .sources = &clk_src_group1, | ||
968 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, | ||
969 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | ||
970 | }, { | ||
971 | .clk = { | ||
972 | .name = "sclk_spi", | ||
973 | .id = 2, | ||
974 | .ctrlbit = (1 << 6), | ||
975 | .enable = s5pc100_sclk0_ctrl, | ||
976 | |||
977 | }, | ||
978 | .sources = &clk_src_group1, | ||
979 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, | ||
980 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, | ||
981 | }, { | ||
982 | .clk = { | ||
983 | .name = "uclk1", | ||
984 | .id = -1, | ||
985 | .ctrlbit = (1 << 3), | ||
986 | .enable = s5pc100_sclk0_ctrl, | ||
987 | |||
988 | }, | ||
989 | .sources = &clk_src_group2, | ||
990 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | ||
991 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | ||
992 | }, { | ||
993 | .clk = { | ||
994 | .name = "sclk_mixer", | ||
995 | .id = -1, | ||
996 | .ctrlbit = (1 << 6), | ||
997 | .enable = s5pc100_sclk0_ctrl, | ||
998 | |||
999 | }, | ||
1000 | .sources = &clk_src_group6, | ||
1001 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, | ||
1002 | }, { | ||
1003 | .clk = { | ||
1004 | .name = "sclk_audio", | ||
1005 | .id = 0, | ||
1006 | .ctrlbit = (1 << 8), | ||
1007 | .enable = s5pc100_sclk1_ctrl, | ||
1008 | |||
1009 | }, | ||
1010 | .sources = &clk_src_group3, | ||
1011 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, | ||
1012 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | ||
1013 | }, { | ||
1014 | .clk = { | ||
1015 | .name = "sclk_audio", | ||
1016 | .id = 1, | ||
1017 | .ctrlbit = (1 << 9), | ||
1018 | .enable = s5pc100_sclk1_ctrl, | ||
1019 | |||
1020 | }, | ||
1021 | .sources = &clk_src_group4, | ||
1022 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, | ||
1023 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | ||
1024 | }, { | ||
1025 | .clk = { | ||
1026 | .name = "sclk_audio", | ||
1027 | .id = 2, | ||
1028 | .ctrlbit = (1 << 10), | ||
1029 | .enable = s5pc100_sclk1_ctrl, | ||
1030 | |||
1031 | }, | ||
1032 | .sources = &clk_src_group5, | ||
1033 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, | ||
1034 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | ||
1035 | }, { | ||
1036 | .clk = { | ||
1037 | .name = "sclk_lcd", | ||
1038 | .id = -1, | ||
1039 | .ctrlbit = (1 << 0), | ||
1040 | .enable = s5pc100_sclk1_ctrl, | ||
1041 | |||
1042 | }, | ||
1043 | .sources = &clk_src_group7, | ||
1044 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 }, | ||
1045 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | ||
1046 | }, { | ||
1047 | .clk = { | ||
1048 | .name = "sclk_fimc", | ||
1049 | .id = 0, | ||
1050 | .ctrlbit = (1 << 1), | ||
1051 | .enable = s5pc100_sclk1_ctrl, | ||
1052 | |||
1053 | }, | ||
1054 | .sources = &clk_src_group7, | ||
1055 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 }, | ||
1056 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | ||
1057 | }, { | ||
1058 | .clk = { | ||
1059 | .name = "sclk_fimc", | ||
1060 | .id = 1, | ||
1061 | .ctrlbit = (1 << 2), | ||
1062 | .enable = s5pc100_sclk1_ctrl, | ||
1063 | |||
1064 | }, | ||
1065 | .sources = &clk_src_group7, | ||
1066 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 }, | ||
1067 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | ||
1068 | }, { | ||
1069 | .clk = { | ||
1070 | .name = "sclk_fimc", | ||
1071 | .id = 2, | ||
1072 | .ctrlbit = (1 << 3), | ||
1073 | .enable = s5pc100_sclk1_ctrl, | ||
1074 | |||
1075 | }, | ||
1076 | .sources = &clk_src_group7, | ||
1077 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 }, | ||
1078 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, | ||
1079 | }, { | ||
1080 | .clk = { | ||
1081 | .name = "mmc_bus", | ||
1082 | .id = 0, | ||
1083 | .ctrlbit = (1 << 12), | ||
1084 | .enable = s5pc100_sclk1_ctrl, | ||
1085 | |||
1086 | }, | ||
1087 | .sources = &clk_src_mmc0, | ||
1088 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | ||
1089 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, | ||
1090 | }, { | ||
1091 | .clk = { | ||
1092 | .name = "mmc_bus", | ||
1093 | .id = 1, | ||
1094 | .ctrlbit = (1 << 13), | ||
1095 | .enable = s5pc100_sclk1_ctrl, | ||
1096 | |||
1097 | }, | ||
1098 | .sources = &clk_src_mmc12, | ||
1099 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | ||
1100 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, | ||
1101 | }, { | ||
1102 | .clk = { | ||
1103 | .name = "mmc_bus", | ||
1104 | .id = 2, | ||
1105 | .ctrlbit = (1 << 14), | ||
1106 | .enable = s5pc100_sclk1_ctrl, | ||
1107 | |||
1108 | }, | ||
1109 | .sources = &clk_src_mmc12, | ||
1110 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | ||
1111 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | ||
1112 | }, { | ||
1113 | .clk = { | ||
1114 | .name = "sclk_irda", | ||
1115 | .id = 2, | ||
1116 | .ctrlbit = (1 << 10), | ||
1117 | .enable = s5pc100_sclk0_ctrl, | ||
1118 | |||
1119 | }, | ||
1120 | .sources = &clk_src_irda_usb, | ||
1121 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | ||
1122 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | ||
1123 | }, { | ||
1124 | .clk = { | ||
1125 | .name = "sclk_irda", | ||
1126 | .id = -1, | ||
1127 | .ctrlbit = (1 << 10), | ||
1128 | .enable = s5pc100_sclk0_ctrl, | ||
1129 | |||
1130 | }, | ||
1131 | .sources = &clk_src_mmc12, | ||
1132 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 }, | ||
1133 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, | ||
1134 | }, { | ||
1135 | .clk = { | ||
1136 | .name = "sclk_pwi", | ||
1137 | .id = -1, | ||
1138 | .ctrlbit = (1 << 1), | ||
1139 | .enable = s5pc100_sclk0_ctrl, | ||
1140 | |||
1141 | }, | ||
1142 | .sources = &clk_src_pwi, | ||
1143 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 }, | ||
1144 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 }, | ||
1145 | }, { | ||
1146 | .clk = { | ||
1147 | .name = "sclk_uhost", | ||
1148 | .id = -1, | ||
1149 | .ctrlbit = (1 << 11), | ||
1150 | .enable = s5pc100_sclk0_ctrl, | ||
1151 | |||
1152 | }, | ||
1153 | .sources = &clk_src_irda_usb, | ||
1154 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 }, | ||
1155 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 }, | ||
1156 | }, | ||
1157 | }; | ||
1158 | |||
1159 | /* Clock initialisation code */ | ||
1160 | static struct clksrc_clk *sysclks[] = { | ||
1161 | &clk_mout_apll, | ||
1162 | &clk_mout_epll, | ||
1163 | &clk_mout_mpll, | ||
1164 | &clk_mout_hpll, | ||
1165 | &clk_mout_href, | ||
1166 | &clk_mout_48m, | ||
1167 | &clk_div_apll, | ||
1168 | &clk_div_arm, | ||
1169 | &clk_div_d0_bus, | ||
1170 | &clk_div_pclkd0, | ||
1171 | &clk_div_secss, | ||
1172 | &clk_div_apll2, | ||
1173 | &clk_mout_am, | ||
1174 | &clk_div_d1_bus, | ||
1175 | &clk_div_mpll2, | ||
1176 | &clk_div_mpll, | ||
1177 | &clk_mout_onenand, | ||
1178 | &clk_div_onenand, | ||
1179 | &clk_div_pclkd1, | ||
1180 | &clk_div_cam, | ||
1181 | &clk_div_hdmi, | ||
1182 | }; | ||
1183 | |||
1184 | void __init_or_cpufreq s5pc100_setup_clocks(void) | ||
1185 | { | ||
1186 | unsigned long xtal; | ||
1187 | unsigned long arm; | ||
1188 | unsigned long hclkd0; | ||
1189 | unsigned long hclkd1; | ||
1190 | unsigned long pclkd0; | ||
1191 | unsigned long pclkd1; | ||
1192 | unsigned long apll; | ||
1193 | unsigned long mpll; | ||
1194 | unsigned long epll; | ||
1195 | unsigned long hpll; | ||
1196 | unsigned int ptr; | ||
1197 | |||
1198 | /* Set S5PC100 functions for clk_fout_epll */ | ||
1199 | clk_fout_epll.enable = s5pc100_epll_enable; | ||
1200 | clk_fout_epll.ops = &s5pc100_epll_ops; | ||
1201 | |||
1202 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
1203 | |||
1204 | xtal = clk_get_rate(&clk_xtal); | ||
1205 | |||
1206 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
1207 | |||
1208 | apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); | ||
1209 | mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON)); | ||
1210 | epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON)); | ||
1211 | hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON)); | ||
1212 | |||
1213 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n", | ||
1214 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); | ||
1215 | |||
1216 | clk_fout_apll.rate = apll; | ||
1217 | clk_fout_mpll.rate = mpll; | ||
1218 | clk_fout_epll.rate = epll; | ||
1219 | clk_mout_hpll.clk.rate = hpll; | ||
1220 | |||
1221 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
1222 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
1223 | |||
1224 | arm = clk_get_rate(&clk_div_arm.clk); | ||
1225 | hclkd0 = clk_get_rate(&clk_div_d0_bus.clk); | ||
1226 | pclkd0 = clk_get_rate(&clk_div_pclkd0.clk); | ||
1227 | hclkd1 = clk_get_rate(&clk_div_d1_bus.clk); | ||
1228 | pclkd1 = clk_get_rate(&clk_div_pclkd1.clk); | ||
1229 | |||
1230 | printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n", | ||
1231 | print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1)); | ||
1232 | |||
1233 | clk_f.rate = arm; | ||
1234 | clk_h.rate = hclkd1; | ||
1235 | clk_p.rate = pclkd1; | ||
1236 | } | ||
1237 | |||
1238 | /* | ||
1239 | * The following clocks will be enabled during clock initialization. | ||
1240 | */ | ||
1241 | static struct clk init_clocks[] = { | ||
1242 | { | ||
1243 | .name = "tzic", | ||
1244 | .id = -1, | ||
1245 | .parent = &clk_div_d0_bus.clk, | ||
1246 | .enable = s5pc100_d0_0_ctrl, | ||
1247 | .ctrlbit = (1 << 1), | ||
1248 | }, { | ||
1249 | .name = "intc", | ||
1250 | .id = -1, | ||
1251 | .parent = &clk_div_d0_bus.clk, | ||
1252 | .enable = s5pc100_d0_0_ctrl, | ||
1253 | .ctrlbit = (1 << 0), | ||
1254 | }, { | ||
1255 | .name = "ebi", | ||
1256 | .id = -1, | ||
1257 | .parent = &clk_div_d0_bus.clk, | ||
1258 | .enable = s5pc100_d0_1_ctrl, | ||
1259 | .ctrlbit = (1 << 5), | ||
1260 | }, { | ||
1261 | .name = "intmem", | ||
1262 | .id = -1, | ||
1263 | .parent = &clk_div_d0_bus.clk, | ||
1264 | .enable = s5pc100_d0_1_ctrl, | ||
1265 | .ctrlbit = (1 << 4), | ||
1266 | }, { | ||
1267 | .name = "sromc", | ||
1268 | .id = -1, | ||
1269 | .parent = &clk_div_d0_bus.clk, | ||
1270 | .enable = s5pc100_d0_1_ctrl, | ||
1271 | .ctrlbit = (1 << 1), | ||
1272 | }, { | ||
1273 | .name = "dmc", | ||
1274 | .id = -1, | ||
1275 | .parent = &clk_div_d0_bus.clk, | ||
1276 | .enable = s5pc100_d0_1_ctrl, | ||
1277 | .ctrlbit = (1 << 0), | ||
1278 | }, { | ||
1279 | .name = "chipid", | ||
1280 | .id = -1, | ||
1281 | .parent = &clk_div_d0_bus.clk, | ||
1282 | .enable = s5pc100_d0_1_ctrl, | ||
1283 | .ctrlbit = (1 << 0), | ||
1284 | }, { | ||
1285 | .name = "gpio", | ||
1286 | .id = -1, | ||
1287 | .parent = &clk_div_d1_bus.clk, | ||
1288 | .enable = s5pc100_d1_3_ctrl, | ||
1289 | .ctrlbit = (1 << 1), | ||
1290 | }, { | ||
1291 | .name = "uart", | ||
1292 | .id = 0, | ||
1293 | .parent = &clk_div_d1_bus.clk, | ||
1294 | .enable = s5pc100_d1_4_ctrl, | ||
1295 | .ctrlbit = (1 << 0), | ||
1296 | }, { | ||
1297 | .name = "uart", | ||
1298 | .id = 1, | ||
1299 | .parent = &clk_div_d1_bus.clk, | ||
1300 | .enable = s5pc100_d1_4_ctrl, | ||
1301 | .ctrlbit = (1 << 1), | ||
1302 | }, { | ||
1303 | .name = "uart", | ||
1304 | .id = 2, | ||
1305 | .parent = &clk_div_d1_bus.clk, | ||
1306 | .enable = s5pc100_d1_4_ctrl, | ||
1307 | .ctrlbit = (1 << 2), | ||
1308 | }, { | ||
1309 | .name = "uart", | ||
1310 | .id = 3, | ||
1311 | .parent = &clk_div_d1_bus.clk, | ||
1312 | .enable = s5pc100_d1_4_ctrl, | ||
1313 | .ctrlbit = (1 << 3), | ||
1314 | }, { | ||
1315 | .name = "timers", | ||
1316 | .id = -1, | ||
1317 | .parent = &clk_div_d1_bus.clk, | ||
1318 | .enable = s5pc100_d1_3_ctrl, | ||
1319 | .ctrlbit = (1 << 6), | ||
1320 | }, | ||
1321 | }; | ||
1322 | |||
1323 | static struct clk *clks[] __initdata = { | ||
1324 | &clk_ext, | ||
1325 | &clk_i2scdclk0, | ||
1326 | &clk_i2scdclk1, | ||
1327 | &clk_i2scdclk2, | ||
1328 | &clk_pcmcdclk0, | ||
1329 | &clk_pcmcdclk1, | ||
1330 | }; | ||
1331 | |||
1332 | void __init s5pc100_register_clocks(void) | ||
1333 | { | ||
1334 | struct clk *clkp; | ||
1335 | int ret; | ||
1336 | int ptr; | ||
1337 | |||
1338 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
1339 | |||
1340 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
1341 | s3c_register_clksrc(sysclks[ptr], 1); | ||
1342 | |||
1343 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
1344 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
1345 | |||
1346 | clkp = init_clocks_disable; | ||
1347 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | ||
1348 | |||
1349 | ret = s3c24xx_register_clock(clkp); | ||
1350 | if (ret < 0) { | ||
1351 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
1352 | clkp->name, ret); | ||
1353 | } | ||
1354 | (clkp->enable)(clkp, 0); | ||
1355 | } | ||
1356 | |||
1357 | s3c_pwmclk_init(); | ||
1358 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index 1ffc57ac293d..c8e8336a3a12 100644 --- a/arch/arm/plat-s5pc1xx/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c | |||
@@ -17,11 +17,11 @@ | |||
17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
18 | 18 | ||
19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
20 | #include <mach/regs-gpio.h> | ||
20 | 21 | ||
21 | #include <plat/gpio-core.h> | 22 | #include <plat/gpio-core.h> |
22 | #include <plat/gpio-cfg.h> | 23 | #include <plat/gpio-cfg.h> |
23 | #include <plat/gpio-cfg-helpers.h> | 24 | #include <plat/gpio-cfg-helpers.h> |
24 | #include <plat/regs-gpio.h> | ||
25 | 25 | ||
26 | /* S5PC100 GPIO bank summary: | 26 | /* S5PC100 GPIO bank summary: |
27 | * | 27 | * |
@@ -61,74 +61,7 @@ | |||
61 | * L3 8 4Bit None | 61 | * L3 8 4Bit None |
62 | */ | 62 | */ |
63 | 63 | ||
64 | #define OFF_GPCON (0x00) | 64 | #if 0 |
65 | #define OFF_GPDAT (0x04) | ||
66 | |||
67 | #define con_4bit_shift(__off) ((__off) * 4) | ||
68 | |||
69 | #if 1 | ||
70 | #define gpio_dbg(x...) do { } while (0) | ||
71 | #else | ||
72 | #define gpio_dbg(x...) printk(KERN_DEBUG x) | ||
73 | #endif | ||
74 | |||
75 | /* The s5pc1xx_gpiolib routines are to control the gpio banks where | ||
76 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
77 | * following example: | ||
78 | * | ||
79 | * base + 0x00: Control register, 4 bits per gpio | ||
80 | * gpio n: 4 bits starting at (4*n) | ||
81 | * 0000 = input, 0001 = output, others mean special-function | ||
82 | * base + 0x04: Data register, 1 bit per gpio | ||
83 | * bit n: data bit n | ||
84 | * | ||
85 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
86 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
87 | * the output. | ||
88 | */ | ||
89 | |||
90 | static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) | ||
91 | { | ||
92 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
93 | void __iomem *base = ourchip->base; | ||
94 | unsigned long con; | ||
95 | |||
96 | con = __raw_readl(base + OFF_GPCON); | ||
97 | con &= ~(0xf << con_4bit_shift(offset)); | ||
98 | __raw_writel(con, base + OFF_GPCON); | ||
99 | |||
100 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
101 | |||
102 | return 0; | ||
103 | } | ||
104 | |||
105 | static int s5pc1xx_gpiolib_output(struct gpio_chip *chip, | ||
106 | unsigned offset, int value) | ||
107 | { | ||
108 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
109 | void __iomem *base = ourchip->base; | ||
110 | unsigned long con; | ||
111 | unsigned long dat; | ||
112 | |||
113 | con = __raw_readl(base + OFF_GPCON); | ||
114 | con &= ~(0xf << con_4bit_shift(offset)); | ||
115 | con |= 0x1 << con_4bit_shift(offset); | ||
116 | |||
117 | dat = __raw_readl(base + OFF_GPDAT); | ||
118 | if (value) | ||
119 | dat |= 1 << offset; | ||
120 | else | ||
121 | dat &= ~(1 << offset); | ||
122 | |||
123 | __raw_writel(dat, base + OFF_GPDAT); | ||
124 | __raw_writel(con, base + OFF_GPCON); | ||
125 | __raw_writel(dat, base + OFF_GPDAT); | ||
126 | |||
127 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
128 | |||
129 | return 0; | ||
130 | } | ||
131 | |||
132 | static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | 65 | static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) |
133 | { | 66 | { |
134 | return S3C_IRQ_GPIO(chip->base + offset); | 67 | return S3C_IRQ_GPIO(chip->base + offset); |
@@ -152,7 +85,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) | |||
152 | return IRQ_EINT(24 + offset); | 85 | return IRQ_EINT(24 + offset); |
153 | return -EINVAL; | 86 | return -EINVAL; |
154 | } | 87 | } |
155 | 88 | #endif | |
156 | static struct s3c_gpio_cfg gpio_cfg = { | 89 | static struct s3c_gpio_cfg gpio_cfg = { |
157 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | 90 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, |
158 | .set_pull = s3c_gpio_setpull_updown, | 91 | .set_pull = s3c_gpio_setpull_updown, |
@@ -452,12 +385,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
452 | extern struct irq_chip s5pc1xx_gpioint; | 385 | extern struct irq_chip s5pc1xx_gpioint; |
453 | extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); | 386 | extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); |
454 | 387 | ||
455 | static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) | 388 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) |
456 | { | 389 | { |
457 | chip->chip.direction_input = s5pc1xx_gpiolib_input; | 390 | #if 0 |
458 | chip->chip.direction_output = s5pc1xx_gpiolib_output; | ||
459 | chip->pm = __gpio_pm(&s3c_gpio_pm_4bit); | ||
460 | |||
461 | /* Interrupt */ | 391 | /* Interrupt */ |
462 | if (chip->config == &gpio_cfg) { | 392 | if (chip->config == &gpio_cfg) { |
463 | int i, irq; | 393 | int i, irq; |
@@ -473,31 +403,26 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) | |||
473 | } | 403 | } |
474 | } else if (chip->config == &gpio_cfg_eint) | 404 | } else if (chip->config == &gpio_cfg_eint) |
475 | chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; | 405 | chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; |
476 | } | 406 | #endif |
477 | |||
478 | static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips, | ||
479 | int nr_chips, | ||
480 | void (*fn)(struct s3c_gpio_chip *)) | ||
481 | { | ||
482 | for (; nr_chips > 0; nr_chips--, chips++) { | ||
483 | if (fn) | ||
484 | (fn)(chips); | ||
485 | s3c_gpiolib_add(chips); | ||
486 | } | ||
487 | } | 407 | } |
488 | 408 | ||
489 | static __init int s5pc1xx_gpiolib_init(void) | 409 | static __init int s5pc1xx_gpiolib_init(void) |
490 | { | 410 | { |
491 | struct s3c_gpio_chip *chips; | 411 | struct s3c_gpio_chip *chip; |
492 | int nr_chips; | 412 | int nr_chips; |
493 | 413 | ||
494 | chips = s5pc100_gpio_chips; | 414 | chip = s5pc100_gpio_chips; |
495 | nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); | 415 | nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); |
416 | |||
417 | for (; nr_chips > 0; nr_chips--, chip++) | ||
418 | s5pc100_gpiolib_link(chip); | ||
496 | 419 | ||
497 | s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link); | 420 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, |
421 | ARRAY_SIZE(s5pc100_gpio_chips)); | ||
422 | #if 0 | ||
498 | /* Interrupt */ | 423 | /* Interrupt */ |
499 | set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); | 424 | set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); |
500 | 425 | #endif | |
501 | return 0; | 426 | return 0; |
502 | } | 427 | } |
503 | core_initcall(s5pc1xx_gpiolib_init); | 428 | core_initcall(s5pc1xx_gpiolib_init); |
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 2c4cbe8ee6b7..29a8a12d9b4f 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h | |||
@@ -12,6 +12,9 @@ | |||
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #ifndef __ASM_ARCH_GPIO_H | ||
16 | #define __ASM_ARCH_GPIO_H __FILE__ | ||
17 | |||
15 | #define gpio_get_value __gpio_get_value | 18 | #define gpio_get_value __gpio_get_value |
16 | #define gpio_set_value __gpio_set_value | 19 | #define gpio_set_value __gpio_set_value |
17 | #define gpio_cansleep __gpio_cansleep | 20 | #define gpio_cansleep __gpio_cansleep |
@@ -52,11 +55,6 @@ | |||
52 | #define S5PC100_GPIO_L2_NR (8) | 55 | #define S5PC100_GPIO_L2_NR (8) |
53 | #define S5PC100_GPIO_L3_NR (8) | 56 | #define S5PC100_GPIO_L3_NR (8) |
54 | #define S5PC100_GPIO_L4_NR (8) | 57 | #define S5PC100_GPIO_L4_NR (8) |
55 | #define S5PC100_GPIO_MP00_NR (8) | ||
56 | #define S5PC100_GPIO_MP01_NR (8) | ||
57 | #define S5PC100_GPIO_MP02_NR (8) | ||
58 | #define S5PC100_GPIO_MP03_NR (8) | ||
59 | #define S5PC100_GPIO_MP04_NR (5) | ||
60 | 58 | ||
61 | /* GPIO bank numbes */ | 59 | /* GPIO bank numbes */ |
62 | 60 | ||
@@ -65,50 +63,45 @@ | |||
65 | * change from one gpio bank to another can be caught. | 63 | * change from one gpio bank to another can be caught. |
66 | */ | 64 | */ |
67 | 65 | ||
68 | #define S5PC1XX_GPIO_NEXT(__gpio) \ | 66 | #define S5PC100_GPIO_NEXT(__gpio) \ |
69 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | 67 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) |
70 | 68 | ||
71 | enum s3c_gpio_number { | 69 | enum s5p_gpio_number { |
72 | S5PC100_GPIO_A0_START = 0, | 70 | S5PC100_GPIO_A0_START = 0, |
73 | S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0), | 71 | S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0), |
74 | S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1), | 72 | S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1), |
75 | S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B), | 73 | S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B), |
76 | S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C), | 74 | S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C), |
77 | S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D), | 75 | S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D), |
78 | S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0), | 76 | S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0), |
79 | S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1), | 77 | S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1), |
80 | S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0), | 78 | S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0), |
81 | S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1), | 79 | S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1), |
82 | S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2), | 80 | S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2), |
83 | S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3), | 81 | S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3), |
84 | S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0), | 82 | S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0), |
85 | S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1), | 83 | S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1), |
86 | S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2), | 84 | S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2), |
87 | S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3), | 85 | S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3), |
88 | S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0), | 86 | S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0), |
89 | S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1), | 87 | S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1), |
90 | S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2), | 88 | S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2), |
91 | S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3), | 89 | S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3), |
92 | S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I), | 90 | S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I), |
93 | S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0), | 91 | S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0), |
94 | S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1), | 92 | S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1), |
95 | S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2), | 93 | S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2), |
96 | S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3), | 94 | S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3), |
97 | S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4), | 95 | S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4), |
98 | S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0), | 96 | S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0), |
99 | S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1), | 97 | S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1), |
100 | S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2), | 98 | S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2), |
101 | S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3), | 99 | S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3), |
102 | S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0), | 100 | S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0), |
103 | S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1), | 101 | S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1), |
104 | S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2), | 102 | S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2), |
105 | S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3), | 103 | S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3), |
106 | S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4), | 104 | S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4), |
107 | S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00), | ||
108 | S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01), | ||
109 | S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02), | ||
110 | S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03), | ||
111 | S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04), | ||
112 | }; | 105 | }; |
113 | 106 | ||
114 | /* S5PC100 GPIO number definitions. */ | 107 | /* S5PC100 GPIO number definitions. */ |
@@ -146,17 +139,13 @@ enum s3c_gpio_number { | |||
146 | #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) | 139 | #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) |
147 | #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) | 140 | #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) |
148 | #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) | 141 | #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) |
149 | #define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr)) | ||
150 | #define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr)) | ||
151 | #define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr)) | ||
152 | #define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr)) | ||
153 | #define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr)) | ||
154 | #define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr)) | ||
155 | 142 | ||
156 | /* It used the end of the S5PC1XX gpios */ | 143 | /* It used the end of the S5PC100 gpios */ |
157 | #define S3C_GPIO_END S5PC100_GPIO_END | 144 | #define S3C_GPIO_END S5PC100_GPIO_END |
158 | 145 | ||
159 | /* define the number of gpios we need to the one after the MP04() range */ | 146 | /* define the number of gpios we need to the one after the MP04() range */ |
160 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) | 147 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) |
161 | 148 | ||
162 | #include <asm-generic/gpio.h> | 149 | #include <asm-generic/gpio.h> |
150 | |||
151 | #endif /* __ASM_ARCH_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h new file mode 100644 index 000000000000..f2283bdc941e --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h | |||
@@ -0,0 +1,71 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PC100 - Clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | ||
21 | #define S5P_MPLL_LOCK S5P_CLKREG(0x04) | ||
22 | #define S5P_EPLL_LOCK S5P_CLKREG(0x08) | ||
23 | #define S5P_HPLL_LOCK S5P_CLKREG(0x0C) | ||
24 | |||
25 | #define S5P_APLL_CON S5P_CLKREG(0x100) | ||
26 | #define S5P_MPLL_CON S5P_CLKREG(0x104) | ||
27 | #define S5P_EPLL_CON S5P_CLKREG(0x108) | ||
28 | #define S5P_HPLL_CON S5P_CLKREG(0x10C) | ||
29 | |||
30 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | ||
31 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) | ||
32 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | ||
33 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) | ||
34 | |||
35 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | ||
36 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) | ||
37 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | ||
38 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) | ||
39 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) | ||
40 | |||
41 | #define S5P_CLK_OUT S5P_CLKREG(0x400) | ||
42 | |||
43 | #define S5P_CLKGATE_D00 S5P_CLKREG(0x500) | ||
44 | #define S5P_CLKGATE_D01 S5P_CLKREG(0x504) | ||
45 | #define S5P_CLKGATE_D02 S5P_CLKREG(0x508) | ||
46 | |||
47 | #define S5P_CLKGATE_D10 S5P_CLKREG(0x520) | ||
48 | #define S5P_CLKGATE_D11 S5P_CLKREG(0x524) | ||
49 | #define S5P_CLKGATE_D12 S5P_CLKREG(0x528) | ||
50 | #define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) | ||
51 | #define S5P_CLKGATE_D14 S5P_CLKREG(0x530) | ||
52 | #define S5P_CLKGATE_D15 S5P_CLKREG(0x534) | ||
53 | |||
54 | #define S5P_CLKGATE_D20 S5P_CLKREG(0x540) | ||
55 | |||
56 | #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560) | ||
57 | #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564) | ||
58 | |||
59 | /* CLKDIV0 */ | ||
60 | #define S5P_CLKDIV0_D0_MASK (0x7<<8) | ||
61 | #define S5P_CLKDIV0_D0_SHIFT (8) | ||
62 | #define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) | ||
63 | #define S5P_CLKDIV0_PCLKD0_SHIFT (12) | ||
64 | |||
65 | /* CLKDIV1 */ | ||
66 | #define S5P_CLKDIV1_D1_MASK (0x7<<12) | ||
67 | #define S5P_CLKDIV1_D1_SHIFT (12) | ||
68 | #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) | ||
69 | #define S5P_CLKDIV1_PCLKD1_SHIFT (16) | ||
70 | |||
71 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h index 43c7bc8bf784..68666913354c 100644 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h | |||
@@ -3,11 +3,11 @@ | |||
3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
5 | * | 5 | * |
6 | * S5PC1XX - GPIO register definitions | 6 | * S5PC100 - GPIO register definitions |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H | 9 | #ifndef __ASM_MACH_S5PC100_REGS_GPIO_H |
10 | #define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ | 10 | #define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__ |
11 | 11 | ||
12 | #include <mach/map.h> | 12 | #include <mach/map.h> |
13 | 13 | ||
@@ -66,5 +66,5 @@ | |||
66 | #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | 66 | #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) |
67 | #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | 67 | #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) |
68 | 68 | ||
69 | #endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ | 69 | #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ |
70 | 70 | ||
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index ae3c52cd0ebb..bfe67db34f04 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
@@ -35,7 +35,6 @@ | |||
35 | 35 | ||
36 | #include <plat/regs-serial.h> | 36 | #include <plat/regs-serial.h> |
37 | #include <plat/gpio-cfg.h> | 37 | #include <plat/gpio-cfg.h> |
38 | #include <plat/regs-gpio.h> | ||
39 | 38 | ||
40 | #include <plat/clock.h> | 39 | #include <plat/clock.h> |
41 | #include <plat/devs.h> | 40 | #include <plat/devs.h> |
diff --git a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c index 1a63768a9a2e..6eba6cb8e2f4 100644 --- a/arch/arm/plat-s5pc1xx/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c | |||
@@ -1,9 +1,9 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c | 2 | * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c |
3 | * | 3 | * |
4 | * Copyright 2009 Samsung Electronics | 4 | * Copyright 2009 Samsung Electronics |
5 | * | 5 | * |
6 | * Base S5PC1XX setup information for 24bpp LCD framebuffer | 6 | * Base S5PC100 setup information for 24bpp LCD framebuffer |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
@@ -19,7 +19,6 @@ | |||
19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
20 | #include <plat/fb.h> | 20 | #include <plat/fb.h> |
21 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
22 | #include <plat/gpio-cfg-s5pc1xx.h> | ||
23 | 22 | ||
24 | #define DISR_OFFSET 0x7008 | 23 | #define DISR_OFFSET 0x7008 |
25 | 24 | ||
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c index 5e4a7c3a231e..dd3174e6ecc5 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c0.c +++ b/arch/arm/mach-s5pc100/setup-i2c0.c | |||
@@ -1,9 +1,9 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c | 1 | /* linux/arch/arm/mach-s5pc100/setup-i2c0.c |
2 | * | 2 | * |
3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
5 | * | 5 | * |
6 | * Base S5PC1XX I2C bus 0 gpio configuration | 6 | * Base S5PC100 I2C bus 0 gpio configuration |
7 | * | 7 | * |
8 | * Based on plat-s3c64xx/setup-i2c0.c | 8 | * Based on plat-s3c64xx/setup-i2c0.c |
9 | * | 9 | * |
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c index a0a8b4ae6ad8..d1fec26b69ee 100644 --- a/arch/arm/plat-s5pc1xx/setup-i2c1.c +++ b/arch/arm/mach-s5pc100/setup-i2c1.c | |||
@@ -1,9 +1,9 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/setup-i2c1.c | 1 | /* linux/arch/arm/mach-s5pc100/setup-i2c1.c |
2 | * | 2 | * |
3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
5 | * | 5 | * |
6 | * Base S5PC1XX I2C bus 1 gpio configuration | 6 | * Base S5PC100 I2C bus 1 gpio configuration |
7 | * | 7 | * |
8 | * Based on plat-s3c64xx/setup-i2c1.c | 8 | * Based on plat-s3c64xx/setup-i2c1.c |
9 | * | 9 | * |
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index af33a1a89b72..7601c28e240b 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig | |||
@@ -12,6 +12,7 @@ if ARCH_S5PV210 | |||
12 | config CPU_S5PV210 | 12 | config CPU_S5PV210 |
13 | bool | 13 | bool |
14 | select PLAT_S5P | 14 | select PLAT_S5P |
15 | select S3C_PL330_DMA | ||
15 | help | 16 | help |
16 | Enable S5PV210 CPU support | 17 | Enable S5PV210 CPU support |
17 | 18 | ||
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 8ebf51c52a01..99827813d293 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile | |||
@@ -12,9 +12,14 @@ obj- := | |||
12 | 12 | ||
13 | # Core support for S5PV210 system | 13 | # Core support for S5PV210 system |
14 | 14 | ||
15 | obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o | 15 | obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o |
16 | obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o | ||
16 | 17 | ||
17 | # machine support | 18 | # machine support |
18 | 19 | ||
19 | obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o | 20 | obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o |
20 | obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o | 21 | obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o |
22 | |||
23 | # device support | ||
24 | |||
25 | obj-y += dev-audio.o | ||
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index ccccae262351..154bca4abc09 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -31,6 +31,128 @@ | |||
31 | #include <plat/clock-clksrc.h> | 31 | #include <plat/clock-clksrc.h> |
32 | #include <plat/s5pv210.h> | 32 | #include <plat/s5pv210.h> |
33 | 33 | ||
34 | static struct clksrc_clk clk_mout_apll = { | ||
35 | .clk = { | ||
36 | .name = "mout_apll", | ||
37 | .id = -1, | ||
38 | }, | ||
39 | .sources = &clk_src_apll, | ||
40 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
41 | }; | ||
42 | |||
43 | static struct clksrc_clk clk_mout_epll = { | ||
44 | .clk = { | ||
45 | .name = "mout_epll", | ||
46 | .id = -1, | ||
47 | }, | ||
48 | .sources = &clk_src_epll, | ||
49 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | ||
50 | }; | ||
51 | |||
52 | static struct clksrc_clk clk_mout_mpll = { | ||
53 | .clk = { | ||
54 | .name = "mout_mpll", | ||
55 | .id = -1, | ||
56 | }, | ||
57 | .sources = &clk_src_mpll, | ||
58 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | ||
59 | }; | ||
60 | |||
61 | static struct clk *clkset_armclk_list[] = { | ||
62 | [0] = &clk_mout_apll.clk, | ||
63 | [1] = &clk_mout_mpll.clk, | ||
64 | }; | ||
65 | |||
66 | static struct clksrc_sources clkset_armclk = { | ||
67 | .sources = clkset_armclk_list, | ||
68 | .nr_sources = ARRAY_SIZE(clkset_armclk_list), | ||
69 | }; | ||
70 | |||
71 | static struct clksrc_clk clk_armclk = { | ||
72 | .clk = { | ||
73 | .name = "armclk", | ||
74 | .id = -1, | ||
75 | }, | ||
76 | .sources = &clkset_armclk, | ||
77 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | ||
78 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, | ||
79 | }; | ||
80 | |||
81 | static struct clksrc_clk clk_hclk_msys = { | ||
82 | .clk = { | ||
83 | .name = "hclk_msys", | ||
84 | .id = -1, | ||
85 | .parent = &clk_armclk.clk, | ||
86 | }, | ||
87 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | ||
88 | }; | ||
89 | |||
90 | static struct clksrc_clk clk_pclk_msys = { | ||
91 | .clk = { | ||
92 | .name = "pclk_msys", | ||
93 | .id = -1, | ||
94 | .parent = &clk_hclk_msys.clk, | ||
95 | }, | ||
96 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | ||
97 | }; | ||
98 | |||
99 | static struct clksrc_clk clk_sclk_a2m = { | ||
100 | .clk = { | ||
101 | .name = "sclk_a2m", | ||
102 | .id = -1, | ||
103 | .parent = &clk_mout_apll.clk, | ||
104 | }, | ||
105 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | ||
106 | }; | ||
107 | |||
108 | static struct clk *clkset_hclk_sys_list[] = { | ||
109 | [0] = &clk_mout_mpll.clk, | ||
110 | [1] = &clk_sclk_a2m.clk, | ||
111 | }; | ||
112 | |||
113 | static struct clksrc_sources clkset_hclk_sys = { | ||
114 | .sources = clkset_hclk_sys_list, | ||
115 | .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list), | ||
116 | }; | ||
117 | |||
118 | static struct clksrc_clk clk_hclk_dsys = { | ||
119 | .clk = { | ||
120 | .name = "hclk_dsys", | ||
121 | .id = -1, | ||
122 | }, | ||
123 | .sources = &clkset_hclk_sys, | ||
124 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | ||
125 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, | ||
126 | }; | ||
127 | |||
128 | static struct clksrc_clk clk_pclk_dsys = { | ||
129 | .clk = { | ||
130 | .name = "pclk_dsys", | ||
131 | .id = -1, | ||
132 | .parent = &clk_hclk_dsys.clk, | ||
133 | }, | ||
134 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, | ||
135 | }; | ||
136 | |||
137 | static struct clksrc_clk clk_hclk_psys = { | ||
138 | .clk = { | ||
139 | .name = "hclk_psys", | ||
140 | .id = -1, | ||
141 | }, | ||
142 | .sources = &clkset_hclk_sys, | ||
143 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | ||
144 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, | ||
145 | }; | ||
146 | |||
147 | static struct clksrc_clk clk_pclk_psys = { | ||
148 | .clk = { | ||
149 | .name = "pclk_psys", | ||
150 | .id = -1, | ||
151 | .parent = &clk_hclk_psys.clk, | ||
152 | }, | ||
153 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, | ||
154 | }; | ||
155 | |||
34 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) | 156 | static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) |
35 | { | 157 | { |
36 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); | 158 | return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); |
@@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable) | |||
51 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); | 173 | return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); |
52 | } | 174 | } |
53 | 175 | ||
54 | static struct clk clk_h200 = { | 176 | static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable) |
55 | .name = "hclk200", | 177 | { |
178 | return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable); | ||
179 | } | ||
180 | |||
181 | static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) | ||
182 | { | ||
183 | return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); | ||
184 | } | ||
185 | |||
186 | static struct clk clk_sclk_hdmi27m = { | ||
187 | .name = "sclk_hdmi27m", | ||
56 | .id = -1, | 188 | .id = -1, |
189 | .rate = 27000000, | ||
57 | }; | 190 | }; |
58 | 191 | ||
59 | static struct clk clk_h100 = { | 192 | static struct clk clk_sclk_hdmiphy = { |
60 | .name = "hclk100", | 193 | .name = "sclk_hdmiphy", |
61 | .id = -1, | 194 | .id = -1, |
62 | }; | 195 | }; |
63 | 196 | ||
64 | static struct clk clk_h166 = { | 197 | static struct clk clk_sclk_usbphy0 = { |
65 | .name = "hclk166", | 198 | .name = "sclk_usbphy0", |
66 | .id = -1, | 199 | .id = -1, |
67 | }; | 200 | }; |
68 | 201 | ||
69 | static struct clk clk_h133 = { | 202 | static struct clk clk_sclk_usbphy1 = { |
70 | .name = "hclk133", | 203 | .name = "sclk_usbphy1", |
71 | .id = -1, | 204 | .id = -1, |
72 | }; | 205 | }; |
73 | 206 | ||
74 | static struct clk clk_p100 = { | 207 | static struct clk clk_pcmcdclk0 = { |
75 | .name = "pclk100", | 208 | .name = "pcmcdclk", |
76 | .id = -1, | 209 | .id = -1, |
77 | }; | 210 | }; |
78 | 211 | ||
79 | static struct clk clk_p83 = { | 212 | static struct clk clk_pcmcdclk1 = { |
80 | .name = "pclk83", | 213 | .name = "pcmcdclk", |
81 | .id = -1, | 214 | .id = -1, |
82 | }; | 215 | }; |
83 | 216 | ||
84 | static struct clk clk_p66 = { | 217 | static struct clk clk_pcmcdclk2 = { |
85 | .name = "pclk66", | 218 | .name = "pcmcdclk", |
86 | .id = -1, | 219 | .id = -1, |
87 | }; | 220 | }; |
88 | 221 | ||
89 | static struct clk *sys_clks[] = { | 222 | static struct clk *clkset_vpllsrc_list[] = { |
90 | &clk_h200, | 223 | [0] = &clk_fin_vpll, |
91 | &clk_h100, | 224 | [1] = &clk_sclk_hdmi27m, |
92 | &clk_h166, | 225 | }; |
93 | &clk_h133, | 226 | |
94 | &clk_p100, | 227 | static struct clksrc_sources clkset_vpllsrc = { |
95 | &clk_p83, | 228 | .sources = clkset_vpllsrc_list, |
96 | &clk_p66 | 229 | .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list), |
230 | }; | ||
231 | |||
232 | static struct clksrc_clk clk_vpllsrc = { | ||
233 | .clk = { | ||
234 | .name = "vpll_src", | ||
235 | .id = -1, | ||
236 | .enable = s5pv210_clk_mask0_ctrl, | ||
237 | .ctrlbit = (1 << 7), | ||
238 | }, | ||
239 | .sources = &clkset_vpllsrc, | ||
240 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 }, | ||
241 | }; | ||
242 | |||
243 | static struct clk *clkset_sclk_vpll_list[] = { | ||
244 | [0] = &clk_vpllsrc.clk, | ||
245 | [1] = &clk_fout_vpll, | ||
246 | }; | ||
247 | |||
248 | static struct clksrc_sources clkset_sclk_vpll = { | ||
249 | .sources = clkset_sclk_vpll_list, | ||
250 | .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), | ||
251 | }; | ||
252 | |||
253 | static struct clksrc_clk clk_sclk_vpll = { | ||
254 | .clk = { | ||
255 | .name = "sclk_vpll", | ||
256 | .id = -1, | ||
257 | }, | ||
258 | .sources = &clkset_sclk_vpll, | ||
259 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | ||
260 | }; | ||
261 | |||
262 | static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk) | ||
263 | { | ||
264 | return clk_get_rate(clk->parent) / 2; | ||
265 | } | ||
266 | |||
267 | static struct clk_ops clk_hclk_imem_ops = { | ||
268 | .get_rate = s5pv210_clk_imem_get_rate, | ||
97 | }; | 269 | }; |
98 | 270 | ||
99 | static struct clk init_clocks_disable[] = { | 271 | static struct clk init_clocks_disable[] = { |
100 | { | 272 | { |
101 | .name = "rot", | 273 | .name = "rot", |
102 | .id = -1, | 274 | .id = -1, |
103 | .parent = &clk_h166, | 275 | .parent = &clk_hclk_dsys.clk, |
104 | .enable = s5pv210_clk_ip0_ctrl, | 276 | .enable = s5pv210_clk_ip0_ctrl, |
105 | .ctrlbit = (1<<29), | 277 | .ctrlbit = (1<<29), |
106 | }, { | 278 | }, { |
107 | .name = "otg", | 279 | .name = "otg", |
108 | .id = -1, | 280 | .id = -1, |
109 | .parent = &clk_h133, | 281 | .parent = &clk_hclk_psys.clk, |
110 | .enable = s5pv210_clk_ip1_ctrl, | 282 | .enable = s5pv210_clk_ip1_ctrl, |
111 | .ctrlbit = (1<<16), | 283 | .ctrlbit = (1<<16), |
112 | }, { | 284 | }, { |
113 | .name = "usb-host", | 285 | .name = "usb-host", |
114 | .id = -1, | 286 | .id = -1, |
115 | .parent = &clk_h133, | 287 | .parent = &clk_hclk_psys.clk, |
116 | .enable = s5pv210_clk_ip1_ctrl, | 288 | .enable = s5pv210_clk_ip1_ctrl, |
117 | .ctrlbit = (1<<17), | 289 | .ctrlbit = (1<<17), |
118 | }, { | 290 | }, { |
119 | .name = "lcd", | 291 | .name = "lcd", |
120 | .id = -1, | 292 | .id = -1, |
121 | .parent = &clk_h166, | 293 | .parent = &clk_hclk_dsys.clk, |
122 | .enable = s5pv210_clk_ip1_ctrl, | 294 | .enable = s5pv210_clk_ip1_ctrl, |
123 | .ctrlbit = (1<<0), | 295 | .ctrlbit = (1<<0), |
124 | }, { | 296 | }, { |
125 | .name = "cfcon", | 297 | .name = "cfcon", |
126 | .id = 0, | 298 | .id = 0, |
127 | .parent = &clk_h133, | 299 | .parent = &clk_hclk_psys.clk, |
128 | .enable = s5pv210_clk_ip1_ctrl, | 300 | .enable = s5pv210_clk_ip1_ctrl, |
129 | .ctrlbit = (1<<25), | 301 | .ctrlbit = (1<<25), |
130 | }, { | 302 | }, { |
131 | .name = "hsmmc", | 303 | .name = "hsmmc", |
132 | .id = 0, | 304 | .id = 0, |
133 | .parent = &clk_h133, | 305 | .parent = &clk_hclk_psys.clk, |
134 | .enable = s5pv210_clk_ip2_ctrl, | 306 | .enable = s5pv210_clk_ip2_ctrl, |
135 | .ctrlbit = (1<<16), | 307 | .ctrlbit = (1<<16), |
136 | }, { | 308 | }, { |
137 | .name = "hsmmc", | 309 | .name = "hsmmc", |
138 | .id = 1, | 310 | .id = 1, |
139 | .parent = &clk_h133, | 311 | .parent = &clk_hclk_psys.clk, |
140 | .enable = s5pv210_clk_ip2_ctrl, | 312 | .enable = s5pv210_clk_ip2_ctrl, |
141 | .ctrlbit = (1<<17), | 313 | .ctrlbit = (1<<17), |
142 | }, { | 314 | }, { |
143 | .name = "hsmmc", | 315 | .name = "hsmmc", |
144 | .id = 2, | 316 | .id = 2, |
145 | .parent = &clk_h133, | 317 | .parent = &clk_hclk_psys.clk, |
146 | .enable = s5pv210_clk_ip2_ctrl, | 318 | .enable = s5pv210_clk_ip2_ctrl, |
147 | .ctrlbit = (1<<18), | 319 | .ctrlbit = (1<<18), |
148 | }, { | 320 | }, { |
149 | .name = "hsmmc", | 321 | .name = "hsmmc", |
150 | .id = 3, | 322 | .id = 3, |
151 | .parent = &clk_h133, | 323 | .parent = &clk_hclk_psys.clk, |
152 | .enable = s5pv210_clk_ip2_ctrl, | 324 | .enable = s5pv210_clk_ip2_ctrl, |
153 | .ctrlbit = (1<<19), | 325 | .ctrlbit = (1<<19), |
154 | }, { | 326 | }, { |
155 | .name = "systimer", | 327 | .name = "systimer", |
156 | .id = -1, | 328 | .id = -1, |
157 | .parent = &clk_p66, | 329 | .parent = &clk_pclk_psys.clk, |
158 | .enable = s5pv210_clk_ip3_ctrl, | 330 | .enable = s5pv210_clk_ip3_ctrl, |
159 | .ctrlbit = (1<<16), | 331 | .ctrlbit = (1<<16), |
160 | }, { | 332 | }, { |
161 | .name = "watchdog", | 333 | .name = "watchdog", |
162 | .id = -1, | 334 | .id = -1, |
163 | .parent = &clk_p66, | 335 | .parent = &clk_pclk_psys.clk, |
164 | .enable = s5pv210_clk_ip3_ctrl, | 336 | .enable = s5pv210_clk_ip3_ctrl, |
165 | .ctrlbit = (1<<22), | 337 | .ctrlbit = (1<<22), |
166 | }, { | 338 | }, { |
167 | .name = "rtc", | 339 | .name = "rtc", |
168 | .id = -1, | 340 | .id = -1, |
169 | .parent = &clk_p66, | 341 | .parent = &clk_pclk_psys.clk, |
170 | .enable = s5pv210_clk_ip3_ctrl, | 342 | .enable = s5pv210_clk_ip3_ctrl, |
171 | .ctrlbit = (1<<15), | 343 | .ctrlbit = (1<<15), |
172 | }, { | 344 | }, { |
173 | .name = "i2c", | 345 | .name = "i2c", |
174 | .id = 0, | 346 | .id = 0, |
175 | .parent = &clk_p66, | 347 | .parent = &clk_pclk_psys.clk, |
176 | .enable = s5pv210_clk_ip3_ctrl, | 348 | .enable = s5pv210_clk_ip3_ctrl, |
177 | .ctrlbit = (1<<7), | 349 | .ctrlbit = (1<<7), |
178 | }, { | 350 | }, { |
179 | .name = "i2c", | 351 | .name = "i2c", |
180 | .id = 1, | 352 | .id = 1, |
181 | .parent = &clk_p66, | 353 | .parent = &clk_pclk_psys.clk, |
182 | .enable = s5pv210_clk_ip3_ctrl, | 354 | .enable = s5pv210_clk_ip3_ctrl, |
183 | .ctrlbit = (1<<8), | 355 | .ctrlbit = (1<<8), |
184 | }, { | 356 | }, { |
185 | .name = "i2c", | 357 | .name = "i2c", |
186 | .id = 2, | 358 | .id = 2, |
187 | .parent = &clk_p66, | 359 | .parent = &clk_pclk_psys.clk, |
188 | .enable = s5pv210_clk_ip3_ctrl, | 360 | .enable = s5pv210_clk_ip3_ctrl, |
189 | .ctrlbit = (1<<9), | 361 | .ctrlbit = (1<<9), |
190 | }, { | 362 | }, { |
191 | .name = "spi", | 363 | .name = "spi", |
192 | .id = 0, | 364 | .id = 0, |
193 | .parent = &clk_p66, | 365 | .parent = &clk_pclk_psys.clk, |
194 | .enable = s5pv210_clk_ip3_ctrl, | 366 | .enable = s5pv210_clk_ip3_ctrl, |
195 | .ctrlbit = (1<<12), | 367 | .ctrlbit = (1<<12), |
196 | }, { | 368 | }, { |
197 | .name = "spi", | 369 | .name = "spi", |
198 | .id = 1, | 370 | .id = 1, |
199 | .parent = &clk_p66, | 371 | .parent = &clk_pclk_psys.clk, |
200 | .enable = s5pv210_clk_ip3_ctrl, | 372 | .enable = s5pv210_clk_ip3_ctrl, |
201 | .ctrlbit = (1<<13), | 373 | .ctrlbit = (1<<13), |
202 | }, { | 374 | }, { |
203 | .name = "spi", | 375 | .name = "spi", |
204 | .id = 2, | 376 | .id = 2, |
205 | .parent = &clk_p66, | 377 | .parent = &clk_pclk_psys.clk, |
206 | .enable = s5pv210_clk_ip3_ctrl, | 378 | .enable = s5pv210_clk_ip3_ctrl, |
207 | .ctrlbit = (1<<14), | 379 | .ctrlbit = (1<<14), |
208 | }, { | 380 | }, { |
209 | .name = "timers", | 381 | .name = "timers", |
210 | .id = -1, | 382 | .id = -1, |
211 | .parent = &clk_p66, | 383 | .parent = &clk_pclk_psys.clk, |
212 | .enable = s5pv210_clk_ip3_ctrl, | 384 | .enable = s5pv210_clk_ip3_ctrl, |
213 | .ctrlbit = (1<<23), | 385 | .ctrlbit = (1<<23), |
214 | }, { | 386 | }, { |
215 | .name = "adc", | 387 | .name = "adc", |
216 | .id = -1, | 388 | .id = -1, |
217 | .parent = &clk_p66, | 389 | .parent = &clk_pclk_psys.clk, |
218 | .enable = s5pv210_clk_ip3_ctrl, | 390 | .enable = s5pv210_clk_ip3_ctrl, |
219 | .ctrlbit = (1<<24), | 391 | .ctrlbit = (1<<24), |
220 | }, { | 392 | }, { |
221 | .name = "keypad", | 393 | .name = "keypad", |
222 | .id = -1, | 394 | .id = -1, |
223 | .parent = &clk_p66, | 395 | .parent = &clk_pclk_psys.clk, |
224 | .enable = s5pv210_clk_ip3_ctrl, | 396 | .enable = s5pv210_clk_ip3_ctrl, |
225 | .ctrlbit = (1<<21), | 397 | .ctrlbit = (1<<21), |
226 | }, { | 398 | }, { |
@@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = { | |||
246 | 418 | ||
247 | static struct clk init_clocks[] = { | 419 | static struct clk init_clocks[] = { |
248 | { | 420 | { |
421 | .name = "hclk_imem", | ||
422 | .id = -1, | ||
423 | .parent = &clk_hclk_msys.clk, | ||
424 | .ctrlbit = (1 << 5), | ||
425 | .enable = s5pv210_clk_ip0_ctrl, | ||
426 | .ops = &clk_hclk_imem_ops, | ||
427 | }, { | ||
249 | .name = "uart", | 428 | .name = "uart", |
250 | .id = 0, | 429 | .id = 0, |
251 | .parent = &clk_p66, | 430 | .parent = &clk_pclk_psys.clk, |
252 | .enable = s5pv210_clk_ip3_ctrl, | 431 | .enable = s5pv210_clk_ip3_ctrl, |
253 | .ctrlbit = (1<<7), | 432 | .ctrlbit = (1<<7), |
254 | }, { | 433 | }, { |
255 | .name = "uart", | 434 | .name = "uart", |
256 | .id = 1, | 435 | .id = 1, |
257 | .parent = &clk_p66, | 436 | .parent = &clk_pclk_psys.clk, |
258 | .enable = s5pv210_clk_ip3_ctrl, | 437 | .enable = s5pv210_clk_ip3_ctrl, |
259 | .ctrlbit = (1<<8), | 438 | .ctrlbit = (1<<8), |
260 | }, { | 439 | }, { |
261 | .name = "uart", | 440 | .name = "uart", |
262 | .id = 2, | 441 | .id = 2, |
263 | .parent = &clk_p66, | 442 | .parent = &clk_pclk_psys.clk, |
264 | .enable = s5pv210_clk_ip3_ctrl, | 443 | .enable = s5pv210_clk_ip3_ctrl, |
265 | .ctrlbit = (1<<9), | 444 | .ctrlbit = (1<<9), |
266 | }, { | 445 | }, { |
267 | .name = "uart", | 446 | .name = "uart", |
268 | .id = 3, | 447 | .id = 3, |
269 | .parent = &clk_p66, | 448 | .parent = &clk_pclk_psys.clk, |
270 | .enable = s5pv210_clk_ip3_ctrl, | 449 | .enable = s5pv210_clk_ip3_ctrl, |
271 | .ctrlbit = (1<<10), | 450 | .ctrlbit = (1<<10), |
272 | }, | 451 | }, |
273 | }; | 452 | }; |
274 | 453 | ||
275 | static struct clksrc_clk clk_mout_apll = { | 454 | static struct clk *clkset_uart_list[] = { |
276 | .clk = { | 455 | [6] = &clk_mout_mpll.clk, |
277 | .name = "mout_apll", | 456 | [7] = &clk_mout_epll.clk, |
457 | }; | ||
458 | |||
459 | static struct clksrc_sources clkset_uart = { | ||
460 | .sources = clkset_uart_list, | ||
461 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
462 | }; | ||
463 | |||
464 | static struct clk *clkset_group1_list[] = { | ||
465 | [0] = &clk_sclk_a2m.clk, | ||
466 | [1] = &clk_mout_mpll.clk, | ||
467 | [2] = &clk_mout_epll.clk, | ||
468 | [3] = &clk_sclk_vpll.clk, | ||
469 | }; | ||
470 | |||
471 | static struct clksrc_sources clkset_group1 = { | ||
472 | .sources = clkset_group1_list, | ||
473 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | ||
474 | }; | ||
475 | |||
476 | static struct clk *clkset_sclk_onenand_list[] = { | ||
477 | [0] = &clk_hclk_psys.clk, | ||
478 | [1] = &clk_hclk_dsys.clk, | ||
479 | }; | ||
480 | |||
481 | static struct clksrc_sources clkset_sclk_onenand = { | ||
482 | .sources = clkset_sclk_onenand_list, | ||
483 | .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list), | ||
484 | }; | ||
485 | |||
486 | static struct clk *clkset_sclk_dac_list[] = { | ||
487 | [0] = &clk_sclk_vpll.clk, | ||
488 | [1] = &clk_sclk_hdmiphy, | ||
489 | }; | ||
490 | |||
491 | static struct clksrc_sources clkset_sclk_dac = { | ||
492 | .sources = clkset_sclk_dac_list, | ||
493 | .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list), | ||
494 | }; | ||
495 | |||
496 | static struct clksrc_clk clk_sclk_dac = { | ||
497 | .clk = { | ||
498 | .name = "sclk_dac", | ||
278 | .id = -1, | 499 | .id = -1, |
500 | .ctrlbit = (1 << 10), | ||
501 | .enable = s5pv210_clk_ip1_ctrl, | ||
279 | }, | 502 | }, |
280 | .sources = &clk_src_apll, | 503 | .sources = &clkset_sclk_dac, |
281 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | 504 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, |
282 | }; | 505 | }; |
283 | 506 | ||
284 | static struct clksrc_clk clk_mout_epll = { | 507 | static struct clksrc_clk clk_sclk_pixel = { |
285 | .clk = { | 508 | .clk = { |
286 | .name = "mout_epll", | 509 | .name = "sclk_pixel", |
287 | .id = -1, | 510 | .id = -1, |
511 | .parent = &clk_sclk_vpll.clk, | ||
288 | }, | 512 | }, |
289 | .sources = &clk_src_epll, | 513 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, |
290 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | ||
291 | }; | 514 | }; |
292 | 515 | ||
293 | static struct clksrc_clk clk_mout_mpll = { | 516 | static struct clk *clkset_sclk_hdmi_list[] = { |
294 | .clk = { | 517 | [0] = &clk_sclk_pixel.clk, |
295 | .name = "mout_mpll", | 518 | [1] = &clk_sclk_hdmiphy, |
519 | }; | ||
520 | |||
521 | static struct clksrc_sources clkset_sclk_hdmi = { | ||
522 | .sources = clkset_sclk_hdmi_list, | ||
523 | .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list), | ||
524 | }; | ||
525 | |||
526 | static struct clksrc_clk clk_sclk_hdmi = { | ||
527 | .clk = { | ||
528 | .name = "sclk_hdmi", | ||
296 | .id = -1, | 529 | .id = -1, |
530 | .enable = s5pv210_clk_ip1_ctrl, | ||
531 | .ctrlbit = (1 << 11), | ||
297 | }, | 532 | }, |
298 | .sources = &clk_src_mpll, | 533 | .sources = &clkset_sclk_hdmi, |
299 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | 534 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, |
300 | }; | 535 | }; |
301 | 536 | ||
302 | static struct clk *clkset_uart_list[] = { | 537 | static struct clk *clkset_sclk_mixer_list[] = { |
538 | [0] = &clk_sclk_dac.clk, | ||
539 | [1] = &clk_sclk_hdmi.clk, | ||
540 | }; | ||
541 | |||
542 | static struct clksrc_sources clkset_sclk_mixer = { | ||
543 | .sources = clkset_sclk_mixer_list, | ||
544 | .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list), | ||
545 | }; | ||
546 | |||
547 | static struct clk *clkset_sclk_audio0_list[] = { | ||
548 | [0] = &clk_ext_xtal_mux, | ||
549 | [1] = &clk_pcmcdclk0, | ||
550 | [2] = &clk_sclk_hdmi27m, | ||
551 | [3] = &clk_sclk_usbphy0, | ||
552 | [4] = &clk_sclk_usbphy1, | ||
553 | [5] = &clk_sclk_hdmiphy, | ||
303 | [6] = &clk_mout_mpll.clk, | 554 | [6] = &clk_mout_mpll.clk, |
304 | [7] = &clk_mout_epll.clk, | 555 | [7] = &clk_mout_epll.clk, |
556 | [8] = &clk_sclk_vpll.clk, | ||
305 | }; | 557 | }; |
306 | 558 | ||
307 | static struct clksrc_sources clkset_uart = { | 559 | static struct clksrc_sources clkset_sclk_audio0 = { |
308 | .sources = clkset_uart_list, | 560 | .sources = clkset_sclk_audio0_list, |
309 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | 561 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), |
562 | }; | ||
563 | |||
564 | static struct clksrc_clk clk_sclk_audio0 = { | ||
565 | .clk = { | ||
566 | .name = "sclk_audio", | ||
567 | .id = 0, | ||
568 | .enable = s5pv210_clk_ip3_ctrl, | ||
569 | .ctrlbit = (1 << 4), | ||
570 | }, | ||
571 | .sources = &clkset_sclk_audio0, | ||
572 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, | ||
573 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 }, | ||
574 | }; | ||
575 | |||
576 | static struct clk *clkset_sclk_audio1_list[] = { | ||
577 | [0] = &clk_ext_xtal_mux, | ||
578 | [1] = &clk_pcmcdclk1, | ||
579 | [2] = &clk_sclk_hdmi27m, | ||
580 | [3] = &clk_sclk_usbphy0, | ||
581 | [4] = &clk_sclk_usbphy1, | ||
582 | [5] = &clk_sclk_hdmiphy, | ||
583 | [6] = &clk_mout_mpll.clk, | ||
584 | [7] = &clk_mout_epll.clk, | ||
585 | [8] = &clk_sclk_vpll.clk, | ||
586 | }; | ||
587 | |||
588 | static struct clksrc_sources clkset_sclk_audio1 = { | ||
589 | .sources = clkset_sclk_audio1_list, | ||
590 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list), | ||
591 | }; | ||
592 | |||
593 | static struct clksrc_clk clk_sclk_audio1 = { | ||
594 | .clk = { | ||
595 | .name = "sclk_audio", | ||
596 | .id = 1, | ||
597 | .enable = s5pv210_clk_ip3_ctrl, | ||
598 | .ctrlbit = (1 << 5), | ||
599 | }, | ||
600 | .sources = &clkset_sclk_audio1, | ||
601 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, | ||
602 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 }, | ||
603 | }; | ||
604 | |||
605 | static struct clk *clkset_sclk_audio2_list[] = { | ||
606 | [0] = &clk_ext_xtal_mux, | ||
607 | [1] = &clk_pcmcdclk0, | ||
608 | [2] = &clk_sclk_hdmi27m, | ||
609 | [3] = &clk_sclk_usbphy0, | ||
610 | [4] = &clk_sclk_usbphy1, | ||
611 | [5] = &clk_sclk_hdmiphy, | ||
612 | [6] = &clk_mout_mpll.clk, | ||
613 | [7] = &clk_mout_epll.clk, | ||
614 | [8] = &clk_sclk_vpll.clk, | ||
615 | }; | ||
616 | |||
617 | static struct clksrc_sources clkset_sclk_audio2 = { | ||
618 | .sources = clkset_sclk_audio2_list, | ||
619 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list), | ||
620 | }; | ||
621 | |||
622 | static struct clksrc_clk clk_sclk_audio2 = { | ||
623 | .clk = { | ||
624 | .name = "sclk_audio", | ||
625 | .id = 2, | ||
626 | .enable = s5pv210_clk_ip3_ctrl, | ||
627 | .ctrlbit = (1 << 6), | ||
628 | }, | ||
629 | .sources = &clkset_sclk_audio2, | ||
630 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, | ||
631 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 }, | ||
632 | }; | ||
633 | |||
634 | static struct clk *clkset_sclk_spdif_list[] = { | ||
635 | [0] = &clk_sclk_audio0.clk, | ||
636 | [1] = &clk_sclk_audio1.clk, | ||
637 | [2] = &clk_sclk_audio2.clk, | ||
638 | }; | ||
639 | |||
640 | static struct clksrc_sources clkset_sclk_spdif = { | ||
641 | .sources = clkset_sclk_spdif_list, | ||
642 | .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list), | ||
643 | }; | ||
644 | |||
645 | static struct clk *clkset_group2_list[] = { | ||
646 | [0] = &clk_ext_xtal_mux, | ||
647 | [1] = &clk_xusbxti, | ||
648 | [2] = &clk_sclk_hdmi27m, | ||
649 | [3] = &clk_sclk_usbphy0, | ||
650 | [4] = &clk_sclk_usbphy1, | ||
651 | [5] = &clk_sclk_hdmiphy, | ||
652 | [6] = &clk_mout_mpll.clk, | ||
653 | [7] = &clk_mout_epll.clk, | ||
654 | [8] = &clk_sclk_vpll.clk, | ||
655 | }; | ||
656 | |||
657 | static struct clksrc_sources clkset_group2 = { | ||
658 | .sources = clkset_group2_list, | ||
659 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | ||
310 | }; | 660 | }; |
311 | 661 | ||
312 | static struct clksrc_clk clksrcs[] = { | 662 | static struct clksrc_clk clksrcs[] = { |
313 | { | 663 | { |
314 | .clk = { | 664 | .clk = { |
315 | .name = "uclk1", | 665 | .name = "sclk_dmc", |
316 | .id = -1, | 666 | .id = -1, |
667 | }, | ||
668 | .sources = &clkset_group1, | ||
669 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, | ||
670 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, | ||
671 | }, { | ||
672 | .clk = { | ||
673 | .name = "sclk_onenand", | ||
674 | .id = -1, | ||
675 | }, | ||
676 | .sources = &clkset_sclk_onenand, | ||
677 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, | ||
678 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 }, | ||
679 | }, { | ||
680 | .clk = { | ||
681 | .name = "uclk1", | ||
682 | .id = 0, | ||
317 | .ctrlbit = (1<<17), | 683 | .ctrlbit = (1<<17), |
318 | .enable = s5pv210_clk_ip3_ctrl, | 684 | .enable = s5pv210_clk_ip3_ctrl, |
319 | }, | 685 | }, |
320 | .sources = &clkset_uart, | 686 | .sources = &clkset_uart, |
321 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, | 687 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, |
322 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | 688 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, |
323 | } | 689 | }, { |
690 | .clk = { | ||
691 | .name = "uclk1", | ||
692 | .id = 1, | ||
693 | .enable = s5pv210_clk_ip3_ctrl, | ||
694 | .ctrlbit = (1 << 18), | ||
695 | }, | ||
696 | .sources = &clkset_uart, | ||
697 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, | ||
698 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | ||
699 | }, { | ||
700 | .clk = { | ||
701 | .name = "uclk1", | ||
702 | .id = 2, | ||
703 | .enable = s5pv210_clk_ip3_ctrl, | ||
704 | .ctrlbit = (1 << 19), | ||
705 | }, | ||
706 | .sources = &clkset_uart, | ||
707 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, | ||
708 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 }, | ||
709 | }, { | ||
710 | .clk = { | ||
711 | .name = "uclk1", | ||
712 | .id = 3, | ||
713 | .enable = s5pv210_clk_ip3_ctrl, | ||
714 | .ctrlbit = (1 << 20), | ||
715 | }, | ||
716 | .sources = &clkset_uart, | ||
717 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, | ||
718 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, | ||
719 | }, { | ||
720 | .clk = { | ||
721 | .name = "sclk_mixer", | ||
722 | .id = -1, | ||
723 | .enable = s5pv210_clk_ip1_ctrl, | ||
724 | .ctrlbit = (1 << 9), | ||
725 | }, | ||
726 | .sources = &clkset_sclk_mixer, | ||
727 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, | ||
728 | }, { | ||
729 | .clk = { | ||
730 | .name = "sclk_spdif", | ||
731 | .id = -1, | ||
732 | .enable = s5pv210_clk_mask0_ctrl, | ||
733 | .ctrlbit = (1 << 27), | ||
734 | }, | ||
735 | .sources = &clkset_sclk_spdif, | ||
736 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 }, | ||
737 | }, { | ||
738 | .clk = { | ||
739 | .name = "sclk_fimc", | ||
740 | .id = 0, | ||
741 | .enable = s5pv210_clk_ip0_ctrl, | ||
742 | .ctrlbit = (1 << 24), | ||
743 | }, | ||
744 | .sources = &clkset_group2, | ||
745 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, | ||
746 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | ||
747 | }, { | ||
748 | .clk = { | ||
749 | .name = "sclk_fimc", | ||
750 | .id = 1, | ||
751 | .enable = s5pv210_clk_ip0_ctrl, | ||
752 | .ctrlbit = (1 << 25), | ||
753 | }, | ||
754 | .sources = &clkset_group2, | ||
755 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, | ||
756 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | ||
757 | }, { | ||
758 | .clk = { | ||
759 | .name = "sclk_fimc", | ||
760 | .id = 2, | ||
761 | .enable = s5pv210_clk_ip0_ctrl, | ||
762 | .ctrlbit = (1 << 26), | ||
763 | }, | ||
764 | .sources = &clkset_group2, | ||
765 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, | ||
766 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | ||
767 | }, { | ||
768 | .clk = { | ||
769 | .name = "sclk_cam", | ||
770 | .id = 0, | ||
771 | }, | ||
772 | .sources = &clkset_group2, | ||
773 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, | ||
774 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 }, | ||
775 | }, { | ||
776 | .clk = { | ||
777 | .name = "sclk_cam", | ||
778 | .id = 1, | ||
779 | }, | ||
780 | .sources = &clkset_group2, | ||
781 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, | ||
782 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 }, | ||
783 | }, { | ||
784 | .clk = { | ||
785 | .name = "sclk_fimd", | ||
786 | .id = -1, | ||
787 | .enable = s5pv210_clk_ip1_ctrl, | ||
788 | .ctrlbit = (1 << 0), | ||
789 | }, | ||
790 | .sources = &clkset_group2, | ||
791 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, | ||
792 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, | ||
793 | }, { | ||
794 | .clk = { | ||
795 | .name = "sclk_mmc", | ||
796 | .id = 0, | ||
797 | .enable = s5pv210_clk_ip2_ctrl, | ||
798 | .ctrlbit = (1 << 16), | ||
799 | }, | ||
800 | .sources = &clkset_group2, | ||
801 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, | ||
802 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 }, | ||
803 | }, { | ||
804 | .clk = { | ||
805 | .name = "sclk_mmc", | ||
806 | .id = 1, | ||
807 | .enable = s5pv210_clk_ip2_ctrl, | ||
808 | .ctrlbit = (1 << 17), | ||
809 | }, | ||
810 | .sources = &clkset_group2, | ||
811 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, | ||
812 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 }, | ||
813 | }, { | ||
814 | .clk = { | ||
815 | .name = "sclk_mmc", | ||
816 | .id = 2, | ||
817 | .enable = s5pv210_clk_ip2_ctrl, | ||
818 | .ctrlbit = (1 << 18), | ||
819 | }, | ||
820 | .sources = &clkset_group2, | ||
821 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, | ||
822 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 }, | ||
823 | }, { | ||
824 | .clk = { | ||
825 | .name = "sclk_mmc", | ||
826 | .id = 3, | ||
827 | .enable = s5pv210_clk_ip2_ctrl, | ||
828 | .ctrlbit = (1 << 19), | ||
829 | }, | ||
830 | .sources = &clkset_group2, | ||
831 | .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, | ||
832 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | ||
833 | }, { | ||
834 | .clk = { | ||
835 | .name = "sclk_mfc", | ||
836 | .id = -1, | ||
837 | .enable = s5pv210_clk_ip0_ctrl, | ||
838 | .ctrlbit = (1 << 16), | ||
839 | }, | ||
840 | .sources = &clkset_group1, | ||
841 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | ||
842 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | ||
843 | }, { | ||
844 | .clk = { | ||
845 | .name = "sclk_g2d", | ||
846 | .id = -1, | ||
847 | .enable = s5pv210_clk_ip0_ctrl, | ||
848 | .ctrlbit = (1 << 12), | ||
849 | }, | ||
850 | .sources = &clkset_group1, | ||
851 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | ||
852 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | ||
853 | }, { | ||
854 | .clk = { | ||
855 | .name = "sclk_g3d", | ||
856 | .id = -1, | ||
857 | .enable = s5pv210_clk_ip0_ctrl, | ||
858 | .ctrlbit = (1 << 8), | ||
859 | }, | ||
860 | .sources = &clkset_group1, | ||
861 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | ||
862 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | ||
863 | }, { | ||
864 | .clk = { | ||
865 | .name = "sclk_csis", | ||
866 | .id = -1, | ||
867 | .enable = s5pv210_clk_ip0_ctrl, | ||
868 | .ctrlbit = (1 << 31), | ||
869 | }, | ||
870 | .sources = &clkset_group2, | ||
871 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, | ||
872 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 }, | ||
873 | }, { | ||
874 | .clk = { | ||
875 | .name = "sclk_spi", | ||
876 | .id = 0, | ||
877 | .enable = s5pv210_clk_ip3_ctrl, | ||
878 | .ctrlbit = (1 << 12), | ||
879 | }, | ||
880 | .sources = &clkset_group2, | ||
881 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, | ||
882 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 }, | ||
883 | }, { | ||
884 | .clk = { | ||
885 | .name = "sclk_spi", | ||
886 | .id = 1, | ||
887 | .enable = s5pv210_clk_ip3_ctrl, | ||
888 | .ctrlbit = (1 << 13), | ||
889 | }, | ||
890 | .sources = &clkset_group2, | ||
891 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, | ||
892 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 }, | ||
893 | }, { | ||
894 | .clk = { | ||
895 | .name = "sclk_pwi", | ||
896 | .id = -1, | ||
897 | .enable = &s5pv210_clk_ip4_ctrl, | ||
898 | .ctrlbit = (1 << 2), | ||
899 | }, | ||
900 | .sources = &clkset_group2, | ||
901 | .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, | ||
902 | .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 }, | ||
903 | }, { | ||
904 | .clk = { | ||
905 | .name = "sclk_pwm", | ||
906 | .id = -1, | ||
907 | .enable = s5pv210_clk_ip3_ctrl, | ||
908 | .ctrlbit = (1 << 23), | ||
909 | }, | ||
910 | .sources = &clkset_group2, | ||
911 | .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, | ||
912 | .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 }, | ||
913 | }, | ||
324 | }; | 914 | }; |
325 | 915 | ||
326 | /* Clock initialisation code */ | 916 | /* Clock initialisation code */ |
327 | static struct clksrc_clk *init_parents[] = { | 917 | static struct clksrc_clk *sysclks[] = { |
328 | &clk_mout_apll, | 918 | &clk_mout_apll, |
329 | &clk_mout_epll, | 919 | &clk_mout_epll, |
330 | &clk_mout_mpll, | 920 | &clk_mout_mpll, |
921 | &clk_armclk, | ||
922 | &clk_hclk_msys, | ||
923 | &clk_sclk_a2m, | ||
924 | &clk_hclk_dsys, | ||
925 | &clk_hclk_psys, | ||
926 | &clk_pclk_msys, | ||
927 | &clk_pclk_dsys, | ||
928 | &clk_pclk_psys, | ||
929 | &clk_vpllsrc, | ||
930 | &clk_sclk_vpll, | ||
931 | &clk_sclk_dac, | ||
932 | &clk_sclk_pixel, | ||
933 | &clk_sclk_hdmi, | ||
331 | }; | 934 | }; |
332 | 935 | ||
333 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
334 | |||
335 | void __init_or_cpufreq s5pv210_setup_clocks(void) | 936 | void __init_or_cpufreq s5pv210_setup_clocks(void) |
336 | { | 937 | { |
337 | struct clk *xtal_clk; | 938 | struct clk *xtal_clk; |
338 | unsigned long xtal; | 939 | unsigned long xtal; |
940 | unsigned long vpllsrc; | ||
339 | unsigned long armclk; | 941 | unsigned long armclk; |
340 | unsigned long hclk200; | 942 | unsigned long hclk_msys; |
341 | unsigned long hclk166; | 943 | unsigned long hclk_dsys; |
342 | unsigned long hclk133; | 944 | unsigned long hclk_psys; |
343 | unsigned long pclk100; | 945 | unsigned long pclk_msys; |
344 | unsigned long pclk83; | 946 | unsigned long pclk_dsys; |
345 | unsigned long pclk66; | 947 | unsigned long pclk_psys; |
346 | unsigned long apll; | 948 | unsigned long apll; |
347 | unsigned long mpll; | 949 | unsigned long mpll; |
348 | unsigned long epll; | 950 | unsigned long epll; |
951 | unsigned long vpll; | ||
349 | unsigned int ptr; | 952 | unsigned int ptr; |
350 | u32 clkdiv0, clkdiv1; | 953 | u32 clkdiv0, clkdiv1; |
351 | 954 | ||
@@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) | |||
368 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); | 971 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); |
369 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); | 972 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); |
370 | epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); | 973 | epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); |
371 | 974 | vpllsrc = clk_get_rate(&clk_vpllsrc.clk); | |
372 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", | 975 | vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); |
373 | apll, mpll, epll); | ||
374 | |||
375 | armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL); | ||
376 | if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK) | ||
377 | hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); | ||
378 | else | ||
379 | hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200); | ||
380 | |||
381 | if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) { | ||
382 | hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); | ||
383 | hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); | ||
384 | } else | ||
385 | hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166); | ||
386 | |||
387 | if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) { | ||
388 | hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M); | ||
389 | hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); | ||
390 | } else | ||
391 | hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133); | ||
392 | |||
393 | pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100); | ||
394 | pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83); | ||
395 | pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66); | ||
396 | |||
397 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \ | ||
398 | HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | ||
399 | armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66); | ||
400 | 976 | ||
401 | clk_fout_apll.rate = apll; | 977 | clk_fout_apll.rate = apll; |
402 | clk_fout_mpll.rate = mpll; | 978 | clk_fout_mpll.rate = mpll; |
403 | clk_fout_epll.rate = epll; | 979 | clk_fout_epll.rate = epll; |
980 | clk_fout_vpll.rate = vpll; | ||
404 | 981 | ||
405 | clk_f.rate = armclk; | 982 | printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", |
406 | clk_h.rate = hclk133; | 983 | apll, mpll, epll, vpll); |
407 | clk_p.rate = pclk66; | 984 | |
408 | clk_p66.rate = pclk66; | 985 | armclk = clk_get_rate(&clk_armclk.clk); |
409 | clk_p83.rate = pclk83; | 986 | hclk_msys = clk_get_rate(&clk_hclk_msys.clk); |
410 | clk_h133.rate = hclk133; | 987 | hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); |
411 | clk_h166.rate = hclk166; | 988 | hclk_psys = clk_get_rate(&clk_hclk_psys.clk); |
412 | clk_h200.rate = hclk200; | 989 | pclk_msys = clk_get_rate(&clk_pclk_msys.clk); |
990 | pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); | ||
991 | pclk_psys = clk_get_rate(&clk_pclk_psys.clk); | ||
992 | |||
993 | printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" | ||
994 | "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", | ||
995 | armclk, hclk_msys, hclk_dsys, hclk_psys, | ||
996 | pclk_msys, pclk_dsys, pclk_psys); | ||
413 | 997 | ||
414 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | 998 | clk_f.rate = armclk; |
415 | s3c_set_clksrc(init_parents[ptr], true); | 999 | clk_h.rate = hclk_psys; |
1000 | clk_p.rate = pclk_psys; | ||
416 | 1001 | ||
417 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | 1002 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
418 | s3c_set_clksrc(&clksrcs[ptr], true); | 1003 | s3c_set_clksrc(&clksrcs[ptr], true); |
419 | } | 1004 | } |
420 | 1005 | ||
421 | static struct clk *clks[] __initdata = { | 1006 | static struct clk *clks[] __initdata = { |
422 | &clk_mout_epll.clk, | 1007 | &clk_sclk_hdmi27m, |
423 | &clk_mout_mpll.clk, | 1008 | &clk_sclk_hdmiphy, |
1009 | &clk_sclk_usbphy0, | ||
1010 | &clk_sclk_usbphy1, | ||
1011 | &clk_pcmcdclk0, | ||
1012 | &clk_pcmcdclk1, | ||
1013 | &clk_pcmcdclk2, | ||
424 | }; | 1014 | }; |
425 | 1015 | ||
426 | void __init s5pv210_register_clocks(void) | 1016 | void __init s5pv210_register_clocks(void) |
@@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void) | |||
433 | if (ret > 0) | 1023 | if (ret > 0) |
434 | printk(KERN_ERR "Failed to register %u clocks\n", ret); | 1024 | printk(KERN_ERR "Failed to register %u clocks\n", ret); |
435 | 1025 | ||
1026 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
1027 | s3c_register_clksrc(sysclks[ptr], 1); | ||
1028 | |||
436 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | 1029 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); |
437 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | 1030 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); |
438 | 1031 | ||
439 | ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks)); | ||
440 | if (ret > 0) | ||
441 | printk(KERN_ERR "Failed to register system clocks\n"); | ||
442 | |||
443 | clkp = init_clocks_disable; | 1032 | clkp = init_clocks_disable; |
444 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | 1033 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { |
445 | ret = s3c24xx_register_clock(clkp); | 1034 | ret = s3c24xx_register_clock(clkp); |
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 0e0f8fde2aa6..2b776eb5d150 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c | |||
@@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void) | |||
100 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | 100 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
101 | } | 101 | } |
102 | 102 | ||
103 | static struct sysdev_class s5pv210_sysclass = { | 103 | struct sysdev_class s5pv210_sysclass = { |
104 | .name = "s5pv210-core", | 104 | .name = "s5pv210-core", |
105 | }; | 105 | }; |
106 | 106 | ||
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c new file mode 100644 index 000000000000..6e215330a1be --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-audio.c | |||
@@ -0,0 +1,327 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/dev-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | ||
15 | #include <plat/audio.h> | ||
16 | |||
17 | #include <mach/gpio.h> | ||
18 | #include <mach/map.h> | ||
19 | #include <mach/dma.h> | ||
20 | #include <mach/irqs.h> | ||
21 | |||
22 | static int s5pv210_cfg_i2s(struct platform_device *pdev) | ||
23 | { | ||
24 | /* configure GPIO for i2s port */ | ||
25 | switch (pdev->id) { | ||
26 | case 1: | ||
27 | s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(2)); | ||
28 | s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(2)); | ||
29 | s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(2)); | ||
30 | s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(2)); | ||
31 | s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(2)); | ||
32 | break; | ||
33 | |||
34 | case 2: | ||
35 | s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(4)); | ||
36 | s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(4)); | ||
37 | s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(4)); | ||
38 | s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(4)); | ||
39 | s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(4)); | ||
40 | break; | ||
41 | |||
42 | case -1: | ||
43 | s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(2)); | ||
44 | s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(2)); | ||
45 | s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(2)); | ||
46 | s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(2)); | ||
47 | s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(2)); | ||
48 | s3c_gpio_cfgpin(S5PV210_GPI(5), S3C_GPIO_SFN(2)); | ||
49 | s3c_gpio_cfgpin(S5PV210_GPI(6), S3C_GPIO_SFN(2)); | ||
50 | break; | ||
51 | |||
52 | default: | ||
53 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
54 | return -EINVAL; | ||
55 | } | ||
56 | |||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | static struct s3c_audio_pdata s3c_i2s_pdata = { | ||
61 | .cfg_gpio = s5pv210_cfg_i2s, | ||
62 | }; | ||
63 | |||
64 | static struct resource s5pv210_iis0_resource[] = { | ||
65 | [0] = { | ||
66 | .start = S5PV210_PA_IIS0, | ||
67 | .end = S5PV210_PA_IIS0 + 0x100 - 1, | ||
68 | .flags = IORESOURCE_MEM, | ||
69 | }, | ||
70 | [1] = { | ||
71 | .start = DMACH_I2S0_TX, | ||
72 | .end = DMACH_I2S0_TX, | ||
73 | .flags = IORESOURCE_DMA, | ||
74 | }, | ||
75 | [2] = { | ||
76 | .start = DMACH_I2S0_RX, | ||
77 | .end = DMACH_I2S0_RX, | ||
78 | .flags = IORESOURCE_DMA, | ||
79 | }, | ||
80 | }; | ||
81 | |||
82 | struct platform_device s5pv210_device_iis0 = { | ||
83 | .name = "s3c64xx-iis-v4", | ||
84 | .id = -1, | ||
85 | .num_resources = ARRAY_SIZE(s5pv210_iis0_resource), | ||
86 | .resource = s5pv210_iis0_resource, | ||
87 | .dev = { | ||
88 | .platform_data = &s3c_i2s_pdata, | ||
89 | }, | ||
90 | }; | ||
91 | |||
92 | static struct resource s5pv210_iis1_resource[] = { | ||
93 | [0] = { | ||
94 | .start = S5PV210_PA_IIS1, | ||
95 | .end = S5PV210_PA_IIS1 + 0x100 - 1, | ||
96 | .flags = IORESOURCE_MEM, | ||
97 | }, | ||
98 | [1] = { | ||
99 | .start = DMACH_I2S1_TX, | ||
100 | .end = DMACH_I2S1_TX, | ||
101 | .flags = IORESOURCE_DMA, | ||
102 | }, | ||
103 | [2] = { | ||
104 | .start = DMACH_I2S1_RX, | ||
105 | .end = DMACH_I2S1_RX, | ||
106 | .flags = IORESOURCE_DMA, | ||
107 | }, | ||
108 | }; | ||
109 | |||
110 | struct platform_device s5pv210_device_iis1 = { | ||
111 | .name = "s3c64xx-iis", | ||
112 | .id = 1, | ||
113 | .num_resources = ARRAY_SIZE(s5pv210_iis1_resource), | ||
114 | .resource = s5pv210_iis1_resource, | ||
115 | .dev = { | ||
116 | .platform_data = &s3c_i2s_pdata, | ||
117 | }, | ||
118 | }; | ||
119 | |||
120 | static struct resource s5pv210_iis2_resource[] = { | ||
121 | [0] = { | ||
122 | .start = S5PV210_PA_IIS2, | ||
123 | .end = S5PV210_PA_IIS2 + 0x100 - 1, | ||
124 | .flags = IORESOURCE_MEM, | ||
125 | }, | ||
126 | [1] = { | ||
127 | .start = DMACH_I2S2_TX, | ||
128 | .end = DMACH_I2S2_TX, | ||
129 | .flags = IORESOURCE_DMA, | ||
130 | }, | ||
131 | [2] = { | ||
132 | .start = DMACH_I2S2_RX, | ||
133 | .end = DMACH_I2S2_RX, | ||
134 | .flags = IORESOURCE_DMA, | ||
135 | }, | ||
136 | }; | ||
137 | |||
138 | struct platform_device s5pv210_device_iis2 = { | ||
139 | .name = "s3c64xx-iis", | ||
140 | .id = 2, | ||
141 | .num_resources = ARRAY_SIZE(s5pv210_iis2_resource), | ||
142 | .resource = s5pv210_iis2_resource, | ||
143 | .dev = { | ||
144 | .platform_data = &s3c_i2s_pdata, | ||
145 | }, | ||
146 | }; | ||
147 | |||
148 | /* PCM Controller platform_devices */ | ||
149 | |||
150 | static int s5pv210_pcm_cfg_gpio(struct platform_device *pdev) | ||
151 | { | ||
152 | switch (pdev->id) { | ||
153 | case 0: | ||
154 | s3c_gpio_cfgpin(S5PV210_GPI(0), S3C_GPIO_SFN(3)); | ||
155 | s3c_gpio_cfgpin(S5PV210_GPI(1), S3C_GPIO_SFN(3)); | ||
156 | s3c_gpio_cfgpin(S5PV210_GPI(2), S3C_GPIO_SFN(3)); | ||
157 | s3c_gpio_cfgpin(S5PV210_GPI(3), S3C_GPIO_SFN(3)); | ||
158 | s3c_gpio_cfgpin(S5PV210_GPI(4), S3C_GPIO_SFN(3)); | ||
159 | break; | ||
160 | case 1: | ||
161 | s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(3)); | ||
162 | s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(3)); | ||
163 | s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(3)); | ||
164 | s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(3)); | ||
165 | s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(3)); | ||
166 | break; | ||
167 | case 2: | ||
168 | s3c_gpio_cfgpin(S5PV210_GPC1(0), S3C_GPIO_SFN(2)); | ||
169 | s3c_gpio_cfgpin(S5PV210_GPC1(1), S3C_GPIO_SFN(2)); | ||
170 | s3c_gpio_cfgpin(S5PV210_GPC1(2), S3C_GPIO_SFN(2)); | ||
171 | s3c_gpio_cfgpin(S5PV210_GPC1(3), S3C_GPIO_SFN(2)); | ||
172 | s3c_gpio_cfgpin(S5PV210_GPC1(4), S3C_GPIO_SFN(2)); | ||
173 | break; | ||
174 | default: | ||
175 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
176 | return -EINVAL; | ||
177 | } | ||
178 | |||
179 | return 0; | ||
180 | } | ||
181 | |||
182 | static struct s3c_audio_pdata s3c_pcm_pdata = { | ||
183 | .cfg_gpio = s5pv210_pcm_cfg_gpio, | ||
184 | }; | ||
185 | |||
186 | static struct resource s5pv210_pcm0_resource[] = { | ||
187 | [0] = { | ||
188 | .start = S5PV210_PA_PCM0, | ||
189 | .end = S5PV210_PA_PCM0 + 0x100 - 1, | ||
190 | .flags = IORESOURCE_MEM, | ||
191 | }, | ||
192 | [1] = { | ||
193 | .start = DMACH_PCM0_TX, | ||
194 | .end = DMACH_PCM0_TX, | ||
195 | .flags = IORESOURCE_DMA, | ||
196 | }, | ||
197 | [2] = { | ||
198 | .start = DMACH_PCM0_RX, | ||
199 | .end = DMACH_PCM0_RX, | ||
200 | .flags = IORESOURCE_DMA, | ||
201 | }, | ||
202 | }; | ||
203 | |||
204 | struct platform_device s5pv210_device_pcm0 = { | ||
205 | .name = "samsung-pcm", | ||
206 | .id = 0, | ||
207 | .num_resources = ARRAY_SIZE(s5pv210_pcm0_resource), | ||
208 | .resource = s5pv210_pcm0_resource, | ||
209 | .dev = { | ||
210 | .platform_data = &s3c_pcm_pdata, | ||
211 | }, | ||
212 | }; | ||
213 | |||
214 | static struct resource s5pv210_pcm1_resource[] = { | ||
215 | [0] = { | ||
216 | .start = S5PV210_PA_PCM1, | ||
217 | .end = S5PV210_PA_PCM1 + 0x100 - 1, | ||
218 | .flags = IORESOURCE_MEM, | ||
219 | }, | ||
220 | [1] = { | ||
221 | .start = DMACH_PCM1_TX, | ||
222 | .end = DMACH_PCM1_TX, | ||
223 | .flags = IORESOURCE_DMA, | ||
224 | }, | ||
225 | [2] = { | ||
226 | .start = DMACH_PCM1_RX, | ||
227 | .end = DMACH_PCM1_RX, | ||
228 | .flags = IORESOURCE_DMA, | ||
229 | }, | ||
230 | }; | ||
231 | |||
232 | struct platform_device s5pv210_device_pcm1 = { | ||
233 | .name = "samsung-pcm", | ||
234 | .id = 1, | ||
235 | .num_resources = ARRAY_SIZE(s5pv210_pcm1_resource), | ||
236 | .resource = s5pv210_pcm1_resource, | ||
237 | .dev = { | ||
238 | .platform_data = &s3c_pcm_pdata, | ||
239 | }, | ||
240 | }; | ||
241 | |||
242 | static struct resource s5pv210_pcm2_resource[] = { | ||
243 | [0] = { | ||
244 | .start = S5PV210_PA_PCM2, | ||
245 | .end = S5PV210_PA_PCM2 + 0x100 - 1, | ||
246 | .flags = IORESOURCE_MEM, | ||
247 | }, | ||
248 | [1] = { | ||
249 | .start = DMACH_PCM2_TX, | ||
250 | .end = DMACH_PCM2_TX, | ||
251 | .flags = IORESOURCE_DMA, | ||
252 | }, | ||
253 | [2] = { | ||
254 | .start = DMACH_PCM2_RX, | ||
255 | .end = DMACH_PCM2_RX, | ||
256 | .flags = IORESOURCE_DMA, | ||
257 | }, | ||
258 | }; | ||
259 | |||
260 | struct platform_device s5pv210_device_pcm2 = { | ||
261 | .name = "samsung-pcm", | ||
262 | .id = 2, | ||
263 | .num_resources = ARRAY_SIZE(s5pv210_pcm2_resource), | ||
264 | .resource = s5pv210_pcm2_resource, | ||
265 | .dev = { | ||
266 | .platform_data = &s3c_pcm_pdata, | ||
267 | }, | ||
268 | }; | ||
269 | |||
270 | /* AC97 Controller platform devices */ | ||
271 | |||
272 | static int s5pv210_ac97_cfg_gpio(struct platform_device *pdev) | ||
273 | { | ||
274 | s3c_gpio_cfgpin(S5PV210_GPC0(0), S3C_GPIO_SFN(4)); | ||
275 | s3c_gpio_cfgpin(S5PV210_GPC0(1), S3C_GPIO_SFN(4)); | ||
276 | s3c_gpio_cfgpin(S5PV210_GPC0(2), S3C_GPIO_SFN(4)); | ||
277 | s3c_gpio_cfgpin(S5PV210_GPC0(3), S3C_GPIO_SFN(4)); | ||
278 | s3c_gpio_cfgpin(S5PV210_GPC0(4), S3C_GPIO_SFN(4)); | ||
279 | |||
280 | return 0; | ||
281 | } | ||
282 | |||
283 | static struct resource s5pv210_ac97_resource[] = { | ||
284 | [0] = { | ||
285 | .start = S5PV210_PA_AC97, | ||
286 | .end = S5PV210_PA_AC97 + 0x100 - 1, | ||
287 | .flags = IORESOURCE_MEM, | ||
288 | }, | ||
289 | [1] = { | ||
290 | .start = DMACH_AC97_PCMOUT, | ||
291 | .end = DMACH_AC97_PCMOUT, | ||
292 | .flags = IORESOURCE_DMA, | ||
293 | }, | ||
294 | [2] = { | ||
295 | .start = DMACH_AC97_PCMIN, | ||
296 | .end = DMACH_AC97_PCMIN, | ||
297 | .flags = IORESOURCE_DMA, | ||
298 | }, | ||
299 | [3] = { | ||
300 | .start = DMACH_AC97_MICIN, | ||
301 | .end = DMACH_AC97_MICIN, | ||
302 | .flags = IORESOURCE_DMA, | ||
303 | }, | ||
304 | [4] = { | ||
305 | .start = IRQ_AC97, | ||
306 | .end = IRQ_AC97, | ||
307 | .flags = IORESOURCE_IRQ, | ||
308 | }, | ||
309 | }; | ||
310 | |||
311 | static struct s3c_audio_pdata s3c_ac97_pdata = { | ||
312 | .cfg_gpio = s5pv210_ac97_cfg_gpio, | ||
313 | }; | ||
314 | |||
315 | static u64 s5pv210_ac97_dmamask = DMA_BIT_MASK(32); | ||
316 | |||
317 | struct platform_device s5pv210_device_ac97 = { | ||
318 | .name = "s3c-ac97", | ||
319 | .id = -1, | ||
320 | .num_resources = ARRAY_SIZE(s5pv210_ac97_resource), | ||
321 | .resource = s5pv210_ac97_resource, | ||
322 | .dev = { | ||
323 | .platform_data = &s3c_ac97_pdata, | ||
324 | .dma_mask = &s5pv210_ac97_dmamask, | ||
325 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
326 | }, | ||
327 | }; | ||
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c new file mode 100644 index 000000000000..778ad5fe231a --- /dev/null +++ b/arch/arm/mach-s5pv210/dma.c | |||
@@ -0,0 +1,168 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/dma-mapping.h> | ||
22 | |||
23 | #include <plat/devs.h> | ||
24 | #include <plat/irqs.h> | ||
25 | |||
26 | #include <mach/map.h> | ||
27 | #include <mach/irqs.h> | ||
28 | |||
29 | #include <plat/s3c-pl330-pdata.h> | ||
30 | |||
31 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
32 | |||
33 | static struct resource s5pv210_pdma0_resource[] = { | ||
34 | [0] = { | ||
35 | .start = S5PV210_PA_PDMA0, | ||
36 | .end = S5PV210_PA_PDMA0 + SZ_4K, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, | ||
39 | [1] = { | ||
40 | .start = IRQ_PDMA0, | ||
41 | .end = IRQ_PDMA0, | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | }; | ||
45 | |||
46 | static struct s3c_pl330_platdata s5pv210_pdma0_pdata = { | ||
47 | .peri = { | ||
48 | [0] = DMACH_UART0_RX, | ||
49 | [1] = DMACH_UART0_TX, | ||
50 | [2] = DMACH_UART1_RX, | ||
51 | [3] = DMACH_UART1_TX, | ||
52 | [4] = DMACH_UART2_RX, | ||
53 | [5] = DMACH_UART2_TX, | ||
54 | [6] = DMACH_UART3_RX, | ||
55 | [7] = DMACH_UART3_TX, | ||
56 | [8] = DMACH_MAX, | ||
57 | [9] = DMACH_I2S0_RX, | ||
58 | [10] = DMACH_I2S0_TX, | ||
59 | [11] = DMACH_I2S0S_TX, | ||
60 | [12] = DMACH_I2S1_RX, | ||
61 | [13] = DMACH_I2S1_TX, | ||
62 | [14] = DMACH_MAX, | ||
63 | [15] = DMACH_MAX, | ||
64 | [16] = DMACH_SPI0_RX, | ||
65 | [17] = DMACH_SPI0_TX, | ||
66 | [18] = DMACH_SPI1_RX, | ||
67 | [19] = DMACH_SPI1_TX, | ||
68 | [20] = DMACH_MAX, | ||
69 | [21] = DMACH_MAX, | ||
70 | [22] = DMACH_AC97_MICIN, | ||
71 | [23] = DMACH_AC97_PCMIN, | ||
72 | [24] = DMACH_AC97_PCMOUT, | ||
73 | [25] = DMACH_MAX, | ||
74 | [26] = DMACH_PWM, | ||
75 | [27] = DMACH_SPDIF, | ||
76 | [28] = DMACH_MAX, | ||
77 | [29] = DMACH_MAX, | ||
78 | [30] = DMACH_MAX, | ||
79 | [31] = DMACH_MAX, | ||
80 | }, | ||
81 | }; | ||
82 | |||
83 | static struct platform_device s5pv210_device_pdma0 = { | ||
84 | .name = "s3c-pl330", | ||
85 | .id = 1, | ||
86 | .num_resources = ARRAY_SIZE(s5pv210_pdma0_resource), | ||
87 | .resource = s5pv210_pdma0_resource, | ||
88 | .dev = { | ||
89 | .dma_mask = &dma_dmamask, | ||
90 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
91 | .platform_data = &s5pv210_pdma0_pdata, | ||
92 | }, | ||
93 | }; | ||
94 | |||
95 | static struct resource s5pv210_pdma1_resource[] = { | ||
96 | [0] = { | ||
97 | .start = S5PV210_PA_PDMA1, | ||
98 | .end = S5PV210_PA_PDMA1 + SZ_4K, | ||
99 | .flags = IORESOURCE_MEM, | ||
100 | }, | ||
101 | [1] = { | ||
102 | .start = IRQ_PDMA1, | ||
103 | .end = IRQ_PDMA1, | ||
104 | .flags = IORESOURCE_IRQ, | ||
105 | }, | ||
106 | }; | ||
107 | |||
108 | static struct s3c_pl330_platdata s5pv210_pdma1_pdata = { | ||
109 | .peri = { | ||
110 | [0] = DMACH_UART0_RX, | ||
111 | [1] = DMACH_UART0_TX, | ||
112 | [2] = DMACH_UART1_RX, | ||
113 | [3] = DMACH_UART1_TX, | ||
114 | [4] = DMACH_UART2_RX, | ||
115 | [5] = DMACH_UART2_TX, | ||
116 | [6] = DMACH_UART3_RX, | ||
117 | [7] = DMACH_UART3_TX, | ||
118 | [8] = DMACH_MAX, | ||
119 | [9] = DMACH_I2S0_RX, | ||
120 | [10] = DMACH_I2S0_TX, | ||
121 | [11] = DMACH_I2S0S_TX, | ||
122 | [12] = DMACH_I2S1_RX, | ||
123 | [13] = DMACH_I2S1_TX, | ||
124 | [14] = DMACH_I2S2_RX, | ||
125 | [15] = DMACH_I2S2_TX, | ||
126 | [16] = DMACH_SPI0_RX, | ||
127 | [17] = DMACH_SPI0_TX, | ||
128 | [18] = DMACH_SPI1_RX, | ||
129 | [19] = DMACH_SPI1_TX, | ||
130 | [20] = DMACH_MAX, | ||
131 | [21] = DMACH_MAX, | ||
132 | [22] = DMACH_PCM0_RX, | ||
133 | [23] = DMACH_PCM0_TX, | ||
134 | [24] = DMACH_PCM1_RX, | ||
135 | [25] = DMACH_PCM1_TX, | ||
136 | [26] = DMACH_MSM_REQ0, | ||
137 | [27] = DMACH_MSM_REQ1, | ||
138 | [28] = DMACH_MSM_REQ2, | ||
139 | [29] = DMACH_MSM_REQ3, | ||
140 | [30] = DMACH_PCM2_RX, | ||
141 | [31] = DMACH_PCM2_TX, | ||
142 | }, | ||
143 | }; | ||
144 | |||
145 | static struct platform_device s5pv210_device_pdma1 = { | ||
146 | .name = "s3c-pl330", | ||
147 | .id = 2, | ||
148 | .num_resources = ARRAY_SIZE(s5pv210_pdma1_resource), | ||
149 | .resource = s5pv210_pdma1_resource, | ||
150 | .dev = { | ||
151 | .dma_mask = &dma_dmamask, | ||
152 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
153 | .platform_data = &s5pv210_pdma1_pdata, | ||
154 | }, | ||
155 | }; | ||
156 | |||
157 | static struct platform_device *s5pv210_dmacs[] __initdata = { | ||
158 | &s5pv210_device_pdma0, | ||
159 | &s5pv210_device_pdma1, | ||
160 | }; | ||
161 | |||
162 | static int __init s5pv210_dma_init(void) | ||
163 | { | ||
164 | platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs)); | ||
165 | |||
166 | return 0; | ||
167 | } | ||
168 | arch_initcall(s5pv210_dma_init); | ||
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c new file mode 100644 index 000000000000..9ea8972e023d --- /dev/null +++ b/arch/arm/mach-s5pv210/gpiolib.c | |||
@@ -0,0 +1,261 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/gpiolib.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PV210 - GPIOlib support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/irq.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/gpio.h> | ||
17 | #include <plat/gpio-core.h> | ||
18 | #include <plat/gpio-cfg.h> | ||
19 | #include <plat/gpio-cfg-helpers.h> | ||
20 | #include <mach/map.h> | ||
21 | |||
22 | static struct s3c_gpio_cfg gpio_cfg = { | ||
23 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
24 | .set_pull = s3c_gpio_setpull_updown, | ||
25 | .get_pull = s3c_gpio_getpull_updown, | ||
26 | }; | ||
27 | |||
28 | static struct s3c_gpio_cfg gpio_cfg_noint = { | ||
29 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
30 | .set_pull = s3c_gpio_setpull_updown, | ||
31 | .get_pull = s3c_gpio_getpull_updown, | ||
32 | }; | ||
33 | |||
34 | /* GPIO bank's base address given the index of the bank in the | ||
35 | * list of all gpio banks. | ||
36 | */ | ||
37 | #define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20)) | ||
38 | |||
39 | /* | ||
40 | * Following are the gpio banks in v210. | ||
41 | * | ||
42 | * The 'config' member when left to NULL, is initialized to the default | ||
43 | * structure gpio_cfg in the init function below. | ||
44 | * | ||
45 | * The 'base' member is also initialized in the init function below. | ||
46 | * Note: The initialization of 'base' member of s3c_gpio_chip structure | ||
47 | * uses the above macro and depends on the banks being listed in order here. | ||
48 | */ | ||
49 | static struct s3c_gpio_chip s5pv210_gpio_4bit[] = { | ||
50 | { | ||
51 | .chip = { | ||
52 | .base = S5PV210_GPA0(0), | ||
53 | .ngpio = S5PV210_GPIO_A0_NR, | ||
54 | .label = "GPA0", | ||
55 | }, | ||
56 | }, { | ||
57 | .chip = { | ||
58 | .base = S5PV210_GPA1(0), | ||
59 | .ngpio = S5PV210_GPIO_A1_NR, | ||
60 | .label = "GPA1", | ||
61 | }, | ||
62 | }, { | ||
63 | .chip = { | ||
64 | .base = S5PV210_GPB(0), | ||
65 | .ngpio = S5PV210_GPIO_B_NR, | ||
66 | .label = "GPB", | ||
67 | }, | ||
68 | }, { | ||
69 | .chip = { | ||
70 | .base = S5PV210_GPC0(0), | ||
71 | .ngpio = S5PV210_GPIO_C0_NR, | ||
72 | .label = "GPC0", | ||
73 | }, | ||
74 | }, { | ||
75 | .chip = { | ||
76 | .base = S5PV210_GPC1(0), | ||
77 | .ngpio = S5PV210_GPIO_C1_NR, | ||
78 | .label = "GPC1", | ||
79 | }, | ||
80 | }, { | ||
81 | .chip = { | ||
82 | .base = S5PV210_GPD0(0), | ||
83 | .ngpio = S5PV210_GPIO_D0_NR, | ||
84 | .label = "GPD0", | ||
85 | }, | ||
86 | }, { | ||
87 | .chip = { | ||
88 | .base = S5PV210_GPD1(0), | ||
89 | .ngpio = S5PV210_GPIO_D1_NR, | ||
90 | .label = "GPD1", | ||
91 | }, | ||
92 | }, { | ||
93 | .chip = { | ||
94 | .base = S5PV210_GPE0(0), | ||
95 | .ngpio = S5PV210_GPIO_E0_NR, | ||
96 | .label = "GPE0", | ||
97 | }, | ||
98 | }, { | ||
99 | .chip = { | ||
100 | .base = S5PV210_GPE1(0), | ||
101 | .ngpio = S5PV210_GPIO_E1_NR, | ||
102 | .label = "GPE1", | ||
103 | }, | ||
104 | }, { | ||
105 | .chip = { | ||
106 | .base = S5PV210_GPF0(0), | ||
107 | .ngpio = S5PV210_GPIO_F0_NR, | ||
108 | .label = "GPF0", | ||
109 | }, | ||
110 | }, { | ||
111 | .chip = { | ||
112 | .base = S5PV210_GPF1(0), | ||
113 | .ngpio = S5PV210_GPIO_F1_NR, | ||
114 | .label = "GPF1", | ||
115 | }, | ||
116 | }, { | ||
117 | .chip = { | ||
118 | .base = S5PV210_GPF2(0), | ||
119 | .ngpio = S5PV210_GPIO_F2_NR, | ||
120 | .label = "GPF2", | ||
121 | }, | ||
122 | }, { | ||
123 | .chip = { | ||
124 | .base = S5PV210_GPF3(0), | ||
125 | .ngpio = S5PV210_GPIO_F3_NR, | ||
126 | .label = "GPF3", | ||
127 | }, | ||
128 | }, { | ||
129 | .chip = { | ||
130 | .base = S5PV210_GPG0(0), | ||
131 | .ngpio = S5PV210_GPIO_G0_NR, | ||
132 | .label = "GPG0", | ||
133 | }, | ||
134 | }, { | ||
135 | .chip = { | ||
136 | .base = S5PV210_GPG1(0), | ||
137 | .ngpio = S5PV210_GPIO_G1_NR, | ||
138 | .label = "GPG1", | ||
139 | }, | ||
140 | }, { | ||
141 | .chip = { | ||
142 | .base = S5PV210_GPG2(0), | ||
143 | .ngpio = S5PV210_GPIO_G2_NR, | ||
144 | .label = "GPG2", | ||
145 | }, | ||
146 | }, { | ||
147 | .chip = { | ||
148 | .base = S5PV210_GPG3(0), | ||
149 | .ngpio = S5PV210_GPIO_G3_NR, | ||
150 | .label = "GPG3", | ||
151 | }, | ||
152 | }, { | ||
153 | .chip = { | ||
154 | .base = S5PV210_GPI(0), | ||
155 | .ngpio = S5PV210_GPIO_I_NR, | ||
156 | .label = "GPI", | ||
157 | }, | ||
158 | }, { | ||
159 | .chip = { | ||
160 | .base = S5PV210_GPJ0(0), | ||
161 | .ngpio = S5PV210_GPIO_J0_NR, | ||
162 | .label = "GPJ0", | ||
163 | }, | ||
164 | }, { | ||
165 | .chip = { | ||
166 | .base = S5PV210_GPJ1(0), | ||
167 | .ngpio = S5PV210_GPIO_J1_NR, | ||
168 | .label = "GPJ1", | ||
169 | }, | ||
170 | }, { | ||
171 | .chip = { | ||
172 | .base = S5PV210_GPJ2(0), | ||
173 | .ngpio = S5PV210_GPIO_J2_NR, | ||
174 | .label = "GPJ2", | ||
175 | }, | ||
176 | }, { | ||
177 | .chip = { | ||
178 | .base = S5PV210_GPJ3(0), | ||
179 | .ngpio = S5PV210_GPIO_J3_NR, | ||
180 | .label = "GPJ3", | ||
181 | }, | ||
182 | }, { | ||
183 | .chip = { | ||
184 | .base = S5PV210_GPJ4(0), | ||
185 | .ngpio = S5PV210_GPIO_J4_NR, | ||
186 | .label = "GPJ4", | ||
187 | }, | ||
188 | }, { | ||
189 | .config = &gpio_cfg_noint, | ||
190 | .chip = { | ||
191 | .base = S5PV210_MP01(0), | ||
192 | .ngpio = S5PV210_GPIO_MP01_NR, | ||
193 | .label = "MP01", | ||
194 | }, | ||
195 | }, { | ||
196 | .config = &gpio_cfg_noint, | ||
197 | .chip = { | ||
198 | .base = S5PV210_MP02(0), | ||
199 | .ngpio = S5PV210_GPIO_MP02_NR, | ||
200 | .label = "MP02", | ||
201 | }, | ||
202 | }, { | ||
203 | .config = &gpio_cfg_noint, | ||
204 | .chip = { | ||
205 | .base = S5PV210_MP03(0), | ||
206 | .ngpio = S5PV210_GPIO_MP03_NR, | ||
207 | .label = "MP03", | ||
208 | }, | ||
209 | }, { | ||
210 | .base = (S5P_VA_GPIO + 0xC00), | ||
211 | .config = &gpio_cfg_noint, | ||
212 | .chip = { | ||
213 | .base = S5PV210_GPH0(0), | ||
214 | .ngpio = S5PV210_GPIO_H0_NR, | ||
215 | .label = "GPH0", | ||
216 | }, | ||
217 | }, { | ||
218 | .base = (S5P_VA_GPIO + 0xC20), | ||
219 | .config = &gpio_cfg_noint, | ||
220 | .chip = { | ||
221 | .base = S5PV210_GPH1(0), | ||
222 | .ngpio = S5PV210_GPIO_H1_NR, | ||
223 | .label = "GPH1", | ||
224 | }, | ||
225 | }, { | ||
226 | .base = (S5P_VA_GPIO + 0xC40), | ||
227 | .config = &gpio_cfg_noint, | ||
228 | .chip = { | ||
229 | .base = S5PV210_GPH2(0), | ||
230 | .ngpio = S5PV210_GPIO_H2_NR, | ||
231 | .label = "GPH2", | ||
232 | }, | ||
233 | }, { | ||
234 | .base = (S5P_VA_GPIO + 0xC60), | ||
235 | .config = &gpio_cfg_noint, | ||
236 | .chip = { | ||
237 | .base = S5PV210_GPH3(0), | ||
238 | .ngpio = S5PV210_GPIO_H3_NR, | ||
239 | .label = "GPH3", | ||
240 | }, | ||
241 | }, | ||
242 | }; | ||
243 | |||
244 | static __init int s5pv210_gpiolib_init(void) | ||
245 | { | ||
246 | struct s3c_gpio_chip *chip = s5pv210_gpio_4bit; | ||
247 | int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit); | ||
248 | int i = 0; | ||
249 | |||
250 | for (i = 0; i < nr_chips; i++, chip++) { | ||
251 | if (chip->config == NULL) | ||
252 | chip->config = &gpio_cfg; | ||
253 | if (chip->base == NULL) | ||
254 | chip->base = S5PV210_BANK_BASE(i); | ||
255 | } | ||
256 | |||
257 | samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips); | ||
258 | |||
259 | return 0; | ||
260 | } | ||
261 | core_initcall(s5pv210_gpiolib_init); | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/dma.h b/arch/arm/mach-s5pv210/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/dma.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_DMA_H | ||
21 | #define __MACH_DMA_H | ||
22 | |||
23 | /* This platform uses the common S3C DMA API driver for PL330 */ | ||
24 | #include <plat/s3c-dma-pl330.h> | ||
25 | |||
26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h index 533b020e21e9..d6461ba2b71d 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h | |||
@@ -18,6 +18,8 @@ | |||
18 | #define gpio_cansleep __gpio_cansleep | 18 | #define gpio_cansleep __gpio_cansleep |
19 | #define gpio_to_irq __gpio_to_irq | 19 | #define gpio_to_irq __gpio_to_irq |
20 | 20 | ||
21 | /* Practically, GPIO banks upto MP03 are the configurable gpio banks */ | ||
22 | |||
21 | /* GPIO bank sizes */ | 23 | /* GPIO bank sizes */ |
22 | #define S5PV210_GPIO_A0_NR (8) | 24 | #define S5PV210_GPIO_A0_NR (8) |
23 | #define S5PV210_GPIO_A1_NR (4) | 25 | #define S5PV210_GPIO_A1_NR (4) |
@@ -47,6 +49,10 @@ | |||
47 | #define S5PV210_GPIO_J3_NR (8) | 49 | #define S5PV210_GPIO_J3_NR (8) |
48 | #define S5PV210_GPIO_J4_NR (5) | 50 | #define S5PV210_GPIO_J4_NR (5) |
49 | 51 | ||
52 | #define S5PV210_GPIO_MP01_NR (8) | ||
53 | #define S5PV210_GPIO_MP02_NR (4) | ||
54 | #define S5PV210_GPIO_MP03_NR (8) | ||
55 | |||
50 | /* GPIO bank numbers */ | 56 | /* GPIO bank numbers */ |
51 | 57 | ||
52 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | 58 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra |
@@ -85,6 +91,9 @@ enum s5p_gpio_number { | |||
85 | S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), | 91 | S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), |
86 | S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), | 92 | S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), |
87 | S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), | 93 | S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), |
94 | S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4), | ||
95 | S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01), | ||
96 | S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02), | ||
88 | }; | 97 | }; |
89 | 98 | ||
90 | /* S5PV210 GPIO number definitions */ | 99 | /* S5PV210 GPIO number definitions */ |
@@ -115,13 +124,16 @@ enum s5p_gpio_number { | |||
115 | #define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) | 124 | #define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) |
116 | #define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) | 125 | #define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) |
117 | #define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) | 126 | #define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) |
127 | #define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr)) | ||
128 | #define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr)) | ||
129 | #define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr)) | ||
118 | 130 | ||
119 | /* the end of the S5PV210 specific gpios */ | 131 | /* the end of the S5PV210 specific gpios */ |
120 | #define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1) | 132 | #define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1) |
121 | #define S3C_GPIO_END S5PV210_GPIO_END | 133 | #define S3C_GPIO_END S5PV210_GPIO_END |
122 | 134 | ||
123 | /* define the number of gpios we need to the one after the GPJ4() range */ | 135 | /* define the number of gpios we need to the one after the MP03() range */ |
124 | #define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \ | 136 | #define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \ |
125 | CONFIG_SAMSUNG_GPIO_EXTRA + 1) | 137 | CONFIG_SAMSUNG_GPIO_EXTRA + 1) |
126 | 138 | ||
127 | #include <asm-generic/gpio.h> | 139 | #include <asm-generic/gpio.h> |
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index c22694c8231f..5adcb9f26e44 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h | |||
@@ -43,6 +43,10 @@ | |||
43 | 43 | ||
44 | #define S5PV210_PA_SROMC (0xE8000000) | 44 | #define S5PV210_PA_SROMC (0xE8000000) |
45 | 45 | ||
46 | #define S5PV210_PA_MDMA 0xFA200000 | ||
47 | #define S5PV210_PA_PDMA0 0xE0900000 | ||
48 | #define S5PV210_PA_PDMA1 0xE0A00000 | ||
49 | |||
46 | #define S5PV210_PA_VIC0 (0xF2000000) | 50 | #define S5PV210_PA_VIC0 (0xF2000000) |
47 | #define S5P_PA_VIC0 S5PV210_PA_VIC0 | 51 | #define S5P_PA_VIC0 S5PV210_PA_VIC0 |
48 | 52 | ||
@@ -58,6 +62,19 @@ | |||
58 | #define S5PV210_PA_SDRAM (0x20000000) | 62 | #define S5PV210_PA_SDRAM (0x20000000) |
59 | #define S5P_PA_SDRAM S5PV210_PA_SDRAM | 63 | #define S5P_PA_SDRAM S5PV210_PA_SDRAM |
60 | 64 | ||
65 | /* I2S */ | ||
66 | #define S5PV210_PA_IIS0 0xEEE30000 | ||
67 | #define S5PV210_PA_IIS1 0xE2100000 | ||
68 | #define S5PV210_PA_IIS2 0xE2A00000 | ||
69 | |||
70 | /* PCM */ | ||
71 | #define S5PV210_PA_PCM0 0xE2300000 | ||
72 | #define S5PV210_PA_PCM1 0xE1200000 | ||
73 | #define S5PV210_PA_PCM2 0xE2B00000 | ||
74 | |||
75 | /* AC97 */ | ||
76 | #define S5PV210_PA_AC97 0xE2200000 | ||
77 | |||
61 | /* compatibiltiy defines. */ | 78 | /* compatibiltiy defines. */ |
62 | #define S3C_PA_UART S5PV210_PA_UART | 79 | #define S3C_PA_UART S5PV210_PA_UART |
63 | #define S3C_PA_IIC S5PV210_PA_IIC0 | 80 | #define S3C_PA_IIC S5PV210_PA_IIC0 |
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h index 69027fea987a..f8a9f1b330e0 100644 --- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h | |||
@@ -1,13 +1,14 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h | 1 | /* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h |
2 | * | 2 | * |
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Copyright 2008 Openmoko, Inc. | ||
3 | * Copyright 2008 Simtec Electronics | 7 | * Copyright 2008 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 8 | * Ben Dooks <ben@simtec.co.uk> |
5 | * http://armlinux.simtec.co.uk/ | 9 | * http://armlinux.simtec.co.uk/ |
6 | * | 10 | * |
7 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | 11 | * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h |
8 | * http://www.samsung.com/ | ||
9 | * | ||
10 | * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
11 | * | 12 | * |
12 | * S5PV210 - pwm clock and timer support | 13 | * S5PV210 - pwm clock and timer support |
13 | * | 14 | * |
@@ -21,14 +22,14 @@ | |||
21 | 22 | ||
22 | /** | 23 | /** |
23 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | 24 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk |
24 | * @cfg: The timer TCFG1 register bits shifted down to 0. | 25 | * @tcfg: The timer TCFG1 register bits shifted down to 0. |
25 | * | 26 | * |
26 | * Return true if the given configuration from TCFG1 is a TCLK instead | 27 | * Return true if the given configuration from TCFG1 is a TCLK instead |
27 | * any of the TDIV clocks. | 28 | * any of the TDIV clocks. |
28 | */ | 29 | */ |
29 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | 30 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) |
30 | { | 31 | { |
31 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | 32 | return tcfg == S3C64XX_TCFG1_MUX_TCLK; |
32 | } | 33 | } |
33 | 34 | ||
34 | /** | 35 | /** |
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | |||
40 | */ | 41 | */ |
41 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | 42 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) |
42 | { | 43 | { |
43 | return 1 << (1 + tcfg1); | 44 | return 1 << tcfg1; |
44 | } | 45 | } |
45 | 46 | ||
46 | /** | 47 | /** |
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | |||
50 | */ | 51 | */ |
51 | static inline unsigned int pwm_tdiv_has_div1(void) | 52 | static inline unsigned int pwm_tdiv_has_div1(void) |
52 | { | 53 | { |
53 | return 0; | 54 | return 1; |
54 | } | 55 | } |
55 | 56 | ||
56 | /** | 57 | /** |
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) | |||
61 | */ | 62 | */ |
62 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | 63 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) |
63 | { | 64 | { |
64 | return ilog2(div) - 1; | 65 | return ilog2(div); |
65 | } | 66 | } |
66 | 67 | ||
67 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | 68 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK |
68 | 69 | ||
69 | #endif /* __ASM_ARCH_PWMCLK_H */ | 70 | #endif /* __ASM_ARCH_PWMCLK_H */ |
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index ab4869df30c0..6f9fd3274e2e 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c | |||
@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { | |||
72 | }; | 72 | }; |
73 | 73 | ||
74 | static struct platform_device *smdkc110_devices[] __initdata = { | 74 | static struct platform_device *smdkc110_devices[] __initdata = { |
75 | &s5pv210_device_iis0, | ||
76 | &s5pv210_device_ac97, | ||
75 | }; | 77 | }; |
76 | 78 | ||
77 | static void __init smdkc110_map_io(void) | 79 | static void __init smdkc110_map_io(void) |
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index a27883253204..3c29e18528a5 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c | |||
@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { | |||
72 | }; | 72 | }; |
73 | 73 | ||
74 | static struct platform_device *smdkv210_devices[] __initdata = { | 74 | static struct platform_device *smdkv210_devices[] __initdata = { |
75 | &s5pv210_device_iis0, | ||
76 | &s5pv210_device_ac97, | ||
75 | }; | 77 | }; |
76 | 78 | ||
77 | static void __init smdkv210_map_io(void) | 79 | static void __init smdkv210_map_io(void) |
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c new file mode 100644 index 000000000000..9ec6845840e5 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c0.c | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * I2C0 GPIO configuration. | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <plat/iic.h> | ||
21 | |||
22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
23 | { | ||
24 | /* Will be populated later */ | ||
25 | } | ||
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index e7113d0b8168..285894171186 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
@@ -870,9 +870,10 @@ void __init reserve_node_zero(pg_data_t *pgdat) | |||
870 | if (machine_is_p720t()) | 870 | if (machine_is_p720t()) |
871 | res_size = 0x00014000; | 871 | res_size = 0x00014000; |
872 | 872 | ||
873 | /* H1940 and RX3715 need to reserve this for suspend */ | 873 | /* H1940, RX3715 and RX1950 need to reserve this for suspend */ |
874 | 874 | ||
875 | if (machine_is_h1940() || machine_is_rx3715()) { | 875 | if (machine_is_h1940() || machine_is_rx3715() |
876 | || machine_is_rx1950()) { | ||
876 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000, | 877 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000, |
877 | BOOTMEM_DEFAULT); | 878 | BOOTMEM_DEFAULT); |
878 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000, | 879 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000, |
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 3ce8f010b3c6..984bf66826d2 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
@@ -164,4 +164,9 @@ config S3C24XX_SIMTEC_AUDIO | |||
164 | help | 164 | help |
165 | Add audio devices for common Simtec S3C24XX boards | 165 | Add audio devices for common Simtec S3C24XX boards |
166 | 166 | ||
167 | config S3C2410_SETUP_TS | ||
168 | bool | ||
169 | help | ||
170 | Compile in platform device definition for Samsung TouchScreen. | ||
171 | |||
167 | endif | 172 | endif |
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 44aea8868f89..c2064c308719 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
@@ -38,6 +38,7 @@ obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o | |||
38 | 38 | ||
39 | # device specific setup and/or initialisation | 39 | # device specific setup and/or initialisation |
40 | obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o | 40 | obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o |
41 | obj-$(CONFIG_S3C2410_SETUP_TS) += setup-ts.o | ||
41 | 42 | ||
42 | # SPI gpio central GPIO functions | 43 | # SPI gpio central GPIO functions |
43 | 44 | ||
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 9265f09bfa58..58583732b29a 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/slab.h> | 23 | #include <linux/slab.h> |
24 | #include <linux/string.h> | ||
24 | 25 | ||
25 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
@@ -38,8 +39,7 @@ | |||
38 | #include <plat/devs.h> | 39 | #include <plat/devs.h> |
39 | #include <plat/cpu.h> | 40 | #include <plat/cpu.h> |
40 | #include <plat/regs-spi.h> | 41 | #include <plat/regs-spi.h> |
41 | 42 | #include <plat/ts.h> | |
42 | #include <mach/ts.h> | ||
43 | 43 | ||
44 | /* Serial port registrations */ | 44 | /* Serial port registrations */ |
45 | 45 | ||
@@ -149,10 +149,14 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) | |||
149 | { | 149 | { |
150 | struct s3c2410fb_mach_info *npd; | 150 | struct s3c2410fb_mach_info *npd; |
151 | 151 | ||
152 | npd = kmalloc(sizeof(*npd), GFP_KERNEL); | 152 | npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL); |
153 | if (npd) { | 153 | if (npd) { |
154 | memcpy(npd, pd, sizeof(*npd)); | ||
155 | s3c_device_lcd.dev.platform_data = npd; | 154 | s3c_device_lcd.dev.platform_data = npd; |
155 | npd->displays = kmemdup(pd->displays, | ||
156 | sizeof(struct s3c2410fb_display) * npd->num_displays, | ||
157 | GFP_KERNEL); | ||
158 | if (!npd->displays) | ||
159 | printk(KERN_ERR "no memory for LCD display data\n"); | ||
156 | } else { | 160 | } else { |
157 | printk(KERN_ERR "no memory for LCD platform data\n"); | 161 | printk(KERN_ERR "no memory for LCD platform data\n"); |
158 | } | 162 | } |
@@ -338,14 +342,6 @@ struct platform_device s3c_device_adc = { | |||
338 | .resource = s3c_adc_resource, | 342 | .resource = s3c_adc_resource, |
339 | }; | 343 | }; |
340 | 344 | ||
341 | /* HWMON */ | ||
342 | |||
343 | struct platform_device s3c_device_hwmon = { | ||
344 | .name = "s3c-hwmon", | ||
345 | .id = -1, | ||
346 | .dev.parent = &s3c_device_adc.dev, | ||
347 | }; | ||
348 | |||
349 | /* SDI */ | 345 | /* SDI */ |
350 | 346 | ||
351 | static struct resource s3c_sdi_resource[] = { | 347 | static struct resource s3c_sdi_resource[] = { |
@@ -371,7 +367,7 @@ struct platform_device s3c_device_sdi = { | |||
371 | 367 | ||
372 | EXPORT_SYMBOL(s3c_device_sdi); | 368 | EXPORT_SYMBOL(s3c_device_sdi); |
373 | 369 | ||
374 | void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) | 370 | void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) |
375 | { | 371 | { |
376 | struct s3c24xx_mci_pdata *npd; | 372 | struct s3c24xx_mci_pdata *npd; |
377 | 373 | ||
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 93827b3d4e84..6ad274e7593d 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
@@ -1104,7 +1104,7 @@ EXPORT_SYMBOL(s3c2410_dma_config); | |||
1104 | * devaddr: physical address of the source | 1104 | * devaddr: physical address of the source |
1105 | */ | 1105 | */ |
1106 | 1106 | ||
1107 | int s3c2410_dma_devconfig(int channel, | 1107 | int s3c2410_dma_devconfig(unsigned int channel, |
1108 | enum s3c2410_dmasrc source, | 1108 | enum s3c2410_dmasrc source, |
1109 | unsigned long devaddr) | 1109 | unsigned long devaddr) |
1110 | { | 1110 | { |
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c index 45126d3aafc6..2f3d7c089dfa 100644 --- a/arch/arm/plat-s3c24xx/gpio.c +++ b/arch/arm/plat-s3c24xx/gpio.c | |||
@@ -34,6 +34,8 @@ | |||
34 | 34 | ||
35 | #include <mach/regs-gpio.h> | 35 | #include <mach/regs-gpio.h> |
36 | 36 | ||
37 | #include <plat/gpio-core.h> | ||
38 | |||
37 | /* gpiolib wrappers until these are totally eliminated */ | 39 | /* gpiolib wrappers until these are totally eliminated */ |
38 | 40 | ||
39 | void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) | 41 | void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) |
@@ -68,10 +70,10 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin); | |||
68 | 70 | ||
69 | unsigned int s3c2410_gpio_getpin(unsigned int pin) | 71 | unsigned int s3c2410_gpio_getpin(unsigned int pin) |
70 | { | 72 | { |
71 | void __iomem *base = S3C24XX_GPIO_BASE(pin); | 73 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); |
72 | unsigned long offs = S3C2410_GPIO_OFFSET(pin); | 74 | unsigned long offs = pin - chip->chip.base; |
73 | 75 | ||
74 | return __raw_readl(base + 0x04) & (1<< offs); | 76 | return __raw_readl(chip->base + 0x04) & (1<< offs); |
75 | } | 77 | } |
76 | 78 | ||
77 | EXPORT_SYMBOL(s3c2410_gpio_getpin); | 79 | EXPORT_SYMBOL(s3c2410_gpio_getpin); |
diff --git a/arch/arm/plat-s3c24xx/setup-ts.c b/arch/arm/plat-s3c24xx/setup-ts.c new file mode 100644 index 000000000000..ed2638663675 --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-ts.c | |||
@@ -0,0 +1,34 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/setup-ts.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Based on S3C24XX setup for i2c device | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/gpio.h> | ||
15 | |||
16 | struct platform_device; /* don't need the contents */ | ||
17 | |||
18 | #include <mach/hardware.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | /** | ||
22 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems | ||
23 | * | ||
24 | * Configure the GPIO for the S3C2410 system, where we have external FETs | ||
25 | * connected to the device (later systems such as the S3C2440 integrate | ||
26 | * these into the device). | ||
27 | */ | ||
28 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) | ||
29 | { | ||
30 | s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); | ||
31 | s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); | ||
33 | s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); | ||
34 | } | ||
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index d400a6a20fe4..92bd75607b43 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig | |||
@@ -13,6 +13,7 @@ config PLAT_S5P | |||
13 | select NO_IOPORT | 13 | select NO_IOPORT |
14 | select ARCH_REQUIRE_GPIOLIB | 14 | select ARCH_REQUIRE_GPIOLIB |
15 | select S3C_GPIO_TRACK | 15 | select S3C_GPIO_TRACK |
16 | select S5P_GPIO_DRVSTR | ||
16 | select SAMSUNG_GPIOLIB_4BIT | 17 | select SAMSUNG_GPIOLIB_4BIT |
17 | select S3C_GPIO_CFG_S3C64XX | 18 | select S3C_GPIO_CFG_S3C64XX |
18 | select S3C_GPIO_PULL_UPDOWN | 19 | select S3C_GPIO_PULL_UPDOWN |
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index a7c54b332d27..0ec09a9c36bd 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile | |||
@@ -16,4 +16,3 @@ obj-y += dev-uart.o | |||
16 | obj-y += cpu.o | 16 | obj-y += cpu.o |
17 | obj-y += clock.o | 17 | obj-y += clock.o |
18 | obj-y += irq.o | 18 | obj-y += irq.o |
19 | obj-y += setup-i2c0.o | ||
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c index aa96e335073b..24a931fd8d3b 100644 --- a/arch/arm/plat-s5p/clock.c +++ b/arch/arm/plat-s5p/clock.c | |||
@@ -33,7 +33,12 @@ struct clk clk_ext_xtal_mux = { | |||
33 | .id = -1, | 33 | .id = -1, |
34 | }; | 34 | }; |
35 | 35 | ||
36 | static struct clk s5p_clk_27m = { | 36 | struct clk clk_xusbxti = { |
37 | .name = "xusbxti", | ||
38 | .id = -1, | ||
39 | }; | ||
40 | |||
41 | struct clk s5p_clk_27m = { | ||
37 | .name = "clk_27m", | 42 | .name = "clk_27m", |
38 | .id = -1, | 43 | .id = -1, |
39 | .rate = 27000000, | 44 | .rate = 27000000, |
@@ -69,6 +74,13 @@ struct clk clk_fout_epll = { | |||
69 | .ctrlbit = (1 << 31), | 74 | .ctrlbit = (1 << 31), |
70 | }; | 75 | }; |
71 | 76 | ||
77 | /* VPLL clock output */ | ||
78 | struct clk clk_fout_vpll = { | ||
79 | .name = "fout_vpll", | ||
80 | .id = -1, | ||
81 | .ctrlbit = (1 << 31), | ||
82 | }; | ||
83 | |||
72 | /* ARM clock */ | 84 | /* ARM clock */ |
73 | struct clk clk_arm = { | 85 | struct clk clk_arm = { |
74 | .name = "armclk", | 86 | .name = "armclk", |
@@ -133,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = { | |||
133 | &clk_fout_apll, | 145 | &clk_fout_apll, |
134 | &clk_fout_mpll, | 146 | &clk_fout_mpll, |
135 | &clk_fout_epll, | 147 | &clk_fout_epll, |
148 | &clk_fout_vpll, | ||
136 | &clk_arm, | 149 | &clk_arm, |
137 | &clk_vpll, | 150 | &clk_vpll, |
138 | }; | 151 | }; |
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h index 42e757f2e40c..9ff3d718be39 100644 --- a/arch/arm/plat-s5p/include/plat/irqs.h +++ b/arch/arm/plat-s5p/include/plat/irqs.h | |||
@@ -79,7 +79,7 @@ | |||
79 | #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) | 79 | #define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) |
80 | #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) | 80 | #define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) |
81 | 81 | ||
82 | #define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) | 82 | #define S5P_TIMER_IRQ(x) (11 + (x)) |
83 | 83 | ||
84 | #define IRQ_TIMER0 S5P_TIMER_IRQ(0) | 84 | #define IRQ_TIMER0 S5P_TIMER_IRQ(0) |
85 | #define IRQ_TIMER1 S5P_TIMER_IRQ(1) | 85 | #define IRQ_TIMER1 S5P_TIMER_IRQ(1) |
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h index d48325bb29e2..7db322726bc2 100644 --- a/arch/arm/plat-s5p/include/plat/pll.h +++ b/arch/arm/plat-s5p/include/plat/pll.h | |||
@@ -81,3 +81,25 @@ static inline unsigned long s5p_get_pll90xx(unsigned long baseclk, | |||
81 | 81 | ||
82 | return result; | 82 | return result; |
83 | } | 83 | } |
84 | |||
85 | #define PLL65XX_MDIV_MASK (0x3FF) | ||
86 | #define PLL65XX_PDIV_MASK (0x3F) | ||
87 | #define PLL65XX_SDIV_MASK (0x7) | ||
88 | #define PLL65XX_MDIV_SHIFT (16) | ||
89 | #define PLL65XX_PDIV_SHIFT (8) | ||
90 | #define PLL65XX_SDIV_SHIFT (0) | ||
91 | |||
92 | static inline unsigned long s5p_get_pll65xx(unsigned long baseclk, u32 pll_con) | ||
93 | { | ||
94 | u32 mdiv, pdiv, sdiv; | ||
95 | u64 fvco = baseclk; | ||
96 | |||
97 | mdiv = (pll_con >> PLL65XX_MDIV_SHIFT) & PLL65XX_MDIV_MASK; | ||
98 | pdiv = (pll_con >> PLL65XX_PDIV_SHIFT) & PLL65XX_PDIV_MASK; | ||
99 | sdiv = (pll_con >> PLL65XX_SDIV_SHIFT) & PLL65XX_SDIV_MASK; | ||
100 | |||
101 | fvco *= mdiv; | ||
102 | do_div(fvco, (pdiv << sdiv)); | ||
103 | |||
104 | return (unsigned long)fvco; | ||
105 | } | ||
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h index 56fb8b414d41..09418b1101fe 100644 --- a/arch/arm/plat-s5p/include/plat/s5p-clock.h +++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h | |||
@@ -21,12 +21,16 @@ | |||
21 | #define clk_fin_mpll clk_ext_xtal_mux | 21 | #define clk_fin_mpll clk_ext_xtal_mux |
22 | #define clk_fin_epll clk_ext_xtal_mux | 22 | #define clk_fin_epll clk_ext_xtal_mux |
23 | #define clk_fin_vpll clk_ext_xtal_mux | 23 | #define clk_fin_vpll clk_ext_xtal_mux |
24 | #define clk_fin_hpll clk_ext_xtal_mux | ||
24 | 25 | ||
25 | extern struct clk clk_ext_xtal_mux; | 26 | extern struct clk clk_ext_xtal_mux; |
27 | extern struct clk clk_xusbxti; | ||
26 | extern struct clk clk_48m; | 28 | extern struct clk clk_48m; |
29 | extern struct clk s5p_clk_27m; | ||
27 | extern struct clk clk_fout_apll; | 30 | extern struct clk clk_fout_apll; |
28 | extern struct clk clk_fout_mpll; | 31 | extern struct clk clk_fout_mpll; |
29 | extern struct clk clk_fout_epll; | 32 | extern struct clk clk_fout_epll; |
33 | extern struct clk clk_fout_vpll; | ||
30 | extern struct clk clk_arm; | 34 | extern struct clk clk_arm; |
31 | extern struct clk clk_vpll; | 35 | extern struct clk clk_vpll; |
32 | 36 | ||
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig index c7ccdf22eefa..c7bd2bbda239 100644 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ b/arch/arm/plat-s5pc1xx/Kconfig | |||
@@ -16,9 +16,10 @@ config PLAT_S5PC1XX | |||
16 | select SAMSUNG_IRQ_VIC_TIMER | 16 | select SAMSUNG_IRQ_VIC_TIMER |
17 | select S3C_GPIO_TRACK | 17 | select S3C_GPIO_TRACK |
18 | select S3C_GPIO_PULL_UPDOWN | 18 | select S3C_GPIO_PULL_UPDOWN |
19 | select S5P_GPIO_DRVSTR | ||
19 | select S3C_GPIO_CFG_S3C24XX | 20 | select S3C_GPIO_CFG_S3C24XX |
20 | select S3C_GPIO_CFG_S3C64XX | 21 | select S3C_GPIO_CFG_S3C64XX |
21 | select S5P_GPIO_CFG_S5PC1XX | 22 | select SAMSUNG_GPIOLIB_4BIT |
22 | help | 23 | help |
23 | Base platform code for any Samsung S5PC1XX device | 24 | Base platform code for any Samsung S5PC1XX device |
24 | 25 | ||
@@ -38,25 +39,6 @@ config CPU_S5PC100_CLOCK | |||
38 | 39 | ||
39 | # platform specific device setup | 40 | # platform specific device setup |
40 | 41 | ||
41 | config S5PC1XX_SETUP_FB_24BPP | ||
42 | bool | ||
43 | help | ||
44 | Common setup code for S5PC1XX with an 24bpp RGB display helper. | ||
45 | |||
46 | config S5PC1XX_SETUP_I2C0 | ||
47 | bool | ||
48 | default y | ||
49 | help | ||
50 | Common setup code for i2c bus 0. | ||
51 | |||
52 | Note, currently since i2c0 is always compiled, this setup helper | ||
53 | is always compiled with it. | ||
54 | |||
55 | config S5PC1XX_SETUP_I2C1 | ||
56 | bool | ||
57 | help | ||
58 | Common setup code for i2c bus 1. | ||
59 | |||
60 | config S5PC1XX_SETUP_SDHCI_GPIO | 42 | config S5PC1XX_SETUP_SDHCI_GPIO |
61 | bool | 43 | bool |
62 | help | 44 | help |
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile index 278f26806089..9ce6409a9e02 100644 --- a/arch/arm/plat-s5pc1xx/Makefile +++ b/arch/arm/plat-s5pc1xx/Makefile | |||
@@ -13,9 +13,8 @@ obj- := | |||
13 | 13 | ||
14 | obj-y += dev-uart.o | 14 | obj-y += dev-uart.o |
15 | obj-y += cpu.o | 15 | obj-y += cpu.o |
16 | obj-y += irq.o irq-gpio.o irq-eint.o | 16 | obj-y += irq.o |
17 | obj-y += clock.o | 17 | obj-y += clock.o |
18 | obj-y += gpiolib.o | ||
19 | 18 | ||
20 | # CPU support | 19 | # CPU support |
21 | 20 | ||
@@ -24,8 +23,4 @@ obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o | |||
24 | 23 | ||
25 | # Device setup | 24 | # Device setup |
26 | 25 | ||
27 | obj-$(CONFIG_S5P_GPIO_CFG_S5PC1XX) += gpio-config.o | ||
28 | obj-$(CONFIG_S5PC1XX_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
29 | obj-$(CONFIG_S5PC1XX_SETUP_I2C0) += setup-i2c0.o | ||
30 | obj-$(CONFIG_S5PC1XX_SETUP_I2C1) += setup-i2c1.o | ||
31 | obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | 26 | obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o |
diff --git a/arch/arm/plat-s5pc1xx/gpio-config.c b/arch/arm/plat-s5pc1xx/gpio-config.c deleted file mode 100644 index a4f67e80a150..000000000000 --- a/arch/arm/plat-s5pc1xx/gpio-config.c +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/gpio-config.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics | ||
4 | * | ||
5 | * S5PC1XX GPIO Configuration. | ||
6 | * | ||
7 | * Based on plat-s3c64xx/gpio-config.c | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/gpio.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <plat/gpio-core.h> | ||
20 | #include <plat/gpio-cfg-s5pc1xx.h> | ||
21 | |||
22 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off) | ||
23 | { | ||
24 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
25 | void __iomem *reg; | ||
26 | int shift = off * 2; | ||
27 | u32 drvstr; | ||
28 | |||
29 | if (!chip) | ||
30 | return -EINVAL; | ||
31 | |||
32 | reg = chip->base + 0x0C; | ||
33 | |||
34 | drvstr = __raw_readl(reg); | ||
35 | drvstr = 0xffff & (0x3 << shift); | ||
36 | drvstr = drvstr >> shift; | ||
37 | |||
38 | return (__force s5p_gpio_drvstr_t)drvstr; | ||
39 | } | ||
40 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | ||
41 | |||
42 | int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, | ||
43 | s5p_gpio_drvstr_t drvstr) | ||
44 | { | ||
45 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
46 | void __iomem *reg; | ||
47 | int shift = off * 2; | ||
48 | u32 tmp; | ||
49 | |||
50 | if (!chip) | ||
51 | return -EINVAL; | ||
52 | |||
53 | reg = chip->base + 0x0C; | ||
54 | |||
55 | tmp = __raw_readl(reg); | ||
56 | tmp |= drvstr << shift; | ||
57 | |||
58 | __raw_writel(tmp, reg); | ||
59 | |||
60 | return 0; | ||
61 | } | ||
62 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h deleted file mode 100644 index 72ad59f61efc..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg-s5pc1xx.h +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-cfg.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronic | ||
4 | * | ||
5 | * S5PC1XX Platform - GPIO pin configuration | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | /* This file contains the necessary definitions to get the basic gpio | ||
13 | * pin configuration done such as setting a pin to input or output or | ||
14 | * changing the pull-{up,down} configurations. | ||
15 | */ | ||
16 | |||
17 | #ifndef __GPIO_CFG_S5PC1XX_H | ||
18 | #define __GPIO_CFG_S5PC1XX_H __FILE__ | ||
19 | |||
20 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; | ||
21 | |||
22 | #define S5P_GPIO_DRVSTR_LV1 0x00 | ||
23 | #define S5P_GPIO_DRVSTR_LV2 0x01 | ||
24 | #define S5P_GPIO_DRVSTR_LV3 0x10 | ||
25 | #define S5P_GPIO_DRVSTR_LV4 0x11 | ||
26 | |||
27 | extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin, unsigned int off); | ||
28 | |||
29 | extern int s5p_gpio_set_drvstr(unsigned int pin, unsigned int off, | ||
30 | s5p_gpio_drvstr_t drvstr); | ||
31 | |||
32 | #endif /* __GPIO_CFG_S5PC1XX_H */ | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index d552c65fa1b0..229919e9744c 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -90,12 +90,6 @@ config S3C_GPIO_CFG_S3C64XX | |||
90 | Internal configuration to enable S3C64XX style GPIO configuration | 90 | Internal configuration to enable S3C64XX style GPIO configuration |
91 | functions. | 91 | functions. |
92 | 92 | ||
93 | config S5P_GPIO_CFG_S5PC1XX | ||
94 | bool | ||
95 | help | ||
96 | Internal configuration to enable S5PC1XX style GPIO configuration | ||
97 | functions. | ||
98 | |||
99 | config S3C_GPIO_PULL_UPDOWN | 93 | config S3C_GPIO_PULL_UPDOWN |
100 | bool | 94 | bool |
101 | help | 95 | help |
@@ -111,6 +105,12 @@ config S3C_GPIO_PULL_UP | |||
111 | help | 105 | help |
112 | Internal configuration to enable the correct GPIO pull helper | 106 | Internal configuration to enable the correct GPIO pull helper |
113 | 107 | ||
108 | config S5P_GPIO_DRVSTR | ||
109 | bool | ||
110 | help | ||
111 | Internal configuration to get and set correct GPIO driver strength | ||
112 | helper | ||
113 | |||
114 | config SAMSUNG_GPIO_EXTRA | 114 | config SAMSUNG_GPIO_EXTRA |
115 | int "Number of additional GPIO pins" | 115 | int "Number of additional GPIO pins" |
116 | default 0 | 116 | default 0 |
@@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2 | |||
160 | help | 160 | help |
161 | Compile in platform device definitions for HSMMC channel 2 | 161 | Compile in platform device definitions for HSMMC channel 2 |
162 | 162 | ||
163 | config S3C_DEV_HWMON | ||
164 | bool | ||
165 | help | ||
166 | Compile in platform device definitions for HWMON | ||
167 | |||
163 | config S3C_DEV_I2C1 | 168 | config S3C_DEV_I2C1 |
164 | bool | 169 | bool |
165 | help | 170 | help |
@@ -185,12 +190,27 @@ config S3C_DEV_NAND | |||
185 | help | 190 | help |
186 | Compile in platform device definition for NAND controller | 191 | Compile in platform device definition for NAND controller |
187 | 192 | ||
193 | config S3C_DEV_RTC | ||
194 | bool | ||
195 | help | ||
196 | Complie in platform device definition for RTC | ||
197 | |||
198 | config SAMSUNG_DEV_ADC | ||
199 | bool | ||
200 | help | ||
201 | Compile in platform device definition for ADC controller | ||
202 | |||
188 | config S3C64XX_DEV_SPI | 203 | config S3C64XX_DEV_SPI |
189 | bool | 204 | bool |
190 | help | 205 | help |
191 | Compile in platform device definitions for S3C64XX's type | 206 | Compile in platform device definitions for S3C64XX's type |
192 | SPI controllers. | 207 | SPI controllers. |
193 | 208 | ||
209 | config SAMSUNG_DEV_TS | ||
210 | bool | ||
211 | help | ||
212 | Common in platform device definitions for touchscreen device | ||
213 | |||
194 | # DMA | 214 | # DMA |
195 | 215 | ||
196 | config S3C_DMA | 216 | config S3C_DMA |
@@ -198,6 +218,12 @@ config S3C_DMA | |||
198 | help | 218 | help |
199 | Internal configuration for S3C DMA core | 219 | Internal configuration for S3C DMA core |
200 | 220 | ||
221 | config S3C_PL330_DMA | ||
222 | bool | ||
223 | select PL330 | ||
224 | help | ||
225 | S3C DMA API Driver for PL330 DMAC. | ||
226 | |||
201 | comment "Power management" | 227 | comment "Power management" |
202 | 228 | ||
203 | config SAMSUNG_PM_DEBUG | 229 | config SAMSUNG_PM_DEBUG |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 22c89d08f6e5..48288499a3b9 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o | |||
33 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | 33 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o |
34 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | 34 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o |
35 | obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o | 35 | obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o |
36 | obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o | ||
36 | obj-y += dev-i2c0.o | 37 | obj-y += dev-i2c0.o |
37 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | 38 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
38 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | 39 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
@@ -40,11 +41,17 @@ obj-y += dev-uart.o | |||
40 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | 41 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o |
41 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | 42 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o |
42 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o | 43 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o |
44 | obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o | ||
45 | |||
46 | obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o | ||
47 | obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o | ||
43 | 48 | ||
44 | # DMA support | 49 | # DMA support |
45 | 50 | ||
46 | obj-$(CONFIG_S3C_DMA) += dma.o | 51 | obj-$(CONFIG_S3C_DMA) += dma.o |
47 | 52 | ||
53 | obj-$(CONFIG_S3C_PL330_DMA) += s3c-pl330.o | ||
54 | |||
48 | # PM support | 55 | # PM support |
49 | 56 | ||
50 | obj-$(CONFIG_PM) += pm.o | 57 | obj-$(CONFIG_PM) += pm.o |
diff --git a/arch/arm/mach-s3c64xx/dev-adc.c b/arch/arm/plat-samsung/dev-adc.c index fafef9b6bcfa..9d903d4095ed 100644 --- a/arch/arm/mach-s3c64xx/dev-adc.c +++ b/arch/arm/plat-samsung/dev-adc.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/dev-adc.c | 1 | /* linux/arch/arm/plat-samsung/dev-adc.c |
2 | * | 2 | * |
3 | * Copyright 2010 Maurus Cuelenaere | 3 | * Copyright 2010 Maurus Cuelenaere |
4 | * | 4 | * |
@@ -22,8 +22,8 @@ | |||
22 | 22 | ||
23 | static struct resource s3c_adc_resource[] = { | 23 | static struct resource s3c_adc_resource[] = { |
24 | [0] = { | 24 | [0] = { |
25 | .start = S3C64XX_PA_ADC, | 25 | .start = SAMSUNG_PA_ADC, |
26 | .end = S3C64XX_PA_ADC + SZ_256 - 1, | 26 | .end = SAMSUNG_PA_ADC + SZ_256 - 1, |
27 | .flags = IORESOURCE_MEM, | 27 | .flags = IORESOURCE_MEM, |
28 | }, | 28 | }, |
29 | [1] = { | 29 | [1] = { |
@@ -39,7 +39,7 @@ static struct resource s3c_adc_resource[] = { | |||
39 | }; | 39 | }; |
40 | 40 | ||
41 | struct platform_device s3c_device_adc = { | 41 | struct platform_device s3c_device_adc = { |
42 | .name = "s3c64xx-adc", | 42 | .name = "samsung-adc", |
43 | .id = -1, | 43 | .id = -1, |
44 | .num_resources = ARRAY_SIZE(s3c_adc_resource), | 44 | .num_resources = ARRAY_SIZE(s3c_adc_resource), |
45 | .resource = s3c_adc_resource, | 45 | .resource = s3c_adc_resource, |
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c index 002a15f313f3..bf60204c6297 100644 --- a/arch/arm/plat-samsung/dev-fb.c +++ b/arch/arm/plat-samsung/dev-fb.c | |||
@@ -19,7 +19,6 @@ | |||
19 | 19 | ||
20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
21 | #include <mach/map.h> | 21 | #include <mach/map.h> |
22 | #include <mach/regs-fb.h> | ||
23 | 22 | ||
24 | #include <plat/fb.h> | 23 | #include <plat/fb.h> |
25 | #include <plat/devs.h> | 24 | #include <plat/devs.h> |
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c new file mode 100644 index 000000000000..b3ffb9587250 --- /dev/null +++ b/arch/arm/plat-samsung/dev-hwmon.c | |||
@@ -0,0 +1,42 @@ | |||
1 | /* linux/arch/arm/plat-samsung/dev-hwmon.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * Adapted for HWMON by Maurus Cuelenaere | ||
8 | * | ||
9 | * Samsung series device definition for HWMON | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | |||
19 | #include <plat/devs.h> | ||
20 | #include <plat/hwmon.h> | ||
21 | |||
22 | struct platform_device s3c_device_hwmon = { | ||
23 | .name = "s3c-hwmon", | ||
24 | .id = -1, | ||
25 | .dev.parent = &s3c_device_adc.dev, | ||
26 | }; | ||
27 | |||
28 | void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd) | ||
29 | { | ||
30 | struct s3c_hwmon_pdata *npd; | ||
31 | |||
32 | if (!pd) { | ||
33 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
34 | return; | ||
35 | } | ||
36 | |||
37 | npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL); | ||
38 | if (!npd) | ||
39 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
40 | |||
41 | s3c_device_hwmon.dev.platform_data = npd; | ||
42 | } | ||
diff --git a/arch/arm/mach-s3c64xx/dev-rtc.c b/arch/arm/plat-samsung/dev-rtc.c index b9e7a05f0129..bf4e2267333c 100644 --- a/arch/arm/mach-s3c64xx/dev-rtc.c +++ b/arch/arm/plat-samsung/dev-rtc.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/dev-rtc.c | 1 | /* linux/arch/arm/plat-samsung/dev-rtc.c |
2 | * | 2 | * |
3 | * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com> | 3 | * Copyright 2009 by Maurus Cuelenaere <mcuelenaere@gmail.com> |
4 | * | 4 | * |
@@ -18,26 +18,26 @@ | |||
18 | 18 | ||
19 | static struct resource s3c_rtc_resource[] = { | 19 | static struct resource s3c_rtc_resource[] = { |
20 | [0] = { | 20 | [0] = { |
21 | .start = S3C64XX_PA_RTC, | 21 | .start = S3C_PA_RTC, |
22 | .end = S3C64XX_PA_RTC + 0xff, | 22 | .end = S3C_PA_RTC + 0xff, |
23 | .flags = IORESOURCE_MEM, | 23 | .flags = IORESOURCE_MEM, |
24 | }, | 24 | }, |
25 | [1] = { | 25 | [1] = { |
26 | .start = IRQ_RTC_ALARM, | 26 | .start = IRQ_RTC_ALARM, |
27 | .end = IRQ_RTC_ALARM, | 27 | .end = IRQ_RTC_ALARM, |
28 | .flags = IORESOURCE_IRQ, | 28 | .flags = IORESOURCE_IRQ, |
29 | }, | 29 | }, |
30 | [2] = { | 30 | [2] = { |
31 | .start = IRQ_RTC_TIC, | 31 | .start = IRQ_RTC_TIC, |
32 | .end = IRQ_RTC_TIC, | 32 | .end = IRQ_RTC_TIC, |
33 | .flags = IORESOURCE_IRQ | 33 | .flags = IORESOURCE_IRQ |
34 | } | 34 | } |
35 | }; | 35 | }; |
36 | 36 | ||
37 | struct platform_device s3c_device_rtc = { | 37 | struct platform_device s3c_device_rtc = { |
38 | .name = "s3c64xx-rtc", | 38 | .name = "s3c64xx-rtc", |
39 | .id = -1, | 39 | .id = -1, |
40 | .num_resources = ARRAY_SIZE(s3c_rtc_resource), | 40 | .num_resources = ARRAY_SIZE(s3c_rtc_resource), |
41 | .resource = s3c_rtc_resource, | 41 | .resource = s3c_rtc_resource, |
42 | }; | 42 | }; |
43 | EXPORT_SYMBOL(s3c_device_rtc); | 43 | EXPORT_SYMBOL(s3c_device_rtc); |
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c new file mode 100644 index 000000000000..236ef8427d7d --- /dev/null +++ b/arch/arm/plat-samsung/dev-ts.c | |||
@@ -0,0 +1,61 @@ | |||
1 | /* linux/arch/arm/mach-s3c64xx/dev-ts.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | ||
6 | * | ||
7 | * Adapted by Maurus Cuelenaere for s3c64xx | ||
8 | * | ||
9 | * S3C64XX series device definition for touchscreen device | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/string.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | |||
20 | #include <mach/irqs.h> | ||
21 | #include <mach/map.h> | ||
22 | |||
23 | #include <plat/devs.h> | ||
24 | #include <plat/ts.h> | ||
25 | |||
26 | static struct resource s3c_ts_resource[] = { | ||
27 | [0] = { | ||
28 | .start = SAMSUNG_PA_ADC, | ||
29 | .end = SAMSUNG_PA_ADC + SZ_256 - 1, | ||
30 | .flags = IORESOURCE_MEM, | ||
31 | }, | ||
32 | [1] = { | ||
33 | .start = IRQ_TC, | ||
34 | .end = IRQ_TC, | ||
35 | .flags = IORESOURCE_IRQ, | ||
36 | }, | ||
37 | }; | ||
38 | |||
39 | struct platform_device s3c_device_ts = { | ||
40 | .name = "s3c64xx-ts", | ||
41 | .id = -1, | ||
42 | .num_resources = ARRAY_SIZE(s3c_ts_resource), | ||
43 | .resource = s3c_ts_resource, | ||
44 | }; | ||
45 | |||
46 | void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd) | ||
47 | { | ||
48 | struct s3c2410_ts_mach_info *npd; | ||
49 | |||
50 | if (!pd) { | ||
51 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
52 | return; | ||
53 | } | ||
54 | |||
55 | npd = kmemdup(pd, sizeof(struct s3c2410_ts_mach_info), GFP_KERNEL); | ||
56 | if (!npd) | ||
57 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
58 | |||
59 | s3c_device_ts.dev.platform_data = npd; | ||
60 | } | ||
61 | EXPORT_SYMBOL(s3c24xx_ts_set_platdata); | ||
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c index 3282db360fa8..57b68a50f45e 100644 --- a/arch/arm/plat-samsung/gpio-config.c +++ b/arch/arm/plat-samsung/gpio-config.c | |||
@@ -33,9 +33,9 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) | |||
33 | 33 | ||
34 | offset = pin - chip->chip.base; | 34 | offset = pin - chip->chip.base; |
35 | 35 | ||
36 | local_irq_save(flags); | 36 | s3c_gpio_lock(chip, flags); |
37 | ret = s3c_gpio_do_setcfg(chip, offset, config); | 37 | ret = s3c_gpio_do_setcfg(chip, offset, config); |
38 | local_irq_restore(flags); | 38 | s3c_gpio_unlock(chip, flags); |
39 | 39 | ||
40 | return ret; | 40 | return ret; |
41 | } | 41 | } |
@@ -51,9 +51,9 @@ unsigned s3c_gpio_getcfg(unsigned int pin) | |||
51 | if (chip) { | 51 | if (chip) { |
52 | offset = pin - chip->chip.base; | 52 | offset = pin - chip->chip.base; |
53 | 53 | ||
54 | local_irq_save(flags); | 54 | s3c_gpio_lock(chip, flags); |
55 | ret = s3c_gpio_do_getcfg(chip, offset); | 55 | ret = s3c_gpio_do_getcfg(chip, offset); |
56 | local_irq_restore(flags); | 56 | s3c_gpio_unlock(chip, flags); |
57 | } | 57 | } |
58 | 58 | ||
59 | return ret; | 59 | return ret; |
@@ -72,9 +72,9 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) | |||
72 | 72 | ||
73 | offset = pin - chip->chip.base; | 73 | offset = pin - chip->chip.base; |
74 | 74 | ||
75 | local_irq_save(flags); | 75 | s3c_gpio_lock(chip, flags); |
76 | ret = s3c_gpio_do_setpull(chip, offset, pull); | 76 | ret = s3c_gpio_do_setpull(chip, offset, pull); |
77 | local_irq_restore(flags); | 77 | s3c_gpio_unlock(chip, flags); |
78 | 78 | ||
79 | return ret; | 79 | return ret; |
80 | } | 80 | } |
@@ -261,3 +261,51 @@ s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, | |||
261 | } | 261 | } |
262 | #endif /* CONFIG_S3C_GPIO_PULL_UP */ | 262 | #endif /* CONFIG_S3C_GPIO_PULL_UP */ |
263 | 263 | ||
264 | #ifdef CONFIG_S5P_GPIO_DRVSTR | ||
265 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) | ||
266 | { | ||
267 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
268 | unsigned int off; | ||
269 | void __iomem *reg; | ||
270 | int shift; | ||
271 | u32 drvstr; | ||
272 | |||
273 | if (!chip) | ||
274 | return -EINVAL; | ||
275 | |||
276 | off = chip->chip.base - pin; | ||
277 | shift = off * 2; | ||
278 | reg = chip->base + 0x0C; | ||
279 | |||
280 | drvstr = __raw_readl(reg); | ||
281 | drvstr = 0xffff & (0x3 << shift); | ||
282 | drvstr = drvstr >> shift; | ||
283 | |||
284 | return (__force s5p_gpio_drvstr_t)drvstr; | ||
285 | } | ||
286 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | ||
287 | |||
288 | int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) | ||
289 | { | ||
290 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
291 | unsigned int off; | ||
292 | void __iomem *reg; | ||
293 | int shift; | ||
294 | u32 tmp; | ||
295 | |||
296 | if (!chip) | ||
297 | return -EINVAL; | ||
298 | |||
299 | off = chip->chip.base - pin; | ||
300 | shift = off * 2; | ||
301 | reg = chip->base + 0x0C; | ||
302 | |||
303 | tmp = __raw_readl(reg); | ||
304 | tmp |= drvstr << shift; | ||
305 | |||
306 | __raw_writel(tmp, reg); | ||
307 | |||
308 | return 0; | ||
309 | } | ||
310 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | ||
311 | #endif /* CONFIG_S5P_GPIO_DRVSTR */ | ||
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c index 28d2ab8a08db..b83a83351cea 100644 --- a/arch/arm/plat-samsung/gpio.c +++ b/arch/arm/plat-samsung/gpio.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/gpio.h> | 17 | #include <linux/gpio.h> |
18 | #include <linux/spinlock.h> | ||
18 | 19 | ||
19 | #include <plat/gpio-core.h> | 20 | #include <plat/gpio-core.h> |
20 | 21 | ||
@@ -52,14 +53,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) | |||
52 | unsigned long flags; | 53 | unsigned long flags; |
53 | unsigned long con; | 54 | unsigned long con; |
54 | 55 | ||
55 | local_irq_save(flags); | 56 | s3c_gpio_lock(ourchip, flags); |
56 | 57 | ||
57 | con = __raw_readl(base + 0x00); | 58 | con = __raw_readl(base + 0x00); |
58 | con &= ~(3 << (offset * 2)); | 59 | con &= ~(3 << (offset * 2)); |
59 | 60 | ||
60 | __raw_writel(con, base + 0x00); | 61 | __raw_writel(con, base + 0x00); |
61 | 62 | ||
62 | local_irq_restore(flags); | 63 | s3c_gpio_unlock(ourchip, flags); |
63 | return 0; | 64 | return 0; |
64 | } | 65 | } |
65 | 66 | ||
@@ -72,7 +73,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip, | |||
72 | unsigned long dat; | 73 | unsigned long dat; |
73 | unsigned long con; | 74 | unsigned long con; |
74 | 75 | ||
75 | local_irq_save(flags); | 76 | s3c_gpio_lock(ourchip, flags); |
76 | 77 | ||
77 | dat = __raw_readl(base + 0x04); | 78 | dat = __raw_readl(base + 0x04); |
78 | dat &= ~(1 << offset); | 79 | dat &= ~(1 << offset); |
@@ -87,7 +88,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip, | |||
87 | __raw_writel(con, base + 0x00); | 88 | __raw_writel(con, base + 0x00); |
88 | __raw_writel(dat, base + 0x04); | 89 | __raw_writel(dat, base + 0x04); |
89 | 90 | ||
90 | local_irq_restore(flags); | 91 | s3c_gpio_unlock(ourchip, flags); |
91 | return 0; | 92 | return 0; |
92 | } | 93 | } |
93 | 94 | ||
@@ -99,7 +100,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip, | |||
99 | unsigned long flags; | 100 | unsigned long flags; |
100 | unsigned long dat; | 101 | unsigned long dat; |
101 | 102 | ||
102 | local_irq_save(flags); | 103 | s3c_gpio_lock(ourchip, flags); |
103 | 104 | ||
104 | dat = __raw_readl(base + 0x04); | 105 | dat = __raw_readl(base + 0x04); |
105 | dat &= ~(1 << offset); | 106 | dat &= ~(1 << offset); |
@@ -107,7 +108,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip, | |||
107 | dat |= 1 << offset; | 108 | dat |= 1 << offset; |
108 | __raw_writel(dat, base + 0x04); | 109 | __raw_writel(dat, base + 0x04); |
109 | 110 | ||
110 | local_irq_restore(flags); | 111 | s3c_gpio_unlock(ourchip, flags); |
111 | } | 112 | } |
112 | 113 | ||
113 | static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) | 114 | static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) |
@@ -131,6 +132,8 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) | |||
131 | BUG_ON(!gc->label); | 132 | BUG_ON(!gc->label); |
132 | BUG_ON(!gc->ngpio); | 133 | BUG_ON(!gc->ngpio); |
133 | 134 | ||
135 | spin_lock_init(&chip->lock); | ||
136 | |||
134 | if (!gc->direction_input) | 137 | if (!gc->direction_input) |
135 | gc->direction_input = s3c_gpiolib_input; | 138 | gc->direction_input = s3c_gpiolib_input; |
136 | if (!gc->direction_output) | 139 | if (!gc->direction_output) |
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h index 12caf48a6bdc..0fbcd0effd8e 100644 --- a/arch/arm/plat-samsung/include/plat/clock.h +++ b/arch/arm/plat-samsung/include/plat/clock.h | |||
@@ -74,6 +74,7 @@ extern struct clk clk_ext; | |||
74 | extern struct clk clk_h2; | 74 | extern struct clk clk_h2; |
75 | extern struct clk clk_27m; | 75 | extern struct clk clk_27m; |
76 | extern struct clk clk_48m; | 76 | extern struct clk clk_48m; |
77 | extern struct clk clk_xusbxti; | ||
77 | 78 | ||
78 | extern int clk_default_setrate(struct clk *clk, unsigned long rate); | 79 | extern int clk_default_setrate(struct clk *clk, unsigned long rate); |
79 | extern struct clk_ops clk_ops_def_setrate; | 80 | extern struct clk_ops clk_ops_def_setrate; |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 5dbeb7991e60..6412933d6fbb 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -79,6 +79,9 @@ extern struct sysdev_class s3c2442_sysclass; | |||
79 | extern struct sysdev_class s3c2443_sysclass; | 79 | extern struct sysdev_class s3c2443_sysclass; |
80 | extern struct sysdev_class s3c6410_sysclass; | 80 | extern struct sysdev_class s3c6410_sysclass; |
81 | extern struct sysdev_class s3c64xx_sysclass; | 81 | extern struct sysdev_class s3c64xx_sysclass; |
82 | extern struct sysdev_class s5p6440_sysclass; | ||
83 | extern struct sysdev_class s5p6442_sysclass; | ||
84 | extern struct sysdev_class s5pv210_sysclass; | ||
82 | 85 | ||
83 | extern void (*s5pc1xx_idle)(void); | 86 | extern void (*s5pc1xx_idle)(void); |
84 | 87 | ||
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 796d24258313..ef69e56b2885 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -64,6 +64,22 @@ extern struct platform_device s3c_device_nand; | |||
64 | extern struct platform_device s3c_device_usbgadget; | 64 | extern struct platform_device s3c_device_usbgadget; |
65 | extern struct platform_device s3c_device_usb_hsotg; | 65 | extern struct platform_device s3c_device_usb_hsotg; |
66 | 66 | ||
67 | extern struct platform_device s5pv210_device_ac97; | ||
68 | extern struct platform_device s5pv210_device_pcm0; | ||
69 | extern struct platform_device s5pv210_device_pcm1; | ||
70 | extern struct platform_device s5pv210_device_pcm2; | ||
71 | extern struct platform_device s5pv210_device_iis0; | ||
72 | extern struct platform_device s5pv210_device_iis1; | ||
73 | extern struct platform_device s5pv210_device_iis2; | ||
74 | |||
75 | extern struct platform_device s5p6442_device_pcm0; | ||
76 | extern struct platform_device s5p6442_device_pcm1; | ||
77 | extern struct platform_device s5p6442_device_iis0; | ||
78 | extern struct platform_device s5p6442_device_iis1; | ||
79 | |||
80 | extern struct platform_device s5p6440_device_pcm; | ||
81 | extern struct platform_device s5p6440_device_iis; | ||
82 | |||
67 | /* s3c2440 specific devices */ | 83 | /* s3c2440 specific devices */ |
68 | 84 | ||
69 | #ifdef CONFIG_CPU_S3C2440 | 85 | #ifdef CONFIG_CPU_S3C2440 |
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h index 7584d751ed51..2e8f8c6560d7 100644 --- a/arch/arm/plat-samsung/include/plat/dma.h +++ b/arch/arm/plat-samsung/include/plat/dma.h | |||
@@ -110,8 +110,8 @@ extern int s3c2410_dma_config(unsigned int channel, int xferunit); | |||
110 | * configure the device we're talking to | 110 | * configure the device we're talking to |
111 | */ | 111 | */ |
112 | 112 | ||
113 | extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, | 113 | extern int s3c2410_dma_devconfig(unsigned int channel, |
114 | unsigned long devaddr); | 114 | enum s3c2410_dmasrc source, unsigned long devaddr); |
115 | 115 | ||
116 | /* s3c2410_dma_getposition | 116 | /* s3c2410_dma_getposition |
117 | * | 117 | * |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index ffc01a76b7ce..1f85649d8c18 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
@@ -15,6 +15,13 @@ | |||
15 | #ifndef __PLAT_S3C_FB_H | 15 | #ifndef __PLAT_S3C_FB_H |
16 | #define __PLAT_S3C_FB_H __FILE__ | 16 | #define __PLAT_S3C_FB_H __FILE__ |
17 | 17 | ||
18 | /* S3C_FB_MAX_WIN | ||
19 | * Set to the maximum number of windows that any of the supported hardware | ||
20 | * can use. Since the platform data uses this for an array size, having it | ||
21 | * set to the maximum of any version of the hardware can do is safe. | ||
22 | */ | ||
23 | #define S3C_FB_MAX_WIN (5) | ||
24 | |||
18 | /** | 25 | /** |
19 | * struct s3c_fb_pd_win - per window setup data | 26 | * struct s3c_fb_pd_win - per window setup data |
20 | * @win_mode: The display parameters to initialise (not for window 0) | 27 | * @win_mode: The display parameters to initialise (not for window 0) |
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 8d01e853df39..34efdd2b032c 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define __PLAT_GPIO_CFG_H __FILE__ | 25 | #define __PLAT_GPIO_CFG_H __FILE__ |
26 | 26 | ||
27 | typedef unsigned int __bitwise__ s3c_gpio_pull_t; | 27 | typedef unsigned int __bitwise__ s3c_gpio_pull_t; |
28 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; | ||
28 | 29 | ||
29 | /* forward declaration if gpio-core.h hasn't been included */ | 30 | /* forward declaration if gpio-core.h hasn't been included */ |
30 | struct s3c_gpio_chip; | 31 | struct s3c_gpio_chip; |
@@ -118,4 +119,33 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); | |||
118 | */ | 119 | */ |
119 | extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); | 120 | extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); |
120 | 121 | ||
122 | /* Define values for the drvstr available for each gpio pin. | ||
123 | * | ||
124 | * These values control the value of the output signal driver strength, | ||
125 | * configurable on most pins on the S5C series. | ||
126 | */ | ||
127 | #define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x00) | ||
128 | #define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x01) | ||
129 | #define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x10) | ||
130 | #define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x11) | ||
131 | |||
132 | /** | ||
133 | * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin | ||
134 | * @pin: The pin number to get the settings for | ||
135 | * | ||
136 | * Read the driver streght value for the specified pin. | ||
137 | */ | ||
138 | extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin); | ||
139 | |||
140 | /** | ||
141 | * s3c_gpio_set_drvstr() - set the driver streght value of a gpio pin | ||
142 | * @pin: The pin number to configure the driver streght value | ||
143 | * @drvstr: The new value of the driver strength | ||
144 | * | ||
145 | * This function sets the driver strength value for the specified pin. | ||
146 | * It will return 0 if successfull, or a negative error code if the pin | ||
147 | * cannot support the requested setting. | ||
148 | */ | ||
149 | extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); | ||
150 | |||
121 | #endif /* __PLAT_GPIO_CFG_H */ | 151 | #endif /* __PLAT_GPIO_CFG_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index f0584f26d493..f3a68d1a07b9 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h | |||
@@ -44,16 +44,26 @@ struct s3c_gpio_cfg; | |||
44 | * @chip: The chip structure to be exported via gpiolib. | 44 | * @chip: The chip structure to be exported via gpiolib. |
45 | * @base: The base pointer to the gpio configuration registers. | 45 | * @base: The base pointer to the gpio configuration registers. |
46 | * @config: special function and pull-resistor control information. | 46 | * @config: special function and pull-resistor control information. |
47 | * @lock: Lock for exclusive access to this gpio bank. | ||
47 | * @pm_save: Save information for suspend/resume support. | 48 | * @pm_save: Save information for suspend/resume support. |
48 | * | 49 | * |
49 | * This wrapper provides the necessary information for the Samsung | 50 | * This wrapper provides the necessary information for the Samsung |
50 | * specific gpios being registered with gpiolib. | 51 | * specific gpios being registered with gpiolib. |
52 | * | ||
53 | * The lock protects each gpio bank from multiple access of the shared | ||
54 | * configuration registers, or from reading of data whilst another thread | ||
55 | * is writing to the register set. | ||
56 | * | ||
57 | * Each chip has its own lock to avoid any contention between different | ||
58 | * CPU cores trying to get one lock for different GPIO banks, where each | ||
59 | * bank of GPIO has its own register space and configuration registers. | ||
51 | */ | 60 | */ |
52 | struct s3c_gpio_chip { | 61 | struct s3c_gpio_chip { |
53 | struct gpio_chip chip; | 62 | struct gpio_chip chip; |
54 | struct s3c_gpio_cfg *config; | 63 | struct s3c_gpio_cfg *config; |
55 | struct s3c_gpio_pm *pm; | 64 | struct s3c_gpio_pm *pm; |
56 | void __iomem *base; | 65 | void __iomem *base; |
66 | spinlock_t lock; | ||
57 | #ifdef CONFIG_PM | 67 | #ifdef CONFIG_PM |
58 | u32 pm_save[4]; | 68 | u32 pm_save[4]; |
59 | #endif | 69 | #endif |
@@ -138,3 +148,7 @@ extern struct s3c_gpio_pm s3c_gpio_pm_4bit; | |||
138 | #define __gpio_pm(x) NULL | 148 | #define __gpio_pm(x) NULL |
139 | 149 | ||
140 | #endif /* CONFIG_PM */ | 150 | #endif /* CONFIG_PM */ |
151 | |||
152 | /* locking wrappers to deal with multiple access to the same gpio bank */ | ||
153 | #define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) | ||
154 | #define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) | ||
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h index 1ba88ea0aa31..c167e4429bc7 100644 --- a/arch/arm/plat-samsung/include/plat/hwmon.h +++ b/arch/arm/plat-samsung/include/plat/hwmon.h | |||
@@ -37,5 +37,15 @@ struct s3c_hwmon_pdata { | |||
37 | struct s3c_hwmon_chcfg *in[8]; | 37 | struct s3c_hwmon_chcfg *in[8]; |
38 | }; | 38 | }; |
39 | 39 | ||
40 | /** | ||
41 | * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device | ||
42 | * @pd: Platform data to register to device. | ||
43 | * | ||
44 | * Register the given platform data for use with the S3C HWMON device. | ||
45 | * The call will copy the platform data, so the board definitions can | ||
46 | * make the structure itself __initdata. | ||
47 | */ | ||
48 | extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd); | ||
49 | |||
40 | #endif /* __ASM_ARCH_ADC_HWMON_H */ | 50 | #endif /* __ASM_ARCH_ADC_HWMON_H */ |
41 | 51 | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h new file mode 100644 index 000000000000..5fe6721b57f7 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S3C_DMA_PL330_H_ | ||
12 | #define __S3C_DMA_PL330_H_ | ||
13 | |||
14 | #define S3C2410_DMAF_AUTOSTART (1 << 0) | ||
15 | #define S3C2410_DMAF_CIRCULAR (1 << 1) | ||
16 | |||
17 | /* | ||
18 | * PL330 can assign any channel to communicate with | ||
19 | * any of the peripherals attched to the DMAC. | ||
20 | * For the sake of consistency across client drivers, | ||
21 | * We keep the channel names unchanged and only add | ||
22 | * missing peripherals are added. | ||
23 | * Order is not important since S3C PL330 API driver | ||
24 | * use these just as IDs. | ||
25 | */ | ||
26 | enum dma_ch { | ||
27 | DMACH_UART0_RX, | ||
28 | DMACH_UART0_TX, | ||
29 | DMACH_UART1_RX, | ||
30 | DMACH_UART1_TX, | ||
31 | DMACH_UART2_RX, | ||
32 | DMACH_UART2_TX, | ||
33 | DMACH_UART3_RX, | ||
34 | DMACH_UART3_TX, | ||
35 | DMACH_IRDA, | ||
36 | DMACH_I2S0_RX, | ||
37 | DMACH_I2S0_TX, | ||
38 | DMACH_I2S0S_TX, | ||
39 | DMACH_I2S1_RX, | ||
40 | DMACH_I2S1_TX, | ||
41 | DMACH_I2S2_RX, | ||
42 | DMACH_I2S2_TX, | ||
43 | DMACH_SPI0_RX, | ||
44 | DMACH_SPI0_TX, | ||
45 | DMACH_SPI1_RX, | ||
46 | DMACH_SPI1_TX, | ||
47 | DMACH_SPI2_RX, | ||
48 | DMACH_SPI2_TX, | ||
49 | DMACH_AC97_MICIN, | ||
50 | DMACH_AC97_PCMIN, | ||
51 | DMACH_AC97_PCMOUT, | ||
52 | DMACH_EXTERNAL, | ||
53 | DMACH_PWM, | ||
54 | DMACH_SPDIF, | ||
55 | DMACH_HSI_RX, | ||
56 | DMACH_HSI_TX, | ||
57 | DMACH_PCM0_TX, | ||
58 | DMACH_PCM0_RX, | ||
59 | DMACH_PCM1_TX, | ||
60 | DMACH_PCM1_RX, | ||
61 | DMACH_PCM2_TX, | ||
62 | DMACH_PCM2_RX, | ||
63 | DMACH_MSM_REQ3, | ||
64 | DMACH_MSM_REQ2, | ||
65 | DMACH_MSM_REQ1, | ||
66 | DMACH_MSM_REQ0, | ||
67 | /* END Marker, also used to denote a reserved channel */ | ||
68 | DMACH_MAX, | ||
69 | }; | ||
70 | |||
71 | static inline bool s3c_dma_has_circular(void) | ||
72 | { | ||
73 | return true; | ||
74 | } | ||
75 | |||
76 | #include <plat/dma.h> | ||
77 | |||
78 | #endif /* __S3C_DMA_PL330_H_ */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h new file mode 100644 index 000000000000..bf5e2a9d408d --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/s3c-pl330-pdata.h | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #ifndef __S3C_PL330_PDATA_H | ||
13 | #define __S3C_PL330_PDATA_H | ||
14 | |||
15 | #include <plat/s3c-dma-pl330.h> | ||
16 | |||
17 | /* | ||
18 | * Every PL330 DMAC has max 32 peripheral interfaces, | ||
19 | * of which some may be not be really used in your | ||
20 | * DMAC's configuration. | ||
21 | * Populate this array of 32 peri i/fs with relevant | ||
22 | * channel IDs for used peri i/f and DMACH_MAX for | ||
23 | * those unused. | ||
24 | * | ||
25 | * The platforms just need to provide this info | ||
26 | * to the S3C DMA API driver for PL330. | ||
27 | */ | ||
28 | struct s3c_pl330_platdata { | ||
29 | enum dma_ch peri[32]; | ||
30 | }; | ||
31 | |||
32 | #endif /* __S3C_PL330_PDATA_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/ts.h b/arch/arm/plat-samsung/include/plat/ts.h index dc361700d695..26fdb22e0fc2 100644 --- a/arch/arm/mach-s3c2410/include/mach/ts.h +++ b/arch/arm/plat-samsung/include/plat/ts.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* linux/include/asm/arch-s3c2410/ts.h | 1 | /* arch/arm/plat-samsung/include/plat/ts.h |
2 | * | 2 | * |
3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> | 3 | * Copyright (c) 2005 Arnaud Patard <arnaud.patard@rtp-net.org> |
4 | * | 4 | * |
@@ -14,8 +14,12 @@ struct s3c2410_ts_mach_info { | |||
14 | int delay; | 14 | int delay; |
15 | int presc; | 15 | int presc; |
16 | int oversampling_shift; | 16 | int oversampling_shift; |
17 | void (*cfg_gpio)(struct platform_device *dev); | ||
17 | }; | 18 | }; |
18 | 19 | ||
19 | extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); | 20 | extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); |
20 | 21 | ||
22 | /* defined by architecture to configure gpio */ | ||
23 | extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev); | ||
24 | |||
21 | #endif /* __ASM_ARM_TS_H */ | 25 | #endif /* __ASM_ARM_TS_H */ |
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 69a4c7f02e25..d50ab9d2af53 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c | |||
@@ -329,7 +329,7 @@ void s3c_pm_save_gpios(void) | |||
329 | struct s3c_gpio_chip *ourchip; | 329 | struct s3c_gpio_chip *ourchip; |
330 | unsigned int gpio_nr; | 330 | unsigned int gpio_nr; |
331 | 331 | ||
332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { | 332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
333 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 333 | ourchip = s3c_gpiolib_getchip(gpio_nr); |
334 | if (!ourchip) | 334 | if (!ourchip) |
335 | continue; | 335 | continue; |
@@ -367,7 +367,7 @@ void s3c_pm_restore_gpios(void) | |||
367 | struct s3c_gpio_chip *ourchip; | 367 | struct s3c_gpio_chip *ourchip; |
368 | unsigned int gpio_nr; | 368 | unsigned int gpio_nr; |
369 | 369 | ||
370 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { | 370 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
371 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 371 | ourchip = s3c_gpiolib_getchip(gpio_nr); |
372 | if (!ourchip) | 372 | if (!ourchip) |
373 | continue; | 373 | continue; |
diff --git a/arch/arm/plat-samsung/s3c-pl330.c b/arch/arm/plat-samsung/s3c-pl330.c new file mode 100644 index 000000000000..a91305a60aed --- /dev/null +++ b/arch/arm/plat-samsung/s3c-pl330.c | |||
@@ -0,0 +1,1224 @@ | |||
1 | /* linux/arch/arm/plat-samsung/s3c-pl330.c | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | */ | ||
11 | |||
12 | #include <linux/init.h> | ||
13 | #include <linux/module.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/slab.h> | ||
17 | #include <linux/platform_device.h> | ||
18 | |||
19 | #include <asm/hardware/pl330.h> | ||
20 | |||
21 | #include <plat/s3c-pl330-pdata.h> | ||
22 | |||
23 | /** | ||
24 | * struct s3c_pl330_dmac - Logical representation of a PL330 DMAC. | ||
25 | * @busy_chan: Number of channels currently busy. | ||
26 | * @peri: List of IDs of peripherals this DMAC can work with. | ||
27 | * @node: To attach to the global list of DMACs. | ||
28 | * @pi: PL330 configuration info for the DMAC. | ||
29 | * @kmcache: Pool to quickly allocate xfers for all channels in the dmac. | ||
30 | */ | ||
31 | struct s3c_pl330_dmac { | ||
32 | unsigned busy_chan; | ||
33 | enum dma_ch *peri; | ||
34 | struct list_head node; | ||
35 | struct pl330_info *pi; | ||
36 | struct kmem_cache *kmcache; | ||
37 | }; | ||
38 | |||
39 | /** | ||
40 | * struct s3c_pl330_xfer - A request submitted by S3C DMA clients. | ||
41 | * @token: Xfer ID provided by the client. | ||
42 | * @node: To attach to the list of xfers on a channel. | ||
43 | * @px: Xfer for PL330 core. | ||
44 | * @chan: Owner channel of this xfer. | ||
45 | */ | ||
46 | struct s3c_pl330_xfer { | ||
47 | void *token; | ||
48 | struct list_head node; | ||
49 | struct pl330_xfer px; | ||
50 | struct s3c_pl330_chan *chan; | ||
51 | }; | ||
52 | |||
53 | /** | ||
54 | * struct s3c_pl330_chan - Logical channel to communicate with | ||
55 | * a Physical peripheral. | ||
56 | * @pl330_chan_id: Token of a hardware channel thread of PL330 DMAC. | ||
57 | * NULL if the channel is available to be acquired. | ||
58 | * @id: ID of the peripheral that this channel can communicate with. | ||
59 | * @options: Options specified by the client. | ||
60 | * @sdaddr: Address provided via s3c2410_dma_devconfig. | ||
61 | * @node: To attach to the global list of channels. | ||
62 | * @lrq: Pointer to the last submitted pl330_req to PL330 core. | ||
63 | * @xfer_list: To manage list of xfers enqueued. | ||
64 | * @req: Two requests to communicate with the PL330 engine. | ||
65 | * @callback_fn: Callback function to the client. | ||
66 | * @rqcfg: Channel configuration for the xfers. | ||
67 | * @xfer_head: Pointer to the xfer to be next excecuted. | ||
68 | * @dmac: Pointer to the DMAC that manages this channel, NULL if the | ||
69 | * channel is available to be acquired. | ||
70 | * @client: Client of this channel. NULL if the | ||
71 | * channel is available to be acquired. | ||
72 | */ | ||
73 | struct s3c_pl330_chan { | ||
74 | void *pl330_chan_id; | ||
75 | enum dma_ch id; | ||
76 | unsigned int options; | ||
77 | unsigned long sdaddr; | ||
78 | struct list_head node; | ||
79 | struct pl330_req *lrq; | ||
80 | struct list_head xfer_list; | ||
81 | struct pl330_req req[2]; | ||
82 | s3c2410_dma_cbfn_t callback_fn; | ||
83 | struct pl330_reqcfg rqcfg; | ||
84 | struct s3c_pl330_xfer *xfer_head; | ||
85 | struct s3c_pl330_dmac *dmac; | ||
86 | struct s3c2410_dma_client *client; | ||
87 | }; | ||
88 | |||
89 | /* All DMACs in the platform */ | ||
90 | static LIST_HEAD(dmac_list); | ||
91 | |||
92 | /* All channels to peripherals in the platform */ | ||
93 | static LIST_HEAD(chan_list); | ||
94 | |||
95 | /* | ||
96 | * Since we add resources(DMACs and Channels) to the global pool, | ||
97 | * we need to guard access to the resources using a global lock | ||
98 | */ | ||
99 | static DEFINE_SPINLOCK(res_lock); | ||
100 | |||
101 | /* Returns the channel with ID 'id' in the chan_list */ | ||
102 | static struct s3c_pl330_chan *id_to_chan(const enum dma_ch id) | ||
103 | { | ||
104 | struct s3c_pl330_chan *ch; | ||
105 | |||
106 | list_for_each_entry(ch, &chan_list, node) | ||
107 | if (ch->id == id) | ||
108 | return ch; | ||
109 | |||
110 | return NULL; | ||
111 | } | ||
112 | |||
113 | /* Allocate a new channel with ID 'id' and add to chan_list */ | ||
114 | static void chan_add(const enum dma_ch id) | ||
115 | { | ||
116 | struct s3c_pl330_chan *ch = id_to_chan(id); | ||
117 | |||
118 | /* Return if the channel already exists */ | ||
119 | if (ch) | ||
120 | return; | ||
121 | |||
122 | ch = kmalloc(sizeof(*ch), GFP_KERNEL); | ||
123 | /* Return silently to work with other channels */ | ||
124 | if (!ch) | ||
125 | return; | ||
126 | |||
127 | ch->id = id; | ||
128 | ch->dmac = NULL; | ||
129 | |||
130 | list_add_tail(&ch->node, &chan_list); | ||
131 | } | ||
132 | |||
133 | /* If the channel is not yet acquired by any client */ | ||
134 | static bool chan_free(struct s3c_pl330_chan *ch) | ||
135 | { | ||
136 | if (!ch) | ||
137 | return false; | ||
138 | |||
139 | /* Channel points to some DMAC only when it's acquired */ | ||
140 | return ch->dmac ? false : true; | ||
141 | } | ||
142 | |||
143 | /* | ||
144 | * Returns 0 is peripheral i/f is invalid or not present on the dmac. | ||
145 | * Index + 1, otherwise. | ||
146 | */ | ||
147 | static unsigned iface_of_dmac(struct s3c_pl330_dmac *dmac, enum dma_ch ch_id) | ||
148 | { | ||
149 | enum dma_ch *id = dmac->peri; | ||
150 | int i; | ||
151 | |||
152 | /* Discount invalid markers */ | ||
153 | if (ch_id == DMACH_MAX) | ||
154 | return 0; | ||
155 | |||
156 | for (i = 0; i < PL330_MAX_PERI; i++) | ||
157 | if (id[i] == ch_id) | ||
158 | return i + 1; | ||
159 | |||
160 | return 0; | ||
161 | } | ||
162 | |||
163 | /* If all channel threads of the DMAC are busy */ | ||
164 | static inline bool dmac_busy(struct s3c_pl330_dmac *dmac) | ||
165 | { | ||
166 | struct pl330_info *pi = dmac->pi; | ||
167 | |||
168 | return (dmac->busy_chan < pi->pcfg.num_chan) ? false : true; | ||
169 | } | ||
170 | |||
171 | /* | ||
172 | * Returns the number of free channels that | ||
173 | * can be handled by this dmac only. | ||
174 | */ | ||
175 | static unsigned ch_onlyby_dmac(struct s3c_pl330_dmac *dmac) | ||
176 | { | ||
177 | enum dma_ch *id = dmac->peri; | ||
178 | struct s3c_pl330_dmac *d; | ||
179 | struct s3c_pl330_chan *ch; | ||
180 | unsigned found, count = 0; | ||
181 | enum dma_ch p; | ||
182 | int i; | ||
183 | |||
184 | for (i = 0; i < PL330_MAX_PERI; i++) { | ||
185 | p = id[i]; | ||
186 | ch = id_to_chan(p); | ||
187 | |||
188 | if (p == DMACH_MAX || !chan_free(ch)) | ||
189 | continue; | ||
190 | |||
191 | found = 0; | ||
192 | list_for_each_entry(d, &dmac_list, node) { | ||
193 | if (d != dmac && iface_of_dmac(d, ch->id)) { | ||
194 | found = 1; | ||
195 | break; | ||
196 | } | ||
197 | } | ||
198 | if (!found) | ||
199 | count++; | ||
200 | } | ||
201 | |||
202 | return count; | ||
203 | } | ||
204 | |||
205 | /* | ||
206 | * Measure of suitability of 'dmac' handling 'ch' | ||
207 | * | ||
208 | * 0 indicates 'dmac' can not handle 'ch' either | ||
209 | * because it is not supported by the hardware or | ||
210 | * because all dmac channels are currently busy. | ||
211 | * | ||
212 | * >0 vlaue indicates 'dmac' has the capability. | ||
213 | * The bigger the value the more suitable the dmac. | ||
214 | */ | ||
215 | #define MAX_SUIT UINT_MAX | ||
216 | #define MIN_SUIT 0 | ||
217 | |||
218 | static unsigned suitablility(struct s3c_pl330_dmac *dmac, | ||
219 | struct s3c_pl330_chan *ch) | ||
220 | { | ||
221 | struct pl330_info *pi = dmac->pi; | ||
222 | enum dma_ch *id = dmac->peri; | ||
223 | struct s3c_pl330_dmac *d; | ||
224 | unsigned s; | ||
225 | int i; | ||
226 | |||
227 | s = MIN_SUIT; | ||
228 | /* If all the DMAC channel threads are busy */ | ||
229 | if (dmac_busy(dmac)) | ||
230 | return s; | ||
231 | |||
232 | for (i = 0; i < PL330_MAX_PERI; i++) | ||
233 | if (id[i] == ch->id) | ||
234 | break; | ||
235 | |||
236 | /* If the 'dmac' can't talk to 'ch' */ | ||
237 | if (i == PL330_MAX_PERI) | ||
238 | return s; | ||
239 | |||
240 | s = MAX_SUIT; | ||
241 | list_for_each_entry(d, &dmac_list, node) { | ||
242 | /* | ||
243 | * If some other dmac can talk to this | ||
244 | * peri and has some channel free. | ||
245 | */ | ||
246 | if (d != dmac && iface_of_dmac(d, ch->id) && !dmac_busy(d)) { | ||
247 | s = 0; | ||
248 | break; | ||
249 | } | ||
250 | } | ||
251 | if (s) | ||
252 | return s; | ||
253 | |||
254 | s = 100; | ||
255 | |||
256 | /* Good if free chans are more, bad otherwise */ | ||
257 | s += (pi->pcfg.num_chan - dmac->busy_chan) - ch_onlyby_dmac(dmac); | ||
258 | |||
259 | return s; | ||
260 | } | ||
261 | |||
262 | /* More than one DMAC may have capability to transfer data with the | ||
263 | * peripheral. This function assigns most suitable DMAC to manage the | ||
264 | * channel and hence communicate with the peripheral. | ||
265 | */ | ||
266 | static struct s3c_pl330_dmac *map_chan_to_dmac(struct s3c_pl330_chan *ch) | ||
267 | { | ||
268 | struct s3c_pl330_dmac *d, *dmac = NULL; | ||
269 | unsigned sn, sl = MIN_SUIT; | ||
270 | |||
271 | list_for_each_entry(d, &dmac_list, node) { | ||
272 | sn = suitablility(d, ch); | ||
273 | |||
274 | if (sn == MAX_SUIT) | ||
275 | return d; | ||
276 | |||
277 | if (sn > sl) | ||
278 | dmac = d; | ||
279 | } | ||
280 | |||
281 | return dmac; | ||
282 | } | ||
283 | |||
284 | /* Acquire the channel for peripheral 'id' */ | ||
285 | static struct s3c_pl330_chan *chan_acquire(const enum dma_ch id) | ||
286 | { | ||
287 | struct s3c_pl330_chan *ch = id_to_chan(id); | ||
288 | struct s3c_pl330_dmac *dmac; | ||
289 | |||
290 | /* If the channel doesn't exist or is already acquired */ | ||
291 | if (!ch || !chan_free(ch)) { | ||
292 | ch = NULL; | ||
293 | goto acq_exit; | ||
294 | } | ||
295 | |||
296 | dmac = map_chan_to_dmac(ch); | ||
297 | /* If couldn't map */ | ||
298 | if (!dmac) { | ||
299 | ch = NULL; | ||
300 | goto acq_exit; | ||
301 | } | ||
302 | |||
303 | dmac->busy_chan++; | ||
304 | ch->dmac = dmac; | ||
305 | |||
306 | acq_exit: | ||
307 | return ch; | ||
308 | } | ||
309 | |||
310 | /* Delete xfer from the queue */ | ||
311 | static inline void del_from_queue(struct s3c_pl330_xfer *xfer) | ||
312 | { | ||
313 | struct s3c_pl330_xfer *t; | ||
314 | struct s3c_pl330_chan *ch; | ||
315 | int found; | ||
316 | |||
317 | if (!xfer) | ||
318 | return; | ||
319 | |||
320 | ch = xfer->chan; | ||
321 | |||
322 | /* Make sure xfer is in the queue */ | ||
323 | found = 0; | ||
324 | list_for_each_entry(t, &ch->xfer_list, node) | ||
325 | if (t == xfer) { | ||
326 | found = 1; | ||
327 | break; | ||
328 | } | ||
329 | |||
330 | if (!found) | ||
331 | return; | ||
332 | |||
333 | /* If xfer is last entry in the queue */ | ||
334 | if (xfer->node.next == &ch->xfer_list) | ||
335 | t = list_entry(ch->xfer_list.next, | ||
336 | struct s3c_pl330_xfer, node); | ||
337 | else | ||
338 | t = list_entry(xfer->node.next, | ||
339 | struct s3c_pl330_xfer, node); | ||
340 | |||
341 | /* If there was only one node left */ | ||
342 | if (t == xfer) | ||
343 | ch->xfer_head = NULL; | ||
344 | else if (ch->xfer_head == xfer) | ||
345 | ch->xfer_head = t; | ||
346 | |||
347 | list_del(&xfer->node); | ||
348 | } | ||
349 | |||
350 | /* Provides pointer to the next xfer in the queue. | ||
351 | * If CIRCULAR option is set, the list is left intact, | ||
352 | * otherwise the xfer is removed from the list. | ||
353 | * Forced delete 'pluck' can be set to override the CIRCULAR option. | ||
354 | */ | ||
355 | static struct s3c_pl330_xfer *get_from_queue(struct s3c_pl330_chan *ch, | ||
356 | int pluck) | ||
357 | { | ||
358 | struct s3c_pl330_xfer *xfer = ch->xfer_head; | ||
359 | |||
360 | if (!xfer) | ||
361 | return NULL; | ||
362 | |||
363 | /* If xfer is last entry in the queue */ | ||
364 | if (xfer->node.next == &ch->xfer_list) | ||
365 | ch->xfer_head = list_entry(ch->xfer_list.next, | ||
366 | struct s3c_pl330_xfer, node); | ||
367 | else | ||
368 | ch->xfer_head = list_entry(xfer->node.next, | ||
369 | struct s3c_pl330_xfer, node); | ||
370 | |||
371 | if (pluck || !(ch->options & S3C2410_DMAF_CIRCULAR)) | ||
372 | del_from_queue(xfer); | ||
373 | |||
374 | return xfer; | ||
375 | } | ||
376 | |||
377 | static inline void add_to_queue(struct s3c_pl330_chan *ch, | ||
378 | struct s3c_pl330_xfer *xfer, int front) | ||
379 | { | ||
380 | struct pl330_xfer *xt; | ||
381 | |||
382 | /* If queue empty */ | ||
383 | if (ch->xfer_head == NULL) | ||
384 | ch->xfer_head = xfer; | ||
385 | |||
386 | xt = &ch->xfer_head->px; | ||
387 | /* If the head already submitted (CIRCULAR head) */ | ||
388 | if (ch->options & S3C2410_DMAF_CIRCULAR && | ||
389 | (xt == ch->req[0].x || xt == ch->req[1].x)) | ||
390 | ch->xfer_head = xfer; | ||
391 | |||
392 | /* If this is a resubmission, it should go at the head */ | ||
393 | if (front) { | ||
394 | ch->xfer_head = xfer; | ||
395 | list_add(&xfer->node, &ch->xfer_list); | ||
396 | } else { | ||
397 | list_add_tail(&xfer->node, &ch->xfer_list); | ||
398 | } | ||
399 | } | ||
400 | |||
401 | static inline void _finish_off(struct s3c_pl330_xfer *xfer, | ||
402 | enum s3c2410_dma_buffresult res, int ffree) | ||
403 | { | ||
404 | struct s3c_pl330_chan *ch; | ||
405 | |||
406 | if (!xfer) | ||
407 | return; | ||
408 | |||
409 | ch = xfer->chan; | ||
410 | |||
411 | /* Do callback */ | ||
412 | if (ch->callback_fn) | ||
413 | ch->callback_fn(NULL, xfer->token, xfer->px.bytes, res); | ||
414 | |||
415 | /* Force Free or if buffer is not needed anymore */ | ||
416 | if (ffree || !(ch->options & S3C2410_DMAF_CIRCULAR)) | ||
417 | kmem_cache_free(ch->dmac->kmcache, xfer); | ||
418 | } | ||
419 | |||
420 | static inline int s3c_pl330_submit(struct s3c_pl330_chan *ch, | ||
421 | struct pl330_req *r) | ||
422 | { | ||
423 | struct s3c_pl330_xfer *xfer; | ||
424 | int ret = 0; | ||
425 | |||
426 | /* If already submitted */ | ||
427 | if (r->x) | ||
428 | return 0; | ||
429 | |||
430 | xfer = get_from_queue(ch, 0); | ||
431 | if (xfer) { | ||
432 | r->x = &xfer->px; | ||
433 | |||
434 | /* Use max bandwidth for M<->M xfers */ | ||
435 | if (r->rqtype == MEMTOMEM) { | ||
436 | struct pl330_info *pi = xfer->chan->dmac->pi; | ||
437 | int burst = 1 << ch->rqcfg.brst_size; | ||
438 | u32 bytes = r->x->bytes; | ||
439 | int bl; | ||
440 | |||
441 | bl = pi->pcfg.data_bus_width / 8; | ||
442 | bl *= pi->pcfg.data_buf_dep; | ||
443 | bl /= burst; | ||
444 | |||
445 | /* src/dst_burst_len can't be more than 16 */ | ||
446 | if (bl > 16) | ||
447 | bl = 16; | ||
448 | |||
449 | while (bl > 1) { | ||
450 | if (!(bytes % (bl * burst))) | ||
451 | break; | ||
452 | bl--; | ||
453 | } | ||
454 | |||
455 | ch->rqcfg.brst_len = bl; | ||
456 | } else { | ||
457 | ch->rqcfg.brst_len = 1; | ||
458 | } | ||
459 | |||
460 | ret = pl330_submit_req(ch->pl330_chan_id, r); | ||
461 | |||
462 | /* If submission was successful */ | ||
463 | if (!ret) { | ||
464 | ch->lrq = r; /* latest submitted req */ | ||
465 | return 0; | ||
466 | } | ||
467 | |||
468 | r->x = NULL; | ||
469 | |||
470 | /* If both of the PL330 ping-pong buffers filled */ | ||
471 | if (ret == -EAGAIN) { | ||
472 | dev_err(ch->dmac->pi->dev, "%s:%d!\n", | ||
473 | __func__, __LINE__); | ||
474 | /* Queue back again */ | ||
475 | add_to_queue(ch, xfer, 1); | ||
476 | ret = 0; | ||
477 | } else { | ||
478 | dev_err(ch->dmac->pi->dev, "%s:%d!\n", | ||
479 | __func__, __LINE__); | ||
480 | _finish_off(xfer, S3C2410_RES_ERR, 0); | ||
481 | } | ||
482 | } | ||
483 | |||
484 | return ret; | ||
485 | } | ||
486 | |||
487 | static void s3c_pl330_rq(struct s3c_pl330_chan *ch, | ||
488 | struct pl330_req *r, enum pl330_op_err err) | ||
489 | { | ||
490 | unsigned long flags; | ||
491 | struct s3c_pl330_xfer *xfer; | ||
492 | struct pl330_xfer *xl = r->x; | ||
493 | enum s3c2410_dma_buffresult res; | ||
494 | |||
495 | spin_lock_irqsave(&res_lock, flags); | ||
496 | |||
497 | r->x = NULL; | ||
498 | |||
499 | s3c_pl330_submit(ch, r); | ||
500 | |||
501 | spin_unlock_irqrestore(&res_lock, flags); | ||
502 | |||
503 | /* Map result to S3C DMA API */ | ||
504 | if (err == PL330_ERR_NONE) | ||
505 | res = S3C2410_RES_OK; | ||
506 | else if (err == PL330_ERR_ABORT) | ||
507 | res = S3C2410_RES_ABORT; | ||
508 | else | ||
509 | res = S3C2410_RES_ERR; | ||
510 | |||
511 | /* If last request had some xfer */ | ||
512 | if (xl) { | ||
513 | xfer = container_of(xl, struct s3c_pl330_xfer, px); | ||
514 | _finish_off(xfer, res, 0); | ||
515 | } else { | ||
516 | dev_info(ch->dmac->pi->dev, "%s:%d No Xfer?!\n", | ||
517 | __func__, __LINE__); | ||
518 | } | ||
519 | } | ||
520 | |||
521 | static void s3c_pl330_rq0(void *token, enum pl330_op_err err) | ||
522 | { | ||
523 | struct pl330_req *r = token; | ||
524 | struct s3c_pl330_chan *ch = container_of(r, | ||
525 | struct s3c_pl330_chan, req[0]); | ||
526 | s3c_pl330_rq(ch, r, err); | ||
527 | } | ||
528 | |||
529 | static void s3c_pl330_rq1(void *token, enum pl330_op_err err) | ||
530 | { | ||
531 | struct pl330_req *r = token; | ||
532 | struct s3c_pl330_chan *ch = container_of(r, | ||
533 | struct s3c_pl330_chan, req[1]); | ||
534 | s3c_pl330_rq(ch, r, err); | ||
535 | } | ||
536 | |||
537 | /* Release an acquired channel */ | ||
538 | static void chan_release(struct s3c_pl330_chan *ch) | ||
539 | { | ||
540 | struct s3c_pl330_dmac *dmac; | ||
541 | |||
542 | if (chan_free(ch)) | ||
543 | return; | ||
544 | |||
545 | dmac = ch->dmac; | ||
546 | ch->dmac = NULL; | ||
547 | dmac->busy_chan--; | ||
548 | } | ||
549 | |||
550 | int s3c2410_dma_ctrl(enum dma_ch id, enum s3c2410_chan_op op) | ||
551 | { | ||
552 | struct s3c_pl330_xfer *xfer; | ||
553 | enum pl330_chan_op pl330op; | ||
554 | struct s3c_pl330_chan *ch; | ||
555 | unsigned long flags; | ||
556 | int idx, ret; | ||
557 | |||
558 | spin_lock_irqsave(&res_lock, flags); | ||
559 | |||
560 | ch = id_to_chan(id); | ||
561 | |||
562 | if (!ch || chan_free(ch)) { | ||
563 | ret = -EINVAL; | ||
564 | goto ctrl_exit; | ||
565 | } | ||
566 | |||
567 | switch (op) { | ||
568 | case S3C2410_DMAOP_START: | ||
569 | /* Make sure both reqs are enqueued */ | ||
570 | idx = (ch->lrq == &ch->req[0]) ? 1 : 0; | ||
571 | s3c_pl330_submit(ch, &ch->req[idx]); | ||
572 | s3c_pl330_submit(ch, &ch->req[1 - idx]); | ||
573 | pl330op = PL330_OP_START; | ||
574 | break; | ||
575 | |||
576 | case S3C2410_DMAOP_STOP: | ||
577 | pl330op = PL330_OP_ABORT; | ||
578 | break; | ||
579 | |||
580 | case S3C2410_DMAOP_FLUSH: | ||
581 | pl330op = PL330_OP_FLUSH; | ||
582 | break; | ||
583 | |||
584 | case S3C2410_DMAOP_PAUSE: | ||
585 | case S3C2410_DMAOP_RESUME: | ||
586 | case S3C2410_DMAOP_TIMEOUT: | ||
587 | case S3C2410_DMAOP_STARTED: | ||
588 | spin_unlock_irqrestore(&res_lock, flags); | ||
589 | return 0; | ||
590 | |||
591 | default: | ||
592 | spin_unlock_irqrestore(&res_lock, flags); | ||
593 | return -EINVAL; | ||
594 | } | ||
595 | |||
596 | ret = pl330_chan_ctrl(ch->pl330_chan_id, pl330op); | ||
597 | |||
598 | if (pl330op == PL330_OP_START) { | ||
599 | spin_unlock_irqrestore(&res_lock, flags); | ||
600 | return ret; | ||
601 | } | ||
602 | |||
603 | idx = (ch->lrq == &ch->req[0]) ? 1 : 0; | ||
604 | |||
605 | /* Abort the current xfer */ | ||
606 | if (ch->req[idx].x) { | ||
607 | xfer = container_of(ch->req[idx].x, | ||
608 | struct s3c_pl330_xfer, px); | ||
609 | |||
610 | /* Drop xfer during FLUSH */ | ||
611 | if (pl330op == PL330_OP_FLUSH) | ||
612 | del_from_queue(xfer); | ||
613 | |||
614 | ch->req[idx].x = NULL; | ||
615 | |||
616 | spin_unlock_irqrestore(&res_lock, flags); | ||
617 | _finish_off(xfer, S3C2410_RES_ABORT, | ||
618 | pl330op == PL330_OP_FLUSH ? 1 : 0); | ||
619 | spin_lock_irqsave(&res_lock, flags); | ||
620 | } | ||
621 | |||
622 | /* Flush the whole queue */ | ||
623 | if (pl330op == PL330_OP_FLUSH) { | ||
624 | |||
625 | if (ch->req[1 - idx].x) { | ||
626 | xfer = container_of(ch->req[1 - idx].x, | ||
627 | struct s3c_pl330_xfer, px); | ||
628 | |||
629 | del_from_queue(xfer); | ||
630 | |||
631 | ch->req[1 - idx].x = NULL; | ||
632 | |||
633 | spin_unlock_irqrestore(&res_lock, flags); | ||
634 | _finish_off(xfer, S3C2410_RES_ABORT, 1); | ||
635 | spin_lock_irqsave(&res_lock, flags); | ||
636 | } | ||
637 | |||
638 | /* Finish off the remaining in the queue */ | ||
639 | xfer = ch->xfer_head; | ||
640 | while (xfer) { | ||
641 | |||
642 | del_from_queue(xfer); | ||
643 | |||
644 | spin_unlock_irqrestore(&res_lock, flags); | ||
645 | _finish_off(xfer, S3C2410_RES_ABORT, 1); | ||
646 | spin_lock_irqsave(&res_lock, flags); | ||
647 | |||
648 | xfer = ch->xfer_head; | ||
649 | } | ||
650 | } | ||
651 | |||
652 | ctrl_exit: | ||
653 | spin_unlock_irqrestore(&res_lock, flags); | ||
654 | |||
655 | return ret; | ||
656 | } | ||
657 | EXPORT_SYMBOL(s3c2410_dma_ctrl); | ||
658 | |||
659 | int s3c2410_dma_enqueue(enum dma_ch id, void *token, | ||
660 | dma_addr_t addr, int size) | ||
661 | { | ||
662 | struct s3c_pl330_chan *ch; | ||
663 | struct s3c_pl330_xfer *xfer; | ||
664 | unsigned long flags; | ||
665 | int idx, ret = 0; | ||
666 | |||
667 | spin_lock_irqsave(&res_lock, flags); | ||
668 | |||
669 | ch = id_to_chan(id); | ||
670 | |||
671 | /* Error if invalid or free channel */ | ||
672 | if (!ch || chan_free(ch)) { | ||
673 | ret = -EINVAL; | ||
674 | goto enq_exit; | ||
675 | } | ||
676 | |||
677 | /* Error if size is unaligned */ | ||
678 | if (ch->rqcfg.brst_size && size % (1 << ch->rqcfg.brst_size)) { | ||
679 | ret = -EINVAL; | ||
680 | goto enq_exit; | ||
681 | } | ||
682 | |||
683 | xfer = kmem_cache_alloc(ch->dmac->kmcache, GFP_ATOMIC); | ||
684 | if (!xfer) { | ||
685 | ret = -ENOMEM; | ||
686 | goto enq_exit; | ||
687 | } | ||
688 | |||
689 | xfer->token = token; | ||
690 | xfer->chan = ch; | ||
691 | xfer->px.bytes = size; | ||
692 | xfer->px.next = NULL; /* Single request */ | ||
693 | |||
694 | /* For S3C DMA API, direction is always fixed for all xfers */ | ||
695 | if (ch->req[0].rqtype == MEMTODEV) { | ||
696 | xfer->px.src_addr = addr; | ||
697 | xfer->px.dst_addr = ch->sdaddr; | ||
698 | } else { | ||
699 | xfer->px.src_addr = ch->sdaddr; | ||
700 | xfer->px.dst_addr = addr; | ||
701 | } | ||
702 | |||
703 | add_to_queue(ch, xfer, 0); | ||
704 | |||
705 | /* Try submitting on either request */ | ||
706 | idx = (ch->lrq == &ch->req[0]) ? 1 : 0; | ||
707 | |||
708 | if (!ch->req[idx].x) | ||
709 | s3c_pl330_submit(ch, &ch->req[idx]); | ||
710 | else | ||
711 | s3c_pl330_submit(ch, &ch->req[1 - idx]); | ||
712 | |||
713 | spin_unlock_irqrestore(&res_lock, flags); | ||
714 | |||
715 | if (ch->options & S3C2410_DMAF_AUTOSTART) | ||
716 | s3c2410_dma_ctrl(id, S3C2410_DMAOP_START); | ||
717 | |||
718 | return 0; | ||
719 | |||
720 | enq_exit: | ||
721 | spin_unlock_irqrestore(&res_lock, flags); | ||
722 | |||
723 | return ret; | ||
724 | } | ||
725 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | ||
726 | |||
727 | int s3c2410_dma_request(enum dma_ch id, | ||
728 | struct s3c2410_dma_client *client, | ||
729 | void *dev) | ||
730 | { | ||
731 | struct s3c_pl330_dmac *dmac; | ||
732 | struct s3c_pl330_chan *ch; | ||
733 | unsigned long flags; | ||
734 | int ret = 0; | ||
735 | |||
736 | spin_lock_irqsave(&res_lock, flags); | ||
737 | |||
738 | ch = chan_acquire(id); | ||
739 | if (!ch) { | ||
740 | ret = -EBUSY; | ||
741 | goto req_exit; | ||
742 | } | ||
743 | |||
744 | dmac = ch->dmac; | ||
745 | |||
746 | ch->pl330_chan_id = pl330_request_channel(dmac->pi); | ||
747 | if (!ch->pl330_chan_id) { | ||
748 | chan_release(ch); | ||
749 | ret = -EBUSY; | ||
750 | goto req_exit; | ||
751 | } | ||
752 | |||
753 | ch->client = client; | ||
754 | ch->options = 0; /* Clear any option */ | ||
755 | ch->callback_fn = NULL; /* Clear any callback */ | ||
756 | ch->lrq = NULL; | ||
757 | |||
758 | ch->rqcfg.brst_size = 2; /* Default word size */ | ||
759 | ch->rqcfg.swap = SWAP_NO; | ||
760 | ch->rqcfg.scctl = SCCTRL0; /* Noncacheable and nonbufferable */ | ||
761 | ch->rqcfg.dcctl = DCCTRL0; /* Noncacheable and nonbufferable */ | ||
762 | ch->rqcfg.privileged = 0; | ||
763 | ch->rqcfg.insnaccess = 0; | ||
764 | |||
765 | /* Set invalid direction */ | ||
766 | ch->req[0].rqtype = DEVTODEV; | ||
767 | ch->req[1].rqtype = ch->req[0].rqtype; | ||
768 | |||
769 | ch->req[0].cfg = &ch->rqcfg; | ||
770 | ch->req[1].cfg = ch->req[0].cfg; | ||
771 | |||
772 | ch->req[0].peri = iface_of_dmac(dmac, id) - 1; /* Original index */ | ||
773 | ch->req[1].peri = ch->req[0].peri; | ||
774 | |||
775 | ch->req[0].token = &ch->req[0]; | ||
776 | ch->req[0].xfer_cb = s3c_pl330_rq0; | ||
777 | ch->req[1].token = &ch->req[1]; | ||
778 | ch->req[1].xfer_cb = s3c_pl330_rq1; | ||
779 | |||
780 | ch->req[0].x = NULL; | ||
781 | ch->req[1].x = NULL; | ||
782 | |||
783 | /* Reset xfer list */ | ||
784 | INIT_LIST_HEAD(&ch->xfer_list); | ||
785 | ch->xfer_head = NULL; | ||
786 | |||
787 | req_exit: | ||
788 | spin_unlock_irqrestore(&res_lock, flags); | ||
789 | |||
790 | return ret; | ||
791 | } | ||
792 | EXPORT_SYMBOL(s3c2410_dma_request); | ||
793 | |||
794 | int s3c2410_dma_free(enum dma_ch id, struct s3c2410_dma_client *client) | ||
795 | { | ||
796 | struct s3c_pl330_chan *ch; | ||
797 | struct s3c_pl330_xfer *xfer; | ||
798 | unsigned long flags; | ||
799 | int ret = 0; | ||
800 | unsigned idx; | ||
801 | |||
802 | spin_lock_irqsave(&res_lock, flags); | ||
803 | |||
804 | ch = id_to_chan(id); | ||
805 | |||
806 | if (!ch || chan_free(ch)) | ||
807 | goto free_exit; | ||
808 | |||
809 | /* Refuse if someone else wanted to free the channel */ | ||
810 | if (ch->client != client) { | ||
811 | ret = -EBUSY; | ||
812 | goto free_exit; | ||
813 | } | ||
814 | |||
815 | /* Stop any active xfer, Flushe the queue and do callbacks */ | ||
816 | pl330_chan_ctrl(ch->pl330_chan_id, PL330_OP_FLUSH); | ||
817 | |||
818 | /* Abort the submitted requests */ | ||
819 | idx = (ch->lrq == &ch->req[0]) ? 1 : 0; | ||
820 | |||
821 | if (ch->req[idx].x) { | ||
822 | xfer = container_of(ch->req[idx].x, | ||
823 | struct s3c_pl330_xfer, px); | ||
824 | |||
825 | ch->req[idx].x = NULL; | ||
826 | del_from_queue(xfer); | ||
827 | |||
828 | spin_unlock_irqrestore(&res_lock, flags); | ||
829 | _finish_off(xfer, S3C2410_RES_ABORT, 1); | ||
830 | spin_lock_irqsave(&res_lock, flags); | ||
831 | } | ||
832 | |||
833 | if (ch->req[1 - idx].x) { | ||
834 | xfer = container_of(ch->req[1 - idx].x, | ||
835 | struct s3c_pl330_xfer, px); | ||
836 | |||
837 | ch->req[1 - idx].x = NULL; | ||
838 | del_from_queue(xfer); | ||
839 | |||
840 | spin_unlock_irqrestore(&res_lock, flags); | ||
841 | _finish_off(xfer, S3C2410_RES_ABORT, 1); | ||
842 | spin_lock_irqsave(&res_lock, flags); | ||
843 | } | ||
844 | |||
845 | /* Pluck and Abort the queued requests in order */ | ||
846 | do { | ||
847 | xfer = get_from_queue(ch, 1); | ||
848 | |||
849 | spin_unlock_irqrestore(&res_lock, flags); | ||
850 | _finish_off(xfer, S3C2410_RES_ABORT, 1); | ||
851 | spin_lock_irqsave(&res_lock, flags); | ||
852 | } while (xfer); | ||
853 | |||
854 | ch->client = NULL; | ||
855 | |||
856 | pl330_release_channel(ch->pl330_chan_id); | ||
857 | |||
858 | ch->pl330_chan_id = NULL; | ||
859 | |||
860 | chan_release(ch); | ||
861 | |||
862 | free_exit: | ||
863 | spin_unlock_irqrestore(&res_lock, flags); | ||
864 | |||
865 | return ret; | ||
866 | } | ||
867 | EXPORT_SYMBOL(s3c2410_dma_free); | ||
868 | |||
869 | int s3c2410_dma_config(enum dma_ch id, int xferunit) | ||
870 | { | ||
871 | struct s3c_pl330_chan *ch; | ||
872 | struct pl330_info *pi; | ||
873 | unsigned long flags; | ||
874 | int i, dbwidth, ret = 0; | ||
875 | |||
876 | spin_lock_irqsave(&res_lock, flags); | ||
877 | |||
878 | ch = id_to_chan(id); | ||
879 | |||
880 | if (!ch || chan_free(ch)) { | ||
881 | ret = -EINVAL; | ||
882 | goto cfg_exit; | ||
883 | } | ||
884 | |||
885 | pi = ch->dmac->pi; | ||
886 | dbwidth = pi->pcfg.data_bus_width / 8; | ||
887 | |||
888 | /* Max size of xfer can be pcfg.data_bus_width */ | ||
889 | if (xferunit > dbwidth) { | ||
890 | ret = -EINVAL; | ||
891 | goto cfg_exit; | ||
892 | } | ||
893 | |||
894 | i = 0; | ||
895 | while (xferunit != (1 << i)) | ||
896 | i++; | ||
897 | |||
898 | /* If valid value */ | ||
899 | if (xferunit == (1 << i)) | ||
900 | ch->rqcfg.brst_size = i; | ||
901 | else | ||
902 | ret = -EINVAL; | ||
903 | |||
904 | cfg_exit: | ||
905 | spin_unlock_irqrestore(&res_lock, flags); | ||
906 | |||
907 | return ret; | ||
908 | } | ||
909 | EXPORT_SYMBOL(s3c2410_dma_config); | ||
910 | |||
911 | /* Options that are supported by this driver */ | ||
912 | #define S3C_PL330_FLAGS (S3C2410_DMAF_CIRCULAR | S3C2410_DMAF_AUTOSTART) | ||
913 | |||
914 | int s3c2410_dma_setflags(enum dma_ch id, unsigned int options) | ||
915 | { | ||
916 | struct s3c_pl330_chan *ch; | ||
917 | unsigned long flags; | ||
918 | int ret = 0; | ||
919 | |||
920 | spin_lock_irqsave(&res_lock, flags); | ||
921 | |||
922 | ch = id_to_chan(id); | ||
923 | |||
924 | if (!ch || chan_free(ch) || options & ~(S3C_PL330_FLAGS)) | ||
925 | ret = -EINVAL; | ||
926 | else | ||
927 | ch->options = options; | ||
928 | |||
929 | spin_unlock_irqrestore(&res_lock, flags); | ||
930 | |||
931 | return 0; | ||
932 | } | ||
933 | EXPORT_SYMBOL(s3c2410_dma_setflags); | ||
934 | |||
935 | int s3c2410_dma_set_buffdone_fn(enum dma_ch id, s3c2410_dma_cbfn_t rtn) | ||
936 | { | ||
937 | struct s3c_pl330_chan *ch; | ||
938 | unsigned long flags; | ||
939 | int ret = 0; | ||
940 | |||
941 | spin_lock_irqsave(&res_lock, flags); | ||
942 | |||
943 | ch = id_to_chan(id); | ||
944 | |||
945 | if (!ch || chan_free(ch)) | ||
946 | ret = -EINVAL; | ||
947 | else | ||
948 | ch->callback_fn = rtn; | ||
949 | |||
950 | spin_unlock_irqrestore(&res_lock, flags); | ||
951 | |||
952 | return ret; | ||
953 | } | ||
954 | EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn); | ||
955 | |||
956 | int s3c2410_dma_devconfig(enum dma_ch id, enum s3c2410_dmasrc source, | ||
957 | unsigned long address) | ||
958 | { | ||
959 | struct s3c_pl330_chan *ch; | ||
960 | unsigned long flags; | ||
961 | int ret = 0; | ||
962 | |||
963 | spin_lock_irqsave(&res_lock, flags); | ||
964 | |||
965 | ch = id_to_chan(id); | ||
966 | |||
967 | if (!ch || chan_free(ch)) { | ||
968 | ret = -EINVAL; | ||
969 | goto devcfg_exit; | ||
970 | } | ||
971 | |||
972 | switch (source) { | ||
973 | case S3C2410_DMASRC_HW: /* P->M */ | ||
974 | ch->req[0].rqtype = DEVTOMEM; | ||
975 | ch->req[1].rqtype = DEVTOMEM; | ||
976 | ch->rqcfg.src_inc = 0; | ||
977 | ch->rqcfg.dst_inc = 1; | ||
978 | break; | ||
979 | case S3C2410_DMASRC_MEM: /* M->P */ | ||
980 | ch->req[0].rqtype = MEMTODEV; | ||
981 | ch->req[1].rqtype = MEMTODEV; | ||
982 | ch->rqcfg.src_inc = 1; | ||
983 | ch->rqcfg.dst_inc = 0; | ||
984 | break; | ||
985 | default: | ||
986 | ret = -EINVAL; | ||
987 | goto devcfg_exit; | ||
988 | } | ||
989 | |||
990 | ch->sdaddr = address; | ||
991 | |||
992 | devcfg_exit: | ||
993 | spin_unlock_irqrestore(&res_lock, flags); | ||
994 | |||
995 | return ret; | ||
996 | } | ||
997 | EXPORT_SYMBOL(s3c2410_dma_devconfig); | ||
998 | |||
999 | int s3c2410_dma_getposition(enum dma_ch id, dma_addr_t *src, dma_addr_t *dst) | ||
1000 | { | ||
1001 | struct s3c_pl330_chan *ch = id_to_chan(id); | ||
1002 | struct pl330_chanstatus status; | ||
1003 | int ret; | ||
1004 | |||
1005 | if (!ch || chan_free(ch)) | ||
1006 | return -EINVAL; | ||
1007 | |||
1008 | ret = pl330_chan_status(ch->pl330_chan_id, &status); | ||
1009 | if (ret < 0) | ||
1010 | return ret; | ||
1011 | |||
1012 | *src = status.src_addr; | ||
1013 | *dst = status.dst_addr; | ||
1014 | |||
1015 | return 0; | ||
1016 | } | ||
1017 | EXPORT_SYMBOL(s3c2410_dma_getposition); | ||
1018 | |||
1019 | static irqreturn_t pl330_irq_handler(int irq, void *data) | ||
1020 | { | ||
1021 | if (pl330_update(data)) | ||
1022 | return IRQ_HANDLED; | ||
1023 | else | ||
1024 | return IRQ_NONE; | ||
1025 | } | ||
1026 | |||
1027 | static int pl330_probe(struct platform_device *pdev) | ||
1028 | { | ||
1029 | struct s3c_pl330_dmac *s3c_pl330_dmac; | ||
1030 | struct s3c_pl330_platdata *pl330pd; | ||
1031 | struct pl330_info *pl330_info; | ||
1032 | struct resource *res; | ||
1033 | int i, ret, irq; | ||
1034 | |||
1035 | pl330pd = pdev->dev.platform_data; | ||
1036 | |||
1037 | /* Can't do without the list of _32_ peripherals */ | ||
1038 | if (!pl330pd || !pl330pd->peri) { | ||
1039 | dev_err(&pdev->dev, "platform data missing!\n"); | ||
1040 | return -ENODEV; | ||
1041 | } | ||
1042 | |||
1043 | pl330_info = kzalloc(sizeof(*pl330_info), GFP_KERNEL); | ||
1044 | if (!pl330_info) | ||
1045 | return -ENOMEM; | ||
1046 | |||
1047 | pl330_info->pl330_data = NULL; | ||
1048 | pl330_info->dev = &pdev->dev; | ||
1049 | |||
1050 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
1051 | if (!res) { | ||
1052 | ret = -ENODEV; | ||
1053 | goto probe_err1; | ||
1054 | } | ||
1055 | |||
1056 | request_mem_region(res->start, resource_size(res), pdev->name); | ||
1057 | |||
1058 | pl330_info->base = ioremap(res->start, resource_size(res)); | ||
1059 | if (!pl330_info->base) { | ||
1060 | ret = -ENXIO; | ||
1061 | goto probe_err2; | ||
1062 | } | ||
1063 | |||
1064 | irq = platform_get_irq(pdev, 0); | ||
1065 | if (irq < 0) { | ||
1066 | ret = irq; | ||
1067 | goto probe_err3; | ||
1068 | } | ||
1069 | |||
1070 | ret = request_irq(irq, pl330_irq_handler, 0, | ||
1071 | dev_name(&pdev->dev), pl330_info); | ||
1072 | if (ret) | ||
1073 | goto probe_err4; | ||
1074 | |||
1075 | ret = pl330_add(pl330_info); | ||
1076 | if (ret) | ||
1077 | goto probe_err5; | ||
1078 | |||
1079 | /* Allocate a new DMAC */ | ||
1080 | s3c_pl330_dmac = kmalloc(sizeof(*s3c_pl330_dmac), GFP_KERNEL); | ||
1081 | if (!s3c_pl330_dmac) { | ||
1082 | ret = -ENOMEM; | ||
1083 | goto probe_err6; | ||
1084 | } | ||
1085 | |||
1086 | /* Hook the info */ | ||
1087 | s3c_pl330_dmac->pi = pl330_info; | ||
1088 | |||
1089 | /* No busy channels */ | ||
1090 | s3c_pl330_dmac->busy_chan = 0; | ||
1091 | |||
1092 | s3c_pl330_dmac->kmcache = kmem_cache_create(dev_name(&pdev->dev), | ||
1093 | sizeof(struct s3c_pl330_xfer), 0, 0, NULL); | ||
1094 | |||
1095 | if (!s3c_pl330_dmac->kmcache) { | ||
1096 | ret = -ENOMEM; | ||
1097 | goto probe_err7; | ||
1098 | } | ||
1099 | |||
1100 | /* Get the list of peripherals */ | ||
1101 | s3c_pl330_dmac->peri = pl330pd->peri; | ||
1102 | |||
1103 | /* Attach to the list of DMACs */ | ||
1104 | list_add_tail(&s3c_pl330_dmac->node, &dmac_list); | ||
1105 | |||
1106 | /* Create a channel for each peripheral in the DMAC | ||
1107 | * that is, if it doesn't already exist | ||
1108 | */ | ||
1109 | for (i = 0; i < PL330_MAX_PERI; i++) | ||
1110 | if (s3c_pl330_dmac->peri[i] != DMACH_MAX) | ||
1111 | chan_add(s3c_pl330_dmac->peri[i]); | ||
1112 | |||
1113 | printk(KERN_INFO | ||
1114 | "Loaded driver for PL330 DMAC-%d %s\n", pdev->id, pdev->name); | ||
1115 | printk(KERN_INFO | ||
1116 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | ||
1117 | pl330_info->pcfg.data_buf_dep, | ||
1118 | pl330_info->pcfg.data_bus_width / 8, pl330_info->pcfg.num_chan, | ||
1119 | pl330_info->pcfg.num_peri, pl330_info->pcfg.num_events); | ||
1120 | |||
1121 | return 0; | ||
1122 | |||
1123 | probe_err7: | ||
1124 | kfree(s3c_pl330_dmac); | ||
1125 | probe_err6: | ||
1126 | pl330_del(pl330_info); | ||
1127 | probe_err5: | ||
1128 | free_irq(irq, pl330_info); | ||
1129 | probe_err4: | ||
1130 | probe_err3: | ||
1131 | iounmap(pl330_info->base); | ||
1132 | probe_err2: | ||
1133 | release_mem_region(res->start, resource_size(res)); | ||
1134 | probe_err1: | ||
1135 | kfree(pl330_info); | ||
1136 | |||
1137 | return ret; | ||
1138 | } | ||
1139 | |||
1140 | static int pl330_remove(struct platform_device *pdev) | ||
1141 | { | ||
1142 | struct s3c_pl330_dmac *dmac, *d; | ||
1143 | struct s3c_pl330_chan *ch; | ||
1144 | unsigned long flags; | ||
1145 | int del, found; | ||
1146 | |||
1147 | if (!pdev->dev.platform_data) | ||
1148 | return -EINVAL; | ||
1149 | |||
1150 | spin_lock_irqsave(&res_lock, flags); | ||
1151 | |||
1152 | found = 0; | ||
1153 | list_for_each_entry(d, &dmac_list, node) | ||
1154 | if (d->pi->dev == &pdev->dev) { | ||
1155 | found = 1; | ||
1156 | break; | ||
1157 | } | ||
1158 | |||
1159 | if (!found) { | ||
1160 | spin_unlock_irqrestore(&res_lock, flags); | ||
1161 | return 0; | ||
1162 | } | ||
1163 | |||
1164 | dmac = d; | ||
1165 | |||
1166 | /* Remove all Channels that are managed only by this DMAC */ | ||
1167 | list_for_each_entry(ch, &chan_list, node) { | ||
1168 | |||
1169 | /* Only channels that are handled by this DMAC */ | ||
1170 | if (iface_of_dmac(dmac, ch->id)) | ||
1171 | del = 1; | ||
1172 | else | ||
1173 | continue; | ||
1174 | |||
1175 | /* Don't remove if some other DMAC has it too */ | ||
1176 | list_for_each_entry(d, &dmac_list, node) | ||
1177 | if (d != dmac && iface_of_dmac(d, ch->id)) { | ||
1178 | del = 0; | ||
1179 | break; | ||
1180 | } | ||
1181 | |||
1182 | if (del) { | ||
1183 | spin_unlock_irqrestore(&res_lock, flags); | ||
1184 | s3c2410_dma_free(ch->id, ch->client); | ||
1185 | spin_lock_irqsave(&res_lock, flags); | ||
1186 | list_del(&ch->node); | ||
1187 | kfree(ch); | ||
1188 | } | ||
1189 | } | ||
1190 | |||
1191 | /* Remove the DMAC */ | ||
1192 | list_del(&dmac->node); | ||
1193 | kfree(dmac); | ||
1194 | |||
1195 | spin_unlock_irqrestore(&res_lock, flags); | ||
1196 | |||
1197 | return 0; | ||
1198 | } | ||
1199 | |||
1200 | static struct platform_driver pl330_driver = { | ||
1201 | .driver = { | ||
1202 | .owner = THIS_MODULE, | ||
1203 | .name = "s3c-pl330", | ||
1204 | }, | ||
1205 | .probe = pl330_probe, | ||
1206 | .remove = pl330_remove, | ||
1207 | }; | ||
1208 | |||
1209 | static int __init pl330_init(void) | ||
1210 | { | ||
1211 | return platform_driver_register(&pl330_driver); | ||
1212 | } | ||
1213 | module_init(pl330_init); | ||
1214 | |||
1215 | static void __exit pl330_exit(void) | ||
1216 | { | ||
1217 | platform_driver_unregister(&pl330_driver); | ||
1218 | return; | ||
1219 | } | ||
1220 | module_exit(pl330_exit); | ||
1221 | |||
1222 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | ||
1223 | MODULE_DESCRIPTION("Driver for PL330 DMA Controller"); | ||
1224 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 3d1ade2e5196..6c0f1712f55b 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig | |||
@@ -142,8 +142,8 @@ config TOUCHSCREEN_FUJITSU | |||
142 | module will be called fujitsu-ts. | 142 | module will be called fujitsu-ts. |
143 | 143 | ||
144 | config TOUCHSCREEN_S3C2410 | 144 | config TOUCHSCREEN_S3C2410 |
145 | tristate "Samsung S3C2410 touchscreen input driver" | 145 | tristate "Samsung S3C2410/generic touchscreen input driver" |
146 | depends on ARCH_S3C2410 | 146 | depends on ARCH_S3C2410 || SAMSUNG_DEV_TS |
147 | select S3C24XX_ADC | 147 | select S3C24XX_ADC |
148 | help | 148 | help |
149 | Say Y here if you have the s3c2410 touchscreen. | 149 | Say Y here if you have the s3c2410 touchscreen. |
diff --git a/drivers/input/touchscreen/s3c2410_ts.c b/drivers/input/touchscreen/s3c2410_ts.c index 98a7d1279486..e0b7c834111d 100644 --- a/drivers/input/touchscreen/s3c2410_ts.c +++ b/drivers/input/touchscreen/s3c2410_ts.c | |||
@@ -37,9 +37,7 @@ | |||
37 | 37 | ||
38 | #include <plat/adc.h> | 38 | #include <plat/adc.h> |
39 | #include <plat/regs-adc.h> | 39 | #include <plat/regs-adc.h> |
40 | 40 | #include <plat/ts.h> | |
41 | #include <mach/regs-gpio.h> | ||
42 | #include <mach/ts.h> | ||
43 | 41 | ||
44 | #define TSC_SLEEP (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0)) | 42 | #define TSC_SLEEP (S3C2410_ADCTSC_PULL_UP_DISABLE | S3C2410_ADCTSC_XY_PST(0)) |
45 | 43 | ||
@@ -57,6 +55,8 @@ | |||
57 | S3C2410_ADCTSC_AUTO_PST | \ | 55 | S3C2410_ADCTSC_AUTO_PST | \ |
58 | S3C2410_ADCTSC_XY_PST(0)) | 56 | S3C2410_ADCTSC_XY_PST(0)) |
59 | 57 | ||
58 | #define FEAT_PEN_IRQ (1 << 0) /* HAS ADCCLRINTPNDNUP */ | ||
59 | |||
60 | /* Per-touchscreen data. */ | 60 | /* Per-touchscreen data. */ |
61 | 61 | ||
62 | /** | 62 | /** |
@@ -71,6 +71,7 @@ | |||
71 | * @irq_tc: The interrupt number for pen up/down interrupt | 71 | * @irq_tc: The interrupt number for pen up/down interrupt |
72 | * @count: The number of samples collected. | 72 | * @count: The number of samples collected. |
73 | * @shift: The log2 of the maximum count to read in one go. | 73 | * @shift: The log2 of the maximum count to read in one go. |
74 | * @features: The features supported by the TSADC MOdule. | ||
74 | */ | 75 | */ |
75 | struct s3c2410ts { | 76 | struct s3c2410ts { |
76 | struct s3c_adc_client *client; | 77 | struct s3c_adc_client *client; |
@@ -83,26 +84,12 @@ struct s3c2410ts { | |||
83 | int irq_tc; | 84 | int irq_tc; |
84 | int count; | 85 | int count; |
85 | int shift; | 86 | int shift; |
87 | int features; | ||
86 | }; | 88 | }; |
87 | 89 | ||
88 | static struct s3c2410ts ts; | 90 | static struct s3c2410ts ts; |
89 | 91 | ||
90 | /** | 92 | /** |
91 | * s3c2410_ts_connect - configure gpio for s3c2410 systems | ||
92 | * | ||
93 | * Configure the GPIO for the S3C2410 system, where we have external FETs | ||
94 | * connected to the device (later systems such as the S3C2440 integrate | ||
95 | * these into the device). | ||
96 | */ | ||
97 | static inline void s3c2410_ts_connect(void) | ||
98 | { | ||
99 | s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); | ||
100 | s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); | ||
101 | s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); | ||
102 | s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); | ||
103 | } | ||
104 | |||
105 | /** | ||
106 | * get_down - return the down state of the pen | 93 | * get_down - return the down state of the pen |
107 | * @data0: The data read from ADCDAT0 register. | 94 | * @data0: The data read from ADCDAT0 register. |
108 | * @data1: The data read from ADCDAT1 register. | 95 | * @data1: The data read from ADCDAT1 register. |
@@ -188,6 +175,11 @@ static irqreturn_t stylus_irq(int irq, void *dev_id) | |||
188 | else | 175 | else |
189 | dev_info(ts.dev, "%s: count=%d\n", __func__, ts.count); | 176 | dev_info(ts.dev, "%s: count=%d\n", __func__, ts.count); |
190 | 177 | ||
178 | if (ts.features & FEAT_PEN_IRQ) { | ||
179 | /* Clear pen down/up interrupt */ | ||
180 | writel(0x0, ts.io + S3C64XX_ADCCLRINTPNDNUP); | ||
181 | } | ||
182 | |||
191 | return IRQ_HANDLED; | 183 | return IRQ_HANDLED; |
192 | } | 184 | } |
193 | 185 | ||
@@ -296,9 +288,9 @@ static int __devinit s3c2410ts_probe(struct platform_device *pdev) | |||
296 | goto err_clk; | 288 | goto err_clk; |
297 | } | 289 | } |
298 | 290 | ||
299 | /* Configure the touchscreen external FETs on the S3C2410 */ | 291 | /* inititalise the gpio */ |
300 | if (!platform_get_device_id(pdev)->driver_data) | 292 | if (info->cfg_gpio) |
301 | s3c2410_ts_connect(); | 293 | info->cfg_gpio(to_platform_device(ts.dev)); |
302 | 294 | ||
303 | ts.client = s3c_adc_register(pdev, s3c24xx_ts_select, | 295 | ts.client = s3c_adc_register(pdev, s3c24xx_ts_select, |
304 | s3c24xx_ts_conversion, 1); | 296 | s3c24xx_ts_conversion, 1); |
@@ -334,6 +326,7 @@ static int __devinit s3c2410ts_probe(struct platform_device *pdev) | |||
334 | ts.input->id.version = 0x0102; | 326 | ts.input->id.version = 0x0102; |
335 | 327 | ||
336 | ts.shift = info->oversampling_shift; | 328 | ts.shift = info->oversampling_shift; |
329 | ts.features = platform_get_device_id(pdev)->driver_data; | ||
337 | 330 | ||
338 | ret = request_irq(ts.irq_tc, stylus_irq, IRQF_DISABLED, | 331 | ret = request_irq(ts.irq_tc, stylus_irq, IRQF_DISABLED, |
339 | "s3c2410_ts_pen", ts.input); | 332 | "s3c2410_ts_pen", ts.input); |
@@ -420,15 +413,14 @@ static struct dev_pm_ops s3c_ts_pmops = { | |||
420 | #endif | 413 | #endif |
421 | 414 | ||
422 | static struct platform_device_id s3cts_driver_ids[] = { | 415 | static struct platform_device_id s3cts_driver_ids[] = { |
423 | { "s3c2410-ts", 0 }, | 416 | { "s3c64xx-ts", FEAT_PEN_IRQ }, |
424 | { "s3c2440-ts", 1 }, | ||
425 | { } | 417 | { } |
426 | }; | 418 | }; |
427 | MODULE_DEVICE_TABLE(platform, s3cts_driver_ids); | 419 | MODULE_DEVICE_TABLE(platform, s3cts_driver_ids); |
428 | 420 | ||
429 | static struct platform_driver s3c_ts_driver = { | 421 | static struct platform_driver s3c_ts_driver = { |
430 | .driver = { | 422 | .driver = { |
431 | .name = "s3c24xx-ts", | 423 | .name = "samsung-ts", |
432 | .owner = THIS_MODULE, | 424 | .owner = THIS_MODULE, |
433 | #ifdef CONFIG_PM | 425 | #ifdef CONFIG_PM |
434 | .pm = &s3c_ts_pmops, | 426 | .pm = &s3c_ts_pmops, |
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 5f3f03df92e3..302836a80693 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
@@ -534,21 +534,13 @@ config SERIAL_S3C24A0 | |||
534 | Serial port support for the Samsung S3C24A0 SoC | 534 | Serial port support for the Samsung S3C24A0 SoC |
535 | 535 | ||
536 | config SERIAL_S3C6400 | 536 | config SERIAL_S3C6400 |
537 | tristate "Samsung S3C6400/S3C6410/S5P6440 Seria port support" | 537 | tristate "Samsung S3C6400/S3C6410/S5P6440/S5PC100 Serial port support" |
538 | depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440) | 538 | depends on SERIAL_SAMSUNG && (CPU_S3C6400 || CPU_S3C6410 || CPU_S5P6440 || CPU_S5PC100) |
539 | select SERIAL_SAMSUNG_UARTS_4 | 539 | select SERIAL_SAMSUNG_UARTS_4 |
540 | default y | 540 | default y |
541 | help | 541 | help |
542 | Serial port support for the Samsung S3C6400, S3C6410 and S5P6440 | 542 | Serial port support for the Samsung S3C6400, S3C6410, S5P6440 |
543 | SoCs | 543 | and S5PC100 SoCs |
544 | |||
545 | config SERIAL_S5PC100 | ||
546 | tristate "Samsung S5PC100 Serial port support" | ||
547 | depends on SERIAL_SAMSUNG && CPU_S5PC100 | ||
548 | select SERIAL_SAMSUNG_UARTS_4 | ||
549 | default y | ||
550 | help | ||
551 | Serial port support for the Samsung S5PC100 SoCs | ||
552 | 544 | ||
553 | config SERIAL_S5PV210 | 545 | config SERIAL_S5PV210 |
554 | tristate "Samsung S5PV210 Serial port support" | 546 | tristate "Samsung S5PV210 Serial port support" |
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6aa4723b74ee..328f107346c4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile | |||
@@ -44,7 +44,6 @@ obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o | |||
44 | obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o | 44 | obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o |
45 | obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o | 45 | obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o |
46 | obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o | 46 | obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o |
47 | obj-$(CONFIG_SERIAL_S5PC100) += s3c6400.o | ||
48 | obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o | 47 | obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o |
49 | obj-$(CONFIG_SERIAL_MAX3100) += max3100.o | 48 | obj-$(CONFIG_SERIAL_MAX3100) += max3100.o |
50 | obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o | 49 | obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o |