diff options
author | Brian Norris <computersforpeace@gmail.com> | 2012-09-26 19:15:27 -0400 |
---|---|---|
committer | Artem Bityutskiy <artem.bityutskiy@linux.intel.com> | 2012-11-15 08:37:46 -0500 |
commit | 30fad64325ba368ffe1f92bd37f4b96c1fa4da83 (patch) | |
tree | 8ab570d3c44de56308f198b3f0928cf1d1e066fb | |
parent | ecbcbc7b75bb1b7596fca2d588d2f7539dc4e581 (diff) |
mtd: fsl_elbc_nand: remove unnecessary badblock_pattern
Since the introduction of nand_create_default_bbt_descr() (now known as
nand_create_badblock_pattern()) in
commit 58373ff0afff4cc8ac40608872995f4d87eb72ec
nand_chip.badblock_pattern will be dynamically calculated to the same
1-byte-length pattern that is required by fsl_elbc_nand. This custom
badblock_pattern is no longer needed, then, and its removal may help
facilitate further nand_bbt.c/nand_base.c cleanup in the future (one
down, many to go?)
Anyway, with nand_bbt.c fixed, this effectively reverts:
commit 452db2724351ff3d9416a183a7955e00ab4e6ab4
[MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-rw-r--r-- | drivers/mtd/nand/fsl_elbc_nand.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index cc1480a5e4c1..4c4d3e5bca18 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c | |||
@@ -109,20 +109,6 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { | |||
109 | }; | 109 | }; |
110 | 110 | ||
111 | /* | 111 | /* |
112 | * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset | ||
113 | * 1, so we have to adjust bad block pattern. This pattern should be used for | ||
114 | * x8 chips only. So far hardware does not support x16 chips anyway. | ||
115 | */ | ||
116 | static u8 scan_ff_pattern[] = { 0xff, }; | ||
117 | |||
118 | static struct nand_bbt_descr largepage_memorybased = { | ||
119 | .options = 0, | ||
120 | .offs = 0, | ||
121 | .len = 1, | ||
122 | .pattern = scan_ff_pattern, | ||
123 | }; | ||
124 | |||
125 | /* | ||
126 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, | 112 | * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, |
127 | * interfere with ECC positions, that's why we implement our own descriptors. | 113 | * interfere with ECC positions, that's why we implement our own descriptors. |
128 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. | 114 | * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. |
@@ -699,7 +685,6 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd) | |||
699 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? | 685 | chip->ecc.layout = (priv->fmr & FMR_ECCM) ? |
700 | &fsl_elbc_oob_lp_eccm1 : | 686 | &fsl_elbc_oob_lp_eccm1 : |
701 | &fsl_elbc_oob_lp_eccm0; | 687 | &fsl_elbc_oob_lp_eccm0; |
702 | chip->badblock_pattern = &largepage_memorybased; | ||
703 | } | 688 | } |
704 | } else { | 689 | } else { |
705 | dev_err(priv->dev, | 690 | dev_err(priv->dev, |