diff options
author | Magnus Damm <damm@opensource.se> | 2010-05-11 05:36:16 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-05-13 04:36:48 -0400 |
commit | 2cf79bea43491722a23b63a6f4e54d3804c10ed6 (patch) | |
tree | c59788ac87d1060cb03507da49db4f51a1acc5df | |
parent | 4a81fe625efc8b9122eb4473dab31fa90e07a381 (diff) |
sh: switch sh7786 to clkdev
This patch converts the remaining sh7786 clocks
to use clkdev for lookup. The now unused name
and id from struct clk are also removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7786.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c index 3ce3b5a69525..105a6d41b569 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c | |||
@@ -23,8 +23,6 @@ | |||
23 | * from the platform code. | 23 | * from the platform code. |
24 | */ | 24 | */ |
25 | static struct clk extal_clk = { | 25 | static struct clk extal_clk = { |
26 | .name = "extal", | ||
27 | .id = -1, | ||
28 | .rate = 33333333, | 26 | .rate = 33333333, |
29 | }; | 27 | }; |
30 | 28 | ||
@@ -46,8 +44,6 @@ static struct clk_ops pll_clk_ops = { | |||
46 | }; | 44 | }; |
47 | 45 | ||
48 | static struct clk pll_clk = { | 46 | static struct clk pll_clk = { |
49 | .name = "pll_clk", | ||
50 | .id = -1, | ||
51 | .ops = &pll_clk_ops, | 47 | .ops = &pll_clk_ops, |
52 | .parent = &extal_clk, | 48 | .parent = &extal_clk, |
53 | .flags = CLK_ENABLE_ON_INIT, | 49 | .flags = CLK_ENABLE_ON_INIT, |
@@ -133,6 +129,10 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
133 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } | 129 | #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
134 | 130 | ||
135 | static struct clk_lookup lookups[] = { | 131 | static struct clk_lookup lookups[] = { |
132 | /* main clocks */ | ||
133 | CLKDEV_CON_ID("extal", &extal_clk), | ||
134 | CLKDEV_CON_ID("pll_clk", &pll_clk), | ||
135 | |||
136 | /* DIV4 clocks */ | 136 | /* DIV4 clocks */ |
137 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | 137 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), |
138 | CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), | 138 | CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]), |