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authorDavid Brown <davidb@codeaurora.org>2012-04-23 18:34:20 -0400
committerDavid Brown <davidb@codeaurora.org>2012-04-23 19:13:27 -0400
commit2b7b9a7d6c676691cd746a654e2c3b06a6feb9ba (patch)
tree9c9a88747f9db48d8aefbf59615009d2f0fba290
parentaf33eadc73e4a5d35a966c1c7ffe28a8424c9d96 (diff)
ARM: msm: Fix gic irqdomain support
As of commit 75294957be1dee7d22dd7d90bd31334ba410e836 Author: Grant Likely <grant.likely@secretlab.ca> Date: Tue Feb 14 14:06:57 2012 -0700 irq_domain: Remove 'new' irq_domain in favour of the ppc one the ARM gic controller uses proper irq domains. Fix the MSM gic initialization and DT so that it works again. Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Grant Likely <grant.likely@secretlab.ca>
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts4
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c25
2 files changed, 17 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 15ded0deaa79..45bc4bb04e57 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -10,7 +10,7 @@
10 intc: interrupt-controller@02080000 { 10 intc: interrupt-controller@02080000 {
11 compatible = "qcom,msm-8660-qgic"; 11 compatible = "qcom,msm-8660-qgic";
12 interrupt-controller; 12 interrupt-controller;
13 #interrupt-cells = <1>; 13 #interrupt-cells = <3>;
14 reg = < 0x02080000 0x1000 >, 14 reg = < 0x02080000 0x1000 >,
15 < 0x02081000 0x1000 >; 15 < 0x02081000 0x1000 >;
16 }; 16 };
@@ -19,6 +19,6 @@
19 compatible = "qcom,msm-hsuart", "qcom,msm-uart"; 19 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
20 reg = <0x19c40000 0x1000>, 20 reg = <0x19c40000 0x1000>,
21 <0x19c00000 0x1000>; 21 <0x19c00000 0x1000>;
22 interrupts = <195>; 22 interrupts = <0 195 0x0>;
23 }; 23 };
24}; 24};
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e71169750..fb3496a52ef4 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -17,6 +17,7 @@
17#include <linux/irqdomain.h> 17#include <linux/irqdomain.h>
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/of_irq.h>
20#include <linux/of_platform.h> 21#include <linux/of_platform.h>
21#include <linux/memblock.h> 22#include <linux/memblock.h>
22 23
@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
49 msm_map_msm8x60_io(); 50 msm_map_msm8x60_io();
50} 51}
51 52
53#ifdef CONFIG_OF
54static struct of_device_id msm_dt_gic_match[] __initdata = {
55 { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
56 {}
57};
58#endif
59
52static void __init msm8x60_init_irq(void) 60static void __init msm8x60_init_irq(void)
53{ 61{
54 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, 62 if (!of_have_populated_dt())
55 (void *)MSM_QGIC_CPU_BASE); 63 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
64 (void *)MSM_QGIC_CPU_BASE);
65#ifdef CONFIG_OF
66 else
67 of_irq_init(msm_dt_gic_match);
68#endif
56 69
57 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ 70 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
58 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); 71 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
73 {} 86 {}
74}; 87};
75 88
76static struct of_device_id msm_dt_gic_match[] __initdata = {
77 { .compatible = "qcom,msm-8660-qgic", },
78 {}
79};
80
81static void __init msm8x60_dt_init(void) 89static void __init msm8x60_dt_init(void)
82{ 90{
83 irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
84 GIC_SPI_START);
85
86 if (of_machine_is_compatible("qcom,msm8660-surf")) { 91 if (of_machine_is_compatible("qcom,msm8660-surf")) {
87 printk(KERN_INFO "Init surf UART registers\n"); 92 printk(KERN_INFO "Init surf UART registers\n");
88 msm8x60_init_uart12dm(); 93 msm8x60_init_uart12dm();