Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM soc device tree updates from Olof Johansson:
 "Device tree conversion and enablement branch.  Mostly a bunch of new
  bindings and setup for various platforms, but the Via/Winchip VT8500
  platform is also converted over from being 100% legacy to now use
  device tree for probing.  More of that will come for 3.8."

Trivial conflicts due to removal of vt8500 files, and one documentation
file that was added with slightly different contents both here and in
the USb tree.

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits)
  arm: vt8500: Fixup for missing gpio.h
  ARM: LPC32xx: LED fix in PHY3250 DTS file
  ARM: dt: mmp-dma: add binding file
  arm: vt8500: Update arch-vt8500 to devicetree support.
  arm: vt8500: gpio: Devicetree support for arch-vt8500
  arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
  arm: vt8500: clk: Add Common Clock Framework support
  video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
  serial: vt8500: Add devicetree support for vt8500-serial
  rtc: vt8500: Add devicetree support for vt8500-rtc
  arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
  ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
  ARM: tegra: Add Avionic Design Medcom-Wide support
  ARM: tegra: Add Avionic Design Plutux support
  ARM: tegra: Add Avionic Design Tamonten support
  ARM: tegra: dts: Add pwm label
  ARM: ux500: Fix SSP register address format
  ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT
  ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT
  ARM: ux500: Add all encompassing sound node to the HREF Device Tree
  ...

269 files changed, 10743 insertions, 11219 deletions

diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
new file mode 100644
index 000000000000..31af1cbb60bd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
@@ -0,0 +1,17 @@
+* Marvell Tauros2 Cache
+
+Required properties:
+- compatible : Should be "marvell,tauros2-cache".
+- marvell,tauros2-cache-features : Specify the features supported for the
+  tauros2 cache.
+  The features including
+    CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
+    CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
+  The definition can be found at
+  arch/arm/include/asm/hardware/cache-tauros2.h
+
+Example:
+        L2: l2-cache {
+                compatible = "marvell,tauros2-cache";
+                marvell,tauros2-cache-features = <0x3>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/msm/timer.txt b/Documentation/devicetree/bindings/arm/msm/timer.txt
new file mode 100644
index 000000000000..8c5907b9cae8
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
@@ -0,0 +1,38 @@
+* MSM Timer
+
+Properties:
+
+- compatible : Should at least contain "qcom,msm-timer". More specific
+  properties such as "qcom,msm-gpt" and "qcom,msm-dgt" specify a general
+  purpose timer and a debug timer respectively.
+
+- interrupts : Interrupt indicating a match event.
+
+- reg : Specifies the base address of the timer registers. The second region
+  specifies an optional register used to configure the clock divider.
+
+- clock-frequency : The frequency of the timer in Hz.
+
+Optional:
+
+- cpu-offset : per-cpu offset used when the timer is accessed without the
+  CPU remapping facilities. The offset is cpu-offset * cpu-nr.
+
+Example:
+
+       timer@200a004 {
+               compatible = "qcom,msm-gpt", "qcom,msm-timer";
+               interrupts = <1 2 0x301>;
+               reg = <0x0200a004 0x10>;
+               clock-frequency = <32768>;
+               cpu-offset = <0x40000>;
+       };
+
+       timer@200a024 {
+               compatible = "qcom,msm-dgt", "qcom,msm-timer";
+               interrupts = <1 3 0x301>;
+               reg = <0x0200a024 0x10>,
+                     <0x0200a034 0x4>;
+               clock-frequency = <6750000>;
+               cpu-offset = <0x40000>;
+       };
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index ccdd0e53451f..d0051a750587 100644
--- a/Documentation/devicetree/bindings/arm/omap/omap.txt
+++ b/Documentation/devicetree/bindings/arm/omap/omap.txt
@@ -36,6 +36,9 @@ Boards:
 - OMAP3 BeagleBoard : Low cost community board
   compatible = "ti,omap3-beagle", "ti,omap3"
 
+- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
+  compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3"
+
 - OMAP4 SDP : Software Developement Board
   compatible = "ti,omap4-sdp", "ti,omap4430"
 
diff --git a/Documentation/devicetree/bindings/arm/vt8500.txt b/Documentation/devicetree/bindings/arm/vt8500.txt
new file mode 100644
index 000000000000..d657832c6819
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500.txt
@@ -0,0 +1,14 @@
+VIA/Wondermedia VT8500 Platforms Device Tree Bindings
+---------------------------------------
+
+Boards with the VIA VT8500 SoC shall have the following properties:
+Required root node property:
+compatible = "via,vt8500";
+
+Boards with the Wondermedia WM8505 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8505";
+
+Boards with the Wondermedia WM8650 SoC shall have the following properties:
+Required root node property:
+compatible = "wm,wm8650";
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
new file mode 100644
index 000000000000..0a4ce1051b02
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-intc.txt
@@ -0,0 +1,16 @@
+VIA/Wondermedia VT8500 Interrupt Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-intc"
+- reg : Should contain 1 register ranges(address and length)
+- #interrupt-cells : should be <1>
+
+Example:
+
+        intc: interrupt-controller@d8140000 {
+                compatible = "via,vt8500-intc";
+                interrupt-controller;
+                reg = <0xd8140000 0x10000>;
+                #interrupt-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
new file mode 100644
index 000000000000..521b9c7de933
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-pmc.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia VT8500 Power Management Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-pmc"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+        pmc@d8130000 {
+                compatible = "via,vt8500-pmc";
+                reg = <0xd8130000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
new file mode 100644
index 000000000000..901c73f0d8ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vt8500/via,vt8500-timer.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Timer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-timer"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : interrupt for the timer
+
+Example:
+
+        timer@d8130100 {
+                compatible = "via,vt8500-timer";
+                reg = <0xd8130100 0x28>;
+                interrupts = <36>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
new file mode 100644
index 000000000000..a0b867ef8d96
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -0,0 +1,76 @@
+* Clock bindings for Freescale i.MX23
+
+Required properties:
+- compatible: Should be "fsl,imx23-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX23
+clocks and IDs.
+
+        Clock           ID
+        ------------------
+        ref_xtal        0
+        pll             1
+        ref_cpu         2
+        ref_emi         3
+        ref_pix         4
+        ref_io          5
+        saif_sel        6
+        lcdif_sel       7
+        gpmi_sel        8
+        ssp_sel         9
+        emi_sel         10
+        cpu             11
+        etm_sel         12
+        cpu_pll         13
+        cpu_xtal        14
+        hbus            15
+        xbus            16
+        lcdif_div       17
+        ssp_div         18
+        gpmi_div        19
+        emi_pll         20
+        emi_xtal        21
+        etm_div         22
+        saif_div        23
+        clk32k_div      24
+        rtc             25
+        adc             26
+        spdif_div       27
+        clk32k          28
+        dri             29
+        pwm             30
+        filt            31
+        uart            32
+        ssp             33
+        gpmi            34
+        spdif           35
+        emi             36
+        saif            37
+        lcdif           38
+        etm             39
+        usb             40
+        usb_pwr         41
+
+Examples:
+
+clks: clkctrl@80040000 {
+        compatible = "fsl,imx23-clkctrl";
+        reg = <0x80040000 0x2000>;
+        #clock-cells = <1>;
+        clock-output-names =
+                ...
+                "uart",         /* 32 */
+                ...
+                "end_of_list";
+};
+
+auart0: serial@8006c000 {
+        compatible = "fsl,imx23-auart";
+        reg = <0x8006c000 0x2000>;
+        interrupts = <24 25 23>;
+        clocks = <&clks 32>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
new file mode 100644
index 000000000000..aa2af2866fe8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -0,0 +1,99 @@
+* Clock bindings for Freescale i.MX28
+
+Required properties:
+- compatible: Should be "fsl,imx28-clkctrl"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX28
+clocks and IDs.
+
+        Clock           ID
+        ------------------
+        ref_xtal        0
+        pll0            1
+        pll1            2
+        pll2            3
+        ref_cpu         4
+        ref_emi         5
+        ref_io0         6
+        ref_io1         7
+        ref_pix         8
+        ref_hsadc       9
+        ref_gpmi        10
+        saif0_sel       11
+        saif1_sel       12
+        gpmi_sel        13
+        ssp0_sel        14
+        ssp1_sel        15
+        ssp2_sel        16
+        ssp3_sel        17
+        emi_sel         18
+        etm_sel         19
+        lcdif_sel       20
+        cpu             21
+        ptp_sel         22
+        cpu_pll         23
+        cpu_xtal        24
+        hbus            25
+        xbus            26
+        ssp0_div        27
+        ssp1_div        28
+        ssp2_div        29
+        ssp3_div        30
+        gpmi_div        31
+        emi_pll         32
+        emi_xtal        33
+        lcdif_div       34
+        etm_div         35
+        ptp             36
+        saif0_div       37
+        saif1_div       38
+        clk32k_div      39
+        rtc             40
+        lradc           41
+        spdif_div       42
+        clk32k          43
+        pwm             44
+        uart            45
+        ssp0            46
+        ssp1            47
+        ssp2            48
+        ssp3            49
+        gpmi            50
+        spdif           51
+        emi             52
+        saif0           53
+        saif1           54
+        lcdif           55
+        etm             56
+        fec             57
+        can0            58
+        can1            59
+        usb0            60
+        usb1            61
+        usb0_pwr        62
+        usb1_pwr        63
+        enet_out        64
+
+Examples:
+
+clks: clkctrl@80040000 {
+        compatible = "fsl,imx28-clkctrl";
+        reg = <0x80040000 0x2000>;
+        #clock-cells = <1>;
+        clock-output-names =
+                ...
+                "uart",         /* 45 */
+                ...
+                "end_of_list";
+};
+
+auart0: serial@8006a000 {
+        compatible = "fsl,imx28-auart", "fsl,imx23-auart";
+        reg = <0x8006a000 0x2000>;
+        interrupts = <112 70 71>;
+        clocks = <&clks 45>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
new file mode 100644
index 000000000000..492bd991d52a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -0,0 +1,222 @@
+* Clock bindings for Freescale i.MX6 Quad
+
+Required properties:
+- compatible: Should be "fsl,imx6q-ccm"
+- reg: Address and length of the register set
+- interrupts: Should contain CCM interrupt
+- #clock-cells: Should be <1>
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell.  The following is a full list of i.MX6Q
+clocks and IDs.
+
+        Clock                   ID
+        ---------------------------
+        dummy                   0
+        ckil                    1
+        ckih                    2
+        osc                     3
+        pll2_pfd0_352m          4
+        pll2_pfd1_594m          5
+        pll2_pfd2_396m          6
+        pll3_pfd0_720m          7
+        pll3_pfd1_540m          8
+        pll3_pfd2_508m          9
+        pll3_pfd3_454m          10
+        pll2_198m               11
+        pll3_120m               12
+        pll3_80m                13
+        pll3_60m                14
+        twd                     15
+        step                    16
+        pll1_sw                 17
+        periph_pre              18
+        periph2_pre             19
+        periph_clk2_sel         20
+        periph2_clk2_sel        21
+        axi_sel                 22
+        esai_sel                23
+        asrc_sel                24
+        spdif_sel               25
+        gpu2d_axi               26
+        gpu3d_axi               27
+        gpu2d_core_sel          28
+        gpu3d_core_sel          29
+        gpu3d_shader_sel        30
+        ipu1_sel                31
+        ipu2_sel                32
+        ldb_di0_sel             33
+        ldb_di1_sel             34
+        ipu1_di0_pre_sel        35
+        ipu1_di1_pre_sel        36
+        ipu2_di0_pre_sel        37
+        ipu2_di1_pre_sel        38
+        ipu1_di0_sel            39
+        ipu1_di1_sel            40
+        ipu2_di0_sel            41
+        ipu2_di1_sel            42
+        hsi_tx_sel              43
+        pcie_axi_sel            44
+        ssi1_sel                45
+        ssi2_sel                46
+        ssi3_sel                47
+        usdhc1_sel              48
+        usdhc2_sel              49
+        usdhc3_sel              50
+        usdhc4_sel              51
+        enfc_sel                52
+        emi_sel                 53
+        emi_slow_sel            54
+        vdo_axi_sel             55
+        vpu_axi_sel             56
+        cko1_sel                57
+        periph                  58
+        periph2                 59
+        periph_clk2             60
+        periph2_clk2            61
+        ipg                     62
+        ipg_per                 63
+        esai_pred               64
+        esai_podf               65
+        asrc_pred               66
+        asrc_podf               67
+        spdif_pred              68
+        spdif_podf              69
+        can_root                70
+        ecspi_root              71
+        gpu2d_core_podf         72
+        gpu3d_core_podf         73
+        gpu3d_shader            74
+        ipu1_podf               75
+        ipu2_podf               76
+        ldb_di0_podf            77
+        ldb_di1_podf            78
+        ipu1_di0_pre            79
+        ipu1_di1_pre            80
+        ipu2_di0_pre            81
+        ipu2_di1_pre            82
+        hsi_tx_podf             83
+        ssi1_pred               84
+        ssi1_podf               85
+        ssi2_pred               86
+        ssi2_podf               87
+        ssi3_pred               88
+        ssi3_podf               89
+        uart_serial_podf        90
+        usdhc1_podf             91
+        usdhc2_podf             92
+        usdhc3_podf             93
+        usdhc4_podf             94
+        enfc_pred               95
+        enfc_podf               96
+        emi_podf                97
+        emi_slow_podf           98
+        vpu_axi_podf            99
+        cko1_podf               100
+        axi                     101
+        mmdc_ch0_axi_podf       102
+        mmdc_ch1_axi_podf       103
+        arm                     104
+        ahb                     105
+        apbh_dma                106
+        asrc                    107
+        can1_ipg                108
+        can1_serial             109
+        can2_ipg                110
+        can2_serial             111
+        ecspi1                  112
+        ecspi2                  113
+        ecspi3                  114
+        ecspi4                  115
+        ecspi5                  116
+        enet                    117
+        esai                    118
+        gpt_ipg                 119
+        gpt_ipg_per             120
+        gpu2d_core              121
+        gpu3d_core              122
+        hdmi_iahb               123
+        hdmi_isfr               124
+        i2c1                    125
+        i2c2                    126
+        i2c3                    127
+        iim                     128
+        enfc                    129
+        ipu1                    130
+        ipu1_di0                131
+        ipu1_di1                132
+        ipu2                    133
+        ipu2_di0                134
+        ldb_di0                 135
+        ldb_di1                 136
+        ipu2_di1                137
+        hsi_tx                  138
+        mlb                     139
+        mmdc_ch0_axi            140
+        mmdc_ch1_axi            141
+        ocram                   142
+        openvg_axi              143
+        pcie_axi                144
+        pwm1                    145
+        pwm2                    146
+        pwm3                    147
+        pwm4                    148
+        per1_bch                149
+        gpmi_bch_apb            150
+        gpmi_bch                151
+        gpmi_io                 152
+        gpmi_apb                153
+        sata                    154
+        sdma                    155
+        spba                    156
+        ssi1                    157
+        ssi2                    158
+        ssi3                    159
+        uart_ipg                160
+        uart_serial             161
+        usboh3                  162
+        usdhc1                  163
+        usdhc2                  164
+        usdhc3                  165
+        usdhc4                  166
+        vdo_axi                 167
+        vpu_axi                 168
+        cko1                    169
+        pll1_sys                170
+        pll2_bus                171
+        pll3_usb_otg            172
+        pll4_audio              173
+        pll5_video              174
+        pll6_mlb                175
+        pll7_usb_host           176
+        pll8_enet               177
+        ssi1_ipg                178
+        ssi2_ipg                179
+        ssi3_ipg                180
+        rom                     181
+        usbphy1                 182
+        usbphy2                 183
+        ldb_di0_div_3_5         184
+        ldb_di1_div_3_5         185
+
+Examples:
+
+clks: ccm@020c4000 {
+        compatible = "fsl,imx6q-ccm";
+        reg = <0x020c4000 0x4000>;
+        interrupts = <0 87 0x04 0 88 0x04>;
+        #clock-cells = <1>;
+        clock-output-names = ...
+                             "uart_ipg",
+                             "uart_serial",
+                             ...;
+};
+
+uart1: serial@02020000 {
+        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+        reg = <0x02020000 0x4000>;
+        interrupts = <0 26 0x04>;
+        clocks = <&clks 160>, <&clks 161>;
+        clock-names = "ipg", "per";
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/clock/vt8500.txt b/Documentation/devicetree/bindings/clock/vt8500.txt
new file mode 100644
index 000000000000..a880c70d0047
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/vt8500.txt
@@ -0,0 +1,72 @@
+Device Tree Clock bindings for arch-vt8500
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+        "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
+        "wm,wm8650-pll-clock" - for a WM8650 PLL clock
+        "via,vt8500-device-clock" - for a VT/WM device clock
+
+Required properties for PLL clocks:
+- reg : shall be the control register offset from PMC base for the pll clock.
+- clocks : shall be the input parent clock phandle for the clock. This should
+        be the reference clock.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+Required properties for device clocks:
+- clocks : shall be the input parent clock phandle for the clock. This should
+        be a pll output.
+- #clock-cells : from common clock binding; shall be set to 0.
+
+
+Device Clocks
+
+Device clocks are required to have one or both of the following sets of
+properties:
+
+
+Gated device clocks:
+
+Required properties:
+- enable-reg : shall be the register offset from PMC base for the enable
+        register.
+- enable-bit : shall be the bit within enable-reg to enable/disable the clock.
+
+
+Divisor device clocks:
+
+Required property:
+- divisor-reg : shall be the register offset from PMC base for the divisor
+        register.
+Optional property:
+- divisor-mask : shall be the mask for the divisor register. Defaults to 0x1f
+        if not specified.
+
+
+For example:
+
+ref25: ref25M {
+        #clock-cells = <0>;
+        compatible = "fixed-clock";
+        clock-frequency = <25000000>;
+};
+
+plla: plla {
+        #clock-cells = <0>;
+        compatible = "wm,wm8650-pll-clock";
+        clocks = <&ref25>;
+        reg = <0x200>;
+};
+
+sdhc: sdhc {
+        #clock-cells = <0>;
+        compatible = "via,vt8500-device-clock";
+        clocks = <&pllb>;
+        divisor-reg = <0x328>;
+        divisor-mask = <0x3f>;
+        enable-reg = <0x254>;
+        enable-bit = <18>;
+};
diff --git a/Documentation/devicetree/bindings/dma/mmp-dma.txt b/Documentation/devicetree/bindings/dma/mmp-dma.txt
new file mode 100644
index 000000000000..a4fa4efa1d83
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mmp-dma.txt
@@ -0,0 +1,74 @@
+* MARVELL MMP DMA controller
+
+Marvell Peripheral DMA Controller
+Used platfroms: pxa688, pxa910, pxa3xx, etc
+
+Required properties:
+- compatible: Should be "marvell,pdma-1.0"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+                or one irq for pdma device
+- #dma-channels: Number of DMA channels supported by the controller.
+
+"marvell,pdma-1.0"
+Used platfroms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688.
+
+Examples:
+
+/*
+ * Each channel has specific irq
+ * ICU parse out irq channel from ICU register,
+ * while DMA controller may not able to distinguish the irq channel
+ * Using this method, interrupt-parent is required as demuxer
+ * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
+ * 18~21 is ADMA irq
+ */
+pdma: dma-controller@d4000000 {
+              compatible = "marvell,pdma-1.0";
+              reg = <0xd4000000 0x10000>;
+              interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
+              interrupt-parent = <&intcmux32>;
+              #dma-channels = <16>;
+      };
+
+/*
+ * One irq for all channels
+ * Dmaengine driver (DMA controller) distinguish irq channel via
+ * parsing internal register
+ */
+pdma: dma-controller@d4000000 {
+              compatible = "marvell,pdma-1.0";
+              reg = <0xd4000000 0x10000>;
+              interrupts = <47>;
+              #dma-channels = <16>;
+      };
+
+
+Marvell Two Channel DMA Controller used specifically for audio
+Used platfroms: pxa688, pxa910
+
+Required properties:
+- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ"
+- reg: Should contain DMA registers location and length.
+- interrupts: Either contain all of the per-channel DMA interrupts
+                or one irq for dma device
+
+"marvell,adma-1.0" used on pxa688
+"marvell,pxa910-squ" used on pxa910
+
+Examples:
+
+/* each channel has specific irq */
+adma0: dma-controller@d42a0800 {
+              compatible = "marvell,adma-1.0";
+              reg = <0xd42a0800 0x100>;
+              interrupts = <18 19>;
+              interrupt-parent = <&intcmux32>;
+      };
+
+/* One irq for all channels */
+squ: dma-controller@d42a0800 {
+              compatible = "marvell,pxa910-squ";
+              reg = <0xd42a0800 0x100>;
+              interrupts = <46>;
+      };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
index 5375625e8cd2..f1e5dfecf55d 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -39,3 +39,46 @@ Example:
                 #gpio-cells = <4>;
                 gpio-controller;
         };
+
+
+Samsung S3C24XX GPIO Controller
+
+Required properties:
+- compatible: Compatible property value should be "samsung,s3c24xx-gpio".
+
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+
+- #gpio-cells: Should be 3. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [flags and pull up/down]
+
+  Values for gpio specifier:
+  - Pin number: depending on the controller a number from 0 up to 15.
+  - Mux function: Depending on the SoC and the gpio bank the gpio can be set
+                  as input, output or a special function
+  - Flags and Pull Up/Down: the values to use differ for the individual SoCs
+                    example S3C2416/S3C2450:
+                            0 - Pull Up/Down Disabled.
+                            1 - Pull Down Enabled.
+                            2 - Pull Up Enabled.
+          Bit 16 (0x00010000) - Input is active low.
+  Consult the user manual for the correct values of Mux and Pull Up/Down.
+
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+
+Example:
+
+        gpa: gpio-controller@56000000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "samsung,s3c24xx-gpio";
+                reg = <0x56000000 0x10>;
+                #gpio-cells = <3>;
+                gpio-controller;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
index 16695d9cf1e8..66788fda1db3 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-twl4030.txt
@@ -11,6 +11,11 @@ Required properties:
 - interrupt-controller: Mark the device node as an interrupt controller
   The first cell is the GPIO number.
   The second cell is not used.
+- ti,use-leds : Enables LEDA and LEDB outputs if set
+- ti,debounce : if n-th bit is set, debounces GPIO-n
+- ti,mmc-cd : if n-th bit is set, GPIO-n controls VMMC(n+1)
+- ti,pullups : if n-th bit is set, set a pullup on GPIO-n
+- ti,pulldowns : if n-th bit is set, set a pulldown on GPIO-n
 
 Example:
 
@@ -20,4 +25,5 @@ twl_gpio: gpio {
     gpio-controller;
     #interrupt-cells = <2>;
     interrupt-controller;
+    ti,use-leds;
 };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
new file mode 100644
index 000000000000..f4dc5233167e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+        or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+        1) bank
+        2) pin number
+        3) flags - should be 0
+
+Example:
+
+        gpio: gpio-controller@d8110000 {
+                compatible = "via,vt8500-gpio";
+                gpio-controller;
+                reg = <0xd8110000 0x10000>;
+                #gpio-cells = <3>;
+        };
+
+        vibrate {
+                gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+        };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 1a85f986961b..2f5322b119eb 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -56,3 +56,4 @@ stm,m41t00		Serial Access TIMEKEEPER
 stm,m41t62              Serial real-time clock (RTC) with alarm
 stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
 ti,tsc2003              I2C Touch-Screen Controller
+ti,tmp102               Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
new file mode 100644
index 000000000000..9ceb19e0c7fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2-timings.txt
@@ -0,0 +1,52 @@
+* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
+
+Required properties:
+- compatible : Should be "jedec,lpddr2-timings"
+- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
+- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
+
+Optional properties:
+
+The following properties represent AC timing parameters from the memory
+data-sheet of the device for a given speed-bin. All these properties are
+of type <u32> and the default unit is ps (pico seconds). Parameters with
+a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
+- tRCD
+- tWR
+- tRAS-min
+- tRRD
+- tWTR
+- tXP
+- tRTP
+- tDQSCK-max
+- tFAW
+- tZQCS
+- tZQinit
+- tRPab
+- tZQCL
+- tCKESR
+- tRAS-max-ns
+- tDQSCK-max-derated
+
+Example:
+
+timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+        compatible      = "jedec,lpddr2-timings";
+        min-freq        = <10000000>;
+        max-freq        = <400000000>;
+        tRPab           = <21000>;
+        tRCD            = <18000>;
+        tWR             = <15000>;
+        tRAS-min        = <42000>;
+        tRRD            = <10000>;
+        tWTR            = <7500>;
+        tXP             = <7500>;
+        tRTP            = <7500>;
+        tCKESR          = <15000>;
+        tDQSCK-max      = <5500>;
+        tFAW            = <50000>;
+        tZQCS           = <90000>;
+        tZQCL           = <360000>;
+        tZQinit         = <1000000>;
+        tRAS-max-ns     = <70000>;
+};
diff --git a/Documentation/devicetree/bindings/lpddr2/lpddr2.txt b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
new file mode 100644
index 000000000000..58354a075e13
--- /dev/null
+++ b/Documentation/devicetree/bindings/lpddr2/lpddr2.txt
@@ -0,0 +1,102 @@
+* LPDDR2 SDRAM memories compliant to JEDEC JESD209-2
+
+Required properties:
+- compatible : Should be one of - "jedec,lpddr2-nvm", "jedec,lpddr2-s2",
+  "jedec,lpddr2-s4"
+
+  "ti,jedec-lpddr2-s2" should be listed if the memory part is LPDDR2-S2 type
+
+  "ti,jedec-lpddr2-s4" should be listed if the memory part is LPDDR2-S4 type
+
+  "ti,jedec-lpddr2-nvm" should be listed if the memory part is LPDDR2-NVM type
+
+- density  : <u32> representing density in Mb (Mega bits)
+
+- io-width : <u32> representing bus width. Possible values are 8, 16, and 32
+
+Optional properties:
+
+The following optional properties represent the minimum value of some AC
+timing parameters of the DDR device in terms of number of clock cycles.
+These values shall be obtained from the device data-sheet.
+- tRRD-min-tck
+- tWTR-min-tck
+- tXP-min-tck
+- tRTP-min-tck
+- tCKE-min-tck
+- tRPab-min-tck
+- tRCD-min-tck
+- tWR-min-tck
+- tRASmin-min-tck
+- tCKESR-min-tck
+- tFAW-min-tck
+
+Child nodes:
+- The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
+  "lpddr2-timings" provides AC timing parameters of the device for
+  a given speed-bin. The user may provide the timings for as many
+  speed-bins as is required. Please see Documentation/devicetree/
+  bindings/lpddr2/lpddr2-timings.txt for more information on "lpddr2-timings"
+
+Example:
+
+elpida_ECB240ABACN : lpddr2 {
+        compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+        density         = <2048>;
+        io-width        = <32>;
+
+        tRPab-min-tck   = <3>;
+        tRCD-min-tck    = <3>;
+        tWR-min-tck     = <3>;
+        tRASmin-min-tck = <3>;
+        tRRD-min-tck    = <2>;
+        tWTR-min-tck    = <2>;
+        tXP-min-tck     = <2>;
+        tRTP-min-tck    = <2>;
+        tCKE-min-tck    = <3>;
+        tCKESR-min-tck  = <3>;
+        tFAW-min-tck    = <8>;
+
+        timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+                compatible      = "jedec,lpddr2-timings";
+                min-freq        = <10000000>;
+                max-freq        = <400000000>;
+                tRPab           = <21000>;
+                tRCD            = <18000>;
+                tWR             = <15000>;
+                tRAS-min        = <42000>;
+                tRRD            = <10000>;
+                tWTR            = <7500>;
+                tXP             = <7500>;
+                tRTP            = <7500>;
+                tCKESR          = <15000>;
+                tDQSCK-max      = <5500>;
+                tFAW            = <50000>;
+                tZQCS           = <90000>;
+                tZQCL           = <360000>;
+                tZQinit         = <1000000>;
+                tRAS-max-ns     = <70000>;
+        };
+
+        timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+                compatible      = "jedec,lpddr2-timings";
+                min-freq        = <10000000>;
+                max-freq        = <200000000>;
+                tRPab           = <21000>;
+                tRCD            = <18000>;
+                tWR             = <15000>;
+                tRAS-min        = <42000>;
+                tRRD            = <10000>;
+                tWTR            = <10000>;
+                tXP             = <7500>;
+                tRTP            = <7500>;
+                tCKESR          = <15000>;
+                tDQSCK-max      = <5500>;
+                tFAW            = <50000>;
+                tZQCS           = <90000>;
+                tZQCL           = <360000>;
+                tZQinit         = <1000000>;
+                tRAS-max-ns     = <70000>;
+        };
+
+}
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
new file mode 100644
index 000000000000..938f8e1ba205
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
@@ -0,0 +1,55 @@
+* EMIF family of TI SDRAM controllers
+
+EMIF - External Memory Interface - is an SDRAM controller used in
+TI SoCs. EMIF supports, based on the IP revision, one or more of
+DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
+of the EMIF IP and memory parts attached to it.
+
+Required properties:
+- compatible    : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
+  is the IP revision of the specific EMIF instance.
+
+- phy-type      : <u32> indicating the DDR phy type. Following are the
+  allowed values
+  <1>   : Attila PHY
+  <2>   : Intelli PHY
+
+- device-handle : phandle to a "lpddr2" node representing the memory part
+
+- ti,hwmods     : For TI hwmods processing and omap device creation
+  the value shall be "emif<n>" where <n> is the number of the EMIF
+  instance with base 1.
+
+Optional properties:
+- cs1-used              : Have this property if CS1 of this EMIF
+  instance has a memory part attached to it. If there is a memory
+  part attached to CS1, it should be the same type as the one on CS0,
+  so there is no need to give the details of this memory part.
+
+- cal-resistor-per-cs   : Have this property if the board has one
+  calibration resistor per chip-select.
+
+- hw-caps-read-idle-ctrl: Have this property if the controller
+  supports read idle window programming
+
+- hw-caps-dll-calib-ctrl: Have this property if the controller
+  supports dll calibration control
+
+- hw-caps-ll-interface  : Have this property if the controller
+  has a low latency interface and corresponding interrupt events
+
+- hw-caps-temp-alert    : Have this property if the controller
+  has capability for generating SDRAM temperature alerts
+
+Example:
+
+emif1: emif@0x4c000000 {
+        compatible      = "ti,emif-4d";
+        ti,hwmods       = "emif2";
+        phy-type        = <1>;
+        device-handle   = <&elpida_ECB240ABACN>;
+        cs1-used;
+        hw-caps-read-idle-ctrl;
+        hw-caps-ll-interface;
+        hw-caps-temp-alert;
+};
diff --git a/Documentation/devicetree/bindings/mfd/ab8500.txt b/Documentation/devicetree/bindings/mfd/ab8500.txt
index 69e757a657a0..ce83c8d3c00e 100644
--- a/Documentation/devicetree/bindings/mfd/ab8500.txt
+++ b/Documentation/devicetree/bindings/mfd/ab8500.txt
@@ -23,6 +23,7 @@ Device                     IRQ Names              Supply Names   Description
 ab8500-bm                :                      :              : Battery Manager
 ab8500-btemp             :                      :              : Battery Temperature
 ab8500-charger           :                      :              : Battery Charger
+ab8500-codec             :                      :              : Audio Codec
 ab8500-fg                :                      :              : Fuel Gauge
 ab8500-gpadc             : HW_CONV_END          : vddadc       : Analogue to Digital Converter
                            SW_CONV_END          :              :
@@ -52,6 +53,14 @@ Optional child device properties:
                            supplied in the interrupts property
 - <supply_name>-supply   : contains a phandle to the regulator supply node in Device Tree
 
+Non-standard child device properties:
+ - Audio CODEC:
+   - stericsson,amic[1|2]-type-single-ended : Single-ended Analoge Mic (default: differential)
+   - stericsson,amic1a-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic1b-bias-vamic2          : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,amic2-bias-vamic1           : Analoge Mic wishes to use a non-standard Vamic
+   - stericsson,earpeice-cmv                : Earpeice voltage (only: 950 | 1100 | 1270 | 1580)
+
 ab8500@5 {
          compatible = "stericsson,ab8500";
          reg = <5>; /* mailbox 5 is i2c */
@@ -110,6 +119,12 @@ ab8500@5 {
                 compatible = "stericsson,ab8500-pwm";
         };
 
+        codec: ab8500-codec {
+                compatible = "stericsson,ab8500-codec";
+
+                stericsson,earpeice-cmv = <950>; /* Units in mV. */
+        };
+
         ab8500-regulators {
                 compatible = "stericsson,ab8500-regulator";
 
diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
new file mode 100644
index 000000000000..f1421e2bbab7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -0,0 +1,31 @@
+PXA3xx NAND DT bindings
+
+Required properties:
+
+ - compatible:          Should be "marvell,pxa3xx-nand"
+ - reg:                 The register base for the controller
+ - interrupts:          The interrupt to map
+ - #address-cells:      Set to <1> if the node includes partitions
+
+Optional properties:
+
+ - marvell,nand-enable-arbiter: Set to enable the bus arbiter
+ - marvell,nand-keep-config:    Set to keep the NAND controller config as set
+                                by the bootloader
+ - num-cs:                      Number of chipselect lines to usw
+
+Example:
+
+        nand0: nand@43100000 {
+                compatible = "marvell,pxa3xx-nand";
+                reg = <0x43100000 90>;
+                interrupts = <45>;
+                #address-cells = <1>;
+
+                marvell,nand-enable-arbiter;
+                marvell,nand-keep-config;
+                num-cs = <1>;
+
+                /* partitions (optional) */
+        };
+
diff --git a/Documentation/devicetree/bindings/rtc/pxa-rtc.txt b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
new file mode 100644
index 000000000000..8c6672a1b7d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/pxa-rtc.txt
@@ -0,0 +1,14 @@
+* PXA RTC
+
+PXA specific RTC driver.
+
+Required properties:
+- compatible : Should be "marvell,pxa-rtc"
+
+Examples:
+
+rtc@40900000 {
+        compatible = "marvell,pxa-rtc";
+        reg = <0x40900000 0x3c>;
+        interrupts = <30 31>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
new file mode 100644
index 000000000000..3c0484c49582
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/via,vt8500-rtc.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 Realtime Clock Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-rtc"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : alarm interrupt
+
+Example:
+
+        rtc@d8100000 {
+                compatible = "via,vt8500-rtc";
+                reg = <0xd8100000 0x10000>;
+                interrupts = <48>;
+        };
diff --git a/Documentation/devicetree/bindings/sound/ux500-mop500.txt b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
new file mode 100644
index 000000000000..48e071c96b46
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-mop500.txt
@@ -0,0 +1,39 @@
+* MOP500 Audio Machine Driver
+
+This node is responsible for linking together all ux500 Audio Driver components.
+
+Required properties:
+ - compatible              : "stericsson,snd-soc-mop500"
+
+Non-standard properties:
+ - stericsson,cpu-dai      : Phandle to the CPU-side DAI
+ - stericsson,audio-codec  : Phandle to the Audio CODEC
+ - stericsson,card-name    : Over-ride default card name
+
+Example:
+
+        sound {
+                compatible = "stericsson,snd-soc-mop500";
+
+                stericsson,cpu-dai = <&msp1 &msp3>;
+                stericsson,audio-codec = <&codec>;
+        };
+
+        msp1: msp@80124000 {
+                compatible = "stericsson,ux500-msp-i2s";
+                reg = <0x80124000 0x1000>;
+                interrupts = <0 62 0x4>;
+                v-ape-supply = <&db8500_vape_reg>;
+        };
+
+        msp3: msp@80125000 {
+                compatible = "stericsson,ux500-msp-i2s";
+                reg = <0x80125000 0x1000>;
+                interrupts = <0 62 0x4>;
+                v-ape-supply = <&db8500_vape_reg>;
+        };
+
+        codec: ab8500-codec {
+                compatible = "stericsson,ab8500-codec";
+                stericsson,earpeice-cmv = <950>; /* Units in mV. */
+        };
diff --git a/Documentation/devicetree/bindings/sound/ux500-msp.txt b/Documentation/devicetree/bindings/sound/ux500-msp.txt
new file mode 100644
index 000000000000..99acd9c774e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/ux500-msp.txt
@@ -0,0 +1,43 @@
+* ux500 MSP (CPU-side Digital Audio Interface)
+
+Required properties:
+ - compatible       :"stericsson,ux500-msp-i2s"
+ - reg              : Physical base address and length of the device's registers.
+
+Optional properties:
+ - interrupts       : The interrupt output from the device.
+ - interrupt-parent : The parent interrupt controller.
+ - <name>-supply    : Phandle to the regulator <name> supply
+
+Example:
+
+        sound {
+                compatible = "stericsson,snd-soc-mop500";
+
+                stericsson,platform-pcm-dma = <&pcm>;
+                stericsson,cpu-dai = <&msp1 &msp3>;
+                stericsson,audio-codec = <&codec>;
+        };
+
+        pcm: ux500-pcm {
+                compatible = "stericsson,ux500-pcm";
+        };
+
+        msp1: msp@80124000 {
+                compatible = "stericsson,ux500-msp-i2s";
+                reg = <0x80124000 0x1000>;
+                interrupts = <0 62 0x4>;
+                v-ape-supply = <&db8500_vape_reg>;
+        };
+
+        msp3: msp@80125000 {
+                compatible = "stericsson,ux500-msp-i2s";
+                reg = <0x80125000 0x1000>;
+                interrupts = <0 62 0x4>;
+                v-ape-supply = <&db8500_vape_reg>;
+        };
+
+        codec: ab8500-codec {
+                compatible = "stericsson,ab8500-codec";
+                stericsson,earpeice-cmv = <950>; /* Units in mV. */
+        };
diff --git a/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
new file mode 100644
index 000000000000..5feef1ef167d
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/via,vt8500-uart.txt
@@ -0,0 +1,17 @@
+VIA/Wondermedia VT8500 UART Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-uart"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UART interrupt
+- clocks : phandle to the uart source clock (usually a 24Mhz fixed clock)
+
+Example:
+
+        uart@d8210000 {
+                compatible = "via,vt8500-uart";
+                reg = <0xd8210000 0x1040>;
+                interrupts = <47>;
+                clocks = <&ref24>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/platform-uhci.txt b/Documentation/devicetree/bindings/usb/platform-uhci.txt
index 91477d6830ec..a4fb0719d157 100644
--- a/Documentation/devicetree/bindings/usb/platform-uhci.txt
+++ b/Documentation/devicetree/bindings/usb/platform-uhci.txt
@@ -1,12 +1,15 @@
-Generic Platform UHCI controllers.
+Generic Platform UHCI Controller
+-----------------------------------------------------
 
 Required properties:
- - compatible: Should be "platform-uhci".
- - reg: Address range of the uhci registers
- - interrupts: Should contain the uhci interrupt.
+- compatible : "platform-uhci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : UHCI controller interrupt
 
-usb: uhci@D8007301 {
-        compatible = "platform-uhci", "usb-uhci";
-        reg = <0xD8007301 0x200>;
-        interrupts = <0>;
-};
+Example:
+
+        uhci@d8007b00 {
+                compatible = "platform-uhci";
+                reg = <0xd8007b00 0x200>;
+                interrupts = <43>;
+        };
diff --git a/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
new file mode 100644
index 000000000000..17b3ad1d97e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/via,vt8500-ehci.txt
@@ -0,0 +1,15 @@
+VIA/Wondermedia VT8500 EHCI Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-ehci"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : ehci controller interrupt
+
+Example:
+
+        ehci@d8007900 {
+                compatible = "via,vt8500-ehci";
+                reg = <0xd8007900 0x200>;
+                interrupts = <43>;
+        };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 4f293e5571f0..9de2b9ff9d6e 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -48,5 +48,7 @@ sirf	SiRF Technology, Inc.
 st      STMicroelectronics
 stericsson      ST-Ericsson
 ti      Texas Instruments
+via     VIA Technologies, Inc.
 wlf     Wolfson Microelectronics
+wm      Wondermedia Technologies, Inc.
 xlnx    Xilinx
diff --git a/Documentation/devicetree/bindings/video/via,vt8500-fb.txt b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
new file mode 100644
index 000000000000..c870b6478ec8
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/via,vt8500-fb.txt
@@ -0,0 +1,62 @@
+VIA VT8500 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-fb"
+- reg : Should contain 1 register ranges(address and length)
+- interrupts : framebuffer controller interrupt
+- display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+        This should be in the board dts.
+- default-mode: a videomode within the display with timing parameters
+        as specified below.
+
+Example:
+
+        fb@d800e400 {
+                compatible = "via,vt8500-fb";
+                reg = <0xd800e400 0x400>;
+                interrupts = <12>;
+                display = <&display>;
+                default-mode = <&mode0>;
+        };
+
+VIA VT8500 Display
+-----------------------------------------------------
+Required properties (as per of_videomode_helper):
+
+ - hactive, vactive: Display resolution
+ - hfront-porch, hback-porch, hsync-len: Horizontal Display timing parameters
+   in pixels
+   vfront-porch, vback-porch, vsync-len: Vertical display timing parameters in
+   lines
+ - clock: displayclock in Hz
+ - bpp: lcd panel bit-depth.
+        <16> for RGB565, <32> for RGB888
+
+Optional properties (as per of_videomode_helper):
+ - width-mm, height-mm: Display dimensions in mm
+ - hsync-active-high (bool): Hsync pulse is active high
+ - vsync-active-high (bool): Vsync pulse is active high
+ - interlaced (bool): This is an interlaced mode
+ - doublescan (bool): This is a doublescan mode
+
+Example:
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
diff --git a/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
new file mode 100644
index 000000000000..a850fa011f02
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,prizm-ge-rops.txt
@@ -0,0 +1,13 @@
+VIA/Wondermedia Graphics Engine Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,prizm-ge-rops"
+- reg : Should contain 1 register ranges(address and length)
+
+Example:
+
+        ge_rops@d8050400 {
+                compatible = "wm,prizm-ge-rops";
+                reg = <0xd8050400 0x100>;
+        };
diff --git a/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
new file mode 100644
index 000000000000..3d325e1d11ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/wm,wm8505-fb.txt
@@ -0,0 +1,23 @@
+Wondermedia WM8505 Framebuffer
+-----------------------------------------------------
+
+Required properties:
+- compatible : "wm,wm8505-fb"
+- reg : Should contain 1 register ranges(address and length)
+- via,display: a phandle pointing to the display node
+
+Required nodes:
+- display: a display node is required to initialize the lcd panel
+        This should be in the board dts. See definition in
+        Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+- default-mode: a videomode node as specified in
+        Documentation/devicetree/bindings/video/via,vt8500-fb.txt
+
+Example:
+
+        fb@d8050800 {
+                compatible = "wm,wm8505-fb";
+                reg = <0xd8050800 0x200>;
+                display = <&display>;
+                default-mode = <&mode0>;
+        };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a97adeccf558..7362c9216b6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1003,6 +1003,10 @@ config ARCH_VT8500
         select ARCH_HAS_CPUFREQ
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
+        select USE_OF
+        select COMMON_CLK
+        select HAVE_CLK
+        select CLKDEV_LOOKUP
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -1129,8 +1133,6 @@ source "arch/arm/mach-versatile/Kconfig"
 source "arch/arm/mach-vexpress/Kconfig"
 source "arch/arm/plat-versatile/Kconfig"
 
-source "arch/arm/mach-vt8500/Kconfig"
-
 source "arch/arm/mach-w90x900/Kconfig"
 
 # Definitions to make life easier
@@ -1617,6 +1619,7 @@ config ARCH_NR_GPIO
         default 355 if ARCH_U8500
         default 264 if MACH_H4700
         default 512 if SOC_OMAP5
+        default 288 if ARCH_VT8500
         default 0
         help
           Maximum number of GPIOs in the system.
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index a9af4db7234c..c634f87e230e 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -17,4 +17,64 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+
+                        tps: tps@24 {
+                                reg = <0x24>;
+                        };
+
+                };
+        };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+        regulators {
+                dcdc1_reg: regulator@0 {
+                        regulator-always-on;
+                };
+
+                dcdc2_reg: regulator@1 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1325000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                dcdc3_reg: regulator@2 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <925000>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                ldo1_reg: regulator@3 {
+                        regulator-always-on;
+                };
+
+                ldo2_reg: regulator@4 {
+                        regulator-always-on;
+                };
+
+                ldo3_reg: regulator@5 {
+                        regulator-always-on;
+                };
+
+                ldo4_reg: regulator@6 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index d6a97d9eff72..185d6325a458 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -17,4 +17,104 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        ocp {
+                uart1: serial@44e09000 {
+                        status = "okay";
+                };
+
+                i2c1: i2c@44e0b000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+
+                        tps: tps@2d {
+                                reg = <0x2d>;
+                        };
+                };
+        };
+
+        vbat: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-boot-on;
+        };
+};
+
+/include/ "tps65910.dtsi"
+
+&tps {
+        vcc1-supply = <&vbat>;
+        vcc2-supply = <&vbat>;
+        vcc3-supply = <&vbat>;
+        vcc4-supply = <&vbat>;
+        vcc5-supply = <&vbat>;
+        vcc6-supply = <&vbat>;
+        vcc7-supply = <&vbat>;
+        vccio-supply = <&vbat>;
+
+        regulators {
+                vrtc_reg: regulator@0 {
+                        regulator-always-on;
+                };
+
+                vio_reg: regulator@1 {
+                        regulator-always-on;
+                };
+
+                vdd1_reg: regulator@2 {
+                        /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+                        regulator-name = "vdd_mpu";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1312500>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd2_reg: regulator@3 {
+                        /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+                        regulator-name = "vdd_core";
+                        regulator-min-microvolt = <912500>;
+                        regulator-max-microvolt = <1150000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                };
+
+                vdd3_reg: regulator@4 {
+                        regulator-always-on;
+                };
+
+                vdig1_reg: regulator@5 {
+                        regulator-always-on;
+                };
+
+                vdig2_reg: regulator@6 {
+                        regulator-always-on;
+                };
+
+                vpll_reg: regulator@7 {
+                        regulator-always-on;
+                };
+
+                vdac_reg: regulator@8 {
+                        regulator-always-on;
+                };
+
+                vaux1_reg: regulator@9 {
+                        regulator-always-on;
+                };
+
+                vaux2_reg: regulator@10 {
+                        regulator-always-on;
+                };
+
+                vaux33_reg: regulator@11 {
+                        regulator-always-on;
+                };
+
+                vmmc_reg: regulator@12 {
+                        regulator-always-on;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bd0cff3f808c..bb31bff01998 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -69,95 +69,146 @@
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x44e07000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <96>;
                 };
 
-                gpio2: gpio@4804C000 {
+                gpio2: gpio@4804c000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x4804c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <98>;
                 };
 
-                gpio3: gpio@481AC000 {
+                gpio3: gpio@481ac000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x481ac000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <32>;
                 };
 
-                gpio4: gpio@481AE000 {
+                gpio4: gpio@481ae000 {
                         compatible = "ti,omap4-gpio";
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupt-controller;
                         #interrupt-cells = <1>;
+                        reg = <0x481ae000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <62>;
                 };
 
-                uart1: serial@44E09000 {
+                uart1: serial@44e09000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
+                        reg = <0x44e09000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <72>;
+                        status = "disabled";
                 };
 
                 uart2: serial@48022000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
+                        reg = <0x48022000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <73>;
+                        status = "disabled";
                 };
 
                 uart3: serial@48024000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
+                        reg = <0x48024000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <74>;
+                        status = "disabled";
                 };
 
-                uart4: serial@481A6000 {
+                uart4: serial@481a6000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
+                        reg = <0x481a6000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <44>;
+                        status = "disabled";
                 };
 
-                uart5: serial@481A8000 {
+                uart5: serial@481a8000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
+                        reg = <0x481a8000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <45>;
+                        status = "disabled";
                 };
 
-                uart6: serial@481AA000 {
+                uart6: serial@481aa000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
+                        reg = <0x481aa000 0x2000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <46>;
+                        status = "disabled";
                 };
 
-                i2c1: i2c@44E0B000 {
+                i2c1: i2c@44e0b000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
+                        reg = <0x44e0b000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <70>;
+                        status = "disabled";
                 };
 
-                i2c2: i2c@4802A000 {
+                i2c2: i2c@4802a000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
+                        reg = <0x4802a000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <71>;
+                        status = "disabled";
                 };
 
-                i2c3: i2c@4819C000 {
+                i2c3: i2c@4819c000 {
                         compatible = "ti,omap4-i2c";
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
+                        reg = <0x4819c000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <30>;
+                        status = "disabled";
                 };
 
                 wdt2: wdt@44e35000 {
                         compatible = "ti,omap3-wdt";
                         ti,hwmods = "wd_timer2";
+                        reg = <0x44e35000 0x1000>;
+                        interrupt-parent = <&intc>;
+                        interrupts = <91>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index 3180a9c588b9..748ba7aa746c 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -194,6 +194,8 @@
                         interrupts = <0 47 0x4>;
                         #address-cells = <1>;
                         #size-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                         ranges;
 
                         prcmu-timer-4@80157450 {
@@ -330,6 +332,7 @@
                         ab8500@5 {
                                 compatible = "stericsson,ab8500";
                                 reg = <5>; /* mailbox 5 is i2c */
+                                interrupt-parent = <&intc>;
                                 interrupts = <0 40 0x4>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
@@ -371,7 +374,7 @@
                                 };
 
                                 ab8500-ponkey {
-                                        compatible = "stericsson,ab8500-ponkey";
+                                        compatible = "stericsson,ab8500-poweron-key";
                                         interrupts = <6 0x4
                                                       7 0x4>;
                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
@@ -389,6 +392,12 @@
                                         compatible = "stericsson,ab8500-debug";
                                 };
 
+                                codec: ab8500-codec {
+                                        compatible = "stericsson,ab8500-codec";
+
+                                        stericsson,earpeice-cmv = <950>; /* Units in mV. */
+                                };
+
                                 ab8500-regulators {
                                         compatible = "stericsson,ab8500-regulator";
 
@@ -471,48 +480,63 @@
                 };
 
                 i2c@80004000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80004000 0x1000>;
                         interrupts = <0 21 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80122000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80122000 0x1000>;
                         interrupts = <0 22 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80128000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80128000 0x1000>;
                         interrupts = <0 55 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@80110000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80110000 0x1000>;
                         interrupts = <0 12 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 i2c@8012a000 {
-                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c";
+                        compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x8012a000 0x1000>;
                         interrupts = <0 51 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        v-i2c-supply = <&db8500_vape_reg>;
+
+                        clock-frequency = <400000>;
                 };
 
                 ssp@80002000 {
                         compatible = "arm,pl022", "arm,primecell";
-                        reg = <80002000 0x1000>;
+                        reg = <0x80002000 0x1000>;
                         interrupts = <0 14 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -580,6 +604,39 @@
                         status = "disabled";
                 };
 
+                msp0: msp@80123000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80123000 0x1000>;
+                        interrupts = <0 31 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                msp1: msp@80124000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80124000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                // HDMI sound
+                msp2: msp@80117000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80117000 0x1000>;
+                        interrupts = <0 98 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
+                msp3: msp@80125000 {
+                        compatible = "stericsson,ux500-msp-i2s";
+                        reg = <0x80125000 0x1000>;
+                        interrupts = <0 62 0x4>;
+                        v-ape-supply = <&db8500_vape_reg>;
+                        status = "disabled";
+                };
+
                 external-bus@50000000 {
                         compatible = "simple-bus";
                         reg = <0x50000000 0x4000000>;
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
index d79b28d9c963..a4ba31b23c88 100644
--- a/arch/arm/boot/dts/ea3250.dts
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -166,9 +166,116 @@
                 #size-cells = <0>;
                 autorepeat;
                 button@21 {
-                        label = "GPIO Key UP";
+                        label = "Interrupt Key";
                         linux,code = <103>;
                         gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
                 };
+                key1 {
+                        label = "KEY1";
+                        linux,code = <1>;
+                        gpios = <&pca9532 0 0>;
+                };
+                key2 {
+                        label = "KEY2";
+                        linux,code = <2>;
+                        gpios = <&pca9532 1 0>;
+                };
+                key3 {
+                        label = "KEY3";
+                        linux,code = <3>;
+                        gpios = <&pca9532 2 0>;
+                };
+                key4 {
+                        label = "KEY4";
+                        linux,code = <4>;
+                        gpios = <&pca9532 3 0>;
+                };
+                joy0 {
+                        label = "Joystick Key 0";
+                        linux,code = <10>;
+                        gpios = <&gpio 2 0 0>; /* P2.0 */
+                };
+                joy1 {
+                        label = "Joystick Key 1";
+                        linux,code = <11>;
+                        gpios = <&gpio 2 1 0>; /* P2.1 */
+                };
+                joy2 {
+                        label = "Joystick Key 2";
+                        linux,code = <12>;
+                        gpios = <&gpio 2 2 0>; /* P2.2 */
+                };
+                joy3 {
+                        label = "Joystick Key 3";
+                        linux,code = <13>;
+                        gpios = <&gpio 2 3 0>; /* P2.3 */
+                };
+                joy4 {
+                        label = "Joystick Key 4";
+                        linux,code = <14>;
+                        gpios = <&gpio 2 4 0>; /* P2.4 */
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* LEDs on OEM Board */
+
+                led1 {
+                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
+                        linux,default-trigger = "timer";
+                        default-state = "off";
+                };
+
+                led2 {
+                        gpios = <&gpio 2 10 1>; /* P2.10, active low */
+                        default-state = "off";
+                };
+
+                led3 {
+                        gpios = <&gpio 2 11 1>; /* P2.11, active low */
+                        default-state = "off";
+                };
+
+                led4 {
+                        gpios = <&gpio 2 12 1>; /* P2.12, active low */
+                        default-state = "off";
+                };
+
+                /* LEDs on Base Board */
+
+                lede1 {
+                        gpios = <&pca9532 8 0>;
+                        default-state = "off";
+                };
+                lede2 {
+                        gpios = <&pca9532 9 0>;
+                        default-state = "off";
+                };
+                lede3 {
+                        gpios = <&pca9532 10 0>;
+                        default-state = "off";
+                };
+                lede4 {
+                        gpios = <&pca9532 11 0>;
+                        default-state = "off";
+                };
+                lede5 {
+                        gpios = <&pca9532 12 0>;
+                        default-state = "off";
+                };
+                lede6 {
+                        gpios = <&pca9532 13 0>;
+                        default-state = "off";
+                };
+                lede7 {
+                        gpios = <&pca9532 14 0>;
+                        default-state = "off";
+                };
+                lede8 {
+                        gpios = <&pca9532 15 0>;
+                        default-state = "off";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/elpida_ecb240abacn.dtsi b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
new file mode 100644
index 000000000000..f97f70f83374
--- /dev/null
+++ b/arch/arm/boot/dts/elpida_ecb240abacn.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Common devices used in different OMAP boards
+ */
+
+/ {
+        elpida_ECB240ABACN: lpddr2 {
+                compatible      = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
+                density         = <2048>;
+                io-width        = <32>;
+
+                tRPab-min-tck   = <3>;
+                tRCD-min-tck    = <3>;
+                tWR-min-tck     = <3>;
+                tRASmin-min-tck = <3>;
+                tRRD-min-tck    = <2>;
+                tWTR-min-tck    = <2>;
+                tXP-min-tck     = <2>;
+                tRTP-min-tck    = <2>;
+                tCKE-min-tck    = <3>;
+                tCKESR-min-tck  = <3>;
+                tFAW-min-tck    = <8>;
+
+                timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <400000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <7500>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+
+                timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
+                        compatible      = "jedec,lpddr2-timings";
+                        min-freq        = <10000000>;
+                        max-freq        = <200000000>;
+                        tRPab           = <21000>;
+                        tRCD            = <18000>;
+                        tWR             = <15000>;
+                        tRAS-min        = <42000>;
+                        tRRD            = <10000>;
+                        tWTR            = <10000>;
+                        tXP             = <7500>;
+                        tRTP            = <7500>;
+                        tCKESR          = <15000>;
+                        tDQSCK-max      = <5500>;
+                        tFAW            = <50000>;
+                        tZQCS           = <90000>;
+                        tZQCL           = <360000>;
+                        tZQinit         = <1000000>;
+                        tRAS-max-ns     = <70000>;
+                        tDQSCK-max-derated = <6000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
new file mode 100644
index 000000000000..2131d77dc9c9
--- /dev/null
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2012 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "dbx5x0.dtsi"
+
+/ {
+        model = "ST-Ericsson HREF platform with Device Tree";
+        compatible = "st-ericsson,hrefv60+";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        soc-u9500 {
+                uart@80120000 {
+                        status = "okay";
+                };
+
+                uart@80121000 {
+                        status = "okay";
+                };
+
+                uart@80007000 {
+                        status = "okay";
+                };
+
+                i2c@80004000 {
+                        tc3589x@42 {
+                                compatible = "tc3589x";
+                                reg = <0x42>;
+                                interrupt-parent = <&gpio6>;
+                                interrupts = <25 0x1>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+
+                                tc3589x_gpio: tc3589x_gpio {
+                                        compatible = "tc3589x-gpio";
+                                        interrupts = <0 0x1>;
+
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                        };
+
+                        tps61052@33 {
+                                compatible = "tps61052";
+                                reg = <0x33>;
+                        };
+                };
+
+                i2c@80128000 {
+                        lp5521@0x33 {
+                                compatible = "lp5521";
+                                reg = <0x33>;
+                        };
+
+                        lp5521@0x34 {
+                                compatible = "lp5521";
+                                reg = <0x34>;
+                        };
+
+                        bh1780@0x29 {
+                                compatible = "rohm,bh1780gli";
+                                reg = <0x33>;
+                        };
+                };
+
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index e3486f486b40..035c13f9d3c0 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -42,12 +42,13 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
                                                 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
                                                 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index 20912b1d8893..384d8b66f337 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -31,6 +31,22 @@
                                 bus-width = <4>;
                                 status = "okay";
                         };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2013 /* MX23_PAD_SSP1_DETECT__GPIO_2_1 */
+                                                0x0113 /* MX23_PAD_GPMI_ALE__GPIO_0_17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
                 };
 
                 apbx@80040000 {
@@ -39,6 +55,47 @@
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
+
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */
+                        gpio = <&gpio0 17 0>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "green";
+                        gpios = <&gpio2 1 0>;
+                        linux,default-trigger = "default-on";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
index 757a327ff3e8..85c3864b6a56 100644
--- a/arch/arm/boot/dts/imx23-stmp378x_devb.dts
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -36,7 +36,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index e6138310e5ce..3f3b6fc229b3 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -52,6 +52,7 @@
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx23-dma-apbh";
                                 reg = <0x80004000 0x2000>;
+                                clocks = <&clks 15>;
                         };
 
                         ecc@80008000 {
@@ -67,6 +68,7 @@
                                 reg-names = "gpmi-nand", "bch";
                                 interrupts = <13>, <56>;
                                 interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 34>;
                                 fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
@@ -74,6 +76,7 @@
                         ssp0: ssp@80010000 {
                                 reg = <0x80010000 0x2000>;
                                 interrupts = <15 14>;
+                                clocks = <&clks 33>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
@@ -140,6 +143,17 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart0_2pins_a: auart0-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x01e2 /* MX23_PAD_I2C_SCL__AUART1_TX */
+                                                0x01f2 /* MX23_PAD_I2C_SDA__AUART1_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 gpmi_pins_a: gpmi-nand@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -183,7 +197,6 @@
                                                 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
                                                 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
                                                 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
-                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
                                                 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
                                         >;
                                         fsl,drive-strength = <1>;
@@ -280,6 +293,7 @@
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx23-dma-apbx";
                                 reg = <0x80024000 0x2000>;
+                                clocks = <&clks 16>;
                         };
 
                         dcp@80028000 {
@@ -306,12 +320,14 @@
                                 compatible = "fsl,imx23-lcdif";
                                 reg = <0x80030000 2000>;
                                 interrupts = <46 45>;
+                                clocks = <&clks 38>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80034000 {
                                 reg = <0x80034000 0x2000>;
                                 interrupts = <2 20>;
+                                clocks = <&clks 33>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
@@ -329,9 +345,10 @@
                         reg = <0x80040000 0x40000>;
                         ranges;
 
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx23-clkctrl";
                                 reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                         };
 
                         saif0: saif@80042000 {
@@ -383,6 +400,7 @@
                         pwm: pwm@80064000 {
                                 compatible = "fsl,imx23-pwm";
                                 reg = <0x80064000 0x2000>;
+                                clocks = <&clks 30>;
                                 #pwm-cells = <2>;
                                 fsl,pwm-number = <5>;
                                 status = "disabled";
@@ -397,6 +415,7 @@
                                 compatible = "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <24 25 23>;
+                                clocks = <&clks 32>;
                                 status = "disabled";
                         };
 
@@ -404,6 +423,7 @@
                                 compatible = "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <59 60 58>;
+                                clocks = <&clks 32>;
                                 status = "disabled";
                         };
 
@@ -411,11 +431,15 @@
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <0>;
+                                clocks = <&clks 32>, <&clks 16>;
+                                clock-names = "uart", "apb_pclk";
                                 status = "disabled";
                         };
 
-                        usbphy@8007c000 {
+                        usbphy0: usbphy@8007c000 {
+                                compatible = "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 41>;
                                 status = "disabled";
                         };
                 };
@@ -428,8 +452,12 @@
                 reg = <0x80080000 0x80000>;
                 ranges;
 
-                usbctrl@80080000 {
+                usb0: usb@80080000 {
+                        compatible = "fsl,imx23-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x40000>;
+                        interrupts = <11>;
+                        fsl,usbphy = <&usbphy0>;
+                        clocks = <&clks 40>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2acc86cfdd05..af50469e34b2 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -23,10 +23,6 @@
         soc {
                 aipi@10000000 { /* aipi */
 
-                        wdog@10002000 {
-                                status = "okay";
-                        };
-
                         serial@1000a000 {
                                 fsl,uart-has-rtscts;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 5303ab680a34..3e54f1498841 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -62,7 +62,6 @@
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                 reg = <0x10002000 0x4000>;
                                 interrupts = <27>;
-                                status = "disabled";
                         };
 
                         uart1: serial@1000a000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
index b383417a558f..5171667a7763 100644
--- a/arch/arm/boot/dts/imx28-apx4devkit.dts
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -37,7 +37,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
new file mode 100644
index 000000000000..05c892e931e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+        model = "Crystalfontz CFA-10049 Board";
+        compatible = "crystalfontz,cfa10049", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                spi3_pins_cfa10049: spi3-cfa10049@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
+                                                0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
+                                                0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
+                                                0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                        };
+
+                        ssp3: ssp@80016000 {
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi3_pins_cfa10049>;
+                                status = "okay";
+
+                                gpio5: gpio5@0 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0>;
+                                        registers-number = <2>;
+                                        spi-max-frequency = <100000>;
+                                };
+
+                                gpio6: gpio6@1 {
+                                        compatible = "fairchild,74hc595";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <1>;
+                                        registers-number = <4>;
+                                        spi-max-frequency = <100000>;
+                                };
+
+                        };
+                };
+
+                apbx@80040000 {
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index 773c0e84d1fb..a0ad71ca3a44 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -46,11 +46,28 @@
                                 wp-gpios = <&gpio0 28 0>;
                         };
 
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "sst,sst25vf016b";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
+
                         pinctrl@80018000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
@@ -128,6 +145,10 @@
                                 status = "okay";
                         };
 
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_a>;
@@ -140,6 +161,12 @@
                                         VDDIO-supply = <&reg_3p3v>;
 
                                 };
+
+                                at24@51 {
+                                        compatible = "at24,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x51>;
+                                };
                         };
 
                         pwm: pwm@80064000 {
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 183a3fd2d859..3bab6b00c52d 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -23,6 +23,8 @@
         apb@80000000 {
                 apbh@80000000 {
                         gpmi-nand@8000c000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
                                 status = "okay";
@@ -61,19 +63,40 @@
                                              &mmc0_cd_cfg
                                              &mmc0_sck_cfg>;
                                 bus-width = <8>;
-                                wp-gpios = <&gpio3 10 1>;
+                                wp-gpios = <&gpio3 10 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
                                 status = "okay";
                         };
 
+                        ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx28-spi";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi2_pins_a>;
+                                status = "okay";
+
+                                flash: m25p80@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        compatible = "m25p80";
+                                        spi-max-frequency = <40000000>;
+                                        reg = <0>;
+                                };
+                        };
+
                         pinctrl@80018000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
                                                 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
                                                 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+                                                0x30c3 /* MX28_PAD_AUART3_RX__GPIO_3_12 */
+                                                0x30d3 /* MX28_PAD_AUART3_TX__GPIO_3_13 */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
@@ -129,6 +152,7 @@
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_a>;
+                                clock-frequency = <400000>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -151,32 +175,51 @@
                                 };
                         };
 
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
 
-                        auart0: serial@8006a000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
+                        usbphy0: usbphy@8007c000 {
                                 status = "okay";
                         };
 
-                        auart3: serial@80070000 {
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&auart3_pins_a>;
+                                pinctrl-0 = <&auart0_2pins_a>;
                                 status = "okay";
                         };
                 };
         };
 
         ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy0_pins_a>;
+                        status = "okay";
+                };
+
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        status = "okay";
+                };
+
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac0_pins_a>;
-                        phy-reset-gpios = <&gpio3 11 0>;
                         status = "okay";
                 };
 
@@ -198,6 +241,30 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 28 0>;
+                };
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 12 0>;
+                };
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 13 0>;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 62bf767409a6..37be532f0055 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -25,7 +25,7 @@
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&hog_pins_a>;
 
-                                hog_pins_a: hog-gpios@0 {
+                                hog_pins_a: hog@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
                                                 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
@@ -34,6 +34,24 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                mac0_pins_gpio: mac0-gpio-mode@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */
+                                                0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */
+                                                0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */
+                                                0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */
+                                                0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */
+                                                0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */
+                                                0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */
+                                                0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */
+                                                0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
                 };
 
@@ -72,8 +90,9 @@
         ahb@80080000 {
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
-                        pinctrl-names = "default";
+                        pinctrl-names = "default", "gpio_mode";
                         pinctrl-0 = <&mac0_pins_a>;
+                        pinctrl-1 = <&mac0_pins_gpio>;
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 3fa6d190fab4..724147eab84b 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -27,6 +27,8 @@
                 serial2 = &auart2;
                 serial3 = &auart3;
                 serial4 = &auart4;
+                ethernet0 = &mac0;
+                ethernet1 = &mac1;
         };
 
         cpus {
@@ -65,6 +67,7 @@
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx28-dma-apbh";
                                 reg = <0x80004000 0x2000>;
+                                clocks = <&clks 25>;
                         };
 
                         perfmon@80006000 {
@@ -81,34 +84,47 @@
                                 reg-names = "gpmi-nand", "bch";
                                 interrupts = <88>, <41>;
                                 interrupt-names = "gpmi-dma", "bch";
+                                clocks = <&clks 50>;
                                 fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
                         ssp0: ssp@80010000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80010000 0x2000>;
                                 interrupts = <96 82>;
+                                clocks = <&clks 46>;
                                 fsl,ssp-dma-channel = <0>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80012000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80012000 0x2000>;
                                 interrupts = <97 83>;
+                                clocks = <&clks 47>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
 
                         ssp2: ssp@80014000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80014000 0x2000>;
                                 interrupts = <98 84>;
+                                clocks = <&clks 48>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
 
                         ssp3: ssp@80016000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
                                 reg = <0x80016000 0x2000>;
                                 interrupts = <99 85>;
+                                clocks = <&clks 49>;
                                 fsl,ssp-dma-channel = <3>;
                                 status = "disabled";
                         };
@@ -410,6 +426,28 @@
                                         fsl,pull-up = <1>;
                                 };
 
+                                i2c0_pins_b: i2c0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */
+                                                0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                i2c1_pins_a: i2c1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3101 /* MX28_PAD_PWM0__I2C1_SCL */
+                                                0x3111 /* MX28_PAD_PWM1__I2C1_SDA */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
                                 saif0_pins_a: saif0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -453,6 +491,16 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                pwm4_pins_a: pwm4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31d0 /* MX28_PAD_PWM4__PWM_4 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 lcdif_24bit_pins_a: lcdif-24bit@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -507,6 +555,49 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                spi2_pins_a: spi2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */
+                                                0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */
+                                                0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */
+                                                0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                usbphy0_pins_a: usbphy0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                usbphy0_pins_b: usbphy0@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                usbphy1_pins_a: usbphy1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
 
                         digctl@8001c000 {
@@ -523,6 +614,7 @@
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx28-dma-apbx";
                                 reg = <0x80024000 0x2000>;
+                                clocks = <&clks 26>;
                         };
 
                         dcp@80028000 {
@@ -551,6 +643,7 @@
                                 compatible = "fsl,imx28-lcdif";
                                 reg = <0x80030000 0x2000>;
                                 interrupts = <38 86>;
+                                clocks = <&clks 55>;
                                 status = "disabled";
                         };
 
@@ -558,6 +651,8 @@
                                 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80032000 0x2000>;
                                 interrupts = <8>;
+                                clocks = <&clks 58>, <&clks 58>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -565,6 +660,8 @@
                                 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80034000 0x2000>;
                                 interrupts = <9>;
+                                clocks = <&clks 59>, <&clks 59>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -611,15 +708,17 @@
                         reg = <0x80040000 0x40000>;
                         ranges;
 
-                        clkctl@80040000 {
+                        clks: clkctrl@80040000 {
+                                compatible = "fsl,imx28-clkctrl";
                                 reg = <0x80040000 0x2000>;
-                                status = "disabled";
+                                #clock-cells = <1>;
                         };
 
                         saif0: saif@80042000 {
                                 compatible = "fsl,imx28-saif";
                                 reg = <0x80042000 0x2000>;
                                 interrupts = <59 80>;
+                                clocks = <&clks 53>;
                                 fsl,saif-dma-channel = <4>;
                                 status = "disabled";
                         };
@@ -633,12 +732,16 @@
                                 compatible = "fsl,imx28-saif";
                                 reg = <0x80046000 0x2000>;
                                 interrupts = <58 81>;
+                                clocks = <&clks 54>;
                                 fsl,saif-dma-channel = <5>;
                                 status = "disabled";
                         };
 
                         lradc@80050000 {
+                                compatible = "fsl,imx28-lradc";
                                 reg = <0x80050000 0x2000>;
+                                interrupts = <10 14 15 16 17 18 19
+                                                20 21 22 23 24 25>;
                                 status = "disabled";
                         };
 
@@ -677,6 +780,7 @@
                         pwm: pwm@80064000 {
                                 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
                                 reg = <0x80064000 0x2000>;
+                                clocks = <&clks 44>;
                                 #pwm-cells = <2>;
                                 fsl,pwm-number = <8>;
                                 status = "disabled";
@@ -691,6 +795,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006a000 0x2000>;
                                 interrupts = <112 70 71>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -698,6 +803,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <113 72 73>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -705,6 +811,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <114 74 75>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -712,6 +819,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <115 76 77>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -719,6 +827,7 @@
                                 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80072000 0x2000>;
                                 interrupts = <116 78 79>;
+                                clocks = <&clks 45>;
                                 status = "disabled";
                         };
 
@@ -726,18 +835,22 @@
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0x80074000 0x1000>;
                                 interrupts = <47>;
+                                clocks = <&clks 45>, <&clks 26>;
+                                clock-names = "uart", "apb_pclk";
                                 status = "disabled";
                         };
 
                         usbphy0: usbphy@8007c000 {
                                 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
+                                clocks = <&clks 62>;
                                 status = "disabled";
                         };
 
                         usbphy1: usbphy@8007e000 {
                                 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007e000 0x2000>;
+                                clocks = <&clks 63>;
                                 status = "disabled";
                         };
                 };
@@ -754,6 +867,7 @@
                         compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x10000>;
                         interrupts = <93>;
+                        clocks = <&clks 60>;
                         fsl,usbphy = <&usbphy0>;
                         status = "disabled";
                 };
@@ -762,6 +876,7 @@
                         compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80090000 0x10000>;
                         interrupts = <92>;
+                        clocks = <&clks 61>;
                         fsl,usbphy = <&usbphy1>;
                         status = "disabled";
                 };
@@ -775,6 +890,8 @@
                         compatible = "fsl,imx28-fec";
                         reg = <0x800f0000 0x4000>;
                         interrupts = <101>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                         status = "disabled";
                 };
 
@@ -782,6 +899,8 @@
                         compatible = "fsl,imx28-fec";
                         reg = <0x800f4000 0x4000>;
                         interrupts = <102>;
+                        clocks = <&clks 57>, <&clks 57>;
+                        clock-names = "ipg", "ahb";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 59d9789e5508..cbd2b1c7487b 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,23 +25,31 @@
                 aips@70000000 { /* aips-1 */
                         spba@70000000 {
                                 esdhc@70004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         fsl,cd-controller;
                                         fsl,wp-controller;
                                         status = "okay";
                                 };
 
                                 esdhc@70008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                         cd-gpios = <&gpio1 6 0>;
                                         wp-gpios = <&gpio1 5 0>;
                                         status = "okay";
                                 };
 
                                 uart3: serial@7000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@70010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
                                         status = "okay";
@@ -169,31 +177,43 @@
                                 };
                         };
 
-                        wdog@73f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@73fa8000 {
-                                compatible = "fsl,imx51-iomuxc-babbage";
-                                reg = <0x73fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        694  0x20d5     /* MX51_PAD_GPIO1_0__SD1_CD */
+                                                        697  0x20d5     /* MX51_PAD_GPIO1_1__SD1_WP */
+                                                        737  0x100      /* MX51_PAD_GPIO1_5__GPIO1_5 */
+                                                        740  0x100      /* MX51_PAD_GPIO1_6__GPIO1_6 */
+                                                        121  0x5        /* MX51_PAD_EIM_A27__GPIO2_21 */
+                                                        402  0x85       /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
+                                                        405  0x85       /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@73fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 fsl,uart-has-rtscts;
                                 status = "okay";
                         };
 
                         uart2: serial@73fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@80000000 { /* aips-2 */
-                        sdma@83fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
-                        };
-
                         i2c@83fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -206,10 +226,14 @@
                         };
 
                         audmux@83fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                 status = "okay";
                         };
 
                         ethernet@83fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "mii";
                                 status = "okay";
                         };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index aba28dc87fc8..2f71a91ca98e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -130,6 +130,34 @@
                                 };
                         };
 
+                        usb@73f80000 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80200 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80400 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        usb@73f80600 {
+                                compatible = "fsl,imx51-usb", "fsl,imx27-usb";
+                                reg = <0x73f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f84000 0x4000>;
@@ -174,7 +202,6 @@
                                 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
                                 reg = <0x73f98000 0x4000>;
                                 interrupts = <58>;
-                                status = "disabled";
                         };
 
                         wdog@73f9c000 { /* WDOG2 */
@@ -184,6 +211,122 @@
                                 status = "disabled";
                         };
 
+                        iomuxc@73fa8000 {
+                                compatible = "fsl,imx51-iomuxc";
+                                reg = <0x73fa8000 0x4000>;
+
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        384 0x80000000  /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
+                                                        386 0x80000000  /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
+                                                        389 0x80000000  /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
+                                                        391 0x80000000  /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
+                                                >;
+                                        };
+                                };
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        128 0x80000000  /* MX51_PAD_EIM_EB2__FEC_MDIO */
+                                                        134 0x80000000  /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
+                                                        146 0x80000000  /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
+                                                        152 0x80000000  /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
+                                                        158 0x80000000  /* MX51_PAD_EIM_CS4__FEC_RX_ER */
+                                                        165 0x80000000  /* MX51_PAD_EIM_CS5__FEC_CRS */
+                                                        206 0x80000000  /* MX51_PAD_NANDF_RB2__FEC_COL */
+                                                        213 0x80000000  /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
+                                                        293 0x80000000  /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
+                                                        298 0x80000000  /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
+                                                        225 0x80000000  /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
+                                                        231 0x80000000  /* MX51_PAD_NANDF_CS3__FEC_MDC */
+                                                        237 0x80000000  /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
+                                                        243 0x80000000  /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
+                                                        250 0x80000000  /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
+                                                        255 0x80000000  /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
+                                                        260 0x80000000  /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        398 0x185       /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
+                                                        394 0x185       /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
+                                                        409 0x185       /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        666 0x400020d5  /* MX51_PAD_SD1_CMD__SD1_CMD */
+                                                        669 0x20d5      /* MX51_PAD_SD1_CLK__SD1_CLK */
+                                                        672 0x20d5      /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
+                                                        678 0x20d5      /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
+                                                        684 0x20d5      /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
+                                                        691 0x20d5      /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
+                                                >;
+                                        };
+                                };
+
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        704 0x400020d5  /* MX51_PAD_SD2_CMD__SD2_CMD */
+                                                        707 0x20d5      /* MX51_PAD_SD2_CLK__SD2_CLK */
+                                                        710 0x20d5      /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
+                                                        712 0x20d5      /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
+                                                        715 0x20d5      /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
+                                                        719 0x20d5      /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        449 0x400001ed  /* MX51_PAD_KEY_COL4__I2C2_SCL */
+                                                        454 0x400001ed  /* MX51_PAD_KEY_COL5__I2C2_SDA */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        413 0x1c5       /* MX51_PAD_UART1_RXD__UART1_RXD */
+                                                        416 0x1c5       /* MX51_PAD_UART1_TXD__UART1_TXD */
+                                                        418 0x1c5       /* MX51_PAD_UART1_RTS__UART1_RTS */
+                                                        420 0x1c5       /* MX51_PAD_UART1_CTS__UART1_CTS */
+                                                >;
+                                        };
+                                };
+
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        423 0x1c5       /* MX51_PAD_UART2_RXD__UART2_RXD */
+                                                        426 0x1c5       /* MX51_PAD_UART2_TXD__UART2_TXD */
+                                                >;
+                                        };
+                                };
+
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        54 0x1c5        /* MX51_PAD_EIM_D25__UART3_RXD */
+                                                        59 0x1c5        /* MX51_PAD_EIM_D26__UART3_TXD */
+                                                        65 0x1c5        /* MX51_PAD_EIM_D27__UART3_RTS */
+                                                        49 0x1c5        /* MX51_PAD_EIM_D24__UART3_CTS */
+                                                >;
+                                        };
+                                };
+                        };
+
                         uart1: serial@73fbc000 {
                                 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                 reg = <0x73fbc000 0x4000>;
@@ -219,6 +362,7 @@
                                 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
                                 reg = <0x83fb0000 0x4000>;
                                 interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
                         };
 
                         cspi@83fc0000 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index da895e93a999..4be76f223526 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -25,31 +25,66 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_2>;
                                         cd-gpios = <&gpio1 1 0>;
                                         wp-gpios = <&gpio1 9 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-ard";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
+                                                        1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
+                                                        486  0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
+                                                        739  0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
+                                                        218  0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
+                                                        226  0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
+                                                        233  0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
+                                                        241  0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
+                                                        429  0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
+                                                        435  0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
+                                                        441  0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
+                                                        448  0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
+                                                        456  0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
+                                                        464  0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
+                                                        471  0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
+                                                        477  0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
+                                                        492  0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
+                                                        500  0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
+                                                        508  0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
+                                                        516  0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
+                                                        524  0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
+                                                        532  0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
+                                                        540  0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
+                                                        548  0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
+                                                        637  0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
+                                                        642  0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
+                                                        647  0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
+                                                        652  0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
+                                                        657  0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
+                                                        662  0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
+                                                        667  0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
+                                                        611  0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
+                                                        616  0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
+                                                        607  0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_2>;
                                 status = "okay";
                         };
                 };
-
-                aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-                };
         };
 
         eim-cs1@f4000000 {
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 9c798034675e..a124d1e25258 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -25,12 +25,16 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         wp-gpios = <&gpio3 14 0>;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
@@ -56,32 +60,45 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         cd-gpios = <&gpio3 11 0>;
                                         wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-evk";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        705  0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 pmic: mc13892@08 {
@@ -96,6 +113,8 @@
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 2d803a9a6949..08948af86d1a 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -25,6 +25,8 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         status = "okay";
                                 };
@@ -35,32 +37,46 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         cd-gpios = <&gpio3 11 0>;
                                         wp-gpios = <&gpio3 12 0>;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-qsb";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
+                                                        1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        693  0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
+                                                        697  0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                        873  0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 sgtl5000: codec@0a {
@@ -72,6 +88,8 @@
                         };
 
                         i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                 status = "okay";
 
                                 accelerometer: mma8450@1c {
@@ -158,10 +176,14 @@
                         };
 
                         audmux@63fd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_audmux_1>;
                                 status = "okay";
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 08091029168e..06c68580c842 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -25,22 +25,30 @@
                 aips@50000000 { /* AIPS1 */
                         spba@50000000 {
                                 esdhc@50004000 { /* ESDHC1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc1_1>;
                                         cd-gpios = <&gpio3 13 0>;
                                         wp-gpios = <&gpio4 11 0>;
                                         status = "okay";
                                 };
 
                                 esdhc@50008000 { /* ESDHC2 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc2_1>;
                                         non-removable;
                                         status = "okay";
                                 };
 
                                 uart3: serial@5000c000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart3_1>;
                                         fsl,uart-has-rtscts;
                                         status = "okay";
                                 };
 
                                 ecspi@50010000 { /* ECSPI1 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         fsl,spi-num-chipselects = <2>;
                                         cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
                                         status = "okay";
@@ -72,35 +80,49 @@
                                 };
 
                                 esdhc@50020000 { /* ESDHC3 */
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_esdhc3_1>;
                                         non-removable;
                                         status = "okay";
                                 };
                         };
 
-                        wdog@53f98000 { /* WDOG1 */
-                                status = "okay";
-                        };
-
                         iomuxc@53fa8000 {
-                                compatible = "fsl,imx53-iomuxc-smd";
-                                reg = <0x53fa8000 0x4000>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        982  0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
+                                                        989  0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
+                                                        424  0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
+                                                        701  0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
+                                                        449  0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
+                                                        43   0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
+                                                        868  0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
+                                                >;
+                                        };
+                                };
                         };
 
                         uart1: serial@53fbc000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1_1>;
                                 status = "okay";
                         };
 
                         uart2: serial@53fc0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                                 status = "okay";
                         };
                 };
 
                 aips@60000000 { /* AIPS2 */
-                        sdma@63fb0000 {
-                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
-                        };
-
                         i2c@63fc4000 { /* I2C2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c2_1>;
                                 status = "okay";
 
                                 codec: sgtl5000@0a {
@@ -120,6 +142,8 @@
                         };
 
                         i2c@63fc8000 { /* I2C1 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_i2c1_1>;
                                 status = "okay";
 
                                 accelerometer: mma8450@1c {
@@ -139,6 +163,8 @@
                         };
 
                         ethernet@63fec000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_fec_1>;
                                 phy-mode = "rmii";
                                 phy-reset-gpios = <&gpio7 6 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index cd37165edce5..221cf3321b0a 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,6 +135,34 @@
                                 };
                         };
 
+                        usb@53f80000 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80000 0x0200>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80200 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80200 0x0200>;
+                                interrupts = <14>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80400 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80400 0x0200>;
+                                interrupts = <16>;
+                                status = "disabled";
+                        };
+
+                        usb@53f80600 {
+                                compatible = "fsl,imx53-usb", "fsl,imx27-usb";
+                                reg = <0x53f80600 0x0200>;
+                                interrupts = <17>;
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f84000 0x4000>;
@@ -179,7 +207,6 @@
                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
                                 reg = <0x53f98000 0x4000>;
                                 interrupts = <58>;
-                                status = "disabled";
                         };
 
                         wdog@53f9c000 { /* WDOG2 */
@@ -189,6 +216,161 @@
                                 status = "disabled";
                         };
 
+                        iomuxc@53fa8000 {
+                                compatible = "fsl,imx53-iomuxc";
+                                reg = <0x53fa8000 0x4000>;
+
+                                audmux {
+                                        pinctrl_audmux_1: audmuxgrp-1 {
+                                                fsl,pins = <
+                                                        10 0x80000000   /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
+                                                        17 0x80000000   /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
+                                                        23 0x80000000   /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
+                                                        30 0x80000000   /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
+                                                >;
+                                        };
+                                };
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        820 0x80000000  /* MX53_PAD_FEC_MDC__FEC_MDC */
+                                                        779 0x80000000  /* MX53_PAD_FEC_MDIO__FEC_MDIO */
+                                                        786 0x80000000  /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
+                                                        791 0x80000000  /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
+                                                        796 0x80000000  /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
+                                                        799 0x80000000  /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
+                                                        804 0x80000000  /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
+                                                        808 0x80000000  /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
+                                                        811 0x80000000  /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
+                                                        816 0x80000000  /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        433 0x80000000  /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
+                                                        439 0x80000000  /* MX53_PAD_EIM_D17__ECSPI1_MISO */
+                                                        445 0x80000000  /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp-1 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+
+                                        pinctrl_esdhc1_2: esdhc1grp-2 {
+                                                fsl,pins = <
+                                                        995  0x1d5      /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
+                                                        1000 0x1d5      /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
+                                                        1010 0x1d5      /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
+                                                        1024 0x1d5      /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
+                                                        941  0x1d5      /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
+                                                        948  0x1d5      /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
+                                                        955  0x1d5      /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
+                                                        962  0x1d5      /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
+                                                        1005 0x1d5      /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
+                                                        1018 0x1d5      /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
+                                                >;
+                                        };
+                                };
+
+                                esdhc2 {
+                                        pinctrl_esdhc2_1: esdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1038 0x1d5      /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
+                                                        1032 0x1d5      /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
+                                                        1062 0x1d5      /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
+                                                        1056 0x1d5      /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
+                                                        1050 0x1d5      /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
+                                                        1044 0x1d5      /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
+                                                >;
+                                        };
+                                };
+
+                                esdhc3 {
+                                        pinctrl_esdhc3_1: esdhc3grp-1 {
+                                                fsl,pins = <
+                                                        943 0x1d5       /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
+                                                        950 0x1d5       /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
+                                                        957 0x1d5       /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
+                                                        964 0x1d5       /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
+                                                        893 0x1d5       /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
+                                                        900 0x1d5       /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
+                                                        906 0x1d5       /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
+                                                        912 0x1d5       /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
+                                                        857 0x1d5       /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
+                                                        863 0x1d5       /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
+                                                >;
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1_1: i2c1grp-1 {
+                                                fsl,pins = <
+                                                        333 0xc0000000  /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
+                                                        341 0xc0000000  /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
+                                                >;
+                                        };
+                                };
+
+                                i2c2 {
+                                        pinctrl_i2c2_1: i2c2grp-1 {
+                                                fsl,pins = <
+                                                        61 0xc0000000   /* MX53_PAD_KEY_ROW3__I2C2_SDA */
+                                                        53 0xc0000000   /* MX53_PAD_KEY_COL3__I2C2_SCL */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        346 0x1c5       /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
+                                                        354 0x1c5       /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
+                                                >;
+                                        };
+
+                                        pinctrl_uart1_2: uart1grp-2 {
+                                                fsl,pins = <
+                                                        828 0x1c5       /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
+                                                        832 0x1c5       /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
+                                                >;
+                                        };
+                                };
+
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        841 0x1c5       /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
+                                                        836 0x1c5       /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
+                                                >;
+                                        };
+                                };
+
+                                uart3 {
+                                        pinctrl_uart3_1: uart3grp-1 {
+                                                fsl,pins = <
+                                                        884 0x1c5       /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
+                                                        888 0x1c5       /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
+                                                        875 0x1c5       /* MX53_PAD_PATA_DA_1__UART3_CTS */
+                                                        880 0x1c5       /* MX53_PAD_PATA_DA_2__UART3_RTS */
+                                                >;
+                                        };
+                                };
+                        };
+
                         uart1: serial@53fbc000 {
                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                 reg = <0x53fbc000 0x4000>;
@@ -203,6 +385,20 @@
                                 status = "disabled";
                         };
 
+                        can1: can@53fc8000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fc8000 0x4000>;
+                                interrupts = <82>;
+                                status = "disabled";
+                        };
+
+                        can2: can@53fcc000 {
+                                compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x53fcc000 0x4000>;
+                                interrupts = <83>;
+                                status = "disabled";
+                        };
+
                         gpio5: gpio@53fdc000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fdc000 0x4000>;
@@ -277,6 +473,7 @@
                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
                                 reg = <0x63fb0000 0x4000>;
                                 interrupts = <6>;
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
                         };
 
                         cspi@63fc0000 {
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d792581672cc..15df4c105e89 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -28,8 +28,27 @@
                         status = "disabled"; /* gpmi nand conflicts with SD */
                 };
 
+                aips-bus@02000000 { /* AIPS1 */
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        176  0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
+                                                        1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
+                                                        1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
+                                                >;
+                                        };
+                                };
+                        };
+                };
+
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_2>;
                                 phy-mode = "rgmii";
                                 status = "okay";
                         };
@@ -52,6 +71,8 @@
                         };
 
                         uart4: serial@021f0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart4_1>;
                                 status = "okay";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 72f30f3e6171..d152328285a1 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -46,15 +46,20 @@
 
                         iomuxc@020e0000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_gpio_hog>;
+                                pinctrl-0 = <&pinctrl_hog>;
 
-                                gpios {
-                                        pinctrl_gpio_hog: gpiohog {
+                                hog {
+                                        pinctrl_hog: hoggrp {
                                                 fsl,pins = <
-                                                           144  0x80000000      /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
-                                                           121  0x80000000      /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
-                                                           953  0x80000000      /* MX6Q_PAD_GPIO_0__CCM_CLKO */
-                                                           >;
+                                                        1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
+                                                        1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
+                                                        121  0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                                        144  0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                        152  0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
+                                                        1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
+                                                        1270 0x1f0b0    /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
+                                                        953  0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                                >;
                                         };
                                 };
                         };
@@ -63,6 +68,9 @@
                 aips-bus@02100000 { /* AIPS2 */
                         usb@02184000 { /* USB OTG */
                                 vbus-supply = <&reg_usb_otg_vbus>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usbotg_1>;
+                                disable-over-current;
                                 status = "okay";
                         };
 
@@ -71,12 +79,16 @@
                         };
 
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                 phy-mode = "rgmii";
                                 phy-reset-gpios = <&gpio3 23 0>;
                                 status = "okay";
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_2>;
                                 cd-gpios = <&gpio7 0 0>;
                                 wp-gpios = <&gpio7 1 0>;
                                 vmmc-supply = <&reg_3p3v>;
@@ -84,6 +96,8 @@
                         };
 
                         usdhc@0219c000 { /* uSDHC4 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc4_2>;
                                 cd-gpios = <&gpio2 6 0>;
                                 wp-gpios = <&gpio2 7 0>;
                                 vmmc-supply = <&reg_3p3v>;
@@ -99,7 +113,7 @@
                         uart2: serial@021e8000 {
                                 status = "okay";
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_serial2_1>;
+                                pinctrl-0 = <&pinctrl_uart2_1>;
                         };
 
                         i2c@021a0000 { /* I2C1 */
@@ -111,6 +125,7 @@
                                 codec: sgtl5000@0a {
                                         compatible = "fsl,sgtl5000";
                                         reg = <0x0a>;
+                                        clocks = <&clks 169>;
                                         VDDA-supply = <&reg_2p5v>;
                                         VDDIO-supply = <&reg_3p3v>;
                                 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 07509a181178..e596c28c214d 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -22,28 +22,51 @@
         };
 
         soc {
-
                 aips-bus@02000000 { /* AIPS1 */
                         spba-bus@02000000 {
                                 uart1: serial@02020000 {
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_uart1_1>;
                                         status = "okay";
                                 };
                         };
+
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_hog>;
+
+                                hog {
+                                        pinctrl_hog: hoggrp {
+                                                fsl,pins = <
+                                                        1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
+                                                        1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
+                                                        1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
+                                                        1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
+                                                >;
+                                        };
+                                };
+                        };
                 };
 
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_enet_1>;
                                 phy-mode = "rgmii";
                                 status = "okay";
                         };
 
                         usdhc@02194000 { /* uSDHC2 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc2_1>;
                                 cd-gpios = <&gpio2 2 0>;
                                 wp-gpios = <&gpio2 3 0>;
                                 status = "okay";
                         };
 
                         usdhc@02198000 { /* uSDHC3 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_usdhc3_1>;
                                 cd-gpios = <&gpio2 0 0>;
                                 wp-gpios = <&gpio2 1 0>;
                                 status = "okay";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079f71a9..35e5895ba3df 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -97,18 +97,23 @@
                 dma-apbh@00110000 {
                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
                         reg = <0x00110000 0x2000>;
+                        clocks = <&clks 106>;
                 };
 
                 gpmi-nand@00112000 {
-                       compatible = "fsl,imx6q-gpmi-nand";
-                       #address-cells = <1>;
-                       #size-cells = <1>;
-                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
-                       reg-names = "gpmi-nand", "bch";
-                       interrupts = <0 13 0x04>, <0 15 0x04>;
-                       interrupt-names = "gpmi-dma", "bch";
-                       fsl,gpmi-dma-channel = <0>;
-                       status = "disabled";
+                        compatible = "fsl,imx6q-gpmi-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                        reg-names = "gpmi-nand", "bch";
+                        interrupts = <0 13 0x04>, <0 15 0x04>;
+                        interrupt-names = "gpmi-dma", "bch";
+                        clocks = <&clks 152>, <&clks 153>, <&clks 151>,
+                                 <&clks 150>, <&clks 149>;
+                        clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
+                                      "gpmi_bch_apb", "per1_bch";
+                        fsl,gpmi-dma-channel = <0>;
+                        status = "disabled";
                 };
 
                 timer@00a00600 {
@@ -150,6 +155,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02008000 0x4000>;
                                         interrupts = <0 31 0x04>;
+                                        clocks = <&clks 112>, <&clks 112>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -159,6 +166,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x0200c000 0x4000>;
                                         interrupts = <0 32 0x04>;
+                                        clocks = <&clks 113>, <&clks 113>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -168,6 +177,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02010000 0x4000>;
                                         interrupts = <0 33 0x04>;
+                                        clocks = <&clks 114>, <&clks 114>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -177,6 +188,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02014000 0x4000>;
                                         interrupts = <0 34 0x04>;
+                                        clocks = <&clks 115>, <&clks 115>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -186,6 +199,8 @@
                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
                                         reg = <0x02018000 0x4000>;
                                         interrupts = <0 35 0x04>;
+                                        clocks = <&clks 116>, <&clks 116>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -193,6 +208,8 @@
                                         compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                         reg = <0x02020000 0x4000>;
                                         interrupts = <0 26 0x04>;
+                                        clocks = <&clks 160>, <&clks 161>;
+                                        clock-names = "ipg", "per";
                                         status = "disabled";
                                 };
 
@@ -205,6 +222,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02028000 0x4000>;
                                         interrupts = <0 46 0x04>;
+                                        clocks = <&clks 178>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <38 37>;
                                         status = "disabled";
@@ -214,6 +232,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x0202c000 0x4000>;
                                         interrupts = <0 47 0x04>;
+                                        clocks = <&clks 179>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <42 41>;
                                         status = "disabled";
@@ -223,6 +242,7 @@
                                         compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
                                         reg = <0x02030000 0x4000>;
                                         interrupts = <0 48 0x04>;
+                                        clocks = <&clks 180>;
                                         fsl,fifo-depth = <15>;
                                         fsl,ssi-dma-events = <46 45>;
                                         status = "disabled";
@@ -362,20 +382,22 @@
                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                 reg = <0x020bc000 0x4000>;
                                 interrupts = <0 80 0x04>;
-                                status = "disabled";
+                                clocks = <&clks 0>;
                         };
 
                         wdog@020c0000 { /* WDOG2 */
                                 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
                                 reg = <0x020c0000 0x4000>;
                                 interrupts = <0 81 0x04>;
+                                clocks = <&clks 0>;
                                 status = "disabled";
                         };
 
-                        ccm@020c4000 {
+                        clks: ccm@020c4000 {
                                 compatible = "fsl,imx6q-ccm";
                                 reg = <0x020c4000 0x4000>;
                                 interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
                         };
 
                         anatop@020c8000 {
@@ -472,12 +494,14 @@
                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
                                 interrupts = <0 44 0x04>;
+                                clocks = <&clks 182>;
                         };
 
                         usbphy2: usbphy@020ca000 {
                                 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020ca000 0x1000>;
                                 interrupts = <0 45 0x04>;
+                                clocks = <&clks 183>;
                         };
 
                         snvs@020cc000 {
@@ -514,86 +538,207 @@
                                 /* shared pinctrl settings */
                                 audmux {
                                         pinctrl_audmux_1: audmux-1 {
-                                                fsl,pins = <18   0x80000000     /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
-                                                            1586 0x80000000     /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
-                                                            11   0x80000000     /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
-                                                            3    0x80000000>;   /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                fsl,pins = <
+                                                        18   0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
+                                                        1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
+                                                        11   0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
+                                                        3    0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        101 0x100b1     /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                        109 0x100b1     /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                        94  0x100b1     /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                                >;
+                                        };
+                                };
+
+                                enet {
+                                        pinctrl_enet_1: enetgrp-1 {
+                                                fsl,pins = <
+                                                        695 0x1b0b0     /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
+                                                        756 0x1b0b0     /* MX6Q_PAD_ENET_MDC__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
+                                        };
+
+                                        pinctrl_enet_2: enetgrp-2 {
+                                                fsl,pins = <
+                                                        890 0x1b0b0     /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
+                                                        909 0x1b0b0     /* MX6Q_PAD_KEY_COL2__ENET_MDC */
+                                                        24  0x1b0b0     /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
+                                                        30  0x1b0b0     /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
+                                                        34  0x1b0b0     /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
+                                                        39  0x1b0b0     /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
+                                                        44  0x1b0b0     /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
+                                                        56  0x1b0b0     /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
+                                                        702 0x1b0b0     /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
+                                                        74  0x1b0b0     /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
+                                                        52  0x1b0b0     /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
+                                                        61  0x1b0b0     /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
+                                                        66  0x1b0b0     /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
+                                                        70  0x1b0b0     /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
+                                                        48  0x1b0b0     /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
+                                                >;
                                         };
                                 };
 
                                 gpmi-nand {
                                         pinctrl_gpmi_nand_1: gpmi-nand-1 {
-                                                fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
-                                                            1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
-                                                            1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
-                                                            1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
-                                                            1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
-                                                            1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
-                                                            1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
-                                                            1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
-                                                            1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
-                                                            1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
-                                                            1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
-                                                            1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
-                                                            1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
-                                                            1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
-                                                            1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
-                                                            1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
-                                                            1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
-                                                            1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
-                                                            1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                fsl,pins = <
+                                                        1328 0xb0b1     /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+                                                        1336 0xb0b1     /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+                                                        1344 0xb0b1     /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+                                                        1352 0xb000     /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+                                                        1360 0xb0b1     /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+                                                        1365 0xb0b1     /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+                                                        1371 0xb0b1     /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+                                                        1378 0xb0b1     /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+                                                        1387 0xb0b1     /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+                                                        1393 0xb0b1     /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+                                                        1397 0xb0b1     /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+                                                        1405 0xb0b1     /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+                                                        1413 0xb0b1     /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+                                                        1421 0xb0b1     /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+                                                        1429 0xb0b1     /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+                                                        1437 0xb0b1     /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+                                                        1445 0xb0b1     /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+                                                        1453 0xb0b1     /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                        1463 0x00b1     /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                                >;
                                         };
                                 };
 
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
-                                                fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
-                                                            196 0x4001b8b1>;    /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                fsl,pins = <
+                                                        137 0x4001b8b1  /* MX6Q_PAD_EIM_D21__I2C1_SCL */
+                                                        196 0x4001b8b1  /* MX6Q_PAD_EIM_D28__I2C1_SDA */
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        1140 0x1b0b1    /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
+                                                        1148 0x1b0b1    /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
+                                                >;
                                         };
                                 };
 
-                                serial2 {
-                                        pinctrl_serial2_1: serial2grp-1 {
-                                                fsl,pins = <183 0x1b0b1         /* MX6Q_PAD_EIM_D26__UART2_TXD */
-                                                            191 0x1b0b1>;       /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                uart2 {
+                                        pinctrl_uart2_1: uart2grp-1 {
+                                                fsl,pins = <
+                                                        183 0x1b0b1     /* MX6Q_PAD_EIM_D26__UART2_TXD */
+                                                        191 0x1b0b1     /* MX6Q_PAD_EIM_D27__UART2_RXD */
+                                                >;
+                                        };
+                                };
+
+                                uart4 {
+                                        pinctrl_uart4_1: uart4grp-1 {
+                                                fsl,pins = <
+                                                        877 0x1b0b1     /* MX6Q_PAD_KEY_COL0__UART4_TXD */
+                                                        885 0x1b0b1     /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
+                                                >;
+                                        };
+                                };
+
+                                usbotg {
+                                        pinctrl_usbotg_1: usbotggrp-1 {
+                                                fsl,pins = <
+                                                        1592 0x17059    /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        1577 0x17059    /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
+                                                        1569 0x10059    /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
+                                                        16   0x17059    /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
+                                                        0    0x17059    /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
+                                                        8    0x17059    /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
+                                                        1583 0x17059    /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
+                                                        1430 0x17059    /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
+                                                        1438 0x17059    /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
+                                                        1446 0x17059    /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
+                                                        1454 0x17059    /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
+                                                >;
                                         };
                                 };
 
                                 usdhc3 {
                                         pinctrl_usdhc3_1: usdhc3grp-1 {
-                                                fsl,pins = <1273 0x17059        /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
-                                                            1281 0x10059        /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
-                                                            1289 0x17059        /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
-                                                            1297 0x17059        /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
-                                                            1305 0x17059        /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
-                                                            1312 0x17059        /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
-                                                            1265 0x17059        /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
-                                                            1257 0x17059        /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
-                                                            1249 0x17059        /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
-                                                            1241 0x17059>;      /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                fsl,pins = <
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                        1265 0x17059    /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
+                                                        1257 0x17059    /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
+                                                        1249 0x17059    /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
+                                                        1241 0x17059    /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
+                                                >;
+                                        };
+
+                                        pinctrl_usdhc3_2: usdhc3grp-2 {
+                                                fsl,pins = <
+                                                        1273 0x17059    /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
+                                                        1281 0x10059    /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
+                                                        1289 0x17059    /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
+                                                        1297 0x17059    /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
+                                                        1305 0x17059    /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
+                                                        1312 0x17059    /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
+                                                >;
                                         };
                                 };
 
                                 usdhc4 {
                                         pinctrl_usdhc4_1: usdhc4grp-1 {
-                                                fsl,pins = <1386 0x17059        /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
-                                                            1392 0x10059        /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
-                                                            1462 0x17059        /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
-                                                            1470 0x17059        /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
-                                                            1478 0x17059        /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
-                                                            1486 0x17059        /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
-                                                            1493 0x17059        /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
-                                                            1501 0x17059        /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
-                                                            1509 0x17059        /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
-                                                            1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                fsl,pins = <
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                        1493 0x17059    /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
+                                                        1501 0x17059    /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
+                                                        1509 0x17059    /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
+                                                        1517 0x17059    /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
+                                                >;
                                         };
-                                };
 
-                                ecspi1 {
-                                        pinctrl_ecspi1_1: ecspi1grp-1 {
-                                                fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
-                                                            109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
-                                                            94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                        pinctrl_usdhc4_2: usdhc4grp-2 {
+                                                fsl,pins = <
+                                                        1386 0x17059    /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
+                                                        1392 0x10059    /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
+                                                        1462 0x17059    /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
+                                                        1470 0x17059    /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
+                                                        1478 0x17059    /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
+                                                        1486 0x17059    /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
+                                                >;
                                         };
                                 };
                         };
@@ -612,6 +757,9 @@
                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
                                 reg = <0x020ec000 0x4000>;
                                 interrupts = <0 2 0x04>;
+                                clocks = <&clks 155>, <&clks 155>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q-to1.bin";
                         };
                 };
 
@@ -635,7 +783,9 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184000 0x200>;
                                 interrupts = <0 43 0x04>;
+                                clocks = <&clks 162>;
                                 fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
                                 status = "disabled";
                         };
 
@@ -643,7 +793,9 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184200 0x200>;
                                 interrupts = <0 40 0x04>;
+                                clocks = <&clks 162>;
                                 fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                 status = "disabled";
                         };
 
@@ -651,6 +803,8 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184400 0x200>;
                                 interrupts = <0 41 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -658,13 +812,24 @@
                                 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
                                 reg = <0x02184600 0x200>;
                                 interrupts = <0 42 0x04>;
+                                clocks = <&clks 162>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks 162>;
+                        };
+
                         ethernet@02188000 {
                                 compatible = "fsl,imx6q-fec";
                                 reg = <0x02188000 0x4000>;
                                 interrupts = <0 118 0x04 0 119 0x04>;
+                                clocks = <&clks 117>, <&clks 117>;
+                                clock-names = "ipg", "ahb";
                                 status = "disabled";
                         };
 
@@ -677,6 +842,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02190000 0x4000>;
                                 interrupts = <0 22 0x04>;
+                                clocks = <&clks 163>, <&clks 163>, <&clks 163>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -684,6 +851,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02194000 0x4000>;
                                 interrupts = <0 23 0x04>;
+                                clocks = <&clks 164>, <&clks 164>, <&clks 164>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -691,6 +860,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x02198000 0x4000>;
                                 interrupts = <0 24 0x04>;
+                                clocks = <&clks 165>, <&clks 165>, <&clks 165>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -698,6 +869,8 @@
                                 compatible = "fsl,imx6q-usdhc";
                                 reg = <0x0219c000 0x4000>;
                                 interrupts = <0 25 0x04>;
+                                clocks = <&clks 166>, <&clks 166>, <&clks 166>;
+                                clock-names = "ipg", "ahb", "per";
                                 status = "disabled";
                         };
 
@@ -707,6 +880,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a0000 0x4000>;
                                 interrupts = <0 36 0x04>;
+                                clocks = <&clks 125>;
                                 status = "disabled";
                         };
 
@@ -716,6 +890,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a4000 0x4000>;
                                 interrupts = <0 37 0x04>;
+                                clocks = <&clks 126>;
                                 status = "disabled";
                         };
 
@@ -725,6 +900,7 @@
                                 compatible = "fsl,imx6q-i2c", "fsl,imx1-i2c";
                                 reg = <0x021a8000 0x4000>;
                                 interrupts = <0 38 0x04>;
+                                clocks = <&clks 127>;
                                 status = "disabled";
                         };
 
@@ -788,6 +964,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021e8000 0x4000>;
                                 interrupts = <0 27 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -795,6 +973,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021ec000 0x4000>;
                                 interrupts = <0 28 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -802,6 +982,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f0000 0x4000>;
                                 interrupts = <0 29 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
 
@@ -809,6 +991,8 @@
                                 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                 reg = <0x021f4000 0x4000>;
                                 interrupts = <0 30 0x04>;
+                                clocks = <&clks 160>, <&clks 161>;
+                                clock-names = "ipg", "per";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi
index 80f74e256408..0514fb41627e 100644
--- a/arch/arm/boot/dts/mmp2.dtsi
+++ b/arch/arm/boot/dts/mmp2.dtsi
@@ -26,6 +26,11 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
+
                 axi@d4200000 {  /* AXI */
                         compatible = "mrvl,axi-bus", "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 45bc4bb04e57..31f2157cd7d7 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -7,7 +7,7 @@
         compatible = "qcom,msm8660-surf", "qcom,msm8660";
         interrupt-parent = <&intc>;
 
-        intc: interrupt-controller@02080000 {
+        intc: interrupt-controller@2080000 {
                 compatible = "qcom,msm-8660-qgic";
                 interrupt-controller;
                 #interrupt-cells = <3>;
@@ -15,6 +15,23 @@
                       < 0x02081000 0x1000 >;
         };
 
+        timer@2000004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x02000004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x40000>;
+        };
+
+        timer@2000024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 0 0x301>;
+                reg = <0x02000024 0x10>,
+                      <0x02000034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x40000>;
+        };
+
         serial@19c400000 {
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x19c40000 0x1000>,
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
new file mode 100644
index 000000000000..9e621b5ad3dd
--- /dev/null
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -0,0 +1,41 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Qualcomm MSM8960 CDP";
+        compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller@2000000 {
+                compatible = "qcom,msm-qgic2";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x02000000 0x1000 >,
+                      < 0x02002000 0x1000 >;
+        };
+
+        timer@200a004 {
+                compatible = "qcom,msm-gpt", "qcom,msm-timer";
+                interrupts = <1 2 0x301>;
+                reg = <0x0200a004 0x10>;
+                clock-frequency = <32768>;
+                cpu-offset = <0x80000>;
+        };
+
+        timer@200a024 {
+                compatible = "qcom,msm-dgt", "qcom,msm-timer";
+                interrupts = <1 1 0x301>;
+                reg = <0x0200a024 0x10>,
+                      <0x0200a034 0x4>;
+                clock-frequency = <6750000>;
+                cpu-offset = <0x80000>;
+        };
+
+        serial@19c400000 {
+                compatible = "qcom,msm-hsuart", "qcom,msm-uart";
+                reg = <0x16440000 0x1000>,
+                      <0x16400000 0x1000>;
+                interrupts = <0 154 0x0>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 25b50b759dec..77b84e17c477 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2.dtsi"
+/include/ "omap2420.dtsi"
 
 / {
         model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
new file mode 100644
index 000000000000..bfd76b4a0ddc
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Device Tree Source for OMAP2420 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+        compatible = "ti,omap2420", "ti,omap2";
+
+        ocp {
+                omap2420_pmx: pinmux@48000030 {
+                        compatible = "ti,omap2420-padconf", "pinctrl-single";
+                        reg = <0x48000030 0x0113>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2420-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,hwmods = "mcbsp2";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
new file mode 100644
index 000000000000..4565d9750f4d
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Device Tree Source for OMAP243x SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap2.dtsi"
+
+/ {
+        compatible = "ti,omap2430", "ti,omap2";
+
+        ocp {
+                omap2430_pmx: pinmux@49002030 {
+                        compatible = "ti,omap2430-padconf", "pinctrl-single";
+                        reg = <0x49002030 0x0154>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <8>;
+                        pinctrl-single,function-mask = <0x3f>;
+                };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <64>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>, /* RX interrupt */
+                                     <61>; /* RX overflow interrupt */
+                        interrupt-names = "common", "tx", "rx", "rx_overflow";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@48076000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48076000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@4808c000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808c000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@4808e000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x4808e000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <18>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap2430-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <19>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index cdcb98c7e075..c38cf76df81f 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,16 +7,44 @@
  */
 /dts-v1/;
 
-/include/ "omap3.dtsi"
+/include/ "omap36xx.dtsi"
 
 / {
-        model = "TI OMAP3 BeagleBoard";
-        compatible = "ti,omap3-beagle", "ti,omap3";
+        model = "TI OMAP3 BeagleBoard xM";
+        compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3";
 
         memory {
                 device_type = "memory";
                 reg = <0x80000000 0x20000000>; /* 512 MB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+                pmu_stat {
+                        label = "beagleboard::pmu_stat";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                };
+
+                heartbeat {
+                        label = "beagleboard::usr0";
+                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        linux,default-trigger = "heartbeat";
+                };
+
+                mmc {
+                        label = "beagleboard::usr1";
+                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        linux,default-trigger = "mmc0";
+                };
+        };
+
+        sound {
+                compatible = "ti,omap-twl4030";
+                ti,model = "omap3beagle";
+
+                ti,mcbsp = <&mcbsp2>;
+                ti,codec = <&twl_audio>;
+        };
 };
 
 &i2c1 {
@@ -27,11 +55,17 @@
                 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
                 interrupt-parent = <&intc>;
 
-                vsim: regulator@10 {
+                vsim: regulator-vsim {
                         compatible = "ti,twl4030-vsim";
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <3000000>;
                 };
+
+                twl_audio: audio {
+                        compatible = "ti,twl4030-audio";
+                        codec {
+                        };
+                };
         };
 };
 
@@ -67,3 +101,15 @@
 &mmc3 {
         status = "disabled";
 };
+
+&twl_gpio {
+        ti,use-leds;
+        /* pullups: BIT(1) */
+        ti,pullups = <0x000002>;
+        /*
+         * pulldowns:
+         * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
+         * BIT(15), BIT(16), BIT(17)
+         */
+        ti,pulldowns = <0x03a1c4>;
+};
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index f349ee9182ce..e8ba1c247a39 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -17,6 +17,15 @@
                 device_type = "memory";
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
+
+        leds {
+                compatible = "gpio-leds";
+                ledb {
+                        label = "omap3evm::ledb";
+                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        linux,default-trigger = "default-on";
+                };
+        };
 };
 
 &i2c1 {
@@ -46,3 +55,7 @@
                 reg = <0x5c>;
         };
 };
+
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
new file mode 100644
index 000000000000..89808ce01673
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The Gumstix Overo must be combined with an expansion board.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        leds {
+                compatible = "gpio-leds";
+                overo {
+                        label = "overo:blue:COM";
+                        gpios = <&twl_gpio 19 0>;
+                        linux,default-trigger = "mmc0";
+                };
+        };
+};
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+/include/ "twl4030.dtsi"
+
+/* i2c2 pins are used for gpio */
+&i2c2 {
+        status = "disabled";
+};
+
+/* on board microSD slot */
+&mmc1 {
+        vmmc-supply = <&vmmc1>;
+        bus-width = <4>;
+};
+
+/* optional on board WiFi */
+&mmc2 {
+        bus-width = <4>;
+};
+
+&twl_gpio {
+        ti,use-leds;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
new file mode 100644
index 000000000000..a13d12de77ff
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2012 Florian Vaussard, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Tobi expansion board is manufactured by Gumstix Inc.
+ */
+
+/include/ "omap3-overo.dtsi"
+
+/ {
+        model = "TI OMAP3 Gumstix Overo on Tobi";
+        compatible = "ti,omap3-tobi", "ti,omap3-overo", "ti,omap3";
+
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "overo:red:gpio21";
+                        gpios = <&gpio1 21 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
+
+&i2c3 {
+        clock-frequency = <100000>;
+};
+
+&mmc3 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 810947198208..f38ea8771b44 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -17,7 +17,6 @@
                 serial0 = &uart1;
                 serial1 = &uart2;
                 serial2 = &uart3;
-                serial3 = &uart4;
         };
 
         cpus {
@@ -69,6 +68,24 @@
                         reg = <0x48200000 0x1000>;
                 };
 
+                omap3_pmx_core: pinmux@48002030 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002030 0x05cc>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+
+                omap3_pmx_wkup: pinmux@0x48002a58 {
+                        compatible = "ti,omap3-padconf", "pinctrl-single";
+                        reg = <0x48002a58 0x5c>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+
                 gpio1: gpio@48310000 {
                         compatible = "ti,omap3-gpio";
                         ti,hwmods = "gpio1";
@@ -141,12 +158,6 @@
                         clock-frequency = <48000000>;
                 };
 
-                uart4: serial@49042000 {
-                        compatible = "ti,omap3-uart";
-                        ti,hwmods = "uart4";
-                        clock-frequency = <48000000>;
-                };
-
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap3-i2c";
                         #address-cells = <1>;
@@ -220,5 +231,74 @@
                         compatible = "ti,omap3-wdt";
                         ti,hwmods = "wd_timer2";
                 };
+
+                mcbsp1: mcbsp@48074000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48074000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <16>, /* OCP compliant interrupt */
+                                     <59>, /* TX interrupt */
+                                     <60>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@49022000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49022000 0xff>,
+                              <0x49028000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <17>, /* OCP compliant interrupt */
+                                     <62>, /* TX interrupt */
+                                     <63>, /* RX interrupt */
+                                     <4>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <1280>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@49024000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49024000 0xff>,
+                              <0x4902a000 0xff>;
+                        reg-names = "mpu", "sidetone";
+                        interrupts = <22>, /* OCP compliant interrupt */
+                                     <89>, /* TX interrupt */
+                                     <90>, /* RX interrupt */
+                                     <5>;  /* Sidetone */
+                        interrupt-names = "common", "tx", "rx", "sidetone";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@49026000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x49026000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <23>, /* OCP compliant interrupt */
+                                     <54>, /* TX interrupt */
+                                     <55>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                mcbsp5: mcbsp@48096000 {
+                        compatible = "ti,omap3-mcbsp";
+                        reg = <0x48096000 0xff>;
+                        reg-names = "mpu";
+                        interrupts = <27>, /* OCP compliant interrupt */
+                                     <81>, /* TX interrupt */
+                                     <82>; /* RX interrupt */
+                        interrupt-names = "common", "tx", "rx";
+                        interrupt-parent = <&intc>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp5";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
new file mode 100644
index 000000000000..96bf0287cb9f
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Device Tree Source for OMAP3 SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "omap3.dtsi"
+
+/ {
+        aliases {
+                serial3 = &uart4;
+        };
+
+        ocp {
+                uart4: serial@49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 9880c12877b3..20b966ee1bb3 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 PandaBoard";
@@ -126,3 +127,13 @@
         ti,non-removable;
         bus-width = <4>;
 };
+
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 72216e932fc0..94a23b39033d 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -8,6 +8,7 @@
 /dts-v1/;
 
 /include/ "omap4.dtsi"
+/include/ "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 SDP board";
@@ -18,7 +19,7 @@
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
-        vdd_eth: fixedregulator@0 {
+        vdd_eth: fixedregulator-vdd-eth {
                 compatible = "regulator-fixed";
                 regulator-name = "VDD_ETH";
                 regulator-min-microvolt = <3300000>;
@@ -28,7 +29,7 @@
                 regulator-boot-on;
         };
 
-        vbat: fixedregulator@2 {
+        vbat: fixedregulator-vbat {
                 compatible = "regulator-fixed";
                 regulator-name = "VBAT";
                 regulator-min-microvolt = <3750000>;
@@ -115,6 +116,33 @@
         };
 };
 
+&omap4_pmx_core {
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
+                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
+                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
+                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
+                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
+                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
+                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+
+        uart4_pins: pinmux_uart4_pins {
+                pinctrl-single,pins = <
+                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
+                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                >;
+        };
+};
+
 &i2c1 {
         clock-frequency = <400000>;
 
@@ -226,3 +254,98 @@
         bus-width = <4>;
         ti,non-removable;
 };
+
+&emif1 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&emif2 {
+        cs1-used;
+        device-handle = <&elpida_ECB240ABACN>;
+};
+
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x00000012      /* KEY_E */
+                        0x00010013      /* KEY_R */
+                        0x00020014      /* KEY_T */
+                        0x00030066      /* KEY_HOME */
+                        0x0004003f      /* KEY_F5 */
+                        0x000500f0      /* KEY_UNKNOWN */
+                        0x00060017      /* KEY_I */
+                        0x0007002a      /* KEY_LEFTSHIFT */
+                        0x01000020      /* KEY_D*/
+                        0x01010021      /* KEY_F */
+                        0x01020022      /* KEY_G */
+                        0x010300e7      /* KEY_SEND */
+                        0x01040040      /* KEY_F6 */
+                        0x010500f0      /* KEY_UNKNOWN */
+                        0x01060025      /* KEY_K */
+                        0x0107001c      /* KEY_ENTER */
+                        0x0200002d      /* KEY_X */
+                        0x0201002e      /* KEY_C */
+                        0x0202002f      /* KEY_V */
+                        0x0203006b      /* KEY_END */
+                        0x02040041      /* KEY_F7 */
+                        0x020500f0      /* KEY_UNKNOWN */
+                        0x02060034      /* KEY_DOT */
+                        0x0207003a      /* KEY_CAPSLOCK */
+                        0x0300002c      /* KEY_Z */
+                        0x0301004e      /* KEY_KPLUS */
+                        0x03020030      /* KEY_B */
+                        0x0303003b      /* KEY_F1 */
+                        0x03040042      /* KEY_F8 */
+                        0x030500f0      /* KEY_UNKNOWN */
+                        0x03060018      /* KEY_O */
+                        0x03070039      /* KEY_SPACE */
+                        0x04000011      /* KEY_W */
+                        0x04010015      /* KEY_Y */
+                        0x04020016      /* KEY_U */
+                        0x0403003c      /* KEY_F2 */
+                        0x04040073      /* KEY_VOLUMEUP */
+                        0x040500f0      /* KEY_UNKNOWN */
+                        0x04060026      /* KEY_L */
+                        0x04070069      /* KEY_LEFT */
+                        0x0500001f      /* KEY_S */
+                        0x05010023      /* KEY_H */
+                        0x05020024      /* KEY_J */
+                        0x0503003d      /* KEY_F3 */
+                        0x05040043      /* KEY_F9 */
+                        0x05050072      /* KEY_VOLUMEDOWN */
+                        0x05060032      /* KEY_M */
+                        0x0507006a      /* KEY_RIGHT */
+                        0x06000010      /* KEY_Q */
+                        0x0601001e      /* KEY_A */
+                        0x06020031      /* KEY_N */
+                        0x0603009e      /* KEY_BACK */
+                        0x0604000e      /* KEY_BACKSPACE */
+                        0x060500f0      /* KEY_UNKNOWN */
+                        0x06060019      /* KEY_P */
+                        0x06070067      /* KEY_UP */
+                        0x07000094      /* KEY_PROG1 */
+                        0x07010095      /* KEY_PROG2 */
+                        0x070200ca      /* KEY_PROG3 */
+                        0x070300cb      /* KEY_PROG4 */
+                        0x0704003e      /* KEY_F4 */
+                        0x070500f0      /* KEY_UNKNOWN */
+                        0x07060160      /* KEY_OK */
+                        0x0707006c>;    /* KEY_DOWN */
+        linux,input-no-autorepeat;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart4_pins>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 04cbbcb6ff91..5d1c48459e6e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -30,12 +30,35 @@
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
                 };
         };
 
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+
+        L2: l2-cache-controller@48242000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x48242000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
+        local-timer@0x48240600 {
+                compatible = "arm,cortex-a9-twd-timer";
+                reg = <0x48240600 0x20>;
+                interrupts = <1 13 0x304>;
+        };
+
         /*
          * The soc node represents the soc top level view. It is uses for IPs
          * that are not memory mapped in the MPU view or for the MPU itself.
@@ -61,30 +84,6 @@
         /*
          * XXX: Use a flat representation of the OMAP4 interconnect.
          * The real OMAP interconnect network is quite complex.
-         *
-         * MPU -+-- MPU_PRIVATE - GIC, L2
-         *      |
-         *      +----------------+----------+
-         *      |                |          |
-         *      +            +- EMIF - DDR  |
-         *      |            |              |
-         *      |            +     +--------+
-         *      |            |     |
-         *      |            +- L4_ABE - AESS, MCBSP, TIMERs...
-         *      |            |
-         *      +- L3_MAIN --+- L4_CORE - IPs...
-         *                   |
-         *                   +- L4_PER - IPs...
-         *                   |
-         *                   +- L4_CFG -+- L4_WKUP - IPs...
-         *                   |          |
-         *                   |          +- IPs...
-         *                   +- IPU ----+
-         *                   |          |
-         *                   +- DSP ----+
-         *                   |          |
-         *                   +- DSS ----+
-         *
          * Since that will not bring real advantage to represent that in DT for
          * the moment, just use a fake OCP bus entry to represent the whole bus
          * hierarchy.
@@ -96,16 +95,27 @@
                 ranges;
                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 
-                gic: interrupt-controller@48241000 {
-                        compatible = "arm,cortex-a9-gic";
-                        interrupt-controller;
-                        #interrupt-cells = <3>;
-                        reg = <0x48241000 0x1000>,
-                              <0x48240100 0x0100>;
+                omap4_pmx_core: pinmux@4a100040 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a100040 0x0196>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
+                };
+                omap4_pmx_wkup: pinmux@4a31e040 {
+                        compatible = "ti,omap4-padconf", "pinctrl-single";
+                        reg = <0x4a31e040 0x0038>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <16>;
+                        pinctrl-single,function-mask = <0x7fff>;
                 };
 
                 gpio1: gpio@4a310000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4a310000 0x200>;
+                        interrupts = <0 29 0x4>;
                         ti,hwmods = "gpio1";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -115,6 +125,8 @@
 
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48055000 0x200>;
+                        interrupts = <0 30 0x4>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -124,6 +136,8 @@
 
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48057000 0x200>;
+                        interrupts = <0 31 0x4>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -133,6 +147,8 @@
 
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x48059000 0x200>;
+                        interrupts = <0 32 0x4>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -142,6 +158,8 @@
 
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4805b000 0x200>;
+                        interrupts = <0 33 0x4>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -151,6 +169,8 @@
 
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
+                        reg = <0x4805d000 0x200>;
+                        interrupts = <0 34 0x4>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -160,30 +180,40 @@
 
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806a000 0x100>;
+                        interrupts = <0 72 0x4>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
 
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806c000 0x100>;
+                        interrupts = <0 73 0x4>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
 
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x48020000 0x100>;
+                        interrupts = <0 74 0x4>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
 
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
+                        reg = <0x4806e000 0x100>;
+                        interrupts = <0 70 0x4>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
 
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48070000 0x100>;
+                        interrupts = <0 56 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -191,6 +221,8 @@
 
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48072000 0x100>;
+                        interrupts = <0 57 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -198,6 +230,8 @@
 
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48060000 0x100>;
+                        interrupts = <0 61 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -205,6 +239,8 @@
 
                 i2c4: i2c@48350000 {
                         compatible = "ti,omap4-i2c";
+                        reg = <0x48350000 0x100>;
+                        interrupts = <0 62 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -212,6 +248,8 @@
 
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x48098000 0x200>;
+                        interrupts = <0 65 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -220,6 +258,8 @@
 
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x4809a000 0x200>;
+                        interrupts = <0 66 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -228,6 +268,8 @@
 
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x480b8000 0x200>;
+                        interrupts = <0 91 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -236,6 +278,8 @@
 
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
+                        reg = <0x480ba000 0x200>;
+                        interrupts = <0 48 0x4>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -244,6 +288,8 @@
 
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x4809c000 0x400>;
+                        interrupts = <0 83 0x4>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -251,30 +297,40 @@
 
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480b4000 0x400>;
+                        interrupts = <0 86 0x4>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                 };
 
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480ad000 0x400>;
+                        interrupts = <0 94 0x4>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                 };
 
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d1000 0x400>;
+                        interrupts = <0 96 0x4>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                 };
 
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
+                        reg = <0x480d5000 0x400>;
+                        interrupts = <0 59 0x4>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                 };
 
                 wdt2: wdt@4a314000 {
                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                        reg = <0x4a314000 0x80>;
+                        interrupts = <0 80 0x4>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -282,6 +338,7 @@
                         compatible = "ti,omap4-mcpdm";
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                         interrupts = <0 112 0x4>;
                         interrupt-parent = <&gic>;
                         ti,hwmods = "mcpdm";
@@ -291,9 +348,87 @@
                         compatible = "ti,omap4-dmic";
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
                         interrupts = <0 114 0x4>;
                         interrupt-parent = <&gic>;
                         ti,hwmods = "dmic";
                 };
+
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
+
+                mcbsp4: mcbsp@48096000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x48096000 0xff>; /* L4 Interconnect */
+                        reg-names = "mpu";
+                        interrupts = <0 16 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp4";
+                };
+
+                keypad: keypad@4a31c000 {
+                        compatible = "ti,omap4-keypad";
+                        reg = <0x4a31c000 0x80>;
+                        interrupts = <0 120 0x4>;
+                        reg-names = "mpu";
+                        ti,hwmods = "kbd";
+                };
+
+                emif1: emif@4c000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4c000000 0x100>;
+                        interrupts = <0 110 0x4>;
+                        ti,hwmods = "emif1";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
+
+                emif2: emif@4d000000 {
+                        compatible = "ti,emif-4d";
+                        reg = <0x4d000000 0x100>;
+                        interrupts = <0 111 0x4>;
+                        ti,hwmods = "emif2";
+                        phy-type = <1>;
+                        hw-caps-read-idle-ctrl;
+                        hw-caps-ll-interface;
+                        hw-caps-temp-alert;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index 200c39ad1c82..9c41a3f311aa 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -17,4 +17,68 @@
                 device_type = "memory";
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
+
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        status = "disabled";
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+
+        /* Pressure Sensor */
+        bmp085@77 {
+                compatible = "bosch,bmp085";
+                reg = <0x77>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+
+        /* Temperature Sensor */
+        tmp102@48{
+                compatible = "ti,tmp102";
+                reg = <0x48>;
+        };
+};
+
+&keypad {
+        keypad,num-rows = <8>;
+        keypad,num-columns = <8>;
+        linux,keymap = <0x02020073      /* VOLUP */
+                        0x02030072      /* VOLDOWM */
+                        0x020400e7      /* SEND */
+                        0x02050066      /* HOME */
+                        0x0206006b      /* END */
+                        0x020700d9>;    /* SEARCH */
+        linux,input-no-autorepeat;
 };
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 57e527083746..5db33f481a33 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -33,9 +33,21 @@
         cpus {
                 cpu@0 {
                         compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a15";
+                        timer {
+                                compatible = "arm,armv7-timer";
+                                /* 14th PPI IRQ, active low level-sensitive */
+                                interrupts = <1 14 0x308>;
+                                clock-frequency = <6144000>;
+                        };
                 };
         };
 
@@ -145,6 +157,41 @@
                         #interrupt-cells = <1>;
                 };
 
+                i2c1: i2c@48070000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@48072000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@48060000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+
+                i2c4: i2c@4807A000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c4";
+                };
+
+                i2c5: i2c@4807C000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c5";
+                };
+
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         ti,hwmods = "uart1";
@@ -180,5 +227,97 @@
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
+
+                mmc1: mmc@4809c000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc1";
+                        ti,dual-volt;
+                        ti,needs-special-reset;
+                };
+
+                mmc2: mmc@480b4000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc2";
+                        ti,needs-special-reset;
+                };
+
+                mmc3: mmc@480ad000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc3";
+                        ti,needs-special-reset;
+                };
+
+                mmc4: mmc@480d1000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc4";
+                        ti,needs-special-reset;
+                };
+
+                mmc5: mmc@480d5000 {
+                        compatible = "ti,omap4-hsmmc";
+                        ti,hwmods = "mmc5";
+                        ti,needs-special-reset;
+                };
+
+                keypad: keypad@4ae1c000 {
+                        compatible = "ti,omap4-keypad";
+                        ti,hwmods = "kbd";
+                };
+
+                mcpdm: mcpdm@40132000 {
+                        compatible = "ti,omap4-mcpdm";
+                        reg = <0x40132000 0x7f>, /* MPU private access */
+                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 112 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "mcpdm";
+                };
+
+                dmic: dmic@4012e000 {
+                        compatible = "ti,omap4-dmic";
+                        reg = <0x4012e000 0x7f>, /* MPU private access */
+                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 114 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "dmic";
+                };
+
+                mcbsp1: mcbsp@40122000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40122000 0xff>, /* MPU private access */
+                              <0x49022000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 17 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp1";
+                };
+
+                mcbsp2: mcbsp@40124000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40124000 0xff>, /* MPU private access */
+                              <0x49024000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 22 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp2";
+                };
+
+                mcbsp3: mcbsp@40126000 {
+                        compatible = "ti,omap4-mcbsp";
+                        reg = <0x40126000 0xff>, /* MPU private access */
+                              <0x49026000 0xff>; /* L3 Interconnect */
+                        reg-names = "mpu", "dma";
+                        interrupts = <0 23 0x4>;
+                        interrupt-names = "common";
+                        interrupt-parent = <&gic>;
+                        ti,buffer-size = <128>;
+                        ti,hwmods = "mcbsp3";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index 802ec5b2fd00..90fdbd77f274 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -135,13 +135,11 @@
                         ssp0: ssp@20084000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                pl022,num-chipselects = <1>;
+                                num-cs = <1>;
                                 cs-gpios = <&gpio 3 5 0>;
 
                                 eeprom: at25@0 {
-                                        pl022,hierarchy = <0>;
                                         pl022,interface = <0>;
-                                        pl022,slave-tx-disable = <0>;
                                         pl022,com-mode = <0>;
                                         pl022,rx-level-trig = <1>;
                                         pl022,tx-level-trig = <1>;
@@ -191,16 +189,14 @@
         leds {
                 compatible = "gpio-leds";
 
-                led0 {
-                        gpios = <&gpio 5 1 1>; /* GPO_P3 1, GPIO 80, active low */
-                        linux,default-trigger = "heartbeat";
+                led0 { /* red */
+                        gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
                         default-state = "off";
                 };
 
-                led1 {
-                        gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
-                        linux,default-trigger = "timer";
-                        default-state = "off";
+                led1 { /* green */
+                        gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
+                        linux,default-trigger = "heartbeat";
                 };
         };
 };
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
deleted file mode 100644
index 34ae3a64ba25..000000000000
--- a/arch/arm/boot/dts/prima2-cb.dts
+++ /dev/null
@@ -1,424 +0,0 @@
-/dts-v1/;
-/ {
-        model = "SiRF Prima2 eVB";
-        compatible = "sirf,prima2-cb", "sirf,prima2";
-        #address-cells = <1>;
-        #size-cells = <1>;
-        interrupt-parent = <&intc>;
-
-        memory {
-                reg = <0x00000000 0x20000000>;
-        };
-
-        chosen {
-                bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
-                linux,stdout-path = &uart1;
-        };
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu@0 {
-                        reg = <0x0>;
-                        d-cache-line-size = <32>;
-                        i-cache-line-size = <32>;
-                        d-cache-size = <32768>;
-                        i-cache-size = <32768>;
-                        /* from bootloader */
-                        timebase-frequency = <0>;
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                };
-        };
-
-        axi {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0x40000000 0x40000000 0x80000000>;
-
-                l2-cache-controller@80040000 {
-                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
-                        reg = <0x80040000 0x1000>;
-                        interrupts = <59>;
-                        arm,tag-latency = <1 1 1>;
-                        arm,data-latency = <1 1 1>;
-                        arm,filter-ranges = <0 0x40000000>;
-                };
-
-                intc: interrupt-controller@80020000 {
-                        #interrupt-cells = <1>;
-                        interrupt-controller;
-                        compatible = "sirf,prima2-intc";
-                        reg = <0x80020000 0x1000>;
-                };
-
-                sys-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x88000000 0x88000000 0x40000>;
-
-                        clock-controller@88000000 {
-                                compatible = "sirf,prima2-clkc";
-                                reg = <0x88000000 0x1000>;
-                                interrupts = <3>;
-                        };
-
-                        reset-controller@88010000 {
-                                compatible = "sirf,prima2-rstc";
-                                reg = <0x88010000 0x1000>;
-                        };
-
-                        rsc-controller@88020000 {
-                                compatible = "sirf,prima2-rsc";
-                                reg = <0x88020000 0x1000>;
-                        };
-                };
-
-                mem-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90000000 0x90000000 0x10000>;
-
-                        memory-controller@90000000 {
-                                compatible = "sirf,prima2-memc";
-                                reg = <0x90000000 0x10000>;
-                                interrupts = <27>;
-                        };
-                };
-
-                disp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x90010000 0x90010000 0x30000>;
-
-                        display@90010000 {
-                                compatible = "sirf,prima2-lcd";
-                                reg = <0x90010000 0x20000>;
-                                interrupts = <30>;
-                        };
-
-                        vpp@90020000 {
-                                compatible = "sirf,prima2-vpp";
-                                reg = <0x90020000 0x10000>;
-                                interrupts = <31>;
-                        };
-                };
-
-                graphics-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0x98000000 0x98000000 0x8000000>;
-
-                        graphics@98000000 {
-                                compatible = "powervr,sgx531";
-                                reg = <0x98000000 0x8000000>;
-                                interrupts = <6>;
-                        };
-                };
-
-                multimedia-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa0000000 0xa0000000 0x8000000>;
-
-                        multimedia@a0000000 {
-                                compatible = "sirf,prima2-video-codec";
-                                reg = <0xa0000000 0x8000000>;
-                                interrupts = <5>;
-                        };
-                };
-
-                dsp-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xa8000000 0xa8000000 0x2000000>;
-
-                        dspif@a8000000 {
-                                compatible = "sirf,prima2-dspif";
-                                reg = <0xa8000000 0x10000>;
-                                interrupts = <9>;
-                        };
-
-                        gps@a8010000 {
-                                compatible = "sirf,prima2-gps";
-                                reg = <0xa8010000 0x10000>;
-                                interrupts = <7>;
-                        };
-
-                        dsp@a9000000 {
-                                compatible = "sirf,prima2-dsp";
-                                reg = <0xa9000000 0x1000000>;
-                                interrupts = <8>;
-                        };
-                };
-
-                peri-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb0000000 0xb0000000 0x180000>;
-
-                        timer@b0020000 {
-                                compatible = "sirf,prima2-tick";
-                                reg = <0xb0020000 0x1000>;
-                                interrupts = <0>;
-                        };
-
-                        nand@b0030000 {
-                                compatible = "sirf,prima2-nand";
-                                reg = <0xb0030000 0x10000>;
-                                interrupts = <41>;
-                        };
-
-                        audio@b0040000 {
-                                compatible = "sirf,prima2-audio";
-                                reg = <0xb0040000 0x10000>;
-                                interrupts = <35>;
-                        };
-
-                        uart0: uart@b0050000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0050000 0x10000>;
-                                interrupts = <17>;
-                        };
-
-                        uart1: uart@b0060000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0060000 0x10000>;
-                                interrupts = <18>;
-                        };
-
-                        uart2: uart@b0070000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-uart";
-                                reg = <0xb0070000 0x10000>;
-                                interrupts = <19>;
-                        };
-
-                        usp0: usp@b0080000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0080000 0x10000>;
-                                interrupts = <20>;
-                        };
-
-                        usp1: usp@b0090000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb0090000 0x10000>;
-                                interrupts = <21>;
-                        };
-
-                        usp2: usp@b00a0000 {
-                                cell-index = <2>;
-                                compatible = "sirf,prima2-usp";
-                                reg = <0xb00a0000 0x10000>;
-                                interrupts = <22>;
-                        };
-
-                        dmac0: dma-controller@b00b0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb00b0000 0x10000>;
-                                interrupts = <12>;
-                        };
-
-                        dmac1: dma-controller@b0160000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-dmac";
-                                reg = <0xb0160000 0x10000>;
-                                interrupts = <13>;
-                        };
-
-                        vip@b00C0000 {
-                                compatible = "sirf,prima2-vip";
-                                reg = <0xb00C0000 0x10000>;
-                        };
-
-                        spi0: spi@b00d0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb00d0000 0x10000>;
-                                interrupts = <15>;
-                        };
-
-                        spi1: spi@b0170000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-spi";
-                                reg = <0xb0170000 0x10000>;
-                                interrupts = <16>;
-                        };
-
-                        i2c0: i2c@b00e0000 {
-                                cell-index = <0>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00e0000 0x10000>;
-                                interrupts = <24>;
-                        };
-
-                        i2c1: i2c@b00f0000 {
-                                cell-index = <1>;
-                                compatible = "sirf,prima2-i2c";
-                                reg = <0xb00f0000 0x10000>;
-                                interrupts = <25>;
-                        };
-
-                        tsc@b0110000 {
-                                compatible = "sirf,prima2-tsc";
-                                reg = <0xb0110000 0x10000>;
-                                interrupts = <33>;
-                        };
-
-                        gpio: gpio-controller@b0120000 {
-                                #gpio-cells = <2>;
-                                #interrupt-cells = <2>;
-                                compatible = "sirf,prima2-gpio-pinmux";
-                                reg = <0xb0120000 0x10000>;
-                                gpio-controller;
-                                interrupt-controller;
-                        };
-
-                        pwm@b0130000 {
-                                compatible = "sirf,prima2-pwm";
-                                reg = <0xb0130000 0x10000>;
-                        };
-
-                        efusesys@b0140000 {
-                                compatible = "sirf,prima2-efuse";
-                                reg = <0xb0140000 0x10000>;
-                        };
-
-                        pulsec@b0150000 {
-                                compatible = "sirf,prima2-pulsec";
-                                reg = <0xb0150000 0x10000>;
-                                interrupts = <48>;
-                        };
-
-                        pci-iobg {
-                                compatible = "sirf,prima2-pciiobg", "simple-bus";
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0x56000000 0x56000000 0x1b00000>;
-
-                                sd0: sdhci@56000000 {
-                                        cell-index = <0>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56000000 0x100000>;
-                                        interrupts = <38>;
-                                };
-
-                                sd1: sdhci@56100000 {
-                                        cell-index = <1>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56100000 0x100000>;
-                                        interrupts = <38>;
-                                };
-
-                                sd2: sdhci@56200000 {
-                                        cell-index = <2>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56200000 0x100000>;
-                                        interrupts = <23>;
-                                };
-
-                                sd3: sdhci@56300000 {
-                                        cell-index = <3>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56300000 0x100000>;
-                                        interrupts = <23>;
-                                };
-
-                                sd4: sdhci@56400000 {
-                                        cell-index = <4>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56400000 0x100000>;
-                                        interrupts = <39>;
-                                };
-
-                                sd5: sdhci@56500000 {
-                                        cell-index = <5>;
-                                        compatible = "sirf,prima2-sdhc";
-                                        reg = <0x56500000 0x100000>;
-                                        interrupts = <39>;
-                                };
-
-                                pci-copy@57900000 {
-                                        compatible = "sirf,prima2-pcicp";
-                                        reg = <0x57900000 0x100000>;
-                                        interrupts = <40>;
-                                };
-
-                                rom-interface@57a00000 {
-                                        compatible = "sirf,prima2-romif";
-                                        reg = <0x57a00000 0x100000>;
-                                };
-                        };
-                };
-
-                rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x80030000 0x10000>;
-
-                        gpsrtc@1000 {
-                                compatible = "sirf,prima2-gpsrtc";
-                                reg = <0x1000 0x1000>;
-                                interrupts = <55 56 57>;
-                        };
-
-                        sysrtc@2000 {
-                                compatible = "sirf,prima2-sysrtc";
-                                reg = <0x2000 0x1000>;
-                                interrupts = <52 53 54>;
-                        };
-
-                        pwrc@3000 {
-                                compatible = "sirf,prima2-pwrc";
-                                reg = <0x3000 0x1000>;
-                                interrupts = <32>;
-                        };
-                };
-
-                uus-iobg {
-                        compatible = "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0xb8000000 0xb8000000 0x40000>;
-
-                        usb0: usb@b00e0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8000000 0x10000>;
-                                interrupts = <10>;
-                        };
-
-                        usb1: usb@b00f0000 {
-                                compatible = "chipidea,ci13611a-prima2";
-                                reg = <0xb8010000 0x10000>;
-                                interrupts = <11>;
-                        };
-
-                        sata@b00f0000 {
-                                compatible = "synopsys,dwc-ahsata";
-                                reg = <0xb8020000 0x10000>;
-                                interrupts = <37>;
-                        };
-
-                        security@b00f0000 {
-                                compatible = "sirf,prima2-security";
-                                reg = <0xb8030000 0x10000>;
-                                interrupts = <42>;
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/prima2-evb.dts b/arch/arm/boot/dts/prima2-evb.dts
new file mode 100644
index 000000000000..57286b4e7b87
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-evb.dts
@@ -0,0 +1,37 @@
+/*
+ * DTS file for CSR SiRFprimaII Evaluation Board
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "prima2.dtsi"
+
+/ {
+        model = "CSR SiRFprimaII Evaluation Board";
+        compatible = "sirf,prima2", "sirf,prima2-cb";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        axi {
+                peri-iobg {
+                        uart@b0060000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&uart1_pins_a>;
+                        };
+                        spi@b00d0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi0_pins_a>;
+                        };
+                        spi@b0170000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&spi1_pins_a>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
new file mode 100644
index 000000000000..055fca542120
--- /dev/null
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -0,0 +1,640 @@
+/*
+ * DTS file for CSR SiRFprimaII SoC
+ *
+ * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "sirf,prima2";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        interrupt-parent = <&intc>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        reg = <0x0>;
+                        d-cache-line-size = <32>;
+                        i-cache-line-size = <32>;
+                        d-cache-size = <32768>;
+                        i-cache-size = <32768>;
+                        /* from bootloader */
+                        timebase-frequency = <0>;
+                        bus-frequency = <0>;
+                        clock-frequency = <0>;
+                };
+        };
+
+        axi {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x40000000 0x40000000 0x80000000>;
+
+                l2-cache-controller@80040000 {
+                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
+                        reg = <0x80040000 0x1000>;
+                        interrupts = <59>;
+                        arm,tag-latency = <1 1 1>;
+                        arm,data-latency = <1 1 1>;
+                        arm,filter-ranges = <0 0x40000000>;
+                };
+
+                intc: interrupt-controller@80020000 {
+                        #interrupt-cells = <1>;
+                        interrupt-controller;
+                        compatible = "sirf,prima2-intc";
+                        reg = <0x80020000 0x1000>;
+                };
+
+                sys-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x88000000 0x88000000 0x40000>;
+
+                        clock-controller@88000000 {
+                                compatible = "sirf,prima2-clkc";
+                                reg = <0x88000000 0x1000>;
+                                interrupts = <3>;
+                        };
+
+                        reset-controller@88010000 {
+                                compatible = "sirf,prima2-rstc";
+                                reg = <0x88010000 0x1000>;
+                        };
+
+                        rsc-controller@88020000 {
+                                compatible = "sirf,prima2-rsc";
+                                reg = <0x88020000 0x1000>;
+                        };
+                };
+
+                mem-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90000000 0x90000000 0x10000>;
+
+                        memory-controller@90000000 {
+                                compatible = "sirf,prima2-memc";
+                                reg = <0x90000000 0x10000>;
+                                interrupts = <27>;
+                        };
+                };
+
+                disp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x90010000 0x90010000 0x30000>;
+
+                        display@90010000 {
+                                compatible = "sirf,prima2-lcd";
+                                reg = <0x90010000 0x20000>;
+                                interrupts = <30>;
+                        };
+
+                        vpp@90020000 {
+                                compatible = "sirf,prima2-vpp";
+                                reg = <0x90020000 0x10000>;
+                                interrupts = <31>;
+                        };
+                };
+
+                graphics-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0x98000000 0x98000000 0x8000000>;
+
+                        graphics@98000000 {
+                                compatible = "powervr,sgx531";
+                                reg = <0x98000000 0x8000000>;
+                                interrupts = <6>;
+                        };
+                };
+
+                multimedia-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa0000000 0xa0000000 0x8000000>;
+
+                        multimedia@a0000000 {
+                                compatible = "sirf,prima2-video-codec";
+                                reg = <0xa0000000 0x8000000>;
+                                interrupts = <5>;
+                        };
+                };
+
+                dsp-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+                        dspif@a8000000 {
+                                compatible = "sirf,prima2-dspif";
+                                reg = <0xa8000000 0x10000>;
+                                interrupts = <9>;
+                        };
+
+                        gps@a8010000 {
+                                compatible = "sirf,prima2-gps";
+                                reg = <0xa8010000 0x10000>;
+                                interrupts = <7>;
+                        };
+
+                        dsp@a9000000 {
+                                compatible = "sirf,prima2-dsp";
+                                reg = <0xa9000000 0x1000000>;
+                                interrupts = <8>;
+                        };
+                };
+
+                peri-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb0000000 0xb0000000 0x180000>;
+
+                        timer@b0020000 {
+                                compatible = "sirf,prima2-tick";
+                                reg = <0xb0020000 0x1000>;
+                                interrupts = <0>;
+                        };
+
+                        nand@b0030000 {
+                                compatible = "sirf,prima2-nand";
+                                reg = <0xb0030000 0x10000>;
+                                interrupts = <41>;
+                        };
+
+                        audio@b0040000 {
+                                compatible = "sirf,prima2-audio";
+                                reg = <0xb0040000 0x10000>;
+                                interrupts = <35>;
+                        };
+
+                        uart0: uart@b0050000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0050000 0x10000>;
+                                interrupts = <17>;
+                        };
+
+                        uart1: uart@b0060000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0060000 0x10000>;
+                                interrupts = <18>;
+                        };
+
+                        uart2: uart@b0070000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-uart";
+                                reg = <0xb0070000 0x10000>;
+                                interrupts = <19>;
+                        };
+
+                        usp0: usp@b0080000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0080000 0x10000>;
+                                interrupts = <20>;
+                        };
+
+                        usp1: usp@b0090000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb0090000 0x10000>;
+                                interrupts = <21>;
+                        };
+
+                        usp2: usp@b00a0000 {
+                                cell-index = <2>;
+                                compatible = "sirf,prima2-usp";
+                                reg = <0xb00a0000 0x10000>;
+                                interrupts = <22>;
+                        };
+
+                        dmac0: dma-controller@b00b0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb00b0000 0x10000>;
+                                interrupts = <12>;
+                        };
+
+                        dmac1: dma-controller@b0160000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-dmac";
+                                reg = <0xb0160000 0x10000>;
+                                interrupts = <13>;
+                        };
+
+                        vip@b00C0000 {
+                                compatible = "sirf,prima2-vip";
+                                reg = <0xb00C0000 0x10000>;
+                        };
+
+                        spi0: spi@b00d0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb00d0000 0x10000>;
+                                interrupts = <15>;
+                        };
+
+                        spi1: spi@b0170000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-spi";
+                                reg = <0xb0170000 0x10000>;
+                                interrupts = <16>;
+                        };
+
+                        i2c0: i2c@b00e0000 {
+                                cell-index = <0>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00e0000 0x10000>;
+                                interrupts = <24>;
+                        };
+
+                        i2c1: i2c@b00f0000 {
+                                cell-index = <1>;
+                                compatible = "sirf,prima2-i2c";
+                                reg = <0xb00f0000 0x10000>;
+                                interrupts = <25>;
+                        };
+
+                        tsc@b0110000 {
+                                compatible = "sirf,prima2-tsc";
+                                reg = <0xb0110000 0x10000>;
+                                interrupts = <33>;
+                        };
+
+                        gpio: pinctrl@b0120000 {
+                                #gpio-cells = <2>;
+                                #interrupt-cells = <2>;
+                                compatible = "sirf,prima2-pinctrl";
+                                reg = <0xb0120000 0x10000>;
+                                interrupts = <43 44 45 46 47>;
+                                gpio-controller;
+                                interrupt-controller;
+
+                                lcd_16pins_a: lcd0@0 {
+                                        lcd {
+                                                sirf,pins = "lcd_16bitsgrp";
+                                                sirf,function = "lcd_16bits";
+                                        };
+                                };
+                                lcd_18pins_a: lcd0@1 {
+                                        lcd {
+                                                sirf,pins = "lcd_18bitsgrp";
+                                                sirf,function = "lcd_18bits";
+                                        };
+                                };
+                                lcd_24pins_a: lcd0@2 {
+                                        lcd {
+                                                sirf,pins = "lcd_24bitsgrp";
+                                                sirf,function = "lcd_24bits";
+                                        };
+                                };
+                                lcdrom_pins_a: lcdrom0@0 {
+                                        lcd {
+                                                sirf,pins = "lcdromgrp";
+                                                sirf,function = "lcdrom";
+                                        };
+                                };
+                                uart0_pins_a: uart0@0 {
+                                        uart {
+                                                sirf,pins = "uart0grp";
+                                                sirf,function = "uart0";
+                                        };
+                                };
+                                uart1_pins_a: uart1@0 {
+                                        uart {
+                                                sirf,pins = "uart1grp";
+                                                sirf,function = "uart1";
+                                        };
+                                };
+                                uart2_pins_a: uart2@0 {
+                                        uart {
+                                                sirf,pins = "uart2grp";
+                                                sirf,function = "uart2";
+                                        };
+                                };
+                                uart2_noflow_pins_a: uart2@1 {
+                                        uart {
+                                                sirf,pins = "uart2_nostreamctrlgrp";
+                                                sirf,function = "uart2_nostreamctrl";
+                                        };
+                                };
+                                spi0_pins_a: spi0@0 {
+                                        spi {
+                                                sirf,pins = "spi0grp";
+                                                sirf,function = "spi0";
+                                        };
+                                };
+                                spi1_pins_a: spi1@0 {
+                                        spi {
+                                                sirf,pins = "spi1grp";
+                                                sirf,function = "spi1";
+                                        };
+                                };
+                                i2c0_pins_a: i2c0@0 {
+                                        i2c {
+                                                sirf,pins = "i2c0grp";
+                                                sirf,function = "i2c0";
+                                        };
+                                };
+                                i2c1_pins_a: i2c1@0 {
+                                        i2c {
+                                                sirf,pins = "i2c1grp";
+                                                sirf,function = "i2c1";
+                                        };
+                                };
+                                pwm0_pins_a: pwm0@0 {
+                                        pwm {
+                                                sirf,pins = "pwm0grp";
+                                                sirf,function = "pwm0";
+                                        };
+                                };
+                                pwm1_pins_a: pwm1@0 {
+                                        pwm {
+                                                sirf,pins = "pwm1grp";
+                                                sirf,function = "pwm1";
+                                        };
+                                };
+                                pwm2_pins_a: pwm2@0 {
+                                        pwm {
+                                                sirf,pins = "pwm2grp";
+                                                sirf,function = "pwm2";
+                                        };
+                                };
+                                pwm3_pins_a: pwm3@0 {
+                                        pwm {
+                                                sirf,pins = "pwm3grp";
+                                                sirf,function = "pwm3";
+                                        };
+                                };
+                                gps_pins_a: gps@0 {
+                                        gps {
+                                                sirf,pins = "gpsgrp";
+                                                sirf,function = "gps";
+                                        };
+                                };
+                                vip_pins_a: vip@0 {
+                                        vip {
+                                                sirf,pins = "vipgrp";
+                                                sirf,function = "vip";
+                                        };
+                                };
+                                sdmmc0_pins_a: sdmmc0@0 {
+                                        sdmmc0 {
+                                                sirf,pins = "sdmmc0grp";
+                                                sirf,function = "sdmmc0";
+                                        };
+                                };
+                                sdmmc1_pins_a: sdmmc1@0 {
+                                        sdmmc1 {
+                                                sirf,pins = "sdmmc1grp";
+                                                sirf,function = "sdmmc1";
+                                        };
+                                };
+                                sdmmc2_pins_a: sdmmc2@0 {
+                                        sdmmc2 {
+                                                sirf,pins = "sdmmc2grp";
+                                                sirf,function = "sdmmc2";
+                                        };
+                                };
+                                sdmmc3_pins_a: sdmmc3@0 {
+                                        sdmmc3 {
+                                                sirf,pins = "sdmmc3grp";
+                                                sirf,function = "sdmmc3";
+                                        };
+                                };
+                                sdmmc4_pins_a: sdmmc4@0 {
+                                        sdmmc4 {
+                                                sirf,pins = "sdmmc4grp";
+                                                sirf,function = "sdmmc4";
+                                        };
+                                };
+                                sdmmc5_pins_a: sdmmc5@0 {
+                                        sdmmc5 {
+                                                sirf,pins = "sdmmc5grp";
+                                                sirf,function = "sdmmc5";
+                                        };
+                                };
+                                i2s_pins_a: i2s@0 {
+                                        i2s {
+                                                sirf,pins = "i2sgrp";
+                                                sirf,function = "i2s";
+                                        };
+                                };
+                                ac97_pins_a: ac97@0 {
+                                        ac97 {
+                                                sirf,pins = "ac97grp";
+                                                sirf,function = "ac97";
+                                        };
+                                };
+                                nand_pins_a: nand@0 {
+                                        nand {
+                                                sirf,pins = "nandgrp";
+                                                sirf,function = "nand";
+                                        };
+                                };
+                                usp0_pins_a: usp0@0 {
+                                        usp0 {
+                                                sirf,pins = "usp0grp";
+                                                sirf,function = "usp0";
+                                        };
+                                };
+                                usp1_pins_a: usp1@0 {
+                                        usp1 {
+                                                sirf,pins = "usp1grp";
+                                                sirf,function = "usp1";
+                                        };
+                                };
+                                usp2_pins_a: usp2@0 {
+                                        usp2 {
+                                                sirf,pins = "usp2grp";
+                                                sirf,function = "usp2";
+                                        };
+                                };
+                                usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
+                                        usb0_utmi_drvbus {
+                                                sirf,pins = "usb0_utmi_drvbusgrp";
+                                                sirf,function = "usb0_utmi_drvbus";
+                                        };
+                                };
+                                usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
+                                        usb1_utmi_drvbus {
+                                                sirf,pins = "usb1_utmi_drvbusgrp";
+                                                sirf,function = "usb1_utmi_drvbus";
+                                        };
+                                };
+                                warm_rst_pins_a: warm_rst@0 {
+                                        warm_rst {
+                                                sirf,pins = "warm_rstgrp";
+                                                sirf,function = "warm_rst";
+                                        };
+                                };
+                                pulse_count_pins_a: pulse_count@0 {
+                                        pulse_count {
+                                                sirf,pins = "pulse_countgrp";
+                                                sirf,function = "pulse_count";
+                                        };
+                                };
+                                cko0_rst_pins_a: cko0_rst@0 {
+                                        cko0_rst {
+                                                sirf,pins = "cko0_rstgrp";
+                                                sirf,function = "cko0_rst";
+                                        };
+                                };
+                                cko1_rst_pins_a: cko1_rst@0 {
+                                        cko1_rst {
+                                                sirf,pins = "cko1_rstgrp";
+                                                sirf,function = "cko1_rst";
+                                        };
+                                };
+                        };
+
+                        pwm@b0130000 {
+                                compatible = "sirf,prima2-pwm";
+                                reg = <0xb0130000 0x10000>;
+                        };
+
+                        efusesys@b0140000 {
+                                compatible = "sirf,prima2-efuse";
+                                reg = <0xb0140000 0x10000>;
+                        };
+
+                        pulsec@b0150000 {
+                                compatible = "sirf,prima2-pulsec";
+                                reg = <0xb0150000 0x10000>;
+                                interrupts = <48>;
+                        };
+
+                        pci-iobg {
+                                compatible = "sirf,prima2-pciiobg", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0x56000000 0x56000000 0x1b00000>;
+
+                                sd0: sdhci@56000000 {
+                                        cell-index = <0>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56000000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd1: sdhci@56100000 {
+                                        cell-index = <1>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56100000 0x100000>;
+                                        interrupts = <38>;
+                                };
+
+                                sd2: sdhci@56200000 {
+                                        cell-index = <2>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56200000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd3: sdhci@56300000 {
+                                        cell-index = <3>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56300000 0x100000>;
+                                        interrupts = <23>;
+                                };
+
+                                sd4: sdhci@56400000 {
+                                        cell-index = <4>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56400000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                sd5: sdhci@56500000 {
+                                        cell-index = <5>;
+                                        compatible = "sirf,prima2-sdhc";
+                                        reg = <0x56500000 0x100000>;
+                                        interrupts = <39>;
+                                };
+
+                                pci-copy@57900000 {
+                                        compatible = "sirf,prima2-pcicp";
+                                        reg = <0x57900000 0x100000>;
+                                        interrupts = <40>;
+                                };
+
+                                rom-interface@57a00000 {
+                                        compatible = "sirf,prima2-romif";
+                                        reg = <0x57a00000 0x100000>;
+                                };
+                        };
+                };
+
+                rtc-iobg {
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x80030000 0x10000>;
+
+                        gpsrtc@1000 {
+                                compatible = "sirf,prima2-gpsrtc";
+                                reg = <0x1000 0x1000>;
+                                interrupts = <55 56 57>;
+                        };
+
+                        sysrtc@2000 {
+                                compatible = "sirf,prima2-sysrtc";
+                                reg = <0x2000 0x1000>;
+                                interrupts = <52 53 54>;
+                        };
+
+                        pwrc@3000 {
+                                compatible = "sirf,prima2-pwrc";
+                                reg = <0x3000 0x1000>;
+                                interrupts = <32>;
+                        };
+                };
+
+                uus-iobg {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0xb8000000 0xb8000000 0x40000>;
+
+                        usb0: usb@b00e0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8000000 0x10000>;
+                                interrupts = <10>;
+                        };
+
+                        usb1: usb@b00f0000 {
+                                compatible = "chipidea,ci13611a-prima2";
+                                reg = <0xb8010000 0x10000>;
+                                interrupts = <11>;
+                        };
+
+                        sata@b00f0000 {
+                                compatible = "synopsys,dwc-ahsata";
+                                reg = <0xb8020000 0x10000>;
+                                interrupts = <37>;
+                        };
+
+                        security@b00f0000 {
+                                compatible = "sirf,prima2-security";
+                                reg = <0xb8030000 0x10000>;
+                                interrupts = <42>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
new file mode 100644
index 000000000000..d7c5d721a5c7
--- /dev/null
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -0,0 +1,14 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+        model = "Marvell PXA27x familiy SoC";
+        compatible = "marvell,pxa27x";
+
+        pxabus {
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <34>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
new file mode 100644
index 000000000000..f18aad35e8b3
--- /dev/null
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -0,0 +1,132 @@
+/*
+ * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Marvell PXA2xx family SoC";
+        compatible = "marvell,pxa2xx";
+        interrupt-parent = <&pxairq>;
+
+        aliases {
+                serial0 = &ffuart;
+                serial1 = &btuart;
+                serial2 = &stuart;
+                serial3 = &hwuart;
+                i2c0 = &pwri2c;
+                i2c1 = &pxai2c1;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,xscale";
+                };
+        };
+
+        pxabus {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                pxairq: interrupt-controller@40d00000 {
+                        #interrupt-cells = <1>;
+                        compatible = "marvell,pxa-intc";
+                        interrupt-controller;
+                        interrupt-parent;
+                        marvell,intc-nr-irqs = <32>;
+                        reg = <0x40d00000 0xd0>;
+                };
+
+                gpio: gpio@40e00000 {
+                        compatible = "mrvl,pxa-gpio";
+                        #address-cells = <0x1>;
+                        #size-cells = <0x1>;
+                        reg = <0x40e00000 0x10000>;
+                        gpio-controller;
+                        #gpio-cells = <0x2>;
+                        interrupts = <10>;
+                        interrupt-names = "gpio_mux";
+                        interrupt-controller;
+                        #interrupt-cells = <0x2>;
+                        ranges;
+
+                        gcb0: gpio@40e00000 {
+                                reg = <0x40e00000 0x4>;
+                        };
+
+                        gcb1: gpio@40e00004 {
+                                reg = <0x40e00004 0x4>;
+                        };
+
+                        gcb2: gpio@40e00008 {
+                                reg = <0x40e00008 0x4>;
+                        };
+                        gcb3: gpio@40e0000c {
+                                reg = <0x40e0000c 0x4>;
+                        };
+                };
+
+                ffuart: uart@40100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40100000 0x30>;
+                        interrupts = <22>;
+                        status = "disabled";
+                };
+
+                btuart: uart@40200000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40200000 0x30>;
+                        interrupts = <21>;
+                        status = "disabled";
+                };
+
+                stuart: uart@40700000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x40700000 0x30>;
+                        interrupts = <20>;
+                        status = "disabled";
+                };
+
+                hwuart: uart@41100000 {
+                        compatible = "mrvl,pxa-uart";
+                        reg = <0x41100000 0x30>;
+                        interrupts = <7>;
+                        status = "disabled";
+                };
+
+                pxai2c1: i2c@40301680 {
+                        compatible = "mrvl,pxa-i2c";
+                        reg = <0x40301680 0x30>;
+                        interrupts = <18>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                usb0: ohci@4c000000 {
+                        compatible = "mrvl,pxa-ohci";
+                        reg = <0x4c000000 0x10000>;
+                        interrupts = <3>;
+                        status = "disabled";
+                };
+
+                mmc0: mmc@41100000 {
+                        compatible = "mrvl,pxa-mmc";
+                        reg = <0x41100000 0x1000>;
+                        interrupts = <23>;
+                        status = "disabled";
+                };
+
+                rtc@40900000 {
+                        compatible = "marvell,pxa-rtc";
+                        reg = <0x40900000 0x3c>;
+                        interrupts = <30 31>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
new file mode 100644
index 000000000000..f9d92da86783
--- /dev/null
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -0,0 +1,32 @@
+/* The pxa3xx skeleton simply augments the 2xx version */
+/include/ "pxa2xx.dtsi"
+
+/ {
+        model = "Marvell PXA3xx familiy SoC";
+        compatible = "marvell,pxa3xx";
+
+        pxabus {
+                pwri2c: i2c@40f500c0 {
+                        compatible = "mrvl,pwri2c";
+                        reg = <0x40f500c0 0x30>;
+                        interrupts = <6>;
+                        #address-cells = <0x1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                nand0: nand@43100000 {
+                        compatible = "marvell,pxa3xx-nand";
+                        reg = <0x43100000 90>;
+                        interrupts = <45>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;      
+                        status = "disabled";
+                };
+
+                pxairq: interrupt-controller@40d00000 {
+                        marvell,intc-priority;
+                        marvell,intc-nr-irqs = <56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi
index aebf32de73b4..a3be44d86bcd 100644
--- a/arch/arm/boot/dts/pxa910.dtsi
+++ b/arch/arm/boot/dts/pxa910.dtsi
@@ -25,6 +25,11 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                L2: l2-cache {
+                        compatible = "marvell,tauros2-cache";
+                        marvell,tauros2-cache-features = <0x3>;
+                };
+
                 axi@d4200000 {  /* AXI */
                         compatible = "mrvl,axi-bus", "simple-bus";
                         #address-cells = <1>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index 7e334d4cae21..702c0baa6004 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "db8500.dtsi"
+/include/ "dbx5x0.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -83,6 +83,22 @@
         };
 
         soc-u9500 {
+
+                sound {
+                        compatible = "stericsson,snd-soc-mop500";
+
+                        stericsson,cpu-dai = <&msp1 &msp3>;
+                        stericsson,audio-codec = <&codec>;
+                };
+
+                msp1: msp@80124000 {
+                        status = "okay";
+                };
+
+                msp3: msp@80125000 {
+                        status = "okay";
+                };
+
                 external-bus@50000000 {
                         status = "okay";
 
@@ -111,7 +127,6 @@
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
 
-                        #gpio-cells = <1>;
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
 
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
new file mode 100644
index 000000000000..a2d6d6541f83
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Medcom-Wide board";
+        compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 5000000>;
+
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-wm8903-medcom-wide",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Medcom-Wide";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 684a9e1ff7e9..ddf287f52d49 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -272,12 +272,170 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&p5valw_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "+1.2vs_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "+1.0vs_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "+3.7vs_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "+1.1vs_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "+1.2vs_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "+3.3vs_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "+2.85vs_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        /*
+                                         * Research indicates this should be
+                                         * 1.8v; other boards that use this
+                                         * rail for the same purpose need it
+                                         * set to 1.8v. The schematic signal
+                                         * name is incorrect; perhaps copied
+                                         * from an incorrect NVIDIA reference.
+                                         */
+                                        regulator-name = "+2.85vs_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "+3.3vs_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "+3.3vs_rtc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
                 adt7461@4c {
                         compatible = "adi,adt7461";
                         reg = <0x4c>;
                 };
         };
 
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
         usb@c5000000 {
                 status = "okay";
         };
@@ -325,6 +483,21 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                p5valw_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+5valw";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-alc5632-paz00",
                         "nvidia,tegra-audio-alc5632";
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
new file mode 100644
index 000000000000..331a3ef24d59
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -0,0 +1,50 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Plutux board";
+        compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-plutux",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design Plutux";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 85e621ab2968..e60dc7124e92 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -374,6 +374,154 @@
                 status = "okay";
                 clock-frequency = <400000>;
 
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1125000>;
+                                        regulator-max-microvolt = <1125000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+
                 temperature-sensor@4c {
                         compatible = "nct1008";
                         reg = <0x4c>;
@@ -387,6 +535,10 @@
                 };
         };
 
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
         memory-controller@0x7000f400 {
                 emc-table@190000 {
                         reg = <190000>;
@@ -473,6 +625,40 @@
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8903-seaboard",
                              "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
new file mode 100644
index 000000000000..f18cec9f6a77
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -0,0 +1,449 @@
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "Avionic Design Tamonten SOM";
+        compatible = "ad,tamonten", "nvidia,tegra20";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata";
+                                nvidia,function = "ide";
+                        };
+                        atb {
+                                nvidia,pins = "atb", "gma", "gme";
+                                nvidia,function = "sdio4";
+                        };
+                        atc {
+                                nvidia,pins = "atc";
+                                nvidia,function = "nand";
+                        };
+                        atd {
+                                nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "gmi";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "pllp_out4";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtd";
+                                nvidia,function = "sdio2";
+                        };
+                        dtb {
+                                nvidia,pins = "dtb", "dtc", "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gmc {
+                                nvidia,pins = "gmc";
+                                nvidia,function = "uartd";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv", "slxa", "slxk";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uarta";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
+                                        "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
+                                        "ld3", "ld4", "ld5", "ld6", "ld7",
+                                        "ld8", "ld9", "ld10", "ld11", "ld12",
+                                        "ld13", "ld14", "ld15", "ld16", "ld17",
+                                        "ldc", "ldi", "lhp0", "lhp1", "lhp2",
+                                        "lhs", "lm0", "lm1", "lpp", "lpw0",
+                                        "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
+                                        "lsda", "lsdi", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd";
+                                nvidia,function = "pwm";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        slxc {
+                                nvidia,pins = "slxc", "slxd";
+                                nvidia,function = "spdif";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spif";
+                                nvidia,function = "spi1";
+                        };
+                        spig {
+                                nvidia,pins = "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab", "uda";
+                                nvidia,function = "ulpi";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "atd", "ate",
+                                        "cdev1", "cdev2", "dap1", "dtb", "gma",
+                                        "gmb", "gmc", "gmd", "gme", "gpu7",
+                                        "gpv", "i2cp", "pta", "rm", "slxa",
+                                        "slxk", "spia", "spib", "uac";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
+                                        "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_csus {
+                                nvidia,pins = "csus", "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp", "dap2", "dap3", "dap4",
+                                        "dtc", "dte", "dtf", "gpu", "sdio1",
+                                        "slxc", "slxd", "spdi", "spdo", "spig",
+                                        "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ddc {
+                                nvidia,pins = "ddc", "dta", "dtd", "kbca",
+                                        "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
+                                        "sdc";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_hdint {
+                                nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
+                                        "lpw1", "lsc1", "lsck", "lsda", "lsdi",
+                                        "lvp0", "owc", "sdb";
+                                nvidia,tristate = <1>;
+                        };
+                        conf_irrx {
+                                nvidia,pins = "irrx", "irtx", "sdd", "spic",
+                                        "spie", "spih", "uaa", "uab", "uad",
+                                        "uca", "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_lc {
+                                nvidia,pins = "lc", "ls";
+                                nvidia,pull = <2>;
+                        };
+                        conf_ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldi", "lhp0",
+                                        "lhp1", "lhp2", "lhs", "lm0", "lpp",
+                                        "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
+                                        "lvs", "pmc";
+                                nvidia,tristate = <0>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                };
+        };
+
+        i2s@70002800 {
+                status = "okay";
+        };
+
+        serial@70006300 {
+                clock-frequency = <216000000>;
+                status = "okay";
+        };
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+        };
+
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+                status = "okay";
+
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sys_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sys_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sys_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo0";
+                                        regulator-name = "vdd_ldo0,vddio_pex_clk";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
+                                        /*
+                                         * According to the Tegra 2 Automotive
+                                         * DataSheet, a typical value for this
+                                         * would be 2.8V, but the PMIC only
+                                         * supports 2.85V.
+                                         */
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
+        };
+
+        usb@c5008000 {
+                status = "okay";
+        };
+
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
+                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                bus-width = <4>;
+                status = "okay";
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
new file mode 100644
index 000000000000..9aff31b0fe4a
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -0,0 +1,53 @@
+/dts-v1/;
+
+/include/ "tegra20-tamonten.dtsi"
+
+/ {
+        model = "Avionic Design Tamonten Evaluation Carrier";
+        compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
+
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+                status = "okay";
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <187 0x04>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff
+                                    0xffffffff
+                                    0
+                                    0xffffffff
+                                    0xffffffff>;
+                };
+        };
+
+        sound {
+                compatible = "ad,tegra-audio-wm8903-tec",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "Avionic Design TEC";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index be90544e6b59..3e5952fcfbc5 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -289,6 +289,158 @@
         i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
+
+                pmic: tps6586x@34 {
+                        compatible = "ti,tps6586x";
+                        reg = <0x34>;
+                        interrupts = <0 86 0x4>;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        sys-supply = <&vdd_5v0_reg>;
+                        vin-sm0-supply = <&sys_reg>;
+                        vin-sm1-supply = <&sys_reg>;
+                        vin-sm2-supply = <&sys_reg>;
+                        vinldo01-supply = <&sm2_reg>;
+                        vinldo23-supply = <&sm2_reg>;
+                        vinldo4-supply = <&sm2_reg>;
+                        vinldo678-supply = <&sm2_reg>;
+                        vinldo9-supply = <&sm2_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                sys_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "sys";
+                                        regulator-name = "vdd_sys";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sm0";
+                                        regulator-name = "vdd_sm0,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sm1";
+                                        regulator-name = "vdd_sm1,vdd_cpu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                sm2_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sm2";
+                                        regulator-name = "vdd_sm2,vin_ldo*";
+                                        regulator-min-microvolt = <3700000>;
+                                        regulator-max-microvolt = <3700000>;
+                                        regulator-always-on;
+                                };
+
+                                /* LDO0 is not connected to anything */
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_ldo1,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_ldo2,vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "vdd_ldo3,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vdd_ldo5,vcore_mmc";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "vdd_ldo6,avdd_vdac";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo_rtc";
+                                        regulator-name = "vdd_rtc_out,vdd_cell";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
         };
 
         usb@c5000000 {
@@ -317,6 +469,60 @@
                 bus-width = <8>;
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_5v0_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_1v5";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        gpio = <&pmic 0 0>;
+                };
+
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v2";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&pmic 1 0>;
+                        enable-active-high;
+                };
+
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_pnl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        enable-active-high;
+                };
+
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        enable-active-high;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8903-ventana",
                              "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 6916310bf58f..c636d002d6d8 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -261,6 +261,286 @@
                         gpio-controller;
                         #gpio-cells = <2>;
                 };
+
+                max8907@3c {
+                        compatible = "maxim,max8907";
+                        reg = <0x3c>;
+                        interrupts = <0 86 0x4>;
+
+                        maxim,system-power-controller;
+
+                        mbatt-supply = <&usb0_vbus_reg>;
+                        in-v1-supply = <&mbatt_reg>;
+                        in-v2-supply = <&mbatt_reg>;
+                        in-v3-supply = <&mbatt_reg>;
+                        in1-supply = <&mbatt_reg>;
+                        in2-supply = <&nvvdd_sv3_reg>;
+                        in3-supply = <&mbatt_reg>;
+                        in4-supply = <&mbatt_reg>;
+                        in5-supply = <&mbatt_reg>;
+                        in6-supply = <&mbatt_reg>;
+                        in7-supply = <&mbatt_reg>;
+                        in8-supply = <&mbatt_reg>;
+                        in9-supply = <&mbatt_reg>;
+                        in10-supply = <&mbatt_reg>;
+                        in11-supply = <&mbatt_reg>;
+                        in12-supply = <&mbatt_reg>;
+                        in13-supply = <&mbatt_reg>;
+                        in14-supply = <&mbatt_reg>;
+                        in15-supply = <&mbatt_reg>;
+                        in16-supply = <&mbatt_reg>;
+                        in17-supply = <&nvvdd_sv3_reg>;
+                        in18-supply = <&nvvdd_sv3_reg>;
+                        in19-supply = <&mbatt_reg>;
+                        in20-supply = <&mbatt_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                mbatt_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "mbatt";
+                                        regulator-name = "vbat_pmu";
+                                        regulator-always-on;
+                                };
+
+                                regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "sd1";
+                                        regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "sd2";
+                                        regulator-name = "nvvdd_sv2,vdd_core";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                nvvdd_sv3_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "sd3";
+                                        regulator-name = "nvvdd_sv3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "nvvdd_ldo2,avdd_pll*";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@6 {
+                                        reg = <6>;
+                                        regulator-compatible = "ldo3";
+                                        regulator-name = "nvvdd_ldo3,vcom_1v8b";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "nvvdd_ldo4,avdd_usb*";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "nvvdd_ldo7,avddio_audio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+
+                                regulator@12 {
+                                        reg = <12>;
+                                        regulator-compatible = "ldo9";
+                                        regulator-name = "nvvdd_ldo9,avdd_cam*";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@13 {
+                                        reg = <13>;
+                                        regulator-compatible = "ldo10";
+                                        regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@14 {
+                                        reg = <14>;
+                                        regulator-compatible = "ldo11";
+                                        regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@15 {
+                                        reg = <15>;
+                                        regulator-compatible = "ldo12";
+                                        regulator-name = "nvvdd_ldo12,vddio_sdio";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@16 {
+                                        reg = <16>;
+                                        regulator-compatible = "ldo13";
+                                        regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@17 {
+                                        reg = <17>;
+                                        regulator-compatible = "ldo14";
+                                        regulator-name = "nvvdd_ldo14,avdd_vdac";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@18 {
+                                        reg = <18>;
+                                        regulator-compatible = "ldo15";
+                                        regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                regulator@19 {
+                                        reg = <19>;
+                                        regulator-compatible = "ldo16";
+                                        regulator-name = "nvvdd_ldo16,vdd_dbrtr";
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                };
+
+                                regulator@20 {
+                                        reg = <20>;
+                                        regulator-compatible = "ldo17";
+                                        regulator-name = "nvvdd_ldo17,vddio_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                regulator@21 {
+                                        reg = <21>;
+                                        regulator-compatible = "ldo18";
+                                        regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                regulator@22 {
+                                        reg = <22>;
+                                        regulator-compatible = "ldo19";
+                                        regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+
+                                regulator@23 {
+                                        reg = <23>;
+                                        regulator-compatible = "ldo20";
+                                        regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@24 {
+                                        reg = <24>;
+                                        regulator-compatible = "out5v";
+                                        regulator-name = "usb0_vbus_reg";
+                                };
+
+                                regulator@25 {
+                                        reg = <25>;
+                                        regulator-compatible = "out33v";
+                                        regulator-name = "pmu_out3v3";
+                                };
+
+                                regulator@26 {
+                                        reg = <26>;
+                                        regulator-compatible = "bbat";
+                                        regulator-name = "pmu_bbat";
+                                        regulator-min-microvolt = <2400000>;
+                                        regulator-max-microvolt = <2400000>;
+                                        regulator-always-on;
+                                };
+
+                                regulator@27 {
+                                        reg = <27>;
+                                        regulator-compatible = "sdby";
+                                        regulator-name = "vdd_aon";
+                                        regulator-always-on;
+                                };
+
+                                regulator@28 {
+                                        reg = <28>;
+                                        regulator-compatible = "vrtc";
+                                        regulator-name = "vrtc,pmu_vccadc";
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        pmc {
+                nvidia,invert-interrupt;
         };
 
         usb@c5000000 {
@@ -284,6 +564,21 @@
                 bus-width = <8>;
         };
 
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                usb0_vbus_reg: regulator {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+        };
+
         sound {
                 compatible = "nvidia,tegra-audio-wm8753-whistler",
                              "nvidia,tegra-audio-wm8753";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 405d1673904e..67a6cd910b96 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -123,7 +123,7 @@
                 status = "disabled";
         };
 
-        pwm {
+        pwm: pwm {
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
new file mode 100644
index 000000000000..dd4222f00eca
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -0,0 +1,87 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A02 version of board */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu A02 evaluation board";
+        compatible = "nvidia,cardhu-a02", "nvidia,cardhu", "nvidia,tegra30";
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        reg = <100>;
+                        regulator-name = "vdd_ddr";
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 2 0>;
+                };
+
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
new file mode 100644
index 000000000000..0828f097ca86
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+
+/include/ "tegra30-cardhu.dtsi"
+
+/* This dts file support the cardhu A04 and later versions of board */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu A04 (A05, A06, A07) evaluation board";
+        compatible = "nvidia,cardhu-a04", "nvidia,cardhu", "nvidia,tegra30";
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ddr_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "ddr";
+                        reg = <100>;
+                        regulator-min-microvolt = <1500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 7 0>;
+                };
+
+                sys_3v3_reg: regulator@101 {
+                        compatible = "regulator-fixed";
+                        reg = <101>;
+                        regulator-name = "sys_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&pmic 6 0>;
+                };
+
+                usb1_vbus_reg: regulator@102 {
+                        compatible = "regulator-fixed";
+                        reg = <102>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                usb3_vbus_reg: regulator@103 {
+                        compatible = "regulator-fixed";
+                        reg = <103>;
+                        regulator-name = "usb3_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+
+                vdd_5v0_reg: regulator@104 {
+                        compatible = "regulator-fixed";
+                        reg = <104>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&pmic 8 0>;
+                };
+
+                vdd_bl_reg: regulator@105 {
+                        compatible = "regulator-fixed";
+                        reg = <105>;
+                        regulator-name = "vdd_bl";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                };
+
+                vdd_bl2_reg: regulator@106 {
+                        compatible = "regulator-fixed";
+                        reg = <106>;
+                        regulator-name = "vdd_bl2";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
deleted file mode 100644
index c169bced131e..000000000000
--- a/arch/arm/boot/dts/tegra30-cardhu.dts
+++ /dev/null
@@ -1,171 +0,0 @@
-/dts-v1/;
-
-/include/ "tegra30.dtsi"
-
-/ {
-        model = "NVIDIA Tegra30 Cardhu evaluation board";
-        compatible = "nvidia,cardhu", "nvidia,tegra30";
-
-        memory {
-                reg = <0x80000000 0x40000000>;
-        };
-
-        pinmux {
-                pinctrl-names = "default";
-                pinctrl-0 = <&state_default>;
-
-                state_default: pinmux {
-                        sdmmc1_clk_pz0 {
-                                nvidia,pins = "sdmmc1_clk_pz0";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc1_cmd_pz1 {
-                                nvidia,pins =   "sdmmc1_cmd_pz1",
-                                                "sdmmc1_dat0_py7",
-                                                "sdmmc1_dat1_py6",
-                                                "sdmmc1_dat2_py5",
-                                                "sdmmc1_dat3_py4";
-                                nvidia,function = "sdmmc1";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_clk_pcc4 {
-                                nvidia,pins =   "sdmmc4_clk_pcc4",
-                                                "sdmmc4_rst_n_pcc3";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                        sdmmc4_dat0_paa0 {
-                                nvidia,pins =   "sdmmc4_dat0_paa0",
-                                                "sdmmc4_dat1_paa1",
-                                                "sdmmc4_dat2_paa2",
-                                                "sdmmc4_dat3_paa3",
-                                                "sdmmc4_dat4_paa4",
-                                                "sdmmc4_dat5_paa5",
-                                                "sdmmc4_dat6_paa6",
-                                                "sdmmc4_dat7_paa7";
-                                nvidia,function = "sdmmc4";
-                                nvidia,pull = <2>;
-                                nvidia,tristate = <0>;
-                        };
-                        dap2_fs_pa2 {
-                                nvidia,pins =   "dap2_fs_pa2",
-                                                "dap2_sclk_pa3",
-                                                "dap2_din_pa4",
-                                                "dap2_dout_pa5";
-                                nvidia,function = "i2s1";
-                                nvidia,pull = <0>;
-                                nvidia,tristate = <0>;
-                        };
-                };
-        };
-
-        serial@70006000 {
-                status = "okay";
-                clock-frequency = <408000000>;
-        };
-
-        i2c@7000c000 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000c400 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000c500 {
-                status = "okay";
-                clock-frequency = <100000>;
-
-                /* ALS and Proximity sensor */
-                isl29028@44 {
-                        compatible = "isil,isl29028";
-                        reg = <0x44>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
-                };
-        };
-
-        i2c@7000c700 {
-                status = "okay";
-                clock-frequency = <100000>;
-        };
-
-        i2c@7000d000 {
-                status = "okay";
-                clock-frequency = <100000>;
-
-                wm8903: wm8903@1a {
-                        compatible = "wlf,wm8903";
-                        reg = <0x1a>;
-                        interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
-
-                        gpio-controller;
-                        #gpio-cells = <2>;
-
-                        micdet-cfg = <0>;
-                        micdet-delay = <100>;
-                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
-                };
-
-                tps62361 {
-                        compatible = "ti,tps62361";
-                        reg = <0x60>;
-
-                        regulator-name = "tps62361-vout";
-                        regulator-min-microvolt = <500000>;
-                        regulator-max-microvolt = <1500000>;
-                        regulator-boot-on;
-                        regulator-always-on;
-                        ti,vsel0-state-high;
-                        ti,vsel1-state-high;
-                };
-        };
-
-        ahub {
-                i2s@70080400 {
-                        status = "okay";
-                };
-        };
-
-        sdhci@78000000 {
-                status = "okay";
-                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
-                bus-width = <4>;
-        };
-
-        sdhci@78000600 {
-                status = "okay";
-                bus-width = <8>;
-        };
-
-        sound {
-                compatible = "nvidia,tegra-audio-wm8903-cardhu",
-                             "nvidia,tegra-audio-wm8903";
-                nvidia,model = "NVIDIA Tegra Cardhu";
-
-                nvidia,audio-routing =
-                        "Headphone Jack", "HPOUTR",
-                        "Headphone Jack", "HPOUTL",
-                        "Int Spk", "ROP",
-                        "Int Spk", "RON",
-                        "Int Spk", "LOP",
-                        "Int Spk", "LON",
-                        "Mic Jack", "MICBIAS",
-                        "IN1L", "Mic Jack";
-
-                nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,audio-codec = <&wm8903>;
-
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-        };
-};
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
new file mode 100644
index 000000000000..d10c9c5a3606
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -0,0 +1,475 @@
+/include/ "tegra30.dtsi"
+
+/**
+ * This file contains common DT entry for all fab version of Cardhu.
+ * There is multiple fab version of Cardhu starting from A01 to A07.
+ * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
+ * A02 will have different sets of GPIOs for fixed regulator compare to
+ * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
+ * compatible with fab version A04. Based on Cardhu fab version, the
+ * related dts file need to be chosen like for Cardhu fab version A02,
+ * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
+ * tegra30-cardhu-a04.dts.
+ * The identification of board is done in two ways, by looking the sticker
+ * on PCB and by reading board id eeprom.
+ * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
+ * number is the fab version like here it is 002 and hence fab version A02.
+ * The (downstream internal) U-Boot of Cardhu display the board-id as
+ * follows:
+ * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
+ * In this Fab version is 02 i.e. A02.
+ * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
+ * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
+ * wide.
+ */
+
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins =   "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins =   "dap2_fs_pa2",
+                                                "dap2_sclk_pa3",
+                                                "dap2_din_pa4",
+                                                "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                };
+        };
+
+        serial@70006000 {
+                status = "okay";
+                clock-frequency = <408000000>;
+        };
+
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                /* ALS and Proximity sensor */
+                isl29028@44 {
+                        compatible = "isil,isl29028";
+                        reg = <0x44>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <88 0x04>; /*gpio PL0 */
+                };
+        };
+
+        i2c@7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                wm8903: wm8903@1a {
+                        compatible = "wlf,wm8903";
+                        reg = <0x1a>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <179 0x04>; /* gpio PW3 */
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        micdet-cfg = <0>;
+                        micdet-delay = <100>;
+                        gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
+                };
+
+                tps62361 {
+                        compatible = "ti,tps62361";
+                        reg = <0x60>;
+
+                        regulator-name = "tps62361-vout";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1500000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-high;
+                        ti,vsel1-state-high;
+                };
+
+                pmic: tps65911@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+
+                        interrupts = <0 86 0x4>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        ti,system-power-controller;
+
+                        #gpio-cells = <2>;
+                        gpio-controller;
+
+                        vcc1-supply = <&vdd_ac_bat_reg>;
+                        vcc2-supply = <&vdd_ac_bat_reg>;
+                        vcc3-supply = <&vio_reg>;
+                        vcc4-supply = <&vdd_5v0_reg>;
+                        vcc5-supply = <&vdd_ac_bat_reg>;
+                        vcc6-supply = <&vdd2_reg>;
+                        vcc7-supply = <&vdd_ac_bat_reg>;
+                        vccio-supply = <&vdd_ac_bat_reg>;
+
+                        regulators {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                vdd1_reg: regulator@0 {
+                                        reg = <0>;
+                                        regulator-compatible = "vdd1";
+                                        regulator-name = "vddio_ddr_1v2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                vdd2_reg: regulator@1 {
+                                        reg = <1>;
+                                        regulator-compatible = "vdd2";
+                                        regulator-name = "vdd_1v5_gen";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                };
+
+                                vddctrl_reg: regulator@2 {
+                                        reg = <2>;
+                                        regulator-compatible = "vddctrl";
+                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                vio_reg: regulator@3 {
+                                        reg = <3>;
+                                        regulator-compatible = "vio";
+                                        regulator-name = "vdd_1v8_gen";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo1_reg: regulator@4 {
+                                        reg = <4>;
+                                        regulator-compatible = "ldo1";
+                                        regulator-name = "vdd_pexa,vdd_pexb";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                ldo2_reg: regulator@5 {
+                                        reg = <5>;
+                                        regulator-compatible = "ldo2";
+                                        regulator-name = "vdd_sata,avdd_plle";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                /* LDO3 is not connected to anything */
+
+                                ldo4_reg: regulator@7 {
+                                        reg = <7>;
+                                        regulator-compatible = "ldo4";
+                                        regulator-name = "vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo5_reg: regulator@8 {
+                                        reg = <8>;
+                                        regulator-compatible = "ldo5";
+                                        regulator-name = "vddio_sdmmc,avdd_vdac";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo6_reg: regulator@9 {
+                                        reg = <9>;
+                                        regulator-compatible = "ldo6";
+                                        regulator-name = "avdd_dsi_csi,pwrdet_mipi";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+
+                                ldo7_reg: regulator@10 {
+                                        reg = <10>;
+                                        regulator-compatible = "ldo7";
+                                        regulator-name = "vdd_pllm,x,u,a_p_c_s";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo8_reg: regulator@11 {
+                                        reg = <11>;
+                                        regulator-compatible = "ldo8";
+                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
+        pmc {
+                status = "okay";
+                nvidia,invert-interrupt;
+        };
+
+        sdhci@78000000 {
+                status = "okay";
+                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
+                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                bus-width = <4>;
+        };
+
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vdd_ac_bat_reg: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "vdd_ac_bat";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+
+                cam_1v8_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "cam_1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        enable-active-high;
+                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        vin-supply = <&vio_reg>;
+                };
+
+                cp_5v_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "cp_5v";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        enable-active-high;
+                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                };
+
+                emmc_3v3_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "emmc_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                modem_3v3_reg: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "modem_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                };
+
+                pex_hvdd_3v3_reg: regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "pex_hvdd_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam1_ldo_reg: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "vdd_cam1_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam2_ldo_reg: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "vdd_cam2_ldo";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        enable-active-high;
+                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_cam3_ldo_reg: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "vdd_cam3_ldo";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_com_reg: regulator@9 {
+                        compatible = "regulator-fixed";
+                        reg = <9>;
+                        regulator-name = "vdd_com";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_fuse_3v3_reg: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "vdd_fuse_3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_pnl1_reg: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "vdd_pnl1";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        enable-active-high;
+                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        vin-supply = <&sys_3v3_reg>;
+                };
+
+                vdd_vid_reg: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "vddio_vid";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8903-cardhu",
+                             "nvidia,tegra-audio-wm8903";
+                nvidia,model = "NVIDIA Tegra Cardhu";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "HPOUTR",
+                        "Headphone Jack", "HPOUTL",
+                        "Int Spk", "ROP",
+                        "Int Spk", "RON",
+                        "Int Spk", "LOP",
+                        "Int Spk", "LON",
+                        "Mic Jack", "MICBIAS",
+                        "IN1L", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&wm8903>;
+
+                nvidia,spkr-en-gpios = <&wm8903 2 0>;
+                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 3e4334d14efb..b1497c7d7d68 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -117,7 +117,7 @@
                 status = "disabled";
         };
 
-        pwm {
+        pwm: pwm {
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
diff --git a/arch/arm/boot/dts/tps65217.dtsi b/arch/arm/boot/dts/tps65217.dtsi
new file mode 100644
index 000000000000..a63272422d76
--- /dev/null
+++ b/arch/arm/boot/dts/tps65217.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+        compatible = "ti,tps65217";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                dcdc1_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "dcdc1";
+                };
+
+                dcdc2_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "dcdc2";
+                };
+
+                dcdc3_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "dcdc3";
+                };
+
+                ldo1_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "ldo1";
+                };
+
+                ldo2_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "ldo2";
+                };
+
+                ldo3_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "ldo3";
+                };
+
+                ldo4_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "ldo4";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tps65910.dtsi b/arch/arm/boot/dts/tps65910.dtsi
new file mode 100644
index 000000000000..92693a89160e
--- /dev/null
+++ b/arch/arm/boot/dts/tps65910.dtsi
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65910.pdf
+ */
+
+&tps {
+        compatible = "ti,tps65910";
+
+        regulators {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                vrtc_reg: regulator@0 {
+                        reg = <0>;
+                        regulator-compatible = "vrtc";
+                };
+
+                vio_reg: regulator@1 {
+                        reg = <1>;
+                        regulator-compatible = "vio";
+                };
+
+                vdd1_reg: regulator@2 {
+                        reg = <2>;
+                        regulator-compatible = "vdd1";
+                };
+
+                vdd2_reg: regulator@3 {
+                        reg = <3>;
+                        regulator-compatible = "vdd2";
+                };
+
+                vdd3_reg: regulator@4 {
+                        reg = <4>;
+                        regulator-compatible = "vdd3";
+                };
+
+                vdig1_reg: regulator@5 {
+                        reg = <5>;
+                        regulator-compatible = "vdig1";
+                };
+
+                vdig2_reg: regulator@6 {
+                        reg = <6>;
+                        regulator-compatible = "vdig2";
+                };
+
+                vpll_reg: regulator@7 {
+                        reg = <7>;
+                        regulator-compatible = "vpll";
+                };
+
+                vdac_reg: regulator@8 {
+                        reg = <8>;
+                        regulator-compatible = "vdac";
+                };
+
+                vaux1_reg: regulator@9 {
+                        reg = <9>;
+                        regulator-compatible = "vaux1";
+                };
+
+                vaux2_reg: regulator@10 {
+                        reg = <10>;
+                        regulator-compatible = "vaux2";
+                };
+
+                vaux33_reg: regulator@11 {
+                        reg = <11>;
+                        regulator-compatible = "vaux33";
+                };
+
+                vmmc_reg: regulator@12 {
+                        reg = <12>;
+                        regulator-compatible = "vmmc";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 22f4d1394ed3..ff000172c93c 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -19,19 +19,19 @@
                 interrupts = <11>;
         };
 
-        vdac: regulator@0 {
+        vdac: regulator-vdac {
                 compatible = "ti,twl4030-vdac";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
         };
 
-        vpll2: regulator@1 {
+        vpll2: regulator-vpll2 {
                 compatible = "ti,twl4030-vpll2";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
         };
 
-        vmmc1: regulator@2 {
+        vmmc1: regulator-vmmc1 {
                 compatible = "ti,twl4030-vmmc1";
                 regulator-min-microvolt = <1850000>;
                 regulator-max-microvolt = <3150000>;
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index d351b27d7213..123e2c40218a 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -20,70 +20,70 @@
                 interrupts = <11>;
         };
 
-        vaux1: regulator@0 {
+        vaux1: regulator-vaux1 {
                 compatible = "ti,twl6030-vaux1";
                 regulator-min-microvolt = <1000000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vaux2: regulator@1 {
+        vaux2: regulator-vaux2 {
                 compatible = "ti,twl6030-vaux2";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <2800000>;
         };
 
-        vaux3: regulator@2 {
+        vaux3: regulator-vaux3 {
                 compatible = "ti,twl6030-vaux3";
                 regulator-min-microvolt = <1000000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vmmc: regulator@3 {
+        vmmc: regulator-vmmc {
                 compatible = "ti,twl6030-vmmc";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <3000000>;
         };
 
-        vpp: regulator@4 {
+        vpp: regulator-vpp {
                 compatible = "ti,twl6030-vpp";
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <2500000>;
         };
 
-        vusim: regulator@5 {
+        vusim: regulator-vusim {
                 compatible = "ti,twl6030-vusim";
                 regulator-min-microvolt = <1200000>;
                 regulator-max-microvolt = <2900000>;
         };
 
-        vdac: regulator@6 {
+        vdac: regulator-vdac {
                 compatible = "ti,twl6030-vdac";
         };
 
-        vana: regulator@7 {
+        vana: regulator-vana {
                 compatible = "ti,twl6030-vana";
         };
 
-        vcxio: regulator@8 {
+        vcxio: regulator-vcxio {
                 compatible = "ti,twl6030-vcxio";
                 regulator-always-on;
         };
 
-        vusb: regulator@9 {
+        vusb: regulator-vusb {
                 compatible = "ti,twl6030-vusb";
         };
 
-        v1v8: regulator@10 {
+        v1v8: regulator-v1v8 {
                 compatible = "ti,twl6030-v1v8";
                 regulator-always-on;
         };
 
-        v2v1: regulator@11 {
+        v2v1: regulator-v2v1 {
                 compatible = "ti,twl6030-v2v1";
                 regulator-always-on;
         };
 
-        clk32kg: regulator@12 {
+        clk32kg: regulator-clk32kg {
                 compatible = "ti,twl6030-clk32kg";
         };
 };
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
new file mode 100644
index 000000000000..567cf4e8ab84
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -0,0 +1,36 @@
+/*
+ * vt8500-bv07.dts - Device tree file for Benign BV07 Netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "vt8500.dtsi"
+
+/ {
+        model = "Benign BV07 Netbook";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
new file mode 100644
index 000000000000..d8645e990b21
--- /dev/null
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -0,0 +1,116 @@
+/*
+ * vt8500.dtsi - Device tree file for VIA VT8500 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "via,vt8500";
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc>;
+
+                intc: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "via,vt8500-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d800e400 {
+                        compatible = "via,vt8500-fb";
+                        reg = <0xd800e400 0x400>;
+                        interrupts = <12>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
new file mode 100644
index 000000000000..fd4e248074c6
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8505-ref.dts - Device tree file for Wondermedia WM8505 reference netbook
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8505.dtsi"
+
+/ {
+        model = "Wondermedia WM8505 Netbook";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <32>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
new file mode 100644
index 000000000000..b459691655ab
--- /dev/null
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -0,0 +1,143 @@
+/*
+ * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8505";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8505-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007100 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007100 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007300 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007300 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <31>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
new file mode 100644
index 000000000000..cefd938f842f
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -0,0 +1,36 @@
+/*
+ * wm8650-mid.dts - Device tree file for Wondermedia WM8650-MID Tablet
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8650.dtsi"
+
+/ {
+        model = "Wondermedia WM8650-MID Tablet";
+
+        /*
+         * Display node is based on Sascha Hauer's patch on dri-devel.
+         * Added a bpp property to calculate the size of the framebuffer
+         * until the binding is formalized.
+         */
+        display: display@0 {
+                modes {
+                        mode0: mode@0 {
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <88>;
+                                hfront-porch = <40>;
+                                hsync-len = <0>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                vsync-len = <1>;
+                                clock = <0>;    /* unused but required */
+                                bpp = <16>;     /* non-standard but required */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
new file mode 100644
index 000000000000..83b9467559bb
--- /dev/null
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -0,0 +1,147 @@
+/*
+ * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8650";
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                gpio: gpio-controller@d8110000 {
+                        compatible = "wm,wm8650-gpio";
+                        gpio-controller;
+                        reg = <0xd8110000 0x10000>;
+                        #gpio-cells = <3>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
+                                arm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                sdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x328>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <18>;
+                                };
+                        };
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <43>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <43>;
+                };
+
+                fb@d8050800 {
+                        compatible = "wm,wm8505-fb";
+                        reg = <0xd8050800 0x200>;
+                        display = <&display>;
+                        default-mode = <&mode0>;
+                };
+
+                ge_rops@d8050400 {
+                        compatible = "wm,prizm-ge-rops";
+                        reg = <0xd8050400 0x100>;
+                };
+
+                uart@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&ref24>;
+                };
+
+                uart@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&ref24>;
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+        };
+};
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 3c9f32f9b6b4..565132d02105 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
-CONFIG_MACH_MX51_EFIKAMX=y
-CONFIG_MACH_MX51_EFIKASB=y
-CONFIG_MACH_IMX53_DT=y
+CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 4edcfb4e4dee..36d60dda310c 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -23,12 +23,6 @@ CONFIG_BLK_DEV_INTEGRITY=y
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_MXS=y
 CONFIG_MACH_MXS_DT=y
-CONFIG_MACH_MX23EVK=y
-CONFIG_MACH_MX28EVK=y
-CONFIG_MACH_STMP378X_DEVB=y
-CONFIG_MACH_TX28=y
-CONFIG_MACH_M28EVK=y
-CONFIG_MACH_APX4DEVKIT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index e58edc36b406..62303043db9c 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -123,6 +123,7 @@ CONFIG_HW_RANDOM=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
diff --git a/arch/arm/include/asm/hardware/cache-tauros2.h b/arch/arm/include/asm/hardware/cache-tauros2.h
index 538f17ca905b..295e2e40151b 100644
--- a/arch/arm/include/asm/hardware/cache-tauros2.h
+++ b/arch/arm/include/asm/hardware/cache-tauros2.h
@@ -8,4 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-extern void __init tauros2_init(void);
+#define CACHE_TAUROS2_PREFETCH_ON       (1 << 0)
+#define CACHE_TAUROS2_LINEFILL_BURST8   (1 << 1)
+
+extern void __init tauros2_init(unsigned int features);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index cc4c6a5a357c..bd54d7b7ef85 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -279,7 +279,7 @@ void __init dove_init(void)
         printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
-        tauros2_init();
+        tauros2_init(0);
 #endif
         dove_setup_cpu_mbus();
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542ad6f97..7ca5fe45945f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -101,13 +101,8 @@ config	SOC_IMX51
         select SOC_IMX5
         select ARCH_MX5
         select ARCH_MX51
-
-config  SOC_IMX53
-        bool
-        select SOC_IMX5
-        select ARCH_MX5
-        select ARCH_MX53
-        select HAVE_CAN_FLEXCAN if CAN
+        select PINCTRL
+        select PINCTRL_IMX51
 
 if ARCH_IMX_V4_V5
 
@@ -561,7 +556,6 @@ config MACH_BUG
 config MACH_IMX31_DT
         bool "Support i.MX31 platforms from device tree"
         select SOC_IMX31
-        select USE_OF
         help
           Include support for Freescale i.MX31 based platforms
           using the device tree for discovery.
@@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
 
 endchoice
 
-config MX51_EFIKA_COMMON
-        bool
-        select SOC_IMX51
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_PATA_IMX
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
-
-config MACH_MX51_EFIKAMX
-        bool "Support MX51 Genesi Efika MX nettop"
-        select LEDS_GPIO_REGISTER
-        select MX51_EFIKA_COMMON
-        help
-          Include support for Genesi Efika MX nettop. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX51_EFIKASB
-        bool "Support MX51 Genesi Efika Smartbook"
-        select LEDS_GPIO_REGISTER
-        select MX51_EFIKA_COMMON
-        help
-          Include support for Genesi Efika Smartbook. This includes specific
-          configurations for the board and its peripherals.
-
-comment "i.MX53 machines:"
-
-config MACH_IMX53_DT
-        bool "Support i.MX53 platforms from device tree"
-        select SOC_IMX53
-        select MACH_MX53_ARD
-        select MACH_MX53_EVK
-        select MACH_MX53_LOCO
-        select MACH_MX53_SMD
-        help
-          Include support for Freescale i.MX53 based platforms
-          using the device tree for discovery
-
-config MACH_MX53_EVK
-        bool "Support MX53 EVK platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX53_SMD
-        bool "Support MX53 SMD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        help
-          Include support for MX53 SMD platform. This includes specific
-          configurations for the board and its peripherals.
+comment "Device tree only"
 
-config MACH_MX53_LOCO
-        bool "Support MX53 LOCO platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
-        select LEDS_GPIO_REGISTER
-        help
-          Include support for MX53 LOCO platform. This includes specific
-          configurations for the board and its peripherals.
+config  SOC_IMX53
+        bool "i.MX53 support"
+        select SOC_IMX5
+        select ARCH_MX5
+        select ARCH_MX53
+        select HAVE_CAN_FLEXCAN if CAN
+        select PINCTRL
+        select PINCTRL_IMX53
 
-config MACH_MX53_ARD
-        bool "Support MX53 ARD platforms"
-        select SOC_IMX53
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_GPIO_KEYS
         help
-          Include support for MX53 ARD platform. This includes specific
-          configurations for the board and its peripherals.
-
-comment "i.MX6 family:"
+          This enables support for Freescale i.MX53 processor.
 
 config SOC_IMX6Q
         bool "i.MX6 Quad support"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d1204198ca83..895754aeb4f3 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,16 +83,9 @@ endif
 # i.MX5 based machines
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
 obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
 obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
 obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
 
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
+obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 05541cf4a878..c60967629e27 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q)	:= 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
 
 dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
-dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
-                               imx53-qsb.dtb imx53-smd.dtb
+
+dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \
+                           imx53-evk.dtb \
+                           imx53-qsb.dtb \
+                           imx53-smd.dtb \
+
 dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
                            imx6q-sabrelite.dtb \
                            imx6q-sabresd.dtb \
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4233d9e3531d..3ec242f3341e 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -157,6 +157,7 @@ enum mx6q_clks {
 };
 
 static struct clk *clk[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum mx6q_clks const clks_init_on[] __initconst = {
         mmdc_ch0_axi, rom,
@@ -394,52 +395,24 @@ int __init mx6q_clocks_init(void)
                         pr_err("i.MX6q clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
         clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
-        clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
-        clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
-        clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
-        clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
-        clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
-        clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
-        clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
-        clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
-        clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
-        clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
-        clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
-        clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
-        clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
-        clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
-        clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
-        clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
-        clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
-        clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
-        clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
-        clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
-        clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
-        clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
-        clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
-        clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
-        clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
-        clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
         clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
         clk_register_clkdev(clk[ahb], "ahb", NULL);
         clk_register_clkdev(clk[cko1], "cko1", NULL);
 
+        /*
+         * The gpmi needs 100MHz frequency in the EDO/Sync mode,
+         * We can not get the 100MHz from the pll2_pfd0_352m.
+         * So choose pll2_pfd2_396m as enfc_sel's parent.
+         */
+        clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
+
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clk[clks_init_on[i]]);
 
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
deleted file mode 100644
index 77e0db96c448..000000000000
--- a/arch/arm/mach-imx/devices-imx53.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx53.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx53_fec_data;
-#define imx53_add_fec(pdata)   \
-        imx_add_fec(&imx53_fec_data, pdata)
-
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
-#define imx53_add_imx_uart(id, pdata)   \
-        imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-
-
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
-#define imx53_add_imx_i2c(id, pdata)    \
-        imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-
-extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
-#define imx53_add_sdhci_esdhc_imx(id, pdata)    \
-        imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx53_ecspi_data[];
-#define imx53_add_ecspi(id, pdata)      \
-        imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id)  \
-        imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
-
-extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
-#define imx53_add_imx_ssi(id, pdata)    \
-        imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
-#define imx53_add_imx_keypad(pdata)     \
-        imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
-
-extern const struct imx_pata_imx_data imx53_pata_imx_data;
-#define imx53_add_pata_imx() \
-        imx_add_pata_imx(&imx53_pata_imx_data)
-
-extern struct platform_device *__init imx53_add_ahci_imx(void);
diff --git a/arch/arm/mach-imx/efika.h b/arch/arm/mach-imx/efika.h
deleted file mode 100644
index 014aa985faae..000000000000
--- a/arch/arm/mach-imx/efika.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _EFIKA_H
-#define _EFIKA_H
-
-#define EFIKA_WLAN_EN           IMX_GPIO_NR(2, 16)
-#define EFIKA_WLAN_RESET        IMX_GPIO_NR(2, 10)
-#define EFIKA_USB_PHY_RESET     IMX_GPIO_NR(2, 9)
-
-void __init efika_board_common_init(void);
-
-#endif
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index d4067fe36357..f233b4bb2342 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -13,7 +13,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
-        { /* sentinel */ }
-};
-
 static void __init imx51_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-
-        pinctrl_provide_dummies();
-
-        node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx51_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
-
         of_platform_populate(NULL, of_default_bus_match_table,
                              imx51_auxdata_lookup, NULL);
 }
@@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
 };
 
 static const char *imx51_dt_board_compat[] __initdata = {
-        "fsl,imx51-babbage",
         "fsl,imx51",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/mach-imx53.c
index 1b7a2fc36591..29711e95579f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -17,7 +17,6 @@
 #include <linux/irq.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
@@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
-        { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
-        { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
-        { /* sentinel */ }
-};
-
 static void __init imx53_qsb_init(void)
 {
         struct clk *clk;
@@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
 
 static void __init imx53_dt_init(void)
 {
-        struct device_node *node;
-        const struct of_device_id *of_id;
-        void (*func)(void);
-
-        pinctrl_provide_dummies();
-
-        node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
-        if (node) {
-                of_id = of_match_node(imx53_iomuxc_of_match, node);
-                func = of_id->data;
-                func();
-                of_node_put(node);
-        }
-
         if (of_machine_is_compatible("fsl,imx53-qsb"))
                 imx53_qsb_init();
 
@@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
 };
 
 static const char *imx53_dt_board_compat[] __initdata = {
-        "fsl,imx53-ard",
-        "fsl,imx53-evk",
-        "fsl,imx53-qsb",
-        "fsl,imx53-smd",
         "fsl,imx53",
         NULL
 };
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6a387d..692b4b143bb1 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,7 +22,6 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/anatop.h>
@@ -100,7 +99,6 @@ static void __init imx6q_sabrelite_cko1_setup(void)
         clk_set_parent(cko1_sel, ahb);
         rate = clk_round_rate(cko1, 16000000);
         clk_set_rate(cko1, rate);
-        clk_register_clkdev(cko1, NULL, "0-000a");
 put_clk:
         if (!IS_ERR(cko1_sel))
                 clk_put(cko1_sel);
@@ -159,12 +157,6 @@ static void __init imx6q_usb_init(void)
 
 static void __init imx6q_init_machine(void)
 {
-        /*
-         * This should be removed when all imx6q boards have pinctrl
-         * states for devices defined in device tree.
-         */
-        pinctrl_provide_dummies();
-
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                 imx6q_sabrelite_init();
 
@@ -218,9 +210,6 @@ static struct sys_timer imx6q_timer = {
 };
 
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-arm2",
-        "fsl,imx6q-sabrelite",
-        "fsl,imx6q-sabresd",
         "fsl,imx6q",
         NULL,
 };
diff --git a/arch/arm/mach-imx/mach-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
deleted file mode 100644
index 8d09c0126cab..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikamx.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKAMX_PCBID0          IMX_GPIO_NR(3, 16)
-#define EFIKAMX_PCBID1          IMX_GPIO_NR(3, 17)
-#define EFIKAMX_PCBID2          IMX_GPIO_NR(3, 11)
-
-#define EFIKAMX_BLUE_LED        IMX_GPIO_NR(3, 13)
-#define EFIKAMX_GREEN_LED       IMX_GPIO_NR(3, 14)
-#define EFIKAMX_RED_LED         IMX_GPIO_NR(3, 15)
-
-#define EFIKAMX_POWER_KEY       IMX_GPIO_NR(2, 31)
-
-/* board 1.1 doesn't have same reset gpio */
-#define EFIKAMX_RESET1_1        IMX_GPIO_NR(3, 2)
-#define EFIKAMX_RESET           IMX_GPIO_NR(1, 4)
-
-#define EFIKAMX_POWEROFF        IMX_GPIO_NR(4, 13)
-
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-
-/* the pci ids pin have pull up. they're driven low according to board id */
-#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, PAD_CTL_PUS_100K_UP)
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-
-static iomux_v3_cfg_t mx51efikamx_pads[] = {
-        /* board id */
-        MX51_PAD_PCBID0,
-        MX51_PAD_PCBID1,
-        MX51_PAD_PCBID2,
-
-        /* leds */
-        MX51_PAD_CSI1_D9__GPIO3_13,
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-        MX51_PAD_CSI1_HSYNC__GPIO3_15,
-
-        /* power key */
-        MX51_PAD_PWRKEY,
-
-        /* reset */
-        MX51_PAD_DI1_PIN13__GPIO3_2,
-        MX51_PAD_GPIO1_4__GPIO1_4,
-
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-};
-
-/*   PCBID2  PCBID1 PCBID0  STATE
-        1       1      1    ER1:rev1.1
-        1       1      0    ER2:rev1.2
-        1       0      1    ER3:rev1.3
-        1       0      0    ER4:rev1.4
-*/
-static void __init mx51_efikamx_board_id(void)
-{
-        int id;
-
-        /* things are taking time to settle */
-        msleep(150);
-
-        gpio_request(EFIKAMX_PCBID0, "pcbid0");
-        gpio_direction_input(EFIKAMX_PCBID0);
-        gpio_request(EFIKAMX_PCBID1, "pcbid1");
-        gpio_direction_input(EFIKAMX_PCBID1);
-        gpio_request(EFIKAMX_PCBID2, "pcbid2");
-        gpio_direction_input(EFIKAMX_PCBID2);
-
-        id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
-        id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
-
-        switch (id) {
-        case 7:
-                system_rev = 0x11;
-                break;
-        case 6:
-                system_rev = 0x12;
-                break;
-        case 5:
-                system_rev = 0x13;
-                break;
-        case 4:
-                system_rev = 0x14;
-                break;
-        default:
-                system_rev = 0x10;
-                break;
-        }
-
-        if ((system_rev == 0x10)
-                || (system_rev == 0x12)
-                || (system_rev == 0x14)) {
-                printk(KERN_WARNING
-                        "EfikaMX: Unsupported board revision 1.%u!\n",
-                        system_rev & 0xf);
-        }
-}
-
-static struct gpio_led mx51_efikamx_leds[] __initdata = {
-        {
-                .name = "efikamx:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKAMX_GREEN_LED,
-        },
-        {
-                .name = "efikamx:red",
-                .default_trigger = "ide-disk",
-                .gpio = EFIKAMX_RED_LED,
-        },
-        {
-                .name = "efikamx:blue",
-                .default_trigger = "mmc0",
-                .gpio = EFIKAMX_BLUE_LED,
-        },
-};
-
-static const struct gpio_led_platform_data
-                mx51_efikamx_leds_data __initconst = {
-        .leds = mx51_efikamx_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
-};
-
-static struct esdhc_platform_data sd_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct gpio_keys_button mx51_efikamx_powerkey[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKAMX_POWER_KEY,
-                .type = EV_PWR,
-                .desc = "Power Button (CM)",
-                .wakeup = 1,
-                .debounce_interval = 10, /* ms */
-        },
-};
-
-static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
-        .buttons = mx51_efikamx_powerkey,
-        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
-};
-
-static void mx51_efikamx_restart(char mode, const char *cmd)
-{
-        if (system_rev == 0x11)
-                gpio_direction_output(EFIKAMX_RESET1_1, 0);
-        else
-                gpio_direction_output(EFIKAMX_RESET, 0);
-}
-
-static struct regulator *pwgt1, *pwgt2, *coincell;
-
-static void mx51_efikamx_power_off(void)
-{
-        if (!IS_ERR(coincell))
-                regulator_disable(coincell);
-
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKAMX_POWEROFF, 1);
-}
-
-static int __init mx51_efikamx_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKAMX_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikamx_power_off;
-
-        /* enable coincell charger. maybe need a small power driver ? */
-        coincell = regulator_get(NULL, "coincell");
-        if (!IS_ERR(coincell)) {
-                regulator_set_voltage(coincell, 3000000, 3000000);
-                regulator_enable(coincell);
-        }
-
-        regulator_has_full_constraints();
-
-        return 0;
-}
-
-static void __init mx51_efikamx_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikamx_power_init();
-}
-
-static void __init mx51_efikamx_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
-                                        ARRAY_SIZE(mx51efikamx_pads));
-        efika_board_common_init();
-
-        mx51_efikamx_board_id();
-
-        /* on < 1.2 boards both SD controllers are used */
-        if (system_rev < 0x12) {
-                imx51_add_sdhci_esdhc_imx(0, NULL);
-                imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
-                mx51_efikamx_leds[2].default_trigger = "mmc1";
-        } else
-                imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
-
-        gpio_led_register_device(-1, &mx51_efikamx_leds_data);
-        imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
-
-        if (system_rev == 0x11) {
-                gpio_request(EFIKAMX_RESET1_1, "reset");
-                gpio_direction_output(EFIKAMX_RESET1_1, 1);
-        } else {
-                gpio_request(EFIKAMX_RESET, "reset");
-                gpio_direction_output(EFIKAMX_RESET, 1);
-        }
-
-        /*
-         * enable wifi by default only on mx
-         * sb and mx have same wlan pin but the value to enable it are
-         * different :/
-         */
-        gpio_request(EFIKA_WLAN_EN, "wlan_en");
-        gpio_direction_output(EFIKA_WLAN_EN, 0);
-        msleep(10);
-
-        gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
-        gpio_direction_output(EFIKA_WLAN_RESET, 0);
-        msleep(10);
-        gpio_set_value(EFIKA_WLAN_RESET, 1);
-}
-
-static void __init mx51_efikamx_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikamx_timer = {
-        .init = mx51_efikamx_timer_init,
-};
-
-MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .timer = &mx51_efikamx_timer,
-        .init_machine = mx51_efikamx_init,
-        .init_late = mx51_efikamx_init_late,
-        .restart = mx51_efikamx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
deleted file mode 100644
index fdbd181b97ef..000000000000
--- a/arch/arm/mach-imx/mach-mx51_efikasb.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <asm/setup.h>
-#include <asm/system_info.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-
-#define EFIKASB_USBH2_STP       IMX_GPIO_NR(2, 20)
-#define EFIKASB_GREEN_LED       IMX_GPIO_NR(1, 3)
-#define EFIKASB_WHITE_LED       IMX_GPIO_NR(2, 25)
-#define EFIKASB_PCBID0          IMX_GPIO_NR(2, 28)
-#define EFIKASB_PCBID1          IMX_GPIO_NR(2, 29)
-#define EFIKASB_PWRKEY          IMX_GPIO_NR(2, 31)
-#define EFIKASB_LID             IMX_GPIO_NR(3, 14)
-#define EFIKASB_POWEROFF        IMX_GPIO_NR(4, 13)
-#define EFIKASB_RFKILL          IMX_GPIO_NR(3, 1)
-
-#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
-#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
-
-static iomux_v3_cfg_t mx51efikasb_pads[] = {
-        /* USB HOST2 */
-        MX51_PAD_EIM_D16__USBH2_DATA0,
-        MX51_PAD_EIM_D17__USBH2_DATA1,
-        MX51_PAD_EIM_D18__USBH2_DATA2,
-        MX51_PAD_EIM_D19__USBH2_DATA3,
-        MX51_PAD_EIM_D20__USBH2_DATA4,
-        MX51_PAD_EIM_D21__USBH2_DATA5,
-        MX51_PAD_EIM_D22__USBH2_DATA6,
-        MX51_PAD_EIM_D23__USBH2_DATA7,
-        MX51_PAD_EIM_A24__USBH2_CLK,
-        MX51_PAD_EIM_A25__USBH2_DIR,
-        MX51_PAD_EIM_A26__USBH2_STP,
-        MX51_PAD_EIM_A27__USBH2_NXT,
-
-        /* leds */
-        MX51_PAD_EIM_CS0__GPIO2_25,
-        MX51_PAD_GPIO1_3__GPIO1_3,
-
-        /* pcb id */
-        MX51_PAD_EIM_CS3__GPIO2_28,
-        MX51_PAD_EIM_CS4__GPIO2_29,
-
-        /* lid */
-        MX51_PAD_CSI1_VSYNC__GPIO3_14,
-
-        /* power key*/
-        MX51_PAD_PWRKEY,
-
-        /* wifi/bt button */
-        MX51_PAD_DI1_PIN12__GPIO3_1,
-
-        /* power off */
-        MX51_PAD_CSI2_VSYNC__GPIO4_13,
-
-        /* wdog reset */
-        MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
-
-        /* BT */
-        MX51_PAD_EIM_A17__GPIO2_11,
-
-        MX51_PAD_SD1_CD,
-};
-
-static int initialize_usbh2_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
-        iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
-
-        mxc_iomux_v3_setup_pad(usbh2gpio);
-        gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
-        gpio_direction_output(EFIKASB_USBH2_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKASB_USBH2_STP, 1);
-        msleep(1);
-
-        gpio_free(EFIKASB_USBH2_STP);
-        mxc_iomux_v3_setup_pad(usbh2stp);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh2_config __initdata = {
-        .init   = initialize_usbh2_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void __init mx51_efikasb_usb(void)
-{
-        usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-        if (usbh2_config.otg)
-                imx51_add_mxc_ehci_hs(2, &usbh2_config);
-}
-
-static const struct gpio_led mx51_efikasb_leds[] __initconst = {
-        {
-                .name = "efikasb:green",
-                .default_trigger = "default-on",
-                .gpio = EFIKASB_GREEN_LED,
-                .active_low = 1,
-        },
-        {
-                .name = "efikasb:white",
-                .default_trigger = "caps",
-                .gpio = EFIKASB_WHITE_LED,
-        },
-};
-
-static const struct gpio_led_platform_data
-                mx51_efikasb_leds_data __initconst = {
-        .leds = mx51_efikasb_leds,
-        .num_leds = ARRAY_SIZE(mx51_efikasb_leds),
-};
-
-static struct gpio_keys_button mx51_efikasb_keys[] = {
-        {
-                .code = KEY_POWER,
-                .gpio = EFIKASB_PWRKEY,
-                .type = EV_KEY,
-                .desc = "Power Button",
-                .wakeup = 1,
-                .active_low = 1,
-        },
-        {
-                .code = SW_LID,
-                .gpio = EFIKASB_LID,
-                .type = EV_SW,
-                .desc = "Lid Switch",
-                .active_low = 1,
-        },
-        {
-                .code = KEY_RFKILL,
-                .gpio = EFIKASB_RFKILL,
-                .type = EV_KEY,
-                .desc = "rfkill",
-                .active_low = 1,
-        },
-};
-
-static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
-        .buttons = mx51_efikasb_keys,
-        .nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
-};
-
-static struct esdhc_platform_data sd0_pdata = {
-#define EFIKASB_SD1_CD  IMX_GPIO_NR(2, 27)
-        .cd_gpio = EFIKASB_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-
-static struct regulator *pwgt1, *pwgt2;
-
-static void mx51_efikasb_power_off(void)
-{
-        gpio_set_value(EFIKA_USB_PHY_RESET, 0);
-
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_disable(pwgt2);
-                regulator_disable(pwgt1);
-        }
-        gpio_direction_output(EFIKASB_POWEROFF, 1);
-}
-
-static int __init mx51_efikasb_power_init(void)
-{
-        pwgt1 = regulator_get(NULL, "pwgt1");
-        pwgt2 = regulator_get(NULL, "pwgt2");
-        if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
-                regulator_enable(pwgt1);
-                regulator_enable(pwgt2);
-        }
-        gpio_request(EFIKASB_POWEROFF, "poweroff");
-        pm_power_off = mx51_efikasb_power_off;
-
-        regulator_has_full_constraints();
-
-        return 0;
-}
-
-static void __init mx51_efikasb_init_late(void)
-{
-        imx51_init_late();
-        mx51_efikasb_power_init();
-}
-
-/* 01     R1.3 board
-   10     R2.0 board */
-static void __init mx51_efikasb_board_id(void)
-{
-        int id;
-
-        gpio_request(EFIKASB_PCBID0, "pcb id0");
-        gpio_direction_input(EFIKASB_PCBID0);
-        gpio_request(EFIKASB_PCBID1, "pcb id1");
-        gpio_direction_input(EFIKASB_PCBID1);
-
-        id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
-        id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
-
-        switch (id) {
-        default:
-                break;
-        case 1:
-                system_rev = 0x13;
-                break;
-        case 2:
-                system_rev = 0x20;
-                break;
-        }
-}
-
-static void __init efikasb_board_init(void)
-{
-        imx51_soc_init();
-
-        mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
-                                        ARRAY_SIZE(mx51efikasb_pads));
-        efika_board_common_init();
-
-        mx51_efikasb_board_id();
-        mx51_efikasb_usb();
-        imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
-        imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
-
-        gpio_led_register_device(-1, &mx51_efikasb_leds_data);
-        imx_add_gpio_keys(&mx51_efikasb_keys_data);
-}
-
-static void __init mx51_efikasb_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 24576000);
-}
-
-static struct sys_timer mx51_efikasb_timer = {
-        .init   = mx51_efikasb_timer_init,
-};
-
-MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .init_machine =  efikasb_board_init,
-        .init_late = mx51_efikasb_init_late,
-        .timer = &mx51_efikasb_timer,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
deleted file mode 100644
index 6c28e65f424d..000000000000
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define ARD_ETHERNET_INT_B      IMX_GPIO_NR(2, 31)
-#define ARD_SD1_CD              IMX_GPIO_NR(1, 1)
-#define ARD_SD1_WP              IMX_GPIO_NR(1, 9)
-#define ARD_I2CPORTEXP_B        IMX_GPIO_NR(2, 3)
-#define ARD_VOLUMEDOWN          IMX_GPIO_NR(4, 0)
-#define ARD_HOME                        IMX_GPIO_NR(5, 10)
-#define ARD_BACK                        IMX_GPIO_NR(5, 11)
-#define ARD_PROG                        IMX_GPIO_NR(5, 12)
-#define ARD_VOLUMEUP            IMX_GPIO_NR(5, 13)
-
-static iomux_v3_cfg_t mx53_ard_pads[] = {
-        /* UART1 */
-        MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
-        MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
-        /* WEIM for CS1 */
-        MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
-        MX53_PAD_EIM_D16__EMI_WEIM_D_16,
-        MX53_PAD_EIM_D17__EMI_WEIM_D_17,
-        MX53_PAD_EIM_D18__EMI_WEIM_D_18,
-        MX53_PAD_EIM_D19__EMI_WEIM_D_19,
-        MX53_PAD_EIM_D20__EMI_WEIM_D_20,
-        MX53_PAD_EIM_D21__EMI_WEIM_D_21,
-        MX53_PAD_EIM_D22__EMI_WEIM_D_22,
-        MX53_PAD_EIM_D23__EMI_WEIM_D_23,
-        MX53_PAD_EIM_D24__EMI_WEIM_D_24,
-        MX53_PAD_EIM_D25__EMI_WEIM_D_25,
-        MX53_PAD_EIM_D26__EMI_WEIM_D_26,
-        MX53_PAD_EIM_D27__EMI_WEIM_D_27,
-        MX53_PAD_EIM_D28__EMI_WEIM_D_28,
-        MX53_PAD_EIM_D29__EMI_WEIM_D_29,
-        MX53_PAD_EIM_D30__EMI_WEIM_D_30,
-        MX53_PAD_EIM_D31__EMI_WEIM_D_31,
-        MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
-        MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
-        MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
-        MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
-        MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
-        MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
-        MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
-        MX53_PAD_EIM_OE__EMI_WEIM_OE,
-        MX53_PAD_EIM_RW__EMI_WEIM_RW,
-        MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
-        /* SDHC1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
-        MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
-        MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
-        MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
-        MX53_PAD_GPIO_1__GPIO1_1,
-        MX53_PAD_GPIO_9__GPIO1_9,
-        /* I2C2 */
-        MX53_PAD_EIM_EB2__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* I2C3 */
-        MX53_PAD_GPIO_3__I2C3_SCL,
-        MX53_PAD_GPIO_16__I2C3_SDA,
-        /* GPIO */
-        MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
-        MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
-        MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
-        MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
-        MX53_PAD_GPIO_10__GPIO4_0,              /* vol down */
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                       \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                 \
-        .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button ard_buttons[] = {
-        GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
-        GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
-        GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
-        GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data ard_button_data __initconst = {
-        .buttons        = ard_buttons,
-        .nbuttons       = ARRAY_SIZE(ard_buttons),
-};
-
-static struct resource ard_smsc911x_resources[] = {
-        {
-                .start = MX53_CS1_64MB_BASE_ADDR,
-                .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                /* irq number is run-time assigned */
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct smsc911x_platform_config ard_smsc911x_config = {
-        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags = SMSC911X_USE_32BIT,
-};
-
-static struct platform_device ard_smsc_lan9220_device = {
-        .name = "smsc911x",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
-        .resource = ard_smsc911x_resources,
-        .dev = {
-                .platform_data = &ard_smsc911x_config,
-        },
-};
-
-static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
-        .cd_gpio = ARD_SD1_CD,
-        .wp_gpio = ARD_SD1_WP,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c2_data = {
-        .bitrate = 50000,
-};
-
-static struct imxi2c_platform_data mx53_ard_i2c3_data = {
-        .bitrate = 400000,
-};
-
-static void __init mx53_ard_io_init(void)
-{
-        gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
-        gpio_direction_input(ARD_ETHERNET_INT_B);
-
-        gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
-        gpio_direction_output(ARD_I2CPORTEXP_B, 1);
-}
-
-/* Config CS1 settings for ethernet controller */
-static int weim_cs_config(void)
-{
-        u32 reg;
-        void __iomem *weim_base, *iomuxc_base;
-
-        weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
-        if (!weim_base)
-                return -ENOMEM;
-
-        iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
-        if (!iomuxc_base) {
-                iounmap(weim_base);
-                return -ENOMEM;
-        }
-
-        /* CS1 timings for LAN9220 */
-        writel(0x20001, (weim_base + 0x18));
-        writel(0x0, (weim_base + 0x1C));
-        writel(0x16000202, (weim_base + 0x20));
-        writel(0x00000002, (weim_base + 0x24));
-        writel(0x16002082, (weim_base + 0x28));
-        writel(0x00000000, (weim_base + 0x2C));
-        writel(0x00000000, (weim_base + 0x90));
-
-        /* specify 64 MB on CS1 and CS0 on GPR1 */
-        reg = readl(iomuxc_base + 0x4);
-        reg &= ~0x3F;
-        reg |= 0x1B;
-        writel(reg, (iomuxc_base + 0x4));
-
-        iounmap(iomuxc_base);
-        iounmap(weim_base);
-
-        return 0;
-}
-
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-};
-
-void __init imx53_ard_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
-                                         ARRAY_SIZE(mx53_ard_pads));
-        weim_cs_config();
-}
-
-static struct platform_device *devices[] __initdata = {
-        &ard_smsc_lan9220_device,
-};
-
-static void __init mx53_ard_board_init(void)
-{
-        imx53_soc_init();
-        imx53_add_imx_uart(0, NULL);
-
-        imx53_ard_common_init();
-        mx53_ard_io_init();
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-        ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
-        ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-
-        imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
-        imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
-        imx_add_gpio_keys(&ard_button_data);
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_ard_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_ard_timer = {
-        .init   = mx53_ard_timer_init,
-};
-
-MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_ard_timer,
-        .init_machine = mx53_ard_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
deleted file mode 100644
index 09fe2197b491..000000000000
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <mach/iomux-mx53.h>
-
-#define MX53_EVK_FEC_PHY_RST    IMX_GPIO_NR(7, 6)
-#define EVK_ECSPI1_CS0          IMX_GPIO_NR(2, 30)
-#define EVK_ECSPI1_CS1          IMX_GPIO_NR(3, 19)
-#define MX53EVK_LED             IMX_GPIO_NR(7, 7)
-
-#include "devices-imx53.h"
-
-static iomux_v3_cfg_t mx53_evk_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-        MX53_PAD_PATA_DIOR__UART2_RTS,
-        MX53_PAD_PATA_INTRQ__UART2_CTS,
-
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-
-        MX53_PAD_EIM_D16__ECSPI1_SCLK,
-        MX53_PAD_EIM_D17__ECSPI1_MISO,
-        MX53_PAD_EIM_D18__ECSPI1_MOSI,
-
-        /* ecspi chip select lines */
-        MX53_PAD_EIM_EB2__GPIO2_30,
-        MX53_PAD_EIM_D19__GPIO3_19,
-        /* LED */
-        MX53_PAD_PATA_DA_1__GPIO7_7,
-};
-
-static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct gpio_led mx53evk_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = MX53EVK_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
-        .leds           = mx53evk_leds,
-        .num_leds       = ARRAY_SIZE(mx53evk_leds),
-};
-
-static inline void mx53_evk_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
-        imx53_add_imx_uart(2, NULL);
-}
-
-static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static inline void mx53_evk_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
-                                                        "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        msleep(1);
-        gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
-        {
-                .modalias = "mtd_dataflash",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-                .platform_data = NULL,
-        },
-};
-
-static int mx53_evk_spi_cs[] = {
-        EVK_ECSPI1_CS0,
-        EVK_ECSPI1_CS1,
-};
-
-static const struct spi_imx_master mx53_evk_spi_data __initconst = {
-        .chipselect     = mx53_evk_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
-};
-
-void __init imx53_evk_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
-                                         ARRAY_SIZE(mx53_evk_pads));
-}
-
-static void __init mx53_evk_board_init(void)
-{
-        imx53_soc_init();
-        imx53_evk_common_init();
-
-        mx53_evk_init_uart();
-        mx53_evk_fec_reset();
-        imx53_add_fec(&mx53_evk_fec_pdata);
-
-        imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
-
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-
-        spi_register_board_info(mx53_evk_spi_board_info,
-                ARRAY_SIZE(mx53_evk_spi_board_info));
-        imx53_add_ecspi(0, &mx53_evk_spi_data);
-        imx53_add_imx2_wdt(0);
-        gpio_led_register_device(-1, &mx53evk_leds_data);
-}
-
-static void __init mx53_evk_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_evk_timer = {
-        .init   = mx53_evk_timer_init,
-};
-
-MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_evk_timer,
-        .init_machine = mx53_evk_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
deleted file mode 100644
index 8abe23c1d3c8..000000000000
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define MX53_LOCO_POWER                 IMX_GPIO_NR(1, 8)
-#define MX53_LOCO_UI1                   IMX_GPIO_NR(2, 14)
-#define MX53_LOCO_UI2                   IMX_GPIO_NR(2, 15)
-#define LOCO_FEC_PHY_RST                IMX_GPIO_NR(7, 6)
-#define LOCO_LED                        IMX_GPIO_NR(7, 7)
-#define LOCO_SD3_CD                     IMX_GPIO_NR(3, 11)
-#define LOCO_SD3_WP                     IMX_GPIO_NR(3, 12)
-#define LOCO_SD1_CD                     IMX_GPIO_NR(3, 13)
-#define LOCO_ACCEL_EN                   IMX_GPIO_NR(6, 14)
-
-static iomux_v3_cfg_t mx53_loco_pads[] = {
-        /* FEC */
-        MX53_PAD_FEC_MDC__FEC_MDC,
-        MX53_PAD_FEC_MDIO__FEC_MDIO,
-        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
-        MX53_PAD_FEC_RX_ER__FEC_RX_ER,
-        MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
-        MX53_PAD_FEC_RXD1__FEC_RDATA_1,
-        MX53_PAD_FEC_RXD0__FEC_RDATA_0,
-        MX53_PAD_FEC_TX_EN__FEC_TX_EN,
-        MX53_PAD_FEC_TXD1__FEC_TDATA_1,
-        MX53_PAD_FEC_TXD0__FEC_TDATA_0,
-        /* FEC_nRST */
-        MX53_PAD_PATA_DA_0__GPIO7_6,
-        /* FEC_nINT */
-        MX53_PAD_PATA_DATA4__GPIO2_4,
-        /* AUDMUX5 */
-        MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
-        MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
-        MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
-        MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        MX53_PAD_NANDF_CS1__GPIO6_14,   /* Accelerometer Enable */
-        /* I2C2 */
-        MX53_PAD_KEY_COL3__I2C2_SCL,
-        MX53_PAD_KEY_ROW3__I2C2_SDA,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD1_CD */
-        MX53_PAD_EIM_DA13__GPIO3_13,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-        /* SD3_CD */
-        MX53_PAD_EIM_DA11__GPIO3_11,
-        /* SD3_WP */
-        MX53_PAD_EIM_DA12__GPIO3_12,
-        /* VGA */
-        MX53_PAD_EIM_OE__IPU_DI1_PIN7,
-        MX53_PAD_EIM_RW__IPU_DI1_PIN8,
-        /* DISPLB */
-        MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
-        MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
-        MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
-        MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
-        /* DISP0_POWER_EN */
-        MX53_PAD_EIM_D24__GPIO3_24,
-        /* DISP0 DET INT */
-        MX53_PAD_EIM_D31__GPIO3_31,
-        /* LVDS */
-        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
-        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
-        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
-        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
-        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
-        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
-        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
-        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
-        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
-        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* UART1 */
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-        /* CSI0 */
-        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
-        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
-        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
-        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
-        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
-        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
-        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
-        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
-        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
-        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
-        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
-        /* DISPLAY */
-        MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
-        MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
-        MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
-        MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
-        MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
-        MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
-        MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
-        MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
-        MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
-        MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
-        MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
-        MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
-        MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
-        MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
-        MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
-        MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
-        MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
-        MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
-        MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
-        MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
-        MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
-        MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
-        MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
-        MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
-        MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
-        MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
-        MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
-        MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
-        /* Audio CLK*/
-        MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
-        /* PWM */
-        MX53_PAD_GPIO_1__PWM2_PWMO,
-        /* SPDIF */
-        MX53_PAD_GPIO_7__SPDIF_PLOCK,
-        MX53_PAD_GPIO_17__SPDIF_OUT1,
-        /* GPIO */
-        MX53_PAD_PATA_DA_1__GPIO7_7,            /* LED */
-        MX53_PAD_PATA_DA_2__GPIO7_8,
-        MX53_PAD_PATA_DATA5__GPIO2_5,
-        MX53_PAD_PATA_DATA6__GPIO2_6,
-        MX53_PAD_PATA_DATA14__GPIO2_14,
-        MX53_PAD_PATA_DATA15__GPIO2_15,
-        MX53_PAD_PATA_INTRQ__GPIO7_2,
-        MX53_PAD_EIM_WAIT__GPIO5_0,
-        MX53_PAD_NANDF_WP_B__GPIO6_9,
-        MX53_PAD_NANDF_RB0__GPIO6_10,
-        MX53_PAD_NANDF_CS1__GPIO6_14,
-        MX53_PAD_NANDF_CS2__GPIO6_15,
-        MX53_PAD_NANDF_CS3__GPIO6_16,
-        MX53_PAD_GPIO_5__GPIO1_5,
-        MX53_PAD_GPIO_16__GPIO7_11,
-        MX53_PAD_GPIO_8__GPIO1_8,
-};
-
-#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake)    \
-{                                                               \
-        .gpio           = gpio_num,                             \
-        .type           = EV_KEY,                               \
-        .code           = ev_code,                              \
-        .active_low     = act_low,                              \
-        .desc           = "btn " descr,                         \
-        .wakeup         = wake,                                 \
-}
-
-static struct gpio_keys_button loco_buttons[] = {
-        GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
-        GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
-        GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
-};
-
-static const struct gpio_keys_platform_data loco_button_data __initconst = {
-        .buttons        = loco_buttons,
-        .nbuttons       = ARRAY_SIZE(loco_buttons),
-};
-
-static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
-        .cd_gpio = LOCO_SD1_CD,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_NONE,
-};
-
-static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
-        .cd_gpio = LOCO_SD3_CD,
-        .wp_gpio = LOCO_SD3_WP,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_GPIO,
-};
-
-static inline void mx53_loco_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(LOCO_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(LOCO_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_loco_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static const struct gpio_led mx53loco_leds[] __initconst = {
-        {
-                .name                   = "green",
-                .default_trigger        = "heartbeat",
-                .gpio                   = LOCO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
-        .leds           = mx53loco_leds,
-        .num_leds       = ARRAY_SIZE(mx53loco_leds),
-};
-
-void __init imx53_qsb_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
-                                         ARRAY_SIZE(mx53_loco_pads));
-}
-
-static struct i2c_board_info mx53loco_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("mma8450", 0x1C),
-        },
-};
-
-static void __init mx53_loco_board_init(void)
-{
-        int ret;
-        imx53_soc_init();
-        imx53_qsb_common_init();
-
-        imx53_add_imx_uart(0, NULL);
-        mx53_loco_fec_reset();
-        imx53_add_fec(&mx53_loco_fec_data);
-        imx53_add_imx2_wdt(0);
-
-        ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
-        if (ret)
-                pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
-
-        i2c_register_board_info(0, mx53loco_i2c_devices,
-                                ARRAY_SIZE(mx53loco_i2c_devices));
-        imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
-        imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
-        imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
-        imx_add_gpio_keys(&loco_button_data);
-        gpio_led_register_device(-1, &mx53loco_leds_data);
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_loco_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 0, 0);
-}
-
-static struct sys_timer mx53_loco_timer = {
-        .init   = mx53_loco_timer_init,
-};
-
-MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_loco_timer,
-        .init_machine = mx53_loco_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
deleted file mode 100644
index b15d6a6d3b68..000000000000
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx53.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx53.h"
-
-#define SMD_FEC_PHY_RST         IMX_GPIO_NR(7, 6)
-#define MX53_SMD_SATA_PWR_EN    IMX_GPIO_NR(3, 3)
-
-static iomux_v3_cfg_t mx53_smd_pads[] = {
-        MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
-        MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
-
-        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
-        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
-
-        MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
-        MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
-        MX53_PAD_PATA_DA_1__UART3_CTS,
-        MX53_PAD_PATA_DA_2__UART3_RTS,
-        /* I2C1 */
-        MX53_PAD_CSI0_DAT8__I2C1_SDA,
-        MX53_PAD_CSI0_DAT9__I2C1_SCL,
-        /* SD1 */
-        MX53_PAD_SD1_CMD__ESDHC1_CMD,
-        MX53_PAD_SD1_CLK__ESDHC1_CLK,
-        MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
-        MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
-        MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
-        MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
-        /* SD2 */
-        MX53_PAD_SD2_CMD__ESDHC2_CMD,
-        MX53_PAD_SD2_CLK__ESDHC2_CLK,
-        MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
-        MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
-        MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
-        MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
-        /* SD3 */
-        MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
-        MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
-        MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
-        MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
-        MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
-        MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
-        MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
-        MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
-        MX53_PAD_PATA_IORDY__ESDHC3_CLK,
-        MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
-};
-
-static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static inline void mx53_smd_init_uart(void)
-{
-        imx53_add_imx_uart(0, NULL);
-        imx53_add_imx_uart(1, NULL);
-        imx53_add_imx_uart(2, &mx53_smd_uart_data);
-}
-
-static inline void mx53_smd_fec_reset(void)
-{
-        int ret;
-
-        /* reset FEC PHY */
-        ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        gpio_direction_output(SMD_FEC_PHY_RST, 0);
-        msleep(1);
-        gpio_set_value(SMD_FEC_PHY_RST, 1);
-}
-
-static const struct fec_platform_data mx53_smd_fec_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-
-static inline void mx53_smd_ahci_pwr_on(void)
-{
-        int ret;
-
-        /* Enable SATA PWR */
-        ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
-                        GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
-        if (ret) {
-                pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
-                return;
-        }
-}
-
-void __init imx53_smd_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
-                                         ARRAY_SIZE(mx53_smd_pads));
-}
-
-static void __init mx53_smd_board_init(void)
-{
-        imx53_soc_init();
-        imx53_smd_common_init();
-
-        mx53_smd_init_uart();
-        mx53_smd_fec_reset();
-        imx53_add_fec(&mx53_smd_fec_data);
-        imx53_add_imx2_wdt(0);
-        imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
-        imx53_add_sdhci_esdhc_imx(0, NULL);
-        imx53_add_sdhci_esdhc_imx(1, NULL);
-        imx53_add_sdhci_esdhc_imx(2, NULL);
-        mx53_smd_ahci_pwr_on();
-        imx53_add_ahci_imx();
-}
-
-static void __init mx53_smd_timer_init(void)
-{
-        mx53_clocks_init(32768, 24000000, 22579200, 0);
-}
-
-static struct sys_timer mx53_smd_timer = {
-        .init   = mx53_smd_timer_init,
-};
-
-MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
-        .map_io = mx53_map_io,
-        .init_early = imx53_init_early,
-        .init_irq = mx53_init_irq,
-        .handle_irq = imx53_handle_irq,
-        .timer = &mx53_smd_timer,
-        .init_machine = mx53_smd_board_init,
-        .init_late      = imx53_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 52d8f534be10..acb0aadb4255 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
         .script_addrs = &imx51_sdma_script,
 };
 
-static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
-        .ap_2_ap_addr = 642,
-        .app_2_mcu_addr = 683,
-        .mcu_2_app_addr = 747,
-        .uart_2_mcu_addr = 817,
-        .shp_2_mcu_addr = 891,
-        .mcu_2_shp_addr = 960,
-        .uartsh_2_mcu_addr = 1032,
-        .spdif_2_mcu_addr = 1100,
-        .mcu_2_spdif_addr = 1134,
-        .firi_2_mcu_addr = 1193,
-        .mcu_2_firi_addr = 1290,
-};
-
-static struct sdma_platform_data imx53_sdma_pdata __initdata = {
-        .fw_name = "sdma-imx53.bin",
-        .script_addrs = &imx53_sdma_script,
-};
-
 static const struct resource imx50_audmux_res[] __initconst = {
         DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
 };
@@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
         DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
 };
 
-static const struct resource imx53_audmux_res[] __initconst = {
-        DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
-};
-
 void __init imx50_soc_init(void)
 {
         /* i.mx50 has the i.mx35 type gpio */
@@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
                                         ARRAY_SIZE(imx51_audmux_res));
 }
 
-void __init imx53_soc_init(void)
-{
-        /* i.mx53 has the i.mx35 type gpio */
-        mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-        mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
-
-        pinctrl_provide_dummies();
-        /* i.mx53 has the i.mx35 type sdma */
-        imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
-
-        /* Setup AIPS registers */
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
-        imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
-
-        /* i.mx53 has the i.mx31 type audmux */
-        platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
-                                        ARRAY_SIZE(imx53_audmux_res));
-}
-
 void __init imx51_init_late(void)
 {
         mx51_neon_fixup();
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
deleted file mode 100644
index ee870c49bc63..000000000000
--- a/arch/arm/mach-imx/mx51_efika.c
+++ /dev/null
@@ -1,633 +0,0 @@
-/*
- * based on code from the following
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
- * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/input.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13892.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/consumer.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx51.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <mach/ulpi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include "devices-imx51.h"
-#include "efika.h"
-#include "cpu_op-mx51.h"
-
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-
-#define EFIKAMX_USB_HUB_RESET   IMX_GPIO_NR(1, 5)
-#define EFIKAMX_USBH1_STP       IMX_GPIO_NR(1, 27)
-
-#define EFIKAMX_SPI_CS0         IMX_GPIO_NR(4, 24)
-#define EFIKAMX_SPI_CS1         IMX_GPIO_NR(4, 25)
-
-#define EFIKAMX_PMIC            IMX_GPIO_NR(1, 6)
-
-static iomux_v3_cfg_t mx51efika_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-
-        /* SD/MMC WP/CD */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        MX51_PAD_GPIO1_7__SD2_WP,
-        MX51_PAD_GPIO1_8__SD2_CD,
-
-        /* spi */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_GPIO1_6__GPIO1_6,
-
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-
-        /* USB HUB RESET */
-        MX51_PAD_GPIO1_5__GPIO1_5,
-
-        /* WLAN */
-        MX51_PAD_EIM_A22__GPIO2_16,
-        MX51_PAD_EIM_A16__GPIO2_10,
-
-        /* USB PHY RESET */
-        MX51_PAD_EIM_D27__GPIO2_9,
-};
-
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* This function is board specific as the bit mask for the plldiv will also
- * be different for other Freescale SoCs, thus a common bitmask is not
- * possible and cannot get place in /plat-mxc/ehci.c.
- */
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init   = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *socregs_base;
-
-        mxc_iomux_v3_setup_pad(usbh1gpio);
-        gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
-        gpio_direction_output(EFIKAMX_USBH1_STP, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USBH1_STP, 1);
-        msleep(1);
-
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
-
-        /* The clock for the USBH1 ULPI port will come externally */
-        /* from the PHY. */
-        v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                        socregs_base + MX51_USB_CTRL_1_OFFSET);
-
-        iounmap(usb_base);
-
-        gpio_free(EFIKAMX_USBH1_STP);
-        mxc_iomux_v3_setup_pad(usbh1stp);
-
-        mdelay(10);
-
-        return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
-}
-
-static struct mxc_usbh_platform_data usbh1_config __initdata = {
-        .init   = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static void mx51_efika_hubreset(void)
-{
-        gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
-        gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
-}
-
-static void __init mx51_efika_usb(void)
-{
-        mx51_efika_hubreset();
-
-        /* pulling it low, means no USB at all... */
-        gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
-        gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
-        msleep(1);
-        gpio_set_value(EFIKA_USB_PHY_RESET, 1);
-
-        usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
-                        ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
-
-        imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        if (usbh1_config.otg)
-                imx51_add_mxc_ehci_hs(1, &usbh1_config);
-}
-
-static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
-        {
-         .name = "u-boot",
-         .offset = 0,
-         .size = SZ_256K,
-        },
-        {
-          .name = "config",
-          .offset = MTDPART_OFS_APPEND,
-          .size = SZ_64K,
-        },
-};
-
-static struct flash_platform_data mx51_efika_spi_flash_data = {
-        .name           = "spi_flash",
-        .parts          = mx51_efika_spi_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
-        .type           = "sst25vf032b",
-};
-
-static struct regulator_consumer_supply sw1_consumers[] = {
-        {
-                .supply = "cpu_vcc",
-        }
-};
-
-static struct regulator_consumer_supply vdig_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDA", "1-000a"),
-        REGULATOR_SUPPLY("VDDD", "1-000a"),
-};
-
-static struct regulator_consumer_supply vvideo_consumers[] = {
-        /* sgtl5000 */
-        REGULATOR_SUPPLY("VDDIO", "1-000a"),
-};
-
-static struct regulator_consumer_supply vsd_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
-        REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
-};
-
-static struct regulator_consumer_supply pwgt1_consumer[] = {
-        {
-                .supply = "pwgt1",
-        }
-};
-
-static struct regulator_consumer_supply pwgt2_consumer[] = {
-        {
-                .supply = "pwgt2",
-        }
-};
-
-static struct regulator_consumer_supply coincell_consumer[] = {
-        {
-                .supply = "coincell",
-        }
-};
-
-static struct regulator_init_data sw1_init = {
-        .constraints = {
-                .name = "SW1",
-                .min_uV = 600000,
-                .max_uV = 1375000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .valid_modes_mask = 0,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 850000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
-        .consumer_supplies = sw1_consumers,
-};
-
-static struct regulator_init_data sw2_init = {
-        .constraints = {
-                .name = "SW2",
-                .min_uV = 900000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-                .state_mem = {
-                        .uV = 950000,
-                        .mode = REGULATOR_MODE_NORMAL,
-                        .enabled = 1,
-                },
-        }
-};
-
-static struct regulator_init_data sw3_init = {
-        .constraints = {
-                .name = "SW3",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data sw4_init = {
-        .constraints = {
-                .name = "SW4",
-                .min_uV = 1100000,
-                .max_uV = 1850000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on = 1,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data viohi_init = {
-        .constraints = {
-                .name = "VIOHI",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb_init = {
-        .constraints = {
-                .name = "VUSB",
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data swbst_init = {
-        .constraints = {
-                .name = "SWBST",
-        }
-};
-
-static struct regulator_init_data vdig_init = {
-        .constraints = {
-                .name = "VDIG",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
-        .consumer_supplies = vdig_consumers,
-};
-
-static struct regulator_init_data vpll_init = {
-        .constraints = {
-                .name = "VPLL",
-                .min_uV = 1050000,
-                .max_uV = 1800000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vusb2_init = {
-        .constraints = {
-                .name = "VUSB2",
-                .min_uV = 2400000,
-                .max_uV = 2775000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vvideo_init = {
-        .constraints = {
-                .name = "VVIDEO",
-                .min_uV = 2775000,
-                .max_uV = 2775000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .apply_uV = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
-        .consumer_supplies = vvideo_consumers,
-};
-
-static struct regulator_init_data vaudio_init = {
-        .constraints = {
-                .name = "VAUDIO",
-                .min_uV = 2300000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vsd_init = {
-        .constraints = {
-                .name = "VSD",
-                .min_uV = 1800000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE,
-                .boot_on = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
-        .consumer_supplies = vsd_consumers,
-};
-
-static struct regulator_init_data vcam_init = {
-        .constraints = {
-                .name = "VCAM",
-                .min_uV = 2500000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
-                .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
-                .boot_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen1_init = {
-        .constraints = {
-                .name = "VGEN1",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen2_init = {
-        .constraints = {
-                .name = "VGEN2",
-                .min_uV = 1200000,
-                .max_uV = 3150000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data vgen3_init = {
-        .constraints = {
-                .name = "VGEN3",
-                .min_uV = 1800000,
-                .max_uV = 2900000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-                .boot_on = 1,
-                .always_on = 1,
-        }
-};
-
-static struct regulator_init_data gpo1_init = {
-        .constraints = {
-                .name = "GPO1",
-        }
-};
-
-static struct regulator_init_data gpo2_init = {
-        .constraints = {
-                .name = "GPO2",
-        }
-};
-
-static struct regulator_init_data gpo3_init = {
-        .constraints = {
-                .name = "GPO3",
-        }
-};
-
-static struct regulator_init_data gpo4_init = {
-        .constraints = {
-                .name = "GPO4",
-        }
-};
-
-static struct regulator_init_data pwgt1_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
-        .consumer_supplies = pwgt1_consumer,
-};
-
-static struct regulator_init_data pwgt2_init = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
-        .consumer_supplies = pwgt2_consumer,
-};
-
-static struct regulator_init_data vcoincell_init = {
-        .constraints = {
-                .name = "COINCELL",
-                .min_uV = 3000000,
-                .max_uV = 3000000,
-                .valid_ops_mask =
-                        REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
-        .consumer_supplies = coincell_consumer,
-};
-
-static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
-        { .id = MC13892_SW1,            .init_data =  &sw1_init },
-        { .id = MC13892_SW2,            .init_data =  &sw2_init },
-        { .id = MC13892_SW3,            .init_data =  &sw3_init },
-        { .id = MC13892_SW4,            .init_data =  &sw4_init },
-        { .id = MC13892_SWBST,          .init_data =  &swbst_init },
-        { .id = MC13892_VIOHI,          .init_data =  &viohi_init },
-        { .id = MC13892_VPLL,           .init_data =  &vpll_init },
-        { .id = MC13892_VDIG,           .init_data =  &vdig_init },
-        { .id = MC13892_VSD,            .init_data =  &vsd_init },
-        { .id = MC13892_VUSB2,          .init_data =  &vusb2_init },
-        { .id = MC13892_VVIDEO,         .init_data =  &vvideo_init },
-        { .id = MC13892_VAUDIO,         .init_data =  &vaudio_init },
-        { .id = MC13892_VCAM,           .init_data =  &vcam_init },
-        { .id = MC13892_VGEN1,          .init_data =  &vgen1_init },
-        { .id = MC13892_VGEN2,          .init_data =  &vgen2_init },
-        { .id = MC13892_VGEN3,          .init_data =  &vgen3_init },
-        { .id = MC13892_VUSB,           .init_data =  &vusb_init },
-        { .id = MC13892_GPO1,           .init_data =  &gpo1_init },
-        { .id = MC13892_GPO2,           .init_data =  &gpo2_init },
-        { .id = MC13892_GPO3,           .init_data =  &gpo3_init },
-        { .id = MC13892_GPO4,           .init_data =  &gpo4_init },
-        { .id = MC13892_PWGT1SPI,       .init_data = &pwgt1_init },
-        { .id = MC13892_PWGT2SPI,       .init_data = &pwgt2_init },
-        { .id = MC13892_VCOINCELL,      .init_data = &vcoincell_init },
-};
-
-static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
-        .flags = MC13XXX_USE_RTC,
-        .regulators = {
-                .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-                .regulators = mx51_efika_regulators,
-        },
-};
-
-static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
-        {
-                .modalias = "m25p80",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .platform_data = &mx51_efika_spi_flash_data,
-                .irq = -1,
-        },
-        {
-                .modalias = "mc13892",
-                .max_speed_hz = 1000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .platform_data = &mx51_efika_mc13892_data,
-                /* irq number is run-time assigned */
-        },
-};
-
-static int mx51_efika_spi_cs[] = {
-        EFIKAMX_SPI_CS0,
-        EFIKAMX_SPI_CS1,
-};
-
-static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
-        .chipselect     = mx51_efika_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
-};
-
-void __init efika_board_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
-                                        ARRAY_SIZE(mx51efika_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        mx51_efika_usb();
-
-        /* FIXME: comes from original code. check this. */
-        if (mx51_revision() < IMX_CHIP_REVISION_2_0)
-                sw2_init.constraints.state_mem.uV = 1100000;
-        else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
-                sw2_init.constraints.state_mem.uV = 1250000;
-                sw1_init.constraints.state_mem.uV = 1000000;
-        }
-        if (machine_is_mx51_efikasb())
-                vgen1_init.constraints.max_uV = 1200000;
-
-        gpio_request(EFIKAMX_PMIC, "pmic irq");
-        gpio_direction_input(EFIKAMX_PMIC);
-        mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
-        spi_register_board_info(mx51_efika_spi_board_info,
-                ARRAY_SIZE(mx51_efika_spi_board_info));
-        imx51_add_ecspi(0, &mx51_efika_spi_pdata);
-
-        imx51_add_pata_imx();
-
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-}
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c2ce3d05b044..3a3768c7a191 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -100,7 +100,7 @@ static int __init mmp2_init(void)
 {
         if (cpu_is_mmp2()) {
 #ifdef CONFIG_CACHE_TAUROS2
-                tauros2_init();
+                tauros2_init(0);
 #endif
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(mmp2_addr_map);
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 7d84521bb715..8b1e16fbb7a5 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/platform_device.h>
 
+#include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
 #include <mach/regs-apbc.h>
@@ -83,6 +84,9 @@ void __init pxa910_init_irq(void)
 static int __init pxa910_init(void)
 {
         if (cpu_is_pxa910()) {
+#ifdef CONFIG_CACHE_TAUROS2
+                tauros2_init(0);
+#endif
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa910_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 1cd40ad301d3..b2740c800e8c 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -38,8 +38,6 @@ config ARCH_QSD8X50
 
 config ARCH_MSM8X60
         bool "MSM8X60"
-        select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
-                                  && !MACH_MSM8X60_FFA)
         select ARCH_MSM_SCORPIONMP
         select ARM_GIC
         select CPU_V7
@@ -47,16 +45,17 @@ config ARCH_MSM8X60
         select GPIO_MSM_V2
         select MSM_GPIOMUX
         select MSM_SCM if SMP
+        select USE_OF
 
 config ARCH_MSM8960
         bool "MSM8960"
         select ARCH_MSM_SCORPIONMP
-        select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3)
         select ARM_GIC
         select CPU_V7
         select MSM_V2_TLMM
         select MSM_GPIOMUX
         select MSM_SCM if SMP
+        select USE_OF
 
 endchoice
 
@@ -112,42 +111,6 @@ config MACH_QSD8X50A_ST1_5
         help
           Support for the Qualcomm ST1.5.
 
-config MACH_MSM8X60_RUMI3
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 RUMI3"
-        help
-          Support for the Qualcomm MSM8x60 RUMI3 emulator.
-
-config MACH_MSM8X60_SURF
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 SURF"
-        help
-          Support for the Qualcomm MSM8x60 SURF eval board.
-
-config MACH_MSM8X60_SIM
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 Simulator"
-        help
-          Support for the Qualcomm MSM8x60 simulator.
-
-config MACH_MSM8X60_FFA
-        depends on ARCH_MSM8X60
-        bool "MSM8x60 FFA"
-        help
-          Support for the Qualcomm MSM8x60 FFA eval board.
-
-config MACH_MSM8960_SIM
-        depends on ARCH_MSM8960
-        bool "MSM8960 Simulator"
-        help
-          Support for the Qualcomm MSM8960 simulator.
-
-config MACH_MSM8960_RUMI3
-        depends on ARCH_MSM8960
-        bool "MSM8960 RUMI3"
-        help
-          Support for the Qualcomm MSM8960 RUMI3 emulator.
-
 endmenu
 
 config MSM_SMD_PKG3
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 6a6c197212eb..17519faf082f 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -25,8 +25,8 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o b
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
-obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
-obj-$(CONFIG_ARCH_MSM8960) += board-msm8960.o devices-msm8960.o
+obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
+obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
 
 obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
 obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
diff --git a/arch/arm/mach-msm/Makefile.boot b/arch/arm/mach-msm/Makefile.boot
index 9b803a578b4d..f7d6ae9c3487 100644
--- a/arch/arm/mach-msm/Makefile.boot
+++ b/arch/arm/mach-msm/Makefile.boot
@@ -1,3 +1,6 @@
   zreladdr-y            += 0x10008000
 params_phys-y           := 0x10000100
 initrd_phys-y           := 0x10800000
+
+dtb-$(CONFIG_ARCH_MSM8X60) += msm8660-surf.dtb
+dtb-$(CONFIG_ARCH_MSM8960) += msm8960-cdp.dtb
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
new file mode 100644
index 000000000000..f77f57f39104
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -0,0 +1,63 @@
+/* Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/board.h>
+#include "common.h"
+
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+
+static void __init msm8x60_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+
+static void __init msm8x60_init_late(void)
+{
+        smd_debugfs_init();
+}
+
+static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
+        {}
+};
+
+static void __init msm8x60_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        msm_auxdata_lookup, NULL);
+}
+
+static const char *msm8x60_fluid_match[] __initdata = {
+        "qcom,msm8660-fluid",
+        "qcom,msm8660-surf",
+        NULL
+};
+
+DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .map_io = msm_map_msm8x60_io,
+        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
+        .init_machine = msm8x60_dt_init,
+        .init_late = msm8x60_init_late,
+        .timer = &msm_dt_timer,
+        .dt_compat = msm8x60_fluid_match,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
new file mode 100644
index 000000000000..8df99b8f3c92
--- /dev/null
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -0,0 +1,49 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+
+static const struct of_device_id msm_dt_gic_match[] __initconst = {
+        { .compatible = "qcom,msm-qgic2", .data = gic_of_init },
+        { }
+};
+
+static void __init msm_dt_init_irq(void)
+{
+        of_irq_init(msm_dt_gic_match);
+}
+
+static void __init msm_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const msm8960_dt_match[] __initconst = {
+        "qcom,msm8960-cdp",
+        NULL
+};
+
+DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
+        .map_io = msm_map_msm8960_io,
+        .init_irq = msm_dt_init_irq,
+        .timer = &msm_dt_timer,
+        .init_machine = msm_dt_init,
+        .dt_compat = msm8960_dt_match,
+        .handle_irq = gic_handle_irq,
+MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 4fa3e99d9a62..6ce542e2e21c 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -36,6 +36,7 @@
 #include <linux/mtd/partitions.h>
 
 #include "devices.h"
+#include "common.h"
 
 static struct resource smc91x_resources[] = {
         [0] = {
@@ -66,8 +67,6 @@ static struct platform_device *devices[] __initdata = {
         &smc91x_device,
 };
 
-extern struct sys_timer msm_timer;
-
 static void __init halibut_init_early(void)
 {
         arch_ioremap_caller = __msm_ioremap_caller;
@@ -107,5 +106,5 @@ MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
         .init_irq       = halibut_init_irq,
         .init_machine   = halibut_init,
         .init_late      = halibut_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index a5001378135d..effa6f4336c7 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -38,8 +38,7 @@
 #include "devices.h"
 #include "gpiomux.h"
 #include "proc_comm.h"
-
-extern struct sys_timer msm_timer;
+#include "common.h"
 
 static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
                 struct meminfo *mi)
@@ -132,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 
 MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
@@ -143,7 +142,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
 
 MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
@@ -154,5 +153,5 @@ MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
         .init_irq = msm7x30_init_irq,
         .init_machine = msm7x30_init,
         .init_late = msm7x30_init_late,
-        .timer = &msm_timer,
+        .timer = &msm7x30_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
deleted file mode 100644
index 65f4a1daa2e5..000000000000
--- a/arch/arm/mach-msm/board-msm8960.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- *
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/clkdev.h>
-#include <linux/memblock.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include "devices.h"
-
-static void __init msm8960_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-
-static void __init msm8960_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-
-static void __init msm8960_map_io(void)
-{
-        msm_map_msm8960_io();
-}
-
-static void __init msm8960_init_irq(void)
-{
-        unsigned int i;
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                 (void *)MSM_QGIC_CPU_BASE);
-
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
-        if (machine_is_msm8960_rumi3())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-
-        /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
-         * as they are configured as level, which does not play nice with
-         * handle_percpu_irq.
-         */
-        for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
-                if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        irq_set_handler(i, handle_percpu_irq);
-        }
-}
-
-static struct platform_device *sim_devices[] __initdata = {
-        &msm8960_device_uart_gsbi2,
-};
-
-static struct platform_device *rumi3_devices[] __initdata = {
-        &msm8960_device_uart_gsbi5,
-};
-
-static void __init msm8960_sim_init(void)
-{
-        platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
-}
-
-static void __init msm8960_rumi3_init(void)
-{
-        platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
-}
-
-static void __init msm8960_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_sim_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
-
-MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
-        .fixup = msm8960_fixup,
-        .reserve = msm8960_reserve,
-        .map_io = msm8960_map_io,
-        .init_irq = msm8960_init_irq,
-        .timer = &msm_timer,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8960_rumi3_init,
-        .init_late = msm8960_init_late,
-MACHINE_END
-
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
deleted file mode 100644
index 06003b4ccb10..000000000000
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/memblock.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-static void __init msm8x60_fixup(struct tag *tag, char **cmdline,
-                struct meminfo *mi)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM &&
-                                tag->u.mem.start == 0x40200000) {
-                        tag->u.mem.start = 0x40000000;
-                        tag->u.mem.size += SZ_2M;
-                }
-}
-
-static void __init msm8x60_reserve(void)
-{
-        memblock_remove(0x40000000, SZ_2M);
-}
-
-static void __init msm8x60_map_io(void)
-{
-        msm_map_msm8x60_io();
-}
-
-#ifdef CONFIG_OF
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
-        {}
-};
-#endif
-
-static void __init msm8x60_init_irq(void)
-{
-        if (!of_have_populated_dt())
-                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                         (void *)MSM_QGIC_CPU_BASE);
-#ifdef CONFIG_OF
-        else
-                of_irq_init(msm_dt_gic_match);
-#endif
-
-        /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-        writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
-        /* RUMI does not adhere to GIC spec by enabling STIs by default.
-         * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
-         */
-        if (!machine_is_msm8x60_sim())
-                writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
-}
-
-static void __init msm8x60_init(void)
-{
-}
-
-static void __init msm8x60_init_late(void)
-{
-        smd_debugfs_init();
-}
-
-#ifdef CONFIG_OF
-static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
-        {}
-};
-
-static void __init msm8x60_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table,
-                        msm_auxdata_lookup, NULL);
-}
-
-static const char *msm8x60_fluid_match[] __initdata = {
-        "qcom,msm8660-fluid",
-        "qcom,msm8660-surf",
-        NULL
-};
-#endif /* CONFIG_OF */
-
-MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
-        .fixup = msm8x60_fixup,
-        .reserve = msm8x60_reserve,
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .handle_irq = gic_handle_irq,
-        .init_machine = msm8x60_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-MACHINE_END
-
-#ifdef CONFIG_OF
-/* TODO: General device tree support for all MSM. */
-DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
-        .map_io = msm8x60_map_io,
-        .init_irq = msm8x60_init_irq,
-        .init_machine = msm8x60_dt_init,
-        .init_late = msm8x60_init_late,
-        .timer = &msm_timer,
-        .dt_compat = msm8x60_fluid_match,
-MACHINE_END
-#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index c8fe0edb9761..b16b71abf5f6 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -35,8 +35,7 @@
 #include <mach/mmc.h>
 
 #include "devices.h"
-
-extern struct sys_timer msm_timer;
+#include "common.h"
 
 static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
 static const unsigned        qsd8x50_surf_smc91x_gpio __initdata = 156;
@@ -201,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
         .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
 
 MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
@@ -210,5 +209,5 @@ MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
         .init_irq = qsd8x50_init_irq,
         .init_machine = qsd8x50_init,
         .init_late = qsd8x50_init_late,
-        .timer = &msm_timer,
+        .timer = &qsd8x50_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index bbe13f12fa01..4ba0800e243e 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -31,6 +31,7 @@
 
 #include "devices.h"
 #include "board-trout.h"
+#include "common.h"
 
 extern int trout_init_mmc(unsigned int);
 
@@ -42,8 +43,6 @@ static struct platform_device *devices[] __initdata = {
         &msm_device_i2c,
 };
 
-extern struct sys_timer msm_timer;
-
 static void __init trout_init_early(void)
 {
         arch_ioremap_caller = __msm_ioremap_caller;
@@ -111,5 +110,5 @@ MACHINE_START(TROUT, "HTC Dream")
         .init_irq       = trout_init_irq,
         .init_machine   = trout_init,
         .init_late      = trout_init_late,
-        .timer          = &msm_timer,
+        .timer          = &msm7x01_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
new file mode 100644
index 000000000000..d68e5d7854f5
--- /dev/null
+++ b/arch/arm/mach-msm/common.h
@@ -0,0 +1,30 @@
+/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_COMMON_H
+#define __MACH_COMMON_H
+
+extern struct sys_timer msm7x01_timer;
+extern struct sys_timer msm7x30_timer;
+extern struct sys_timer msm_dt_timer;
+extern struct sys_timer qsd8x50_timer;
+
+extern void msm_map_common_io(void);
+extern void msm_map_msm7x30_io(void);
+extern void msm_map_msm8x60_io(void);
+extern void msm_map_msm8960_io(void);
+extern void msm_map_qsd8x50_io(void);
+
+extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+                                          unsigned int mtype, void *caller);
+
+
+#endif
diff --git a/arch/arm/mach-msm/devices-msm8960.c b/arch/arm/mach-msm/devices-msm8960.c
deleted file mode 100644
index d9e1f26475de..000000000000
--- a/arch/arm/mach-msm/devices-msm8960.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-
-#include <linux/dma-mapping.h>
-#include <mach/irqs-8960.h>
-#include <mach/board.h>
-
-#include "devices.h"
-
-#define MSM_GSBI2_PHYS          0x16100000
-#define MSM_UART2DM_PHYS        (MSM_GSBI2_PHYS + 0x40000)
-
-#define MSM_GSBI5_PHYS          0x16400000
-#define MSM_UART5DM_PHYS        (MSM_GSBI5_PHYS + 0x40000)
-
-static struct resource resources_uart_gsbi2[] = {
-        {
-                .start  = GSBI2_UARTDM_IRQ,
-                .end    = GSBI2_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART2DM_PHYS,
-                .end    = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI2_PHYS,
-                .end    = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device msm8960_device_uart_gsbi2 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi2),
-        .resource       = resources_uart_gsbi2,
-};
-
-static struct resource resources_uart_gsbi5[] = {
-        {
-                .start  = GSBI5_UARTDM_IRQ,
-                .end    = GSBI5_UARTDM_IRQ,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = MSM_UART5DM_PHYS,
-                .end    = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
-                .name   = "uart_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MSM_GSBI5_PHYS,
-                .end    = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
-                .name   = "gsbi_resource",
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-struct platform_device msm8960_device_uart_gsbi5 = {
-        .name   = "msm_serial",
-        .id     = 0,
-        .num_resources  = ARRAY_SIZE(resources_uart_gsbi5),
-        .resource       = resources_uart_gsbi5,
-};
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 5a0811a4c851..0a0c393d8e31 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -24,12 +24,9 @@
 
 struct clk_lookup;
 
-extern struct sys_timer msm_timer;
-
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 
 void __init msm_add_devices(void);
-void __init msm_map_common_io(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
 void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 6c4046c21296..67dc0e98b958 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -105,11 +105,4 @@
 #define MSM_AD5_PHYS          0xAC000000
 #define MSM_AD5_SIZE          (SZ_1M*13)
 
-#ifndef __ASSEMBLY__
-
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
-                                          unsigned int mtype, void *caller);
-
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index f944fe65a657..198202c267c8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -100,8 +100,4 @@
 #define MSM_HSUSB_PHYS        0xA3600000
 #define MSM_HSUSB_SIZE        SZ_1K
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm7x30_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index facf434d09be..9819a556acae 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -50,8 +50,4 @@
 #define MSM_DEBUG_UART_PHYS     0x16440000
 #endif
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8960_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index da77cc1d545d..0faa894729b7 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -122,8 +122,4 @@
 #define MSM_SDC4_PHYS          0xA0600000
 #define MSM_SDC4_SIZE          SZ_4K
 
-#ifndef __ASSEMBLY__
-extern void msm_map_qsd8x50_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 21a2a8859a9a..c6d38f1d0c98 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -67,8 +67,4 @@
 #define MSM_DEBUG_UART_PHYS     0x19C40000
 #endif
 
-#ifndef __ASSEMBLY__
-extern void msm_map_msm8x60_io(void);
-#endif
-
 #endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3cb4f4c35710..3854f6f20ce2 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -29,6 +29,8 @@
 
 #include <mach/board.h>
 
+#include "common.h"
+
 #define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) {                          \
                 .virtual = (unsigned long) MSM_##name##_BASE, \
                 .pfn = __phys_to_pfn(chip##_##name##_PHYS), \
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index e012dc8391cf..2d791e6b4ad1 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -22,17 +22,12 @@
 #include <asm/mach-types.h>
 #include <asm/smp_plat.h>
 
-#include <mach/msm_iomap.h>
-
 #include "scm-boot.h"
 
 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
 #define SCSS_CPU1CORE_RESET 0xD80
 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
 
-/* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
-#define GIC_PPI_EDGE_MASK 0xFFFFD7FF
-
 extern void msm_secondary_startup(void);
 /*
  * control for which core is the next to come out of the secondary
@@ -50,9 +45,6 @@ static inline int get_core_count(void)
 
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
-        /* Configure edge-triggered PPIs */
-        writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
-
         /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 004f93515a4e..476549a8a709 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,7 +1,7 @@
 /*
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -20,15 +20,16 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
 
-#include <mach/msm_iomap.h>
-#include <mach/cpu.h>
-#include <mach/board.h>
+#include "common.h"
 
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
@@ -36,7 +37,6 @@
 #define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
 #define TIMER_ENABLE_EN                 BIT(0)
 #define TIMER_CLEAR             0x000C
-#define DGT_CLK_CTL             0x0034
 #define DGT_CLK_CTL_DIV_4       0x3
 
 #define GPT_HZ 32768
@@ -151,7 +151,7 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
 
         *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
         clockevents_register_device(evt);
-        enable_percpu_irq(evt->irq, 0);
+        enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
         return 0;
 }
 
@@ -172,44 +172,21 @@ static notrace u32 msm_sched_clock_read(void)
         return msm_clocksource.read(&msm_clocksource);
 }
 
-static void __init msm_timer_init(void)
+static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
+                                  bool percpu)
 {
         struct clock_event_device *ce = &msm_clockevent;
         struct clocksource *cs = &msm_clocksource;
         int res;
-        u32 dgt_hz;
-
-        if (cpu_is_msm7x01()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
-                cs->read = msm_read_timer_count_shift;
-                cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
-        } else if (cpu_is_msm7x30()) {
-                event_base = MSM_CSR_BASE + 0x04;
-                source_base = MSM_CSR_BASE + 0x24;
-                dgt_hz = 24576000 / 4;
-        } else if (cpu_is_qsd8x50()) {
-                event_base = MSM_CSR_BASE;
-                source_base = MSM_CSR_BASE + 0x10;
-                dgt_hz = 19200000 / 4;
-        } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                event_base = MSM_TMR_BASE + 0x04;
-                /* Use CPU0's timer as the global clock source. */
-                source_base = MSM_TMR0_BASE + 0x24;
-                dgt_hz = 27000000 / 4;
-                writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
-        } else
-                BUG();
 
         writel_relaxed(0, event_base + TIMER_ENABLE);
         writel_relaxed(0, event_base + TIMER_CLEAR);
         writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
         ce->cpumask = cpumask_of(0);
+        ce->irq = irq;
 
-        ce->irq = INT_GP_TIMER_EXP;
         clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-        if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+        if (percpu) {
                 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
                 if (!msm_evt.percpu_evt) {
                         pr_err("memory allocation failed for %s\n", ce->name);
@@ -219,7 +196,7 @@ static void __init msm_timer_init(void)
                 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
                                          ce->name, msm_evt.percpu_evt);
                 if (!res) {
-                        enable_percpu_irq(ce->irq, 0);
+                        enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
 #ifdef CONFIG_LOCAL_TIMERS
                         local_timer_register(&msm_local_timer_ops);
 #endif
@@ -238,10 +215,143 @@ err:
         res = clocksource_register_hz(cs, dgt_hz);
         if (res)
                 pr_err("clocksource_register failed\n");
-        setup_sched_clock(msm_sched_clock_read,
-                        cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz);
+        setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
 }
 
-struct sys_timer msm_timer = {
-        .init = msm_timer_init
+#ifdef CONFIG_OF
+static const struct of_device_id msm_dgt_match[] __initconst = {
+        { .compatible = "qcom,msm-dgt" },
+        { },
+};
+
+static const struct of_device_id msm_gpt_match[] __initconst = {
+        { .compatible = "qcom,msm-gpt" },
+        { },
+};
+
+static void __init msm_dt_timer_init(void)
+{
+        struct device_node *np;
+        u32 freq;
+        int irq;
+        struct resource res;
+        u32 percpu_offset;
+        void __iomem *dgt_clk_ctl;
+
+        np = of_find_matching_node(NULL, msm_gpt_match);
+        if (!np) {
+                pr_err("Can't find GPT DT node\n");
+                return;
+        }
+
+        event_base = of_iomap(np, 0);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return;
+        }
+
+        irq = irq_of_parse_and_map(np, 0);
+        if (irq <= 0) {
+                pr_err("Can't get irq\n");
+                return;
+        }
+        of_node_put(np);
+
+        np = of_find_matching_node(NULL, msm_dgt_match);
+        if (!np) {
+                pr_err("Can't find DGT DT node\n");
+                return;
+        }
+
+        if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
+                percpu_offset = 0;
+
+        if (of_address_to_resource(np, 0, &res)) {
+                pr_err("Failed to parse DGT resource\n");
+                return;
+        }
+
+        source_base = ioremap(res.start + percpu_offset, resource_size(&res));
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return;
+        }
+
+        if (!of_address_to_resource(np, 1, &res)) {
+                dgt_clk_ctl = ioremap(res.start + percpu_offset,
+                                      resource_size(&res));
+                if (!dgt_clk_ctl) {
+                        pr_err("Failed to map DGT control base\n");
+                        return;
+                }
+                writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
+                iounmap(dgt_clk_ctl);
+        }
+
+        if (of_property_read_u32(np, "clock-frequency", &freq)) {
+                pr_err("Unknown frequency\n");
+                return;
+        }
+        of_node_put(np);
+
+        msm_timer_init(freq, 32, irq, !!percpu_offset);
+}
+
+struct sys_timer msm_dt_timer = {
+        .init = msm_dt_timer_init
+};
+#endif
+
+static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
+{
+        event_base = ioremap(event, SZ_64);
+        if (!event_base) {
+                pr_err("Failed to map event base\n");
+                return 1;
+        }
+        source_base = ioremap(source, SZ_64);
+        if (!source_base) {
+                pr_err("Failed to map source base\n");
+                return 1;
+        }
+        return 0;
+}
+
+static void __init msm7x01_timer_init(void)
+{
+        struct clocksource *cs = &msm_clocksource;
+
+        if (msm_timer_map(0xc0100000, 0xc0100010))
+                return;
+        cs->read = msm_read_timer_count_shift;
+        cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
+        /* 600 KHz */
+        msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
+                        false);
+}
+
+struct sys_timer msm7x01_timer = {
+        .init = msm7x01_timer_init
+};
+
+static void __init msm7x30_timer_init(void)
+{
+        if (msm_timer_map(0xc0100004, 0xc0100024))
+                return;
+        msm_timer_init(24576000 / 4, 32, 1, false);
+}
+
+struct sys_timer msm7x30_timer = {
+        .init = msm7x30_timer_init
+};
+
+static void __init qsd8x50_timer_init(void)
+{
+        if (msm_timer_map(0xAC100000, 0xAC100010))
+                return;
+        msm_timer_init(19200000 / 4, 32, 7, false);
+}
+
+struct sys_timer qsd8x50_timer = {
+        .init = qsd8x50_timer_init
 };
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 9a8bbda195b2..ecc431909d6f 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -1,7 +1,5 @@
 if ARCH_MXS
 
-source "arch/arm/mach-mxs/devices/Kconfig"
-
 config SOC_IMX23
         bool
         select ARM_AMBA
@@ -27,91 +25,4 @@ config MACH_MXS_DT
           Include support for Freescale MXS platforms(i.MX23 and i.MX28)
           using the device tree for discovery
 
-config MACH_STMP378X_DEVB
-        bool "Support STMP378x_devb Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for STMP378x-devb platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX23EVK
-        bool "Support MX23EVK Platform"
-        select SOC_IMX23
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX23EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MACH_MX28EVK
-        bool "Support MX28EVK Platform"
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        help
-          Include support for MX28EVK platform. This includes specific
-          configurations for the board and its peripherals.
-
-config MODULE_TX28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_PWM
-        select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-
-config MODULE_M28
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_FLEXCAN
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXSFB
-
-config MODULE_APX4
-        bool
-        select SOC_IMX28
-        select LEDS_GPIO_REGISTER
-        select MXS_HAVE_AMBA_DUART
-        select MXS_HAVE_PLATFORM_AUART
-        select MXS_HAVE_PLATFORM_FEC
-        select MXS_HAVE_PLATFORM_MXS_I2C
-        select MXS_HAVE_PLATFORM_MXS_MMC
-        select MXS_HAVE_PLATFORM_MXS_SAIF
-
-config MACH_TX28
-        bool "Ka-Ro TX28 module"
-        select MODULE_TX28
-
-config MACH_M28EVK
-        bool "Support DENX M28EVK Platform"
-        select MODULE_M28
-
-config MACH_APX4DEVKIT
-        bool "Support Bluegiga APX4 Development Kit"
-        select MODULE_APX4
-
 endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index fed3695a1339..3d3c8a973062 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,15 +1,6 @@
 # Common support
-obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
+obj-y := icoll.o ocotp.o system.o timer.o mm.o
 
 obj-$(CONFIG_PM) += pm.o
 
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
-obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
-obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
-obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
-obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
-obj-$(CONFIG_MACH_APX4DEVKIT) += mach-apx4devkit.o
-obj-$(CONFIG_MODULE_TX28) += module-tx28.o
-obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
-
-obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 4582999cf080..8bd23a8558db 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -5,6 +5,7 @@ dtb-y += imx23-evk.dtb \
          imx23-stmp378x_devb.dtb \
          imx28-apx4devkit.dtb \
          imx28-cfa10036.dtb \
+         imx28-cfa10049.dtb \
          imx28-evk.dtb \
          imx28-m28evk.dtb \
          imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
deleted file mode 100644
index 9ee5cede3d42..000000000000
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx23.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx23_add_duart(void)
-{
-        struct amba_device *d;
-
-        d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
-                                MX23_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx23_auart_data[] __initconst;
-#define mx23_add_auart(id)      mxs_add_auart(&mx23_auart_data[id])
-#define mx23_add_auart0()               mx23_add_auart(0)
-#define mx23_add_auart1()               mx23_add_auart(1)
-
-extern const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst;
-#define mx23_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx23_gpmi_nand_data)
-
-extern const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst;
-#define mx23_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx23_mxs_mmc_data[id], pdata)
-
-#define mx23_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX23_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
deleted file mode 100644
index fcab431060f4..000000000000
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-#include <linux/amba/bus.h>
-
-static inline int mx28_add_duart(void)
-{
-        struct amba_device *d;
-
-        d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
-                                MX28_INT_DUART, 0, 0, 0);
-        return IS_ERR(d) ? PTR_ERR(d) : 0;
-}
-
-extern const struct mxs_auart_data mx28_auart_data[] __initconst;
-#define mx28_add_auart(id)      mxs_add_auart(&mx28_auart_data[id])
-#define mx28_add_auart0()               mx28_add_auart(0)
-#define mx28_add_auart1()               mx28_add_auart(1)
-#define mx28_add_auart2()               mx28_add_auart(2)
-#define mx28_add_auart3()               mx28_add_auart(3)
-#define mx28_add_auart4()               mx28_add_auart(4)
-
-extern const struct mxs_fec_data mx28_fec_data[] __initconst;
-#define mx28_add_fec(id, pdata) \
-        mxs_add_fec(&mx28_fec_data[id], pdata)
-
-extern const struct mxs_flexcan_data mx28_flexcan_data[] __initconst;
-#define mx28_add_flexcan(id, pdata)     \
-        mxs_add_flexcan(&mx28_flexcan_data[id], pdata)
-#define mx28_add_flexcan0(pdata)        mx28_add_flexcan(0, pdata)
-#define mx28_add_flexcan1(pdata)        mx28_add_flexcan(1, pdata)
-
-extern const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst;
-#define mx28_add_gpmi_nand(pdata)       \
-        mxs_add_gpmi_nand(pdata, &mx28_gpmi_nand_data)
-
-extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
-#define mx28_add_mxs_i2c(id)            mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
-
-extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
-#define mx28_add_mxs_mmc(id, pdata) \
-        mxs_add_mxs_mmc(&mx28_mxs_mmc_data[id], pdata)
-
-#define mx28_add_mxs_pwm(id)            mxs_add_mxs_pwm(MX28_PWM_BASE_ADDR, id)
-
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata);
-
-extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id, pdata) \
-        mxs_add_saif(&mx28_saif_data[id], pdata)
-
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
deleted file mode 100644
index cf50b5a66dda..000000000000
--- a/arch/arm/mach-mxs/devices.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-
-struct platform_device *__init mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask)
-{
-        int ret = -ENOMEM;
-        struct platform_device *pdev;
-
-        pdev = platform_device_alloc(name, id);
-        if (!pdev)
-                goto err;
-
-        if (dmamask) {
-                /*
-                 * This memory isn't freed when the device is put,
-                 * I don't have a nice idea for that though.  Conceptually
-                 * dma_mask in struct device should not be a pointer.
-                 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
-                 */
-                pdev->dev.dma_mask =
-                        kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
-                if (!pdev->dev.dma_mask)
-                        /* ret is still -ENOMEM; */
-                        goto err;
-
-                *pdev->dev.dma_mask = dmamask;
-                pdev->dev.coherent_dma_mask = dmamask;
-        }
-
-        if (res) {
-                ret = platform_device_add_resources(pdev, res, num_resources);
-                if (ret)
-                        goto err;
-        }
-
-        if (data) {
-                ret = platform_device_add_data(pdev, data, size_data);
-                if (ret)
-                        goto err;
-        }
-
-        ret = platform_device_add(pdev);
-        if (ret) {
-err:
-                if (dmamask)
-                        kfree(pdev->dev.dma_mask);
-                platform_device_put(pdev);
-                return ERR_PTR(ret);
-        }
-
-        return pdev;
-}
-
-struct device mxs_apbh_bus = {
-        .init_name      = "mxs_apbh",
-        .parent         = &platform_bus,
-};
-
-static int __init mxs_device_init(void)
-{
-        return device_register(&mxs_apbh_bus);
-}
-core_initcall(mxs_device_init);
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
deleted file mode 100644
index 19659de1c4e8..000000000000
--- a/arch/arm/mach-mxs/devices/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
-config MXS_HAVE_AMBA_DUART
-        bool
-
-config MXS_HAVE_PLATFORM_AUART
-        bool
-
-config MXS_HAVE_PLATFORM_FEC
-        bool
-
-config MXS_HAVE_PLATFORM_FLEXCAN
-        select HAVE_CAN_FLEXCAN if CAN
-        bool
-
-config MXS_HAVE_PLATFORM_GPMI_NAND
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_I2C
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_MMC
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_PWM
-        bool
-
-config MXS_HAVE_PLATFORM_MXSFB
-        bool
-
-config MXS_HAVE_PLATFORM_MXS_SAIF
-        bool
-
-config MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
deleted file mode 100644
index 5f72d9787444..000000000000
--- a/arch/arm/mach-mxs/devices/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
-obj-y += platform-dma.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_GPMI_NAND) += platform-gpmi-nand.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_I2C) += platform-mxs-i2c.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_MMC) += platform-mxs-mmc.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_PWM) += platform-mxs-pwm.o
-obj-y += platform-gpio-mxs.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXSFB) += platform-mxsfb.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF) += platform-mxs-saif.o
-obj-$(CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX) += platform-rtc-stmp3xxx.o
diff --git a/arch/arm/mach-mxs/devices/platform-auart.c b/arch/arm/mach-mxs/devices/platform-auart.c
deleted file mode 100644
index 27608f5d2ac8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-auart.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_auart_data_entry_single(soc, _id, hwid)                     \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _AUART ## hwid ## _BASE_ADDR,          \
-                .irq = soc ## _INT_AUART ## hwid,                       \
-        }
-
-#define mxs_auart_data_entry(soc, _id, hwid)                            \
-        [_id] = mxs_auart_data_entry_single(soc, _id, hwid)
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_auart_data mx23_auart_data[] __initconst = {
-#define mx23_auart_data_entry(_id, hwid)                                \
-        mxs_auart_data_entry(MX23, _id, hwid)
-        mx23_auart_data_entry(0, 1),
-        mx23_auart_data_entry(1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_auart_data mx28_auart_data[] __initconst = {
-#define mx28_auart_data_entry(_id)                                      \
-        mxs_auart_data_entry(MX28, _id, _id)
-        mx28_auart_data_entry(0),
-        mx28_auart_data_entry(1),
-        mx28_auart_data_entry(2),
-        mx28_auart_data_entry(3),
-        mx28_auart_data_entry(4),
-};
-#endif
-
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("mxs-auart", data->id,
-                                        res, ARRAY_SIZE(res), NULL, 0,
-                                        DMA_BIT_MASK(32));
-}
-
diff --git a/arch/arm/mach-mxs/devices/platform-dma.c b/arch/arm/mach-mxs/devices/platform-dma.c
deleted file mode 100644
index 46824501de00..000000000000
--- a/arch/arm/mach-mxs/devices/platform-dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/dma-mapping.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_dma(const char *devid,
-                                                resource_size_t base)
-{
-        struct resource res[] = {
-                {
-                        .start = base,
-                        .end = base + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }
-        };
-
-        return mxs_add_platform_device_dmamask(devid, -1,
-                                res, ARRAY_SIZE(res), NULL, 0,
-                                DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
deleted file mode 100644
index ae96a4fd8f14..000000000000
--- a/arch/arm/mach-mxs/devices/platform-fec.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_fec_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR,        \
-                .irq = soc ## _INT_ENET_MAC ## _id,                     \
-        }
-
-#define mxs_fec_data_entry(soc, _id)                                    \
-        [_id] = mxs_fec_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_fec_data mx28_fec_data[] __initconst = {
-#define mx28_fec_data_entry(_id)                                        \
-        mxs_fec_data_entry(MX28, _id)
-        mx28_fec_data_entry(0),
-        mx28_fec_data_entry(1),
-};
-#endif
-
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_16K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx28-fec", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
-                        DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-flexcan.c b/arch/arm/mach-mxs/devices/platform-flexcan.c
deleted file mode 100644
index 43a6b4bae6fe..000000000000
--- a/arch/arm/mach-mxs/devices/platform-flexcan.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2010, 2011 Pengutronix,
- *                          Marc Kleine-Budde <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)           \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR,           \
-                .iosize = _size,                                        \
-                .irq = soc ## _INT_CAN ## _hwid,                        \
-        }
-
-#define mxs_flexcan_data_entry(soc, _id, _hwid, _size)                  \
-        [_id] = mxs_flexcan_data_entry_single(soc, _id, _hwid, _size)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_flexcan_data mx28_flexcan_data[] __initconst = {
-#define mx28_flexcan_data_entry(_id, _hwid)                             \
-        mxs_flexcan_data_entry_single(MX28, _id, _hwid, SZ_8K)
-        mx28_flexcan_data_entry(0, 0),
-        mx28_flexcan_data_entry(1, 1),
-};
-#endif /* ifdef CONFIG_SOC_IMX28 */
-
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + data->iosize - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("flexcan", data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c b/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
deleted file mode 100644
index cd99f19ec637..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpio-mxs.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_gpio(
-        char *name, int id, resource_size_t iobase, int irq)
-{
-        struct resource res[] = {
-                {
-                        .start = iobase,
-                        .end = iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = irq,
-                        .end = irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return platform_device_register_resndata(&mxs_apbh_bus,
-                        name, id, res, ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c b/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
deleted file mode 100644
index 3e22df5944a8..000000000000
--- a/arch/arm/mach-mxs/devices/platform-gpmi-nand.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/dma-mapping.h>
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_gpmi_nand_data mx23_gpmi_nand_data __initconst = {
-        .devid = "imx23-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX23_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_ATTENTION,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX23_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX23_DMA_GPMI0,
-                                        MX23_DMA_GPMI3 - MX23_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX23_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_gpmi_nand_data mx28_gpmi_nand_data __initconst = {
-        .devid = "imx28-gpmi-nand",
-        .res = {
-                /* GPMI */
-                DEFINE_RES_MEM_NAMED(MX28_GPMI_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_GPMI_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI,
-                                        GPMI_NAND_GPMI_INTERRUPT_RES_NAME),
-                /* BCH */
-                DEFINE_RES_MEM_NAMED(MX28_BCH_BASE_ADDR, SZ_8K,
-                                        GPMI_NAND_BCH_REGS_ADDR_RES_NAME),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_BCH,
-                                        GPMI_NAND_BCH_INTERRUPT_RES_NAME),
-                /* DMA */
-                DEFINE_RES_NAMED(MX28_DMA_GPMI0,
-                                        MX28_DMA_GPMI7 - MX28_DMA_GPMI0 + 1,
-                                        GPMI_NAND_DMA_CHANNELS_RES_NAME,
-                                        IORESOURCE_DMA),
-                DEFINE_RES_IRQ_NAMED(MX28_INT_GPMI_DMA,
-                                        GPMI_NAND_DMA_INTERRUPT_RES_NAME),
-        },
-};
-#endif
-
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data)
-{
-        return mxs_add_platform_device_dmamask(data->devid, -1,
-                                data->res, GPMI_NAND_RES_SIZE,
-                                pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
deleted file mode 100644
index 79222ec8ede1..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix
- * Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_i2c_data_entry_single(soc, _id)                             \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _I2C ## _id ## _BASE_ADDR,             \
-                .errirq = soc ## _INT_I2C ## _id ## _ERROR,             \
-                .dmairq = soc ## _INT_I2C ## _id ## _DMA,               \
-        }
-
-#define mxs_i2c_data_entry(soc, _id)                                    \
-        [_id] = mxs_i2c_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
-        mxs_i2c_data_entry(MX28, 0),
-        mxs_i2c_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->errirq,
-                        .end = data->errirq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("mxs-i2c", data->id, res,
-                                        ARRAY_SIZE(res), NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c b/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
deleted file mode 100644
index b33c9d05c552..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-mmc.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)           \
-        {                                                               \
-                .devid = _devid,                                        \
-                .id = _id,                                              \
-                .iobase = soc ## _SSP ## hwid ## _BASE_ADDR,            \
-                .dma = soc ## _DMA_SSP ## hwid,                         \
-                .irq_err = soc ## _INT_SSP ## hwid ## _ERROR,           \
-                .irq_dma = soc ## _INT_SSP ## hwid ## _DMA,             \
-        }
-
-#define mxs_mxs_mmc_data_entry(soc, _devid, _id, hwid)                  \
-        [_id] = mxs_mxs_mmc_data_entry_single(soc, _devid, _id, hwid)
-
-
-#ifdef CONFIG_SOC_IMX23
-const struct mxs_mxs_mmc_data mx23_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 0, 1),
-        mxs_mxs_mmc_data_entry(MX23, "imx23-mmc", 1, 2),
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst = {
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 0, 0),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 1, 1),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 2, 2),
-        mxs_mxs_mmc_data_entry(MX28, "imx28-mmc", 3, 3),
-};
-#endif
-
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start  = data->iobase,
-                        .end    = data->iobase + SZ_8K - 1,
-                        .flags  = IORESOURCE_MEM,
-                }, {
-                        .start  = data->dma,
-                        .end    = data->dma,
-                        .flags  = IORESOURCE_DMA,
-                }, {
-                        .start  = data->irq_err,
-                        .end    = data->irq_err,
-                        .flags  = IORESOURCE_IRQ,
-                }, {
-                        .start  = data->irq_dma,
-                        .end    = data->irq_dma,
-                        .flags  = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device(data->devid, data->id,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c b/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
deleted file mode 100644
index 680f5a902936..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-pwm.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/devices-common.h>
-
-struct platform_device *__init mxs_add_mxs_pwm(resource_size_t iobase, int id)
-{
-        struct resource res = {
-                .flags = IORESOURCE_MEM,
-        };
-
-        res.start = iobase + 0x10 + 0x20 * id;
-        res.end = res.start + 0x1f;
-
-        return mxs_add_platform_device("mxs-pwm", id, &res, 1, NULL, 0);
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
deleted file mode 100644
index f6e3a60b4201..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define mxs_saif_data_entry_single(soc, _id)                            \
-        {                                                               \
-                .id = _id,                                              \
-                .iobase = soc ## _SAIF ## _id ## _BASE_ADDR,            \
-                .irq = soc ## _INT_SAIF ## _id,                         \
-                .dma = soc ## _DMA_SAIF ## _id,                         \
-                .dmairq = soc ## _INT_SAIF ## _id ##_DMA,               \
-        }
-
-#define mxs_saif_data_entry(soc, _id)                                   \
-        [_id] = mxs_saif_data_entry_single(soc, _id)
-
-#ifdef CONFIG_SOC_IMX28
-const struct mxs_saif_data mx28_saif_data[] __initconst = {
-        mxs_saif_data_entry(MX28, 0),
-        mxs_saif_data_entry(MX28, 1),
-};
-#endif
-
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
-                                const struct mxs_saif_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                }, {
-                        .start = data->dma,
-                        .end = data->dma,
-                        .flags = IORESOURCE_DMA,
-                }, {
-                        .start = data->dmairq,
-                        .end = data->dmairq,
-                        .flags = IORESOURCE_IRQ,
-                },
-
-        };
-
-        return mxs_add_platform_device("mxs-saif", data->id, res,
-                                ARRAY_SIZE(res), pdata, sizeof(*pdata));
-}
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
deleted file mode 100644
index 76b53f73418e..000000000000
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-#include <linux/mxsfb.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_LCDIF_BASE_ADDR,
-                        .end = MX23_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx23-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_mxsfb(
-                const struct mxsfb_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_LCDIF_BASE_ADDR,
-                        .end = MX28_LCDIF_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                },
-        };
-
-        return mxs_add_platform_device_dmamask("imx28-fb", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata), DMA_BIT_MASK(32));
-}
-#endif /* ifdef CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c b/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
deleted file mode 100644
index 639eaee15553..000000000000
--- a/arch/arm/mach-mxs/devices/platform-rtc-stmp3xxx.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/sizes.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#ifdef CONFIG_SOC_IMX23
-struct platform_device *__init mx23_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX23_RTC_BASE_ADDR,
-                        .end = MX23_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX23_INT_RTC_ALARM,
-                        .end = MX23_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX23 */
-
-#ifdef CONFIG_SOC_IMX28
-struct platform_device *__init mx28_add_rtc_stmp3xxx(void)
-{
-        struct resource res[] = {
-                {
-                        .start = MX28_RTC_BASE_ADDR,
-                        .end = MX28_RTC_BASE_ADDR + SZ_8K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = MX28_INT_RTC_ALARM,
-                        .end = MX28_INT_RTC_ALARM,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return mxs_add_platform_device("stmp3xxx-rtc", 0, res, ARRAY_SIZE(res),
-                                        NULL, 0);
-}
-#endif /* CONFIG_SOC_IMX28 */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index de6c7ba42544..4dec79563f19 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -17,21 +17,12 @@ extern void mxs_timer_init(int);
 extern void mxs_restart(char, const char *);
 extern int mxs_saif_clkmux_select(unsigned int clkmux);
 
-extern void mx23_soc_init(void);
 extern int mx23_clocks_init(void);
 extern void mx23_map_io(void);
-extern void mx23_init_irq(void);
 
-extern void mx28_soc_init(void);
 extern int mx28_clocks_init(void);
 extern void mx28_map_io(void);
-extern void mx28_init_irq(void);
 
 extern void icoll_init_irq(void);
 
-extern struct platform_device *mxs_add_dma(const char *devid,
-                                                resource_size_t base);
-extern struct platform_device *mxs_add_gpio(char *name, int id,
-                                            resource_size_t iobase, int irq);
-
 #endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
deleted file mode 100644
index e8b1d958240b..000000000000
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/amba/bus.h>
-
-extern struct device mxs_apbh_bus;
-
-struct platform_device *mxs_add_platform_device_dmamask(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data, u64 dmamask);
-
-static inline struct platform_device *mxs_add_platform_device(
-                const char *name, int id,
-                const struct resource *res, unsigned int num_resources,
-                const void *data, size_t size_data)
-{
-        return mxs_add_platform_device_dmamask(
-                        name, id, res, num_resources, data, size_data, 0);
-}
-
-/* auart */
-struct mxs_auart_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_auart(
-                const struct mxs_auart_data *data);
-
-/* fec */
-#include <linux/fec.h>
-struct mxs_fec_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_fec(
-                const struct mxs_fec_data *data,
-                const struct fec_platform_data *pdata);
-
-/* flexcan */
-#include <linux/can/platform/flexcan.h>
-struct mxs_flexcan_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t iosize;
-        resource_size_t irq;
-};
-struct platform_device *__init mxs_add_flexcan(
-                const struct mxs_flexcan_data *data,
-                const struct flexcan_platform_data *pdata);
-
-/* gpmi-nand */
-#include <linux/mtd/gpmi-nand.h>
-struct mxs_gpmi_nand_data {
-        const char *devid;
-        const struct resource res[GPMI_NAND_RES_SIZE];
-};
-struct platform_device *__init
-mxs_add_gpmi_nand(const struct gpmi_nand_platform_data *pdata,
-                const struct mxs_gpmi_nand_data *data);
-
-/* i2c */
-struct mxs_mxs_i2c_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t errirq;
-        resource_size_t dmairq;
-};
-struct platform_device * __init mxs_add_mxs_i2c(
-                const struct mxs_mxs_i2c_data *data);
-
-/* mmc */
-#include <linux/mmc/mxs-mmc.h>
-struct mxs_mxs_mmc_data {
-        const char *devid;
-        int id;
-        resource_size_t iobase;
-        resource_size_t dma;
-        resource_size_t irq_err;
-        resource_size_t irq_dma;
-};
-struct platform_device *__init mxs_add_mxs_mmc(
-                const struct mxs_mxs_mmc_data *data,
-                const struct mxs_mmc_platform_data *pdata);
-
-/* pwm */
-struct platform_device *__init mxs_add_mxs_pwm(
-                resource_size_t iobase, int id);
-
-/* saif */
-#include <sound/saif.h>
-struct mxs_saif_data {
-        int id;
-        resource_size_t iobase;
-        resource_size_t irq;
-        resource_size_t dma;
-        resource_size_t dmairq;
-};
-
-struct platform_device *__init mxs_add_saif(
-                const struct mxs_saif_data *data,
-                const struct mxs_saif_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
deleted file mode 100644
index b0190a4822f2..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx23.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX23_H__
-#define __MACH_IOMUX_MX23_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX23_PAD_GPMI_D00__GPMI_D00             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D01__GPMI_D01             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D02__GPMI_D02             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D03__GPMI_D03             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D04__GPMI_D04             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D05__GPMI_D05             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D06__GPMI_D06             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D07__GPMI_D07             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D08__GPMI_D08             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D09__GPMI_D09             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D10__GPMI_D10             MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D11__GPMI_D11             MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D12__GPMI_D12             MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D13__GPMI_D13             MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D14__GPMI_D14             MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_D15__GPMI_D15             MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CLE__GPMI_CLE             MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_ALE__GPMI_ALE             MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE2N__GPMI_CE2N           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY0__GPMI_RDY0           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY1__GPMI_RDY1           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY2__GPMI_RDY2           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDY3__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WPN__GPMI_WPN             MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_WRN__GPMI_WRN             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_RDN__GPMI_RDN             MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_CTS__AUART1_CTS         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RTS__AUART1_RTS         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_RX__AUART1_RX           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-#define MX23_PAD_AUART1_TX__AUART1_TX           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SCL__I2C_SCL               MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
-#define MX23_PAD_I2C_SDA__I2C_SDA               MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_LCD_D00__LCD_D00               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D01__LCD_D01               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D02__LCD_D02               MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D03__LCD_D03               MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D04__LCD_D04               MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D05__LCD_D05               MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D06__LCD_D06               MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D07__LCD_D07               MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D08__LCD_D08               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D09__LCD_D09               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D10__LCD_D10               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D11__LCD_D11               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D12__LCD_D12               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D13__LCD_D13               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D14__LCD_D14               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D15__LCD_D15               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D16__LCD_D16               MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_D17__LCD_D17               MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RESET__LCD_RESET           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_RS__LCD_RS                 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_WR__LCD_WR                 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_CS__LCD_CS                 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_DOTCK__LCD_DOTCK           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_ENABLE__LCD_ENABLE         MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_HSYNC__LCD_HSYNC           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX23_PAD_LCD_VSYNC__LCD_VSYNC           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX23_PAD_PWM0__PWM0                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX23_PAD_PWM1__PWM1                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX23_PAD_PWM2__PWM2                     MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX23_PAD_PWM3__PWM3                     MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX23_PAD_PWM4__PWM4                     MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-
-#define MX23_PAD_SSP1_CMD__SSP1_CMD             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DETECT__SSP1_DETECT       MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA0__SSP1_DATA0         MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA1__SSP1_DATA1         MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA2__SSP1_DATA2         MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_DATA3__SSP1_DATA3         MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX23_PAD_SSP1_SCK__SSP1_SCK             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYA__ROTARYA               MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX23_PAD_ROTARYB__ROTARYB               MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A00__EMI_A00               MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A01__EMI_A01               MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A02__EMI_A02               MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A03__EMI_A03               MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A04__EMI_A04               MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A05__EMI_A05               MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A06__EMI_A06               MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A07__EMI_A07               MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A08__EMI_A08               MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A09__EMI_A09               MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A10__EMI_A10               MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A11__EMI_A11               MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_A12__EMI_A12               MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA0__EMI_BA0               MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_BA1__EMI_BA1               MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CASN__EMI_CASN             MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE0N__EMI_CE0N             MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CE1N__EMI_CE1N             MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE1N__GPMI_CE1N           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-#define MX23_PAD_GPMI_CE0N__GPMI_CE0N           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CKE__EMI_CKE               MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_RASN__EMI_RASN             MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_WEN__EMI_WEN               MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
-
-#define MX23_PAD_EMI_D00__EMI_D00               MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D01__EMI_D01               MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D02__EMI_D02               MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D03__EMI_D03               MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D04__EMI_D04               MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D05__EMI_D05               MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D06__EMI_D06               MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D07__EMI_D07               MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D08__EMI_D08               MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D09__EMI_D09               MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D10__EMI_D10               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D11__EMI_D11               MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D12__EMI_D12               MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D13__EMI_D13               MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D14__EMI_D14               MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_D15__EMI_D15               MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM0__EMI_DQM0             MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQM1__EMI_DQM1             MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS0__EMI_DQS0             MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_DQS1__EMI_DQS1             MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLK__EMI_CLK               MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX23_PAD_EMI_CLKN__EMI_CLKN             MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX23_PAD_GPMI_D00__LCD_D8               MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D01__LCD_D9               MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D02__LCD_D10              MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D03__LCD_D11              MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D04__LCD_D12              MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D05__LCD_D13              MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D06__LCD_D14              MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D07__LCD_D15              MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D08__LCD_D18              MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D09__LCD_D19              MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D10__LCD_D20              MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D11__LCD_D21              MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D12__LCD_D22              MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D13__LCD_D23              MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D14__AUART2_RX            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_D15__AUART2_TX            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CLE__LCD_D16              MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_ALE__LCD_D17              MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX23_PAD_GPMI_CE2N__ATA_A2              MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RTS__IR_CLK             MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_RX__IR_RX               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-#define MX23_PAD_AUART1_TX__IR_TX               MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SCL__GPMI_RDY2             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
-#define MX23_PAD_I2C_SDA__GPMI_CE2N             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
-
-#define MX23_PAD_LCD_D00__ETM_DA8               MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D01__ETM_DA9               MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D02__ETM_DA10              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D03__ETM_DA11              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D04__ETM_DA12              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D05__ETM_DA13              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D06__ETM_DA14              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D07__ETM_DA15              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D08__ETM_DA0               MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D09__ETM_DA1               MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D10__ETM_DA2               MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D11__ETM_DA3               MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D12__ETM_DA4               MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D13__ETM_DA5               MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D14__ETM_DA6               MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_D15__ETM_DA7               MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RESET__ETM_TCTL            MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_RS__ETM_TCLK               MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_DOTCK__GPMI_RDY3           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_ENABLE__I2C_SCL            MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_HSYNC__I2C_SDA             MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX23_PAD_LCD_VSYNC__LCD_BUSY            MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX23_PAD_PWM0__ROTARYA                  MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX23_PAD_PWM1__ROTARYB                  MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX23_PAD_PWM2__GPMI_RDY3                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX23_PAD_PWM3__ETM_TCTL                 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX23_PAD_PWM4__ETM_TCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX23_PAD_SSP1_DETECT__GPMI_CE3N         MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA1__I2C_SCL            MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_1)
-#define MX23_PAD_SSP1_DATA2__I2C_SDA            MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYA__AUART2_RTS            MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX23_PAD_ROTARYB__AUART2_CTS            MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX23_PAD_GPMI_D00__SSP2_DATA0           MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D01__SSP2_DATA1           MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D02__SSP2_DATA2           MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D03__SSP2_DATA3           MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D04__SSP2_DATA4           MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D05__SSP2_DATA5           MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D06__SSP2_DATA6           MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D07__SSP2_DATA7           MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D08__SSP1_DATA4           MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D09__SSP1_DATA5           MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D10__SSP1_DATA6           MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D11__SSP1_DATA7           MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_D15__GPMI_CE3N            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY0__SSP2_DETECT         MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_RDY1__SSP2_CMD            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX23_PAD_GPMI_WRN__SSP2_SCK             MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_CTS__SSP1_DATA4         MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RTS__SSP1_DATA5         MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_RX__SSP1_DATA6          MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
-#define MX23_PAD_AUART1_TX__SSP1_DATA7          MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SCL__AUART1_TX             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
-#define MX23_PAD_I2C_SDA__AUART1_RX             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
-
-#define MX23_PAD_LCD_D08__SAIF2_SDATA0          MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D09__SAIF1_SDATA0          MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D11__SAIF_LRCLK            MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D12__SAIF2_SDATA1          MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D13__SAIF2_SDATA2          MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D14__SAIF1_SDATA2          MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D15__SAIF1_SDATA1          MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX23_PAD_LCD_RESET__GPMI_CE3N           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX23_PAD_PWM0__DUART_RX                 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
-#define MX23_PAD_PWM1__DUART_TX                 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
-#define MX23_PAD_PWM3__AUART1_CTS               MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX23_PAD_PWM4__AUART1_RTS               MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX23_PAD_SSP1_CMD__JTAG_TDO             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DETECT__USB_OTG_ID        MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA0__JTAG_TDI           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA1__JTAG_TCLK          MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA2__JTAG_RTCK          MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_DATA3__JTAG_TMS           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_2)
-#define MX23_PAD_SSP1_SCK__JTAG_TRST            MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYA__SPDIF                 MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_2)
-#define MX23_PAD_ROTARYB__GPMI_CE3N             MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX23_PAD_GPMI_D00__GPIO_0_0             MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D01__GPIO_0_1             MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D02__GPIO_0_2             MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D03__GPIO_0_3             MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D04__GPIO_0_4             MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D05__GPIO_0_5             MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D06__GPIO_0_6             MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D07__GPIO_0_7             MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D08__GPIO_0_8             MXS_IOMUX_PAD_NAKED(0,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D09__GPIO_0_9             MXS_IOMUX_PAD_NAKED(0,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D10__GPIO_0_10            MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D11__GPIO_0_11            MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D12__GPIO_0_12            MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D13__GPIO_0_13            MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D14__GPIO_0_14            MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_D15__GPIO_0_15            MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CLE__GPIO_0_16            MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_ALE__GPIO_0_17            MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE2N__GPIO_0_18           MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY0__GPIO_0_19           MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY1__GPIO_0_20           MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY2__GPIO_0_21           MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDY3__GPIO_0_22           MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WPN__GPIO_0_23            MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_WRN__GPIO_0_24            MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_RDN__GPIO_0_25            MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_CTS__GPIO_0_26          MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RTS__GPIO_0_27          MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_RX__GPIO_0_28           MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_AUART1_TX__GPIO_0_29           MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SCL__GPIO_0_30             MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_I2C_SDA__GPIO_0_31             MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_LCD_D00__GPIO_1_0              MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D01__GPIO_1_1              MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D02__GPIO_1_2              MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D03__GPIO_1_3              MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D04__GPIO_1_4              MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D05__GPIO_1_5              MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D06__GPIO_1_6              MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D07__GPIO_1_7              MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D08__GPIO_1_8              MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D09__GPIO_1_9              MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D10__GPIO_1_10             MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D11__GPIO_1_11             MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D12__GPIO_1_12             MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D13__GPIO_1_13             MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D14__GPIO_1_14             MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D15__GPIO_1_15             MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D16__GPIO_1_16             MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_D17__GPIO_1_17             MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RESET__GPIO_1_18           MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_RS__GPIO_1_19              MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_WR__GPIO_1_20              MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_CS__GPIO_1_21              MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_DOTCK__GPIO_1_22           MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_ENABLE__GPIO_1_23          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_HSYNC__GPIO_1_24           MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_LCD_VSYNC__GPIO_1_25           MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM0__GPIO_1_26                MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM1__GPIO_1_27                MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM2__GPIO_1_28                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM3__GPIO_1_29                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_PWM4__GPIO_1_30                MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-
-#define MX23_PAD_SSP1_CMD__GPIO_2_0             MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DETECT__GPIO_2_1          MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA0__GPIO_2_2           MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA1__GPIO_2_3           MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA2__GPIO_2_4           MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_DATA3__GPIO_2_5           MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX23_PAD_SSP1_SCK__GPIO_2_6             MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYA__GPIO_2_7              MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX23_PAD_ROTARYB__GPIO_2_8              MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A00__GPIO_2_9              MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A01__GPIO_2_10             MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A02__GPIO_2_11             MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A03__GPIO_2_12             MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A04__GPIO_2_13             MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A05__GPIO_2_14             MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A06__GPIO_2_15             MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A07__GPIO_2_16             MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A08__GPIO_2_17             MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A09__GPIO_2_18             MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A10__GPIO_2_19             MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A11__GPIO_2_20             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_A12__GPIO_2_21             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA0__GPIO_2_22             MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_BA1__GPIO_2_23             MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CASN__GPIO_2_24            MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE0N__GPIO_2_25            MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CE1N__GPIO_2_26            MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE1N__GPIO_2_27           MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-#define MX23_PAD_GPMI_CE0N__GPIO_2_28           MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_CKE__GPIO_2_29             MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_RASN__GPIO_2_30            MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
-#define MX23_PAD_EMI_WEN__GPIO_2_31             MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
deleted file mode 100644
index f50fefd10520..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux-mx28.h
+++ /dev/null
@@ -1,537 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_IOMUX_MX28_H__
-#define __MACH_IOMUX_MX28_H__
-
-#include <mach/iomux.h>
-
-/*
- * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux.h
- *
- *                                                                      BANK    PIN     MUX
- */
-/* MUXSEL_0 */
-#define MX28_PAD_GPMI_D00__GPMI_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D01__GPMI_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D02__GPMI_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D03__GPMI_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D04__GPMI_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D05__GPMI_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D06__GPMI_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_D07__GPMI_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE0N__GPMI_CE0N                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE1N__GPMI_CE1N                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE2N__GPMI_CE2N                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CE3N__GPMI_CE3N                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY0__GPMI_READY0                 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY1__GPMI_READY1                 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY2__GPMI_READY2                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDY3__GPMI_READY3                 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RDN__GPMI_RDN                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_WRN__GPMI_WRN                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_ALE__GPMI_ALE                     MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_CLE__GPMI_CLE                     MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
-#define MX28_PAD_GPMI_RESETN__GPMI_RESETN               MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
-
-#define MX28_PAD_LCD_D00__LCD_D0                        MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D01__LCD_D1                        MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D02__LCD_D2                        MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D03__LCD_D3                        MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D04__LCD_D4                        MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D05__LCD_D5                        MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D06__LCD_D6                        MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D07__LCD_D7                        MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D08__LCD_D8                        MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D09__LCD_D9                        MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D10__LCD_D10                       MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D11__LCD_D11                       MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D12__LCD_D12                       MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D13__LCD_D13                       MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D14__LCD_D14                       MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D15__LCD_D15                       MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D16__LCD_D16                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D17__LCD_D17                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D18__LCD_D18                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D19__LCD_D19                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D20__LCD_D20                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D21__LCD_D21                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D22__LCD_D22                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_D23__LCD_D23                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RD_E__LCD_RD_E                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN                 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RS__LCD_RS                         MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_CS__LCD_CS                         MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_VSYNC__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_HSYNC__LCD_HSYNC                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_ENABLE__LCD_ENABLE                 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
-
-#define MX28_PAD_SSP0_DATA0__SSP0_D0                    MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA1__SSP0_D1                    MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA2__SSP0_D2                    MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA3__SSP0_D3                    MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA4__SSP0_D4                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA5__SSP0_D5                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA6__SSP0_D6                    MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DATA7__SSP0_D7                    MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_CMD__SSP0_CMD                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT          MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_0)
-#define MX28_PAD_SSP0_SCK__SSP0_SCK                     MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_SCK__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_CMD__SSP1_CMD                     MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA0__SSP1_D0                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
-#define MX28_PAD_SSP1_DATA3__SSP1_D3                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SCK__SSP2_SCK                     MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MOSI__SSP2_CMD                    MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_MISO__SSP2_D0                     MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS0__SSP2_D3                      MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS1__SSP2_D4                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SSP2_SS2__SSP2_D5                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SCK__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MOSI__SSP3_CMD                    MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_MISO__SSP3_D0                     MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SSP3_SS0__SSP3_D3                      MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
-
-#define MX28_PAD_AUART0_RX__AUART0_RX                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_TX__AUART0_TX                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_CTS__AUART0_CTS                 MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_0)
-#define MX28_PAD_AUART0_RTS__AUART0_RTS                 MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RX__AUART1_RX                   MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_TX__AUART1_TX                   MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_CTS__AUART1_CTS                 MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_0)
-#define MX28_PAD_AUART1_RTS__AUART1_RTS                 MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RX__AUART2_RX                   MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_TX__AUART2_TX                   MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_CTS__AUART2_CTS                 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
-#define MX28_PAD_AUART2_RTS__AUART2_RTS                 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RX__AUART3_RX                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_TX__AUART3_TX                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_CTS__AUART3_CTS                 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
-#define MX28_PAD_AUART3_RTS__AUART3_RTS                 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
-#define MX28_PAD_PWM0__PWM_0                            MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
-#define MX28_PAD_PWM1__PWM_1                            MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
-#define MX28_PAD_PWM2__PWM_2                            MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK               MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK             MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0             MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SCL__I2C0_SCL                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
-#define MX28_PAD_I2C0_SDA__I2C0_SDA                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
-#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
-#define MX28_PAD_SPDIF__SPDIF_TX                        MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
-#define MX28_PAD_PWM3__PWM_3                            MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
-#define MX28_PAD_PWM4__PWM_4                            MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
-#define MX28_PAD_LCD_RESET__LCD_RESET                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
-
-#define MX28_PAD_ENET0_MDC__ENET0_MDC                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_MDIO__ENET0_MDIO                 MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN               MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD0__ENET0_RXD0                 MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD1__ENET0_RXD1                 MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK             MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD0__ENET0_TXD0                 MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD1__ENET0_TXD1                 MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD2__ENET0_RXD2                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RXD3__ENET0_RXD3                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD2__ENET0_TXD2                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_TXD3__ENET0_TXD3                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK             MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_COL__ENET0_COL                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
-#define MX28_PAD_ENET0_CRS__ENET0_CRS                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
-#define MX28_PAD_ENET_CLK__CLKCTRL_ENET                 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
-#define MX28_PAD_JTAG_RTCK__JTAG_RTCK                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_D00__EMI_DATA0                     MXS_IOMUX_PAD_NAKED(5,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D01__EMI_DATA1                     MXS_IOMUX_PAD_NAKED(5,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D02__EMI_DATA2                     MXS_IOMUX_PAD_NAKED(5,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D03__EMI_DATA3                     MXS_IOMUX_PAD_NAKED(5,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D04__EMI_DATA4                     MXS_IOMUX_PAD_NAKED(5,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D05__EMI_DATA5                     MXS_IOMUX_PAD_NAKED(5,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D06__EMI_DATA6                     MXS_IOMUX_PAD_NAKED(5,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D07__EMI_DATA7                     MXS_IOMUX_PAD_NAKED(5,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D08__EMI_DATA8                     MXS_IOMUX_PAD_NAKED(5,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D09__EMI_DATA9                     MXS_IOMUX_PAD_NAKED(5,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D10__EMI_DATA10                    MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D11__EMI_DATA11                    MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D12__EMI_DATA12                    MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D13__EMI_DATA13                    MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D14__EMI_DATA14                    MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_D15__EMI_DATA15                    MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT0__EMI_ODT0                     MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM0__EMI_DQM0                     MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_ODT1__EMI_ODT1                     MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQM1__EMI_DQM1                     MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CLK__EMI_CLK                       MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS0__EMI_DQS0                     MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DQS1__EMI_DQS1                     MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN             MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
-
-#define MX28_PAD_EMI_A00__EMI_ADDR0                     MXS_IOMUX_PAD_NAKED(6,  0, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A01__EMI_ADDR1                     MXS_IOMUX_PAD_NAKED(6,  1, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A02__EMI_ADDR2                     MXS_IOMUX_PAD_NAKED(6,  2, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A03__EMI_ADDR3                     MXS_IOMUX_PAD_NAKED(6,  3, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A04__EMI_ADDR4                     MXS_IOMUX_PAD_NAKED(6,  4, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A05__EMI_ADDR5                     MXS_IOMUX_PAD_NAKED(6,  5, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A06__EMI_ADDR6                     MXS_IOMUX_PAD_NAKED(6,  6, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A07__EMI_ADDR7                     MXS_IOMUX_PAD_NAKED(6,  7, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A08__EMI_ADDR8                     MXS_IOMUX_PAD_NAKED(6,  8, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A09__EMI_ADDR9                     MXS_IOMUX_PAD_NAKED(6,  9, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A10__EMI_ADDR10                    MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A11__EMI_ADDR11                    MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A12__EMI_ADDR12                    MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A13__EMI_ADDR13                    MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_A14__EMI_ADDR14                    MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA0__EMI_BA0                       MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA1__EMI_BA1                       MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_BA2__EMI_BA2                       MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CASN__EMI_CASN                     MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_RASN__EMI_RASN                     MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_WEN__EMI_WEN                       MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE0N__EMI_CE0N                     MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CE1N__EMI_CE1N                     MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
-#define MX28_PAD_EMI_CKE__EMI_CKE                       MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
-
-/* MUXSEL_1 */
-#define MX28_PAD_GPMI_D00__SSP1_D0                      MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D01__SSP1_D1                      MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D02__SSP1_D2                      MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D03__SSP1_D3                      MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D04__SSP1_D4                      MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D05__SSP1_D5                      MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D06__SSP1_D6                      MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_D07__SSP1_D7                      MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE0N__SSP3_D0                     MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE1N__SSP3_D3                     MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE2N__CAN1_TX                     MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CE3N__CAN1_RX                     MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT            MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY1__SSP1_CMD                    MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY2__CAN0_TX                     MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDY3__CAN0_RX                     MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RDN__SSP3_SCK                     MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_WRN__SSP1_SCK                     MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_ALE__SSP3_D1                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_CLE__SSP3_D2                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
-#define MX28_PAD_GPMI_RESETN__SSP3_CMD                  MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
-
-#define MX28_PAD_LCD_D03__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D04__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D08__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D09__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT         MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN          MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT         MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN          MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RD_E__LCD_VSYNC                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RS__LCD_DOTCLK                     MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_CS__LCD_ENABLE                     MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0                MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK                 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_SSP0_DATA4__SSP2_D0                    MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA5__SSP2_D3                    MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA6__SSP2_CMD                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_1)
-#define MX28_PAD_SSP0_DATA7__SSP2_SCK                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_SCK__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_CMD__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA0__SSP2_D6                    MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
-#define MX28_PAD_SSP1_DATA3__SSP2_D7                    MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SCK__AUART2_RX                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MOSI__AUART2_TX                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_MISO__AUART3_RX                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS0__AUART3_TX                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS1__SSP2_D1                      MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SSP2_SS2__SSP2_D2                      MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SCK__AUART4_TX                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MOSI__AUART4_RX                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_MISO__AUART4_RTS                  MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
-#define MX28_PAD_SSP3_SS0__AUART4_CTS                   MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
-
-#define MX28_PAD_AUART0_RX__I2C0_SCL                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_TX__I2C0_SDA                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_CTS__AUART4_RX                  MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_1)
-#define MX28_PAD_AUART0_RTS__AUART4_TX                  MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT            MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT           MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_1)
-#define MX28_PAD_AUART1_RTS__USB0_ID                    MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RX__SSP3_D1                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_TX__SSP3_D2                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_CTS__I2C1_SCL                   MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
-#define MX28_PAD_AUART2_RTS__I2C1_SDA                   MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RX__CAN0_TX                     MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_TX__CAN0_RX                     MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_CTS__CAN1_TX                    MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
-#define MX28_PAD_AUART3_RTS__CAN1_RX                    MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
-#define MX28_PAD_PWM0__I2C1_SCL                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
-#define MX28_PAD_PWM1__I2C1_SDA                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
-#define MX28_PAD_PWM2__USB0_ID                          MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_MCLK__PWM_3                      MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_LRCLK__PWM_4                     MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_BITCLK__PWM_5                    MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF0_SDATA0__PWM_6                    MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA               MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
-#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB               MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
-#define MX28_PAD_SAIF1_SDATA0__PWM_7                    MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
-#define MX28_PAD_LCD_RESET__LCD_VSYNC                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
-
-#define MX28_PAD_ENET0_MDC__GPMI_CE4N                   MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_MDIO__GPMI_CE5N                  MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N                 MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD0__GPMI_CE7N                  MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD1__GPMI_READY4                MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER            MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TX_EN__GPMI_READY5               MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD0__GPMI_READY6                MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD1__GPMI_READY7                MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD2__ENET1_RXD0                 MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RXD3__ENET1_RXD1                 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD2__ENET1_TXD0                 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_TXD3__ENET1_TXD1                 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER              MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_COL__ENET1_TX_EN                 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
-#define MX28_PAD_ENET0_CRS__ENET1_RX_EN                 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
-
-/* MUXSEL_2 */
-#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER                 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK                  MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY0__USB0_ID                     MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER                 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER               MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_ALE__SSP3_D4                      MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
-#define MX28_PAD_GPMI_CLE__SSP3_D5                      MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_LCD_D00__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D01__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D02__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D03__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D04__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D05__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D06__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D07__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D08__ETM_DA8                       MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D09__ETM_DA9                       MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D10__ETM_DA10                      MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D11__ETM_DA11                      MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D12__ETM_DA12                      MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D13__ETM_DA13                      MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D14__ETM_DA14                      MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D15__ETM_DA15                      MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D16__ETM_DA7                       MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D17__ETM_DA6                       MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D18__ETM_DA5                       MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D19__ETM_DA4                       MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D20__ETM_DA3                       MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D21__ETM_DA2                       MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D22__ETM_DA1                       MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_D23__ETM_DA0                       MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_RD_E__ETM_TCTL                     MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_WR_RWN__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_HSYNC__ETM_TCTL                    MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
-#define MX28_PAD_LCD_DOTCLK__ETM_TCLK                   MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
-
-#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT        MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN         MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT      MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
-#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN       MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1                 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2                MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1                MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2                 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT             MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT        MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT       MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN         MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_AUART0_RX__DUART_CTS                   MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_TX__DUART_RTS                   MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_CTS__DUART_RX                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_2)
-#define MX28_PAD_AUART0_RTS__DUART_TX                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RX__PWM_0                       MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_TX__PWM_1                       MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA             MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_2)
-#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB             MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RX__SSP3_D4                     MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_TX__SSP3_D5                     MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK               MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
-#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK                MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT       MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN        MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
-#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
-#define MX28_PAD_PWM0__DUART_RX                         MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
-#define MX28_PAD_PWM1__DUART_TX                         MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
-#define MX28_PAD_PWM2__USB1_OVERCURRENT                 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_MCLK__AUART4_CTS                 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS                MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_BITCLK__AUART4_RX                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF0_SDATA0__AUART4_TX                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SCL__DUART_RX                     MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
-#define MX28_PAD_I2C0_SDA__DUART_TX                     MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
-#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1             MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
-#define MX28_PAD_SPDIF__ENET1_RX_ER                     MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
-
-#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1                MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2               MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1              MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2               MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT    MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT      MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN       MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT      MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN       MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN     MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT       MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
-#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN        MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
-
-/* MUXSEL_GPIO */
-#define MX28_PAD_GPMI_D00__GPIO_0_0                     MXS_IOMUX_PAD_NAKED(0,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D01__GPIO_0_1                     MXS_IOMUX_PAD_NAKED(0,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D02__GPIO_0_2                     MXS_IOMUX_PAD_NAKED(0,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D03__GPIO_0_3                     MXS_IOMUX_PAD_NAKED(0,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D04__GPIO_0_4                     MXS_IOMUX_PAD_NAKED(0,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D05__GPIO_0_5                     MXS_IOMUX_PAD_NAKED(0,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D06__GPIO_0_6                     MXS_IOMUX_PAD_NAKED(0,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_D07__GPIO_0_7                     MXS_IOMUX_PAD_NAKED(0,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE0N__GPIO_0_16                   MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE1N__GPIO_0_17                   MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE2N__GPIO_0_18                   MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CE3N__GPIO_0_19                   MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY0__GPIO_0_20                   MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY1__GPIO_0_21                   MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY2__GPIO_0_22                   MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDY3__GPIO_0_23                   MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RDN__GPIO_0_24                    MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_WRN__GPIO_0_25                    MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_ALE__GPIO_0_26                    MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_CLE__GPIO_0_27                    MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_GPMI_RESETN__GPIO_0_28                 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_LCD_D00__GPIO_1_0                      MXS_IOMUX_PAD_NAKED(1,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D01__GPIO_1_1                      MXS_IOMUX_PAD_NAKED(1,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D02__GPIO_1_2                      MXS_IOMUX_PAD_NAKED(1,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D03__GPIO_1_3                      MXS_IOMUX_PAD_NAKED(1,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D04__GPIO_1_4                      MXS_IOMUX_PAD_NAKED(1,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D05__GPIO_1_5                      MXS_IOMUX_PAD_NAKED(1,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D06__GPIO_1_6                      MXS_IOMUX_PAD_NAKED(1,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D07__GPIO_1_7                      MXS_IOMUX_PAD_NAKED(1,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D08__GPIO_1_8                      MXS_IOMUX_PAD_NAKED(1,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D09__GPIO_1_9                      MXS_IOMUX_PAD_NAKED(1,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D10__GPIO_1_10                     MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D11__GPIO_1_11                     MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D12__GPIO_1_12                     MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D13__GPIO_1_13                     MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D14__GPIO_1_14                     MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D15__GPIO_1_15                     MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D16__GPIO_1_16                     MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D17__GPIO_1_17                     MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D18__GPIO_1_18                     MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D19__GPIO_1_19                     MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D20__GPIO_1_20                     MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D21__GPIO_1_21                     MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D22__GPIO_1_22                     MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_D23__GPIO_1_23                     MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RD_E__GPIO_1_24                    MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_WR_RWN__GPIO_1_25                  MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RS__GPIO_1_26                      MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_CS__GPIO_1_27                      MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_VSYNC__GPIO_1_28                   MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_HSYNC__GPIO_1_29                   MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_DOTCLK__GPIO_1_30                  MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_ENABLE__GPIO_1_31                  MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_SSP0_DATA0__GPIO_2_0                   MXS_IOMUX_PAD_NAKED(2,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA1__GPIO_2_1                   MXS_IOMUX_PAD_NAKED(2,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA2__GPIO_2_2                   MXS_IOMUX_PAD_NAKED(2,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA3__GPIO_2_3                   MXS_IOMUX_PAD_NAKED(2,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA4__GPIO_2_4                   MXS_IOMUX_PAD_NAKED(2,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA5__GPIO_2_5                   MXS_IOMUX_PAD_NAKED(2,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA6__GPIO_2_6                   MXS_IOMUX_PAD_NAKED(2,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DATA7__GPIO_2_7                   MXS_IOMUX_PAD_NAKED(2,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_CMD__GPIO_2_8                     MXS_IOMUX_PAD_NAKED(2,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_DETECT__GPIO_2_9                  MXS_IOMUX_PAD_NAKED(2,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP0_SCK__GPIO_2_10                    MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_SCK__GPIO_2_12                    MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_CMD__GPIO_2_13                    MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA0__GPIO_2_14                  MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP1_DATA3__GPIO_2_15                  MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SCK__GPIO_2_16                    MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MOSI__GPIO_2_17                   MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_MISO__GPIO_2_18                   MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS0__GPIO_2_19                    MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS1__GPIO_2_20                    MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP2_SS2__GPIO_2_21                    MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SCK__GPIO_2_24                    MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MOSI__GPIO_2_25                   MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_MISO__GPIO_2_26                   MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SSP3_SS0__GPIO_2_27                    MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_AUART0_RX__GPIO_3_0                    MXS_IOMUX_PAD_NAKED(3,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_TX__GPIO_3_1                    MXS_IOMUX_PAD_NAKED(3,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_CTS__GPIO_3_2                   MXS_IOMUX_PAD_NAKED(3,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART0_RTS__GPIO_3_3                   MXS_IOMUX_PAD_NAKED(3,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RX__GPIO_3_4                    MXS_IOMUX_PAD_NAKED(3,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_TX__GPIO_3_5                    MXS_IOMUX_PAD_NAKED(3,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_CTS__GPIO_3_6                   MXS_IOMUX_PAD_NAKED(3,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART1_RTS__GPIO_3_7                   MXS_IOMUX_PAD_NAKED(3,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RX__GPIO_3_8                    MXS_IOMUX_PAD_NAKED(3,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_TX__GPIO_3_9                    MXS_IOMUX_PAD_NAKED(3,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_CTS__GPIO_3_10                  MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART2_RTS__GPIO_3_11                  MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RX__GPIO_3_12                   MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_TX__GPIO_3_13                   MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_CTS__GPIO_3_14                  MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_AUART3_RTS__GPIO_3_15                  MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM0__GPIO_3_16                        MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM1__GPIO_3_17                        MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM2__GPIO_3_18                        MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_MCLK__GPIO_3_20                  MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21                 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22                MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23                MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SCL__GPIO_3_24                    MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
-#define MX28_PAD_I2C0_SDA__GPIO_3_25                    MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26                MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
-#define MX28_PAD_SPDIF__GPIO_3_27                       MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM3__GPIO_3_28                        MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
-#define MX28_PAD_PWM4__GPIO_3_29                        MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
-#define MX28_PAD_LCD_RESET__GPIO_3_30                   MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
-
-#define MX28_PAD_ENET0_MDC__GPIO_4_0                    MXS_IOMUX_PAD_NAKED(4,  0, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_MDIO__GPIO_4_1                   MXS_IOMUX_PAD_NAKED(4,  1, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_EN__GPIO_4_2                  MXS_IOMUX_PAD_NAKED(4,  2, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD0__GPIO_4_3                   MXS_IOMUX_PAD_NAKED(4,  3, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD1__GPIO_4_4                   MXS_IOMUX_PAD_NAKED(4,  4, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5                 MXS_IOMUX_PAD_NAKED(4,  5, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TX_EN__GPIO_4_6                  MXS_IOMUX_PAD_NAKED(4,  6, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD0__GPIO_4_7                   MXS_IOMUX_PAD_NAKED(4,  7, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD1__GPIO_4_8                   MXS_IOMUX_PAD_NAKED(4,  8, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD2__GPIO_4_9                   MXS_IOMUX_PAD_NAKED(4,  9, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RXD3__GPIO_4_10                  MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD2__GPIO_4_11                  MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_TXD3__GPIO_4_12                  MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13                MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_COL__GPIO_4_14                   MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET0_CRS__GPIO_4_15                   MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
-#define MX28_PAD_ENET_CLK__GPIO_4_16                    MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
-#define MX28_PAD_JTAG_RTCK__GPIO_4_20                   MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
-
-#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
deleted file mode 100644
index 7abdf58b8bb7..000000000000
--- a/arch/arm/mach-mxs/include/mach/iomux.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                      <armlinux@phytec.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_IOMUX_H__
-#define __MACH_MXS_IOMUX_H__
-
-/*
- * IOMUX/PAD Bit field definitions
- *
- * PAD_BANK:             0..2   (3)
- * PAD_PIN:              3..7   (5)
- * PAD_MUXSEL:           8..9   (2)
- * PAD_MA:              10..11  (2)
- * PAD_MA_VALID:        12      (1)
- * PAD_VOL:             13      (1)
- * PAD_VOL_VALID:       14      (1)
- * PAD_PULL:            15      (1)
- * PAD_PULL_VALID:      16      (1)
- * RESERVED:            17..31  (15)
- */
-typedef u32 iomux_cfg_t;
-
-#define MXS_PAD_BANK_SHIFT      0
-#define MXS_PAD_BANK_MASK       ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
-#define MXS_PAD_PIN_SHIFT       3
-#define MXS_PAD_PIN_MASK        ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
-#define MXS_PAD_MUXSEL_SHIFT    8
-#define MXS_PAD_MUXSEL_MASK     ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
-#define MXS_PAD_MA_SHIFT        10
-#define MXS_PAD_MA_MASK         ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
-#define MXS_PAD_MA_VALID_SHIFT  12
-#define MXS_PAD_MA_VALID_MASK   ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
-#define MXS_PAD_VOL_SHIFT       13
-#define MXS_PAD_VOL_MASK        ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
-#define MXS_PAD_VOL_VALID_SHIFT 14
-#define MXS_PAD_VOL_VALID_MASK  ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
-#define MXS_PAD_PULL_SHIFT      15
-#define MXS_PAD_PULL_MASK       ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
-#define MXS_PAD_PULL_VALID_SHIFT 16
-#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
-
-#define PAD_MUXSEL_0            0
-#define PAD_MUXSEL_1            1
-#define PAD_MUXSEL_2            2
-#define PAD_MUXSEL_GPIO         3
-
-#define PAD_4MA                 0
-#define PAD_8MA                 1
-#define PAD_12MA                2
-#define PAD_16MA                3
-
-#define PAD_1V8                 0
-#define PAD_3V3                 1
-
-#define PAD_NOPULL              0
-#define PAD_PULLUP              1
-
-#define MXS_PAD_4MA     ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_8MA     ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_12MA    ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-#define MXS_PAD_16MA    ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
-                                        MXS_PAD_MA_VALID_MASK)
-
-#define MXS_PAD_1V8     ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-#define MXS_PAD_3V3     ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
-                                        MXS_PAD_VOL_VALID_MASK)
-
-#define MXS_PAD_NOPULL  ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-#define MXS_PAD_PULLUP  ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
-                                        MXS_PAD_PULL_VALID_MASK)
-
-/* generic pad control used in most cases */
-#define MXS_PAD_CTRL    (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL)
-
-#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull)           \
-                (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) |         \
-                ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) |            \
-                ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) |      \
-                ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) |              \
-                ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) |            \
-                ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
-
-/*
- * A pad becomes naked, when none of mA, vol or pull
- * validity bits is set.
- */
-#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
-                MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
-
-static inline unsigned int PAD_BANK(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
-}
-
-static inline unsigned int PAD_PIN(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
-}
-
-static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
-}
-
-static inline unsigned int PAD_MA(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
-}
-
-static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_VOL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
-}
-
-static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
-}
-
-static inline unsigned int PAD_PULL(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
-}
-
-static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
-{
-        return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
-}
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad);
-
-/*
- * configures multiple pads
- * convenient way to call the above function with tables
- */
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
-
-#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
deleted file mode 100644
index 0e804e2f11f4..000000000000
--- a/arch/arm/mach-mxs/iomux.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
- *                       <armlinux@phytec.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/string.h>
-#include <linux/gpio.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mxs.h>
-#include <mach/iomux.h>
-
-/*
- * configures a single pad in the iomuxer
- */
-int mxs_iomux_setup_pad(iomux_cfg_t pad)
-{
-        u32 reg, ofs, bp, bm;
-        void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
-
-        /* muxsel */
-        ofs = 0x100;
-        ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
-        bp = PAD_PIN(pad) % 16 * 2;
-        bm = 0x3 << bp;
-        reg = __raw_readl(iomux_base + ofs);
-        reg &= ~bm;
-        reg |= PAD_MUXSEL(pad) << bp;
-        __raw_writel(reg, iomux_base + ofs);
-
-        /* drive */
-        ofs = cpu_is_mx23() ? 0x200 : 0x300;
-        ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
-        /* mA */
-        if (PAD_MA_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4;
-                bm = 0x3 << bp;
-                reg = __raw_readl(iomux_base + ofs);
-                reg &= ~bm;
-                reg |= PAD_MA(pad) << bp;
-                __raw_writel(reg, iomux_base + ofs);
-        }
-        /* vol */
-        if (PAD_VOL_VALID(pad)) {
-                bp = PAD_PIN(pad) % 8 * 4 + 2;
-                if (PAD_VOL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-
-        /* pull */
-        if (PAD_PULL_VALID(pad)) {
-                ofs = cpu_is_mx23() ? 0x400 : 0x600;
-                ofs += PAD_BANK(pad) * 0x10;
-                bp = PAD_PIN(pad);
-                if (PAD_PULL(pad))
-                        __mxs_setl(1 << bp, iomux_base + ofs);
-                else
-                        __mxs_clrl(1 << bp, iomux_base + ofs);
-        }
-
-        return 0;
-}
-
-int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
-{
-        const iomux_cfg_t *p = pad_list;
-        int i;
-        int ret;
-
-        for (i = 0; i < count; i++) {
-                ret = mxs_iomux_setup_pad(*p);
-                if (ret)
-                        return ret;
-                p++;
-        }
-
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/mach-apx4devkit.c b/arch/arm/mach-mxs/mach-apx4devkit.c
deleted file mode 100644
index f5f061757deb..000000000000
--- a/arch/arm/mach-mxs/mach-apx4devkit.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (C) 2011-2012
- * Lauri Hintsala, Bluegiga, <lauri.hintsala@bluegiga.com>
- * Veli-Pekka Peltola, Bluegiga, <veli-pekka.peltola@bluegiga.com>
- *
- * based on: mach-mx28evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/micrel_phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define APX4DEVKIT_GPIO_USERLED MXS_GPIO_NR(3, 28)
-
-static const iomux_cfg_t apx4devkit_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-
-        /* auart1 */
-        MX28_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-
-        /* auart2 */
-        MX28_PAD_SSP2_SCK__AUART2_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_MOSI__AUART2_TX | MXS_PAD_CTRL,
-
-        /* auart3 */
-        MX28_PAD_SSP2_MISO__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_SSP2_SS0__AUART3_TX | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-
-        /* i2c */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led apx4devkit_leds[] __initconst = {
-        {
-                .name = "user-led",
-                .default_trigger = "heartbeat",
-                .gpio = APX4DEVKIT_GPIO_USERLED,
-        },
-};
-
-static const struct gpio_led_platform_data apx4devkit_led_data __initconst = {
-        .leds = apx4devkit_leds,
-        .num_leds = ARRAY_SIZE(apx4devkit_leds),
-};
-
-static const struct fec_platform_data mx28_fec_pdata __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct mxs_mmc_platform_data apx4devkit_mmc_pdata __initconst = {
-        .wp_gpio = -EINVAL,
-        .flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static const struct i2c_board_info apx4devkit_i2c_boardinfo[] __initconst = {
-        { I2C_BOARD_INFO("sgtl5000", 0x0a) }, /* ASoC */
-        { I2C_BOARD_INFO("pcf8563", 0x51) }, /* RTC */
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || \
-                defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply apx4devkit_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data apx4devkit_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = apx4devkit_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(apx4devkit_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config apx4devkit_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &apx4devkit_vdd_reg_init_data,
-};
-
-static struct platform_device apx4devkit_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &apx4devkit_vdd_pdata,
-        },
-};
-
-static void __init apx4devkit_add_regulators(void)
-{
-        platform_device_register(&apx4devkit_voltage_regulator);
-}
-#else
-static void __init apx4devkit_add_regulators(void) {}
-#endif
-
-static const struct mxs_saif_platform_data
-                        apx4devkit_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-
-static int apx4devkit_phy_fixup(struct phy_device *phy)
-{
-        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
-        return 0;
-}
-
-static void __init apx4devkit_fec_phy_clk_enable(void)
-{
-        struct clk *clk;
-
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-}
-
-static void __init apx4devkit_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(apx4devkit_pads,
-                        ARRAY_SIZE(apx4devkit_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart1();
-        mx28_add_auart2();
-        mx28_add_auart3();
-
-        /*
-         * Register fixup for the Micrel KS8031 PHY clock
-         * (shares same ID with KS8051)
-         */
-        phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
-                        apx4devkit_phy_fixup);
-
-        apx4devkit_fec_phy_clk_enable();
-        mx28_add_fec(0, &mx28_fec_pdata);
-
-        mx28_add_mxs_mmc(0, &apx4devkit_mmc_pdata);
-
-        gpio_led_register_device(0, &apx4devkit_led_data);
-
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &apx4devkit_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &apx4devkit_mxs_saif_pdata[1]);
-
-        apx4devkit_add_regulators();
-
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, apx4devkit_i2c_boardinfo,
-                        ARRAY_SIZE(apx4devkit_i2c_boardinfo));
-
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0, NULL, 0);
-}
-
-static void __init apx4devkit_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer apx4devkit_timer = {
-        .init   = apx4devkit_timer_init,
-};
-
-MACHINE_START(APX4DEVKIT, "Bluegiga APX4 Development Kit")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &apx4devkit_timer,
-        .init_machine   = apx4devkit_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
deleted file mode 100644
index 4c00c879b893..000000000000
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-
-#define M28EVK_GPIO_USERLED1    MXS_GPIO_NR(3, 16)
-#define M28EVK_GPIO_USERLED2    MXS_GPIO_NR(3, 17)
-
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define M28EVK_LCD_ENABLE       MXS_GPIO_NR(3, 28)
-
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-
-static const iomux_cfg_t m28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_AUART0_CTS__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-
-        MX28_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL,
-
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__GPIO_3_17 | MXS_PAD_CTRL,
-
-        /* nand */
-        MX28_PAD_GPMI_D00__GPMI_D0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D01__GPMI_D1 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D02__GPMI_D2 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D03__GPMI_D3 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D04__GPMI_D4 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D05__GPMI_D5 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D06__GPMI_D6 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_D07__GPMI_D7 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_CE0N__GPMI_CE0N |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDY0__GPMI_READY0 |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_RDN__GPMI_RDN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_WRN__GPMI_WRN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_ALE__GPMI_ALE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_CLE__GPMI_CLE |
-                (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RESETN__GPMI_RESETN |
-                (MXS_PAD_12MA | MXS_PAD_1V8 | MXS_PAD_PULLUP),
-
-        /* Backlight */
-        MX28_PAD_PWM3__GPIO_3_28 | MXS_PAD_CTRL,
-};
-
-/* led */
-static const struct gpio_led m28evk_leds[] __initconst = {
-        {
-                .name = "user-led1",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED1,
-        },
-        {
-                .name = "user-led2",
-                .default_trigger = "heartbeat",
-                .gpio = M28EVK_GPIO_USERLED2,
-        },
-};
-
-static const struct gpio_led_platform_data m28evk_led_data __initconst = {
-        .leds = m28evk_leds,
-        .num_leds = ARRAY_SIZE(m28evk_leds),
-};
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-
-static int __init m28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-
-        if (!ocotp)
-                return -ETIMEDOUT;
-
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code DENX OUI (C0:E5:4E) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0xC0;
-                mx28_fec_pdata[i].mac[1] = 0xE5;
-                mx28_fec_pdata[i].mac[2] = 0x4E;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-
-        return 0;
-}
-
-/* mxsfb (lcdif) */
-static struct fb_videomode m28evk_video_modes[] = {
-        {
-                .name           = "Ampire AM-800480R2TMQW-T01H",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 30066, /* picosecond (33.26 MHz) */
-                .left_margin    = 0,
-                .right_margin   = 256,
-                .upper_margin   = 0,
-                .lower_margin   = 45,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data m28evk_mxsfb_pdata __initconst = {
-        .mode_list      = m28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(m28evk_video_modes),
-        .default_bpp    = 16,
-        .ld_intf_width  = STMLCDIF_18BIT,
-};
-
-static struct at24_platform_data m28evk_eeprom = {
-        .byte_len = 16384,
-        .page_size = 32,
-        .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info m28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("at24", 0x51),   /* E0=1, E1=0, E2=0 */
-                .platform_data = &m28evk_eeprom,
-        },
-};
-
-static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-
-static void __init m28evk_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-
-        if (!m28evk_fec_get_mac()) {
-                mx28_add_fec(0, &mx28_fec_pdata[0]);
-                mx28_add_fec(1, &mx28_fec_pdata[1]);
-        }
-
-        mx28_add_flexcan(0, NULL);
-        mx28_add_flexcan(1, NULL);
-
-        mx28_add_mxsfb(&m28evk_mxsfb_pdata);
-
-        mx28_add_mxs_mmc(0, &m28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &m28evk_mmc_pdata[1]);
-
-        gpio_led_register_device(0, &m28evk_led_data);
-
-        /* I2C */
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, m28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(m28_stk5v3_i2c_boardinfo));
-}
-
-static void __init m28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer m28evk_timer = {
-        .init   = m28evk_timer_init,
-};
-
-MACHINE_START(M28EVK, "DENX M28 EVK")
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &m28evk_timer,
-        .init_machine   = m28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
deleted file mode 100644
index e7272a41939d..000000000000
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define MX23EVK_LCD_ENABLE      MXS_GPIO_NR(1, 18)
-#define MX23EVK_BL_ENABLE       MXS_GPIO_NR(1, 28)
-#define MX23EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(1, 30)
-#define MX23EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(1, 29)
-
-static const iomux_cfg_t mx23evk_pads[] __initconst = {
-        /* duart */
-        MX23_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX23_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_TX__AUART1_TX | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | MXS_PAD_CTRL,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | MXS_PAD_CTRL,
-
-        /* mxsfb (lcdif) */
-        MX23_PAD_LCD_D00__LCD_D00 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D01__LCD_D01 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D02__LCD_D02 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D03__LCD_D03 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D04__LCD_D04 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D05__LCD_D05 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D06__LCD_D06 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D07__LCD_D07 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D08__LCD_D08 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D09__LCD_D09 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D08__LCD_D18 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D09__LCD_D19 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D10__LCD_D20 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D11__LCD_D21 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D12__LCD_D22 | MXS_PAD_CTRL,
-        MX23_PAD_GPMI_D13__LCD_D23 | MXS_PAD_CTRL,
-        MX23_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL,
-        MX23_PAD_LCD_DOTCK__LCD_DOTCK | MXS_PAD_CTRL,
-        MX23_PAD_LCD_ENABLE__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX23_PAD_LCD_RESET__GPIO_1_18 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_CTRL,
-
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D08__SSP1_DATA4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D09__SSP1_DATA5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D10__SSP1_DATA6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_GPMI_D11__SSP1_DATA7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX23_PAD_PWM4__GPIO_1_30 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX23_PAD_PWM3__GPIO_1_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx23evk_video_modes[] = {
-        {
-                .name           = "Samsung-LMS430HF02",
-                .refresh        = 60,
-                .xres           = 480,
-                .yres           = 272,
-                .pixclock       = 108096, /* picosecond (9.2 MHz) */
-                .left_margin    = 15,
-                .right_margin   = 8,
-                .upper_margin   = 12,
-                .lower_margin   = 4,
-                .hsync_len      = 1,
-                .vsync_len      = 1,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data mx23evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx23evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx23evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx23evk_mmc_pdata __initdata = {
-        .wp_gpio = MX23EVK_MMC0_WRITE_PROTECT,
-        .flags = SLOTF_8_BIT_CAPABLE,
-};
-
-static void __init mx23evk_init(void)
-{
-        int ret;
-
-        mx23_soc_init();
-
-        mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
-
-        mx23_add_duart();
-        mx23_add_auart0();
-
-        /* power on mmc slot by writing 0 to the gpio */
-        ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
-                               "mmc0-slot-power");
-        if (ret)
-                pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
-        mx23_add_mxs_mmc(0, &mx23evk_mmc_pdata);
-
-        ret = gpio_request_one(MX23EVK_LCD_ENABLE, GPIOF_DIR_OUT, "lcd-enable");
-        if (ret)
-                pr_warn("failed to request gpio lcd-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_LCD_ENABLE, 1);
-
-        ret = gpio_request_one(MX23EVK_BL_ENABLE, GPIOF_DIR_OUT, "bl-enable");
-        if (ret)
-                pr_warn("failed to request gpio bl-enable: %d\n", ret);
-        else
-                gpio_set_value(MX23EVK_BL_ENABLE, 1);
-
-        mx23_add_mxsfb(&mx23evk_mxsfb_pdata);
-        mx23_add_rtc_stmp3xxx();
-}
-
-static void __init mx23evk_timer_init(void)
-{
-        mx23_clocks_init();
-}
-
-static struct sys_timer mx23evk_timer = {
-        .init   = mx23evk_timer_init,
-};
-
-MACHINE_START(MX23EVK, "Freescale MX23 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &mx23evk_timer,
-        .init_machine   = mx23evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
deleted file mode 100644
index dafd48e86c8c..000000000000
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ /dev/null
@@ -1,477 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-#include <mach/digctl.h>
-
-#include "devices-mx28.h"
-
-#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
-#define MX28EVK_FEC_PHY_POWER   MXS_GPIO_NR(2, 15)
-#define MX28EVK_GPIO_LED        MXS_GPIO_NR(3, 5)
-#define MX28EVK_BL_ENABLE       MXS_GPIO_NR(3, 18)
-#define MX28EVK_LCD_ENABLE      MXS_GPIO_NR(3, 30)
-#define MX28EVK_FEC_PHY_RESET   MXS_GPIO_NR(4, 13)
-
-#define MX28EVK_MMC0_WRITE_PROTECT      MXS_GPIO_NR(2, 12)
-#define MX28EVK_MMC1_WRITE_PROTECT      MXS_GPIO_NR(0, 28)
-#define MX28EVK_MMC0_SLOT_POWER         MXS_GPIO_NR(3, 28)
-#define MX28EVK_MMC1_SLOT_POWER         MXS_GPIO_NR(3, 29)
-
-static const iomux_cfg_t mx28evk_pads[] __initconst = {
-        /* duart */
-        MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
-        MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
-
-        /* auart0 */
-        MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
-        /* auart3 */
-        MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
-        MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
-
-#define MXS_PAD_FEC     (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
-        /* fec0 */
-        MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
-        /* fec1 */
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
-        /* phy power line */
-        MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
-        /* phy reset line */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
-
-        /* flexcan0 */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-        /* flexcan1 */
-        MX28_PAD_GPMI_CE2N__CAN1_TX,
-        MX28_PAD_GPMI_CE3N__CAN1_RX,
-        /* transceiver power control */
-        MX28_PAD_SSP1_CMD__GPIO_2_13,
-
-        /* mxsfb (lcdif) */
-        MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL,
-        MX28_PAD_LCD_CS__LCD_ENABLE | MXS_PAD_CTRL,
-        /* LCD panel enable */
-        MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL,
-        /* backlight control */
-        MX28_PAD_PWM2__GPIO_3_18 | MXS_PAD_CTRL,
-        /* mmc0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA4__SSP0_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA5__SSP0_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA6__SSP0_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA7__SSP0_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_SSP1_SCK__GPIO_2_12 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM3__GPIO_3_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* mmc1 */
-        MX28_PAD_GPMI_D00__SSP1_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D01__SSP1_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D02__SSP1_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D03__SSP1_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D04__SSP1_D4 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D05__SSP1_D5 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D06__SSP1_D6 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_D07__SSP1_D7 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY1__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_GPMI_WRN__SSP1_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* write protect */
-        MX28_PAD_GPMI_RESETN__GPIO_0_28 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        /* slot power enable */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-
-        /* led */
-        MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_I2C0_SDA__I2C0_SDA |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-
-        /* saif0 & saif1 */
-        MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-};
-
-/* led */
-static const struct gpio_led mx28evk_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = MX28EVK_GPIO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
-        .leds = mx28evk_leds,
-        .num_leds = ARRAY_SIZE(mx28evk_leds),
-};
-
-/* fec */
-static void __init mx28evk_fec_reset(void)
-{
-        struct clk *clk;
-
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 0);
-        mdelay(1);
-        gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
-}
-
-static struct fec_platform_data mx28_fec_pdata[] __initdata = {
-        {
-                /* fec0 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        }, {
-                /* fec1 */
-                .phy = PHY_INTERFACE_MODE_RMII,
-        },
-};
-
-static int __init mx28evk_fec_get_mac(void)
-{
-        int i;
-        u32 val;
-        const u32 *ocotp = mxs_get_ocotp();
-
-        if (!ocotp)
-                return -ETIMEDOUT;
-
-        /*
-         * OCOTP only stores the last 4 octets for each mac address,
-         * so hard-code Freescale OUI (00:04:9f) here.
-         */
-        for (i = 0; i < 2; i++) {
-                val = ocotp[i];
-                mx28_fec_pdata[i].mac[0] = 0x00;
-                mx28_fec_pdata[i].mac[1] = 0x04;
-                mx28_fec_pdata[i].mac[2] = 0x9f;
-                mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
-                mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
-                mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
-        }
-
-        return 0;
-}
-
-/*
- * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
- */
-static int flexcan0_en, flexcan1_en;
-
-static void mx28evk_flexcan_switch(void)
-{
-        if (flexcan0_en || flexcan1_en)
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
-        else
-                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
-}
-
-static void mx28evk_flexcan0_switch(int enable)
-{
-        flexcan0_en = enable;
-        mx28evk_flexcan_switch();
-}
-
-static void mx28evk_flexcan1_switch(int enable)
-{
-        flexcan1_en = enable;
-        mx28evk_flexcan_switch();
-}
-
-static const struct flexcan_platform_data
-                mx28evk_flexcan_pdata[] __initconst = {
-        {
-                .transceiver_switch = mx28evk_flexcan0_switch,
-        }, {
-                .transceiver_switch = mx28evk_flexcan1_switch,
-        }
-};
-
-/* mxsfb (lcdif) */
-static struct fb_videomode mx28evk_video_modes[] = {
-        {
-                .name           = "Seiko-43WVF1G",
-                .refresh        = 60,
-                .xres           = 800,
-                .yres           = 480,
-                .pixclock       = 29851, /* picosecond (33.5 MHz) */
-                .left_margin    = 89,
-                .right_margin   = 164,
-                .upper_margin   = 23,
-                .lower_margin   = 10,
-                .hsync_len      = 10,
-                .vsync_len      = 10,
-                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
-                                  FB_SYNC_DOTCLK_FAILING_ACT,
-        },
-};
-
-static const struct mxsfb_platform_data mx28evk_mxsfb_pdata __initconst = {
-        .mode_list      = mx28evk_video_modes,
-        .mode_count     = ARRAY_SIZE(mx28evk_video_modes),
-        .default_bpp    = 32,
-        .ld_intf_width  = STMLCDIF_24BIT,
-};
-
-static struct mxs_mmc_platform_data mx28evk_mmc_pdata[] __initdata = {
-        {
-                /* mmc0 */
-                .wp_gpio = MX28EVK_MMC0_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        }, {
-                /* mmc1 */
-                .wp_gpio = MX28EVK_MMC1_WRITE_PROTECT,
-                .flags = SLOTF_8_BIT_CAPABLE,
-        },
-};
-
-static struct i2c_board_info mxs_i2c0_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("sgtl5000", 0x0a),
-        },
-};
-
-#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
-static struct regulator_consumer_supply mx28evk_audio_consumer_supplies[] = {
-        REGULATOR_SUPPLY("VDDA", "0-000a"),
-        REGULATOR_SUPPLY("VDDIO", "0-000a"),
-};
-
-static struct regulator_init_data mx28evk_vdd_reg_init_data = {
-        .constraints    = {
-                .name   = "3V3",
-                .always_on = 1,
-        },
-        .consumer_supplies = mx28evk_audio_consumer_supplies,
-        .num_consumer_supplies = ARRAY_SIZE(mx28evk_audio_consumer_supplies),
-};
-
-static struct fixed_voltage_config mx28evk_vdd_pdata = {
-        .supply_name    = "board-3V3",
-        .microvolts     = 3300000,
-        .gpio           = -EINVAL,
-        .enabled_at_boot = 1,
-        .init_data      = &mx28evk_vdd_reg_init_data,
-};
-static struct platform_device mx28evk_voltage_regulator = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &mx28evk_vdd_pdata,
-        },
-};
-static void __init mx28evk_add_regulators(void)
-{
-        platform_device_register(&mx28evk_voltage_regulator);
-}
-#else
-static void __init mx28evk_add_regulators(void) {}
-#endif
-
-static const struct gpio mx28evk_gpios[] __initconst = {
-        { MX28EVK_LCD_ENABLE, GPIOF_OUT_INIT_HIGH, "lcd-enable" },
-        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
-        { MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT, "flexcan-switch" },
-        { MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc0-slot-power" },
-        { MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW, "mmc1-slot-power" },
-        { MX28EVK_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
-        { MX28EVK_FEC_PHY_RESET, GPIOF_DIR_OUT, "fec-phy-reset" },
-};
-
-static const struct mxs_saif_platform_data
-                        mx28evk_mxs_saif_pdata[] __initconst = {
-        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
-        {
-                .master_mode = 1,
-                .master_id = 0,
-        }, {
-                .master_mode = 0,
-                .master_id = 0,
-        },
-};
-
-static void __init mx28evk_init(void)
-{
-        int ret;
-
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
-
-        mx28_add_duart();
-        mx28_add_auart0();
-        mx28_add_auart3();
-
-        if (mx28evk_fec_get_mac())
-                pr_warn("%s: failed on fec mac setup\n", __func__);
-
-        ret = gpio_request_array(mx28evk_gpios, ARRAY_SIZE(mx28evk_gpios));
-        if (ret)
-                pr_err("One or more GPIOs failed to be requested: %d\n", ret);
-
-        mx28evk_fec_reset();
-        mx28_add_fec(0, &mx28_fec_pdata[0]);
-        mx28_add_fec(1, &mx28_fec_pdata[1]);
-
-        mx28_add_flexcan(0, &mx28evk_flexcan_pdata[0]);
-        mx28_add_flexcan(1, &mx28evk_flexcan_pdata[1]);
-
-        mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-
-        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
-        mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
-
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, mxs_i2c0_board_info,
-                                ARRAY_SIZE(mxs_i2c0_board_info));
-
-        mx28evk_add_regulators();
-
-        mxs_add_platform_device("mxs-sgtl5000", 0, NULL, 0,
-                        NULL, 0);
-
-        mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
-        mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
-
-        mx28_add_rtc_stmp3xxx();
-
-        gpio_led_register_device(0, &mx28evk_led_data);
-}
-
-static void __init mx28evk_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer mx28evk_timer = {
-        .init   = mx28evk_timer_init,
-};
-
-MACHINE_START(MX28EVK, "Freescale MX28 EVK")
-        /* Maintainer: Freescale Semiconductor, Inc. */
-        .map_io         = mx28_map_io,
-        .init_irq       = mx28_init_irq,
-        .timer          = &mx28evk_timer,
-        .init_machine   = mx28evk_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index ff886e01a0b0..cf43e5effb91 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -12,8 +12,10 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/can/platform/flexcan.h>
+#include <linux/delay.h>
 #include <linux/err.h>
-#include <linux/init.h>
+#include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/irqdomain.h>
 #include <linux/micrel_phy.h>
@@ -21,9 +23,12 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
+#include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
+#include <mach/digctl.h>
+#include <mach/mxs.h>
 
 static struct fb_videomode mx23evk_video_modes[] = {
         {
@@ -99,9 +104,40 @@ static struct fb_videomode apx4devkit_video_modes[] = {
 
 static struct mxsfb_platform_data mxsfb_pdata __initdata;
 
+/*
+ * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
+ */
+#define MX28EVK_FLEXCAN_SWITCH  MXS_GPIO_NR(2, 13)
+
+static int flexcan0_en, flexcan1_en;
+
+static void mx28evk_flexcan_switch(void)
+{
+        if (flexcan0_en || flexcan1_en)
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
+        else
+                gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
+}
+
+static void mx28evk_flexcan0_switch(int enable)
+{
+        flexcan0_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static void mx28evk_flexcan1_switch(int enable)
+{
+        flexcan1_en = enable;
+        mx28evk_flexcan_switch();
+}
+
+static struct flexcan_platform_data flexcan_pdata[2];
+
 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
         OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
+        OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
         { /* sentinel */ }
 };
 
@@ -237,13 +273,21 @@ static void __init imx28_evk_init(void)
         mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
         mxsfb_pdata.default_bpp = 32;
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
 }
 
-static void __init m28evk_init(void)
+static void __init imx28_evk_post_init(void)
 {
-        enable_clk_enet_out();
-        update_fec_mac_prop(OUI_DENX);
+        if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
+                              "flexcan-switch")) {
+                flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
+                flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
+        }
+}
 
+static void __init m28evk_init(void)
+{
         mxsfb_pdata.mode_list = m28evk_video_modes;
         mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
         mxsfb_pdata.default_bpp = 16;
@@ -270,6 +314,80 @@ static void __init apx4devkit_init(void)
         mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
 }
 
+#define ENET0_MDC__GPIO_4_0     MXS_GPIO_NR(4, 0)
+#define ENET0_MDIO__GPIO_4_1    MXS_GPIO_NR(4, 1)
+#define ENET0_RX_EN__GPIO_4_2   MXS_GPIO_NR(4, 2)
+#define ENET0_RXD0__GPIO_4_3    MXS_GPIO_NR(4, 3)
+#define ENET0_RXD1__GPIO_4_4    MXS_GPIO_NR(4, 4)
+#define ENET0_TX_EN__GPIO_4_6   MXS_GPIO_NR(4, 6)
+#define ENET0_TXD0__GPIO_4_7    MXS_GPIO_NR(4, 7)
+#define ENET0_TXD1__GPIO_4_8    MXS_GPIO_NR(4, 8)
+#define ENET_CLK__GPIO_4_16     MXS_GPIO_NR(4, 16)
+
+#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
+#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
+#define TX28_FEC_nINT           MXS_GPIO_NR(4, 5)
+
+static const struct gpio tx28_gpios[] __initconst = {
+        { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
+        { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
+        { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
+        { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
+        { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
+        { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
+        { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
+        { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
+        { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
+        { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
+        { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
+        { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
+};
+
+static void __init tx28_post_init(void)
+{
+        struct device_node *np;
+        struct platform_device *pdev;
+        struct pinctrl *pctl;
+        int ret;
+
+        enable_clk_enet_out();
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
+        pdev = of_find_device_by_node(np);
+        if (!pdev) {
+                pr_err("%s: failed to find fec device\n", __func__);
+                return;
+        }
+
+        pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
+        if (IS_ERR(pctl)) {
+                pr_err("%s: failed to get pinctrl state\n", __func__);
+                return;
+        }
+
+        ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
+        if (ret) {
+                pr_err("%s: failed to request gpios: %d\n", __func__, ret);
+                return;
+        }
+
+        /* Power up fec phy */
+        gpio_set_value(TX28_FEC_PHY_POWER, 1);
+        msleep(26); /* 25ms according to data sheet */
+
+        /* Mode strap pins */
+        gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
+        gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
+        gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
+
+        udelay(100); /* minimum assertion time for nRST */
+
+        /* Deasserting FEC PHY RESET */
+        gpio_set_value(TX28_FEC_PHY_RESET, 1);
+
+        pinctrl_put(pctl);
+}
+
 static void __init mxs_machine_init(void)
 {
         if (of_machine_is_compatible("fsl,imx28-evk"))
@@ -283,22 +401,20 @@ static void __init mxs_machine_init(void)
 
         of_platform_populate(NULL, of_default_bus_match_table,
                              mxs_auxdata_lookup, NULL);
+
+        if (of_machine_is_compatible("karo,tx28"))
+                tx28_post_init();
+
+        if (of_machine_is_compatible("fsl,imx28-evk"))
+                imx28_evk_post_init();
 }
 
 static const char *imx23_dt_compat[] __initdata = {
-        "fsl,imx23-evk",
-        "fsl,stmp378x_devb"
-        "olimex,imx23-olinuxino",
         "fsl,imx23",
         NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
-        "bluegiga,apx4devkit",
-        "crystalfontz,cfa10036",
-        "denx,m28evk",
-        "fsl,imx28-evk",
-        "karo,tx28",
         "fsl,imx28",
         NULL,
 };
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
deleted file mode 100644
index 6548965e4a76..000000000000
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * board setup for STMP378x-Development-Board
- *
- * based on mx23evk board setup and information gained form the original
- * plat-stmp based board setup, now converted to mach-mxs.
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx23.h>
-
-#include "devices-mx23.h"
-
-#define STMP378X_DEVB_MMC0_WRITE_PROTECT        MXS_GPIO_NR(1, 30)
-#define STMP378X_DEVB_MMC0_SLOT_POWER           MXS_GPIO_NR(1, 29)
-
-#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
-
-static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
-        /* duart (extended setup missing in old boardcode, too */
-        MX23_PAD_PWM0__DUART_RX,
-        MX23_PAD_PWM1__DUART_TX,
-
-        /* auart */
-        MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
-        MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
-
-        /* mmc */
-        MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_CMD__SSP1_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX23_PAD_SSP1_DETECT__SSP1_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_SSP1_SCK__SSP1_SCK |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
-        MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
-};
-
-static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
-        .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
-        {
-                .modalias       = "enc28j60",
-                .max_speed_hz   = 6 * 1000 * 1000,
-                .bus_num        = 1,
-                .chip_select    = 0,
-                .platform_data  = NULL,
-        },
-#endif
-};
-
-static void __init stmp378x_dvb_init(void)
-{
-        int ret;
-
-        mx23_soc_init();
-
-        mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
-                        ARRAY_SIZE(stmp378x_dvb_pads));
-
-        mx23_add_duart();
-        mx23_add_auart0();
-        mx23_add_rtc_stmp3xxx();
-
-        /* power on mmc slot */
-        ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
-                GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
-        if (ret)
-                pr_warn("could not power mmc (%d)\n", ret);
-
-        mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
-
-        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-}
-
-static void __init stmp378x_dvb_timer_init(void)
-{
-        mx23_clocks_init();
-}
-
-static struct sys_timer stmp378x_dvb_timer = {
-        .init   = stmp378x_dvb_timer_init,
-};
-
-MACHINE_START(STMP378X, "STMP378X")
-        .map_io         = mx23_map_io,
-        .init_irq       = mx23_init_irq,
-        .timer          = &stmp378x_dvb_timer,
-        .init_machine   = stmp378x_dvb_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
deleted file mode 100644
index 8837029de1a4..000000000000
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * based on: mach-mx28_evk.c
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/spi_gpio.h>
-#include <linux/i2c.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx28.h>
-
-#include "devices-mx28.h"
-#include "module-tx28.h"
-
-#define TX28_STK5_GPIO_LED              MXS_GPIO_NR(4, 10)
-
-static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
-        /* LED */
-        MX28_PAD_ENET0_RXD3__GPIO_4_10 |
-                MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL,
-
-        /* framebuffer */
-#define LCD_MODE (MXS_PAD_3V3 | MXS_PAD_4MA)
-        MX28_PAD_LCD_D00__LCD_D0 | LCD_MODE,
-        MX28_PAD_LCD_D01__LCD_D1 | LCD_MODE,
-        MX28_PAD_LCD_D02__LCD_D2 | LCD_MODE,
-        MX28_PAD_LCD_D03__LCD_D3 | LCD_MODE,
-        MX28_PAD_LCD_D04__LCD_D4 | LCD_MODE,
-        MX28_PAD_LCD_D05__LCD_D5 | LCD_MODE,
-        MX28_PAD_LCD_D06__LCD_D6 | LCD_MODE,
-        MX28_PAD_LCD_D07__LCD_D7 | LCD_MODE,
-        MX28_PAD_LCD_D08__LCD_D8 | LCD_MODE,
-        MX28_PAD_LCD_D09__LCD_D9 | LCD_MODE,
-        MX28_PAD_LCD_D10__LCD_D10 | LCD_MODE,
-        MX28_PAD_LCD_D11__LCD_D11 | LCD_MODE,
-        MX28_PAD_LCD_D12__LCD_D12 | LCD_MODE,
-        MX28_PAD_LCD_D13__LCD_D13 | LCD_MODE,
-        MX28_PAD_LCD_D14__LCD_D14 | LCD_MODE,
-        MX28_PAD_LCD_D15__LCD_D15 | LCD_MODE,
-        MX28_PAD_LCD_D16__LCD_D16 | LCD_MODE,
-        MX28_PAD_LCD_D17__LCD_D17 | LCD_MODE,
-        MX28_PAD_LCD_D18__LCD_D18 | LCD_MODE,
-        MX28_PAD_LCD_D19__LCD_D19 | LCD_MODE,
-        MX28_PAD_LCD_D20__LCD_D20 | LCD_MODE,
-        MX28_PAD_LCD_D21__LCD_D21 | LCD_MODE,
-        MX28_PAD_LCD_D22__LCD_D22 | LCD_MODE,
-        MX28_PAD_LCD_D23__LCD_D23 | LCD_MODE,
-        MX28_PAD_LCD_RD_E__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_WR_RWN__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_RS__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_CS__LCD_CS | LCD_MODE,
-        MX28_PAD_LCD_VSYNC__LCD_VSYNC | LCD_MODE,
-        MX28_PAD_LCD_HSYNC__LCD_HSYNC | LCD_MODE,
-        MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | LCD_MODE,
-        MX28_PAD_LCD_ENABLE__GPIO_1_31 | LCD_MODE,
-        MX28_PAD_LCD_RESET__GPIO_3_30 | LCD_MODE,
-        MX28_PAD_PWM0__PWM_0 | LCD_MODE,
-
-        /* UART1 */
-        MX28_PAD_AUART0_CTS__DUART_RX,
-        MX28_PAD_AUART0_RTS__DUART_TX,
-        MX28_PAD_AUART0_TX__DUART_RTS,
-        MX28_PAD_AUART0_RX__DUART_CTS,
-
-        /* UART2 */
-        MX28_PAD_AUART1_RX__AUART1_RX,
-        MX28_PAD_AUART1_TX__AUART1_TX,
-        MX28_PAD_AUART1_RTS__AUART1_RTS,
-        MX28_PAD_AUART1_CTS__AUART1_CTS,
-
-        /* CAN */
-        MX28_PAD_GPMI_RDY2__CAN0_TX,
-        MX28_PAD_GPMI_RDY3__CAN0_RX,
-
-        /* I2C */
-        MX28_PAD_I2C0_SCL__I2C0_SCL,
-        MX28_PAD_I2C0_SDA__I2C0_SDA,
-
-        /* TSC2007 */
-        MX28_PAD_SAIF0_MCLK__GPIO_3_20 | MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP,
-
-        /* MMC0 */
-        MX28_PAD_SSP0_DATA0__SSP0_D0 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA1__SSP0_D1 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA2__SSP0_D2 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DATA3__SSP0_D3 |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_CMD__SSP0_CMD |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
-        MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-                (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-        MX28_PAD_SSP0_SCK__SSP0_SCK |
-                (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
-};
-
-static const struct gpio_led tx28_stk5v3_leds[] __initconst = {
-        {
-                .name = "GPIO-LED",
-                .default_trigger = "heartbeat",
-                .gpio = TX28_STK5_GPIO_LED,
-        },
-};
-
-static const struct gpio_led_platform_data tx28_stk5v3_led_data __initconst = {
-        .leds = tx28_stk5v3_leds,
-        .num_leds = ARRAY_SIZE(tx28_stk5v3_leds),
-};
-
-static struct spi_board_info tx28_spi_board_info[] = {
-        {
-                .modalias = "spidev",
-                .max_speed_hz = 20000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .controller_data = (void *)SPI_GPIO_NO_CHIPSELECT,
-                .mode = SPI_MODE_0,
-        },
-};
-
-static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
-        {
-                I2C_BOARD_INFO("ds1339", 0x68),
-        },
-};
-
-static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
-       .wp_gpio = -EINVAL,
-       .flags = SLOTF_4_BIT_CAPABLE,
-};
-
-static void __init tx28_stk5v3_init(void)
-{
-        mx28_soc_init();
-
-        mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
-                        ARRAY_SIZE(tx28_stk5v3_pads));
-
-        mx28_add_duart(); /* UART1 */
-        mx28_add_auart(1); /* UART2 */
-
-        tx28_add_fec0();
-        /* spi via ssp will be added when available */
-        spi_register_board_info(tx28_spi_board_info,
-                        ARRAY_SIZE(tx28_spi_board_info));
-        gpio_led_register_device(0, &tx28_stk5v3_led_data);
-        mx28_add_mxs_i2c(0);
-        i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
-                        ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
-        mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
-        mx28_add_rtc_stmp3xxx();
-}
-
-static void __init tx28_timer_init(void)
-{
-        mx28_clocks_init();
-}
-
-static struct sys_timer tx28_timer = {
-        .init = tx28_timer_init,
-};
-
-MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
-        .map_io = mx28_map_io,
-        .init_irq = mx28_init_irq,
-        .timer = &tx28_timer,
-        .init_machine = tx28_stk5v3_init,
-        .restart        = mxs_restart,
-MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
index dccb67a9e7c4..a4294aa9f301 100644
--- a/arch/arm/mach-mxs/mm.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -13,14 +13,11 @@
 
 #include <linux/mm.h>
 #include <linux/init.h>
-#include <linux/pinctrl/machine.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/mx23.h>
 #include <mach/mx28.h>
-#include <mach/common.h>
-#include <mach/iomux.h>
 
 /*
  * Define the MX23 memory map.
@@ -48,43 +45,7 @@ void __init mx23_map_io(void)
         iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
 }
 
-void __init mx23_init_irq(void)
-{
-        icoll_init_irq();
-}
-
 void __init mx28_map_io(void)
 {
         iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
 }
-
-void __init mx28_init_irq(void)
-{
-        icoll_init_irq();
-}
-
-void __init mx23_soc_init(void)
-{
-        pinctrl_provide_dummies();
-
-        mxs_add_dma("imx23-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx23-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-        mxs_add_gpio("imx23-gpio", 0, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO0);
-        mxs_add_gpio("imx23-gpio", 1, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO1);
-        mxs_add_gpio("imx23-gpio", 2, MX23_PINCTRL_BASE_ADDR, MX23_INT_GPIO2);
-}
-
-void __init mx28_soc_init(void)
-{
-        pinctrl_provide_dummies();
-
-        mxs_add_dma("imx28-dma-apbh", MX23_APBH_DMA_BASE_ADDR);
-        mxs_add_dma("imx28-dma-apbx", MX23_APBX_DMA_BASE_ADDR);
-
-        mxs_add_gpio("imx28-gpio", 0, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO0);
-        mxs_add_gpio("imx28-gpio", 1, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO1);
-        mxs_add_gpio("imx28-gpio", 2, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO2);
-        mxs_add_gpio("imx28-gpio", 3, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO3);
-        mxs_add_gpio("imx28-gpio", 4, MX28_PINCTRL_BASE_ADDR, MX28_INT_GPIO4);
-}
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
deleted file mode 100644
index 0f71f82101cc..000000000000
--- a/arch/arm/mach-mxs/module-tx28.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (C) 2010 <LW@KARO-electronics.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-
-#include <linux/delay.h>
-#include <linux/fec.h>
-#include <linux/gpio.h>
-
-#include <mach/iomux-mx28.h>
-#include "devices-mx28.h"
-
-#include "module-tx28.h"
-
-#define TX28_FEC_PHY_POWER      MXS_GPIO_NR(3, 29)
-#define TX28_FEC_PHY_RESET      MXS_GPIO_NR(4, 13)
-
-static const iomux_cfg_t tx28_fec_gpio_pads[] __initconst = {
-        /* PHY POWER */
-        MX28_PAD_PWM4__GPIO_3_29 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* PHY RESET */
-        MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-        /* Mode strap pins 0-2 */
-        MX28_PAD_ENET0_RXD0__GPIO_4_3 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RXD1__GPIO_4_4 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        MX28_PAD_ENET0_RX_EN__GPIO_4_2 |
-                MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3,
-        /* nINT */
-        MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
-                MXS_PAD_4MA | MXS_PAD_NOPULL | MXS_PAD_3V3,
-
-        MX28_PAD_ENET0_MDC__GPIO_4_0,
-        MX28_PAD_ENET0_MDIO__GPIO_4_1,
-        MX28_PAD_ENET0_TX_EN__GPIO_4_6,
-        MX28_PAD_ENET0_TXD0__GPIO_4_7,
-        MX28_PAD_ENET0_TXD1__GPIO_4_8,
-        MX28_PAD_ENET_CLK__GPIO_4_16,
-};
-
-#define FEC_MODE (MXS_PAD_8MA | MXS_PAD_PULLUP | MXS_PAD_3V3)
-static const iomux_cfg_t tx28_fec0_pads[] __initconst = {
-        MX28_PAD_ENET0_MDC__ENET0_MDC | FEC_MODE,
-        MX28_PAD_ENET0_MDIO__ENET0_MDIO | FEC_MODE,
-        MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | FEC_MODE,
-        MX28_PAD_ENET0_RXD0__ENET0_RXD0 | FEC_MODE,
-        MX28_PAD_ENET0_RXD1__ENET0_RXD1 | FEC_MODE,
-        MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | FEC_MODE,
-        MX28_PAD_ENET0_TXD0__ENET0_TXD0 | FEC_MODE,
-        MX28_PAD_ENET0_TXD1__ENET0_TXD1 | FEC_MODE,
-        MX28_PAD_ENET_CLK__CLKCTRL_ENET | FEC_MODE,
-};
-
-static const iomux_cfg_t tx28_fec1_pads[] __initconst = {
-        MX28_PAD_ENET0_RXD2__ENET1_RXD0,
-        MX28_PAD_ENET0_RXD3__ENET1_RXD1,
-        MX28_PAD_ENET0_TXD2__ENET1_TXD0,
-        MX28_PAD_ENET0_TXD3__ENET1_TXD1,
-        MX28_PAD_ENET0_COL__ENET1_TX_EN,
-        MX28_PAD_ENET0_CRS__ENET1_RX_EN,
-};
-
-static const struct fec_platform_data tx28_fec0_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-static const struct fec_platform_data tx28_fec1_data __initconst = {
-        .phy = PHY_INTERFACE_MODE_RMII,
-};
-
-int __init tx28_add_fec0(void)
-{
-        int i, ret;
-
-        pr_debug("%s: Switching FEC PHY power off\n", __func__);
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec_gpio_pads,
-                        ARRAY_SIZE(tx28_fec_gpio_pads));
-        for (i = 0; i < ARRAY_SIZE(tx28_fec_gpio_pads); i++) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-
-                ret = gpio_request(gpio, "FEC");
-                if (ret) {
-                        pr_err("Failed to request GPIO_%d_%d: %d\n",
-                                PAD_BANK(tx28_fec_gpio_pads[i]),
-                                PAD_PIN(tx28_fec_gpio_pads[i]), ret);
-                        goto free_gpios;
-                }
-                ret = gpio_direction_output(gpio, 0);
-                if (ret) {
-                        pr_err("Failed to set direction of GPIO_%d_%d to output: %d\n",
-                                        gpio / 32 + 1, gpio % 32, ret);
-                        goto free_gpios;
-                }
-        }
-
-        /* Power up fec phy */
-        pr_debug("%s: Switching FEC PHY power on\n", __func__);
-        ret = gpio_direction_output(TX28_FEC_PHY_POWER, 1);
-        if (ret) {
-                pr_err("Failed to power on PHY: %d\n", ret);
-                goto free_gpios;
-        }
-        mdelay(26); /* 25ms according to data sheet */
-
-        /* nINT */
-        gpio_direction_input(MXS_GPIO_NR(4, 5));
-        /* Mode strap pins */
-        gpio_direction_output(MXS_GPIO_NR(4, 2), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 3), 1);
-        gpio_direction_output(MXS_GPIO_NR(4, 4), 1);
-
-        udelay(100); /* minimum assertion time for nRST */
-
-        pr_debug("%s: Deasserting FEC PHY RESET\n", __func__);
-        gpio_set_value(TX28_FEC_PHY_RESET, 1);
-
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec0_pads,
-                        ARRAY_SIZE(tx28_fec0_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                goto free_gpios;
-        }
-        pr_debug("%s: Registering FEC0 device\n", __func__);
-        mx28_add_fec(0, &tx28_fec0_data);
-        return 0;
-
-free_gpios:
-        while (--i >= 0) {
-                unsigned int gpio = MXS_GPIO_NR(PAD_BANK(tx28_fec_gpio_pads[i]),
-                        PAD_PIN(tx28_fec_gpio_pads[i]));
-
-                gpio_free(gpio);
-        }
-
-        return ret;
-}
-
-int __init tx28_add_fec1(void)
-{
-        int ret;
-
-        ret = mxs_iomux_setup_multiple_pads(tx28_fec1_pads,
-                        ARRAY_SIZE(tx28_fec1_pads));
-        if (ret) {
-                pr_debug("%s: mxs_iomux_setup_multiple_pads() failed with rc: %d\n",
-                                __func__, ret);
-                return ret;
-        }
-        pr_debug("%s: Registering FEC1 device\n", __func__);
-        mx28_add_fec(1, &tx28_fec1_data);
-        return 0;
-}
diff --git a/arch/arm/mach-mxs/module-tx28.h b/arch/arm/mach-mxs/module-tx28.h
deleted file mode 100644
index 8ed425457d30..000000000000
--- a/arch/arm/mach-mxs/module-tx28.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- *   Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-int __init tx28_add_fec0(void);
-int __init tx28_add_fec1(void);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 346fd26f3aa6..edc30b8b77ed 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -18,12 +18,16 @@ config ARCH_OMAP2PLUS_TYPICAL
         select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
         select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
         select HIGHMEM
+        select PINCTRL
         help
           Compile a kernel suitable for booting most boards
 
 config SOC_HAS_OMAP2_SDRC
         bool "OMAP2 SDRAM Controller support"
 
+config SOC_HAS_REALTIME_COUNTER
+        bool "Real time free running counter"
+
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_OMAP2PLUS
@@ -70,6 +74,8 @@ config SOC_OMAP5
         select ARM_GIC
         select HAVE_SMP
         select ARM_CPU_SUSPEND if PM
+        select SOC_HAS_REALTIME_COUNTER
+        select ARM_ARCH_TIMER
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
diff --git a/arch/arm/mach-omap2/Makefile.boot b/arch/arm/mach-omap2/Makefile.boot
index b03e562acc60..be0fe9226d67 100644
--- a/arch/arm/mach-omap2/Makefile.boot
+++ b/arch/arm/mach-omap2/Makefile.boot
@@ -1,3 +1,9 @@
   zreladdr-y            += 0x80008000
 params_phys-y           := 0x80000100
 initrd_phys-y           := 0x80800000
+
+dtb-$(CONFIG_SOC_OMAP2420)      += omap2420-h4.dtb
+dtb-$(CONFIG_ARCH_OMAP3)        += omap3-beagle-xm.dtb omap3-evm.dtb omap3-tobi.dtb
+dtb-$(CONFIG_ARCH_OMAP4)        += omap4-panda.dtb omap4-pandaES.dtb
+dtb-$(CONFIG_ARCH_OMAP4)        += omap4-var_som.dtb omap4-sdp.dtb
+dtb-$(CONFIG_SOC_OMAP5)         += omap5-evm.dtb
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 9fc865502f0c..e1f289748c5d 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -170,7 +170,10 @@ static int __init omap_l2_cache_init(void)
         /* Enable PL310 L2 Cache controller */
         omap_smc1(0x102, 0x1);
 
-        l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+        if (of_have_populated_dt())
+                l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+        else
+                l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
 
         /*
          * Override default outer_cache.disable with a OMAP4
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7d843cd3b33d..00c006686b0d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3329,6 +3329,33 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
 }
 
 /**
+ * omap_hwmod_fill_dma_resources - fill struct resource array with dma data
+ * @oh: struct omap_hwmod *
+ * @res: pointer to the array of struct resource to fill
+ *
+ * Fill the struct resource array @res with dma resource data from the
+ * omap_hwmod @oh.  Intended to be called by code that registers
+ * omap_devices.  See also omap_hwmod_count_resources().  Returns the
+ * number of array elements filled.
+ */
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res)
+{
+        int i, sdma_reqs_cnt;
+        int r = 0;
+
+        sdma_reqs_cnt = _count_sdma_reqs(oh);
+        for (i = 0; i < sdma_reqs_cnt; i++) {
+                (res + r)->name = (oh->sdma_reqs + i)->name;
+                (res + r)->start = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->end = (oh->sdma_reqs + i)->dma_req;
+                (res + r)->flags = IORESOURCE_DMA;
+                r++;
+        }
+
+        return r;
+}
+
+/**
  * omap_hwmod_get_resource_byname - fetch IP block integration data by name
  * @oh: struct omap_hwmod * to operate on
  * @type: one of the IORESOURCE_* constants from include/linux/ioport.h
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 5214d5bfba27..8847d6eb2313 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -36,11 +36,13 @@
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <asm/mach/time.h>
 #include <asm/smp_twd.h>
 #include <asm/sched_clock.h>
 
+#include <asm/arch_timer.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/dmtimer.h>
@@ -71,6 +73,11 @@
 #define OMAP3_SECURE_TIMER      1
 #endif
 
+#define REALTIME_COUNTER_BASE                           0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET                    0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
+#define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
+
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -348,6 +355,84 @@ static void __init omap2_clocksource_init(int gptimer_id,
                 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
 }
 
+#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in the MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static void __init realtime_counter_init(void)
+{
+        void __iomem *base;
+        static struct clk *sys_clk;
+        unsigned long rate;
+        unsigned int reg, num, den;
+
+        base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
+        if (!base) {
+                pr_err("%s: ioremap failed\n", __func__);
+                return;
+        }
+        sys_clk = clk_get(NULL, "sys_clkin_ck");
+        if (!sys_clk) {
+                pr_err("%s: failed to get system clock handle\n", __func__);
+                iounmap(base);
+                return;
+        }
+
+        rate = clk_get_rate(sys_clk);
+        /* Numerator/denumerator values refer TRM Realtime Counter section */
+        switch (rate) {
+        case 1200000:
+                num = 64;
+                den = 125;
+                break;
+        case 1300000:
+                num = 768;
+                den = 1625;
+                break;
+        case 19200000:
+                num = 8;
+                den = 25;
+                break;
+        case 2600000:
+                num = 384;
+                den = 1625;
+                break;
+        case 2700000:
+                num = 256;
+                den = 1125;
+                break;
+        case 38400000:
+        default:
+                /* Program it for 38.4 MHz */
+                num = 4;
+                den = 25;
+                break;
+        }
+
+        /* Program numerator and denumerator registers */
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= num;
+        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+
+        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+                        NUMERATOR_DENUMERATOR_MASK;
+        reg |= den;
+        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+
+        iounmap(base);
+}
+#else
+static inline void __init realtime_counter_init(void)
+{}
+#endif
+
 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
                                 clksrc_nr, clksrc_src)                  \
 static void __init omap##name##_timer_init(void)                        \
@@ -394,6 +479,11 @@ static void __init omap4_timer_init(void)
         if (omap_rev() != OMAP4430_REV_ES1_0) {
                 int err;
 
+                if (of_have_populated_dt()) {
+                        twd_local_timer_of_register();
+                        return;
+                }
+
                 err = twd_local_timer_register(&twd_local_timer);
                 if (err)
                         pr_err("twd_local_timer_register failed %d\n", err);
@@ -404,7 +494,18 @@ OMAP_SYS_TIMER(4)
 #endif
 
 #ifdef CONFIG_SOC_OMAP5
-OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+static void __init omap5_timer_init(void)
+{
+        int err;
+
+        omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+        omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
+        realtime_counter_init();
+
+        err = arch_timer_of_register();
+        if (err)
+                pr_err("%s: arch_timer_register failed %d\n", __func__, err);
+}
 OMAP_SYS_TIMER(5)
 #endif
 
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
index c77a4883a4ee..98167da874c9 100644
--- a/arch/arm/mach-prima2/Makefile.boot
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y              += 0x00008000
 params_phys-y           := 0x00000100
 initrd_phys-y           := 0x00800000
+
+dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index fe2d1f80ef50..8e6288de69b9 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -25,6 +25,18 @@ config PXA_V7_MACH_AUTO
 if !ARCH_PXA_V7
 comment "Intel/Marvell Dev Platforms (sorted by hardware release time)"
 
+config MACH_PXA3XX_DT
+        bool "Support PXA3xx platforms from device tree"
+        select PXA3xx
+        select CPU_PXA300
+        select POWER_SUPPLY
+        select HAVE_PWM
+        select USE_OF
+        help
+          Include support for Marvell PXA3xx based platforms using
+          the device tree. Needn't select any other machine while
+          MACH_PXA3XX_DT is enabled.
+
 config ARCH_LUBBOCK
         bool "Intel DBPXA250 Development Platform (aka Lubbock)"
         select PXA25x
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index be0f7df8685c..2bedc9ed076c 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -26,6 +26,9 @@ obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 
 # NOTE: keep the order of boards in accordance to their order in Kconfig
 
+# Device Tree support
+obj-$(CONFIG_MACH_PXA3XX_DT)    += pxa-dt.o
+
 # Intel/Marvell Dev Platforms
 obj-$(CONFIG_ARCH_LUBBOCK)      += lubbock.o
 obj-$(CONFIG_MACH_MAINSTONE)    += mainstone.o
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
index 2a37a9a8f621..d4e9499832dc 100644
--- a/arch/arm/mach-pxa/clock-pxa3xx.c
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -127,8 +127,10 @@ void clk_pxa3xx_cken_enable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA |= mask;
-        else
+        else if (clk->cken < 64)
                 CKENB |= mask;
+        else
+                CKENC |= mask;
 }
 
 void clk_pxa3xx_cken_disable(struct clk *clk)
@@ -137,8 +139,10 @@ void clk_pxa3xx_cken_disable(struct clk *clk)
 
         if (clk->cken < 32)
                 CKENA &= ~mask;
-        else
+        else if (clk->cken < 64)
                 CKENB &= ~mask;
+        else
+                CKENC &= ~mask;
 }
 
 const struct clkops clk_pxa3xx_cken_ops = {
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index 207ecb49a61b..f4d48d20754e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -131,6 +131,7 @@
 #define AICSR           __REG(0x41340008)       /* Application Subsystem Interrupt Control/Status Register */
 #define CKENA           __REG(0x4134000C)       /* A Clock Enable Register */
 #define CKENB           __REG(0x41340010)       /* B Clock Enable Register */
+#define CKENC           __REG(0x41340024)       /* C Clock Enable Register */
 #define AC97_DIV        __REG(0x41340014)       /* AC97 clock divisor value register */
 
 #define ACCR_XPDIS              (1 << 31)       /* Core PLL Output Disable */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 5dae15ea6718..b6cc1816463e 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -17,6 +17,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <asm/exception.h>
 
@@ -25,8 +27,6 @@
 
 #include "generic.h"
 
-#define IRQ_BASE                io_p2v(0x40d00000)
-
 #define ICIP                    (0x000)
 #define ICMR                    (0x004)
 #define ICLR                    (0x008)
@@ -48,22 +48,19 @@
  * This is for peripheral IRQs internal to the PXA chip.
  */
 
+static void __iomem *pxa_irq_base;
 static int pxa_internal_irq_nr;
-
-static inline int cpu_has_ipr(void)
-{
-        return !cpu_is_pxa25x();
-}
+static bool cpu_has_ipr;
 
 static inline void __iomem *irq_base(int i)
 {
-        static unsigned long phys_base[] = {
-                0x40d00000,
-                0x40d0009c,
-                0x40d00130,
+        static unsigned long phys_base_offset[] = {
+                0x0,
+                0x9c,
+                0x130,
         };
 
-        return io_p2v(phys_base[i]);
+        return pxa_irq_base + phys_base_offset[i];
 }
 
 void pxa_mask_irq(struct irq_data *d)
@@ -96,8 +93,8 @@ asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
         uint32_t icip, icmr, mask;
 
         do {
-                icip = __raw_readl(IRQ_BASE + ICIP);
-                icmr = __raw_readl(IRQ_BASE + ICMR);
+                icip = __raw_readl(pxa_irq_base + ICIP);
+                icmr = __raw_readl(pxa_irq_base + ICMR);
                 mask = icip & icmr;
 
                 if (mask == 0)
@@ -128,6 +125,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
         pxa_internal_irq_nr = irq_nr;
+        cpu_has_ipr = !cpu_is_pxa25x();
+        pxa_irq_base = io_p2v(0x40d00000);
 
         for (n = 0; n < irq_nr; n += 32) {
                 void __iomem *base = irq_base(n >> 5);
@@ -136,8 +135,8 @@ void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
                 __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
                 for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
                         /* initialize interrupt priority */
-                        if (cpu_has_ipr())
-                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+                        if (cpu_has_ipr)
+                                __raw_writel(i | IPR_VALID, pxa_irq_base + IPR(i));
 
                         irq = PXA_IRQ(i);
                         irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
@@ -168,9 +167,9 @@ static int pxa_irq_suspend(void)
                 __raw_writel(0, base + ICMR);
         }
 
-        if (cpu_has_ipr()) {
+        if (cpu_has_ipr) {
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
+                        saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
         }
 
         return 0;
@@ -187,11 +186,11 @@ static void pxa_irq_resume(void)
                 __raw_writel(0, base + ICLR);
         }
 
-        if (cpu_has_ipr())
+        if (cpu_has_ipr)
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+                        __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
 
-        __raw_writel(1, IRQ_BASE + ICCR);
+        __raw_writel(1, pxa_irq_base + ICCR);
 }
 #else
 #define pxa_irq_suspend         NULL
@@ -202,3 +201,93 @@ struct syscore_ops pxa_irq_syscore_ops = {
         .suspend        = pxa_irq_suspend,
         .resume         = pxa_irq_resume,
 };
+
+#ifdef CONFIG_OF
+static struct irq_domain *pxa_irq_domain;
+
+static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
+                       irq_hw_number_t hw)
+{
+        void __iomem *base = irq_base(hw / 32);
+
+        /* initialize interrupt priority */
+        if (cpu_has_ipr)
+                __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
+
+        irq_set_chip_and_handler(hw, &pxa_internal_irq_chip,
+                                 handle_level_irq);
+        irq_set_chip_data(hw, base);
+        set_irq_flags(hw, IRQF_VALID);
+
+        return 0;
+}
+
+static struct irq_domain_ops pxa_irq_ops = {
+        .map    = pxa_irq_map,
+        .xlate  = irq_domain_xlate_onecell,
+};
+
+static const struct of_device_id intc_ids[] __initconst = {
+        { .compatible = "marvell,pxa-intc", },
+        {}
+};
+
+void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
+{
+        struct device_node *node;
+        const struct of_device_id *of_id;
+        struct pxa_intc_conf *conf;
+        struct resource res;
+        int n, ret;
+
+        node = of_find_matching_node(NULL, intc_ids);
+        if (!node) {
+                pr_err("Failed to find interrupt controller in arch-pxa\n");
+                return;
+        }
+        of_id = of_match_node(intc_ids, node);
+        conf = of_id->data;
+
+        ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
+                                   &pxa_internal_irq_nr);
+        if (ret) {
+                pr_err("Not found marvell,intc-nr-irqs property\n");
+                return;
+        }
+
+        ret = of_address_to_resource(node, 0, &res);
+        if (ret < 0) {
+                pr_err("No registers defined for node\n");
+                return;
+        }
+        pxa_irq_base = io_p2v(res.start);
+
+        if (of_find_property(node, "marvell,intc-priority", NULL))
+                cpu_has_ipr = 1;
+
+        ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
+        if (ret < 0) {
+                pr_err("Failed to allocate IRQ numbers\n");
+                return;
+        }
+
+        pxa_irq_domain = irq_domain_add_legacy(node, pxa_internal_irq_nr, 0, 0,
+                                               &pxa_irq_ops, NULL);
+        if (!pxa_irq_domain)
+                panic("Unable to add PXA IRQ domain\n");
+
+        irq_set_default_host(pxa_irq_domain);
+
+        for (n = 0; n < pxa_internal_irq_nr; n += 32) {
+                void __iomem *base = irq_base(n >> 5);
+
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+        }
+
+        /* only unmasked interrupts kick us out of idle */
+        __raw_writel(1, irq_base(0) + ICCR);
+
+        pxa_internal_irq_chip.irq_set_wake = fn;
+}
+#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
new file mode 100644
index 000000000000..c9192cea0033
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -0,0 +1,63 @@
+/*
+ *  linux/arch/arm/mach-pxa/pxa-dt.c
+ *
+ *  Copyright (C) 2012 Daniel Mack
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+#include <mach/pxa3xx.h>
+
+#include "generic.h"
+
+#ifdef CONFIG_PXA3xx
+extern void __init pxa3xx_dt_init_irq(void);
+
+static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40100000, "pxa2xx-uart.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40200000, "pxa2xx-uart.1", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x40700000, "pxa2xx-uart.2", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-uart",         0x41600000, "pxa2xx-uart.3", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-mmc",       0x41100000, "pxa2xx-mci.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-gpio",         0x40e00000, "pxa-gpio", NULL),
+        OF_DEV_AUXDATA("marvell,pxa-ohci",      0x4c000000, "pxa27x-ohci", NULL),
+        OF_DEV_AUXDATA("mrvl,pxa-i2c",          0x40301680, "pxa2xx-i2c.0", NULL),
+        OF_DEV_AUXDATA("mrvl,pwri2c",           0x40f500c0, "pxa3xx-i2c.1", NULL),
+        OF_DEV_AUXDATA("marvell,pxa3xx-nand",   0x43100000, "pxa3xx-nand", NULL),
+        {}
+};
+
+static void __init pxa3xx_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             pxa3xx_auxdata_lookup, NULL);
+}
+
+static const char *pxa3xx_dt_board_compat[] __initdata = {
+        "marvell,pxa300",
+        "marvell,pxa310",
+        "marvell,pxa320",
+        NULL,
+};
+#endif
+
+#ifdef CONFIG_PXA3xx
+DT_MACHINE_START(PXA_DT, "Marvell PXA3xx (Device Tree Support)")
+        .map_io         = pxa3xx_map_io,
+        .init_irq       = pxa3xx_dt_init_irq,
+        .handle_irq     = pxa3xx_handle_irq,
+        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
+        .init_machine   = pxa3xx_dt_init,
+        .dt_compat      = pxa3xx_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index dffb7e813d98..ff9c9574ec3e 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/syscore_ops.h>
 #include <linux/i2c/pxa-i2c.h>
 
@@ -40,6 +41,8 @@
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 
+extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
+
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -382,7 +385,7 @@ static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
         pxa_ext_wakeup_chip.irq_set_wake = fn;
 }
 
-void __init pxa3xx_init_irq(void)
+static void __init __pxa3xx_init_irq(void)
 {
         /* enable CP6 access */
         u32 value;
@@ -390,10 +393,23 @@ void __init pxa3xx_init_irq(void)
         value |= (1 << 6);
         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 
-        pxa_init_irq(56, pxa3xx_set_wake);
         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 }
 
+void __init pxa3xx_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_init_irq(56, pxa3xx_set_wake);
+}
+
+#ifdef CONFIG_OF
+void __init pxa3xx_dt_init_irq(void)
+{
+        __pxa3xx_init_irq();
+        pxa_dt_irq_init(pxa3xx_set_wake);
+}
+#endif  /* CONFIG_OF */
+
 static struct map_desc pxa3xx_io_desc[] __initdata = {
         {       /* Mem Ctl */
                 .virtual        = (unsigned long)SMEMC_VIRT,
@@ -466,7 +482,8 @@ static int __init pxa3xx_init(void)
                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 
-                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+                if (!of_have_populated_dt())
+                        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
         return ret;
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd99338d..5e410192ffb8 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,3 +7,7 @@ __ZRELADDR	:= $(shell /bin/bash -c 'printf "0x%08x" \
 #
 #params_phys-y (Instead: Pass atags pointer in r2)
 #initrd_phys-y (Instead: Use compiled-in initramfs)
+
+dtb-$(CONFIG_MACH_KZM9G) += sh73a0-kzm9g.dtb
+dtb-$(CONFIG_MACH_KZM9D) += emev2-kzm9d.dtb
+dtb-$(CONFIG_MACH_ARMADILLO800EVA) += r8a7740-armadillo800eva.dtb
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 7a1bb62ddcf0..54c16aade475 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -3,9 +3,13 @@ params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom-wide.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a02.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu-a04.dtb
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 5691ef679d01..f24710dfc395 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,6 +12,6 @@ obj-$(CONFIG_MACH_MOP500)	+= board-mop500.o board-mop500-sdi.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
                                 board-mop500-u8500uib.o \
                                 board-mop500-pins.o \
-                                board-mop500-msp.o
+                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-audio.c
index df15646036aa..070629a95625 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -7,7 +7,6 @@
 #include <linux/platform_device.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/pinctrl/consumer.h>
 
 #include <plat/gpio-nomadik.h>
 #include <plat/pincfg.h>
@@ -23,53 +22,6 @@
 #include "devices-db8500.h"
 #include "pins-db8500.h"
 
-/* MSP1/3 Tx/Rx usage protection */
-static DEFINE_SPINLOCK(msp_rxtx_lock);
-
-/* Reference Count */
-static int msp_rxtx_ref;
-
-/* Pin modes */
-struct pinctrl *msp1_p;
-struct pinctrl_state *msp1_def;
-struct pinctrl_state *msp1_sleep;
-
-int msp13_i2s_init(void)
-{
-        int retval = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_def))) {
-                retval = pinctrl_select_state(msp1_p, msp1_def);
-                if (retval)
-                        pr_err("could not set MSP1 defstate\n");
-        }
-        if (!retval)
-                msp_rxtx_ref++;
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-        return retval;
-}
-
-int msp13_i2s_exit(void)
-{
-        int retval = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&msp_rxtx_lock, flags);
-        WARN_ON(!msp_rxtx_ref);
-        msp_rxtx_ref--;
-        if (msp_rxtx_ref == 0 && !(IS_ERR(msp1_p) || IS_ERR(msp1_sleep))) {
-                retval = pinctrl_select_state(msp1_p, msp1_sleep);
-                if (retval)
-                        pr_err("could not set MSP1 sleepstate\n");
-        }
-        spin_unlock_irqrestore(&msp_rxtx_lock, flags);
-
-        return retval;
-}
-
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
         .dir = STEDMA40_PERIPH_TO_MEM,
@@ -96,7 +48,7 @@ static struct stedma40_chan_cfg msp0_dma_tx = {
         /* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp0_platform_data = {
+struct msp_i2s_platform_data msp0_platform_data = {
         .id = MSP_I2S_0,
         .msp_i2s_dma_rx = &msp0_dma_rx,
         .msp_i2s_dma_tx = &msp0_dma_tx,
@@ -128,12 +80,10 @@ static struct stedma40_chan_cfg msp1_dma_tx = {
         /* data_width is set during configuration */
 };
 
-static struct msp_i2s_platform_data msp1_platform_data = {
+struct msp_i2s_platform_data msp1_platform_data = {
         .id = MSP_I2S_1,
         .msp_i2s_dma_rx = NULL,
         .msp_i2s_dma_tx = &msp1_dma_tx,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
@@ -193,11 +143,11 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
 
 /* Platform device for ASoC MOP500 machine */
 static struct platform_device snd_soc_mop500 = {
-                .name = "snd-soc-mop500",
-                .id = 0,
-                .dev = {
-                        .platform_data = NULL,
-                },
+        .name = "snd-soc-mop500",
+        .id = 0,
+        .dev = {
+                .platform_data = NULL,
+        },
 };
 
 /* Platform device for Ux500-PCM */
@@ -209,59 +159,37 @@ static struct platform_device ux500_pcm = {
                 },
 };
 
-static struct msp_i2s_platform_data msp2_platform_data = {
+struct msp_i2s_platform_data msp2_platform_data = {
         .id = MSP_I2S_2,
         .msp_i2s_dma_rx = &msp2_dma_rx,
         .msp_i2s_dma_tx = &msp2_dma_tx,
 };
 
-static struct msp_i2s_platform_data msp3_platform_data = {
+struct msp_i2s_platform_data msp3_platform_data = {
         .id             = MSP_I2S_3,
         .msp_i2s_dma_rx = &msp1_dma_rx,
         .msp_i2s_dma_tx = NULL,
-        .msp_i2s_init = msp13_i2s_init,
-        .msp_i2s_exit = msp13_i2s_exit,
 };
 
-int mop500_msp_init(struct device *parent)
+void mop500_audio_init(struct device *parent)
 {
-        struct platform_device *msp1;
-
         pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
         platform_device_register(&snd_soc_mop500);
 
         pr_info("Initialize MSP I2S-devices.\n");
         db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
                            &msp0_platform_data);
-        msp1 = db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
+        db8500_add_msp_i2s(parent, 1, U8500_MSP1_BASE, IRQ_DB8500_MSP1,
                            &msp1_platform_data);
         db8500_add_msp_i2s(parent, 2, U8500_MSP2_BASE, IRQ_DB8500_MSP2,
                            &msp2_platform_data);
         db8500_add_msp_i2s(parent, 3, U8500_MSP3_BASE, IRQ_DB8500_MSP1,
                            &msp3_platform_data);
+}
 
-        /* Get the pinctrl handle for MSP1 */
-        if (msp1) {
-                msp1_p = pinctrl_get(&msp1->dev);
-                if (IS_ERR(msp1_p))
-                        dev_err(&msp1->dev, "could not get MSP1 pinctrl\n");
-                else {
-                        msp1_def = pinctrl_lookup_state(msp1_p,
-                                                        PINCTRL_STATE_DEFAULT);
-                        if (IS_ERR(msp1_def)) {
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 defstate\n");
-                        }
-                        msp1_sleep = pinctrl_lookup_state(msp1_p,
-                                                          PINCTRL_STATE_SLEEP);
-                        if (IS_ERR(msp1_sleep))
-                                dev_err(&msp1->dev,
-                                        "could not get MSP1 idlestate\n");
-                }
-        }
-
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent)
+{
         pr_info("%s: Register platform-device 'ux500-pcm'\n", __func__);
         platform_device_register(&ux500_pcm);
-
-        return 0;
 }
diff --git a/arch/arm/mach-ux500/board-mop500-msp.h b/arch/arm/mach-ux500/board-mop500-msp.h
deleted file mode 100644
index 6fcfb5e2cc94..000000000000
--- a/arch/arm/mach-ux500/board-mop500-msp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2012
- *
- * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
- *         for ST-Ericsson.
- *
- * License terms:
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-void mop500_msp_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 18ff781cfbe4..9c8e4a9e83ee 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -152,7 +152,7 @@ static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi1_data = {
+struct mmci_platform_data mop500_sdi1_data = {
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA,
@@ -189,7 +189,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi2_data = {
+struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index c8922bca68a4..074791306c99 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -55,7 +55,6 @@
 #include "devices-db8500.h"
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
-#include "board-mop500-msp.h"
 
 static struct gpio_led snowball_led_array[] = {
         {
@@ -606,7 +605,7 @@ static void __init mop500_init_machine(void)
         mop500_i2c_init(parent);
         mop500_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         u8500_cryp1_hash1_init(parent);
@@ -640,7 +639,7 @@ static void __init snowball_init_machine(void)
         mop500_i2c_init(parent);
         snowball_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         /* This board has full regulator constraints */
@@ -672,7 +671,7 @@ static void __init hrefv60_init_machine(void)
         mop500_i2c_init(parent);
         hrefv60_sdi_init(parent);
         mop500_spi_init(parent);
-        mop500_msp_init(parent);
+        mop500_audio_init(parent);
         mop500_uart_init(parent);
 
         i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
@@ -724,12 +723,9 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-        &snowball_led_dev,
-        &snowball_key_dev,
-};
-
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
+        /* Requires call-back bindings. */
+        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
         /* Requires DMA and call-back bindings. */
         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
@@ -737,6 +733,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires DMA bindings. */
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
         OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
         /* Requires clock name bindings. */
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
@@ -755,6 +753,15 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
         /* Requires device name bindings. */
         OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
+        /* Requires clock name and DMA bindings. */
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
+                "ux500-msp-i2s.0", &msp0_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
+                "ux500-msp-i2s.1", &msp1_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
+                "ux500-msp-i2s.2", &msp2_platform_data),
+        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
+                "ux500-msp-i2s.3", &msp3_platform_data),
         {},
 };
 
@@ -795,7 +802,7 @@ static void __init u8500_init_machine(void)
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 mop500_sdi_init(parent);
-                mop500_msp_init(parent);
+                mop500_audio_init(parent);
                 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
                 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
                 i2c_register_board_info(2, mop500_i2c2_devices,
@@ -804,7 +811,7 @@ static void __init u8500_init_machine(void)
                 mop500_uib_init();
 
         } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                mop500_msp_init(parent);
+                mop500_of_audio_init(parent);
         } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
                 /*
                  * The HREFv60 board removed a GPIO expander and routed
@@ -815,16 +822,6 @@ static void __init u8500_init_machine(void)
                 platform_add_devices(mop500_platform_devs,
                                 ARRAY_SIZE(mop500_platform_devs));
 
-                hrefv60_sdi_init(parent);
-                mop500_msp_init(parent);
-
-                i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
-                i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
-
-                i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
-                i2c_register_board_info(2, mop500_i2c2_devices,
-                                        ARRAY_SIZE(mop500_i2c2_devices));
-
                 mop500_uib_init();
         }
 
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index b5bfc1a78b1a..aca39a68712a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <mach/msp.h>
 #include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
@@ -80,7 +81,14 @@
 struct device;
 struct i2c_board_info;
 extern struct mmci_platform_data mop500_sdi0_data;
+extern struct mmci_platform_data mop500_sdi1_data;
+extern struct mmci_platform_data mop500_sdi2_data;
 extern struct mmci_platform_data mop500_sdi4_data;
+extern struct msp_i2s_platform_data msp0_platform_data;
+extern struct msp_i2s_platform_data msp1_platform_data;
+extern struct msp_i2s_platform_data msp2_platform_data;
+extern struct msp_i2s_platform_data msp3_platform_data;
+extern struct arm_pmu_platdata db8500_pmu_platdata;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -91,6 +99,9 @@ void __init mop500_stuib_init(void);
 void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
+void mop500_audio_init(struct device *parent);
+/* Due for removal once the MSP driver has been fully DT:ed. */
+void mop500_of_audio_init(struct device *parent);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 3ce7d940fc3c..27a397f5a42c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -138,10 +138,6 @@ static struct platform_device *platform_devs[] __initdata = {
         &db8500_prcmu_device,
 };
 
-static struct platform_device *of_platform_devs[] __initdata = {
-        &u8500_dma40_device,
-};
-
 static resource_size_t __initdata db8500_gpio_base[] = {
         U8500_GPIOBANK0_BASE,
         U8500_GPIOBANK1_BASE,
@@ -235,7 +231,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 struct device * __init u8500_of_init_devices(void)
 {
         struct device *parent;
-        int i;
 
         parent = db8500_soc_device_init();
 
@@ -244,8 +239,7 @@ struct device * __init u8500_of_init_devices(void)
         platform_device_register_data(parent,
                 "cpufreq-u8500", -1, NULL, 0);
 
-        for (i = 0; i < ARRAY_SIZE(of_platform_devs); i++)
-                of_platform_devs[i]->dev.parent = parent;
+        u8500_dma40_device.dev.parent = parent;
 
         /*
          * Devices to be DT:ed:
@@ -253,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
          *   db8500_pmu_device   = done
          *   db8500_prcmu_device = done
          */
-        platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
+        platform_device_register(&u8500_dma40_device);
 
         return parent;
 }
diff --git a/arch/arm/mach-ux500/include/mach/msp.h b/arch/arm/mach-ux500/include/mach/msp.h
index 798be19129ef..3cc7142eee02 100644
--- a/arch/arm/mach-ux500/include/mach/msp.h
+++ b/arch/arm/mach-ux500/include/mach/msp.h
@@ -22,8 +22,6 @@ struct msp_i2s_platform_data {
         enum msp_i2s_id id;
         struct stedma40_chan_cfg *msp_i2s_dma_rx;
         struct stedma40_chan_cfg *msp_i2s_dma_tx;
-        int (*msp_i2s_init) (void);
-        int (*msp_i2s_exit) (void);
 };
 
 #endif
diff --git a/arch/arm/mach-vt8500/Kconfig b/arch/arm/mach-vt8500/Kconfig
deleted file mode 100644
index 2c20a341c11a..000000000000
--- a/arch/arm/mach-vt8500/Kconfig
+++ /dev/null
@@ -1,73 +0,0 @@
-if ARCH_VT8500
-
-config VTWM_VERSION_VT8500
-        bool
-
-config VTWM_VERSION_WM8505
-        bool
-
-config MACH_BV07
-        bool "Benign BV07-8500 Mini Netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_VT8500
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a VIA VT8500 chip.
-
-config MACH_WM8505_7IN_NETBOOK
-        bool "WM8505 7-inch generic netbook"
-        depends on ARCH_VT8500
-        select VTWM_VERSION_WM8505
-        help
-          Add support for the inexpensive 7-inch netbooks sold by many
-          Chinese distributors under various names. Note that there are
-          many hardware implementations in identical exterior, make sure
-          that yours is indeed based on a WonderMedia WM8505 chip.
-
-comment "LCD panel size"
-
-config WMT_PANEL_800X480
-        bool "7-inch with 800x480 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        default y
-        help
-          These are found in most of the netbooks in generic cases, as
-          well as in Eken M001 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=800x480' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_800X600
-        bool "8-inch with 800x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M003 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=800x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_1024X576
-        bool "10-inch with 1024x576 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in CherryPal netbooks and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=1024x576' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-config WMT_PANEL_1024X600
-        bool "10-inch with 1024x600 resolution"
-        depends on (FB_VT8500 || FB_WM8505)
-        help
-          These are found in Eken M006 tablets and possibly elsewhere.
-
-          To select this panel at runtime, say y here and append
-          'panel=1024x600' to your kernel command line. Otherwise, the
-          largest one available will be used.
-
-endif
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 7ce51767c99c..e035251cda48 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,7 +1 @@
-obj-y += devices.o gpio.o irq.o timer.o restart.o
-
-obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
-obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
-
-obj-$(CONFIG_MACH_BV07) += bv07.o
-obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
+obj-$(CONFIG_ARCH_VT8500) += irq.o timer.o vt8500.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
deleted file mode 100644
index 6fd9d609ebaa..000000000000
--- a/arch/arm/mach-vt8500/bv07.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/bv07.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_lcdc,
-        &vt8500_device_ehci,
-        &vt8500_device_uhci,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init bv07_init(void)
-{
-#ifdef CONFIG_FB_VT8500
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 1, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
-        wmt_setup_restart();
-        vt8500_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-
-MACHINE_START(BV07, "Benign BV07 Mini Netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = vt8500_reserve_mem,
-        .map_io         = vt8500_map_io,
-        .init_irq       = vt8500_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = bv07_init,
-MACHINE_END
diff --git a/arch/arm/mach-vt8500/common.h b/arch/arm/mach-vt8500/common.h
new file mode 100644
index 000000000000..2b2419646e95
--- /dev/null
+++ b/arch/arm/mach-vt8500/common.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/mach-vt8500/dt_common.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+#define __ARCH_ARM_MACH_VT8500_DT_COMMON_H
+
+#include <linux/of.h>
+
+void __init vt8500_timer_init(void);
+int __init vt8500_irq_init(struct device_node *node,
+                                struct device_node *parent);
+
+/* defined in drivers/clk/clk-vt8500.c */
+void __init vtwm_clk_init(void __iomem *pmc_base);
+
+#endif
diff --git a/arch/arm/mach-vt8500/devices-vt8500.c b/arch/arm/mach-vt8500/devices-vt8500.c
deleted file mode 100644
index def7fe393a2c..000000000000
--- a/arch/arm/mach-vt8500/devices-vt8500.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-vt8500.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/vt8500_regs.h>
-#include <mach/vt8500_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init vt8500_set_resources(void)
-{
-        struct resource tmp[3];
-
-        tmp[0] = wmt_mmio_res(VT8500_LCDC_BASE, SZ_1K);
-        tmp[1] = wmt_irq_res(IRQ_LCDC);
-        wmt_res_add(&vt8500_device_lcdc, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-        /* vt8500 uses a single IRQ for both EHCI and UHCI controllers */
-        tmp[0] = wmt_mmio_res(VT8500_UHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_uhci, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(VT8500_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(VT8500_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(VT8500_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init vt8500_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = VT8500_IC_BASE;
-        wmt_gpio_base = VT8500_GPIO_BASE;
-        wmt_pmc_base = VT8500_PMC_BASE;
-        wmt_i8042_base = VT8500_PS2_BASE;
-
-        wmt_nr_irqs = VT8500_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init vt8500_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-        /* Should be done before interrupts and timers are initialized */
-        vt8500_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices-wm8505.c b/arch/arm/mach-vt8500/devices-wm8505.c
deleted file mode 100644
index c810454178dc..000000000000
--- a/arch/arm/mach-vt8500/devices-wm8505.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices-wm8505.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/platform_device.h>
-
-#include <mach/wm8505_regs.h>
-#include <mach/wm8505_irqs.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-void __init wm8505_set_resources(void)
-{
-        struct resource tmp[3];
-
-        tmp[0] = wmt_mmio_res(WM8505_GOVR_BASE, SZ_512);
-        wmt_res_add(&vt8500_device_wm8505_fb, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART0_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART0);
-        wmt_res_add(&vt8500_device_uart0, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART1_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART1);
-        wmt_res_add(&vt8500_device_uart1, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART2_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART2);
-        wmt_res_add(&vt8500_device_uart2, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART3_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART3);
-        wmt_res_add(&vt8500_device_uart3, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART4_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART4);
-        wmt_res_add(&vt8500_device_uart4, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UART5_BASE, 0x1040);
-        tmp[1] = wmt_irq_res(IRQ_UART5);
-        wmt_res_add(&vt8500_device_uart5, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_EHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_EHCI);
-        wmt_res_add(&vt8500_device_ehci, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_UHCI_BASE, SZ_512);
-        tmp[1] = wmt_irq_res(IRQ_UHCI);
-        wmt_res_add(&vt8500_device_uhci, tmp, 2);
-
-        tmp[0] = wmt_mmio_res(WM8505_GEGEA_BASE, SZ_256);
-        wmt_res_add(&vt8500_device_ge_rops, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_PWM_BASE, 0x44);
-        wmt_res_add(&vt8500_device_pwm, tmp, 1);
-
-        tmp[0] = wmt_mmio_res(WM8505_RTC_BASE, 0x2c);
-        tmp[1] = wmt_irq_res(IRQ_RTC);
-        tmp[2] = wmt_irq_res(IRQ_RTCSM);
-        wmt_res_add(&vt8500_device_rtc, tmp, 3);
-}
-
-static void __init wm8505_set_externs(void)
-{
-        /* Non-resource-aware stuff */
-        wmt_ic_base = WM8505_IC_BASE;
-        wmt_sic_base = WM8505_SIC_BASE;
-        wmt_gpio_base = WM8505_GPIO_BASE;
-        wmt_pmc_base = WM8505_PMC_BASE;
-        wmt_i8042_base = WM8505_PS2_BASE;
-
-        wmt_nr_irqs = WM8505_NR_IRQS;
-        wmt_timer_irq = IRQ_PMCOS0;
-        wmt_gpio_ext_irq[0] = IRQ_EXT0;
-        wmt_gpio_ext_irq[1] = IRQ_EXT1;
-        wmt_gpio_ext_irq[2] = IRQ_EXT2;
-        wmt_gpio_ext_irq[3] = IRQ_EXT3;
-        wmt_gpio_ext_irq[4] = IRQ_EXT4;
-        wmt_gpio_ext_irq[5] = IRQ_EXT5;
-        wmt_gpio_ext_irq[6] = IRQ_EXT6;
-        wmt_gpio_ext_irq[7] = IRQ_EXT7;
-        wmt_i8042_kbd_irq = IRQ_PS2KBD;
-        wmt_i8042_aux_irq = IRQ_PS2MOUSE;
-}
-
-void __init wm8505_map_io(void)
-{
-        iotable_init(wmt_io_desc, ARRAY_SIZE(wmt_io_desc));
-
-        /* Should be done before interrupts and timers are initialized */
-        wm8505_set_externs();
-}
diff --git a/arch/arm/mach-vt8500/devices.c b/arch/arm/mach-vt8500/devices.c
deleted file mode 100644
index 46ff82dad544..000000000000
--- a/arch/arm/mach-vt8500/devices.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/pwm_backlight.h>
-#include <linux/memblock.h>
-
-#include <asm/mach/arch.h>
-
-#include <mach/vt8500fb.h>
-#include <mach/i8042.h>
-#include "devices.h"
-
-/* These can't use resources currently */
-unsigned long wmt_ic_base __initdata;
-unsigned long wmt_sic_base __initdata;
-unsigned long wmt_gpio_base __initdata;
-unsigned long wmt_pmc_base __initdata;
-unsigned long wmt_i8042_base __initdata;
-
-int wmt_nr_irqs __initdata;
-int wmt_timer_irq __initdata;
-int wmt_gpio_ext_irq[8] __initdata;
-
-/* Should remain accessible after init.
- * i8042 driver desperately calls for attention...
- */
-int wmt_i8042_kbd_irq;
-int wmt_i8042_aux_irq;
-
-static u64 fb_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_lcdc = {
-        .name           = "vt8500-lcd",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &fb_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device vt8500_device_wm8505_fb = {
-        .name           = "wm8505-fb",
-        .id             = 0,
-};
-
-/* Smallest to largest */
-static struct vt8500fb_platform_data panels[] = {
-#ifdef CONFIG_WMT_PANEL_800X480
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 480 * 2,
-        .mode           = {
-                .name           = "800x480",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_800X600
-{
-        .xres_virtual   = 800,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "800x600",
-                .xres           = 800,
-                .yres           = 600,
-                .left_margin    = 88,
-                .right_margin   = 40,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 0,
-                .vsync_len      = 1,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X576
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 576 * 2,
-        .mode           = {
-                .name           = "1024x576",
-                .xres           = 1024,
-                .yres           = 576,
-                .left_margin    = 40,
-                .right_margin   = 24,
-                .upper_margin   = 32,
-                .lower_margin   = 11,
-                .hsync_len      = 96,
-                .vsync_len      = 2,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-#ifdef CONFIG_WMT_PANEL_1024X600
-{
-        .xres_virtual   = 1024,
-        .yres_virtual   = 600 * 2,
-        .mode           = {
-                .name           = "1024x600",
-                .xres           = 1024,
-                .yres           = 600,
-                .left_margin    = 66,
-                .right_margin   = 2,
-                .upper_margin   = 19,
-                .lower_margin   = 1,
-                .hsync_len      = 23,
-                .vsync_len      = 8,
-                .vmode          = FB_VMODE_NONINTERLACED,
-        },
-},
-#endif
-};
-
-static int current_panel_idx __initdata = ARRAY_SIZE(panels) - 1;
-
-static int __init panel_setup(char *str)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(panels); i++) {
-                if (strcmp(panels[i].mode.name, str) == 0) {
-                        current_panel_idx = i;
-                        break;
-                }
-        }
-        return 0;
-}
-
-early_param("panel", panel_setup);
-
-static inline void preallocate_fb(struct vt8500fb_platform_data *p,
-                                  unsigned long align) {
-        p->video_mem_len = (p->xres_virtual * p->yres_virtual * 4) >>
-                        (p->bpp > 16 ? 0 : (p->bpp > 8 ? 1 :
-                                        (8 / p->bpp) + 1));
-        p->video_mem_phys = (unsigned long)memblock_alloc(p->video_mem_len,
-                                                          align);
-        p->video_mem_virt = phys_to_virt(p->video_mem_phys);
-}
-
-struct platform_device vt8500_device_uart0 = {
-        .name           = "vt8500_serial",
-        .id             = 0,
-};
-
-struct platform_device vt8500_device_uart1 = {
-        .name           = "vt8500_serial",
-        .id             = 1,
-};
-
-struct platform_device vt8500_device_uart2 = {
-        .name           = "vt8500_serial",
-        .id             = 2,
-};
-
-struct platform_device vt8500_device_uart3 = {
-        .name           = "vt8500_serial",
-        .id             = 3,
-};
-
-struct platform_device vt8500_device_uart4 = {
-        .name           = "vt8500_serial",
-        .id             = 4,
-};
-
-struct platform_device vt8500_device_uart5 = {
-        .name           = "vt8500_serial",
-        .id             = 5,
-};
-
-static u64 ehci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_ehci = {
-        .name           = "vt8500-ehci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &ehci_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-static u64 uhci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device vt8500_device_uhci = {
-        .name           = "platform-uhci",
-        .id             = 0,
-        .dev            = {
-                .dma_mask       = &uhci_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-struct platform_device vt8500_device_ge_rops = {
-        .name           = "wmt_ge_rops",
-        .id             = -1,
-};
-
-struct platform_device vt8500_device_pwm = {
-        .name           = "vt8500-pwm",
-        .id             = 0,
-};
-
-static struct platform_pwm_backlight_data vt8500_pwmbl_data = {
-        .pwm_id         = 0,
-        .max_brightness = 128,
-        .dft_brightness = 70,
-        .pwm_period_ns  = 250000, /* revisit when clocks are implemented */
-};
-
-struct platform_device vt8500_device_pwmbl = {
-        .name           = "pwm-backlight",
-        .id             = 0,
-        .dev            = {
-                .platform_data = &vt8500_pwmbl_data,
-        },
-};
-
-struct platform_device vt8500_device_rtc = {
-        .name           = "vt8500-rtc",
-        .id             = 0,
-};
-
-struct map_desc wmt_io_desc[] __initdata = {
-        /* SoC MMIO registers */
-        [0] = {
-                .virtual        = 0xf8000000,
-                .pfn            = __phys_to_pfn(0xd8000000),
-                .length         = 0x00390000, /* max of all chip variants */
-                .type           = MT_DEVICE
-        },
-        /* PCI I/O space, numbers tied to those in <mach/io.h> */
-        [1] = {
-                .virtual        = 0xf0000000,
-                .pfn            = __phys_to_pfn(0xc0000000),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
-        },
-};
-
-void __init vt8500_reserve_mem(void)
-{
-#ifdef CONFIG_FB_VT8500
-        panels[current_panel_idx].bpp = 16; /* Always use RGB565 */
-        preallocate_fb(&panels[current_panel_idx], SZ_4M);
-        vt8500_device_lcdc.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
-
-void __init wm8505_reserve_mem(void)
-{
-#if defined CONFIG_FB_WM8505
-        panels[current_panel_idx].bpp = 32; /* Always use RGB888 */
-        preallocate_fb(&panels[current_panel_idx], 32);
-        vt8500_device_wm8505_fb.dev.platform_data = &panels[current_panel_idx];
-#endif
-}
diff --git a/arch/arm/mach-vt8500/devices.h b/arch/arm/mach-vt8500/devices.h
deleted file mode 100644
index 0e6d9f904c77..000000000000
--- a/arch/arm/mach-vt8500/devices.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* linux/arch/arm/mach-vt8500/devices.h
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_VT8500_DEVICES_H
-#define __ARCH_ARM_MACH_VT8500_DEVICES_H
-
-#include <linux/platform_device.h>
-#include <asm/mach/map.h>
-
-void __init vt8500_init_irq(void);
-void __init wm8505_init_irq(void);
-void __init vt8500_map_io(void);
-void __init wm8505_map_io(void);
-void __init vt8500_reserve_mem(void);
-void __init wm8505_reserve_mem(void);
-void __init vt8500_gpio_init(void);
-void __init vt8500_set_resources(void);
-void __init wm8505_set_resources(void);
-
-extern unsigned long wmt_ic_base __initdata;
-extern unsigned long wmt_sic_base __initdata;
-extern unsigned long wmt_gpio_base __initdata;
-extern unsigned long wmt_pmc_base __initdata;
-
-extern int wmt_nr_irqs __initdata;
-extern int wmt_timer_irq __initdata;
-extern int wmt_gpio_ext_irq[8] __initdata;
-
-extern struct map_desc wmt_io_desc[2] __initdata;
-
-static inline struct resource wmt_mmio_res(u32 start, u32 size)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_MEM,
-                .start = start,
-                .end = start + size - 1,
-        };
-
-        return tmp;
-}
-
-static inline struct resource wmt_irq_res(int irq)
-{
-        struct resource tmp = {
-                .flags = IORESOURCE_IRQ,
-                .start = irq,
-                .end = irq,
-        };
-
-        return tmp;
-}
-
-static inline void wmt_res_add(struct platform_device *pdev,
-                               const struct resource *res, unsigned int num)
-{
-        if (unlikely(platform_device_add_resources(pdev, res, num)))
-                pr_err("Failed to assign resources\n");
-}
-
-extern struct sys_timer vt8500_timer;
-
-extern struct platform_device vt8500_device_uart0;
-extern struct platform_device vt8500_device_uart1;
-extern struct platform_device vt8500_device_uart2;
-extern struct platform_device vt8500_device_uart3;
-extern struct platform_device vt8500_device_uart4;
-extern struct platform_device vt8500_device_uart5;
-
-extern struct platform_device vt8500_device_lcdc;
-extern struct platform_device vt8500_device_wm8505_fb;
-extern struct platform_device vt8500_device_ehci;
-extern struct platform_device vt8500_device_uhci;
-extern struct platform_device vt8500_device_ge_rops;
-extern struct platform_device vt8500_device_pwm;
-extern struct platform_device vt8500_device_pwmbl;
-extern struct platform_device vt8500_device_rtc;
-#endif
diff --git a/arch/arm/mach-vt8500/gpio.c b/arch/arm/mach-vt8500/gpio.c
deleted file mode 100644
index 2bcc0ec783df..000000000000
--- a/arch/arm/mach-vt8500/gpio.c
+++ /dev/null
@@ -1,240 +0,0 @@
-/* linux/arch/arm/mach-vt8500/gpio.c
- *
- * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include "devices.h"
-
-#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
-
-#define ENABLE_REGS     0x0
-#define DIRECTION_REGS  0x20
-#define OUTVALUE_REGS   0x40
-#define INVALUE_REGS    0x60
-
-#define EXT_REGOFF      0x1c
-
-static void __iomem *regbase;
-
-struct vt8500_gpio_chip {
-        struct gpio_chip        chip;
-        unsigned int            shift;
-        unsigned int            regoff;
-};
-
-static int gpio_to_irq_map[8];
-
-static int vt8500_muxed_gpio_request(struct gpio_chip *chip,
-                                     unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        return 0;
-}
-
-static void vt8500_muxed_gpio_free(struct gpio_chip *chip,
-                                   unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + ENABLE_REGS + vt8500_chip->regoff);
-
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + ENABLE_REGS + vt8500_chip->regoff);
-}
-
-static int vt8500_muxed_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        val &= ~(1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        return 0;
-}
-
-static int vt8500_muxed_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        val |= (1 << vt8500_chip->shift << offset);
-        writel(val, regbase + DIRECTION_REGS + vt8500_chip->regoff);
-
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-                val |= (1 << vt8500_chip->shift << offset);
-                writel(val, regbase + OUTVALUE_REGS + vt8500_chip->regoff);
-        }
-        return 0;
-}
-
-static int vt8500_muxed_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-
-        return (readl(regbase + INVALUE_REGS + vt8500_chip->regoff)
-                >> vt8500_chip->shift >> offset) & 1;
-}
-
-static void vt8500_muxed_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
-        unsigned val = readl(regbase + INVALUE_REGS + vt8500_chip->regoff);
-
-        if (value)
-                val |= (1 << vt8500_chip->shift << offset);
-        else
-                val &= ~(1 << vt8500_chip->shift << offset);
-
-        writel(val, regbase + INVALUE_REGS + vt8500_chip->regoff);
-}
-
-#define VT8500_GPIO_BANK(__name, __shift, __off, __base, __num)         \
-{                                                                       \
-        .chip = {                                                       \
-                .label                  = __name,                       \
-                .request                = vt8500_muxed_gpio_request,    \
-                .free                   = vt8500_muxed_gpio_free,       \
-                .direction_input  = vt8500_muxed_gpio_direction_input,  \
-                .direction_output = vt8500_muxed_gpio_direction_output, \
-                .get                    = vt8500_muxed_gpio_get_value,  \
-                .set                    = vt8500_muxed_gpio_set_value,  \
-                .can_sleep              = 0,                            \
-                .base                   = __base,                       \
-                .ngpio                  = __num,                        \
-        },                                                              \
-        .shift          = __shift,                                      \
-        .regoff         = __off,                                        \
-}
-
-static struct vt8500_gpio_chip vt8500_muxed_gpios[] = {
-        VT8500_GPIO_BANK("uart0",       0,      0x0,    8,      4),
-        VT8500_GPIO_BANK("uart1",       4,      0x0,    12,     4),
-        VT8500_GPIO_BANK("spi0",        8,      0x0,    16,     4),
-        VT8500_GPIO_BANK("spi1",        12,     0x0,    20,     4),
-        VT8500_GPIO_BANK("spi2",        16,     0x0,    24,     4),
-        VT8500_GPIO_BANK("pwmout",      24,     0x0,    28,     2),
-
-        VT8500_GPIO_BANK("sdmmc",       0,      0x4,    30,     11),
-        VT8500_GPIO_BANK("ms",          16,     0x4,    41,     7),
-        VT8500_GPIO_BANK("i2c0",        24,     0x4,    48,     2),
-        VT8500_GPIO_BANK("i2c1",        26,     0x4,    50,     2),
-
-        VT8500_GPIO_BANK("mii",         0,      0x8,    52,     20),
-        VT8500_GPIO_BANK("see",         20,     0x8,    72,     4),
-        VT8500_GPIO_BANK("ide",         24,     0x8,    76,     7),
-
-        VT8500_GPIO_BANK("ccir",        0,      0xc,    83,     19),
-
-        VT8500_GPIO_BANK("ts",          8,      0x10,   102,    11),
-
-        VT8500_GPIO_BANK("lcd",         0,      0x14,   113,    23),
-};
-
-static int vt8500_gpio_direction_input(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        val &= ~(1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-        return 0;
-}
-
-static int vt8500_gpio_direction_output(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        val |= (1 << offset);
-        writel(val, regbase + DIRECTION_REGS + EXT_REGOFF);
-
-        if (value) {
-                val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-                val |= (1 << offset);
-                writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-        }
-        return 0;
-}
-
-static int vt8500_gpio_get_value(struct gpio_chip *chip,
-                                       unsigned offset)
-{
-        return (readl(regbase + INVALUE_REGS + EXT_REGOFF) >> offset) & 1;
-}
-
-static void vt8500_gpio_set_value(struct gpio_chip *chip,
-                                        unsigned offset, int value)
-{
-        unsigned val = readl(regbase + OUTVALUE_REGS + EXT_REGOFF);
-
-        if (value)
-                val |= (1 << offset);
-        else
-                val &= ~(1 << offset);
-
-        writel(val, regbase + OUTVALUE_REGS + EXT_REGOFF);
-}
-
-static int vt8500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        if (offset > 7)
-                return -EINVAL;
-
-        return gpio_to_irq_map[offset];
-}
-
-static struct gpio_chip vt8500_external_gpios = {
-        .label                  = "extgpio",
-        .direction_input        = vt8500_gpio_direction_input,
-        .direction_output       = vt8500_gpio_direction_output,
-        .get                    = vt8500_gpio_get_value,
-        .set                    = vt8500_gpio_set_value,
-        .to_irq                 = vt8500_gpio_to_irq,
-        .can_sleep              = 0,
-        .base                   = 0,
-        .ngpio                  = 8,
-};
-
-void __init vt8500_gpio_init(void)
-{
-        int i;
-
-        for (i = 0; i < 8; i++)
-                gpio_to_irq_map[i] = wmt_gpio_ext_irq[i];
-
-        regbase = ioremap(wmt_gpio_base, SZ_64K);
-        if (!regbase) {
-                printk(KERN_ERR "Failed to map MMIO registers for GPIO\n");
-                return;
-        }
-
-        gpiochip_add(&vt8500_external_gpios);
-
-        for (i = 0; i < ARRAY_SIZE(vt8500_muxed_gpios); i++)
-                gpiochip_add(&vt8500_muxed_gpios[i].chip);
-}
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
index 89f9b787d2a0..738979518acb 100644
--- a/arch/arm/mach-vt8500/include/mach/restart.h
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -13,5 +13,5 @@
  *
  */
 
-void wmt_setup_restart(void);
-void wmt_restart(char mode, const char *cmd);
+void vt8500_setup_restart(void);
+void vt8500_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h b/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
deleted file mode 100644
index ecfee9124711..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* VT8500 Interrupt Sources */
-
-#define IRQ_JPEGENC     0       /* JPEG Encoder */
-#define IRQ_JPEGDEC     1       /* JPEG Decoder */
-                                /* Reserved */
-#define IRQ_PATA        3       /* PATA Controller */
-                                /* Reserved */
-#define IRQ_DMA         5       /* DMA Controller */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_GE          8       /* Graphic Engine */
-#define IRQ_GOV         9       /* Graphic Overlay Engine */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-#define IRQ_MPEGTS      11      /* Transport Stream Interface */
-#define IRQ_LCDC        12      /* LCD Controller */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_CIPHER      16      /* Cipher */
-#define IRQ_VPP         17      /* Video Post-Processor */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-                                /* Reserved */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_LCDDF       27      /* LCD Data Formatter */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_MS          30      /* MemoryStick Controller */
-#define IRQ_MS_DMA      31      /* MemoryStick Controller DMA */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_I2S         34      /* I2S */
-#define IRQ_PCM         35      /* PCM */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_VPU         40      /* Video Processing Unit */
-#define IRQ_VID         41      /* Video Digital Input Interface */
-#define IRQ_AC97        42      /* AC97 Interface */
-#define IRQ_EHCI        43      /* USB */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_PS2MOUSE    45      /* PS/2 Mouse */
-#define IRQ_PS2KBD      46      /* PS/2 Keyboard */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_ADC         51      /* ADC */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_DMA0        56      /* DMA Channel 0 */
-#define IRQ_DMA1        57      /* DMA Channel 1 */
-#define IRQ_DMA2        58      /* DMA Channel 2 */
-#define IRQ_DMA3        59      /* DMA Channel 3 */
-#define IRQ_DMA4        60      /* DMA Channel 4 */
-#define IRQ_DMA5        61      /* DMA Channel 5 */
-#define IRQ_DMA6        62      /* DMA Channel 6 */
-#define IRQ_DMA7        63      /* DMA Channel 7 */
-
-#define VT8500_NR_IRQS          64
diff --git a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h b/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
deleted file mode 100644
index 29c63ecb2383..000000000000
--- a/arch/arm/mach-vt8500/include/mach/vt8500_regs.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/vt8500_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_VT8500_REGS_H
-#define __ASM_ARM_ARCH_VT8500_REGS_H
-
-/* VT8500 Registers Map */
-
-#define VT8500_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define VT8500_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-
-#define VT8500_DDR_BASE         0xd8000000      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define VT8500_DMA_BASE         0xd8001000      /* 1k   DMA Controller */
-#define VT8500_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define VT8500_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define VT8500_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define VT8500_USB_BASE         0xd8007800      /* 2k   USB OTG */
-# define VT8500_EHCI_BASE       0xd8007900      /*      EHCI */
-# define VT8500_UHCI_BASE       0xd8007b01      /*      UHCI */
-#define VT8500_PATA_BASE        0xd8008000      /* 512  PATA */
-#define VT8500_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define VT8500_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define VT8500_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define VT8500_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define VT8500_MS_BASE          0xd800b000      /* 1k   MS/MSPRO Controller */
-#define VT8500_LCDC_BASE        0xd800e400      /* 1k   LCD Controller */
-#define VT8500_VPU_BASE         0xd8050000      /* 256  VPU */
-#define VT8500_GOV_BASE         0xd8050300      /* 256  GOV */
-#define VT8500_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define VT8500_LCDF_BASE        0xd8050900      /* 256  LCD Formatter */
-#define VT8500_VID_BASE         0xd8050a00      /* 256  VID */
-#define VT8500_VPP_BASE         0xd8050b00      /* 256  VPP */
-#define VT8500_TSBK_BASE        0xd80f4000      /* 4k   TSBK */
-#define VT8500_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define VT8500_JPEGENC_BASE     0xd80ff000      /* 4k   JPEG Encoder */
-#define VT8500_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define VT8500_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define VT8500_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define VT8500_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define VT8500_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define VT8500_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define VT8500_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define VT8500_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define VT8500_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define VT8500_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define VT8500_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define VT8500_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define VT8500_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define VT8500_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define VT8500_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define VT8500_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define VT8500_PCM_BASE         0xd82d0000      /* 64k  PCM */
-#define VT8500_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define VT8500_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define VT8500_ADC_BASE         0xd8340000      /* 64k  ADC */
-
-#define VT8500_REGS_END_PHYS    0xd834ffff      /* End of MMIO registers */
-#define VT8500_REGS_LENGTH      (VT8500_REGS_END_PHYS \
-                                - VT8500_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h b/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
deleted file mode 100644
index 6128627ac753..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_irqs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/* WM8505 Interrupt Sources */
-
-#define IRQ_UHCI        0       /* UHC FS (UHCI?) */
-#define IRQ_EHCI        1       /* UHC HS */
-#define IRQ_UDCDMA      2       /* UDC DMA */
-                                /* Reserved */
-#define IRQ_PS2MOUSE    4       /* PS/2 Mouse */
-#define IRQ_UDC         5       /* UDC */
-#define IRQ_EXT0        6       /* External Interrupt 0 */
-#define IRQ_EXT1        7       /* External Interrupt 1 */
-#define IRQ_KEYPAD      8       /* Keypad */
-#define IRQ_DMA         9       /* DMA Controller */
-#define IRQ_ETHER       10      /* Ethernet MAC */
-                                /* Reserved */
-                                /* Reserved */
-#define IRQ_EXT2        13      /* External Interrupt 2 */
-#define IRQ_EXT3        14      /* External Interrupt 3 */
-#define IRQ_EXT4        15      /* External Interrupt 4 */
-#define IRQ_APB         16      /* APB Bridge */
-#define IRQ_DMA0        17      /* DMA Channel 0 */
-#define IRQ_I2C1        18      /* I2C 1 */
-#define IRQ_I2C0        19      /* I2C 0 */
-#define IRQ_SDMMC       20      /* SD/MMC Controller */
-#define IRQ_SDMMC_DMA   21      /* SD/MMC Controller DMA */
-#define IRQ_PMC_WU      22      /* Power Management Controller Wakeup */
-#define IRQ_PS2KBD      23      /* PS/2 Keyboard */
-#define IRQ_SPI0        24      /* SPI 0 */
-#define IRQ_SPI1        25      /* SPI 1 */
-#define IRQ_SPI2        26      /* SPI 2 */
-#define IRQ_DMA1        27      /* DMA Channel 1 */
-#define IRQ_NAND        28      /* NAND Flash Controller */
-#define IRQ_NAND_DMA    29      /* NAND Flash Controller DMA */
-#define IRQ_UART5       30      /* UART 5 */
-#define IRQ_UART4       31      /* UART 4 */
-#define IRQ_UART0       32      /* UART 0 */
-#define IRQ_UART1       33      /* UART 1 */
-#define IRQ_DMA2        34      /* DMA Channel 2 */
-#define IRQ_I2S         35      /* I2S */
-#define IRQ_PMCOS0      36      /* PMC OS Timer 0 */
-#define IRQ_PMCOS1      37      /* PMC OS Timer 1 */
-#define IRQ_PMCOS2      38      /* PMC OS Timer 2 */
-#define IRQ_PMCOS3      39      /* PMC OS Timer 3 */
-#define IRQ_DMA3        40      /* DMA Channel 3 */
-#define IRQ_DMA4        41      /* DMA Channel 4 */
-#define IRQ_AC97        42      /* AC97 Interface */
-                                /* Reserved */
-#define IRQ_NOR         44      /* NOR Flash Controller */
-#define IRQ_DMA5        45      /* DMA Channel 5 */
-#define IRQ_DMA6        46      /* DMA Channel 6 */
-#define IRQ_UART2       47      /* UART 2 */
-#define IRQ_RTC         48      /* RTC Interrupt */
-#define IRQ_RTCSM       49      /* RTC Second/Minute Update Interrupt */
-#define IRQ_UART3       50      /* UART 3 */
-#define IRQ_DMA7        51      /* DMA Channel 7 */
-#define IRQ_EXT5        52      /* External Interrupt 5 */
-#define IRQ_EXT6        53      /* External Interrupt 6 */
-#define IRQ_EXT7        54      /* External Interrupt 7 */
-#define IRQ_CIR         55      /* CIR */
-#define IRQ_SIC0        56      /* SIC IRQ0 */
-#define IRQ_SIC1        57      /* SIC IRQ1 */
-#define IRQ_SIC2        58      /* SIC IRQ2 */
-#define IRQ_SIC3        59      /* SIC IRQ3 */
-#define IRQ_SIC4        60      /* SIC IRQ4 */
-#define IRQ_SIC5        61      /* SIC IRQ5 */
-#define IRQ_SIC6        62      /* SIC IRQ6 */
-#define IRQ_SIC7        63      /* SIC IRQ7 */
-                                /* Reserved */
-#define IRQ_JPEGDEC     65      /* JPEG Decoder */
-#define IRQ_SAE         66      /* SAE (?) */
-                                /* Reserved */
-#define IRQ_VPU         79      /* Video Processing Unit */
-#define IRQ_VPP         80      /* Video Post-Processor */
-#define IRQ_VID         81      /* Video Digital Input Interface */
-#define IRQ_SPU         82      /* SPU (?) */
-#define IRQ_PIP         83      /* PIP Error */
-#define IRQ_GE          84      /* Graphic Engine */
-#define IRQ_GOV         85      /* Graphic Overlay Engine */
-#define IRQ_DVO         86      /* Digital Video Output */
-                                /* Reserved */
-#define IRQ_DMA8        92      /* DMA Channel 8 */
-#define IRQ_DMA9        93      /* DMA Channel 9 */
-#define IRQ_DMA10       94      /* DMA Channel 10 */
-#define IRQ_DMA11       95      /* DMA Channel 11 */
-#define IRQ_DMA12       96      /* DMA Channel 12 */
-#define IRQ_DMA13       97      /* DMA Channel 13 */
-#define IRQ_DMA14       98      /* DMA Channel 14 */
-#define IRQ_DMA15       99      /* DMA Channel 15 */
-                                /* Reserved */
-#define IRQ_GOVW        111     /* GOVW (?) */
-#define IRQ_GOVRSDSCD   112     /* GOVR SDSCD (?) */
-#define IRQ_GOVRSDMIF   113     /* GOVR SDMIF (?) */
-#define IRQ_GOVRHDSCD   114     /* GOVR HDSCD (?) */
-#define IRQ_GOVRHDMIF   115     /* GOVR HDMIF (?) */
-
-#define WM8505_NR_IRQS          116
diff --git a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h b/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
deleted file mode 100644
index df1550941efb..000000000000
--- a/arch/arm/mach-vt8500/include/mach/wm8505_regs.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/include/mach/wm8505_regs.h
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARM_ARCH_WM8505_REGS_H
-#define __ASM_ARM_ARCH_WM8505_REGS_H
-
-/* WM8505 Registers Map */
-
-#define WM8505_REGS_START_PHYS  0xd8000000      /* Start of MMIO registers */
-#define WM8505_REGS_START_VIRT  0xf8000000      /* Virtual mapping start */
-
-#define WM8505_DDR_BASE         0xd8000400      /* 1k   DDR/DDR2 Memory
-                                                        Controller */
-#define WM8505_DMA_BASE         0xd8001800      /* 1k   DMA Controller */
-#define WM8505_VDMA_BASE        0xd8001c00      /* 1k   VDMA */
-#define WM8505_SFLASH_BASE      0xd8002000      /* 1k   Serial Flash Memory
-                                                        Controller */
-#define WM8505_ETHER_BASE       0xd8004000      /* 1k   Ethernet MAC 0 */
-#define WM8505_CIPHER_BASE      0xd8006000      /* 4k   Cipher */
-#define WM8505_USB_BASE         0xd8007000      /* 2k   USB 2.0 Host */
-# define WM8505_EHCI_BASE       0xd8007100      /*      EHCI */
-# define WM8505_UHCI_BASE       0xd8007301      /*      UHCI */
-#define WM8505_PS2_BASE         0xd8008800      /* 1k   PS/2 */
-#define WM8505_NAND_BASE        0xd8009000      /* 1k   NAND Controller */
-#define WM8505_NOR_BASE         0xd8009400      /* 1k   NOR Controller */
-#define WM8505_SDMMC_BASE       0xd800a000      /* 1k   SD/MMC Controller */
-#define WM8505_VPU_BASE         0xd8050000      /* 256  VPU */
-#define WM8505_GOV_BASE         0xd8050300      /* 256  GOV */
-#define WM8505_GEGEA_BASE       0xd8050400      /* 768  GE/GE Alpha Mixing */
-#define WM8505_GOVR_BASE        0xd8050800      /* 512  GOVR (frambuffer) */
-#define WM8505_VID_BASE         0xd8050a00      /* 256  VID */
-#define WM8505_SCL_BASE         0xd8050d00      /* 256  SCL */
-#define WM8505_VPP_BASE         0xd8050f00      /* 256  VPP */
-#define WM8505_JPEGDEC_BASE     0xd80fe000      /* 4k   JPEG Decoder */
-#define WM8505_RTC_BASE         0xd8100000      /* 64k  RTC */
-#define WM8505_GPIO_BASE        0xd8110000      /* 64k  GPIO Configuration */
-#define WM8505_SCC_BASE         0xd8120000      /* 64k  System Configuration*/
-#define WM8505_PMC_BASE         0xd8130000      /* 64k  PMC Configuration */
-#define WM8505_IC_BASE          0xd8140000      /* 64k  Interrupt Controller*/
-#define WM8505_SIC_BASE         0xd8150000      /* 64k  Secondary IC */
-#define WM8505_UART0_BASE       0xd8200000      /* 64k  UART 0 */
-#define WM8505_UART2_BASE       0xd8210000      /* 64k  UART 2 */
-#define WM8505_PWM_BASE         0xd8220000      /* 64k  PWM Configuration */
-#define WM8505_SPI0_BASE        0xd8240000      /* 64k  SPI 0 */
-#define WM8505_SPI1_BASE        0xd8250000      /* 64k  SPI 1 */
-#define WM8505_KEYPAD_BASE      0xd8260000      /* 64k  Keypad control */
-#define WM8505_CIR_BASE         0xd8270000      /* 64k  CIR */
-#define WM8505_I2C0_BASE        0xd8280000      /* 64k  I2C 0 */
-#define WM8505_AC97_BASE        0xd8290000      /* 64k  AC97 */
-#define WM8505_SPI2_BASE        0xd82a0000      /* 64k  SPI 2 */
-#define WM8505_UART1_BASE       0xd82b0000      /* 64k  UART 1 */
-#define WM8505_UART3_BASE       0xd82c0000      /* 64k  UART 3 */
-#define WM8505_I2C1_BASE        0xd8320000      /* 64k  I2C 1 */
-#define WM8505_I2S_BASE         0xd8330000      /* 64k  I2S */
-#define WM8505_UART4_BASE       0xd8370000      /* 64k  UART 4 */
-#define WM8505_UART5_BASE       0xd8380000      /* 64k  UART 5 */
-
-#define WM8505_REGS_END_PHYS    0xd838ffff      /* End of MMIO registers */
-#define WM8505_REGS_LENGTH      (WM8505_REGS_END_PHYS \
-                                - WM8505_REGS_START_PHYS + 1)
-
-#endif
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 642de0408f25..f8f9ab9bc56e 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -1,6 +1,7 @@
 /*
  *  arch/arm/mach-vt8500/irq.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,81 +19,102 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original irq.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
 
 #include <asm/irq.h>
 
-#include "devices.h"
 
-#define VT8500_IC_DCTR          0x40            /* Destination control
-                                                register, 64*u8 */
-#define VT8500_INT_ENABLE       (1 << 3)
-#define VT8500_TRIGGER_HIGH     (0 << 4)
-#define VT8500_TRIGGER_RISING   (1 << 4)
-#define VT8500_TRIGGER_FALLING  (2 << 4)
+#define VT8500_ICPC_IRQ         0x20
+#define VT8500_ICPC_FIQ         0x24
+#define VT8500_ICDC             0x40            /* Destination Control 64*u32 */
+#define VT8500_ICIS             0x80            /* Interrupt status, 16*u32 */
+
+/* ICPC */
+#define ICPC_MASK               0x3F
+#define ICPC_ROTATE             BIT(6)
+
+/* IC_DCTR */
+#define ICDC_IRQ                0x00
+#define ICDC_FIQ                0x01
+#define ICDC_DSS0               0x02
+#define ICDC_DSS1               0x03
+#define ICDC_DSS2               0x04
+#define ICDC_DSS3               0x05
+#define ICDC_DSS4               0x06
+#define ICDC_DSS5               0x07
+
+#define VT8500_INT_DISABLE      0
+#define VT8500_INT_ENABLE       BIT(3)
+
+#define VT8500_TRIGGER_HIGH     0
+#define VT8500_TRIGGER_RISING   BIT(5)
+#define VT8500_TRIGGER_FALLING  BIT(6)
 #define VT8500_EDGE             ( VT8500_TRIGGER_RISING \
                                 | VT8500_TRIGGER_FALLING)
-#define VT8500_IC_STATUS        0x80            /* Interrupt status, 2*u32 */
 
-static void __iomem *ic_regbase;
-static void __iomem *sic_regbase;
+static int irq_cnt;
+
+struct vt8500_irq_priv {
+        void __iomem *base;
+};
 
 static void vt8500_irq_mask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 edge;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-        edge = readb(base + VT8500_IC_DCTR + irq) & VT8500_EDGE;
+        edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
         if (edge) {
-                void __iomem *stat_reg = base + VT8500_IC_STATUS
-                                                + (irq < 32 ? 0 : 4);
+                void __iomem *stat_reg = base + VT8500_ICIS
+                                                + (d->hwirq < 32 ? 0 : 4);
                 unsigned status = readl(stat_reg);
 
-                status |= (1 << (irq & 0x1f));
+                status |= (1 << (d->hwirq & 0x1f));
                 writel(status, stat_reg);
         } else {
-                u8 dctr = readb(base + VT8500_IC_DCTR + irq);
+                u8 dctr = readb(base + VT8500_ICDC + d->hwirq);
 
                 dctr &= ~VT8500_INT_ENABLE;
-                writeb(dctr, base + VT8500_IC_DCTR + irq);
+                writeb(dctr, base + VT8500_ICDC + d->hwirq);
         }
 }
 
 static void vt8500_irq_unmask(struct irq_data *d)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 dctr;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-        dctr = readb(base + VT8500_IC_DCTR + irq);
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
         dctr |= VT8500_INT_ENABLE;
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
 }
 
 static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        void __iomem *base = ic_regbase;
-        unsigned irq = d->irq;
-        unsigned orig_irq = irq;
+        struct vt8500_irq_priv *priv =
+                        (struct vt8500_irq_priv *)(d->domain->host_data);
+        void __iomem *base = priv->base;
         u8 dctr;
 
-        if (irq >= 64) {
-                base = sic_regbase;
-                irq -= 64;
-        }
-
-        dctr = readb(base + VT8500_IC_DCTR + irq);
+        dctr = readb(base + VT8500_ICDC + d->hwirq);
         dctr &= ~VT8500_EDGE;
 
         switch (flow_type) {
@@ -100,18 +122,18 @@ static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
                 return -EINVAL;
         case IRQF_TRIGGER_HIGH:
                 dctr |= VT8500_TRIGGER_HIGH;
-                __irq_set_handler_locked(orig_irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
                 break;
         case IRQF_TRIGGER_FALLING:
                 dctr |= VT8500_TRIGGER_FALLING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                 break;
         case IRQF_TRIGGER_RISING:
                 dctr |= VT8500_TRIGGER_RISING;
-                __irq_set_handler_locked(orig_irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                 break;
         }
-        writeb(dctr, base + VT8500_IC_DCTR + irq);
+        writeb(dctr, base + VT8500_ICDC + d->hwirq);
 
         return 0;
 }
@@ -124,57 +146,76 @@ static struct irq_chip vt8500_irq_chip = {
         .irq_set_type = vt8500_irq_set_type,
 };
 
-void __init vt8500_init_irq(void)
+static void __init vt8500_init_irq_hw(void __iomem *base)
 {
         unsigned int i;
 
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
+        /* Enable rotating priority for IRQ */
+        writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
+        writel(0x00, base + VT8500_ICPC_FIQ);
 
-        if (ic_regbase) {
-                /* Enable rotating priority for IRQ */
-                writel((1 << 6), ic_regbase + 0x20);
-                writel(0, ic_regbase + 0x24);
+        for (i = 0; i < 64; i++) {
+                /* Disable all interrupts and route them to IRQ */
+                writeb(VT8500_INT_DISABLE | ICDC_IRQ,
+                                                base + VT8500_ICDC + i);
+        }
+}
 
-                for (i = 0; i < wmt_nr_irqs; i++) {
-                        /* Disable all interrupts and route them to IRQ */
-                        writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
+static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
+                                                        irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID);
 
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
-                }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
-        }
+        return 0;
 }
 
-void __init wm8505_init_irq(void)
+static struct irq_domain_ops vt8500_irq_domain_ops = {
+        .map = vt8500_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+int __init vt8500_irq_init(struct device_node *node, struct device_node *parent)
 {
-        unsigned int i;
+        struct irq_domain *vt8500_irq_domain;
+        struct vt8500_irq_priv *priv;
+        int irq, i;
+        struct device_node *np = node;
+
+        priv = kzalloc(sizeof(struct vt8500_irq_priv), GFP_KERNEL);
+        priv->base = of_iomap(np, 0);
+
+        vt8500_irq_domain = irq_domain_add_legacy(node, 64, irq_cnt, 0,
+                                &vt8500_irq_domain_ops, priv);
+        if (!vt8500_irq_domain)
+                pr_err("%s: Unable to add wmt irq domain!\n", __func__);
+
+        irq_set_default_host(vt8500_irq_domain);
+
+        vt8500_init_irq_hw(priv->base);
 
-        ic_regbase = ioremap(wmt_ic_base, SZ_64K);
-        sic_regbase = ioremap(wmt_sic_base, SZ_64K);
-
-        if (ic_regbase && sic_regbase) {
-                /* Enable rotating priority for IRQ */
-                writel((1 << 6), ic_regbase + 0x20);
-                writel(0, ic_regbase + 0x24);
-                writel((1 << 6), sic_regbase + 0x20);
-                writel(0, sic_regbase + 0x24);
-
-                for (i = 0; i < wmt_nr_irqs; i++) {
-                        /* Disable all interrupts and route them to IRQ */
-                        if (i < 64)
-                                writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
-                        else
-                                writeb(0x00, sic_regbase + VT8500_IC_DCTR
-                                                                + i - 64);
-
-                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID);
+        pr_info("Added IRQ Controller @ %x [virq_base = %d]\n",
+                                                (u32)(priv->base), irq_cnt);
+
+        /* check if this is a slaved controller */
+        if (of_irq_count(np) != 0) {
+                /* check that we have the correct number of interrupts */
+                if (of_irq_count(np) != 8) {
+                        pr_err("%s: Incorrect IRQ map for slave controller\n",
+                                        __func__);
+                        return -EINVAL;
                 }
-        } else {
-                printk(KERN_ERR "Unable to remap the Interrupt Controller registers, not enabling IRQs!\n");
+
+                for (i = 0; i < 8; i++) {
+                        irq = irq_of_parse_and_map(np, i);
+                        enable_irq(irq);
+                }
+
+                pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
         }
+
+        irq_cnt += 64;
+
+        return 0;
 }
+
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
deleted file mode 100644
index 497e89a5e130..000000000000
--- a/arch/arm/mach-vt8500/restart.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-vt8500/restart.c
- *
- * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <asm/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#define LEGACY_PMC_BASE         0xD8130000
-#define WMT_PRIZM_PMSR_REG      0x60
-
-static void __iomem *pmc_base;
-
-void wmt_setup_restart(void)
-{
-        struct device_node *np;
-
-        /*
-         * Check if Power Mgmt Controller node is present in device tree. If no
-         * device tree node, use the legacy PMSR value (valid for all current
-         * SoCs).
-         */
-        np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
-        if (np) {
-                pmc_base = of_iomap(np, 0);
-
-                if (!pmc_base)
-                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
-
-                of_node_put(np);
-        } else {
-                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
-                if (!pmc_base) {
-                        pr_err("%s:ioremap(rstc) failed\n", __func__);
-                        return;
-                }
-        }
-}
-
-void wmt_restart(char mode, const char *cmd)
-{
-        if (pmc_base)
-                writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
-}
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index d5376c592ab6..050e1833f2d0 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -1,6 +1,7 @@
 /*
- *  arch/arm/mach-vt8500/timer.c
+ *  arch/arm/mach-vt8500/timer_dt.c
  *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -18,18 +19,25 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This file is copied and modified from the original timer.c provided by
+ * Alexey Charkov. Minor changes have been made for Device Tree Support.
+ */
+
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/delay.h>
-
 #include <asm/mach/time.h>
 
-#include "devices.h"
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #define VT8500_TIMER_OFFSET     0x0100
+#define VT8500_TIMER_HZ         3000000
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0010
 #define TIMER_STATUS_VAL        0x0014
@@ -39,7 +47,6 @@
 #define TIMER_COUNT_R_ACTIVE    (1 << 5)        /* not ready for read */
 #define TIMER_COUNT_W_ACTIVE    (1 << 4)        /* not ready for write */
 #define TIMER_MATCH_W_ACTIVE    (1 << 0)        /* not ready for write */
-#define VT8500_TIMER_HZ         3000000
 
 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 
@@ -55,7 +62,7 @@ static cycle_t vt8500_timer_read(struct clocksource *cs)
         return readl(regbase + TIMER_COUNT_VAL);
 }
 
-struct clocksource clocksource = {
+static struct clocksource clocksource = {
         .name           = "vt8500_timer",
         .rating         = 200,
         .read           = vt8500_timer_read,
@@ -98,7 +105,7 @@ static void vt8500_timer_set_mode(enum clock_event_mode mode,
         }
 }
 
-struct clock_event_device clockevent = {
+static struct clock_event_device clockevent = {
         .name           = "vt8500_timer",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 200,
@@ -115,26 +122,51 @@ static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-struct irqaction irq = {
+static struct irqaction irq = {
         .name    = "vt8500_timer",
         .flags   = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .handler = vt8500_timer_interrupt,
         .dev_id  = &clockevent,
 };
 
-static void __init vt8500_timer_init(void)
+static struct of_device_id vt8500_timer_ids[] = {
+        { .compatible = "via,vt8500-timer" },
+        { }
+};
+
+void __init vt8500_timer_init(void)
 {
-        regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
-        if (!regbase)
-                printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
+        struct device_node *np;
+        int timer_irq;
+
+        np = of_find_matching_node(NULL, vt8500_timer_ids);
+        if (!np) {
+                pr_err("%s: Timer description missing from Device Tree\n",
+                                                                __func__);
+                return;
+        }
+        regbase = of_iomap(np, 0);
+        if (!regbase) {
+                pr_err("%s: Missing iobase description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
+        timer_irq = irq_of_parse_and_map(np, 0);
+        if (!timer_irq) {
+                pr_err("%s: Missing irq description in Device Tree\n",
+                                                                __func__);
+                of_node_put(np);
+                return;
+        }
 
         writel(1, regbase + TIMER_CTRL_VAL);
         writel(0xf, regbase + TIMER_STATUS_VAL);
         writel(~0, regbase + TIMER_MATCH_VAL);
 
         if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
-                printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
-                                        clocksource.name);
+                pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
+                                        __func__, clocksource.name);
 
         clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
 
@@ -144,12 +176,9 @@ static void __init vt8500_timer_init(void)
         clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
         clockevent.cpumask = cpumask_of(0);
 
-        if (setup_irq(wmt_timer_irq, &irq))
-                printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
-                                        clockevent.name);
+        if (setup_irq(timer_irq, &irq))
+                pr_err("%s: setup_irq failed for %s\n", __func__,
+                                                        clockevent.name);
         clockevents_register_device(&clockevent);
 }
 
-struct sys_timer vt8500_timer = {
-        .init = vt8500_timer_init
-};
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
new file mode 100644
index 000000000000..587ea950d08b
--- /dev/null
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -0,0 +1,195 @@
+/*
+ *  arch/arm/mach-vt8500/vt8500.c
+ *
+ *  Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <mach/restart.h>
+
+#include "common.h"
+
+#define LEGACY_GPIO_BASE        0xD8110000
+#define LEGACY_PMC_BASE         0xD8130000
+
+/* Registers in GPIO Controller */
+#define VT8500_GPIO_MUX_REG     0x200
+
+/* Registers in Power Management Controller */
+#define VT8500_HCR_REG          0x12
+#define VT8500_PMSR_REG         0x60
+
+static void __iomem *pmc_base;
+
+void vt8500_restart(char mode, const char *cmd)
+{
+        if (pmc_base)
+                writel(1, pmc_base + VT8500_PMSR_REG);
+}
+
+static struct map_desc vt8500_io_desc[] __initdata = {
+        /* SoC MMIO registers */
+        [0] = {
+                .virtual        = 0xf8000000,
+                .pfn            = __phys_to_pfn(0xd8000000),
+                .length         = 0x00390000, /* max of all chip variants */
+                .type           = MT_DEVICE
+        },
+};
+
+void __init vt8500_map_io(void)
+{
+        iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc));
+}
+
+static void vt8500_power_off(void)
+{
+        local_irq_disable();
+        writew(5, pmc_base + VT8500_HCR_REG);
+        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
+}
+
+void __init vt8500_init(void)
+{
+        struct device_node *np, *fb;
+        void __iomem *gpio_base;
+
+#ifdef CONFIG_FB_VT8500
+        fb = of_find_compatible_node(NULL, NULL, "via,vt8500-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "via,vt8500-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) | 1,
+                                gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+                of_node_put(fb);
+        }
+#endif
+
+#ifdef CONFIG_FB_WM8505
+        fb = of_find_compatible_node(NULL, NULL, "wm,wm8505-fb");
+        if (fb) {
+                np = of_find_compatible_node(NULL, NULL, "wm,wm8505-gpio");
+                if (!np)
+                        np = of_find_compatible_node(NULL, NULL,
+                                                        "wm,wm8650-gpio");
+                if (np) {
+                        gpio_base = of_iomap(np, 0);
+
+                        if (!gpio_base)
+                                pr_err("%s: of_iomap(gpio_mux) failed\n",
+                                                                __func__);
+
+                        of_node_put(np);
+                } else {
+                        gpio_base = ioremap(LEGACY_GPIO_BASE, 0x1000);
+                        if (!gpio_base)
+                                pr_err("%s: ioremap(legacy_gpio_mux) failed\n",
+                                                                __func__);
+                }
+                if (gpio_base) {
+                        writel(readl(gpio_base + VT8500_GPIO_MUX_REG) |
+                                0x80000000, gpio_base + VT8500_GPIO_MUX_REG);
+                        iounmap(gpio_base);
+                } else
+                        pr_err("%s: Could not remap GPIO mux\n", __func__);
+
+                of_node_put(fb);
+        }
+#endif
+
+        np = of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
+        if (np) {
+                pmc_base = of_iomap(np, 0);
+
+                if (!pmc_base)
+                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+                of_node_put(np);
+        } else {
+                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+                if (!pmc_base)
+                        pr_err("%s:ioremap(power_off) failed\n", __func__);
+        }
+        if (pmc_base)
+                pm_power_off = &vt8500_power_off;
+        else
+                pr_err("%s: PMC Hibernation register could not be remapped, not enabling power off!\n", __func__);
+
+        vtwm_clk_init(pmc_base);
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const struct of_device_id vt8500_irq_match[] __initconst = {
+        { .compatible = "via,vt8500-intc", .data = vt8500_irq_init, },
+        { /* sentinel */ },
+};
+
+static void __init vt8500_init_irq(void)
+{
+        of_irq_init(vt8500_irq_match);
+};
+
+static struct sys_timer vt8500_timer = {
+        .init = vt8500_timer_init,
+};
+
+static const char * const vt8500_dt_compat[] = {
+        "via,vt8500",
+        "wm,wm8650",
+        "wm,wm8505",
+};
+
+DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
+        .dt_compat      = vt8500_dt_compat,
+        .map_io         = vt8500_map_io,
+        .init_irq       = vt8500_init_irq,
+        .timer          = &vt8500_timer,
+        .init_machine   = vt8500_init,
+        .restart        = vt8500_restart,
+MACHINE_END
+
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
deleted file mode 100644
index 4804e2a45574..000000000000
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *  arch/arm/mach-vt8500/wm8505_7in.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/io.h>
-#include <linux/pm.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/restart.h>
-
-#include "devices.h"
-
-static void __iomem *pmc_hiber;
-
-static struct platform_device *devices[] __initdata = {
-        &vt8500_device_uart0,
-        &vt8500_device_ehci,
-        &vt8500_device_uhci,
-        &vt8500_device_wm8505_fb,
-        &vt8500_device_ge_rops,
-        &vt8500_device_pwm,
-        &vt8500_device_pwmbl,
-        &vt8500_device_rtc,
-};
-
-static void vt8500_power_off(void)
-{
-        local_irq_disable();
-        writew(5, pmc_hiber);
-        asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0));
-}
-
-void __init wm8505_7in_init(void)
-{
-#ifdef CONFIG_FB_WM8505
-        void __iomem *gpio_mux_reg = ioremap(wmt_gpio_base + 0x200, 4);
-        if (gpio_mux_reg) {
-                writel(readl(gpio_mux_reg) | 0x80000000, gpio_mux_reg);
-                iounmap(gpio_mux_reg);
-        } else {
-                printk(KERN_ERR "Could not remap the GPIO mux register, display may not work properly!\n");
-        }
-#endif
-        pmc_hiber = ioremap(wmt_pmc_base + 0x12, 2);
-        if (pmc_hiber)
-                pm_power_off = &vt8500_power_off;
-        else
-                printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-        wmt_setup_restart();
-        wm8505_set_resources();
-        platform_add_devices(devices, ARRAY_SIZE(devices));
-        vt8500_gpio_init();
-}
-
-MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
-        .atag_offset    = 0x100,
-        .restart        = wmt_restart,
-        .reserve        = wm8505_reserve_mem,
-        .map_io         = wm8505_map_io,
-        .init_irq       = wm8505_init_irq,
-        .timer          = &vt8500_timer,
-        .init_machine   = wm8505_7in_init,
-MACHINE_END
diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
index 23a7643e9a87..1be0f4e5e6eb 100644
--- a/arch/arm/mm/cache-tauros2.c
+++ b/arch/arm/mm/cache-tauros2.c
@@ -15,8 +15,11 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <asm/cacheflush.h>
 #include <asm/cp15.h>
+#include <asm/cputype.h>
 #include <asm/hardware/cache-tauros2.h>
 
 
@@ -144,25 +147,8 @@ static inline void __init write_extra_features(u32 u)
         __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
 }
 
-static void __init disable_l2_prefetch(void)
-{
-        u32 u;
-
-        /*
-         * Read the CPU Extra Features register and verify that the
-         * Disable L2 Prefetch bit is set.
-         */
-        u = read_extra_features();
-        if (!(u & 0x01000000)) {
-                printk(KERN_INFO "Tauros2: Disabling L2 prefetch.\n");
-                write_extra_features(u | 0x01000000);
-        }
-}
-
 static inline int __init cpuid_scheme(void)
 {
-        extern int processor_id;
-
         return !!((processor_id & 0x000f0000) == 0x000f0000);
 }
 
@@ -189,12 +175,36 @@ static inline void __init write_actlr(u32 actlr)
         __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
 }
 
-void __init tauros2_init(void)
+static void enable_extra_feature(unsigned int features)
+{
+        u32 u;
+
+        u = read_extra_features();
+
+        if (features & CACHE_TAUROS2_PREFETCH_ON)
+                u &= ~0x01000000;
+        else
+                u |= 0x01000000;
+        printk(KERN_INFO "Tauros2: %s L2 prefetch.\n",
+                        (features & CACHE_TAUROS2_PREFETCH_ON)
+                        ? "Enabling" : "Disabling");
+
+        if (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                u |= 0x00100000;
+        else
+                u &= ~0x00100000;
+        printk(KERN_INFO "Tauros2: %s line fill burt8.\n",
+                        (features & CACHE_TAUROS2_LINEFILL_BURST8)
+                        ? "Enabling" : "Disabling");
+
+        write_extra_features(u);
+}
+
+static void __init tauros2_internal_init(unsigned int features)
 {
-        extern int processor_id;
-        char *mode;
+        char *mode = NULL;
 
-        disable_l2_prefetch();
+        enable_extra_feature(features);
 
 #ifdef CONFIG_CPU_32v5
         if ((processor_id & 0xff0f0000) == 0x56050000) {
@@ -286,3 +296,34 @@ void __init tauros2_init(void)
         printk(KERN_INFO "Tauros2: L2 cache support initialised "
                          "in %s mode.\n", mode);
 }
+
+#ifdef CONFIG_OF
+static const struct of_device_id tauros2_ids[] __initconst = {
+        { .compatible = "marvell,tauros2-cache"},
+        {}
+};
+#endif
+
+void __init tauros2_init(unsigned int features)
+{
+#ifdef CONFIG_OF
+        struct device_node *node;
+        int ret;
+        unsigned int f;
+
+        node = of_find_matching_node(NULL, tauros2_ids);
+        if (!node) {
+                pr_info("Not found marvell,tauros2-cache, disable it\n");
+                return;
+        }
+
+        ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);
+        if (ret) {
+                pr_info("Not found marvell,tauros-cache-features property, "
+                        "disable extra features\n");
+                features = 0;
+        } else
+                features = f;
+#endif
+        tauros2_internal_init(features);
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7128e9710417..28ba09f4ebb9 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
 extern void imx35_soc_init(void);
 extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
-extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
 extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
@@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
 extern void imx_gpc_pre_suspend(void);
 extern void imx_gpc_post_resume(void);
-extern void imx51_babbage_common_init(void);
-extern void imx53_ard_common_init(void);
-extern void imx53_evk_common_init(void);
-extern void imx53_qsb_common_init(void);
-extern void imx53_smd_common_init(void);
 extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
 extern void imx6q_clock_map_io(void);
 
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
deleted file mode 100644
index 9761e003bde2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ /dev/null
@@ -1,1219 +0,0 @@
-/*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc..
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_IOMUX_MX53_H__
-#define __MACH_IOMUX_MX53_H__
-
-#include <mach/iomux-v3.h>
-
-/* These 2 defines are for pins that may not have a mux register, but could
- * have a pad setting register, and vice-versa. */
-#define __NA_   0x00
-
-#define MX53_UART_PAD_CTRL              (PAD_CTL_PKE | PAD_CTL_PUE |    \
-                PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define MX53_SDHC_PAD_CTRL      (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
-                                PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH | \
-                                PAD_CTL_SRE_FAST)
-
-
-#define MX53_PAD_GPIO_19__KPP_COL_5                     IOMUX_PAD(0x348, 0x020, 0, 0x840, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__GPIO4_5                       IOMUX_PAD(0x348, 0x020, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__CCM_CLKO                      IOMUX_PAD(0x348, 0x020, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SPDIF_OUT1                    IOMUX_PAD(0x348, 0x020, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2          IOMUX_PAD(0x348, 0x020, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__ECSPI1_RDY                    IOMUX_PAD(0x348, 0x020, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__FEC_TDATA_3                   IOMUX_PAD(0x348, 0x020, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_19__SRC_INT_BOOT                  IOMUX_PAD(0x348, 0x020, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__KPP_COL_0                    IOMUX_PAD(0x34C, 0x024, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__GPIO4_6                      IOMUX_PAD(0x34C, 0x024, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC              IOMUX_PAD(0x34C, 0x024, 2, 0x758, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX                IOMUX_PAD(0x34C, 0x024, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__ECSPI1_SCLK                  IOMUX_PAD(0x34C, 0x024, 5, 0x79C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__FEC_RDATA_3                  IOMUX_PAD(0x34C, 0x024, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST               IOMUX_PAD(0x34C, 0x024, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__KPP_ROW_0                    IOMUX_PAD(0x350, 0x028, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__GPIO4_7                      IOMUX_PAD(0x350, 0x028, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD              IOMUX_PAD(0x350, 0x028, 2, 0x74C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX                IOMUX_PAD(0x350, 0x028, 4, 0x890, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI                  IOMUX_PAD(0x350, 0x028, 5, 0x7A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW0__FEC_TX_ER                    IOMUX_PAD(0x350, 0x028, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__KPP_COL_1                    IOMUX_PAD(0x354, 0x02C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__GPIO4_8                      IOMUX_PAD(0x354, 0x02C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS             IOMUX_PAD(0x354, 0x02C, 2, 0x75C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX                IOMUX_PAD(0x354, 0x02C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__ECSPI1_MISO                  IOMUX_PAD(0x354, 0x02C, 5, 0x7A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__FEC_RX_CLK                   IOMUX_PAD(0x354, 0x02C, 6, 0x808, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY              IOMUX_PAD(0x354, 0x02C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__KPP_ROW_1                    IOMUX_PAD(0x358, 0x030, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__GPIO4_9                      IOMUX_PAD(0x358, 0x030, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD              IOMUX_PAD(0x358, 0x030, 2, 0x748, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX                IOMUX_PAD(0x358, 0x030, 4, 0x898, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__ECSPI1_SS0                   IOMUX_PAD(0x358, 0x030, 5, 0x7A8, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__FEC_COL                      IOMUX_PAD(0x358, 0x030, 6, 0x800, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID              IOMUX_PAD(0x358, 0x030, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__KPP_COL_2                    IOMUX_PAD(0x35C, 0x034, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__GPIO4_10                     IOMUX_PAD(0x35C, 0x034, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__CAN1_TXCAN                   IOMUX_PAD(0x35C, 0x034, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_MDIO                     IOMUX_PAD(0x35C, 0x034, 4, 0x804, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__ECSPI1_SS1                   IOMUX_PAD(0x35C, 0x034, 5, 0x7AC, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__FEC_RDATA_2                  IOMUX_PAD(0x35C, 0x034, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL2__USBPHY1_RXACTIVE             IOMUX_PAD(0x35C, 0x034, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__KPP_ROW_2                    IOMUX_PAD(0x360, 0x038, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__GPIO4_11                     IOMUX_PAD(0x360, 0x038, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__CAN1_RXCAN                   IOMUX_PAD(0x360, 0x038, 2, 0x760, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_MDC                      IOMUX_PAD(0x360, 0x038, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__ECSPI1_SS2                   IOMUX_PAD(0x360, 0x038, 5, 0x7B0, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__FEC_TDATA_2                  IOMUX_PAD(0x360, 0x038, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW2__USBPHY1_RXERROR              IOMUX_PAD(0x360, 0x038, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__KPP_COL_3                    IOMUX_PAD(0x364, 0x03C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__GPIO4_12                     IOMUX_PAD(0x364, 0x03C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBOH3_H2_DP                 IOMUX_PAD(0x364, 0x03C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__SPDIF_IN1                    IOMUX_PAD(0x364, 0x03C, 3, 0x870, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__I2C2_SCL                     IOMUX_PAD(0x364, 0x03C, 4 | IOMUX_CONFIG_SION, 0x81C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__ECSPI1_SS3                   IOMUX_PAD(0x364, 0x03C, 5, 0x7B4, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__FEC_CRS                      IOMUX_PAD(0x364, 0x03C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL3__USBPHY1_SIECLOCK             IOMUX_PAD(0x364, 0x03C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__KPP_ROW_3                    IOMUX_PAD(0x368, 0x040, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__GPIO4_13                     IOMUX_PAD(0x368, 0x040, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBOH3_H2_DM                 IOMUX_PAD(0x368, 0x040, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_ASRC_EXT_CLK             IOMUX_PAD(0x368, 0x040, 3, 0x768, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__I2C2_SDA                     IOMUX_PAD(0x368, 0x040, 4 | IOMUX_CONFIG_SION, 0x820, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__OSC32K_32K_OUT               IOMUX_PAD(0x368, 0x040, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__CCM_PLL4_BYP                 IOMUX_PAD(0x368, 0x040, 6, 0x77C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW3__USBPHY1_LINESTATE_0          IOMUX_PAD(0x368, 0x040, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__KPP_COL_4                    IOMUX_PAD(0x36C, 0x044, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__GPIO4_14                     IOMUX_PAD(0x36C, 0x044, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__CAN2_TXCAN                   IOMUX_PAD(0x36C, 0x044, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__IPU_SISG_4                   IOMUX_PAD(0x36C, 0x044, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__UART5_RTS                    IOMUX_PAD(0x36C, 0x044, 4, 0x894, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC             IOMUX_PAD(0x36C, 0x044, 5, 0x89C, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1          IOMUX_PAD(0x36C, 0x044, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__KPP_ROW_4                    IOMUX_PAD(0x370, 0x048, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__GPIO4_15                     IOMUX_PAD(0x370, 0x048, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__CAN2_RXCAN                   IOMUX_PAD(0x370, 0x048, 2, 0x764, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__IPU_SISG_5                   IOMUX_PAD(0x370, 0x048, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__UART5_CTS                    IOMUX_PAD(0x370, 0x048, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR            IOMUX_PAD(0x370, 0x048, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID            IOMUX_PAD(0x370, 0x048, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK         IOMUX_PAD(0x378, 0x04C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__GPIO4_16                 IOMUX_PAD(0x378, 0x04C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBOH3_USBH2_DIR         IOMUX_PAD(0x378, 0x04C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__SDMA_DEBUG_CORE_STATE_0  IOMUX_PAD(0x378, 0x04C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__EMI_EMI_DEBUG_0          IOMUX_PAD(0x378, 0x04C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_DISP_CLK__USBPHY1_AVALID           IOMUX_PAD(0x378, 0x04C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               IOMUX_PAD(0x37C, 0x050, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__GPIO4_17                    IOMUX_PAD(0x37C, 0x050, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__AUDMUX_AUD6_TXC             IOMUX_PAD(0x37C, 0x050, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1     IOMUX_PAD(0x37C, 0x050, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__EMI_EMI_DEBUG_1             IOMUX_PAD(0x37C, 0x050, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN15__USBPHY1_BVALID              IOMUX_PAD(0x37C, 0x050, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__IPU_DI0_PIN2                 IOMUX_PAD(0x380, 0x054, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__GPIO4_18                     IOMUX_PAD(0x380, 0x054, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__AUDMUX_AUD6_TXD              IOMUX_PAD(0x380, 0x054, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2      IOMUX_PAD(0x380, 0x054, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__EMI_EMI_DEBUG_2              IOMUX_PAD(0x380, 0x054, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN2__USBPHY1_ENDSESSION           IOMUX_PAD(0x380, 0x054, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 IOMUX_PAD(0x384, 0x058, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__GPIO4_19                     IOMUX_PAD(0x384, 0x058, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__AUDMUX_AUD6_TXFS             IOMUX_PAD(0x384, 0x058, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3      IOMUX_PAD(0x384, 0x058, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__EMI_EMI_DEBUG_3              IOMUX_PAD(0x384, 0x058, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN3__USBPHY1_IDDIG                IOMUX_PAD(0x384, 0x058, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__IPU_DI0_PIN4                 IOMUX_PAD(0x388, 0x05C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__GPIO4_20                     IOMUX_PAD(0x388, 0x05C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__AUDMUX_AUD6_RXD              IOMUX_PAD(0x388, 0x05C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__ESDHC1_WP                    IOMUX_PAD(0x388, 0x05C, 3, 0x7FC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__SDMA_DEBUG_YIELD             IOMUX_PAD(0x388, 0x05C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__EMI_EMI_DEBUG_4              IOMUX_PAD(0x388, 0x05C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DI0_PIN4__USBPHY1_HOSTDISCONNECT       IOMUX_PAD(0x388, 0x05C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            IOMUX_PAD(0x38C, 0x060, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__GPIO4_21                   IOMUX_PAD(0x38C, 0x060, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__CSPI_SCLK                  IOMUX_PAD(0x38C, 0x060, 2, 0x780, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBOH3_USBH2_DATA_0        IOMUX_PAD(0x38C, 0x060, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN        IOMUX_PAD(0x38C, 0x060, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__EMI_EMI_DEBUG_5            IOMUX_PAD(0x38C, 0x060, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT0__USBPHY2_TXREADY            IOMUX_PAD(0x38C, 0x060, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            IOMUX_PAD(0x390, 0x064, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__GPIO4_22                   IOMUX_PAD(0x390, 0x064, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__CSPI_MOSI                  IOMUX_PAD(0x390, 0x064, 2, 0x788, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBOH3_USBH2_DATA_1        IOMUX_PAD(0x390, 0x064, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL       \
-                                                        IOMUX_PAD(0x390, 0x064, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__EMI_EMI_DEBUG_6            IOMUX_PAD(0x390, 0x064, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT1__USBPHY2_RXVALID            IOMUX_PAD(0x390, 0x064, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            IOMUX_PAD(0x394, 0x068, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__GPIO4_23                   IOMUX_PAD(0x394, 0x068, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__CSPI_MISO                  IOMUX_PAD(0x394, 0x068, 2, 0x784, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBOH3_USBH2_DATA_2        IOMUX_PAD(0x394, 0x068, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__SDMA_DEBUG_MODE            IOMUX_PAD(0x394, 0x068, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__EMI_EMI_DEBUG_7            IOMUX_PAD(0x394, 0x068, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT2__USBPHY2_RXACTIVE           IOMUX_PAD(0x394, 0x068, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            IOMUX_PAD(0x398, 0x06C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__GPIO4_24                   IOMUX_PAD(0x398, 0x06C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__CSPI_SS0                   IOMUX_PAD(0x398, 0x06C, 2, 0x78C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBOH3_USBH2_DATA_3        IOMUX_PAD(0x398, 0x06C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR       IOMUX_PAD(0x398, 0x06C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__EMI_EMI_DEBUG_8            IOMUX_PAD(0x398, 0x06C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT3__USBPHY2_RXERROR            IOMUX_PAD(0x398, 0x06C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            IOMUX_PAD(0x39C, 0x070, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__GPIO4_25                   IOMUX_PAD(0x39C, 0x070, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__CSPI_SS1                   IOMUX_PAD(0x39C, 0x070, 2, 0x790, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBOH3_USBH2_DATA_4        IOMUX_PAD(0x39C, 0x070, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB         IOMUX_PAD(0x39C, 0x070, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__EMI_EMI_DEBUG_9            IOMUX_PAD(0x39C, 0x070, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT4__USBPHY2_SIECLOCK           IOMUX_PAD(0x39C, 0x070, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            IOMUX_PAD(0x3A0, 0x074, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__GPIO4_26                   IOMUX_PAD(0x3A0, 0x074, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__CSPI_SS2                   IOMUX_PAD(0x3A0, 0x074, 2, 0x794, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBOH3_USBH2_DATA_5        IOMUX_PAD(0x3A0, 0x074, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS   IOMUX_PAD(0x3A0, 0x074, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__EMI_EMI_DEBUG_10           IOMUX_PAD(0x3A0, 0x074, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT5__USBPHY2_LINESTATE_0        IOMUX_PAD(0x3A0, 0x074, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            IOMUX_PAD(0x3A4, 0x078, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__GPIO4_27                   IOMUX_PAD(0x3A4, 0x078, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__CSPI_SS3                   IOMUX_PAD(0x3A4, 0x078, 2, 0x798, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBOH3_USBH2_DATA_6        IOMUX_PAD(0x3A4, 0x078, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE  IOMUX_PAD(0x3A4, 0x078, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__EMI_EMI_DEBUG_11           IOMUX_PAD(0x3A4, 0x078, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT6__USBPHY2_LINESTATE_1        IOMUX_PAD(0x3A4, 0x078, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            IOMUX_PAD(0x3A8, 0x07C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__GPIO4_28                   IOMUX_PAD(0x3A8, 0x07C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__CSPI_RDY                   IOMUX_PAD(0x3A8, 0x07C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBOH3_USBH2_DATA_7        IOMUX_PAD(0x3A8, 0x07C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 IOMUX_PAD(0x3A8, 0x07C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__EMI_EMI_DEBUG_12           IOMUX_PAD(0x3A8, 0x07C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT7__USBPHY2_VBUSVALID          IOMUX_PAD(0x3A8, 0x07C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            IOMUX_PAD(0x3AC, 0x080, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__GPIO4_29                   IOMUX_PAD(0x3AC, 0x080, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__PWM1_PWMO                  IOMUX_PAD(0x3AC, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__WDOG1_WDOG_B               IOMUX_PAD(0x3AC, 0x080, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 IOMUX_PAD(0x3AC, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__EMI_EMI_DEBUG_13           IOMUX_PAD(0x3AC, 0x080, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT8__USBPHY2_AVALID             IOMUX_PAD(0x3AC, 0x080, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            IOMUX_PAD(0x3B0, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__GPIO4_30                   IOMUX_PAD(0x3B0, 0x084, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__PWM2_PWMO                  IOMUX_PAD(0x3B0, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__WDOG2_WDOG_B               IOMUX_PAD(0x3B0, 0x084, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 IOMUX_PAD(0x3B0, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__EMI_EMI_DEBUG_14           IOMUX_PAD(0x3B0, 0x084, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT9__USBPHY2_VSTATUS_0          IOMUX_PAD(0x3B0, 0x084, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          IOMUX_PAD(0x3B4, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__GPIO4_31                  IOMUX_PAD(0x3B4, 0x088, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBOH3_USBH2_STP          IOMUX_PAD(0x3B4, 0x088, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3        \
-                                                        IOMUX_PAD(0x3B4, 0x088, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__EMI_EMI_DEBUG_15          IOMUX_PAD(0x3B4, 0x088, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT10__USBPHY2_VSTATUS_1         IOMUX_PAD(0x3B4, 0x088, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          IOMUX_PAD(0x3B8, 0x08C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__GPIO5_5                   IOMUX_PAD(0x3B8, 0x08C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBOH3_USBH2_NXT          IOMUX_PAD(0x3B8, 0x08C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4        \
-                                                        IOMUX_PAD(0x3B8, 0x08C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__EMI_EMI_DEBUG_16          IOMUX_PAD(0x3B8, 0x08C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT11__USBPHY2_VSTATUS_2         IOMUX_PAD(0x3B8, 0x08C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          IOMUX_PAD(0x3BC, 0x090, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__GPIO5_6                   IOMUX_PAD(0x3BC, 0x090, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBOH3_USBH2_CLK          IOMUX_PAD(0x3BC, 0x090, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5        \
-                                                        IOMUX_PAD(0x3BC, 0x090, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__EMI_EMI_DEBUG_17          IOMUX_PAD(0x3BC, 0x090, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT12__USBPHY2_VSTATUS_3         IOMUX_PAD(0x3BC, 0x090, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          IOMUX_PAD(0x3C0, 0x094, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__GPIO5_7                   IOMUX_PAD(0x3C0, 0x094, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS          IOMUX_PAD(0x3C0, 0x094, 3, 0x754, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0        \
-                                                        IOMUX_PAD(0x3C0, 0x094, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__EMI_EMI_DEBUG_18          IOMUX_PAD(0x3C0, 0x094, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT13__USBPHY2_VSTATUS_4         IOMUX_PAD(0x3C0, 0x094, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          IOMUX_PAD(0x3C4, 0x098, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__GPIO5_8                   IOMUX_PAD(0x3C4, 0x098, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC           IOMUX_PAD(0x3C4, 0x098, 3, 0x750, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1        \
-                                                        IOMUX_PAD(0x3C4, 0x098, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__EMI_EMI_DEBUG_19          IOMUX_PAD(0x3C4, 0x098, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT14__USBPHY2_VSTATUS_5         IOMUX_PAD(0x3C4, 0x098, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          IOMUX_PAD(0x3C8, 0x09C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__GPIO5_9                   IOMUX_PAD(0x3C8, 0x09C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI1_SS1                IOMUX_PAD(0x3C8, 0x09C, 2, 0x7AC, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__ECSPI2_SS1                IOMUX_PAD(0x3C8, 0x09C, 3, 0x7C8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2        \
-                                                        IOMUX_PAD(0x3C8, 0x09C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__EMI_EMI_DEBUG_20          IOMUX_PAD(0x3C8, 0x09C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT15__USBPHY2_VSTATUS_6         IOMUX_PAD(0x3C8, 0x09C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          IOMUX_PAD(0x3CC, 0x0A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__GPIO5_10                  IOMUX_PAD(0x3CC, 0x0A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__ECSPI2_MOSI               IOMUX_PAD(0x3CC, 0x0A0, 2, 0x7C0, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__AUDMUX_AUD5_TXC           IOMUX_PAD(0x3CC, 0x0A0, 3, 0x758, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_EXT_EVENT_0          IOMUX_PAD(0x3CC, 0x0A0, 4, 0x868, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__SDMA_DEBUG_EVT_CHN_LINES_3        \
-                                                        IOMUX_PAD(0x3CC, 0x0A0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__EMI_EMI_DEBUG_21          IOMUX_PAD(0x3CC, 0x0A0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT16__USBPHY2_VSTATUS_7         IOMUX_PAD(0x3CC, 0x0A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          IOMUX_PAD(0x3D0, 0x0A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__GPIO5_11                  IOMUX_PAD(0x3D0, 0x0A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__ECSPI2_MISO               IOMUX_PAD(0x3D0, 0x0A4, 2, 0x7BC, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__AUDMUX_AUD5_TXD           IOMUX_PAD(0x3D0, 0x0A4, 3, 0x74C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_EXT_EVENT_1          IOMUX_PAD(0x3D0, 0x0A4, 4, 0x86C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__SDMA_DEBUG_EVT_CHN_LINES_4        \
-                                                        IOMUX_PAD(0x3D0, 0x0A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT17__EMI_EMI_DEBUG_22          IOMUX_PAD(0x3D0, 0x0A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          IOMUX_PAD(0x3D4, 0x0A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__GPIO5_12                  IOMUX_PAD(0x3D4, 0x0A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__ECSPI2_SS0                IOMUX_PAD(0x3D4, 0x0A8, 2, 0x7C4, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD5_TXFS          IOMUX_PAD(0x3D4, 0x0A8, 3, 0x75C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__AUDMUX_AUD4_RXFS          IOMUX_PAD(0x3D4, 0x0A8, 4, 0x73C, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__SDMA_DEBUG_EVT_CHN_LINES_5        \
-                                                        IOMUX_PAD(0x3D4, 0x0A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_EMI_DEBUG_23          IOMUX_PAD(0x3D4, 0x0A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT18__EMI_WEIM_CS_2             IOMUX_PAD(0x3D4, 0x0A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          IOMUX_PAD(0x3D8, 0x0AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__GPIO5_13                  IOMUX_PAD(0x3D8, 0x0AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__ECSPI2_SCLK               IOMUX_PAD(0x3D8, 0x0AC, 2, 0x7B8, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD5_RXD           IOMUX_PAD(0x3D8, 0x0AC, 3, 0x748, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__AUDMUX_AUD4_RXC           IOMUX_PAD(0x3D8, 0x0AC, 4, 0x738, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__SDMA_DEBUG_EVT_CHN_LINES_6        \
-                                                        IOMUX_PAD(0x3D8, 0x0AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_EMI_DEBUG_24          IOMUX_PAD(0x3D8, 0x0AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT19__EMI_WEIM_CS_3             IOMUX_PAD(0x3D8, 0x0AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          IOMUX_PAD(0x3DC, 0x0B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__GPIO5_14                  IOMUX_PAD(0x3DC, 0x0B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__ECSPI1_SCLK               IOMUX_PAD(0x3DC, 0x0B0, 2, 0x79C, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__AUDMUX_AUD4_TXC           IOMUX_PAD(0x3DC, 0x0B0, 3, 0x740, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7        \
-                                                        IOMUX_PAD(0x3DC, 0x0B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__EMI_EMI_DEBUG_25          IOMUX_PAD(0x3DC, 0x0B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT20__SATA_PHY_TDI              IOMUX_PAD(0x3DC, 0x0B0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          IOMUX_PAD(0x3E0, 0x0B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__GPIO5_15                  IOMUX_PAD(0x3E0, 0x0B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__ECSPI1_MOSI               IOMUX_PAD(0x3E0, 0x0B4, 2, 0x7A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__AUDMUX_AUD4_TXD           IOMUX_PAD(0x3E0, 0x0B4, 3, 0x734, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0   IOMUX_PAD(0x3E0, 0x0B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__EMI_EMI_DEBUG_26          IOMUX_PAD(0x3E0, 0x0B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT21__SATA_PHY_TDO              IOMUX_PAD(0x3E0, 0x0B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          IOMUX_PAD(0x3E4, 0x0B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__GPIO5_16                  IOMUX_PAD(0x3E4, 0x0B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__ECSPI1_MISO               IOMUX_PAD(0x3E4, 0x0B8, 2, 0x7A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__AUDMUX_AUD4_TXFS          IOMUX_PAD(0x3E4, 0x0B8, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1   IOMUX_PAD(0x3E4, 0x0B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__EMI_EMI_DEBUG_27          IOMUX_PAD(0x3E4, 0x0B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT22__SATA_PHY_TCK              IOMUX_PAD(0x3E4, 0x0B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          IOMUX_PAD(0x3E8, 0x0BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__GPIO5_17                  IOMUX_PAD(0x3E8, 0x0BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__ECSPI1_SS0                IOMUX_PAD(0x3E8, 0x0BC, 2, 0x7A8, 1, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__AUDMUX_AUD4_RXD           IOMUX_PAD(0x3E8, 0x0BC, 3, 0x730, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2   IOMUX_PAD(0x3E8, 0x0BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__EMI_EMI_DEBUG_28          IOMUX_PAD(0x3E8, 0x0BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_DISP0_DAT23__SATA_PHY_TMS              IOMUX_PAD(0x3E8, 0x0BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK           IOMUX_PAD(0x3EC, 0x0C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__GPIO5_18                  IOMUX_PAD(0x3EC, 0x0C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__SDMA_DEBUG_PC_0           IOMUX_PAD(0x3EC, 0x0C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_PIXCLK__EMI_EMI_DEBUG_29          IOMUX_PAD(0x3EC, 0x0C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC              IOMUX_PAD(0x3F0, 0x0C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__GPIO5_19                    IOMUX_PAD(0x3F0, 0x0C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK               IOMUX_PAD(0x3F0, 0x0C4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__SDMA_DEBUG_PC_1             IOMUX_PAD(0x3F0, 0x0C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__EMI_EMI_DEBUG_30            IOMUX_PAD(0x3F0, 0x0C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_MCLK__TPIU_TRCTL                  IOMUX_PAD(0x3F0, 0x0C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN         IOMUX_PAD(0x3F4, 0x0C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__GPIO5_20                 IOMUX_PAD(0x3F4, 0x0C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__SDMA_DEBUG_PC_2          IOMUX_PAD(0x3F4, 0x0C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__EMI_EMI_DEBUG_31         IOMUX_PAD(0x3F4, 0x0C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DATA_EN__TPIU_TRCLK               IOMUX_PAD(0x3F4, 0x0C8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC             IOMUX_PAD(0x3F8, 0x0CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__GPIO5_21                   IOMUX_PAD(0x3F8, 0x0CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__SDMA_DEBUG_PC_3            IOMUX_PAD(0x3F8, 0x0CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__EMI_EMI_DEBUG_32           IOMUX_PAD(0x3F8, 0x0CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_VSYNC__TPIU_TRACE_0               IOMUX_PAD(0x3F8, 0x0CC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4                IOMUX_PAD(0x3FC, 0x0D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__GPIO5_22                    IOMUX_PAD(0x3FC, 0x0D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__KPP_COL_5                   IOMUX_PAD(0x3FC, 0x0D0, 2, 0x840, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__ECSPI1_SCLK                 IOMUX_PAD(0x3FC, 0x0D0, 3, 0x79C, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__USBOH3_USBH3_STP            IOMUX_PAD(0x3FC, 0x0D0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC             IOMUX_PAD(0x3FC, 0x0D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__EMI_EMI_DEBUG_33            IOMUX_PAD(0x3FC, 0x0D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT4__TPIU_TRACE_1                IOMUX_PAD(0x3FC, 0x0D0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5                IOMUX_PAD(0x400, 0x0D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__GPIO5_23                    IOMUX_PAD(0x400, 0x0D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__KPP_ROW_5                   IOMUX_PAD(0x400, 0x0D4, 2, 0x84C, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__ECSPI1_MOSI                 IOMUX_PAD(0x400, 0x0D4, 3, 0x7A4, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__USBOH3_USBH3_NXT            IOMUX_PAD(0x400, 0x0D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD             IOMUX_PAD(0x400, 0x0D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__EMI_EMI_DEBUG_34            IOMUX_PAD(0x400, 0x0D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT5__TPIU_TRACE_2                IOMUX_PAD(0x400, 0x0D4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6                IOMUX_PAD(0x404, 0x0D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__GPIO5_24                    IOMUX_PAD(0x404, 0x0D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__KPP_COL_6                   IOMUX_PAD(0x404, 0x0D8, 2, 0x844, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__ECSPI1_MISO                 IOMUX_PAD(0x404, 0x0D8, 3, 0x7A0, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__USBOH3_USBH3_CLK            IOMUX_PAD(0x404, 0x0D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS            IOMUX_PAD(0x404, 0x0D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__EMI_EMI_DEBUG_35            IOMUX_PAD(0x404, 0x0D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT6__TPIU_TRACE_3                IOMUX_PAD(0x404, 0x0D8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7                IOMUX_PAD(0x408, 0x0DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__GPIO5_25                    IOMUX_PAD(0x408, 0x0DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__KPP_ROW_6                   IOMUX_PAD(0x408, 0x0DC, 2, 0x850, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__ECSPI1_SS0                  IOMUX_PAD(0x408, 0x0DC, 3, 0x7A8, 2, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__USBOH3_USBH3_DIR            IOMUX_PAD(0x408, 0x0DC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD             IOMUX_PAD(0x408, 0x0DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__EMI_EMI_DEBUG_36            IOMUX_PAD(0x408, 0x0DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT7__TPIU_TRACE_4                IOMUX_PAD(0x408, 0x0DC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8                IOMUX_PAD(0x40C, 0x0E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__GPIO5_26                    IOMUX_PAD(0x40C, 0x0E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__KPP_COL_7                   IOMUX_PAD(0x40C, 0x0E0, 2, 0x848, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__ECSPI2_SCLK                 IOMUX_PAD(0x40C, 0x0E0, 3, 0x7B8, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__USBOH3_USBH3_OC             IOMUX_PAD(0x40C, 0x0E0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__I2C1_SDA                    IOMUX_PAD(0x40C, 0x0E0, 5 | IOMUX_CONFIG_SION, 0x818, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__EMI_EMI_DEBUG_37            IOMUX_PAD(0x40C, 0x0E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT8__TPIU_TRACE_5                IOMUX_PAD(0x40C, 0x0E0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9                IOMUX_PAD(0x410, 0x0E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__GPIO5_27                    IOMUX_PAD(0x410, 0x0E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__KPP_ROW_7                   IOMUX_PAD(0x410, 0x0E4, 2, 0x854, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__ECSPI2_MOSI                 IOMUX_PAD(0x410, 0x0E4, 3, 0x7C0, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__USBOH3_USBH3_PWR            IOMUX_PAD(0x410, 0x0E4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__I2C1_SCL                    IOMUX_PAD(0x410, 0x0E4, 5 | IOMUX_CONFIG_SION, 0x814, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__EMI_EMI_DEBUG_38            IOMUX_PAD(0x410, 0x0E4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT9__TPIU_TRACE_6                IOMUX_PAD(0x410, 0x0E4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10              IOMUX_PAD(0x414, 0x0E8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__GPIO5_28                   IOMUX_PAD(0x414, 0x0E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__UART1_TXD_MUX              IOMUX_PAD(0x414, 0x0E8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__ECSPI2_MISO                IOMUX_PAD(0x414, 0x0E8, 3, 0x7BC, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC            IOMUX_PAD(0x414, 0x0E8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4            IOMUX_PAD(0x414, 0x0E8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__EMI_EMI_DEBUG_39           IOMUX_PAD(0x414, 0x0E8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT10__TPIU_TRACE_7               IOMUX_PAD(0x414, 0x0E8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11              IOMUX_PAD(0x418, 0x0EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__GPIO5_29                   IOMUX_PAD(0x418, 0x0EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__UART1_RXD_MUX              IOMUX_PAD(0x418, 0x0EC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__ECSPI2_SS0                 IOMUX_PAD(0x418, 0x0EC, 3, 0x7C4, 1, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS           IOMUX_PAD(0x418, 0x0EC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5            IOMUX_PAD(0x418, 0x0EC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__EMI_EMI_DEBUG_40           IOMUX_PAD(0x418, 0x0EC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8               IOMUX_PAD(0x418, 0x0EC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12              IOMUX_PAD(0x41C, 0x0F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__GPIO5_30                   IOMUX_PAD(0x41C, 0x0F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX              IOMUX_PAD(0x41C, 0x0F0, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0        IOMUX_PAD(0x41C, 0x0F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6            IOMUX_PAD(0x41C, 0x0F0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41           IOMUX_PAD(0x41C, 0x0F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9               IOMUX_PAD(0x41C, 0x0F0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13              IOMUX_PAD(0x420, 0x0F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__GPIO5_31                   IOMUX_PAD(0x420, 0x0F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX              IOMUX_PAD(0x420, 0x0F4, 2, 0x890, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1        IOMUX_PAD(0x420, 0x0F4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7            IOMUX_PAD(0x420, 0x0F4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42           IOMUX_PAD(0x420, 0x0F4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10              IOMUX_PAD(0x420, 0x0F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14              IOMUX_PAD(0x424, 0x0F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__GPIO6_0                    IOMUX_PAD(0x424, 0x0F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX              IOMUX_PAD(0x424, 0x0F8, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2        IOMUX_PAD(0x424, 0x0F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8            IOMUX_PAD(0x424, 0x0F8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43           IOMUX_PAD(0x424, 0x0F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11              IOMUX_PAD(0x424, 0x0F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15              IOMUX_PAD(0x428, 0x0FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__GPIO6_1                    IOMUX_PAD(0x428, 0x0FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX              IOMUX_PAD(0x428, 0x0FC, 2, 0x898, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3        IOMUX_PAD(0x428, 0x0FC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9            IOMUX_PAD(0x428, 0x0FC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44           IOMUX_PAD(0x428, 0x0FC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12              IOMUX_PAD(0x428, 0x0FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16              IOMUX_PAD(0x42C, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__GPIO6_2                    IOMUX_PAD(0x42C, 0x100, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__UART4_RTS                  IOMUX_PAD(0x42C, 0x100, 2, 0x88C, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4        IOMUX_PAD(0x42C, 0x100, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10           IOMUX_PAD(0x42C, 0x100, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45           IOMUX_PAD(0x42C, 0x100, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13              IOMUX_PAD(0x42C, 0x100, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17              IOMUX_PAD(0x430, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__GPIO6_3                    IOMUX_PAD(0x430, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__UART4_CTS                  IOMUX_PAD(0x430, 0x104, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5        IOMUX_PAD(0x430, 0x104, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11           IOMUX_PAD(0x430, 0x104, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46           IOMUX_PAD(0x430, 0x104, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14              IOMUX_PAD(0x430, 0x104, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18              IOMUX_PAD(0x434, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__GPIO6_4                    IOMUX_PAD(0x434, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__UART5_RTS                  IOMUX_PAD(0x434, 0x108, 2, 0x894, 2, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6        IOMUX_PAD(0x434, 0x108, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12           IOMUX_PAD(0x434, 0x108, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47           IOMUX_PAD(0x434, 0x108, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15              IOMUX_PAD(0x434, 0x108, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19              IOMUX_PAD(0x438, 0x10C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__GPIO6_5                    IOMUX_PAD(0x438, 0x10C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__UART5_CTS                  IOMUX_PAD(0x438, 0x10C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7        IOMUX_PAD(0x438, 0x10C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13           IOMUX_PAD(0x438, 0x10C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48           IOMUX_PAD(0x438, 0x10C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_CSI0_DAT19__USBPHY2_BISTOK             IOMUX_PAD(0x438, 0x10C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__EMI_WEIM_A_25                 IOMUX_PAD(0x458, 0x110, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__GPIO5_2                       IOMUX_PAD(0x458, 0x110, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__ECSPI2_RDY                    IOMUX_PAD(0x458, 0x110, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI1_PIN12                 IOMUX_PAD(0x458, 0x110, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__CSPI_SS1                      IOMUX_PAD(0x458, 0x110, 4, 0x790, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__IPU_DI0_D1_CS                 IOMUX_PAD(0x458, 0x110, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A25__USBPHY1_BISTOK                IOMUX_PAD(0x458, 0x110, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__EMI_WEIM_EB_2                 IOMUX_PAD(0x45C, 0x114, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__GPIO2_30                      IOMUX_PAD(0x45C, 0x114, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__CCM_DI1_EXT_CLK               IOMUX_PAD(0x45C, 0x114, 2, 0x76C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__IPU_SER_DISP1_CS              IOMUX_PAD(0x45C, 0x114, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__ECSPI1_SS0                    IOMUX_PAD(0x45C, 0x114, 4, 0x7A8, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB2__I2C2_SCL                      IOMUX_PAD(0x45C, 0x114, 5 | IOMUX_CONFIG_SION, 0x81C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__EMI_WEIM_D_16                 IOMUX_PAD(0x460, 0x118, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__GPIO3_16                      IOMUX_PAD(0x460, 0x118, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DI0_PIN5                  IOMUX_PAD(0x460, 0x118, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK            IOMUX_PAD(0x460, 0x118, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__ECSPI1_SCLK                   IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D16__I2C2_SDA                      IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__EMI_WEIM_D_17                 IOMUX_PAD(0x464, 0x11C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__GPIO3_17                      IOMUX_PAD(0x464, 0x11C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DI0_PIN6                  IOMUX_PAD(0x464, 0x11C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN            IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__ECSPI1_MISO                   IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D17__I2C3_SCL                      IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__EMI_WEIM_D_18                 IOMUX_PAD(0x468, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__GPIO3_18                      IOMUX_PAD(0x468, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI0_PIN7                  IOMUX_PAD(0x468, 0x120, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO            IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__ECSPI1_MOSI                   IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__I2C3_SDA                      IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D18__IPU_DI1_D0_CS                 IOMUX_PAD(0x468, 0x120, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EMI_WEIM_D_19                 IOMUX_PAD(0x46C, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__GPIO3_19                      IOMUX_PAD(0x46C, 0x124, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DI0_PIN8                  IOMUX_PAD(0x46C, 0x124, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS             IOMUX_PAD(0x46C, 0x124, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__ECSPI1_SS1                    IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__EPIT1_EPITO                   IOMUX_PAD(0x46C, 0x124, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D19__UART1_CTS                     IOMUX_PAD(0x46C, 0x124, 6, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC               IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EMI_WEIM_D_20                 IOMUX_PAD(0x470, 0x128, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__GPIO3_20                      IOMUX_PAD(0x470, 0x128, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_DI0_PIN16                 IOMUX_PAD(0x470, 0x128, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS              IOMUX_PAD(0x470, 0x128, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__CSPI_SS0                      IOMUX_PAD(0x470, 0x128, 4, 0x78C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__EPIT2_EPITO                   IOMUX_PAD(0x470, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D20__UART1_RTS                     IOMUX_PAD(0x470, 0x128, 6, 0x874, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR              IOMUX_PAD(0x470, 0x128, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__EMI_WEIM_D_21                 IOMUX_PAD(0x474, 0x12C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__GPIO3_21                      IOMUX_PAD(0x474, 0x12C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DI0_PIN17                 IOMUX_PAD(0x474, 0x12C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK            IOMUX_PAD(0x474, 0x12C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__CSPI_SCLK                     IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__I2C1_SCL                      IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D21__USBOH3_USBOTG_OC              IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__EMI_WEIM_D_22                 IOMUX_PAD(0x478, 0x130, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__GPIO3_22                      IOMUX_PAD(0x478, 0x130, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DI0_PIN1                  IOMUX_PAD(0x478, 0x130, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN            IOMUX_PAD(0x478, 0x130, 3, 0x82C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__CSPI_MISO                     IOMUX_PAD(0x478, 0x130, 4, 0x784, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR             IOMUX_PAD(0x478, 0x130, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__EMI_WEIM_D_23                 IOMUX_PAD(0x47C, 0x134, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__GPIO3_23                      IOMUX_PAD(0x47C, 0x134, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART3_CTS                     IOMUX_PAD(0x47C, 0x134, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D23__UART1_DCD                     IOMUX_PAD(0x47C, 0x134, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS                 IOMUX_PAD(0x47C, 0x134, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN2                  IOMUX_PAD(0x47C, 0x134, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_CSI1_DATA_EN              IOMUX_PAD(0x47C, 0x134, 6, 0x834, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D23__IPU_DI1_PIN14                 IOMUX_PAD(0x47C, 0x134, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3                 IOMUX_PAD(0x480, 0x138, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__GPIO2_31                      IOMUX_PAD(0x480, 0x138, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART3_RTS                     IOMUX_PAD(0x480, 0x138, 2, 0x884, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__UART1_RI                      IOMUX_PAD(0x480, 0x138, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3                  IOMUX_PAD(0x480, 0x138, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC                IOMUX_PAD(0x480, 0x138, 6, 0x838, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16                 IOMUX_PAD(0x480, 0x138, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__EMI_WEIM_D_24                 IOMUX_PAD(0x484, 0x13C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__GPIO3_24                      IOMUX_PAD(0x484, 0x13C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX                 IOMUX_PAD(0x484, 0x13C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI1_SS2                    IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__CSPI_SS2                      IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS              IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__ECSPI2_SS2                    IOMUX_PAD(0x484, 0x13C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D24__UART1_DTR                     IOMUX_PAD(0x484, 0x13C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__EMI_WEIM_D_25                 IOMUX_PAD(0x488, 0x140, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__GPIO3_25                      IOMUX_PAD(0x488, 0x140, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX                 IOMUX_PAD(0x488, 0x140, 2, 0x888, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI1_SS3                    IOMUX_PAD(0x488, 0x140, 3, 0x7B4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__CSPI_SS3                      IOMUX_PAD(0x488, 0x140, 4, 0x798, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC               IOMUX_PAD(0x488, 0x140, 5, 0x750, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__ECSPI2_SS3                    IOMUX_PAD(0x488, 0x140, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D25__UART1_DSR                     IOMUX_PAD(0x488, 0x140, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__EMI_WEIM_D_26                 IOMUX_PAD(0x48C, 0x144, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__GPIO3_26                      IOMUX_PAD(0x48C, 0x144, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX                 IOMUX_PAD(0x48C, 0x144, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D26__FIRI_RXD                      IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_CSI0_D_1                  IOMUX_PAD(0x48C, 0x144, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DI1_PIN11                 IOMUX_PAD(0x48C, 0x144, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_SISG_2                    IOMUX_PAD(0x48C, 0x144, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22              IOMUX_PAD(0x48C, 0x144, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__EMI_WEIM_D_27                 IOMUX_PAD(0x490, 0x148, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__GPIO3_27                      IOMUX_PAD(0x490, 0x148, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX                 IOMUX_PAD(0x490, 0x148, 2, 0x880, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D27__FIRI_TXD                      IOMUX_PAD(0x490, 0x148, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_CSI0_D_0                  IOMUX_PAD(0x490, 0x148, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DI1_PIN13                 IOMUX_PAD(0x490, 0x148, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_SISG_3                    IOMUX_PAD(0x490, 0x148, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23              IOMUX_PAD(0x490, 0x148, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__EMI_WEIM_D_28                 IOMUX_PAD(0x494, 0x14C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__GPIO3_28                      IOMUX_PAD(0x494, 0x14C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__UART2_CTS                     IOMUX_PAD(0x494, 0x14C, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO            IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__CSPI_MOSI                     IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__I2C1_SDA                      IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_EXT_TRIG                  IOMUX_PAD(0x494, 0x14C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D28__IPU_DI0_PIN13                 IOMUX_PAD(0x494, 0x14C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__EMI_WEIM_D_29                 IOMUX_PAD(0x498, 0x150, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__GPIO3_29                      IOMUX_PAD(0x498, 0x150, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__UART2_RTS                     IOMUX_PAD(0x498, 0x150, 2, 0x87C, 1, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS             IOMUX_PAD(0x498, 0x150, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__CSPI_SS0                      IOMUX_PAD(0x498, 0x150, 4, 0x78C, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI1_PIN15                 IOMUX_PAD(0x498, 0x150, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_CSI1_VSYNC                IOMUX_PAD(0x498, 0x150, 6, 0x83C, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D29__IPU_DI0_PIN14                 IOMUX_PAD(0x498, 0x150, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__EMI_WEIM_D_30                 IOMUX_PAD(0x49C, 0x154, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__GPIO3_30                      IOMUX_PAD(0x49C, 0x154, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__UART3_CTS                     IOMUX_PAD(0x49C, 0x154, 2, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_CSI0_D_3                  IOMUX_PAD(0x49C, 0x154, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DI0_PIN11                 IOMUX_PAD(0x49C, 0x154, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21              IOMUX_PAD(0x49C, 0x154, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH1_OC               IOMUX_PAD(0x49C, 0x154, 6, 0x8A0, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC               IOMUX_PAD(0x49C, 0x154, 7, 0x8A4, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__EMI_WEIM_D_31                 IOMUX_PAD(0x4A0, 0x158, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__GPIO3_31                      IOMUX_PAD(0x4A0, 0x158, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__UART3_RTS                     IOMUX_PAD(0x4A0, 0x158, 2, 0x884, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_CSI0_D_2                  IOMUX_PAD(0x4A0, 0x158, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DI0_PIN12                 IOMUX_PAD(0x4A0, 0x158, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20              IOMUX_PAD(0x4A0, 0x158, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH1_PWR              IOMUX_PAD(0x4A0, 0x158, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_D31__USBOH3_USBH2_PWR              IOMUX_PAD(0x4A0, 0x158, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__EMI_WEIM_A_24                 IOMUX_PAD(0x4A8, 0x15C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__GPIO5_4                       IOMUX_PAD(0x4A8, 0x15C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_DISP1_DAT_19              IOMUX_PAD(0x4A8, 0x15C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_CSI1_D_19                 IOMUX_PAD(0x4A8, 0x15C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__IPU_SISG_2                    IOMUX_PAD(0x4A8, 0x15C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A24__USBPHY2_BVALID                IOMUX_PAD(0x4A8, 0x15C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__EMI_WEIM_A_23                 IOMUX_PAD(0x4AC, 0x160, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__GPIO6_6                       IOMUX_PAD(0x4AC, 0x160, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_DISP1_DAT_18              IOMUX_PAD(0x4AC, 0x160, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_CSI1_D_18                 IOMUX_PAD(0x4AC, 0x160, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__IPU_SISG_3                    IOMUX_PAD(0x4AC, 0x160, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A23__USBPHY2_ENDSESSION            IOMUX_PAD(0x4AC, 0x160, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__EMI_WEIM_A_22                 IOMUX_PAD(0x4B0, 0x164, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__GPIO2_16                      IOMUX_PAD(0x4B0, 0x164, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_DISP1_DAT_17              IOMUX_PAD(0x4B0, 0x164, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__IPU_CSI1_D_17                 IOMUX_PAD(0x4B0, 0x164, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A22__SRC_BT_CFG1_7                 IOMUX_PAD(0x4B0, 0x164, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__EMI_WEIM_A_21                 IOMUX_PAD(0x4B4, 0x168, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__GPIO2_17                      IOMUX_PAD(0x4B4, 0x168, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_DISP1_DAT_16              IOMUX_PAD(0x4B4, 0x168, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__IPU_CSI1_D_16                 IOMUX_PAD(0x4B4, 0x168, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A21__SRC_BT_CFG1_6                 IOMUX_PAD(0x4B4, 0x168, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__EMI_WEIM_A_20                 IOMUX_PAD(0x4B8, 0x16C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__GPIO2_18                      IOMUX_PAD(0x4B8, 0x16C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_DISP1_DAT_15              IOMUX_PAD(0x4B8, 0x16C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__IPU_CSI1_D_15                 IOMUX_PAD(0x4B8, 0x16C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A20__SRC_BT_CFG1_5                 IOMUX_PAD(0x4B8, 0x16C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__EMI_WEIM_A_19                 IOMUX_PAD(0x4BC, 0x170, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__GPIO2_19                      IOMUX_PAD(0x4BC, 0x170, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_DISP1_DAT_14              IOMUX_PAD(0x4BC, 0x170, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__IPU_CSI1_D_14                 IOMUX_PAD(0x4BC, 0x170, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A19__SRC_BT_CFG1_4                 IOMUX_PAD(0x4BC, 0x170, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__EMI_WEIM_A_18                 IOMUX_PAD(0x4C0, 0x174, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__GPIO2_20                      IOMUX_PAD(0x4C0, 0x174, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_DISP1_DAT_13              IOMUX_PAD(0x4C0, 0x174, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__IPU_CSI1_D_13                 IOMUX_PAD(0x4C0, 0x174, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A18__SRC_BT_CFG1_3                 IOMUX_PAD(0x4C0, 0x174, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__EMI_WEIM_A_17                 IOMUX_PAD(0x4C4, 0x178, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__GPIO2_21                      IOMUX_PAD(0x4C4, 0x178, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_DISP1_DAT_12              IOMUX_PAD(0x4C4, 0x178, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__IPU_CSI1_D_12                 IOMUX_PAD(0x4C4, 0x178, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A17__SRC_BT_CFG1_2                 IOMUX_PAD(0x4C4, 0x178, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__EMI_WEIM_A_16                 IOMUX_PAD(0x4C8, 0x17C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__GPIO2_22                      IOMUX_PAD(0x4C8, 0x17C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK              IOMUX_PAD(0x4C8, 0x17C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__IPU_CSI1_PIXCLK               IOMUX_PAD(0x4C8, 0x17C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_A16__SRC_BT_CFG1_1                 IOMUX_PAD(0x4C8, 0x17C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__EMI_WEIM_CS_0                 IOMUX_PAD(0x4CC, 0x180, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__GPIO2_23                      IOMUX_PAD(0x4CC, 0x180, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__ECSPI2_SCLK                   IOMUX_PAD(0x4CC, 0x180, 2, 0x7B8, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS0__IPU_DI1_PIN5                  IOMUX_PAD(0x4CC, 0x180, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__EMI_WEIM_CS_1                 IOMUX_PAD(0x4D0, 0x184, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__GPIO2_24                      IOMUX_PAD(0x4D0, 0x184, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__ECSPI2_MOSI                   IOMUX_PAD(0x4D0, 0x184, 2, 0x7C0, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_CS1__IPU_DI1_PIN6                  IOMUX_PAD(0x4D0, 0x184, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__EMI_WEIM_OE                    IOMUX_PAD(0x4D4, 0x188, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__GPIO2_25                       IOMUX_PAD(0x4D4, 0x188, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__ECSPI2_MISO                    IOMUX_PAD(0x4D4, 0x188, 2, 0x7BC, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__IPU_DI1_PIN7                   IOMUX_PAD(0x4D4, 0x188, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_OE__USBPHY2_IDDIG                  IOMUX_PAD(0x4D4, 0x188, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__EMI_WEIM_RW                    IOMUX_PAD(0x4D8, 0x18C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__GPIO2_26                       IOMUX_PAD(0x4D8, 0x18C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__ECSPI2_SS0                     IOMUX_PAD(0x4D8, 0x18C, 2, 0x7C4, 2, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__IPU_DI1_PIN8                   IOMUX_PAD(0x4D8, 0x18C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_RW__USBPHY2_HOSTDISCONNECT         IOMUX_PAD(0x4D8, 0x18C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__EMI_WEIM_LBA                  IOMUX_PAD(0x4DC, 0x190, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__GPIO2_27                      IOMUX_PAD(0x4DC, 0x190, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__ECSPI2_SS1                    IOMUX_PAD(0x4DC, 0x190, 2, 0x7C8, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__IPU_DI1_PIN17                 IOMUX_PAD(0x4DC, 0x190, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_LBA__SRC_BT_CFG1_0                 IOMUX_PAD(0x4DC, 0x190, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__EMI_WEIM_EB_0                 IOMUX_PAD(0x4E4, 0x194, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPIO2_28                      IOMUX_PAD(0x4E4, 0x194, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11              IOMUX_PAD(0x4E4, 0x194, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__IPU_CSI1_D_11                 IOMUX_PAD(0x4E4, 0x194, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__GPC_PMIC_RDY                  IOMUX_PAD(0x4E4, 0x194, 5, 0x810, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB0__SRC_BT_CFG2_7                 IOMUX_PAD(0x4E4, 0x194, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__EMI_WEIM_EB_1                 IOMUX_PAD(0x4E8, 0x198, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__GPIO2_29                      IOMUX_PAD(0x4E8, 0x198, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10              IOMUX_PAD(0x4E8, 0x198, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__IPU_CSI1_D_10                 IOMUX_PAD(0x4E8, 0x198, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_EB1__SRC_BT_CFG2_6                 IOMUX_PAD(0x4E8, 0x198, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0            IOMUX_PAD(0x4EC, 0x19C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__GPIO3_0                       IOMUX_PAD(0x4EC, 0x19C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9               IOMUX_PAD(0x4EC, 0x19C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__IPU_CSI1_D_9                  IOMUX_PAD(0x4EC, 0x19C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA0__SRC_BT_CFG2_5                 IOMUX_PAD(0x4EC, 0x19C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1            IOMUX_PAD(0x4F0, 0x1A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__GPIO3_1                       IOMUX_PAD(0x4F0, 0x1A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8               IOMUX_PAD(0x4F0, 0x1A0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__IPU_CSI1_D_8                  IOMUX_PAD(0x4F0, 0x1A0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA1__SRC_BT_CFG2_4                 IOMUX_PAD(0x4F0, 0x1A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2            IOMUX_PAD(0x4F4, 0x1A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__GPIO3_2                       IOMUX_PAD(0x4F4, 0x1A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7               IOMUX_PAD(0x4F4, 0x1A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__IPU_CSI1_D_7                  IOMUX_PAD(0x4F4, 0x1A4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA2__SRC_BT_CFG2_3                 IOMUX_PAD(0x4F4, 0x1A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3            IOMUX_PAD(0x4F8, 0x1A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__GPIO3_3                       IOMUX_PAD(0x4F8, 0x1A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6               IOMUX_PAD(0x4F8, 0x1A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__IPU_CSI1_D_6                  IOMUX_PAD(0x4F8, 0x1A8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA3__SRC_BT_CFG2_2                 IOMUX_PAD(0x4F8, 0x1A8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4            IOMUX_PAD(0x4FC, 0x1AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__GPIO3_4                       IOMUX_PAD(0x4FC, 0x1AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5               IOMUX_PAD(0x4FC, 0x1AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__IPU_CSI1_D_5                  IOMUX_PAD(0x4FC, 0x1AC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA4__SRC_BT_CFG3_7                 IOMUX_PAD(0x4FC, 0x1AC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5            IOMUX_PAD(0x500, 0x1B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__GPIO3_5                       IOMUX_PAD(0x500, 0x1B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4               IOMUX_PAD(0x500, 0x1B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__IPU_CSI1_D_4                  IOMUX_PAD(0x500, 0x1B0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA5__SRC_BT_CFG3_6                 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6            IOMUX_PAD(0x504, 0x1B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__GPIO3_6                       IOMUX_PAD(0x504, 0x1B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3               IOMUX_PAD(0x504, 0x1B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__IPU_CSI1_D_3                  IOMUX_PAD(0x504, 0x1B4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA6__SRC_BT_CFG3_5                 IOMUX_PAD(0x504, 0x1B4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7            IOMUX_PAD(0x508, 0x1B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__GPIO3_7                       IOMUX_PAD(0x508, 0x1B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2               IOMUX_PAD(0x508, 0x1B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__IPU_CSI1_D_2                  IOMUX_PAD(0x508, 0x1B8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA7__SRC_BT_CFG3_4                 IOMUX_PAD(0x508, 0x1B8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8            IOMUX_PAD(0x50C, 0x1BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__GPIO3_8                       IOMUX_PAD(0x50C, 0x1BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1               IOMUX_PAD(0x50C, 0x1BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__IPU_CSI1_D_1                  IOMUX_PAD(0x50C, 0x1BC, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA8__SRC_BT_CFG3_3                 IOMUX_PAD(0x50C, 0x1BC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9            IOMUX_PAD(0x510, 0x1C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__GPIO3_9                       IOMUX_PAD(0x510, 0x1C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0               IOMUX_PAD(0x510, 0x1C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__IPU_CSI1_D_0                  IOMUX_PAD(0x510, 0x1C0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA9__SRC_BT_CFG3_2                 IOMUX_PAD(0x510, 0x1C0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10          IOMUX_PAD(0x514, 0x1C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__GPIO3_10                     IOMUX_PAD(0x514, 0x1C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_DI1_PIN15                IOMUX_PAD(0x514, 0x1C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__IPU_CSI1_DATA_EN             IOMUX_PAD(0x514, 0x1C4, 4, 0x834, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA10__SRC_BT_CFG3_1                IOMUX_PAD(0x514, 0x1C4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11          IOMUX_PAD(0x518, 0x1C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__GPIO3_11                     IOMUX_PAD(0x518, 0x1C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_DI1_PIN2                 IOMUX_PAD(0x518, 0x1C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA11__IPU_CSI1_HSYNC               IOMUX_PAD(0x518, 0x1C8, 4, 0x838, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12          IOMUX_PAD(0x51C, 0x1CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__GPIO3_12                     IOMUX_PAD(0x51C, 0x1CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_DI1_PIN3                 IOMUX_PAD(0x51C, 0x1CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA12__IPU_CSI1_VSYNC               IOMUX_PAD(0x51C, 0x1CC, 4, 0x83C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13          IOMUX_PAD(0x520, 0x1D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__GPIO3_13                     IOMUX_PAD(0x520, 0x1D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__IPU_DI1_D0_CS                IOMUX_PAD(0x520, 0x1D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA13__CCM_DI1_EXT_CLK              IOMUX_PAD(0x520, 0x1D0, 4, 0x76C, 1, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14          IOMUX_PAD(0x524, 0x1D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__GPIO3_14                     IOMUX_PAD(0x524, 0x1D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__IPU_DI1_D1_CS                IOMUX_PAD(0x524, 0x1D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA14__CCM_DI0_EXT_CLK              IOMUX_PAD(0x524, 0x1D4, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15          IOMUX_PAD(0x528, 0x1D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__GPIO3_15                     IOMUX_PAD(0x528, 0x1D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN1                 IOMUX_PAD(0x528, 0x1D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_DA15__IPU_DI1_PIN4                 IOMUX_PAD(0x528, 0x1D8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B             IOMUX_PAD(0x52C, 0x1DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WE_B__GPIO6_12                   IOMUX_PAD(0x52C, 0x1DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B             IOMUX_PAD(0x530, 0x1E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RE_B__GPIO6_13                   IOMUX_PAD(0x530, 0x1E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT                IOMUX_PAD(0x534, 0x1E4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__GPIO5_0                      IOMUX_PAD(0x534, 0x1E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_EIM_WAIT__EMI_WEIM_DTACK_B             IOMUX_PAD(0x534, 0x1E4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__GPIO6_22                  IOMUX_PAD(__NA_, 0x1EC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3             IOMUX_PAD(__NA_, 0x1EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__GPIO6_24                  IOMUX_PAD(__NA_, 0x1F0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2             IOMUX_PAD(__NA_, 0x1F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__GPIO6_26                  IOMUX_PAD(__NA_, 0x1F4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK             IOMUX_PAD(__NA_, 0x1F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__GPIO6_28                  IOMUX_PAD(__NA_, 0x1F8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1             IOMUX_PAD(__NA_, 0x1F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__GPIO6_30                  IOMUX_PAD(__NA_, 0x1FC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0             IOMUX_PAD(__NA_, 0x1FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__GPIO7_22                  IOMUX_PAD(__NA_, 0x200, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3             IOMUX_PAD(__NA_, 0x200, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__GPIO7_24                  IOMUX_PAD(__NA_, 0x204, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK             IOMUX_PAD(__NA_, 0x204, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__GPIO7_26                  IOMUX_PAD(__NA_, 0x208, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2             IOMUX_PAD(__NA_, 0x208, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__GPIO7_28                  IOMUX_PAD(__NA_, 0x20C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1             IOMUX_PAD(__NA_, 0x20C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__GPIO7_30                  IOMUX_PAD(__NA_, 0x210, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0             IOMUX_PAD(__NA_, 0x210, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__GPIO4_0                       IOMUX_PAD(0x540, 0x214, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_10__OSC32k_32K_OUT                IOMUX_PAD(0x540, 0x214, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_11__GPIO4_1                       IOMUX_PAD(0x544, 0x218, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_12__GPIO4_2                       IOMUX_PAD(0x548, 0x21C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_13__GPIO4_3                       IOMUX_PAD(0x54C, 0x220, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_14__GPIO4_4                       IOMUX_PAD(0x550, 0x224, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__EMI_NANDF_CLE               IOMUX_PAD(0x5A0, 0x228, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__GPIO6_7                     IOMUX_PAD(0x5A0, 0x228, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CLE__USBPHY1_VSTATUS_0           IOMUX_PAD(0x5A0, 0x228, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__EMI_NANDF_ALE               IOMUX_PAD(0x5A4, 0x22C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__GPIO6_8                     IOMUX_PAD(0x5A4, 0x22C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_ALE__USBPHY1_VSTATUS_1           IOMUX_PAD(0x5A4, 0x22C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B             IOMUX_PAD(0x5A8, 0x230, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__GPIO6_9                    IOMUX_PAD(0x5A8, 0x230, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_WP_B__USBPHY1_VSTATUS_2          IOMUX_PAD(0x5A8, 0x230, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0              IOMUX_PAD(0x5AC, 0x234, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__GPIO6_10                    IOMUX_PAD(0x5AC, 0x234, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_RB0__USBPHY1_VSTATUS_3           IOMUX_PAD(0x5AC, 0x234, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0              IOMUX_PAD(0x5B0, 0x238, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__GPIO6_11                    IOMUX_PAD(0x5B0, 0x238, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS0__USBPHY1_VSTATUS_4           IOMUX_PAD(0x5B0, 0x238, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1              IOMUX_PAD(0x5B4, 0x23C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__GPIO6_14                    IOMUX_PAD(0x5B4, 0x23C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__MLB_MLBCLK                  IOMUX_PAD(0x5B4, 0x23C, 6, 0x858, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS1__USBPHY1_VSTATUS_5           IOMUX_PAD(0x5B4, 0x23C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2              IOMUX_PAD(0x5B8, 0x240, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__GPIO6_15                    IOMUX_PAD(0x5B8, 0x240, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__IPU_SISG_0                  IOMUX_PAD(0x5B8, 0x240, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__ESAI1_TX0                   IOMUX_PAD(0x5B8, 0x240, 3, 0x7E4, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__EMI_WEIM_CRE                IOMUX_PAD(0x5B8, 0x240, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__CCM_CSI0_MCLK               IOMUX_PAD(0x5B8, 0x240, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__MLB_MLBSIG                  IOMUX_PAD(0x5B8, 0x240, 6, 0x860, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS2__USBPHY1_VSTATUS_6           IOMUX_PAD(0x5B8, 0x240, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3              IOMUX_PAD(0x5BC, 0x244, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__GPIO6_16                    IOMUX_PAD(0x5BC, 0x244, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__IPU_SISG_1                  IOMUX_PAD(0x5BC, 0x244, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__ESAI1_TX1                   IOMUX_PAD(0x5BC, 0x244, 3, 0x7E8, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__EMI_WEIM_A_26               IOMUX_PAD(0x5BC, 0x244, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__MLB_MLBDAT                  IOMUX_PAD(0x5BC, 0x244, 6, 0x85C, 0, NO_PAD_CTRL)
-#define MX53_PAD_NANDF_CS3__USBPHY1_VSTATUS_7           IOMUX_PAD(0x5BC, 0x244, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_MDIO                     IOMUX_PAD(0x5C4, 0x248, 0, 0x804, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__GPIO1_22                     IOMUX_PAD(0x5C4, 0x248, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__ESAI1_SCKR                   IOMUX_PAD(0x5C4, 0x248, 2, 0x7DC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__FEC_COL                      IOMUX_PAD(0x5C4, 0x248, 3, 0x800, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__RTC_CE_RTC_PS2               IOMUX_PAD(0x5C4, 0x248, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__SDMA_DEBUG_BUS_DEVICE_3      IOMUX_PAD(0x5C4, 0x248, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDIO__EMI_EMI_DEBUG_49             IOMUX_PAD(0x5C4, 0x248, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__FEC_TX_CLK                IOMUX_PAD(0x5C8, 0x24C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__GPIO1_23                  IOMUX_PAD(0x5C8, 0x24C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__ESAI1_FSR                 IOMUX_PAD(0x5C8, 0x24C, 2, 0x7CC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__SDMA_DEBUG_BUS_DEVICE_4   IOMUX_PAD(0x5C8, 0x24C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_REF_CLK__EMI_EMI_DEBUG_50          IOMUX_PAD(0x5C8, 0x24C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_ER                   IOMUX_PAD(0x5CC, 0x250, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__GPIO1_24                    IOMUX_PAD(0x5CC, 0x250, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__ESAI1_HCKR                  IOMUX_PAD(0x5CC, 0x250, 2, 0x7D4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__FEC_RX_CLK                  IOMUX_PAD(0x5CC, 0x250, 3, 0x808, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RX_ER__RTC_CE_RTC_PS3              IOMUX_PAD(0x5CC, 0x250, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__FEC_RX_DV                  IOMUX_PAD(0x5D0, 0x254, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__GPIO1_25                   IOMUX_PAD(0x5D0, 0x254, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_CRS_DV__ESAI1_SCKT                 IOMUX_PAD(0x5D0, 0x254, 2, 0x7E0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__FEC_RDATA_1                  IOMUX_PAD(0x5D4, 0x258, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__GPIO1_26                     IOMUX_PAD(0x5D4, 0x258, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__ESAI1_FST                    IOMUX_PAD(0x5D4, 0x258, 2, 0x7D0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__MLB_MLBSIG                   IOMUX_PAD(0x5D4, 0x258, 3, 0x860, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD1__RTC_CE_RTC_PS1               IOMUX_PAD(0x5D4, 0x258, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__FEC_RDATA_0                  IOMUX_PAD(0x5D8, 0x25C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__GPIO1_27                     IOMUX_PAD(0x5D8, 0x25C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__ESAI1_HCKT                   IOMUX_PAD(0x5D8, 0x25C, 2, 0x7D8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_RXD0__OSC32k_32K_OUT               IOMUX_PAD(0x5D8, 0x25C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__FEC_TX_EN                   IOMUX_PAD(0x5DC, 0x260, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__GPIO1_28                    IOMUX_PAD(0x5DC, 0x260, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TX_EN__ESAI1_TX3_RX2               IOMUX_PAD(0x5DC, 0x260, 2, 0x7F0, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__FEC_TDATA_1                  IOMUX_PAD(0x5E0, 0x264, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__GPIO1_29                     IOMUX_PAD(0x5E0, 0x264, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__ESAI1_TX2_RX3                IOMUX_PAD(0x5E0, 0x264, 2, 0x7EC, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__MLB_MLBCLK                   IOMUX_PAD(0x5E0, 0x264, 3, 0x858, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD1__RTC_CE_RTC_PRSC_CLK          IOMUX_PAD(0x5E0, 0x264, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__FEC_TDATA_0                  IOMUX_PAD(0x5E4, 0x268, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__GPIO1_30                     IOMUX_PAD(0x5E4, 0x268, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__ESAI1_TX4_RX1                IOMUX_PAD(0x5E4, 0x268, 2, 0x7F4, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_TXD0__USBPHY2_DATAOUT_0            IOMUX_PAD(0x5E4, 0x268, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__FEC_MDC                       IOMUX_PAD(0x5E8, 0x26C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__GPIO1_31                      IOMUX_PAD(0x5E8, 0x26C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__ESAI1_TX5_RX0                 IOMUX_PAD(0x5E8, 0x26C, 2, 0x7F8, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__MLB_MLBDAT                    IOMUX_PAD(0x5E8, 0x26C, 3, 0x85C, 1, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__RTC_CE_RTC_ALARM1_TRIG        IOMUX_PAD(0x5E8, 0x26C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1             IOMUX_PAD(0x5E8, 0x26C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__PATA_DIOW                   IOMUX_PAD(0x5F0, 0x270, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__GPIO6_17                    IOMUX_PAD(0x5F0, 0x270, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__UART1_TXD_MUX               IOMUX_PAD(0x5F0, 0x270, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2           IOMUX_PAD(0x5F0, 0x270, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__PATA_DMACK                 IOMUX_PAD(0x5F4, 0x274, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__GPIO6_18                   IOMUX_PAD(0x5F4, 0x274, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__UART1_RXD_MUX              IOMUX_PAD(0x5F4, 0x274, 3, 0x878, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3          IOMUX_PAD(0x5F4, 0x274, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__PATA_DMARQ                 IOMUX_PAD(0x5F8, 0x278, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__GPIO7_0                    IOMUX_PAD(0x5F8, 0x278, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__UART2_TXD_MUX              IOMUX_PAD(0x5F8, 0x278, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0              IOMUX_PAD(0x5F8, 0x278, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4          IOMUX_PAD(0x5F8, 0x278, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN         IOMUX_PAD(0x5FC, 0x27C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__GPIO7_1                IOMUX_PAD(0x5FC, 0x27C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX          IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__CCM_CCM_OUT_1          IOMUX_PAD(0x5FC, 0x27C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5      IOMUX_PAD(0x5FC, 0x27C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__PATA_INTRQ                 IOMUX_PAD(0x600, 0x280, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__GPIO7_2                    IOMUX_PAD(0x600, 0x280, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__UART2_CTS                  IOMUX_PAD(0x600, 0x280, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CAN1_TXCAN                 IOMUX_PAD(0x600, 0x280, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2              IOMUX_PAD(0x600, 0x280, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6          IOMUX_PAD(0x600, 0x280, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__PATA_DIOR                   IOMUX_PAD(0x604, 0x284, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__GPIO7_3                     IOMUX_PAD(0x604, 0x284, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__UART2_RTS                   IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__CAN1_RXCAN                  IOMUX_PAD(0x604, 0x284, 4, 0x760, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DIOR__USBPHY2_DATAOUT_7           IOMUX_PAD(0x604, 0x284, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B        IOMUX_PAD(0x608, 0x288, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__GPIO7_4                  IOMUX_PAD(0x608, 0x288, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD               IOMUX_PAD(0x608, 0x288, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__UART1_CTS                IOMUX_PAD(0x608, 0x288, 3, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN               IOMUX_PAD(0x608, 0x288, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0        IOMUX_PAD(0x608, 0x288, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__PATA_IORDY                 IOMUX_PAD(0x60C, 0x28C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__GPIO7_5                    IOMUX_PAD(0x60C, 0x28C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__ESDHC3_CLK                 IOMUX_PAD(0x60C, 0x28C, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__UART1_RTS                  IOMUX_PAD(0x60C, 0x28C, 3, 0x874, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__CAN2_RXCAN                 IOMUX_PAD(0x60C, 0x28C, 4, 0x764, 1, NO_PAD_CTRL)
-#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1          IOMUX_PAD(0x60C, 0x28C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__PATA_DA_0                   IOMUX_PAD(0x610, 0x290, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__GPIO7_6                     IOMUX_PAD(0x610, 0x290, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__ESDHC3_RST                  IOMUX_PAD(0x610, 0x290, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__OWIRE_LINE                  IOMUX_PAD(0x610, 0x290, 4, 0x864, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_0__USBPHY1_DATAOUT_2           IOMUX_PAD(0x610, 0x290, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__PATA_DA_1                   IOMUX_PAD(0x614, 0x294, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__GPIO7_7                     IOMUX_PAD(0x614, 0x294, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__ESDHC4_CMD                  IOMUX_PAD(0x614, 0x294, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__UART3_CTS                   IOMUX_PAD(0x614, 0x294, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3           IOMUX_PAD(0x614, 0x294, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__PATA_DA_2                   IOMUX_PAD(0x618, 0x298, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__GPIO7_8                     IOMUX_PAD(0x618, 0x298, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__ESDHC4_CLK                  IOMUX_PAD(0x618, 0x298, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__UART3_RTS                   IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4           IOMUX_PAD(0x618, 0x298, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__PATA_CS_0                   IOMUX_PAD(0x61C, 0x29C, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__GPIO7_9                     IOMUX_PAD(0x61C, 0x29C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__UART3_TXD_MUX               IOMUX_PAD(0x61C, 0x29C, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5           IOMUX_PAD(0x61C, 0x29C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__PATA_CS_1                   IOMUX_PAD(0x620, 0x2A0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__GPIO7_10                    IOMUX_PAD(0x620, 0x2A0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__UART3_RXD_MUX               IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
-#define MX53_PAD_PATA_CS_1__USBPHY1_DATAOUT_6           IOMUX_PAD(0x620, 0x2A0, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__PATA_DATA_0                IOMUX_PAD(0x628, 0x2A4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPIO2_0                    IOMUX_PAD(0x628, 0x2A4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__EMI_NANDF_D_0              IOMUX_PAD(0x628, 0x2A4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__ESDHC3_DAT4                IOMUX_PAD(0x628, 0x2A4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__GPU3d_GPU_DEBUG_OUT_0      IOMUX_PAD(0x628, 0x2A4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__IPU_DIAG_BUS_0             IOMUX_PAD(0x628, 0x2A4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA0__USBPHY1_DATAOUT_7          IOMUX_PAD(0x628, 0x2A4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__PATA_DATA_1                IOMUX_PAD(0x62C, 0x2A8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPIO2_1                    IOMUX_PAD(0x62C, 0x2A8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__EMI_NANDF_D_1              IOMUX_PAD(0x62C, 0x2A8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__ESDHC3_DAT5                IOMUX_PAD(0x62C, 0x2A8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__GPU3d_GPU_DEBUG_OUT_1      IOMUX_PAD(0x62C, 0x2A8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA1__IPU_DIAG_BUS_1             IOMUX_PAD(0x62C, 0x2A8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__PATA_DATA_2                IOMUX_PAD(0x630, 0x2AC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPIO2_2                    IOMUX_PAD(0x630, 0x2AC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__EMI_NANDF_D_2              IOMUX_PAD(0x630, 0x2AC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__ESDHC3_DAT6                IOMUX_PAD(0x630, 0x2AC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__GPU3d_GPU_DEBUG_OUT_2      IOMUX_PAD(0x630, 0x2AC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA2__IPU_DIAG_BUS_2             IOMUX_PAD(0x630, 0x2AC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__PATA_DATA_3                IOMUX_PAD(0x634, 0x2B0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPIO2_3                    IOMUX_PAD(0x634, 0x2B0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__EMI_NANDF_D_3              IOMUX_PAD(0x634, 0x2B0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__ESDHC3_DAT7                IOMUX_PAD(0x634, 0x2B0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__GPU3d_GPU_DEBUG_OUT_3      IOMUX_PAD(0x634, 0x2B0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA3__IPU_DIAG_BUS_3             IOMUX_PAD(0x634, 0x2B0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__PATA_DATA_4                IOMUX_PAD(0x638, 0x2B4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPIO2_4                    IOMUX_PAD(0x638, 0x2B4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__EMI_NANDF_D_4              IOMUX_PAD(0x638, 0x2B4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__ESDHC4_DAT4                IOMUX_PAD(0x638, 0x2B4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__GPU3d_GPU_DEBUG_OUT_4      IOMUX_PAD(0x638, 0x2B4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA4__IPU_DIAG_BUS_4             IOMUX_PAD(0x638, 0x2B4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__PATA_DATA_5                IOMUX_PAD(0x63C, 0x2B8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPIO2_5                    IOMUX_PAD(0x63C, 0x2B8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__EMI_NANDF_D_5              IOMUX_PAD(0x63C, 0x2B8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__ESDHC4_DAT5                IOMUX_PAD(0x63C, 0x2B8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5      IOMUX_PAD(0x63C, 0x2B8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5             IOMUX_PAD(0x63C, 0x2B8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__PATA_DATA_6                IOMUX_PAD(0x640, 0x2BC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPIO2_6                    IOMUX_PAD(0x640, 0x2BC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__EMI_NANDF_D_6              IOMUX_PAD(0x640, 0x2BC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__ESDHC4_DAT6                IOMUX_PAD(0x640, 0x2BC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6      IOMUX_PAD(0x640, 0x2BC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6             IOMUX_PAD(0x640, 0x2BC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__PATA_DATA_7                IOMUX_PAD(0x644, 0x2C0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPIO2_7                    IOMUX_PAD(0x644, 0x2C0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__EMI_NANDF_D_7              IOMUX_PAD(0x644, 0x2C0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__ESDHC4_DAT7                IOMUX_PAD(0x644, 0x2C0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__GPU3d_GPU_DEBUG_OUT_7      IOMUX_PAD(0x644, 0x2C0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA7__IPU_DIAG_BUS_7             IOMUX_PAD(0x644, 0x2C0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__PATA_DATA_8                IOMUX_PAD(0x648, 0x2C4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPIO2_8                    IOMUX_PAD(0x648, 0x2C4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC1_DAT4                IOMUX_PAD(0x648, 0x2C4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__EMI_NANDF_D_8              IOMUX_PAD(0x648, 0x2C4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__ESDHC3_DAT0                IOMUX_PAD(0x648, 0x2C4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__GPU3d_GPU_DEBUG_OUT_8      IOMUX_PAD(0x648, 0x2C4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA8__IPU_DIAG_BUS_8             IOMUX_PAD(0x648, 0x2C4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__PATA_DATA_9                IOMUX_PAD(0x64C, 0x2C8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPIO2_9                    IOMUX_PAD(0x64C, 0x2C8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC1_DAT5                IOMUX_PAD(0x64C, 0x2C8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__EMI_NANDF_D_9              IOMUX_PAD(0x64C, 0x2C8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__ESDHC3_DAT1                IOMUX_PAD(0x64C, 0x2C8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__GPU3d_GPU_DEBUG_OUT_9      IOMUX_PAD(0x64C, 0x2C8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA9__IPU_DIAG_BUS_9             IOMUX_PAD(0x64C, 0x2C8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__PATA_DATA_10              IOMUX_PAD(0x650, 0x2CC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPIO2_10                  IOMUX_PAD(0x650, 0x2CC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC1_DAT6               IOMUX_PAD(0x650, 0x2CC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__EMI_NANDF_D_10            IOMUX_PAD(0x650, 0x2CC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__ESDHC3_DAT2               IOMUX_PAD(0x650, 0x2CC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__GPU3d_GPU_DEBUG_OUT_10    IOMUX_PAD(0x650, 0x2CC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA10__IPU_DIAG_BUS_10           IOMUX_PAD(0x650, 0x2CC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__PATA_DATA_11              IOMUX_PAD(0x654, 0x2D0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPIO2_11                  IOMUX_PAD(0x654, 0x2D0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC1_DAT7               IOMUX_PAD(0x654, 0x2D0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__EMI_NANDF_D_11            IOMUX_PAD(0x654, 0x2D0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__ESDHC3_DAT3               IOMUX_PAD(0x654, 0x2D0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__GPU3d_GPU_DEBUG_OUT_11    IOMUX_PAD(0x654, 0x2D0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA11__IPU_DIAG_BUS_11           IOMUX_PAD(0x654, 0x2D0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__PATA_DATA_12              IOMUX_PAD(0x658, 0x2D4, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPIO2_12                  IOMUX_PAD(0x658, 0x2D4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC2_DAT4               IOMUX_PAD(0x658, 0x2D4, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__EMI_NANDF_D_12            IOMUX_PAD(0x658, 0x2D4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__ESDHC4_DAT0               IOMUX_PAD(0x658, 0x2D4, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__GPU3d_GPU_DEBUG_OUT_12    IOMUX_PAD(0x658, 0x2D4, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA12__IPU_DIAG_BUS_12           IOMUX_PAD(0x658, 0x2D4, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__PATA_DATA_13              IOMUX_PAD(0x65C, 0x2D8, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPIO2_13                  IOMUX_PAD(0x65C, 0x2D8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC2_DAT5               IOMUX_PAD(0x65C, 0x2D8, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__EMI_NANDF_D_13            IOMUX_PAD(0x65C, 0x2D8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__ESDHC4_DAT1               IOMUX_PAD(0x65C, 0x2D8, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__GPU3d_GPU_DEBUG_OUT_13    IOMUX_PAD(0x65C, 0x2D8, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA13__IPU_DIAG_BUS_13           IOMUX_PAD(0x65C, 0x2D8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__PATA_DATA_14              IOMUX_PAD(0x660, 0x2DC, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPIO2_14                  IOMUX_PAD(0x660, 0x2DC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC2_DAT6               IOMUX_PAD(0x660, 0x2DC, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__EMI_NANDF_D_14            IOMUX_PAD(0x660, 0x2DC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__ESDHC4_DAT2               IOMUX_PAD(0x660, 0x2DC, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__GPU3d_GPU_DEBUG_OUT_14    IOMUX_PAD(0x660, 0x2DC, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA14__IPU_DIAG_BUS_14           IOMUX_PAD(0x660, 0x2DC, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__PATA_DATA_15              IOMUX_PAD(0x664, 0x2E0, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPIO2_15                  IOMUX_PAD(0x664, 0x2E0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC2_DAT7               IOMUX_PAD(0x664, 0x2E0, 2, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__EMI_NANDF_D_15            IOMUX_PAD(0x664, 0x2E0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__ESDHC4_DAT3               IOMUX_PAD(0x664, 0x2E0, 4, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__GPU3d_GPU_DEBUG_OUT_15    IOMUX_PAD(0x664, 0x2E0, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_PATA_DATA15__IPU_DIAG_BUS_15           IOMUX_PAD(0x664, 0x2E0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__ESDHC1_DAT0                 IOMUX_PAD(0x66C, 0x2E4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPIO1_16                    IOMUX_PAD(0x66C, 0x2E4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__GPT_CAPIN1                  IOMUX_PAD(0x66C, 0x2E4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CSPI_MISO                   IOMUX_PAD(0x66C, 0x2E4, 5, 0x784, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA0__CCM_PLL3_BYP                IOMUX_PAD(0x66C, 0x2E4, 7, 0x778, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__ESDHC1_DAT1                 IOMUX_PAD(0x670, 0x2E8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPIO1_17                    IOMUX_PAD(0x670, 0x2E8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__GPT_CAPIN2                  IOMUX_PAD(0x670, 0x2E8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CSPI_SS0                    IOMUX_PAD(0x670, 0x2E8, 5, 0x78C, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA1__CCM_PLL4_BYP                IOMUX_PAD(0x670, 0x2E8, 7, 0x77C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__ESDHC1_CMD                    IOMUX_PAD(0x674, 0x2EC, 0 | IOMUX_CONFIG_SION, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPIO1_18                      IOMUX_PAD(0x674, 0x2EC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__GPT_CMPOUT1                   IOMUX_PAD(0x674, 0x2EC, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CSPI_MOSI                     IOMUX_PAD(0x674, 0x2EC, 5, 0x788, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CMD__CCM_PLL1_BYP                  IOMUX_PAD(0x674, 0x2EC, 7, 0x770, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__ESDHC1_DAT2                 IOMUX_PAD(0x678, 0x2F0, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPIO1_19                    IOMUX_PAD(0x678, 0x2F0, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__GPT_CMPOUT2                 IOMUX_PAD(0x678, 0x2F0, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__PWM2_PWMO                   IOMUX_PAD(0x678, 0x2F0, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_B                IOMUX_PAD(0x678, 0x2F0, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CSPI_SS1                    IOMUX_PAD(0x678, 0x2F0, 5, 0x790, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__WDOG1_WDOG_RST_B_DEB        IOMUX_PAD(0x678, 0x2F0, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA2__CCM_PLL2_BYP                IOMUX_PAD(0x678, 0x2F0, 7, 0x774, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__ESDHC1_CLK                    IOMUX_PAD(0x67C, 0x2F4, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPIO1_20                      IOMUX_PAD(0x67C, 0x2F4, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__OSC32k_32K_OUT                IOMUX_PAD(0x67C, 0x2F4, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__GPT_CLKIN                     IOMUX_PAD(0x67C, 0x2F4, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__CSPI_SCLK                     IOMUX_PAD(0x67C, 0x2F4, 5, 0x780, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_CLK__SATA_PHY_DTB_0                IOMUX_PAD(0x67C, 0x2F4, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__ESDHC1_DAT3                 IOMUX_PAD(0x680, 0x2F8, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPIO1_21                    IOMUX_PAD(0x680, 0x2F8, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__GPT_CMPOUT3                 IOMUX_PAD(0x680, 0x2F8, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__PWM1_PWMO                   IOMUX_PAD(0x680, 0x2F8, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_B                IOMUX_PAD(0x680, 0x2F8, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__CSPI_SS2                    IOMUX_PAD(0x680, 0x2F8, 5, 0x794, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__WDOG2_WDOG_RST_B_DEB        IOMUX_PAD(0x680, 0x2F8, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD1_DATA3__SATA_PHY_DTB_1              IOMUX_PAD(0x680, 0x2F8, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__ESDHC2_CLK                    IOMUX_PAD(0x688, 0x2FC, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__GPIO1_10                      IOMUX_PAD(0x688, 0x2FC, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__KPP_COL_5                     IOMUX_PAD(0x688, 0x2FC, 2, 0x840, 2, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__AUDMUX_AUD4_RXFS              IOMUX_PAD(0x688, 0x2FC, 3, 0x73C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__CSPI_SCLK                     IOMUX_PAD(0x688, 0x2FC, 5, 0x780, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CLK__SCC_RANDOM_V                  IOMUX_PAD(0x688, 0x2FC, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__ESDHC2_CMD                    IOMUX_PAD(0x68C, 0x300, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__GPIO1_11                      IOMUX_PAD(0x68C, 0x300, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__KPP_ROW_5                     IOMUX_PAD(0x68C, 0x300, 2, 0x84C, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__AUDMUX_AUD4_RXC               IOMUX_PAD(0x68C, 0x300, 3, 0x738, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__CSPI_MOSI                     IOMUX_PAD(0x68C, 0x300, 5, 0x788, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_CMD__SCC_RANDOM                    IOMUX_PAD(0x68C, 0x300, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__ESDHC2_DAT3                 IOMUX_PAD(0x690, 0x304, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__GPIO1_12                    IOMUX_PAD(0x690, 0x304, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__KPP_COL_6                   IOMUX_PAD(0x690, 0x304, 2, 0x844, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC             IOMUX_PAD(0x690, 0x304, 3, 0x740, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__CSPI_SS2                    IOMUX_PAD(0x690, 0x304, 5, 0x794, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA3__SJC_DONE                    IOMUX_PAD(0x690, 0x304, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__ESDHC2_DAT2                 IOMUX_PAD(0x694, 0x308, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__GPIO1_13                    IOMUX_PAD(0x694, 0x308, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__KPP_ROW_6                   IOMUX_PAD(0x694, 0x308, 2, 0x850, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD             IOMUX_PAD(0x694, 0x308, 3, 0x734, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__CSPI_SS1                    IOMUX_PAD(0x694, 0x308, 5, 0x790, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA2__SJC_FAIL                    IOMUX_PAD(0x694, 0x308, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__ESDHC2_DAT1                 IOMUX_PAD(0x698, 0x30C, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__GPIO1_14                    IOMUX_PAD(0x698, 0x30C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__KPP_COL_7                   IOMUX_PAD(0x698, 0x30C, 2, 0x848, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS            IOMUX_PAD(0x698, 0x30C, 3, 0x744, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__CSPI_SS0                    IOMUX_PAD(0x698, 0x30C, 5, 0x78C, 4, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA1__RTIC_SEC_VIO                IOMUX_PAD(0x698, 0x30C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__ESDHC2_DAT0                 IOMUX_PAD(0x69C, 0x310, 0, __NA_, 0, MX53_SDHC_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__GPIO1_15                    IOMUX_PAD(0x69C, 0x310, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__KPP_ROW_7                   IOMUX_PAD(0x69C, 0x310, 2, 0x854, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD             IOMUX_PAD(0x69C, 0x310, 3, 0x730, 1, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__CSPI_MISO                   IOMUX_PAD(0x69C, 0x310, 5, 0x784, 3, NO_PAD_CTRL)
-#define MX53_PAD_SD2_DATA0__RTIC_DONE_INT               IOMUX_PAD(0x69C, 0x310, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_CLKO                       IOMUX_PAD(0x6A4, 0x314, 0, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__GPIO1_0                        IOMUX_PAD(0x6A4, 0x314, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__KPP_COL_5                      IOMUX_PAD(0x6A4, 0x314, 2, 0x840, 3, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK               IOMUX_PAD(0x6A4, 0x314, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__EPIT1_EPITO                    IOMUX_PAD(0x6A4, 0x314, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__SRTC_ALARM_DEB                 IOMUX_PAD(0x6A4, 0x314, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__USBOH3_USBH1_PWR               IOMUX_PAD(0x6A4, 0x314, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_0__CSU_TD                         IOMUX_PAD(0x6A4, 0x314, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESAI1_SCKR                     IOMUX_PAD(0x6A8, 0x318, 0, 0x7DC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__GPIO1_1                        IOMUX_PAD(0x6A8, 0x318, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__KPP_ROW_5                      IOMUX_PAD(0x6A8, 0x318, 2, 0x84C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__CCM_SSI_EXT2_CLK               IOMUX_PAD(0x6A8, 0x318, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__PWM2_PWMO                      IOMUX_PAD(0x6A8, 0x318, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__WDOG2_WDOG_B                   IOMUX_PAD(0x6A8, 0x318, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__ESDHC1_CD                      IOMUX_PAD(0x6A8, 0x318, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_1__SRC_TESTER_ACK                 IOMUX_PAD(0x6A8, 0x318, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESAI1_FSR                      IOMUX_PAD(0x6AC, 0x31C, 0, 0x7CC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__GPIO1_9                        IOMUX_PAD(0x6AC, 0x31C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__KPP_COL_6                      IOMUX_PAD(0x6AC, 0x31C, 2, 0x844, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__CCM_REF_EN_B                   IOMUX_PAD(0x6AC, 0x31C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__PWM1_PWMO                      IOMUX_PAD(0x6AC, 0x31C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__WDOG1_WDOG_B                   IOMUX_PAD(0x6AC, 0x31C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__ESDHC1_WP                      IOMUX_PAD(0x6AC, 0x31C, 6, 0x7FC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_9__SCC_FAIL_STATE                 IOMUX_PAD(0x6AC, 0x31C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__ESAI1_HCKR                     IOMUX_PAD(0x6B0, 0x320, 0, 0x7D4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__GPIO1_3                        IOMUX_PAD(0x6B0, 0x320, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__I2C3_SCL                       IOMUX_PAD(0x6B0, 0x320, 2 | IOMUX_CONFIG_SION, 0x824, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__DPLLIP1_TOG_EN                 IOMUX_PAD(0x6B0, 0x320, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__CCM_CLKO2                      IOMUX_PAD(0x6B0, 0x320, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0     IOMUX_PAD(0x6B0, 0x320, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__USBOH3_USBH1_OC                IOMUX_PAD(0x6B0, 0x320, 6, 0x8A0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_3__MLB_MLBCLK                     IOMUX_PAD(0x6B0, 0x320, 7, 0x858, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESAI1_SCKT                     IOMUX_PAD(0x6B4, 0x324, 0, 0x7E0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__GPIO1_6                        IOMUX_PAD(0x6B4, 0x324, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__I2C3_SDA                       IOMUX_PAD(0x6B4, 0x324, 2 | IOMUX_CONFIG_SION, 0x828, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CCM_CCM_OUT_0                  IOMUX_PAD(0x6B4, 0x324, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__CSU_CSU_INT_DEB                IOMUX_PAD(0x6B4, 0x324, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1     IOMUX_PAD(0x6B4, 0x324, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__ESDHC2_LCTL                    IOMUX_PAD(0x6B4, 0x324, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_6__MLB_MLBSIG                     IOMUX_PAD(0x6B4, 0x324, 7, 0x860, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESAI1_FST                      IOMUX_PAD(0x6B8, 0x328, 0, 0x7D0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__GPIO1_2                        IOMUX_PAD(0x6B8, 0x328, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__KPP_ROW_6                      IOMUX_PAD(0x6B8, 0x328, 2, 0x850, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CCM_CCM_OUT_1                  IOMUX_PAD(0x6B8, 0x328, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__CSU_CSU_ALARM_AUT_0            IOMUX_PAD(0x6B8, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__OBSERVE_MUX_OBSRV_INT_OUT2     IOMUX_PAD(0x6B8, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__ESDHC2_WP                      IOMUX_PAD(0x6B8, 0x328, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_2__MLB_MLBDAT                     IOMUX_PAD(0x6B8, 0x328, 7, 0x85C, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESAI1_HCKT                     IOMUX_PAD(0x6BC, 0x32C, 0, 0x7D8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__GPIO1_4                        IOMUX_PAD(0x6BC, 0x32C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__KPP_COL_7                      IOMUX_PAD(0x6BC, 0x32C, 2, 0x848, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CCM_CCM_OUT_2                  IOMUX_PAD(0x6BC, 0x32C, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__CSU_CSU_ALARM_AUT_1            IOMUX_PAD(0x6BC, 0x32C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__OBSERVE_MUX_OBSRV_INT_OUT3     IOMUX_PAD(0x6BC, 0x32C, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__ESDHC2_CD                      IOMUX_PAD(0x6BC, 0x32C, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_4__SCC_SEC_STATE                  IOMUX_PAD(0x6BC, 0x32C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__ESAI1_TX2_RX3                  IOMUX_PAD(0x6C0, 0x330, 0, 0x7EC, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__GPIO1_5                        IOMUX_PAD(0x6C0, 0x330, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__KPP_ROW_7                      IOMUX_PAD(0x6C0, 0x330, 2, 0x854, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_CLKO                       IOMUX_PAD(0x6C0, 0x330, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2            IOMUX_PAD(0x6C0, 0x330, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4     IOMUX_PAD(0x6C0, 0x330, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__I2C3_SCL                       IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_5__CCM_PLL1_BYP                   IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__ESAI1_TX4_RX1                  IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__GPIO1_7                        IOMUX_PAD(0x6C4, 0x334, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__EPIT1_EPITO                    IOMUX_PAD(0x6C4, 0x334, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CAN1_TXCAN                     IOMUX_PAD(0x6C4, 0x334, 3, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX                  IOMUX_PAD(0x6C4, 0x334, 4, __NA_, 0, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_7__FIRI_RXD                       IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__SPDIF_PLOCK                    IOMUX_PAD(0x6C4, 0x334, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_7__CCM_PLL2_BYP                   IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__ESAI1_TX5_RX0                  IOMUX_PAD(0x6C8, 0x338, 0, 0x7F8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__GPIO1_8                        IOMUX_PAD(0x6C8, 0x338, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__EPIT2_EPITO                    IOMUX_PAD(0x6C8, 0x338, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CAN1_RXCAN                     IOMUX_PAD(0x6C8, 0x338, 3, 0x760, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX                  IOMUX_PAD(0x6C8, 0x338, 4, 0x880, 5, MX53_UART_PAD_CTRL)
-#define MX53_PAD_GPIO_8__FIRI_TXD                       IOMUX_PAD(0x6C8, 0x338, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__SPDIF_SRCLK                    IOMUX_PAD(0x6C8, 0x338, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_8__CCM_PLL3_BYP                   IOMUX_PAD(0x6C8, 0x338, 7, 0x778, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__ESAI1_TX3_RX2                 IOMUX_PAD(0x6CC, 0x33C, 0, 0x7F0, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__GPIO7_11                      IOMUX_PAD(0x6CC, 0x33C, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__TZIC_PWRFAIL_INT              IOMUX_PAD(0x6CC, 0x33C, 2, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__RTC_CE_RTC_EXT_TRIG1          IOMUX_PAD(0x6CC, 0x33C, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SPDIF_IN1                     IOMUX_PAD(0x6CC, 0x33C, 5, 0x870, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__I2C3_SDA                      IOMUX_PAD(0x6CC, 0x33C, 6 | IOMUX_CONFIG_SION, 0x828, 2, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_16__SJC_DE_B                      IOMUX_PAD(0x6CC, 0x33C, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__ESAI1_TX0                     IOMUX_PAD(0x6D0, 0x340, 0, 0x7E4, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPIO7_12                      IOMUX_PAD(0x6D0, 0x340, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SDMA_EXT_EVENT_0              IOMUX_PAD(0x6D0, 0x340, 2, 0x868, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__GPC_PMIC_RDY                  IOMUX_PAD(0x6D0, 0x340, 3, 0x810, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__RTC_CE_RTC_FSV_TRIG           IOMUX_PAD(0x6D0, 0x340, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SPDIF_OUT1                    IOMUX_PAD(0x6D0, 0x340, 5, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__IPU_SNOOP2                    IOMUX_PAD(0x6D0, 0x340, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_17__SJC_JTAG_ACT                  IOMUX_PAD(0x6D0, 0x340, 7, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESAI1_TX1                     IOMUX_PAD(0x6D4, 0x344, 0, 0x7E8, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__GPIO7_13                      IOMUX_PAD(0x6D4, 0x344, 1, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SDMA_EXT_EVENT_1              IOMUX_PAD(0x6D4, 0x344, 2, 0x86C, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__OWIRE_LINE                    IOMUX_PAD(0x6D4, 0x344, 3, 0x864, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__RTC_CE_RTC_ALARM2_TRIG        IOMUX_PAD(0x6D4, 0x344, 4, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__CCM_ASRC_EXT_CLK              IOMUX_PAD(0x6D4, 0x344, 5, 0x768, 1, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__ESDHC1_LCTL                   IOMUX_PAD(0x6D4, 0x344, 6, __NA_, 0, NO_PAD_CTRL)
-#define MX53_PAD_GPIO_18__SRC_SYSTEM_RST                IOMUX_PAD(0x6D4, 0x344, 7, __NA_, 0, NO_PAD_CTRL)
-
-#endif  /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 9b9646c3673d..05330735f23f 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -615,6 +615,7 @@ int omap_hwmod_softreset(struct omap_hwmod *oh);
 
 int omap_hwmod_count_resources(struct omap_hwmod *oh);
 int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
+int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res);
 int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type,
                                    const char *name, struct resource *res);
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 5c93c09a80c2..d5f617c542d3 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -365,6 +365,14 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                 goto odbfd_exit1;
         }
 
+        /* Fix up missing resource names */
+        for (i = 0; i < pdev->num_resources; i++) {
+                struct resource *r = &pdev->resource[i];
+
+                if (r->name == NULL)
+                        r->name = dev_name(&pdev->dev);
+        }
+
         if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
                 omap_device_disable_idle_on_suspend(pdev);
 
@@ -485,6 +493,33 @@ static int omap_device_fill_resources(struct omap_device *od,
 }
 
 /**
+ * _od_fill_dma_resources - fill in array of struct resource with dma resources
+ * @od: struct omap_device *
+ * @res: pointer to an array of struct resource to be filled in
+ *
+ * Populate one or more empty struct resource pointed to by @res with
+ * the dma resource data for this omap_device @od.  Used by
+ * omap_device_alloc() after calling omap_device_count_resources().
+ *
+ * Ideally this function would not be needed at all.  If we have
+ * mechanism to get dma resources from DT.
+ *
+ * Returns 0.
+ */
+static int _od_fill_dma_resources(struct omap_device *od,
+                                      struct resource *res)
+{
+        int i, r;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                r = omap_hwmod_fill_dma_resources(od->hwmods[i], res);
+                res += r;
+        }
+
+        return 0;
+}
+
+/**
  * omap_device_alloc - allocate an omap_device
  * @pdev: platform_device that will be included in this omap_device
  * @oh: ptr to the single omap_hwmod that backs this omap_device
@@ -523,24 +558,44 @@ struct omap_device *omap_device_alloc(struct platform_device *pdev,
         od->hwmods = hwmods;
         od->pdev = pdev;
 
+        res_count = omap_device_count_resources(od);
         /*
-         * HACK: Ideally the resources from DT should match, and hwmod
-         * should just add the missing ones. Since the name is not
-         * properly populated by DT, stick to hwmod resources only.
+         * DT Boot:
+         *   OF framework will construct the resource structure (currently
+         *   does for MEM & IRQ resource) and we should respect/use these
+         *   resources, killing hwmod dependency.
+         *   If pdev->num_resources > 0, we assume that MEM & IRQ resources
+         *   have been allocated by OF layer already (through DTB).
+         *
+         * Non-DT Boot:
+         *   Here, pdev->num_resources = 0, and we should get all the
+         *   resources from hwmod.
+         *
+         * TODO: Once DMA resource is available from OF layer, we should
+         *   kill filling any resources from hwmod.
          */
-        if (pdev->num_resources && pdev->resource)
-                dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
-                        __func__, pdev->num_resources);
-
-        res_count = omap_device_count_resources(od);
-        if (res_count > 0) {
-                dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
-                        __func__, res_count);
+        if (res_count > pdev->num_resources) {
+                /* Allocate resources memory to account for new resources */
                 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
                 if (!res)
                         goto oda_exit3;
 
-                omap_device_fill_resources(od, res);
+                /*
+                 * If pdev->num_resources > 0, then assume that,
+                 * MEM and IRQ resources will only come from DT and only
+                 * fill DMA resource from hwmod layer.
+                 */
+                if (pdev->num_resources && pdev->resource) {
+                        dev_dbg(&pdev->dev, "%s(): resources already allocated %d\n",
+                                __func__, res_count);
+                        memcpy(res, pdev->resource,
+                               sizeof(struct resource) * pdev->num_resources);
+                        _od_fill_dma_resources(od, &res[pdev->num_resources]);
+                } else {
+                        dev_dbg(&pdev->dev, "%s(): using resources from hwmod %d\n",
+                                __func__, res_count);
+                        omap_device_fill_resources(od, res);
+                }
 
                 ret = platform_device_add_resources(pdev, res, res_count);
                 kfree(res);
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2b861625bdae..71a25b91de00 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_ARCH_MMP)		+= mmp/
 endif
 obj-$(CONFIG_MACH_LOONGSON1)    += clk-ls1x.o
 obj-$(CONFIG_ARCH_U8500)        += ux500/
+obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
 
 # Chip specific
 obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
new file mode 100644
index 000000000000..a885600f5270
--- /dev/null
+++ b/drivers/clk/clk-vt8500.c
@@ -0,0 +1,510 @@
+/*
+ * Clock implementation for VIA/Wondermedia SoC's
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+
+/* All clocks share the same lock as none can be changed concurrently */
+static DEFINE_SPINLOCK(_lock);
+
+struct clk_device {
+        struct clk_hw   hw;
+        void __iomem    *div_reg;
+        unsigned int    div_mask;
+        void __iomem    *en_reg;
+        int             en_bit;
+        spinlock_t      *lock;
+};
+
+/*
+ * Add new PLL_TYPE_x definitions here as required. Use the first known model
+ * to support the new type as the name.
+ * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
+ * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
+ */
+
+#define PLL_TYPE_VT8500         0
+#define PLL_TYPE_WM8650         1
+
+struct clk_pll {
+        struct clk_hw   hw;
+        void __iomem    *reg;
+        spinlock_t      *lock;
+        int             type;
+};
+
+static void __iomem *pmc_base;
+
+#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
+
+#define VT8500_PMC_BUSY_MASK            0x18
+
+static void vt8500_pmc_wait_busy(void)
+{
+        while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
+                cpu_relax();
+}
+
+static int vt8500_dclk_enable(struct clk_hw *hw)
+{
+        struct clk_device *cdev = to_clk_device(hw);
+        u32 en_val;
+        unsigned long flags = 0;
+
+        spin_lock_irqsave(cdev->lock, flags);
+
+        en_val = readl(cdev->en_reg);
+        en_val |= BIT(cdev->en_bit);
+        writel(en_val, cdev->en_reg);
+
+        spin_unlock_irqrestore(cdev->lock, flags);
+        return 0;
+}
+
+static void vt8500_dclk_disable(struct clk_hw *hw)
+{
+        struct clk_device *cdev = to_clk_device(hw);
+        u32 en_val;
+        unsigned long flags = 0;
+
+        spin_lock_irqsave(cdev->lock, flags);
+
+        en_val = readl(cdev->en_reg);
+        en_val &= ~BIT(cdev->en_bit);
+        writel(en_val, cdev->en_reg);
+
+        spin_unlock_irqrestore(cdev->lock, flags);
+}
+
+static int vt8500_dclk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_device *cdev = to_clk_device(hw);
+        u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
+
+        return en_val ? 1 : 0;
+}
+
+static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct clk_device *cdev = to_clk_device(hw);
+        u32 div = readl(cdev->div_reg) & cdev->div_mask;
+
+        /* Special case for SDMMC devices */
+        if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
+                div = 64 * (div & 0x1f);
+
+        /* div == 0 is actually the highest divisor */
+        if (div == 0)
+                div = (cdev->div_mask + 1);
+
+        return parent_rate / div;
+}
+
+static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        u32 divisor = *prate / rate;
+
+        return *prate / divisor;
+}
+
+static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct clk_device *cdev = to_clk_device(hw);
+        u32 divisor = parent_rate / rate;
+        unsigned long flags = 0;
+
+        if (divisor == cdev->div_mask + 1)
+                divisor = 0;
+
+        if (divisor > cdev->div_mask) {
+                pr_err("%s: invalid divisor for clock\n", __func__);
+                return -EINVAL;
+        }
+
+        spin_lock_irqsave(cdev->lock, flags);
+
+        vt8500_pmc_wait_busy();
+        writel(divisor, cdev->div_reg);
+        vt8500_pmc_wait_busy();
+
+        spin_lock_irqsave(cdev->lock, flags);
+
+        return 0;
+}
+
+
+static const struct clk_ops vt8500_gated_clk_ops = {
+        .enable = vt8500_dclk_enable,
+        .disable = vt8500_dclk_disable,
+        .is_enabled = vt8500_dclk_is_enabled,
+};
+
+static const struct clk_ops vt8500_divisor_clk_ops = {
+        .round_rate = vt8500_dclk_round_rate,
+        .set_rate = vt8500_dclk_set_rate,
+        .recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+static const struct clk_ops vt8500_gated_divisor_clk_ops = {
+        .enable = vt8500_dclk_enable,
+        .disable = vt8500_dclk_disable,
+        .is_enabled = vt8500_dclk_is_enabled,
+        .round_rate = vt8500_dclk_round_rate,
+        .set_rate = vt8500_dclk_set_rate,
+        .recalc_rate = vt8500_dclk_recalc_rate,
+};
+
+#define CLK_INIT_GATED                  BIT(0)
+#define CLK_INIT_DIVISOR                BIT(1)
+#define CLK_INIT_GATED_DIVISOR          (CLK_INIT_DIVISOR | CLK_INIT_GATED)
+
+static __init void vtwm_device_clk_init(struct device_node *node)
+{
+        u32 en_reg, div_reg;
+        struct clk *clk;
+        struct clk_device *dev_clk;
+        const char *clk_name = node->name;
+        const char *parent_name;
+        struct clk_init_data init;
+        int rc;
+        int clk_init_flags = 0;
+
+        dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
+        if (WARN_ON(!dev_clk))
+                return;
+
+        dev_clk->lock = &_lock;
+
+        rc = of_property_read_u32(node, "enable-reg", &en_reg);
+        if (!rc) {
+                dev_clk->en_reg = pmc_base + en_reg;
+                rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
+                if (rc) {
+                        pr_err("%s: enable-bit property required for gated clock\n",
+                                                                __func__);
+                        return;
+                }
+                clk_init_flags |= CLK_INIT_GATED;
+        }
+
+        rc = of_property_read_u32(node, "divisor-reg", &div_reg);
+        if (!rc) {
+                dev_clk->div_reg = pmc_base + div_reg;
+                /*
+                 * use 0x1f as the default mask since it covers
+                 * almost all the clocks and reduces dts properties
+                 */
+                dev_clk->div_mask = 0x1f;
+
+                of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
+                clk_init_flags |= CLK_INIT_DIVISOR;
+        }
+
+        of_property_read_string(node, "clock-output-names", &clk_name);
+
+        switch (clk_init_flags) {
+        case CLK_INIT_GATED:
+                init.ops = &vt8500_gated_clk_ops;
+                break;
+        case CLK_INIT_DIVISOR:
+                init.ops = &vt8500_divisor_clk_ops;
+                break;
+        case CLK_INIT_GATED_DIVISOR:
+                init.ops = &vt8500_gated_divisor_clk_ops;
+                break;
+        default:
+                pr_err("%s: Invalid clock description in device tree\n",
+                                                                __func__);
+                kfree(dev_clk);
+                return;
+        }
+
+        init.name = clk_name;
+        init.flags = 0;
+        parent_name = of_clk_get_parent_name(node, 0);
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        dev_clk->hw.init = &init;
+
+        clk = clk_register(NULL, &dev_clk->hw);
+        if (WARN_ON(IS_ERR(clk))) {
+                kfree(dev_clk);
+                return;
+        }
+        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+        clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* PLL clock related functions */
+
+#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
+
+/* Helper macros for PLL_VT8500 */
+#define VT8500_PLL_MUL(x)       ((x & 0x1F) << 1)
+#define VT8500_PLL_DIV(x)       ((x & 0x100) ? 1 : 2)
+
+#define VT8500_BITS_TO_FREQ(r, m, d)                                    \
+                                ((r / d) * m)
+
+#define VT8500_BITS_TO_VAL(m, d)                                        \
+                                ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
+
+/* Helper macros for PLL_WM8650 */
+#define WM8650_PLL_MUL(x)       (x & 0x3FF)
+#define WM8650_PLL_DIV(x)       (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
+
+#define WM8650_BITS_TO_FREQ(r, m, d1, d2)                               \
+                                (r * m / (d1 * (1 << d2)))
+
+#define WM8650_BITS_TO_VAL(m, d1, d2)                                   \
+                                ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
+
+
+static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+                                u32 *multiplier, u32 *prediv)
+{
+        unsigned long tclk;
+
+        /* sanity check */
+        if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
+                pr_err("%s: requested rate out of range\n", __func__);
+                *multiplier = 0;
+                *prediv = 1;
+                return;
+        }
+        if (rate <= parent_rate * 31)
+                /* use the prediv to double the resolution */
+                *prediv = 2;
+        else
+                *prediv = 1;
+
+        *multiplier = rate / (parent_rate / *prediv);
+        tclk = (parent_rate / *prediv) * *multiplier;
+
+        if (tclk != rate)
+                pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
+                                                                rate, tclk);
+}
+
+static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
+                                u32 *multiplier, u32 *divisor1, u32 *divisor2)
+{
+        u32 mul, div1, div2;
+        u32 best_mul, best_div1, best_div2;
+        unsigned long tclk, rate_err, best_err;
+
+        best_err = (unsigned long)-1;
+
+        /* Find the closest match (lower or equal to requested) */
+        for (div1 = 5; div1 >= 3; div1--)
+                for (div2 = 3; div2 >= 0; div2--)
+                        for (mul = 3; mul <= 1023; mul++) {
+                                tclk = parent_rate * mul / (div1 * (1 << div2));
+                                if (tclk > rate)
+                                        continue;
+                                /* error will always be +ve */
+                                rate_err = rate - tclk;
+                                if (rate_err == 0) {
+                                        *multiplier = mul;
+                                        *divisor1 = div1;
+                                        *divisor2 = div2;
+                                        return;
+                                }
+
+                                if (rate_err < best_err) {
+                                        best_err = rate_err;
+                                        best_mul = mul;
+                                        best_div1 = div1;
+                                        best_div2 = div2;
+                                }
+                        }
+
+        /* if we got here, it wasn't an exact match */
+        pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
+                                                        rate - best_err);
+        *multiplier = mul;
+        *divisor1 = div1;
+        *divisor2 = div2;
+}
+
+static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long parent_rate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        u32 mul, div1, div2;
+        u32 pll_val;
+        unsigned long flags = 0;
+
+        /* sanity check */
+
+        switch (pll->type) {
+        case PLL_TYPE_VT8500:
+                vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
+                pll_val = VT8500_BITS_TO_VAL(mul, div1);
+                break;
+        case PLL_TYPE_WM8650:
+                wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
+                pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
+                break;
+        default:
+                pr_err("%s: invalid pll type\n", __func__);
+                return 0;
+        }
+
+        spin_lock_irqsave(pll->lock, flags);
+
+        vt8500_pmc_wait_busy();
+        writel(pll_val, pll->reg);
+        vt8500_pmc_wait_busy();
+
+        spin_unlock_irqrestore(pll->lock, flags);
+
+        return 0;
+}
+
+static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                unsigned long *prate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        u32 mul, div1, div2;
+        long round_rate;
+
+        switch (pll->type) {
+        case PLL_TYPE_VT8500:
+                vt8500_find_pll_bits(rate, *prate, &mul, &div1);
+                round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
+                break;
+        case PLL_TYPE_WM8650:
+                wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
+                round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
+                break;
+        default:
+                round_rate = 0;
+        }
+
+        return round_rate;
+}
+
+static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
+                                unsigned long parent_rate)
+{
+        struct clk_pll *pll = to_clk_pll(hw);
+        u32 pll_val = readl(pll->reg);
+        unsigned long pll_freq;
+
+        switch (pll->type) {
+        case PLL_TYPE_VT8500:
+                pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
+                pll_freq /= VT8500_PLL_DIV(pll_val);
+                break;
+        case PLL_TYPE_WM8650:
+                pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
+                pll_freq /= WM8650_PLL_DIV(pll_val);
+                break;
+        default:
+                pll_freq = 0;
+        }
+
+        return pll_freq;
+}
+
+const struct clk_ops vtwm_pll_ops = {
+        .round_rate = vtwm_pll_round_rate,
+        .set_rate = vtwm_pll_set_rate,
+        .recalc_rate = vtwm_pll_recalc_rate,
+};
+
+static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
+{
+        u32 reg;
+        struct clk *clk;
+        struct clk_pll *pll_clk;
+        const char *clk_name = node->name;
+        const char *parent_name;
+        struct clk_init_data init;
+        int rc;
+
+        rc = of_property_read_u32(node, "reg", &reg);
+        if (WARN_ON(rc))
+                return;
+
+        pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
+        if (WARN_ON(!pll_clk))
+                return;
+
+        pll_clk->reg = pmc_base + reg;
+        pll_clk->lock = &_lock;
+        pll_clk->type = pll_type;
+
+        of_property_read_string(node, "clock-output-names", &clk_name);
+
+        init.name = clk_name;
+        init.ops = &vtwm_pll_ops;
+        init.flags = 0;
+        parent_name = of_clk_get_parent_name(node, 0);
+        init.parent_names = &parent_name;
+        init.num_parents = 1;
+
+        pll_clk->hw.init = &init;
+
+        clk = clk_register(NULL, &pll_clk->hw);
+        if (WARN_ON(IS_ERR(clk))) {
+                kfree(pll_clk);
+                return;
+        }
+        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+        clk_register_clkdev(clk, clk_name, NULL);
+}
+
+
+/* Wrappers for initialization functions */
+
+static void __init vt8500_pll_init(struct device_node *node)
+{
+        vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
+}
+
+static void __init wm8650_pll_init(struct device_node *node)
+{
+        vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
+}
+
+static const __initconst struct of_device_id clk_match[] = {
+        { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
+        { .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
+        { .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
+        { .compatible = "via,vt8500-device-clock",
+                                        .data = vtwm_device_clk_init, },
+        { /* sentinel */ }
+};
+
+void __init vtwm_clk_init(void __iomem *base)
+{
+        if (!base)
+                return;
+
+        pmc_base = base;
+
+        of_clk_init(clk_match);
+}
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 844043ad0fe4..9f6d15546cbe 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx23.h>
 #include "clk.h"
@@ -71,44 +72,6 @@ static void __init clk_misc_init(void)
         __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
 }
 
-static struct clk_lookup uart_lookups[] = {
-        { .dev_id = "duart", },
-        { .dev_id = "mxs-auart.0", },
-        { .dev_id = "mxs-auart.1", },
-        { .dev_id = "8006c000.serial", },
-        { .dev_id = "8006e000.serial", },
-        { .dev_id = "80070000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-        { .dev_id = "imx23-dma-apbh", },
-        { .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-        { .dev_id = "duart", .con_id = "apb_pclk"},
-        { .dev_id = "80070000.serial", .con_id = "apb_pclk"},
-        { .dev_id = "imx23-dma-apbx", },
-        { .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp_lookups[] = {
-        { .dev_id = "imx23-mmc.0", },
-        { .dev_id = "imx23-mmc.1", },
-        { .dev_id = "80010000.ssp", },
-        { .dev_id = "80034000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-        { .dev_id = "imx23-fb", },
-        { .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-        { .dev_id = "imx23-gpmi-nand", },
-        { .dev_id = "8000c000.gpmi-nand", },
-};
-
 static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_pix[]  __initconst = { "ref_pix", "ref_xtal", };
@@ -127,6 +90,7 @@ enum imx23_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx23_clk clks_init_on[] __initdata = {
         cpu, hbus, xbus, emi, uart,
@@ -134,6 +98,7 @@ static enum imx23_clk clks_init_on[] __initdata = {
 
 int __init mx23_clocks_init(void)
 {
+        struct device_node *np;
         int i;
 
         clk_misc_init();
@@ -188,14 +153,14 @@ int __init mx23_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
+        if (np) {
+                clk_data.clks = clks;
+                clk_data.clk_num = ARRAY_SIZE(clks);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
+
         clk_register_clkdev(clks[clk32k], NULL, "timrot");
-        clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-        clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-        clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-        clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-        clk_register_clkdevs(clks[ssp], ssp_lookups, ARRAY_SIZE(ssp_lookups));
-        clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-        clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index e3aab67b3eb7..613e76f3758e 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -14,6 +14,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <mach/mx28.h>
 #include "clk.h"
@@ -120,90 +121,6 @@ static void __init clk_misc_init(void)
         writel_relaxed(val, FRAC0);
 }
 
-static struct clk_lookup uart_lookups[] = {
-        { .dev_id = "duart", },
-        { .dev_id = "mxs-auart.0", },
-        { .dev_id = "mxs-auart.1", },
-        { .dev_id = "mxs-auart.2", },
-        { .dev_id = "mxs-auart.3", },
-        { .dev_id = "mxs-auart.4", },
-        { .dev_id = "8006a000.serial", },
-        { .dev_id = "8006c000.serial", },
-        { .dev_id = "8006e000.serial", },
-        { .dev_id = "80070000.serial", },
-        { .dev_id = "80072000.serial", },
-        { .dev_id = "80074000.serial", },
-};
-
-static struct clk_lookup hbus_lookups[] = {
-        { .dev_id = "imx28-dma-apbh", },
-        { .dev_id = "80004000.dma-apbh", },
-};
-
-static struct clk_lookup xbus_lookups[] = {
-        { .dev_id = "duart", .con_id = "apb_pclk"},
-        { .dev_id = "80074000.serial", .con_id = "apb_pclk"},
-        { .dev_id = "imx28-dma-apbx", },
-        { .dev_id = "80024000.dma-apbx", },
-};
-
-static struct clk_lookup ssp0_lookups[] = {
-        { .dev_id = "imx28-mmc.0", },
-        { .dev_id = "80010000.ssp", },
-};
-
-static struct clk_lookup ssp1_lookups[] = {
-        { .dev_id = "imx28-mmc.1", },
-        { .dev_id = "80012000.ssp", },
-};
-
-static struct clk_lookup ssp2_lookups[] = {
-        { .dev_id = "imx28-mmc.2", },
-        { .dev_id = "80014000.ssp", },
-};
-
-static struct clk_lookup ssp3_lookups[] = {
-        { .dev_id = "imx28-mmc.3", },
-        { .dev_id = "80016000.ssp", },
-};
-
-static struct clk_lookup lcdif_lookups[] = {
-        { .dev_id = "imx28-fb", },
-        { .dev_id = "80030000.lcdif", },
-};
-
-static struct clk_lookup gpmi_lookups[] = {
-        { .dev_id = "imx28-gpmi-nand", },
-        { .dev_id = "8000c000.gpmi-nand", },
-};
-
-static struct clk_lookup fec_lookups[] = {
-        { .dev_id = "imx28-fec.0", },
-        { .dev_id = "imx28-fec.1", },
-        { .dev_id = "800f0000.ethernet", },
-        { .dev_id = "800f4000.ethernet", },
-};
-
-static struct clk_lookup can0_lookups[] = {
-        { .dev_id = "flexcan.0", },
-        { .dev_id = "80032000.can", },
-};
-
-static struct clk_lookup can1_lookups[] = {
-        { .dev_id = "flexcan.1", },
-        { .dev_id = "80034000.can", },
-};
-
-static struct clk_lookup saif0_lookups[] = {
-        { .dev_id = "mxs-saif.0", },
-        { .dev_id = "80042000.saif", },
-};
-
-static struct clk_lookup saif1_lookups[] = {
-        { .dev_id = "mxs-saif.1", },
-        { .dev_id = "80046000.saif", },
-};
-
 static const char *sel_cpu[]  __initconst = { "ref_cpu", "ref_xtal", };
 static const char *sel_io0[]  __initconst = { "ref_io0", "ref_xtal", };
 static const char *sel_io1[]  __initconst = { "ref_io1", "ref_xtal", };
@@ -228,6 +145,7 @@ enum imx28_clk {
 };
 
 static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 static enum imx28_clk clks_init_on[] __initdata = {
         cpu, hbus, xbus, emi, uart,
@@ -235,6 +153,7 @@ static enum imx28_clk clks_init_on[] __initdata = {
 
 int __init mx28_clocks_init(void)
 {
+        struct device_node *np;
         int i;
 
         clk_misc_init();
@@ -312,27 +231,15 @@ int __init mx28_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
+        if (np) {
+                clk_data.clks = clks;
+                clk_data.clk_num = ARRAY_SIZE(clks);
+                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        }
+
         clk_register_clkdev(clks[clk32k], NULL, "timrot");
         clk_register_clkdev(clks[enet_out], NULL, "enet_out");
-        clk_register_clkdev(clks[pwm], NULL, "80064000.pwm");
-        clk_register_clkdevs(clks[hbus], hbus_lookups, ARRAY_SIZE(hbus_lookups));
-        clk_register_clkdevs(clks[xbus], xbus_lookups, ARRAY_SIZE(xbus_lookups));
-        clk_register_clkdevs(clks[uart], uart_lookups, ARRAY_SIZE(uart_lookups));
-        clk_register_clkdevs(clks[ssp0], ssp0_lookups, ARRAY_SIZE(ssp0_lookups));
-        clk_register_clkdevs(clks[ssp1], ssp1_lookups, ARRAY_SIZE(ssp1_lookups));
-        clk_register_clkdevs(clks[ssp2], ssp2_lookups, ARRAY_SIZE(ssp2_lookups));
-        clk_register_clkdevs(clks[ssp3], ssp3_lookups, ARRAY_SIZE(ssp3_lookups));
-        clk_register_clkdevs(clks[gpmi], gpmi_lookups, ARRAY_SIZE(gpmi_lookups));
-        clk_register_clkdevs(clks[saif0], saif0_lookups, ARRAY_SIZE(saif0_lookups));
-        clk_register_clkdevs(clks[saif1], saif1_lookups, ARRAY_SIZE(saif1_lookups));
-        clk_register_clkdevs(clks[lcdif], lcdif_lookups, ARRAY_SIZE(lcdif_lookups));
-        clk_register_clkdevs(clks[fec], fec_lookups, ARRAY_SIZE(fec_lookups));
-        clk_register_clkdevs(clks[can0], can0_lookups, ARRAY_SIZE(can0_lookups));
-        clk_register_clkdevs(clks[can1], can1_lookups, ARRAY_SIZE(can1_lookups));
-        clk_register_clkdev(clks[usb0_pwr], NULL, "8007c000.usbphy");
-        clk_register_clkdev(clks[usb1_pwr], NULL, "8007e000.usbphy");
-        clk_register_clkdev(clks[usb0], NULL, "80080000.usb");
-        clk_register_clkdev(clks[usb1], NULL, "80090000.usb");
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index ba7926f5c099..a00b828b1643 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -183,6 +183,12 @@ config GPIO_STA2X11
           Say yes here to support the STA2x11/ConneXt GPIO device.
           The GPIO module has 128 GPIO pins with alternate functions.
 
+config GPIO_VT8500
+        bool "VIA/Wondermedia SoC GPIO Support"
+        depends on ARCH_VT8500
+        help
+          Say yes here to support the VT8500/WM8505/WM8650 GPIO controller.
+
 config GPIO_XILINX
         bool "Xilinx GPIO support"
         depends on PPC_OF || MICROBLAZE
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 153caceeb053..a288142ad998 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_GPIO_TPS65912)	+= gpio-tps65912.o
 obj-$(CONFIG_GPIO_TWL4030)      += gpio-twl4030.o
 obj-$(CONFIG_GPIO_UCB1400)      += gpio-ucb1400.o
 obj-$(CONFIG_GPIO_VR41XX)       += gpio-vr41xx.o
+obj-$(CONFIG_GPIO_VT8500)       += gpio-vt8500.o
 obj-$(CONFIG_GPIO_VX855)        += gpio-vx855.o
 obj-$(CONFIG_GPIO_WM831X)       += gpio-wm831x.o
 obj-$(CONFIG_GPIO_WM8350)       += gpio-wm8350.o
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 9cac88a65f78..9528779ca463 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -26,6 +26,8 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/irqs.h>
 
 /*
@@ -59,6 +61,7 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 
 int pxa_last_gpio;
+static int irq_base;
 
 #ifdef CONFIG_OF
 static struct irq_domain *domain;
@@ -167,63 +170,14 @@ static inline int __gpio_is_occupied(unsigned gpio)
         return ret;
 }
 
-#ifdef CONFIG_ARCH_PXA
-static inline int __pxa_gpio_to_irq(int gpio)
-{
-        if (gpio_is_pxa_type(gpio_type))
-                return PXA_GPIO_TO_IRQ(gpio);
-        return -1;
-}
-
-static inline int __pxa_irq_to_gpio(int irq)
-{
-        if (gpio_is_pxa_type(gpio_type))
-                return irq - PXA_GPIO_TO_IRQ(0);
-        return -1;
-}
-#else
-static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
-static inline int __pxa_irq_to_gpio(int irq) { return -1; }
-#endif
-
-#ifdef CONFIG_ARCH_MMP
-static inline int __mmp_gpio_to_irq(int gpio)
-{
-        if (gpio_is_mmp_type(gpio_type))
-                return MMP_GPIO_TO_IRQ(gpio);
-        return -1;
-}
-
-static inline int __mmp_irq_to_gpio(int irq)
-{
-        if (gpio_is_mmp_type(gpio_type))
-                return irq - MMP_GPIO_TO_IRQ(0);
-        return -1;
-}
-#else
-static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
-static inline int __mmp_irq_to_gpio(int irq) { return -1; }
-#endif
-
 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
-        int gpio, ret;
-
-        gpio = chip->base + offset;
-        ret = __pxa_gpio_to_irq(gpio);
-        if (ret >= 0)
-                return ret;
-        return __mmp_gpio_to_irq(gpio);
+        return chip->base + offset + irq_base;
 }
 
 int pxa_irq_to_gpio(int irq)
 {
-        int ret;
-
-        ret = __pxa_irq_to_gpio(irq);
-        if (ret >= 0)
-                return ret;
-        return __mmp_irq_to_gpio(irq);
+        return irq - irq_base;
 }
 
 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@@ -403,6 +357,9 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
         struct pxa_gpio_chip *c;
         int loop, gpio, gpio_base, n;
         unsigned long gedr;
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+
+        chained_irq_enter(chip, desc);
 
         do {
                 loop = 0;
@@ -422,6 +379,8 @@ static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
                         }
                 }
         } while (loop);
+
+        chained_irq_exit(chip, desc);
 }
 
 static void pxa_ack_muxed_gpio(struct irq_data *d)
@@ -535,7 +494,7 @@ const struct irq_domain_ops pxa_irq_domain_ops = {
 
 static int __devinit pxa_gpio_probe_dt(struct platform_device *pdev)
 {
-        int ret, nr_banks, nr_gpios, irq_base;
+        int ret, nr_banks, nr_gpios;
         struct device_node *prev, *next, *np = pdev->dev.of_node;
         const struct of_device_id *of_id =
                                 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
@@ -590,10 +549,20 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
         int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
 
         ret = pxa_gpio_probe_dt(pdev);
-        if (ret < 0)
+        if (ret < 0) {
                 pxa_last_gpio = pxa_gpio_nums();
-        else
+#ifdef CONFIG_ARCH_PXA
+                if (gpio_is_pxa_type(gpio_type))
+                        irq_base = PXA_GPIO_TO_IRQ(0);
+#endif
+#ifdef CONFIG_ARCH_MMP
+                if (gpio_is_mmp_type(gpio_type))
+                        irq_base = MMP_GPIO_TO_IRQ(0);
+#endif
+        } else {
                 use_of = 1;
+        }
+
         if (!pxa_last_gpio)
                 return -EINVAL;
 
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 1c169324e357..8af4b06e80f7 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -938,6 +938,67 @@ static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
                 s3c_gpiolib_track(chip);
 }
 
+#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
+static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
+                        const struct of_phandle_args *gpiospec, u32 *flags)
+{
+        unsigned int pin;
+
+        if (WARN_ON(gc->of_gpio_n_cells < 3))
+                return -EINVAL;
+
+        if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
+                return -EINVAL;
+
+        if (gpiospec->args[0] > gc->ngpio)
+                return -EINVAL;
+
+        pin = gc->base + gpiospec->args[0];
+
+        if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
+                pr_warn("gpio_xlate: failed to set pin function\n");
+        if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
+                pr_warn("gpio_xlate: failed to set pin pull up/down\n");
+
+        if (flags)
+                *flags = gpiospec->args[2] >> 16;
+
+        return gpiospec->args[0];
+}
+
+static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
+        { .compatible = "samsung,s3c24xx-gpio", },
+        {}
+};
+
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        struct gpio_chip *gc =  &chip->chip;
+        u64 address;
+
+        if (!of_have_populated_dt())
+                return;
+
+        address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
+        gc->of_node = of_find_matching_node_by_address(NULL,
+                        s3c24xx_gpio_dt_match, address);
+        if (!gc->of_node) {
+                pr_info("gpio: device tree node not found for gpio controller"
+                        " with base address %08llx\n", address);
+                return;
+        }
+        gc->of_gpio_n_cells = 3;
+        gc->of_xlate = s3c24xx_gpio_xlate;
+}
+#else
+static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
+                                                 u64 base, u64 offset)
+{
+        return;
+}
+#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
+
 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
                                              int nr_chips, void __iomem *base)
 {
@@ -962,6 +1023,8 @@ static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
                         gc->direction_output = samsung_gpiolib_2bit_output;
 
                 samsung_gpiolib_add(chip);
+
+                s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
         }
 }
 
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index f030880bc9bb..c5f8ca233e1f 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -396,6 +396,29 @@ static int __devinit gpio_twl4030_debounce(u32 debounce, u8 mmc_cd)
 
 static int gpio_twl4030_remove(struct platform_device *pdev);
 
+static struct twl4030_gpio_platform_data *of_gpio_twl4030(struct device *dev)
+{
+        struct twl4030_gpio_platform_data *omap_twl_info;
+
+        omap_twl_info = devm_kzalloc(dev, sizeof(*omap_twl_info), GFP_KERNEL);
+        if (!omap_twl_info)
+                return NULL;
+
+        omap_twl_info->use_leds = of_property_read_bool(dev->of_node,
+                        "ti,use-leds");
+
+        of_property_read_u32(dev->of_node, "ti,debounce",
+                             &omap_twl_info->debounce);
+        of_property_read_u32(dev->of_node, "ti,mmc-cd",
+                             (u32 *)&omap_twl_info->mmc_cd);
+        of_property_read_u32(dev->of_node, "ti,pullups",
+                             &omap_twl_info->pullups);
+        of_property_read_u32(dev->of_node, "ti,pulldowns",
+                             &omap_twl_info->pulldowns);
+
+        return omap_twl_info;
+}
+
 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
 {
         struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
@@ -428,33 +451,37 @@ no_irqs:
         twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
         twl_gpiochip.dev = &pdev->dev;
 
-        if (pdata) {
-                /*
-                 * NOTE:  boards may waste power if they don't set pullups
-                 * and pulldowns correctly ... default for non-ULPI pins is
-                 * pulldown, and some other pins may have external pullups
-                 * or pulldowns.  Careful!
-                 */
-                ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
-                if (ret)
-                        dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
-                                        pdata->pullups, pdata->pulldowns,
-                                        ret);
-
-                ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
-                if (ret)
-                        dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
-                                        pdata->debounce, pdata->mmc_cd,
-                                        ret);
-
-                /*
-                 * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
-                 * is (still) clear if use_leds is set.
-                 */
-                if (pdata->use_leds)
-                        twl_gpiochip.ngpio += 2;
+        if (node)
+                pdata = of_gpio_twl4030(&pdev->dev);
+
+        if (pdata == NULL) {
+                dev_err(&pdev->dev, "Platform data is missing\n");
+                return -ENXIO;
         }
 
+        /*
+         * NOTE:  boards may waste power if they don't set pullups
+         * and pulldowns correctly ... default for non-ULPI pins is
+         * pulldown, and some other pins may have external pullups
+         * or pulldowns.  Careful!
+         */
+        ret = gpio_twl4030_pulls(pdata->pullups, pdata->pulldowns);
+        if (ret)
+                dev_dbg(&pdev->dev, "pullups %.05x %.05x --> %d\n",
+                        pdata->pullups, pdata->pulldowns, ret);
+
+        ret = gpio_twl4030_debounce(pdata->debounce, pdata->mmc_cd);
+        if (ret)
+                dev_dbg(&pdev->dev, "debounce %.03x %.01x --> %d\n",
+                        pdata->debounce, pdata->mmc_cd, ret);
+
+        /*
+         * NOTE: we assume VIBRA_CTL.VIBRA_EN, in MODULE_AUDIO_VOICE,
+         * is (still) clear if use_leds is set.
+         */
+        if (pdata->use_leds)
+                twl_gpiochip.ngpio += 2;
+
         ret = gpiochip_add(&twl_gpiochip);
         if (ret < 0) {
                 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
diff --git a/drivers/gpio/gpio-vt8500.c b/drivers/gpio/gpio-vt8500.c
new file mode 100644
index 000000000000..bcd8e4aa7c7d
--- /dev/null
+++ b/drivers/gpio/gpio-vt8500.c
@@ -0,0 +1,316 @@
+/* drivers/gpio/gpio-vt8500.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ * Based on arch/arm/mach-vt8500/gpio.c:
+ * - Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+
+/*
+        We handle GPIOs by bank, each bank containing up to 32 GPIOs covered
+        by one set of registers (although not all may be valid).
+
+        Because different SoC's have different register offsets, we pass the
+        register offsets as data in vt8500_gpio_dt_ids[].
+
+        A value of NO_REG is used to indicate that this register is not
+        supported. Only used for ->en at the moment.
+*/
+
+#define NO_REG  0xFFFF
+
+/*
+ * struct vt8500_gpio_bank_regoffsets
+ * @en: offset to enable register of the bank
+ * @dir: offset to direction register of the bank
+ * @data_out: offset to the data out register of the bank
+ * @data_in: offset to the data in register of the bank
+ * @ngpio: highest valid pin in this bank
+ */
+
+struct vt8500_gpio_bank_regoffsets {
+        unsigned int    en;
+        unsigned int    dir;
+        unsigned int    data_out;
+        unsigned int    data_in;
+        unsigned char   ngpio;
+};
+
+struct vt8500_gpio_data {
+        unsigned int                            num_banks;
+        struct vt8500_gpio_bank_regoffsets      banks[];
+};
+
+#define VT8500_BANK(__en, __dir, __out, __in, __ngpio)          \
+{                                                               \
+        .en = __en,                                             \
+        .dir = __dir,                                           \
+        .data_out = __out,                                      \
+        .data_in = __in,                                        \
+        .ngpio = __ngpio,                                       \
+}
+
+static struct vt8500_gpio_data vt8500_data = {
+        .num_banks      = 7,
+        .banks  = {
+                VT8500_BANK(0x00, 0x20, 0x40, 0x60, 26),
+                VT8500_BANK(0x04, 0x24, 0x44, 0x64, 28),
+                VT8500_BANK(0x08, 0x28, 0x48, 0x68, 31),
+                VT8500_BANK(0x0C, 0x2C, 0x4C, 0x6C, 19),
+                VT8500_BANK(0x10, 0x30, 0x50, 0x70, 19),
+                VT8500_BANK(0x14, 0x34, 0x54, 0x74, 23),
+                VT8500_BANK(NO_REG, 0x3C, 0x5C, 0x7C, 9),
+        },
+};
+
+static struct vt8500_gpio_data wm8505_data = {
+        .num_banks      = 10,
+        .banks  = {
+                VT8500_BANK(0x40, 0x68, 0x90, 0xB8, 8),
+                VT8500_BANK(0x44, 0x6C, 0x94, 0xBC, 32),
+                VT8500_BANK(0x48, 0x70, 0x98, 0xC0, 6),
+                VT8500_BANK(0x4C, 0x74, 0x9C, 0xC4, 16),
+                VT8500_BANK(0x50, 0x78, 0xA0, 0xC8, 25),
+                VT8500_BANK(0x54, 0x7C, 0xA4, 0xCC, 5),
+                VT8500_BANK(0x58, 0x80, 0xA8, 0xD0, 5),
+                VT8500_BANK(0x5C, 0x84, 0xAC, 0xD4, 12),
+                VT8500_BANK(0x60, 0x88, 0xB0, 0xD8, 16),
+                VT8500_BANK(0x64, 0x8C, 0xB4, 0xDC, 22),
+        },
+};
+
+/*
+ * No information about which bits are valid so we just make
+ * them all available until its figured out.
+ */
+static struct vt8500_gpio_data wm8650_data = {
+        .num_banks      = 9,
+        .banks  = {
+                VT8500_BANK(0x40, 0x80, 0xC0, 0x00, 32),
+                VT8500_BANK(0x44, 0x84, 0xC4, 0x04, 32),
+                VT8500_BANK(0x48, 0x88, 0xC8, 0x08, 32),
+                VT8500_BANK(0x4C, 0x8C, 0xCC, 0x0C, 32),
+                VT8500_BANK(0x50, 0x90, 0xD0, 0x10, 32),
+                VT8500_BANK(0x54, 0x94, 0xD4, 0x14, 32),
+                VT8500_BANK(0x58, 0x98, 0xD8, 0x18, 32),
+                VT8500_BANK(0x5C, 0x9C, 0xDC, 0x1C, 32),
+                VT8500_BANK(0x7C, 0xBC, 0xFC, 0x3C, 32),
+        },
+};
+
+struct vt8500_gpio_chip {
+        struct gpio_chip                chip;
+
+        const struct vt8500_gpio_bank_regoffsets *regs;
+        void __iomem    *base;
+};
+
+
+#define to_vt8500(__chip) container_of(__chip, struct vt8500_gpio_chip, chip)
+
+static int vt8500_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        u32 val;
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+        if (vt8500_chip->regs->en == NO_REG)
+                return 0;
+
+        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
+        val |= BIT(offset);
+        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
+
+        return 0;
+}
+
+static void vt8500_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+        u32 val;
+
+        if (vt8500_chip->regs->en == NO_REG)
+                return;
+
+        val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->en);
+        val &= ~BIT(offset);
+        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->en);
+}
+
+static int vt8500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
+        val &= ~BIT(offset);
+        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+        return 0;
+}
+
+static int vt8500_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+                                                                int value)
+{
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+        u32 val = readl_relaxed(vt8500_chip->base + vt8500_chip->regs->dir);
+        val |= BIT(offset);
+        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->dir);
+
+        if (value) {
+                val = readl_relaxed(vt8500_chip->base +
+                                                vt8500_chip->regs->data_out);
+                val |= BIT(offset);
+                writel_relaxed(val, vt8500_chip->base +
+                                                vt8500_chip->regs->data_out);
+        }
+        return 0;
+}
+
+static int vt8500_gpio_get_value(struct gpio_chip *chip, unsigned offset)
+{
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+        return (readl_relaxed(vt8500_chip->base + vt8500_chip->regs->data_in) >>
+                                                                offset) & 1;
+}
+
+static void vt8500_gpio_set_value(struct gpio_chip *chip, unsigned offset,
+                                                                int value)
+{
+        struct vt8500_gpio_chip *vt8500_chip = to_vt8500(chip);
+
+        u32 val = readl_relaxed(vt8500_chip->base +
+                                                vt8500_chip->regs->data_out);
+        if (value)
+                val |= BIT(offset);
+        else
+                val &= ~BIT(offset);
+
+        writel_relaxed(val, vt8500_chip->base + vt8500_chip->regs->data_out);
+}
+
+static int vt8500_of_xlate(struct gpio_chip *gc,
+                            const struct of_phandle_args *gpiospec, u32 *flags)
+{
+        /* bank if specificed in gpiospec->args[0] */
+        if (flags)
+                *flags = gpiospec->args[2];
+
+        return gpiospec->args[1];
+}
+
+static int vt8500_add_chips(struct platform_device *pdev, void __iomem *base,
+                                const struct vt8500_gpio_data *data)
+{
+        struct vt8500_gpio_chip *vtchip;
+        struct gpio_chip *chip;
+        int i;
+        int pin_cnt = 0;
+
+        vtchip = devm_kzalloc(&pdev->dev,
+                        sizeof(struct vt8500_gpio_chip) * data->num_banks,
+                        GFP_KERNEL);
+        if (!vtchip) {
+                pr_err("%s: failed to allocate chip memory\n", __func__);
+                return -ENOMEM;
+        }
+
+        for (i = 0; i < data->num_banks; i++) {
+                vtchip[i].base = base;
+                vtchip[i].regs = &data->banks[i];
+
+                chip = &vtchip[i].chip;
+
+                chip->of_xlate = vt8500_of_xlate;
+                chip->of_gpio_n_cells = 3;
+                chip->of_node = pdev->dev.of_node;
+
+                chip->request = vt8500_gpio_request;
+                chip->free = vt8500_gpio_free;
+                chip->direction_input = vt8500_gpio_direction_input;
+                chip->direction_output = vt8500_gpio_direction_output;
+                chip->get = vt8500_gpio_get_value;
+                chip->set = vt8500_gpio_set_value;
+                chip->can_sleep = 0;
+                chip->base = pin_cnt;
+                chip->ngpio = data->banks[i].ngpio;
+
+                pin_cnt += data->banks[i].ngpio;
+
+                gpiochip_add(chip);
+        }
+        return 0;
+}
+
+static struct of_device_id vt8500_gpio_dt_ids[] = {
+        { .compatible = "via,vt8500-gpio", .data = &vt8500_data, },
+        { .compatible = "wm,wm8505-gpio", .data = &wm8505_data, },
+        { .compatible = "wm,wm8650-gpio", .data = &wm8650_data, },
+        { /* Sentinel */ },
+};
+
+static int __devinit vt8500_gpio_probe(struct platform_device *pdev)
+{
+        void __iomem *gpio_base;
+        struct device_node *np;
+        const struct of_device_id *of_id =
+                                of_match_device(vt8500_gpio_dt_ids, &pdev->dev);
+
+        if (!of_id) {
+                dev_err(&pdev->dev, "Failed to find gpio controller\n");
+                return -ENODEV;
+        }
+
+        np = pdev->dev.of_node;
+        if (!np) {
+                dev_err(&pdev->dev, "Missing GPIO description in devicetree\n");
+                return -EFAULT;
+        }
+
+        gpio_base = of_iomap(np, 0);
+        if (!gpio_base) {
+                dev_err(&pdev->dev, "Unable to map GPIO registers\n");
+                of_node_put(np);
+                return -ENOMEM;
+        }
+
+        vt8500_add_chips(pdev, gpio_base, of_id->data);
+
+        return 0;
+}
+
+static struct platform_driver vt8500_gpio_driver = {
+        .probe          = vt8500_gpio_probe,
+        .driver         = {
+                .name   = "vt8500-gpio",
+                .owner  = THIS_MODULE,
+                .of_match_table = vt8500_gpio_dt_ids,
+        },
+};
+
+module_platform_driver(vt8500_gpio_driver);
+
+MODULE_DESCRIPTION("VT8500 GPIO Driver");
+MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, vt8500_gpio_dt_ids);
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 252aaefcacfa..d944d6ef7da8 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -22,6 +22,8 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <mach/dma.h>
 #include <plat/pxa3xx_nand.h>
@@ -1032,7 +1034,7 @@ static int alloc_nand_resource(struct platform_device *pdev)
         struct pxa3xx_nand_platform_data *pdata;
         struct pxa3xx_nand_info *info;
         struct pxa3xx_nand_host *host;
-        struct nand_chip *chip;
+        struct nand_chip *chip = NULL;
         struct mtd_info *mtd;
         struct resource *r;
         int ret, irq, cs;
@@ -1081,21 +1083,31 @@ static int alloc_nand_resource(struct platform_device *pdev)
         }
         clk_enable(info->clk);
 
-        r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no resource defined for data DMA\n");
-                ret = -ENXIO;
-                goto fail_put_clk;
-        }
-        info->drcmr_dat = r->start;
+        /*
+         * This is a dirty hack to make this driver work from devicetree
+         * bindings. It can be removed once we have a prober DMA controller
+         * framework for DT.
+         */
+        if (pdev->dev.of_node && cpu_is_pxa3xx()) {
+                info->drcmr_dat = 97;
+                info->drcmr_cmd = 99;
+        } else {
+                r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+                if (r == NULL) {
+                        dev_err(&pdev->dev, "no resource defined for data DMA\n");
+                        ret = -ENXIO;
+                        goto fail_put_clk;
+                }
+                info->drcmr_dat = r->start;
 
-        r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no resource defined for command DMA\n");
-                ret = -ENXIO;
-                goto fail_put_clk;
+                r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+                if (r == NULL) {
+                        dev_err(&pdev->dev, "no resource defined for command DMA\n");
+                        ret = -ENXIO;
+                        goto fail_put_clk;
+                }
+                info->drcmr_cmd = r->start;
         }
-        info->drcmr_cmd = r->start;
 
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
@@ -1200,12 +1212,55 @@ static int pxa3xx_nand_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pxa3xx_nand_dt_ids[] = {
+        { .compatible = "marvell,pxa3xx-nand" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
+
+static int pxa3xx_nand_probe_dt(struct platform_device *pdev)
+{
+        struct pxa3xx_nand_platform_data *pdata;
+        struct device_node *np = pdev->dev.of_node;
+        const struct of_device_id *of_id =
+                        of_match_device(pxa3xx_nand_dt_ids, &pdev->dev);
+
+        if (!of_id)
+                return 0;
+
+        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+        if (!pdata)
+                return -ENOMEM;
+
+        if (of_get_property(np, "marvell,nand-enable-arbiter", NULL))
+                pdata->enable_arbiter = 1;
+        if (of_get_property(np, "marvell,nand-keep-config", NULL))
+                pdata->keep_config = 1;
+        of_property_read_u32(np, "num-cs", &pdata->num_cs);
+
+        pdev->dev.platform_data = pdata;
+
+        return 0;
+}
+#else
+static inline int pxa3xx_nand_probe_dt(struct platform_device *pdev)
+{
+        return 0;
+}
+#endif
+
 static int pxa3xx_nand_probe(struct platform_device *pdev)
 {
         struct pxa3xx_nand_platform_data *pdata;
+        struct mtd_part_parser_data ppdata = {};
         struct pxa3xx_nand_info *info;
         int ret, cs, probe_success;
 
+        ret = pxa3xx_nand_probe_dt(pdev);
+        if (ret)
+                return ret;
+
         pdata = pdev->dev.platform_data;
         if (!pdata) {
                 dev_err(&pdev->dev, "no platform data defined\n");
@@ -1229,8 +1284,9 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
                         continue;
                 }
 
+                ppdata.of_node = pdev->dev.of_node;
                 ret = mtd_device_parse_register(info->host[cs]->mtd, NULL,
-                                                NULL, pdata->parts[cs],
+                                                &ppdata, pdata->parts[cs],
                                                 pdata->nr_parts[cs]);
                 if (!ret)
                         probe_success = 1;
@@ -1306,6 +1362,7 @@ static int pxa3xx_nand_resume(struct platform_device *pdev)
 static struct platform_driver pxa3xx_nand_driver = {
         .driver = {
                 .name   = "pxa3xx-nand",
+                .of_match_table = of_match_ptr(pxa3xx_nand_dt_ids),
         },
         .probe          = pxa3xx_nand_probe,
         .remove         = pxa3xx_nand_remove,
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index 7fca6ce5952b..304360cd213e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -17,6 +17,7 @@
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -916,11 +917,66 @@ static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s
         seq_printf(s, " " DRIVER_NAME);
 }
 
+static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                 struct device_node *np_config,
+                                 struct pinctrl_map **map, unsigned *num_maps)
+{
+        struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
+        struct device_node *np;
+        struct property *prop;
+        const char *function, *group;
+        int ret, index = 0, count = 0;
+
+        /* calculate number of maps required */
+        for_each_child_of_node(np_config, np) {
+                ret = of_property_read_string(np, "sirf,function", &function);
+                if (ret < 0)
+                        return ret;
+
+                ret = of_property_count_strings(np, "sirf,pins");
+                if (ret < 0)
+                        return ret;
+
+                count += ret;
+        }
+
+        if (!count) {
+                dev_err(spmx->dev, "No child nodes passed via DT\n");
+                return -ENODEV;
+        }
+
+        *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
+        if (!*map)
+                return -ENOMEM;
+
+        for_each_child_of_node(np_config, np) {
+                of_property_read_string(np, "sirf,function", &function);
+                of_property_for_each_string(np, "sirf,pins", prop, group) {
+                        (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
+                        (*map)[index].data.mux.group = group;
+                        (*map)[index].data.mux.function = function;
+                        index++;
+                }
+        }
+
+        *num_maps = count;
+
+        return 0;
+}
+
+static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
+                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
 static struct pinctrl_ops sirfsoc_pctrl_ops = {
         .get_groups_count = sirfsoc_get_groups_count,
         .get_group_name = sirfsoc_get_group_name,
         .get_group_pins = sirfsoc_get_group_pins,
         .pin_dbg_show = sirfsoc_pin_dbg_show,
+        .dt_node_to_map = sirfsoc_dt_node_to_map,
+        .dt_free_map = sirfsoc_dt_free_map,
 };
 
 struct sirfsoc_pmx_func {
@@ -1221,7 +1277,7 @@ out_no_gpio_remap:
 }
 
 static const struct of_device_id pinmux_ids[] __devinitconst = {
-        { .compatible = "sirf,prima2-gpio-pinmux" },
+        { .compatible = "sirf,prima2-pinctrl" },
         {}
 };
 
diff --git a/drivers/rtc/rtc-ab8500.c b/drivers/rtc/rtc-ab8500.c
index bf3c2f669c3c..2e5970fe9eeb 100644
--- a/drivers/rtc/rtc-ab8500.c
+++ b/drivers/rtc/rtc-ab8500.c
@@ -462,16 +462,10 @@ static int __devexit ab8500_rtc_remove(struct platform_device *pdev)
         return 0;
 }
 
-static const struct of_device_id ab8500_rtc_match[] = {
-        { .compatible = "stericsson,ab8500-rtc", },
-        {}
-};
-
 static struct platform_driver ab8500_rtc_driver = {
         .driver = {
                 .name = "ab8500-rtc",
                 .owner = THIS_MODULE,
-                .of_match_table = ab8500_rtc_match,
         },
         .probe  = ab8500_rtc_probe,
         .remove = __devexit_p(ab8500_rtc_remove),
diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index 0075c8fd93d8..f771b2ee4b18 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -27,6 +27,8 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
 
 #include <mach/hardware.h>
 
@@ -396,6 +398,14 @@ static int __exit pxa_rtc_remove(struct platform_device *pdev)
         return 0;
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id pxa_rtc_dt_ids[] = {
+        { .compatible = "marvell,pxa-rtc" },
+        {}
+};
+MODULE_DEVICE_TABLE(of, pxa_rtc_dt_ids);
+#endif
+
 #ifdef CONFIG_PM
 static int pxa_rtc_suspend(struct device *dev)
 {
@@ -425,6 +435,7 @@ static struct platform_driver pxa_rtc_driver = {
         .remove         = __exit_p(pxa_rtc_remove),
         .driver         = {
                 .name   = "pxa-rtc",
+                .of_match_table = of_match_ptr(pxa_rtc_dt_ids),
 #ifdef CONFIG_PM
                 .pm     = &pxa_rtc_pm_ops,
 #endif
diff --git a/drivers/rtc/rtc-vt8500.c b/drivers/rtc/rtc-vt8500.c
index 9e94fb147c26..07bf19364a74 100644
--- a/drivers/rtc/rtc-vt8500.c
+++ b/drivers/rtc/rtc-vt8500.c
@@ -23,6 +23,7 @@
 #include <linux/bcd.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 /*
  * Register definitions
@@ -302,12 +303,18 @@ static int __devexit vt8500_rtc_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+        { .compatible = "via,vt8500-rtc", },
+        {}
+};
+
 static struct platform_driver vt8500_rtc_driver = {
         .probe          = vt8500_rtc_probe,
         .remove         = __devexit_p(vt8500_rtc_remove),
         .driver         = {
                 .name   = "vt8500-rtc",
                 .owner  = THIS_MODULE,
+                .of_match_table = of_match_ptr(wmt_dt_ids),
         },
 };
 
@@ -315,5 +322,5 @@ module_platform_driver(vt8500_rtc_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
 MODULE_DESCRIPTION("VIA VT8500 SoC Realtime Clock Driver (RTC)");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
 MODULE_ALIAS("platform:vt8500-rtc");
diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 2be006fb3da0..205d4cf4a063 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/platform_device.h>
+#include <linux/of.h>
 
 /*
  * UART Register offsets
@@ -76,6 +77,8 @@
 #define RX_FIFO_INTS    (RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
 #define TX_FIFO_INTS    (TXFAE | TXFE | TXUDR)
 
+#define VT8500_MAX_PORTS        6
+
 struct vt8500_port {
         struct uart_port        uart;
         char                    name[16];
@@ -83,6 +86,13 @@ struct vt8500_port {
         unsigned int            ier;
 };
 
+/*
+ * we use this variable to keep track of which ports
+ * have been allocated as we can't use pdev->id in
+ * devicetree
+ */
+static unsigned long vt8500_ports_in_use;
+
 static inline void vt8500_write(struct uart_port *port, unsigned int val,
                              unsigned int off)
 {
@@ -431,7 +441,7 @@ static int vt8500_verify_port(struct uart_port *port,
         return 0;
 }
 
-static struct vt8500_port *vt8500_uart_ports[4];
+static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
 static struct uart_driver vt8500_uart_driver;
 
 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
@@ -548,7 +558,9 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
 {
         struct vt8500_port *vt8500_port;
         struct resource *mmres, *irqres;
+        struct device_node *np = pdev->dev.of_node;
         int ret;
+        int port;
 
         mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -559,16 +571,46 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
         if (!vt8500_port)
                 return -ENOMEM;
 
+        if (np)
+                port = of_alias_get_id(np, "serial");
+                if (port > VT8500_MAX_PORTS)
+                        port = -1;
+        else
+                port = -1;
+
+        if (port < 0) {
+                /* calculate the port id */
+                port = find_first_zero_bit(&vt8500_ports_in_use,
+                                        sizeof(vt8500_ports_in_use));
+        }
+
+        if (port > VT8500_MAX_PORTS)
+                return -ENODEV;
+
+        /* reserve the port id */
+        if (test_and_set_bit(port, &vt8500_ports_in_use)) {
+                /* port already in use - shouldn't really happen */
+                return -EBUSY;
+        }
+
         vt8500_port->uart.type = PORT_VT8500;
         vt8500_port->uart.iotype = UPIO_MEM;
         vt8500_port->uart.mapbase = mmres->start;
         vt8500_port->uart.irq = irqres->start;
         vt8500_port->uart.fifosize = 16;
         vt8500_port->uart.ops = &vt8500_uart_pops;
-        vt8500_port->uart.line = pdev->id;
+        vt8500_port->uart.line = port;
         vt8500_port->uart.dev = &pdev->dev;
         vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
-        vt8500_port->uart.uartclk = 24000000;
+
+        vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
+        if (vt8500_port->clk) {
+                vt8500_port->uart.uartclk = clk_get_rate(vt8500_port->clk);
+        } else {
+                /* use the default of 24Mhz if not specified and warn */
+                pr_warn("%s: serial clock source not specified\n", __func__);
+                vt8500_port->uart.uartclk = 24000000;
+        }
 
         snprintf(vt8500_port->name, sizeof(vt8500_port->name),
                  "VT8500 UART%d", pdev->id);
@@ -579,7 +621,7 @@ static int __devinit vt8500_serial_probe(struct platform_device *pdev)
                 goto err;
         }
 
-        vt8500_uart_ports[pdev->id] = vt8500_port;
+        vt8500_uart_ports[port] = vt8500_port;
 
         uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
 
@@ -603,12 +645,18 @@ static int __devexit vt8500_serial_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+        { .compatible = "via,vt8500-uart", },
+        {}
+};
+
 static struct platform_driver vt8500_platform_driver = {
         .probe  = vt8500_serial_probe,
         .remove = __devexit_p(vt8500_serial_remove),
         .driver = {
                 .name = "vt8500_serial",
                 .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(wmt_dt_ids),
         },
 };
 
@@ -642,4 +690,4 @@ module_exit(vt8500_serial_exit);
 
 MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
 MODULE_DESCRIPTION("Driver for vt8500 serial device");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0217f7415ef5..b66d951b8e32 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1788,7 +1788,7 @@ config FB_AU1200
 
 config FB_VT8500
         bool "VT8500 LCD Driver"
-        depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_VT8500
+        depends on (FB = y) && ARM && ARCH_VT8500
         select FB_WMT_GE_ROPS
         select FB_SYS_IMAGEBLIT
         help
@@ -1797,11 +1797,11 @@ config FB_VT8500
 
 config FB_WM8505
         bool "WM8505 frame buffer support"
-        depends on (FB = y) && ARM && ARCH_VT8500 && VTWM_VERSION_WM8505
+        depends on (FB = y) && ARM && ARCH_VT8500
         select FB_WMT_GE_ROPS
         select FB_SYS_IMAGEBLIT
         help
-          This is the framebuffer driver for WonderMedia WM8505
+          This is the framebuffer driver for WonderMedia WM8505/WM8650
           integrated LCD controller.
 
 source "drivers/video/geode/Kconfig"
diff --git a/drivers/video/vt8500lcdfb.c b/drivers/video/vt8500lcdfb.c
index 2a5fe6ede845..d24595cd0c9b 100644
--- a/drivers/video/vt8500lcdfb.c
+++ b/drivers/video/vt8500lcdfb.c
@@ -35,6 +35,13 @@
 #include "vt8500lcdfb.h"
 #include "wmt_ge_rops.h"
 
+#ifdef CONFIG_OF
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
+#endif
+
+
 #define to_vt8500lcd_info(__info) container_of(__info, \
                                                 struct vt8500lcd_info, fb)
 
@@ -270,15 +277,21 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
 {
         struct vt8500lcd_info *fbi;
         struct resource *res;
-        struct vt8500fb_platform_data *pdata = pdev->dev.platform_data;
         void *addr;
         int irq, ret;
 
+        struct fb_videomode     of_mode;
+        struct device_node      *np;
+        u32                     bpp;
+        dma_addr_t fb_mem_phys;
+        unsigned long fb_mem_len;
+        void *fb_mem_virt;
+
         ret = -ENOMEM;
         fbi = NULL;
 
-        fbi = kzalloc(sizeof(struct vt8500lcd_info) + sizeof(u32) * 16,
-                                                        GFP_KERNEL);
+        fbi = devm_kzalloc(&pdev->dev, sizeof(struct vt8500lcd_info)
+                        + sizeof(u32) * 16, GFP_KERNEL);
         if (!fbi) {
                 dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
                 ret = -ENOMEM;
@@ -333,9 +346,45 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
                 goto failed_free_res;
         }
 
-        fbi->fb.fix.smem_start  = pdata->video_mem_phys;
-        fbi->fb.fix.smem_len    = pdata->video_mem_len;
-        fbi->fb.screen_base     = pdata->video_mem_virt;
+        np = of_parse_phandle(pdev->dev.of_node, "default-mode", 0);
+        if (!np) {
+                pr_err("%s: No display description in Device Tree\n", __func__);
+                ret = -EINVAL;
+                goto failed_free_res;
+        }
+
+        /*
+         * This code is copied from Sascha Hauer's of_videomode helper
+         * and can be replaced with a call to the helper once mainlined
+         */
+        ret = 0;
+        ret |= of_property_read_u32(np, "hactive", &of_mode.xres);
+        ret |= of_property_read_u32(np, "vactive", &of_mode.yres);
+        ret |= of_property_read_u32(np, "hback-porch", &of_mode.left_margin);
+        ret |= of_property_read_u32(np, "hfront-porch", &of_mode.right_margin);
+        ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+        ret |= of_property_read_u32(np, "vback-porch", &of_mode.upper_margin);
+        ret |= of_property_read_u32(np, "vfront-porch", &of_mode.lower_margin);
+        ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+        ret |= of_property_read_u32(np, "bpp", &bpp);
+        if (ret) {
+                pr_err("%s: Unable to read display properties\n", __func__);
+                goto failed_free_res;
+        }
+        of_mode.vmode = FB_VMODE_NONINTERLACED;
+
+        /* try allocating the framebuffer */
+        fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+        fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+                                GFP_KERNEL);
+        if (!fb_mem_virt) {
+                pr_err("%s: Failed to allocate framebuffer\n", __func__);
+                return -ENOMEM;
+        };
+
+        fbi->fb.fix.smem_start  = fb_mem_phys;
+        fbi->fb.fix.smem_len    = fb_mem_len;
+        fbi->fb.screen_base     = fb_mem_virt;
 
         fbi->palette_size       = PAGE_ALIGN(512);
         fbi->palette_cpu        = dma_alloc_coherent(&pdev->dev,
@@ -370,10 +419,11 @@ static int __devinit vt8500lcd_probe(struct platform_device *pdev)
                 goto failed_free_irq;
         }
 
-        fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
-        fbi->fb.var.bits_per_pixel      = pdata->bpp;
-        fbi->fb.var.xres_virtual        = pdata->xres_virtual;
-        fbi->fb.var.yres_virtual        = pdata->yres_virtual;
+        fb_videomode_to_var(&fbi->fb.var, &of_mode);
+
+        fbi->fb.var.xres_virtual        = of_mode.xres;
+        fbi->fb.var.yres_virtual        = of_mode.yres * 2;
+        fbi->fb.var.bits_per_pixel      = bpp;
 
         ret = vt8500lcd_set_par(&fbi->fb);
         if (ret) {
@@ -448,12 +498,18 @@ static int __devexit vt8500lcd_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id via_dt_ids[] = {
+        { .compatible = "via,vt8500-fb", },
+        {}
+};
+
 static struct platform_driver vt8500lcd_driver = {
         .probe          = vt8500lcd_probe,
         .remove         = __devexit_p(vt8500lcd_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "vt8500-lcd",
+                .of_match_table = of_match_ptr(via_dt_ids),
         },
 };
 
@@ -461,4 +517,5 @@ module_platform_driver(vt8500lcd_driver);
 
 MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com>");
 MODULE_DESCRIPTION("LCD controller driver for VIA VT8500");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, via_dt_ids);
diff --git a/drivers/video/wm8505fb.c b/drivers/video/wm8505fb.c
index c8703bd61b74..ec4742442103 100644
--- a/drivers/video/wm8505fb.c
+++ b/drivers/video/wm8505fb.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/wait.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/memblock.h>
 
 #include <mach/vt8500fb.h>
 
@@ -59,8 +62,12 @@ static int wm8505fb_init_hw(struct fb_info *info)
         writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR);
         writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1);
 
-        /* Set in-memory picture format to RGB 32bpp */
-        writel(0x1c,                   fbi->regbase + WMT_GOVR_COLORSPACE);
+        /*
+         * Set in-memory picture format to RGB
+         * 0x31C sets the correct color mode (RGB565) for WM8650
+         * Bit 8+9 (0x300) are ignored on WM8505 as reserved
+         */
+        writel(0x31c,                  fbi->regbase + WMT_GOVR_COLORSPACE);
         writel(1,                      fbi->regbase + WMT_GOVR_COLORSPACE1);
 
         /* Virtual buffer size */
@@ -127,6 +134,18 @@ static int wm8505fb_set_par(struct fb_info *info)
                 info->var.blue.msb_right = 0;
                 info->fix.visual = FB_VISUAL_TRUECOLOR;
                 info->fix.line_length = info->var.xres_virtual << 2;
+        } else if (info->var.bits_per_pixel == 16) {
+                info->var.red.offset = 11;
+                info->var.red.length = 5;
+                info->var.red.msb_right = 0;
+                info->var.green.offset = 5;
+                info->var.green.length = 6;
+                info->var.green.msb_right = 0;
+                info->var.blue.offset = 0;
+                info->var.blue.length = 5;
+                info->var.blue.msb_right = 0;
+                info->fix.visual = FB_VISUAL_TRUECOLOR;
+                info->fix.line_length = info->var.xres_virtual << 1;
         }
 
         wm8505fb_set_timing(info);
@@ -246,16 +265,20 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
         struct wm8505fb_info    *fbi;
         struct resource         *res;
         void                    *addr;
-        struct vt8500fb_platform_data *pdata;
         int ret;
 
-        pdata = pdev->dev.platform_data;
+        struct fb_videomode     of_mode;
+        struct device_node      *np;
+        u32                     bpp;
+        dma_addr_t fb_mem_phys;
+        unsigned long fb_mem_len;
+        void *fb_mem_virt;
 
         ret = -ENOMEM;
         fbi = NULL;
 
-        fbi = kzalloc(sizeof(struct wm8505fb_info) + sizeof(u32) * 16,
-                                                        GFP_KERNEL);
+        fbi = devm_kzalloc(&pdev->dev, sizeof(struct wm8505fb_info) +
+                        sizeof(u32) * 16, GFP_KERNEL);
         if (!fbi) {
                 dev_err(&pdev->dev, "Failed to initialize framebuffer device\n");
                 ret = -ENOMEM;
@@ -305,21 +328,58 @@ static int __devinit wm8505fb_probe(struct platform_device *pdev)
                 goto failed_free_res;
         }
 
-        fb_videomode_to_var(&fbi->fb.var, &pdata->mode);
+        np = of_parse_phandle(pdev->dev.of_node, "default-mode", 0);
+        if (!np) {
+                pr_err("%s: No display description in Device Tree\n", __func__);
+                ret = -EINVAL;
+                goto failed_free_res;
+        }
+
+        /*
+         * This code is copied from Sascha Hauer's of_videomode helper
+         * and can be replaced with a call to the helper once mainlined
+         */
+        ret = 0;
+        ret |= of_property_read_u32(np, "hactive", &of_mode.xres);
+        ret |= of_property_read_u32(np, "vactive", &of_mode.yres);
+        ret |= of_property_read_u32(np, "hback-porch", &of_mode.left_margin);
+        ret |= of_property_read_u32(np, "hfront-porch", &of_mode.right_margin);
+        ret |= of_property_read_u32(np, "hsync-len", &of_mode.hsync_len);
+        ret |= of_property_read_u32(np, "vback-porch", &of_mode.upper_margin);
+        ret |= of_property_read_u32(np, "vfront-porch", &of_mode.lower_margin);
+        ret |= of_property_read_u32(np, "vsync-len", &of_mode.vsync_len);
+        ret |= of_property_read_u32(np, "bpp", &bpp);
+        if (ret) {
+                pr_err("%s: Unable to read display properties\n", __func__);
+                goto failed_free_res;
+        }
+
+        of_mode.vmode = FB_VMODE_NONINTERLACED;
+        fb_videomode_to_var(&fbi->fb.var, &of_mode);
 
         fbi->fb.var.nonstd              = 0;
         fbi->fb.var.activate            = FB_ACTIVATE_NOW;
 
         fbi->fb.var.height              = -1;
         fbi->fb.var.width               = -1;
-        fbi->fb.var.xres_virtual        = pdata->xres_virtual;
-        fbi->fb.var.yres_virtual        = pdata->yres_virtual;
-        fbi->fb.var.bits_per_pixel      = pdata->bpp;
 
-        fbi->fb.fix.smem_start  = pdata->video_mem_phys;
-        fbi->fb.fix.smem_len    = pdata->video_mem_len;
-        fbi->fb.screen_base     = pdata->video_mem_virt;
-        fbi->fb.screen_size     = pdata->video_mem_len;
+        /* try allocating the framebuffer */
+        fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8);
+        fb_mem_virt = dma_alloc_coherent(&pdev->dev, fb_mem_len, &fb_mem_phys,
+                                GFP_KERNEL);
+        if (!fb_mem_virt) {
+                pr_err("%s: Failed to allocate framebuffer\n", __func__);
+                return -ENOMEM;
+        };
+
+        fbi->fb.var.xres_virtual        = of_mode.xres;
+        fbi->fb.var.yres_virtual        = of_mode.yres * 2;
+        fbi->fb.var.bits_per_pixel      = bpp;
+
+        fbi->fb.fix.smem_start          = fb_mem_phys;
+        fbi->fb.fix.smem_len            = fb_mem_len;
+        fbi->fb.screen_base             = fb_mem_virt;
+        fbi->fb.screen_size             = fb_mem_len;
 
         if (fb_alloc_cmap(&fbi->fb.cmap, 256, 0) < 0) {
                 dev_err(&pdev->dev, "Failed to allocate color map\n");
@@ -395,12 +455,18 @@ static int __devexit wm8505fb_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+        { .compatible = "wm,wm8505-fb", },
+        {}
+};
+
 static struct platform_driver wm8505fb_driver = {
         .probe          = wm8505fb_probe,
         .remove         = __devexit_p(wm8505fb_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = DRIVER_NAME,
+                .of_match_table = of_match_ptr(wmt_dt_ids),
         },
 };
 
@@ -408,4 +474,5 @@ module_platform_driver(wm8505fb_driver);
 
 MODULE_AUTHOR("Ed Spiridonov <edo.rus@gmail.com>");
 MODULE_DESCRIPTION("Framebuffer driver for WMT WM8505");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/drivers/video/wmt_ge_rops.c b/drivers/video/wmt_ge_rops.c
index 55be3865015b..ba025b4c7d09 100644
--- a/drivers/video/wmt_ge_rops.c
+++ b/drivers/video/wmt_ge_rops.c
@@ -158,12 +158,18 @@ static int __devexit wmt_ge_rops_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id wmt_dt_ids[] = {
+        { .compatible = "wm,prizm-ge-rops", },
+        { /* sentinel */ }
+};
+
 static struct platform_driver wmt_ge_rops_driver = {
         .probe          = wmt_ge_rops_probe,
         .remove         = __devexit_p(wmt_ge_rops_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "wmt_ge_rops",
+                .of_match_table = of_match_ptr(wmt_dt_ids),
         },
 };
 
@@ -172,4 +178,5 @@ module_platform_driver(wmt_ge_rops_driver);
 MODULE_AUTHOR("Alexey Charkov <alchark@gmail.com");
 MODULE_DESCRIPTION("Accelerators for raster operations using "
                    "WonderMedia Graphics Engine");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, wmt_dt_ids);
diff --git a/include/linux/mfd/abx500/ab8500-codec.h b/include/linux/mfd/abx500/ab8500-codec.h
index dc6529202cdd..d7079413def0 100644
--- a/include/linux/mfd/abx500/ab8500-codec.h
+++ b/include/linux/mfd/abx500/ab8500-codec.h
@@ -23,7 +23,8 @@ enum amic_type {
 /* Mic-biases */
 enum amic_micbias {
         AMIC_MICBIAS_VAMIC1,
-        AMIC_MICBIAS_VAMIC2
+        AMIC_MICBIAS_VAMIC2,
+        AMIC_MICBIAS_UNKNOWN
 };
 
 /* Bias-voltage */
@@ -31,7 +32,8 @@ enum ear_cm_voltage {
         EAR_CMV_0_95V,
         EAR_CMV_1_10V,
         EAR_CMV_1_27V,
-        EAR_CMV_1_58V
+        EAR_CMV_1_58V,
+        EAR_CMV_UNKNOWN
 };
 
 /* Analog microphone settings */
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index 1717cd935e1c..b8e241125201 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -83,6 +83,11 @@ static inline unsigned int irq_of_parse_and_map(struct device_node *dev,
 {
         return 0;
 }
+
+static inline void *of_irq_find_parent(struct device_node *child)
+{
+        return NULL;
+}
 #endif /* !CONFIG_OF */
 
 #endif /* __OF_IRQ_H */
diff --git a/sound/soc/codecs/ab8500-codec.c b/sound/soc/codecs/ab8500-codec.c
index 23b40186f9b8..07abd09e0b1d 100644
--- a/sound/soc/codecs/ab8500-codec.c
+++ b/sound/soc/codecs/ab8500-codec.c
@@ -34,6 +34,7 @@
 #include <linux/mfd/abx500/ab8500-sysctrl.h>
 #include <linux/mfd/abx500/ab8500-codec.h>
 #include <linux/regulator/consumer.h>
+#include <linux/of.h>
 
 #include <sound/core.h>
 #include <sound/pcm.h>
@@ -2394,9 +2395,65 @@ struct snd_soc_dai_driver ab8500_codec_dai[] = {
         }
 };
 
+static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
+                                struct ab8500_codec_platform_data *codec)
+{
+        u32 value;
+
+        if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
+                codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
+        else
+                codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
+
+        if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
+                codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
+        else
+                codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
+
+        /* Has a non-standard Vamic been requested? */
+        if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
+                codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
+        else
+                codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
+
+        if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
+                codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
+        else
+                codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
+
+        if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
+                codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
+        else
+                codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
+
+        if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
+                switch (value) {
+                case 950 :
+                        codec->ear_cmv = EAR_CMV_0_95V;
+                        break;
+                case 1100 :
+                        codec->ear_cmv = EAR_CMV_1_10V;
+                        break;
+                case 1270 :
+                        codec->ear_cmv = EAR_CMV_1_27V;
+                        break;
+                case 1580 :
+                        codec->ear_cmv = EAR_CMV_1_58V;
+                        break;
+                default :
+                        codec->ear_cmv = EAR_CMV_UNKNOWN;
+                        dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
+                }
+        } else {
+                dev_warn(dev, "No earpiece voltage found in DT - using default\n");
+                codec->ear_cmv = EAR_CMV_0_95V;
+        }
+}
+
 static int ab8500_codec_probe(struct snd_soc_codec *codec)
 {
         struct device *dev = codec->dev;
+        struct device_node *np = dev->of_node;
         struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
         struct ab8500_platform_data *pdata;
         struct filter_control *fc;
@@ -2410,6 +2467,30 @@ static int ab8500_codec_probe(struct snd_soc_codec *codec)
         /* Inform SoC Core that we have our own I/O arrangements. */
         codec->control_data = (void *)true;
 
+        if (np) {
+                if (!pdata)
+                        pdata = devm_kzalloc(dev,
+                                        sizeof(struct ab8500_platform_data),
+                                        GFP_KERNEL);
+
+                if (pdata && !pdata->codec)
+                        pdata->codec
+                                = devm_kzalloc(dev,
+                                        sizeof(struct ab8500_codec_platform_data),
+                                        GFP_KERNEL);
+
+                if (!(pdata && pdata->codec))
+                        return -ENOMEM;
+
+                ab8500_codec_of_probe(dev, np, pdata->codec);
+
+        } else {
+                if (!(pdata && pdata->codec)) {
+                        dev_err(dev, "No codec platform data or DT found\n");
+                        return -EINVAL;
+                }
+        }
+
         status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
         if (status < 0) {
                 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
diff --git a/sound/soc/ux500/mop500.c b/sound/soc/ux500/mop500.c
index 31c4d26d0359..356611d9654d 100644
--- a/sound/soc/ux500/mop500.c
+++ b/sound/soc/ux500/mop500.c
@@ -16,6 +16,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/spi/spi.h>
+#include <linux/of.h>
 
 #include <sound/soc.h>
 #include <sound/initval.h>
@@ -56,16 +57,47 @@ static struct snd_soc_card mop500_card = {
         .num_links = ARRAY_SIZE(mop500_dai_links),
 };
 
+static int __devinit mop500_of_probe(struct platform_device *pdev,
+                                struct device_node *np)
+{
+        struct device_node *codec_np, *msp_np[2];
+        int i;
+
+        msp_np[0] = of_parse_phandle(np, "stericsson,cpu-dai", 0);
+        msp_np[1] = of_parse_phandle(np, "stericsson,cpu-dai", 1);
+        codec_np  = of_parse_phandle(np, "stericsson,audio-codec", 0);
+
+        if (!(msp_np[0] && msp_np[1] && codec_np)) {
+                dev_err(&pdev->dev, "Phandle missing or invalid\n");
+                return -EINVAL;
+        }
+
+        for (i = 0; i < 2; i++) {
+                mop500_dai_links[i].cpu_of_node = msp_np[i];
+                mop500_dai_links[i].cpu_dai_name = NULL;
+                mop500_dai_links[i].codec_of_node = codec_np;
+                mop500_dai_links[i].codec_name = NULL;
+        }
+
+        snd_soc_of_parse_card_name(&mop500_card, "stericsson,card-name");
+
+        return 0;
+}
 static int __devinit mop500_probe(struct platform_device *pdev)
 {
+        struct device_node *np = pdev->dev.of_node;
         int ret;
 
-        pr_debug("%s: Enter.\n", __func__);
-
         dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
 
         mop500_card.dev = &pdev->dev;
 
+        if (np) {
+                ret = mop500_of_probe(pdev, np);
+                if (ret)
+                        return ret;
+        }
+
         dev_dbg(&pdev->dev, "%s: Card %s: Set platform drvdata.\n",
                 __func__, mop500_card.name);
         platform_set_drvdata(pdev, &mop500_card);
@@ -83,8 +115,7 @@ static int __devinit mop500_probe(struct platform_device *pdev)
         ret = snd_soc_register_card(&mop500_card);
         if (ret)
                 dev_err(&pdev->dev,
-                        "Error: snd_soc_register_card failed (%d)!\n",
-                        ret);
+                        "Error: snd_soc_register_card failed (%d)!\n", ret);
 
         return ret;
 }
@@ -97,14 +128,20 @@ static int __devexit mop500_remove(struct platform_device *pdev)
 
         snd_soc_unregister_card(mop500_card);
         mop500_ab8500_remove(mop500_card);
-        
+
         return 0;
 }
 
+static const struct of_device_id snd_soc_mop500_match[] = {
+        { .compatible = "stericsson,snd-soc-mop500", },
+        {},
+};
+
 static struct platform_driver snd_soc_mop500_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name = "snd-soc-mop500",
+                .of_match_table = snd_soc_mop500_match,
         },
         .probe = mop500_probe,
         .remove = __devexit_p(mop500_remove),
diff --git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 057e28ef770e..45e43b4057b0 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -830,10 +830,16 @@ static int __devexit ux500_msp_drv_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id ux500_msp_i2s_match[] = {
+        { .compatible = "stericsson,ux500-msp-i2s", },
+        {},
+};
+
 static struct platform_driver msp_i2s_driver = {
         .driver = {
                 .name = "ux500-msp-i2s",
                 .owner = THIS_MODULE,
+                .of_match_table = ux500_msp_i2s_match,
         },
         .probe = ux500_msp_drv_probe,
         .remove = ux500_msp_drv_remove,
diff --git a/sound/soc/ux500/ux500_msp_i2s.c b/sound/soc/ux500/ux500_msp_i2s.c
index eb85113d472a..e5c79ca42518 100644
--- a/sound/soc/ux500/ux500_msp_i2s.c
+++ b/sound/soc/ux500/ux500_msp_i2s.c
@@ -15,8 +15,10 @@
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 
 #include <mach/hardware.h>
 #include <mach/msp.h>
@@ -25,6 +27,9 @@
 
 #include "ux500_msp_i2s.h"
 
+/* MSP1/3 Tx/Rx usage protection */
+static DEFINE_SPINLOCK(msp_rxtx_lock);
+
  /* Protocol desciptors */
 static const struct msp_protdesc prot_descs[] = {
         { /* I2S */
@@ -352,17 +357,23 @@ static int configure_multichannel(struct ux500_msp *msp,
 
 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
 {
-        int status = 0;
+        int status = 0, retval = 0;
         u32 reg_val_DMACR, reg_val_GCR;
+        unsigned long flags;
 
         /* Check msp state whether in RUN or CONFIGURED Mode */
-        if ((msp->msp_state == MSP_STATE_IDLE) && (msp->plat_init)) {
-                status = msp->plat_init();
-                if (status) {
-                        dev_err(msp->dev, "%s: ERROR: Failed to init MSP (%d)!\n",
-                                __func__, status);
-                        return status;
+        if (msp->msp_state == MSP_STATE_IDLE) {
+                spin_lock_irqsave(&msp_rxtx_lock, flags);
+                if (msp->pinctrl_rxtx_ref == 0 &&
+                        !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) {
+                        retval = pinctrl_select_state(msp->pinctrl_p,
+                                                msp->pinctrl_def);
+                        if (retval)
+                                pr_err("could not set MSP defstate\n");
                 }
+                if (!retval)
+                        msp->pinctrl_rxtx_ref++;
+                spin_unlock_irqrestore(&msp_rxtx_lock, flags);
         }
 
         /* Configure msp with protocol dependent settings */
@@ -620,7 +631,8 @@ int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
 
 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
 {
-        int status = 0;
+        int status = 0, retval = 0;
+        unsigned long flags;
 
         dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
 
@@ -631,12 +643,19 @@ int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
                 writel((readl(msp->registers + MSP_GCR) &
                                (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
                               msp->registers + MSP_GCR);
-                if (msp->plat_exit)
-                        status = msp->plat_exit();
-                        if (status)
-                                dev_warn(msp->dev,
-                                        "%s: WARN: ux500_msp_i2s_exit failed (%d)!\n",
-                                        __func__, status);
+
+                spin_lock_irqsave(&msp_rxtx_lock, flags);
+                WARN_ON(!msp->pinctrl_rxtx_ref);
+                msp->pinctrl_rxtx_ref--;
+                if (msp->pinctrl_rxtx_ref == 0 &&
+                        !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) {
+                        retval = pinctrl_select_state(msp->pinctrl_p,
+                                                msp->pinctrl_sleep);
+                        if (retval)
+                                pr_err("could not set MSP sleepstate\n");
+                }
+                spin_unlock_irqrestore(&msp_rxtx_lock, flags);
+
                 writel(0, msp->registers + MSP_GCR);
                 writel(0, msp->registers + MSP_TCF);
                 writel(0, msp->registers + MSP_RCF);
@@ -665,18 +684,31 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
 {
         struct resource *res = NULL;
         struct i2s_controller *i2s_cont;
+        struct device_node *np = pdev->dev.of_node;
         struct ux500_msp *msp;
 
-        dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
-                pdev->name, platform_data->id);
-
         *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
         msp = *msp_p;
 
+        if (np) {
+                if (!platform_data) {
+                        platform_data = devm_kzalloc(&pdev->dev,
+                                sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
+                        if (!platform_data)
+                                ret = -ENOMEM;
+                }
+        } else
+                if (!platform_data)
+                        ret = -EINVAL;
+
+        if (ret)
+                goto err_res;
+
+        dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
+                pdev->name, platform_data->id);
+
         msp->id = platform_data->id;
         msp->dev = &pdev->dev;
-        msp->plat_init = platform_data->msp_i2s_init;
-        msp->plat_exit = platform_data->msp_i2s_exit;
         msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
         msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
 
@@ -713,6 +745,25 @@ int ux500_msp_i2s_init_msp(struct platform_device *pdev,
         dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
         msp->i2s_cont = i2s_cont;
 
+        msp->pinctrl_p = pinctrl_get(msp->dev);
+        if (IS_ERR(msp->pinctrl_p))
+                dev_err(&pdev->dev, "could not get MSP pinctrl\n");
+        else {
+                msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p,
+                                                PINCTRL_STATE_DEFAULT);
+                if (IS_ERR(msp->pinctrl_def)) {
+                        dev_err(&pdev->dev,
+                                "could not get MSP defstate (%li)\n",
+                                PTR_ERR(msp->pinctrl_def));
+                }
+                msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p,
+                                                PINCTRL_STATE_SLEEP);
+                if (IS_ERR(msp->pinctrl_sleep))
+                        dev_err(&pdev->dev,
+                                "could not get MSP idlestate (%li)\n",
+                                PTR_ERR(msp->pinctrl_def));
+        }
+
         return 0;
 }
 
diff --git a/sound/soc/ux500/ux500_msp_i2s.h b/sound/soc/ux500/ux500_msp_i2s.h
index 2d9136da9865..1311c0df7628 100644
--- a/sound/soc/ux500/ux500_msp_i2s.h
+++ b/sound/soc/ux500/ux500_msp_i2s.h
@@ -524,14 +524,18 @@ struct ux500_msp {
         struct dma_chan *rx_pipeid;
         enum msp_state msp_state;
         int (*transfer) (struct ux500_msp *msp, struct i2s_message *message);
-        int (*plat_init) (void);
-        int (*plat_exit) (void);
         struct timer_list notify_timer;
         int def_elem_len;
         unsigned int dir_busy;
         int loopback_enable;
         u32 backup_regs[MAX_MSP_BACKUP_REGS];
         unsigned int f_bitclk;
+        /* Pin modes */
+        struct pinctrl *pinctrl_p;
+        struct pinctrl_state *pinctrl_def;
+        struct pinctrl_state *pinctrl_sleep;
+        /* Reference Count */
+        int pinctrl_rxtx_ref;
 };
 
 struct ux500_msp_dma_params {