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authorSujith <Sujith.Manoharan@atheros.com>2009-08-07 00:15:33 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-14 09:13:35 -0400
commit180d674bab10ce10747f7bc7214462da185431bd (patch)
treecef60e5e879b35cb4060c067244a21f8d1dcd2ac
parentbf466fb67c8e0559ba1875232b03ee8dee32ae09 (diff)
ath9k: Remove local chainmask variable
The chainmask can be obtained directly from ath_hw. Also, use a helper macro for comparing CTLs - this improves readability. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c86
1 files changed, 42 insertions, 44 deletions
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 29878e0789b1..d34dd23e806a 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -502,14 +502,23 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
502 u16 twiceMaxRegulatoryPower, 502 u16 twiceMaxRegulatoryPower,
503 u16 powerLimit) 503 u16 powerLimit)
504{ 504{
505 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k; 505#define CMP_TEST_GRP \
506 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 506 (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
507 static const u16 tpScaleReductionTable[5] = 507 pEepData->ctlIndex[i]) \
508 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER }; 508 || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
509 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
509 510
510 int i; 511 int i;
511 int16_t twiceLargestAntenna; 512 int16_t twiceLargestAntenna;
513 u16 twiceMinEdgePower;
514 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
515 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
516 u16 numCtlModes, *pCtlMode, ctlMode, freq;
517 struct chan_centers centers;
512 struct cal_ctl_data_4k *rep; 518 struct cal_ctl_data_4k *rep;
519 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
520 static const u16 tpScaleReductionTable[5] =
521 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
513 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = { 522 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
514 0, { 0, 0, 0, 0} 523 0, { 0, 0, 0, 0}
515 }; 524 };
@@ -520,27 +529,18 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
520 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = { 529 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
521 0, {0, 0, 0, 0} 530 0, {0, 0, 0, 0}
522 }; 531 };
523 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
524 u16 ctlModesFor11g[] = 532 u16 ctlModesFor11g[] =
525 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, 533 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
526 CTL_2GHT40 534 CTL_2GHT40
527 }; 535 };
528 u16 numCtlModes, *pCtlMode, ctlMode, freq;
529 struct chan_centers centers;
530 int tx_chainmask;
531 u16 twiceMinEdgePower;
532
533 tx_chainmask = ah->txchainmask;
534 536
535 ath9k_hw_get_channel_centers(ah, chan, &centers); 537 ath9k_hw_get_channel_centers(ah, chan, &centers);
536 538
537 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0]; 539 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
538
539 twiceLargestAntenna = (int16_t)min(AntennaReduction - 540 twiceLargestAntenna = (int16_t)min(AntennaReduction -
540 twiceLargestAntenna, 0); 541 twiceLargestAntenna, 0);
541 542
542 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna; 543 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
543
544 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) { 544 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
545 maxRegAllowedPower -= 545 maxRegAllowedPower -=
546 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2); 546 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
@@ -584,6 +584,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
584 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 584 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
585 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 585 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
586 (pCtlMode[ctlMode] == CTL_2GHT40); 586 (pCtlMode[ctlMode] == CTL_2GHT40);
587
587 if (isHt40CtlMode) 588 if (isHt40CtlMode)
588 freq = centers.synth_center; 589 freq = centers.synth_center;
589 else if (pCtlMode[ctlMode] & EXT_ADDITIVE) 590 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
@@ -596,22 +597,17 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
596 twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 597 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
597 598
598 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) && 599 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
599 pEepData->ctlIndex[i]; i++) { 600 pEepData->ctlIndex[i]; i++) {
600 if ((((cfgCtl & ~CTL_MODE_M) | 601
601 (pCtlMode[ctlMode] & CTL_MODE_M)) == 602 if (CMP_TEST_GRP) {
602 pEepData->ctlIndex[i]) ||
603 (((cfgCtl & ~CTL_MODE_M) |
604 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
605 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
606 SD_NO_CTL))) {
607 rep = &(pEepData->ctlData[i]); 603 rep = &(pEepData->ctlData[i]);
608 604
609 twiceMinEdgePower = 605 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
610 ath9k_hw_get_max_edge_power(freq, 606 freq,
611 rep->ctlEdges[ar5416_get_ntxchains 607 rep->ctlEdges[
612 (tx_chainmask) - 1], 608 ar5416_get_ntxchains(ah->txchainmask) - 1],
613 IS_CHAN_2GHZ(chan), 609 IS_CHAN_2GHZ(chan),
614 AR5416_EEP4K_NUM_BAND_EDGES); 610 AR5416_EEP4K_NUM_BAND_EDGES);
615 611
616 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 612 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
617 twiceMaxEdgePower = 613 twiceMaxEdgePower =
@@ -628,42 +624,38 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
628 624
629 switch (pCtlMode[ctlMode]) { 625 switch (pCtlMode[ctlMode]) {
630 case CTL_11B: 626 case CTL_11B:
631 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); 627 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
632 i++) {
633 targetPowerCck.tPow2x[i] = 628 targetPowerCck.tPow2x[i] =
634 min((u16)targetPowerCck.tPow2x[i], 629 min((u16)targetPowerCck.tPow2x[i],
635 minCtlPower); 630 minCtlPower);
636 } 631 }
637 break; 632 break;
638 case CTL_11G: 633 case CTL_11G:
639 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); 634 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
640 i++) {
641 targetPowerOfdm.tPow2x[i] = 635 targetPowerOfdm.tPow2x[i] =
642 min((u16)targetPowerOfdm.tPow2x[i], 636 min((u16)targetPowerOfdm.tPow2x[i],
643 minCtlPower); 637 minCtlPower);
644 } 638 }
645 break; 639 break;
646 case CTL_2GHT20: 640 case CTL_2GHT20:
647 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); 641 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
648 i++) {
649 targetPowerHt20.tPow2x[i] = 642 targetPowerHt20.tPow2x[i] =
650 min((u16)targetPowerHt20.tPow2x[i], 643 min((u16)targetPowerHt20.tPow2x[i],
651 minCtlPower); 644 minCtlPower);
652 } 645 }
653 break; 646 break;
654 case CTL_11B_EXT: 647 case CTL_11B_EXT:
655 targetPowerCckExt.tPow2x[0] = min((u16) 648 targetPowerCckExt.tPow2x[0] =
656 targetPowerCckExt.tPow2x[0], 649 min((u16)targetPowerCckExt.tPow2x[0],
657 minCtlPower); 650 minCtlPower);
658 break; 651 break;
659 case CTL_11G_EXT: 652 case CTL_11G_EXT:
660 targetPowerOfdmExt.tPow2x[0] = min((u16) 653 targetPowerOfdmExt.tPow2x[0] =
661 targetPowerOfdmExt.tPow2x[0], 654 min((u16)targetPowerOfdmExt.tPow2x[0],
662 minCtlPower); 655 minCtlPower);
663 break; 656 break;
664 case CTL_2GHT40: 657 case CTL_2GHT40:
665 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); 658 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
666 i++) {
667 targetPowerHt40.tPow2x[i] = 659 targetPowerHt40.tPow2x[i] =
668 min((u16)targetPowerHt40.tPow2x[i], 660 min((u16)targetPowerHt40.tPow2x[i],
669 minCtlPower); 661 minCtlPower);
@@ -674,9 +666,13 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
674 } 666 }
675 } 667 }
676 668
677 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = 669 ratesArray[rate6mb] =
678 ratesArray[rate18mb] = ratesArray[rate24mb] = 670 ratesArray[rate9mb] =
679 targetPowerOfdm.tPow2x[0]; 671 ratesArray[rate12mb] =
672 ratesArray[rate18mb] =
673 ratesArray[rate24mb] =
674 targetPowerOfdm.tPow2x[0];
675
680 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 676 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
681 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 677 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
682 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 678 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
@@ -700,6 +696,8 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
700 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 696 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
701 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 697 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
702 } 698 }
699
700#undef CMP_TEST_GRP
703} 701}
704 702
705static void ath9k_hw_4k_set_txpower(struct ath_hw *ah, 703static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,