Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (52 commits)
  Blackfin: encode cpu-rev into uImage name
  Blackfin: bf54x: don't ack GPIO ints when unmasking them
  Blackfin: sram_free_with_lsl: do not ignore return value of sram_free
  Blackfin: boards: add missing "static" to peripheral lists
  Blackfin: DNP5370: new board port
  Blackfin: bf518f-ezbrd: fix dsa resources
  Blackfin: move "-m elf32bfin" to general LDFLAGS
  Blackfin: kgdb_test: make sure to initialize num2
  Blackfin: kgdb: disable preempt schedule when running single step in kgdb
  Blackfin: kgdb: disable interrupt when single stepping in ADEOS
  Blackfin: SMP: kgdb: apply anomaly 257 work around
  Blackfin: fix building IPIPE code when XIP is enabled
  Blackfin: SMP: kgdb: flush core internal write buffer before flushinv
  Blackfin: sport_uart resources: remove unused secondary RX/TX pins
  Blackfin: tll6527m: fix spelling in unused code (struct name)
  Blackfin: bf527-ezkit: add adau1373 chip address
  Blackfin: no-mpu: fix masking of small uncached dma region
  Blackfin: pm: drop irq save/restore in standby and suspend to mem callback
  MAINTAINERS: update Analog Devices support info
  Blackfin: dpmc.h: pull in new pll.h
  ...

157 files changed, 9963 insertions, 11015 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index aca102f758ba..ad600c54c7bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -285,6 +285,41 @@ L:	linux-parisc@vger.kernel.org
 S:      Maintained
 F:      sound/pci/ad1889.*
 
+AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/AD5254
+S:      Supported
+F:      drivers/misc/ad525x_dpot.c
+
+AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/AD5398
+S:      Supported
+F:      drivers/regulator/ad5398.c
+
+AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/AD7142
+S:      Supported
+F:      drivers/input/misc/ad714x.c
+
+AD7877 TOUCHSCREEN DRIVER
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/AD7877
+S:      Supported
+F:      drivers/input/touchscreen/ad7877.c
+
+AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/AD7879
+S:      Supported
+F:      drivers/input/touchscreen/ad7879.c
+
 ADM1025 HARDWARE MONITOR DRIVER
 M:      Jean Delvare <khali@linux-fr.org>
 L:      lm-sensors@lm-sensors.org
@@ -304,6 +339,32 @@ W:	http://linuxwireless.org/
 S:      Orphan
 F:      drivers/net/wireless/adm8211.*
 
+ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/ADP5520
+S:      Supported
+F:      drivers/mfd/adp5520.c
+F:      drivers/video/backlight/adp5520_bl.c
+F:      drivers/led/leds-adp5520.c
+F:      drivers/gpio/adp5520-gpio.c
+F:      drivers/input/keyboard/adp5520-keys.c
+
+ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/ADP5588
+S:      Supported
+F:      drivers/input/keyboard/adp5588-keys.c
+F:      drivers/gpio/adp5588-gpio.c
+
+ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/ADP8860
+S:      Supported
+F:      drivers/video/backlight/adp8860_bl.c
+
 ADT746X FAN DRIVER
 M:      Colin Leroy <colin@colino.net>
 S:      Maintained
@@ -316,6 +377,13 @@ S:	Maintained
 F:      Documentation/hwmon/adt7475
 F:      drivers/hwmon/adt7475.c
 
+ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
+M:      Michael Hennerich <michael.hennerich@analog.com>
+L:      device-driver-devel@blackfin.uclinux.org
+W:      http://wiki-analog.com/ADXL345
+S:      Supported
+F:      drivers/input/misc/adxl34x.c
+
 ADVANSYS SCSI DRIVER
 M:      Matthew Wilcox <matthew@wil.cx>
 L:      linux-scsi@vger.kernel.org
@@ -440,17 +508,23 @@ L:	linux-rdma@vger.kernel.org
 S:      Maintained
 F:      drivers/infiniband/hw/amso1100/
 
-ANALOG DEVICES INC ASOC DRIVERS
-L:      uclinux-dist-devel@blackfin.uclinux.org
+ANALOG DEVICES INC ASOC CODEC DRIVERS
+L:      device-driver-devel@blackfin.uclinux.org
 L:      alsa-devel@alsa-project.org (moderated for non-subscribers)
-W:      http://blackfin.uclinux.org/
+W:      http://wiki-analog.com/
 S:      Supported
-F:      sound/soc/blackfin/*
 F:      sound/soc/codecs/ad1*
 F:      sound/soc/codecs/adau*
 F:      sound/soc/codecs/adav*
 F:      sound/soc/codecs/ssm*
 
+ANALOG DEVICES INC ASOC DRIVERS
+L:      uclinux-dist-devel@blackfin.uclinux.org
+L:      alsa-devel@alsa-project.org (moderated for non-subscribers)
+W:      http://blackfin.uclinux.org/
+S:      Supported
+F:      sound/soc/blackfin/*
+
 AOA (Apple Onboard Audio) ALSA DRIVER
 M:      Johannes Berg <johannes@sipsolutions.net>
 L:      linuxppc-dev@lists.ozlabs.org
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 46738d49b7c8..46f42b2066e5 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -19,7 +19,7 @@ KBUILD_CFLAGS           += -mlong-calls
 endif
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_CFLAGS_MODULE    += -mlong-calls
-KBUILD_LDFLAGS_MODULE   += -m elf32bfin
+LDFLAGS                 += -m elf32bfin
 KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
@@ -97,8 +97,11 @@ rev-$(CONFIG_BF_REV_0_6)  := 0.6
 rev-$(CONFIG_BF_REV_NONE) := none
 rev-$(CONFIG_BF_REV_ANY)  := any
 
-KBUILD_CFLAGS += -mcpu=$(cpu-y)-$(rev-y)
-KBUILD_AFLAGS += -mcpu=$(cpu-y)-$(rev-y)
+CPU_REV := $(cpu-y)-$(rev-y)
+export CPU_REV
+
+KBUILD_CFLAGS += -mcpu=$(CPU_REV)
+KBUILD_AFLAGS += -mcpu=$(CPU_REV)
 
 # - we utilize the silicon rev from the toolchain, so move it over to the checkflags
 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index 13d2dbd658e3..0a49279e3428 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -17,7 +17,7 @@ UIMAGE_OPTS-$(CONFIG_ROMKERNEL) += -a $(CONFIG_ROM_BASE) -x
 
 quiet_cmd_uimage = UIMAGE  $@
       cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A $(ARCH) -O linux -T kernel \
-                   -C $(2) -n '$(MACHINE)-$(KERNELRELEASE)' \
+                   -C $(2) -n '$(CPU_REV)-$(KERNELRELEASE)' \
                    -e $(shell $(NM) vmlinux | awk '$$NF == "__start" {print $$1}') \
                    $(UIMAGE_OPTS-y) -d $< $@
 
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
new file mode 100644
index 000000000000..4cf451024fd8
--- /dev/null
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -0,0 +1,113 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_FUTEX is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+CONFIG_SLAB=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_BF561=y
+CONFIG_SMP=y
+CONFIG_IRQ_TIMER0=10
+CONFIG_CLKIN_HZ=30000000
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
+CONFIG_BFIN_GPTIMERS=m
+CONFIG_C_CDPRIO=y
+CONFIG_BANK_3=0xAAC2
+CONFIG_BINFMT_FLAT=y
+CONFIG_BINFMT_ZFLAT=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_IRDA=m
+CONFIG_IRLAN=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRTTY_SIR=m
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_RAM=y
+CONFIG_MTD_ROM=m
+CONFIG_MTD_PHYSMAP=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT=m
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=m
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_BFIN_WDT=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_JFFS2_FS=m
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_SMB_FS=m
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_MMRS=y
+CONFIG_DEBUG_HWERR=y
+CONFIG_EXACT_HWERR=y
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRYPTO=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/DNP5370_defconfig b/arch/blackfin/configs/DNP5370_defconfig
new file mode 100644
index 000000000000..0ebc7d9aa426
--- /dev/null
+++ b/arch/blackfin/configs/DNP5370_defconfig
@@ -0,0 +1,121 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="DNP5370"
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLOB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_BF537=y
+CONFIG_BF_REV_0_3=y
+CONFIG_DNP5370=y
+CONFIG_IRQ_ERROR=7
+# CONFIG_CYCLES_CLOCKSOURCE is not set
+CONFIG_C_CDPRIO=y
+CONFIG_C_AMBEN_B0_B1_B2=y
+CONFIG_PM=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_LLC2=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_UCLINUX=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_NETDEVICES=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_BFIN_MAC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_BFIN_DMA_INTERFACE is not set
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_BFIN_JTAG_COMM=y
+CONFIG_BFIN_JTAG_COMM_CONSOLE=y
+CONFIG_SERIAL_BFIN=y
+CONFIG_SERIAL_BFIN_CONSOLE=y
+CONFIG_SERIAL_BFIN_UART0=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_BLACKFIN_TWI=y
+CONFIG_SPI=y
+CONFIG_SPI_BFIN=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_LM75=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SPI=y
+CONFIG_DMADEVICES=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=850
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_DEBUG_KOBJECT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_PAGE_POISONING=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_DOUBLEFAULT=y
+CONFIG_CPLB_INFO=y
+CONFIG_CRC_CCITT=y
diff --git a/arch/blackfin/include/asm/bfin_dma.h b/arch/blackfin/include/asm/bfin_dma.h
new file mode 100644
index 000000000000..d51120744148
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_dma.h
@@ -0,0 +1,91 @@
+/*
+ * bfin_dma.h - Blackfin DMA defines/structures/etc...
+ *
+ * Copyright 2004-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __ASM_BFIN_DMA_H__
+#define __ASM_BFIN_DMA_H__
+
+#include <linux/types.h>
+
+/* DMA_CONFIG Masks */
+#define DMAEN                   0x0001  /* DMA Channel Enable */
+#define WNR                             0x0002  /* Channel Direction (W/R*) */
+#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
+#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
+#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
+#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
+#define RESTART                 0x0020  /* DMA Buffer Clear */
+#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
+#define DI_EN                   0x0080  /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
+#define NDSIZE                  0x0f00  /* Next Descriptor Size */
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP    0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
+
+/* DMA_IRQ_STATUS Masks */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin dma registers layout
+ */
+struct bfin_dma_regs {
+        u32 next_desc_ptr;
+        u32 start_addr;
+        __BFP(config);
+        u32 __pad0;
+        __BFP(x_count);
+        __BFP(x_modify);
+        __BFP(y_count);
+        __BFP(y_modify);
+        u32 curr_desc_ptr;
+        u32 curr_addr;
+        __BFP(irq_status);
+        __BFP(peripheral_map);
+        __BFP(curr_x_count);
+        u32 __pad1;
+        __BFP(curr_y_count);
+        u32 __pad2;
+};
+
+/*
+ * bfin handshake mdma registers layout
+ */
+struct bfin_hmdma_regs {
+        __BFP(control);
+        __BFP(ecinit);
+        __BFP(bcinit);
+        __BFP(ecurgent);
+        __BFP(ecoverflow);
+        __BFP(ecount);
+        __BFP(bcount);
+};
+
+#undef __BFP
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
new file mode 100644
index 000000000000..1ff9f1468c02
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -0,0 +1,275 @@
+/*
+ * bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_ASM_SERIAL_H__
+#define __BFIN_ASM_SERIAL_H__
+
+#include <linux/serial_core.h>
+#include <mach/anomaly.h>
+#include <mach/bfin_serial.h>
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || \
+    defined(CONFIG_BFIN_UART1_CTSRTS) || \
+    defined(CONFIG_BFIN_UART2_CTSRTS) || \
+    defined(CONFIG_BFIN_UART3_CTSRTS)
+# ifdef BFIN_UART_BF54X_STYLE
+#  define CONFIG_SERIAL_BFIN_HARD_CTSRTS
+# else
+#  define CONFIG_SERIAL_BFIN_CTSRTS
+# endif
+#endif
+
+struct circ_buf;
+struct timer_list;
+struct work_struct;
+
+struct bfin_serial_port {
+        struct uart_port port;
+        unsigned int old_status;
+        int status_irq;
+#ifndef BFIN_UART_BF54X_STYLE
+        unsigned int lsr;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int tx_done;
+        int tx_count;
+        struct circ_buf rx_dma_buf;
+        struct timer_list rx_dma_timer;
+        int rx_dma_nrows;
+        unsigned int tx_dma_channel;
+        unsigned int rx_dma_channel;
+        struct work_struct tx_dma_workqueue;
+#elif ANOMALY_05000363
+        unsigned int anomaly_threshold;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        int scts;
+#endif
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+        int cts_pin;
+        int rts_pin;
+#endif
+};
+
+/* UART_LCR Masks */
+#define WLS(x)                   (((x)-5) & 0x03)  /* Word Length Select */
+#define STB                      0x04  /* Stop Bits */
+#define PEN                      0x08  /* Parity Enable */
+#define EPS                      0x10  /* Even Parity Select */
+#define STP                      0x20  /* Stick Parity */
+#define SB                       0x40  /* Set Break */
+#define DLAB                     0x80  /* Divisor Latch Access */
+
+/* UART_LSR Masks */
+#define DR                       0x01  /* Data Ready */
+#define OE                       0x02  /* Overrun Error */
+#define PE                       0x04  /* Parity Error */
+#define FE                       0x08  /* Framing Error */
+#define BI                       0x10  /* Break Interrupt */
+#define THRE                     0x20  /* THR Empty */
+#define TEMT                     0x40  /* TSR and UART_THR Empty */
+#define TFI                      0x80  /* Transmission Finished Indicator */
+
+/* UART_IER Masks */
+#define ERBFI                    0x01  /* Enable Receive Buffer Full Interrupt */
+#define ETBEI                    0x02  /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI                     0x04  /* Enable RX Status Interrupt */
+#define EDSSI                    0x08  /* Enable Modem Status Interrupt */
+#define EDTPTI                   0x10  /* Enable DMA Transmit PIRQ Interrupt */
+#define ETFI                     0x20  /* Enable Transmission Finished Interrupt */
+#define ERFCI                    0x40  /* Enable Receive FIFO Count Interrupt */
+
+/* UART_MCR Masks */
+#define XOFF                     0x01  /* Transmitter Off */
+#define MRTS                     0x02  /* Manual Request To Send */
+#define RFIT                     0x04  /* Receive FIFO IRQ Threshold */
+#define RFRT                     0x08  /* Receive FIFO RTS Threshold */
+#define LOOP_ENA                 0x10  /* Loopback Mode Enable */
+#define FCPOL                    0x20  /* Flow Control Pin Polarity */
+#define ARTS                     0x40  /* Automatic Request To Send */
+#define ACTS                     0x80  /* Automatic Clear To Send */
+
+/* UART_MSR Masks */
+#define SCTS                     0x01  /* Sticky CTS */
+#define CTS                      0x10  /* Clear To Send */
+#define RFCS                     0x20  /* Receive FIFO Count Status */
+
+/* UART_GCTL Masks */
+#define UCEN                     0x01  /* Enable UARTx Clocks */
+#define IREN                     0x02  /* Enable IrDA Mode */
+#define TPOLC                    0x04  /* IrDA TX Polarity Change */
+#define RPOLC                    0x08  /* IrDA RX Polarity Change */
+#define FPE                      0x10  /* Force Parity Error On Transmit */
+#define FFE                      0x20  /* Force Framing Error On Transmit */
+
+#ifdef BFIN_UART_BF54X_STYLE
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)        */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)       */
+# define OFFSET_GCTL             0x08  /* Global Control Register         */
+# define OFFSET_LCR              0x0C  /* Line Control Register           */
+# define OFFSET_MCR              0x10  /* Modem Control Register          */
+# define OFFSET_LSR              0x14  /* Line Status Register            */
+# define OFFSET_MSR              0x18  /* Modem Status Register           */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register            */
+# define OFFSET_IER_SET          0x20  /* Set Interrupt Enable Register   */
+# define OFFSET_IER_CLEAR        0x24  /* Clear Interrupt Enable Register */
+# define OFFSET_THR              0x28  /* Transmit Holding register       */
+# define OFFSET_RBR              0x2C  /* Receive Buffer register         */
+#else /* BF533 style */
+# define OFFSET_THR              0x00  /* Transmit Holding register         */
+# define OFFSET_RBR              0x00  /* Receive Buffer register           */
+# define OFFSET_DLL              0x00  /* Divisor Latch (Low-Byte)          */
+# define OFFSET_DLH              0x04  /* Divisor Latch (High-Byte)         */
+# define OFFSET_IER              0x04  /* Interrupt Enable Register         */
+# define OFFSET_IIR              0x08  /* Interrupt Identification Register */
+# define OFFSET_LCR              0x0C  /* Line Control Register             */
+# define OFFSET_MCR              0x10  /* Modem Control Register            */
+# define OFFSET_LSR              0x14  /* Line Status Register              */
+# define OFFSET_MSR              0x18  /* Modem Status Register             */
+# define OFFSET_SCR              0x1C  /* SCR Scratch Register              */
+# define OFFSET_GCTL             0x24  /* Global Control Register           */
+/* code should not need IIR, so force build error if they use it */
+# undef OFFSET_IIR
+#endif
+
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+struct bfin_uart_regs {
+#ifdef BFIN_UART_BF54X_STYLE
+        __BFP(dll);
+        __BFP(dlh);
+        __BFP(gctl);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        __BFP(ier_set);
+        __BFP(ier_clear);
+        __BFP(thr);
+        __BFP(rbr);
+#else
+        union {
+                u16 dll;
+                u16 thr;
+                const u16 rbr;
+        };
+        const u16 __pad0;
+        union {
+                u16 dlh;
+                u16 ier;
+        };
+        const u16 __pad1;
+        const __BFP(iir);
+        __BFP(lcr);
+        __BFP(mcr);
+        __BFP(lsr);
+        __BFP(msr);
+        __BFP(scr);
+        const u32 __pad2;
+        __BFP(gctl);
+#endif
+};
+#undef __BFP
+
+#ifndef port_membase
+# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
+#endif
+
+#define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
+#define UART_GET_DLL(p)       bfin_read16(port_membase(p) + OFFSET_DLL)
+#define UART_GET_DLH(p)       bfin_read16(port_membase(p) + OFFSET_DLH)
+#define UART_GET_GCTL(p)      bfin_read16(port_membase(p) + OFFSET_GCTL)
+#define UART_GET_LCR(p)       bfin_read16(port_membase(p) + OFFSET_LCR)
+#define UART_GET_MCR(p)       bfin_read16(port_membase(p) + OFFSET_MCR)
+#define UART_GET_MSR(p)       bfin_read16(port_membase(p) + OFFSET_MSR)
+
+#define UART_PUT_CHAR(p, v)   bfin_write16(port_membase(p) + OFFSET_THR, v)
+#define UART_PUT_DLL(p, v)    bfin_write16(port_membase(p) + OFFSET_DLL, v)
+#define UART_PUT_DLH(p, v)    bfin_write16(port_membase(p) + OFFSET_DLH, v)
+#define UART_PUT_GCTL(p, v)   bfin_write16(port_membase(p) + OFFSET_GCTL, v)
+#define UART_PUT_LCR(p, v)    bfin_write16(port_membase(p) + OFFSET_LCR, v)
+#define UART_PUT_MCR(p, v)    bfin_write16(port_membase(p) + OFFSET_MCR, v)
+
+#ifdef BFIN_UART_BF54X_STYLE
+
+#define UART_CLEAR_IER(p, v)  bfin_write16(port_membase(p) + OFFSET_IER_CLEAR, v)
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER_SET)
+#define UART_SET_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER_SET, v)
+
+#define UART_CLEAR_DLAB(p)    /* MMRs not muxed on BF54x */
+#define UART_SET_DLAB(p)      /* MMRs not muxed on BF54x */
+
+#define UART_CLEAR_LSR(p)     bfin_write16(port_membase(p) + OFFSET_LSR, -1)
+#define UART_GET_LSR(p)       bfin_read16(port_membase(p) + OFFSET_LSR)
+#define UART_PUT_LSR(p, v)    bfin_write16(port_membase(p) + OFFSET_LSR, v)
+
+/* This handles hard CTS/RTS */
+#define BFIN_UART_CTSRTS_HARD
+#define UART_CLEAR_SCTS(p)      bfin_write16((port_membase(p) + OFFSET_MSR), SCTS)
+#define UART_GET_CTS(x)         (UART_GET_MSR(x) & CTS)
+#define UART_DISABLE_RTS(x)     UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS | MRTS))
+#define UART_ENABLE_RTS(x)      UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
+#define UART_ENABLE_INTS(x, v)  UART_SET_IER(x, v)
+#define UART_DISABLE_INTS(x)    UART_CLEAR_IER(x, 0xF)
+
+#else /* BF533 style */
+
+#define UART_CLEAR_IER(p, v)  UART_PUT_IER(p, UART_GET_IER(p) & ~(v))
+#define UART_GET_IER(p)       bfin_read16(port_membase(p) + OFFSET_IER)
+#define UART_PUT_IER(p, v)    bfin_write16(port_membase(p) + OFFSET_IER, v)
+#define UART_SET_IER(p, v)    UART_PUT_IER(p, UART_GET_IER(p) | (v))
+
+#define UART_CLEAR_DLAB(p)    do { UART_PUT_LCR(p, UART_GET_LCR(p) & ~DLAB); SSYNC(); } while (0)
+#define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
+
+#ifndef put_lsr_cache
+# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
+#endif
+#ifndef get_lsr_cache
+# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
+#endif
+
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline void UART_CLEAR_LSR(void *p)
+{
+        put_lsr_cache(p, 0);
+        bfin_write16(port_membase(p) + OFFSET_LSR, -1);
+}
+static inline unsigned int UART_GET_LSR(void *p)
+{
+        unsigned int lsr = bfin_read16(port_membase(p) + OFFSET_LSR);
+        put_lsr_cache(p, get_lsr_cache(p) | (lsr & (BI|FE|PE|OE)));
+        return lsr | get_lsr_cache(p);
+}
+static inline void UART_PUT_LSR(void *p, uint16_t val)
+{
+        put_lsr_cache(p, get_lsr_cache(p) & ~val);
+}
+
+/* This handles soft CTS/RTS */
+#define UART_GET_CTS(x)        gpio_get_value((x)->cts_pin)
+#define UART_DISABLE_RTS(x)    gpio_set_value((x)->rts_pin, 1)
+#define UART_ENABLE_RTS(x)     gpio_set_value((x)->rts_pin, 0)
+#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
+#define UART_DISABLE_INTS(x)   UART_PUT_IER(x, 0)
+
+#endif
+
+#ifndef BFIN_UART_TX_FIFO_SIZE
+# define BFIN_UART_TX_FIFO_SIZE 2
+#endif
+
+#endif /* __BFIN_ASM_SERIAL_H__ */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 3f7ef4d97791..29f4fd886174 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -108,7 +108,9 @@ static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
 #define smp_mb__before_clear_bit()      barrier()
 #define smp_mb__after_clear_bit()       barrier()
 
+#define test_bit __skip_test_bit
 #include <asm-generic/bitops/non-atomic.h>
+#undef test_bit
 
 #endif /* CONFIG_SMP */
 
diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h
index bd0641a267f1..568885a2c286 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,6 +7,8 @@
 #ifndef __ARCH_BLACKFIN_CACHE_H
 #define __ARCH_BLACKFIN_CACHE_H
 
+#include <linux/linkage.h>      /* for asmlinkage */
+
 /*
  * Bytes per L1 cache line
  * Blackfin loads 32 bytes for cache
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 2666ff8ea952..77135b62818e 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -11,6 +11,9 @@
 
 #include <asm/blackfin.h>       /* for SSYNC() */
 #include <asm/sections.h>       /* for _ramend */
+#ifdef CONFIG_SMP
+#include <asm/smp.h>
+#endif
 
 extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
 extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h
index eedf3ca65ba2..d9dbc1a53534 100644
--- a/arch/blackfin/include/asm/dma.h
+++ b/arch/blackfin/include/asm/dma.h
@@ -14,40 +14,7 @@
 #include <asm/blackfin.h>
 #include <asm/page.h>
 #include <asm-generic/dma.h>
-
-/* DMA_CONFIG Masks */
-#define DMAEN                   0x0001  /* DMA Channel Enable */
-#define WNR                             0x0002  /* Channel Direction (W/R*) */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8 */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16 */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32 */
-#define DMA2D                   0x0010  /* DMA Mode (2D/1D*) */
-#define RESTART                 0x0020  /* DMA Buffer Clear */
-#define DI_SEL                  0x0040  /* Data Interrupt Timing Select */
-#define DI_EN                   0x0080  /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1 */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2 */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3 */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4 */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5 */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6 */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7 */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8 */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9 */
-#define NDSIZE                  0x0f00  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP    0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO    0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY   0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL   0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE   0x7000  /* Large Model Descriptor List Mode */
-
-/* DMA_IRQ_STATUS Masks */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator */
+#include <asm/bfin_dma.h>
 
 /*-------------------------
  * config reg bits value
@@ -149,7 +116,7 @@ void blackfin_dma_resume(void);
 *       DMA API's
 *******************************************************************************/
 extern struct dma_channel dma_ch[MAX_DMA_CHANNELS];
-extern struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS];
+extern struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS];
 extern int channel2irq(unsigned int channel);
 
 static inline void set_dma_start_addr(unsigned int channel, unsigned long addr)
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index efcc3aebeae4..3047120cfcff 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -9,6 +9,8 @@
 #ifndef _BLACKFIN_DPMC_H_
 #define _BLACKFIN_DPMC_H_
 
+#include <mach/pll.h>
+
 /* PLL_CTL Masks */
 #define DF                      0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
 #define PLL_OFF                 0x0002  /* PLL Not Powered */
diff --git a/arch/blackfin/include/asm/io.h b/arch/blackfin/include/asm/io.h
index 234fbac17ec1..dccae26805b0 100644
--- a/arch/blackfin/include/asm/io.h
+++ b/arch/blackfin/include/asm/io.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2009 Analog Devices Inc.
+ * Copyright 2004-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,148 +7,48 @@
 #ifndef _BFIN_IO_H
 #define _BFIN_IO_H
 
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
 #include <linux/compiler.h>
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = b [%2] (z);"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = w [%2] (z);"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ (
-                "cli %1;"
-                "NOP; NOP; SSYNC;"
-                "%0 = [%2];"
-                "sti %1;"
-                : "=d"(val), "=d"(tmp)
-                : "a"(addr)
-        );
-
-        return val;
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+#define DECLARE_BFIN_RAW_READX(size, type, asm, asm_sign) \
+static inline type __raw_read##size(const volatile void __iomem *addr) \
+{ \
+        unsigned int val; \
+        int tmp; \
+        __asm__ __volatile__ ( \
+                "cli %1;" \
+                "NOP; NOP; SSYNC;" \
+                "%0 = "#asm" [%2] "#asm_sign";" \
+                "sti %1;" \
+                : "=d"(val), "=d"(tmp) \
+                : "a"(addr) \
+        ); \
+        return (type) val; \
 }
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c)      memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)  memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)    memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port)    readb(__io(port))
-#define inw(port)    readw(__io(port))
-#define inl(port)    readl(__io(port))
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-
-#define inb_p(port)    inb(__io(port))
-#define inw_p(port)    inw(__io(port))
-#define inl_p(port)    inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c)    readsb(a, d, c)
-#define ioread16_rep(a, d, c)   readsw(a, d, c)
-#define ioread32_rep(a, d, c)   readsl(a, d, c)
-#define iowrite8_rep(a, s, c)   writesb(a, s, c)
-#define iowrite16_rep(a, s, c)  writesw(a, s, c)
-#define iowrite32_rep(a, s, c)  writesl(a, s, c)
-
-#define ioread8(x)                      readb(x)
-#define ioread16(x)                     readw(x)
-#define ioread32(x)                     readl(x)
-#define iowrite8(val, x)                writeb(val, x)
-#define iowrite16(val, x)               writew(val, x)
-#define iowrite32(val, x)               writel(val, x)
-
-/**
- * I/O write barrier
- *
- * Ensure ordering of I/O space writes. This will make sure that writes
- * following the barrier will arrive after all previous writes.
- */
-#define mmiowb() do { SSYNC(); wmb(); } while (0)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_NOCACHE_SER               1
-
-#ifndef __ASSEMBLY__
+DECLARE_BFIN_RAW_READX(b, u8, b, (z))
+#define __raw_readb __raw_readb
+DECLARE_BFIN_RAW_READX(w, u16, w, (z))
+#define __raw_readw __raw_readw
+DECLARE_BFIN_RAW_READX(l, u32, , )
+#define __raw_readl __raw_readl
 
 extern void outsb(unsigned long port, const void *addr, unsigned long count);
 extern void outsw(unsigned long port, const void *addr, unsigned long count);
 extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
 extern void outsl(unsigned long port, const void *addr, unsigned long count);
+#define outsb outsb
+#define outsw outsw
+#define outsl outsl
 
 extern void insb(unsigned long port, void *addr, unsigned long count);
 extern void insw(unsigned long port, void *addr, unsigned long count);
 extern void insw_8(unsigned long port, void *addr, unsigned long count);
 extern void insl(unsigned long port, void *addr, unsigned long count);
 extern void insl_16(unsigned long port, void *addr, unsigned long count);
+#define insb insb
+#define insw insw
+#define insl insl
 
 extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
 extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
@@ -158,108 +58,14 @@ extern void dma_insb(unsigned long port, void *addr, unsigned short count);
 extern void dma_insw(unsigned long port, void *addr, unsigned short count);
 extern void dma_insl(unsigned long port, void *addr, unsigned short count);
 
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
-        insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
-        insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
-        insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
-        outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
-        outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
-        outsb((unsigned long)addr, buf, len);
-}
-
-/*
- * Map some physical address range into the kernel address space.
- */
-static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
-                                int cacheflag)
-{
-        return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-static inline void iounmap(void *addr)
-{
-}
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-static inline void __iounmap(void *addr, unsigned long size)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
+/**
+ * I/O write barrier
+ *
+ * Ensure ordering of I/O space writes. This will make sure that writes
+ * following the barrier will arrive after all previous writes.
  */
-static inline void kernel_set_cachemode(void *addr, unsigned long size,
-                                        int cmode)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void __iomem *ioremap_nocache(unsigned long physaddr,
-                                            unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
+#define mmiowb() do { SSYNC(); wmb(); } while (0)
 
-extern void blkfin_inv_cache_all(void);
+#include <asm-generic/io.h>
 
 #endif
-
-#define ioport_map(port, nr)            ((void __iomem*)(port))
-#define ioport_unmap(addr)
-
-/* Pages to physical address... */
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_IO_H */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 41c4d70544ef..3365cb97f539 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -13,9 +13,6 @@
 #ifdef CONFIG_SMP
 # include <asm/pda.h>
 # include <asm/processor.h>
-/* Forward decl needed due to cdef inter dependencies */
-static inline uint32_t __pure bfin_dspid(void);
-# define blackfin_core_id() (bfin_dspid() & 0xff)
 # define bfin_irq_flags cpu_pda[blackfin_core_id()].imask
 #else
 extern unsigned long bfin_irq_flags;
diff --git a/arch/blackfin/include/asm/processor.h b/arch/blackfin/include/asm/processor.h
index aea880274de7..8af7772e84cc 100644
--- a/arch/blackfin/include/asm/processor.h
+++ b/arch/blackfin/include/asm/processor.h
@@ -14,7 +14,7 @@
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
 #include <asm/ptrace.h>
-#include <asm/blackfin.h>
+#include <mach/blackfin.h>
 
 static inline unsigned long rdusp(void)
 {
@@ -134,6 +134,8 @@ static inline uint32_t __pure bfin_dspid(void)
         return bfin_read_DSPID();
 }
 
+#define blackfin_core_id() (bfin_dspid() & 0xff)
+
 static inline uint32_t __pure bfin_compiled_revid(void)
 {
 #if defined(CONFIG_BF_REV_0_0)
diff --git a/arch/blackfin/include/asm/spinlock.h b/arch/blackfin/include/asm/spinlock.h
index 1942ccfedbe0..1f286e71c21f 100644
--- a/arch/blackfin/include/asm/spinlock.h
+++ b/arch/blackfin/include/asm/spinlock.h
@@ -17,12 +17,12 @@ asmlinkage int __raw_spin_is_locked_asm(volatile int *ptr);
 asmlinkage void __raw_spin_lock_asm(volatile int *ptr);
 asmlinkage int __raw_spin_trylock_asm(volatile int *ptr);
 asmlinkage void __raw_spin_unlock_asm(volatile int *ptr);
-asmlinkage void arch_read_lock_asm(volatile int *ptr);
-asmlinkage int arch_read_trylock_asm(volatile int *ptr);
-asmlinkage void arch_read_unlock_asm(volatile int *ptr);
-asmlinkage void arch_write_lock_asm(volatile int *ptr);
-asmlinkage int arch_write_trylock_asm(volatile int *ptr);
-asmlinkage void arch_write_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_read_lock_asm(volatile int *ptr);
+asmlinkage int __raw_read_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_read_unlock_asm(volatile int *ptr);
+asmlinkage void __raw_write_lock_asm(volatile int *ptr);
+asmlinkage int __raw_write_trylock_asm(volatile int *ptr);
+asmlinkage void __raw_write_unlock_asm(volatile int *ptr);
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
@@ -64,32 +64,36 @@ static inline int arch_write_can_lock(arch_rwlock_t *rw)
 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {
-        arch_read_lock_asm(&rw->lock);
+        __raw_read_lock_asm(&rw->lock);
 }
 
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+
 static inline int arch_read_trylock(arch_rwlock_t *rw)
 {
-        return arch_read_trylock_asm(&rw->lock);
+        return __raw_read_trylock_asm(&rw->lock);
 }
 
 static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
-        arch_read_unlock_asm(&rw->lock);
+        __raw_read_unlock_asm(&rw->lock);
 }
 
 static inline void arch_write_lock(arch_rwlock_t *rw)
 {
-        arch_write_lock_asm(&rw->lock);
+        __raw_write_lock_asm(&rw->lock);
 }
 
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
 static inline int arch_write_trylock(arch_rwlock_t *rw)
 {
-        return arch_write_trylock_asm(&rw->lock);
+        return __raw_write_trylock_asm(&rw->lock);
 }
 
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
-        arch_write_unlock_asm(&rw->lock);
+        __raw_write_unlock_asm(&rw->lock);
 }
 
 #define arch_spin_relax(lock)   cpu_relax()
diff --git a/arch/blackfin/include/mach-common/pll.h b/arch/blackfin/include/mach-common/pll.h
new file mode 100644
index 000000000000..382178b361af
--- /dev/null
+++ b/arch/blackfin/include/mach-common/pll.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2005-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _MACH_COMMON_PLL_H
+#define _MACH_COMMON_PLL_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/blackfin.h>
+#include <asm/irqflags.h>
+
+#ifndef bfin_iwr_restore
+static inline void
+bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
+{
+#ifdef SIC_IWR
+        bfin_write_SIC_IWR(iwr0);
+#else
+        bfin_write_SIC_IWR0(iwr0);
+# ifdef SIC_IWR1
+        bfin_write_SIC_IWR1(iwr1);
+# endif
+# ifdef SIC_IWR2
+        bfin_write_SIC_IWR2(iwr2);
+# endif
+#endif
+}
+#endif
+
+#ifndef bfin_iwr_save
+static inline void
+bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
+              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
+{
+#ifdef SIC_IWR
+        *iwr0 = bfin_read_SIC_IWR();
+#else
+        *iwr0 = bfin_read_SIC_IWR0();
+# ifdef SIC_IWR1
+        *iwr1 = bfin_read_SIC_IWR1();
+# endif
+# ifdef SIC_IWR2
+        *iwr2 = bfin_read_SIC_IWR2();
+# endif
+#endif
+        bfin_iwr_restore(niwr0, niwr1, niwr2);
+}
+#endif
+
+static inline void _bfin_write_pll_relock(u32 addr, unsigned int val)
+{
+        unsigned long flags, iwr0, iwr1, iwr2;
+
+        if (val == bfin_read_PLL_CTL())
+                return;
+
+        flags = hard_local_irq_save();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        bfin_iwr_save(IWR_ENABLE(0), 0, 0, &iwr0, &iwr1, &iwr2);
+
+        bfin_write16(addr, val);
+        SSYNC();
+        asm("IDLE;");
+
+        bfin_iwr_restore(iwr0, iwr1, iwr2);
+        hard_local_irq_restore(flags);
+}
+
+/* Writing to PLL_CTL initiates a PLL relock sequence */
+static inline void bfin_write_PLL_CTL(unsigned int val)
+{
+        _bfin_write_pll_relock(PLL_CTL, val);
+}
+
+/* Writing to VR_CTL initiates a PLL relock sequence */
+static inline void bfin_write_VR_CTL(unsigned int val)
+{
+        _bfin_write_pll_relock(VR_CTL, val);
+}
+
+#endif
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-a.h b/arch/blackfin/include/mach-common/ports-a.h
new file mode 100644
index 000000000000..9f78a761c40a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-a.h
@@ -0,0 +1,25 @@
+/*
+ * Port A Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_A__
+#define __BFIN_PERIPHERAL_PORT_A__
+
+#define PA0             (1 << 0)
+#define PA1             (1 << 1)
+#define PA2             (1 << 2)
+#define PA3             (1 << 3)
+#define PA4             (1 << 4)
+#define PA5             (1 << 5)
+#define PA6             (1 << 6)
+#define PA7             (1 << 7)
+#define PA8             (1 << 8)
+#define PA9             (1 << 9)
+#define PA10            (1 << 10)
+#define PA11            (1 << 11)
+#define PA12            (1 << 12)
+#define PA13            (1 << 13)
+#define PA14            (1 << 14)
+#define PA15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-b.h b/arch/blackfin/include/mach-common/ports-b.h
new file mode 100644
index 000000000000..b81702f09ec6
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-b.h
@@ -0,0 +1,25 @@
+/*
+ * Port B Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_B__
+#define __BFIN_PERIPHERAL_PORT_B__
+
+#define PB0             (1 << 0)
+#define PB1             (1 << 1)
+#define PB2             (1 << 2)
+#define PB3             (1 << 3)
+#define PB4             (1 << 4)
+#define PB5             (1 << 5)
+#define PB6             (1 << 6)
+#define PB7             (1 << 7)
+#define PB8             (1 << 8)
+#define PB9             (1 << 9)
+#define PB10            (1 << 10)
+#define PB11            (1 << 11)
+#define PB12            (1 << 12)
+#define PB13            (1 << 13)
+#define PB14            (1 << 14)
+#define PB15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-c.h b/arch/blackfin/include/mach-common/ports-c.h
new file mode 100644
index 000000000000..3cc665e0ba08
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-c.h
@@ -0,0 +1,25 @@
+/*
+ * Port C Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_C__
+#define __BFIN_PERIPHERAL_PORT_C__
+
+#define PC0             (1 << 0)
+#define PC1             (1 << 1)
+#define PC2             (1 << 2)
+#define PC3             (1 << 3)
+#define PC4             (1 << 4)
+#define PC5             (1 << 5)
+#define PC6             (1 << 6)
+#define PC7             (1 << 7)
+#define PC8             (1 << 8)
+#define PC9             (1 << 9)
+#define PC10            (1 << 10)
+#define PC11            (1 << 11)
+#define PC12            (1 << 12)
+#define PC13            (1 << 13)
+#define PC14            (1 << 14)
+#define PC15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-d.h b/arch/blackfin/include/mach-common/ports-d.h
new file mode 100644
index 000000000000..868c6a01f1b2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-d.h
@@ -0,0 +1,25 @@
+/*
+ * Port D Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_D__
+#define __BFIN_PERIPHERAL_PORT_D__
+
+#define PD0             (1 << 0)
+#define PD1             (1 << 1)
+#define PD2             (1 << 2)
+#define PD3             (1 << 3)
+#define PD4             (1 << 4)
+#define PD5             (1 << 5)
+#define PD6             (1 << 6)
+#define PD7             (1 << 7)
+#define PD8             (1 << 8)
+#define PD9             (1 << 9)
+#define PD10            (1 << 10)
+#define PD11            (1 << 11)
+#define PD12            (1 << 12)
+#define PD13            (1 << 13)
+#define PD14            (1 << 14)
+#define PD15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-e.h b/arch/blackfin/include/mach-common/ports-e.h
new file mode 100644
index 000000000000..c88b0d0dd443
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-e.h
@@ -0,0 +1,25 @@
+/*
+ * Port E Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_E__
+#define __BFIN_PERIPHERAL_PORT_E__
+
+#define PE0             (1 << 0)
+#define PE1             (1 << 1)
+#define PE2             (1 << 2)
+#define PE3             (1 << 3)
+#define PE4             (1 << 4)
+#define PE5             (1 << 5)
+#define PE6             (1 << 6)
+#define PE7             (1 << 7)
+#define PE8             (1 << 8)
+#define PE9             (1 << 9)
+#define PE10            (1 << 10)
+#define PE11            (1 << 11)
+#define PE12            (1 << 12)
+#define PE13            (1 << 13)
+#define PE14            (1 << 14)
+#define PE15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-f.h b/arch/blackfin/include/mach-common/ports-f.h
new file mode 100644
index 000000000000..d6af20633278
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-f.h
@@ -0,0 +1,25 @@
+/*
+ * Port F Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_F__
+#define __BFIN_PERIPHERAL_PORT_F__
+
+#define PF0             (1 << 0)
+#define PF1             (1 << 1)
+#define PF2             (1 << 2)
+#define PF3             (1 << 3)
+#define PF4             (1 << 4)
+#define PF5             (1 << 5)
+#define PF6             (1 << 6)
+#define PF7             (1 << 7)
+#define PF8             (1 << 8)
+#define PF9             (1 << 9)
+#define PF10            (1 << 10)
+#define PF11            (1 << 11)
+#define PF12            (1 << 12)
+#define PF13            (1 << 13)
+#define PF14            (1 << 14)
+#define PF15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-g.h b/arch/blackfin/include/mach-common/ports-g.h
new file mode 100644
index 000000000000..09355d333c0e
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-g.h
@@ -0,0 +1,25 @@
+/*
+ * Port G Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_G__
+#define __BFIN_PERIPHERAL_PORT_G__
+
+#define PG0             (1 << 0)
+#define PG1             (1 << 1)
+#define PG2             (1 << 2)
+#define PG3             (1 << 3)
+#define PG4             (1 << 4)
+#define PG5             (1 << 5)
+#define PG6             (1 << 6)
+#define PG7             (1 << 7)
+#define PG8             (1 << 8)
+#define PG9             (1 << 9)
+#define PG10            (1 << 10)
+#define PG11            (1 << 11)
+#define PG12            (1 << 12)
+#define PG13            (1 << 13)
+#define PG14            (1 << 14)
+#define PG15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-h.h b/arch/blackfin/include/mach-common/ports-h.h
new file mode 100644
index 000000000000..fa3910c6fbd4
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-h.h
@@ -0,0 +1,25 @@
+/*
+ * Port H Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_H__
+#define __BFIN_PERIPHERAL_PORT_H__
+
+#define PH0             (1 << 0)
+#define PH1             (1 << 1)
+#define PH2             (1 << 2)
+#define PH3             (1 << 3)
+#define PH4             (1 << 4)
+#define PH5             (1 << 5)
+#define PH6             (1 << 6)
+#define PH7             (1 << 7)
+#define PH8             (1 << 8)
+#define PH9             (1 << 9)
+#define PH10            (1 << 10)
+#define PH11            (1 << 11)
+#define PH12            (1 << 12)
+#define PH13            (1 << 13)
+#define PH14            (1 << 14)
+#define PH15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-i.h b/arch/blackfin/include/mach-common/ports-i.h
new file mode 100644
index 000000000000..f176f08af624
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-i.h
@@ -0,0 +1,25 @@
+/*
+ * Port I Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_I__
+#define __BFIN_PERIPHERAL_PORT_I__
+
+#define PI0             (1 << 0)
+#define PI1             (1 << 1)
+#define PI2             (1 << 2)
+#define PI3             (1 << 3)
+#define PI4             (1 << 4)
+#define PI5             (1 << 5)
+#define PI6             (1 << 6)
+#define PI7             (1 << 7)
+#define PI8             (1 << 8)
+#define PI9             (1 << 9)
+#define PI10            (1 << 10)
+#define PI11            (1 << 11)
+#define PI12            (1 << 12)
+#define PI13            (1 << 13)
+#define PI14            (1 << 14)
+#define PI15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/include/mach-common/ports-j.h b/arch/blackfin/include/mach-common/ports-j.h
new file mode 100644
index 000000000000..924123ecec5a
--- /dev/null
+++ b/arch/blackfin/include/mach-common/ports-j.h
@@ -0,0 +1,25 @@
+/*
+ * Port J Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT_J__
+#define __BFIN_PERIPHERAL_PORT_J__
+
+#define PJ0             (1 << 0)
+#define PJ1             (1 << 1)
+#define PJ2             (1 << 2)
+#define PJ3             (1 << 3)
+#define PJ4             (1 << 4)
+#define PJ5             (1 << 5)
+#define PJ6             (1 << 6)
+#define PJ7             (1 << 7)
+#define PJ8             (1 << 8)
+#define PJ9             (1 << 9)
+#define PJ10            (1 << 10)
+#define PJ11            (1 << 11)
+#define PJ12            (1 << 12)
+#define PJ13            (1 << 13)
+#define PJ14            (1 << 14)
+#define PJ15            (1 << 15)
+
+#endif
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index bfe75af4e8bd..886e00014d75 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -116,7 +116,7 @@ void __init generate_cplb_tables_all(void)
             ((_ramend - uncached_end) >= 1 * 1024 * 1024))
                 dcplb_bounds[i_d].eaddr = uncached_end;
         else
-                dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024);
+                dcplb_bounds[i_d].eaddr = uncached_end & ~(1 * 1024 * 1024 - 1);
         dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
         /* DMA uncached region.  */
         if (DMA_UNCACHED_REGION) {
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index edae461b1c54..eb92592fd80c 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -345,6 +345,23 @@ void kgdb_roundup_cpu(int cpu, unsigned long flags)
 }
 #endif
 
+#ifdef CONFIG_IPIPE
+static unsigned long kgdb_arch_imask;
+#endif
+
+void kgdb_post_primary_code(struct pt_regs *regs, int e_vector, int err_code)
+{
+        if (kgdb_single_step)
+                preempt_enable();
+
+#ifdef CONFIG_IPIPE
+        if (kgdb_arch_imask) {
+                cpu_pda[raw_smp_processor_id()].ex_imask = kgdb_arch_imask;
+                kgdb_arch_imask = 0;
+        }
+#endif
+}
+
 int kgdb_arch_handle_exception(int vector, int signo,
                                int err_code, char *remcom_in_buffer,
                                char *remcom_out_buffer,
@@ -388,6 +405,12 @@ int kgdb_arch_handle_exception(int vector, int signo,
                          * kgdb_single_step > 0 means in single step mode
                          */
                         kgdb_single_step = i + 1;
+
+                        preempt_disable();
+#ifdef CONFIG_IPIPE
+                        kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
+                        cpu_pda[raw_smp_processor_id()].ex_imask = 0;
+#endif
                 }
 
                 bfin_correct_hw_break();
@@ -448,6 +471,9 @@ void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
 int kgdb_arch_init(void)
 {
         kgdb_single_step = 0;
+#ifdef CONFIG_IPIPE
+        kgdb_arch_imask = 0;
+#endif
 
         bfin_remove_all_hw_break();
         return 0;
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 08c0236acf3c..2a6e9dbb62a5 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -95,6 +95,10 @@ static int __init kgdbtest_init(void)
 {
         struct proc_dir_entry *entry;
 
+#if L2_LENGTH
+        num2 = 0;
+#endif
+
         entry = proc_create("kgdbtest", 0, NULL, &kgdb_test_proc_fops);
         if (entry == NULL)
                 return -ENOMEM;
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index b894c8abe7ec..c0ccadcfa44e 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -104,24 +104,23 @@ static const unsigned short bfin_mac_peripherals[] = {
 
 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
         {
-                .addr = 1,
-                .irq = IRQ_MAC_PHYINT,
-        },
-        {
-                .addr = 2,
-                .irq = IRQ_MAC_PHYINT,
-        },
-        {
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
                 .addr = 3,
+#else
+                .addr = 1,
+#endif
                 .irq = IRQ_MAC_PHYINT,
         },
 };
 
 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
-        .phydev_number = 3,
+        .phydev_number = 1,
         .phydev_data = bfin_phydev_data,
         .phy_mode = PHY_INTERFACE_MODE_MII,
         .mac_peripherals = bfin_mac_peripherals,
+#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
+        .phy_mask = 0xfff7, /* Only probe the port phy connect to the on chip MAC */
+#endif
 };
 
 static struct platform_device bfin_mii_bus = {
@@ -453,7 +452,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -496,7 +495,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -636,9 +635,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -670,9 +669,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/boards/tcm-bf518.c b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
index e6ce1d7c523a..50fc5c89e379 100644
--- a/arch/blackfin/mach-bf518/boards/tcm-bf518.c
+++ b/arch/blackfin/mach-bf518/boards/tcm-bf518.c
@@ -377,7 +377,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -420,7 +420,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -547,9 +547,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -581,9 +581,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf518/dma.c b/arch/blackfin/mach-bf518/dma.c
index 78b43605a0b5..bcd1fbc8c543 100644
--- a/arch/blackfin/mach-bf518/dma.c
+++ b/arch/blackfin/mach-bf518/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index 970d310021e7..f6d924ac0c44 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        int status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long uart_base_addr;
         int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/blackfin.h b/arch/blackfin/mach-bf518/include/mach/blackfin.h
index 9053462be4b1..a8828863226e 100644
--- a/arch/blackfin/mach-bf518/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf518/include/mach/blackfin.h
@@ -1,61 +1,43 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
 #define _MACH_BLACKFIN_H_
 
 #include "bf518.h"
-#include "defBF512.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF518)
-#include "defBF518.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF512
+# include "defBF512.h"
 #endif
-
-#if defined(CONFIG_BF516)
-#include "defBF516.h"
-#endif
-
-#if defined(CONFIG_BF514)
-#include "defBF514.h"
+#ifdef CONFIG_BF514
+# include "defBF514.h"
 #endif
-
-#if defined(CONFIG_BF512)
-#include "defBF512.h"
+#ifdef CONFIG_BF516
+# include "defBF516.h"
 #endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF512.h"
-
-#if defined(CONFIG_BF518)
-#include "cdefBF518.h"
+#ifdef CONFIG_BF518
+# include "defBF518.h"
 #endif
 
-#if defined(CONFIG_BF516)
-#include "cdefBF516.h"
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF512
+#  include "cdefBF512.h"
+# endif
+# ifdef CONFIG_BF514
+#  include "cdefBF514.h"
+# endif
+# ifdef CONFIG_BF516
+#  include "cdefBF516.h"
+# endif
+# ifdef CONFIG_BF518
+#  include "cdefBF518.h"
+# endif
 #endif
 
-#if defined(CONFIG_BF514)
-#include "cdefBF514.h"
-#endif
-#endif
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index 493020d0a65a..b657d37a3402 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,15 +7,1037 @@
 #ifndef _CDEF_BF512_H
 #define _CDEF_BF512_H
 
-/* include all Core registers and bit definitions */
-#include "defBF512.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
 
-/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "cdefBF51x_base.h"
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMAC_TC_PER()                 bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)             bfin_write16(DMAC_TC_PER, val)
+#define bfin_read_DMAC_TC_CNT()                 bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)             bfin_write16(DMAC_TC_CNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
 
 #endif /* _CDEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index 108fa4bde277..dc988668203e 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF514_H
 #define _CDEF_BF514_H
 
-/* include all Core registers and bit definitions */
-#include "defBF514.h"
-
 /* BF514 is BF512 + RSI */
 #include "cdefBF512.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 2751592ef1c1..142e45cbc253 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF516_H
 #define _CDEF_BF516_H
 
-/* include all Core registers and bit definitions */
-#include "defBF516.h"
-
 /* BF516 is BF514 + EMAC */
 #include "cdefBF514.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 7fb7f0eab990..e638197bf8b1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF518_H
 #define _CDEF_BF518_H
 
-/* include all Core registers and bit definitions */
-#include "defBF518.h"
-
 /* BF518 is BF516 + IEEE-1588 */
 #include "cdefBF516.h"
 
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
deleted file mode 100644
index e16969f24ffd..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF51x_base.h
+++ /dev/null
@@ -1,1061 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF51x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF51x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 9b505bb0cb2d..27285823fb25 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,12 +7,1388 @@
 #ifndef _DEF_BF512_H
 #define _DEF_BF512_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
+/* ************************************************************** */
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF512 */
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register                           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID                          0xFFC00014      /* Device ID Register */
 
-/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
-#include "defBF51x_base.h"
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                                */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                                */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register                      */
+
+#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                              */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                              */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                              */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                              */
+#define SIC_ISR0                        0xFFC00120      /* Interrupt Status Register                                    */
+#define SIC_IWR0                        0xFFC00124      /* Interrupt Wakeup Register                                    */
+
+/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+/* SPI0 Controller                      (0xFFC00500 - 0xFFC005FF)                                                       */
+#define SPI0_REGBASE                    0xFFC00500
+#define SPI0_CTL                        0xFFC00500      /* SPI Control Register                                         */
+#define SPI0_FLG                        0xFFC00504      /* SPI Flag register                                            */
+#define SPI0_STAT                       0xFFC00508      /* SPI Status register                                          */
+#define SPI0_TDBR                       0xFFC0050C      /* SPI Transmit Data Buffer Register                            */
+#define SPI0_RDBR                       0xFFC00510      /* SPI Receive Data Buffer Register                             */
+#define SPI0_BAUD                       0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI0_SHADOW                     0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+/* SPI1 Controller                      (0xFFC03400 - 0xFFC034FF)                                                       */
+#define SPI1_REGBASE                    0xFFC03400
+#define SPI1_CTL                        0xFFC03400      /* SPI Control Register                                         */
+#define SPI1_FLG                        0xFFC03404      /* SPI Flag register                                            */
+#define SPI1_STAT                       0xFFC03408      /* SPI Status register                                          */
+#define SPI1_TDBR                       0xFFC0340C      /* SPI Transmit Data Buffer Register                            */
+#define SPI1_RDBR                       0xFFC03410      /* SPI Receive Data Buffer Register                             */
+#define SPI1_BAUD                       0xFFC03414      /* SPI Baud rate Register                                       */
+#define SPI1_SHADOW                     0xFFC03418      /* SPI_RDBR Shadow Register                                     */
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+
+#if 0
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+#endif
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTL Masks                                                                                                 */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* Motor Control PWM Registers */
+
+#define                         PWM_CTRL  0xffc03700   /* PWM Control Register */
+#define                         PWM_STAT  0xffc03704   /* PWM Status Register */
+#define                           PWM_TM  0xffc03708   /* PWM Period Register */
+#define                           PWM_DT  0xffc0370c   /* PWM Dead Time Register */
+#define                         PWM_GATE  0xffc03710   /* PWM Chopping Control */
+#define                          PWM_CHA  0xffc03714   /* PWM Channel A Duty Control */
+#define                          PWM_CHB  0xffc03718   /* PWM Channel B Duty Control */
+#define                          PWM_CHC  0xffc0371c   /* PWM Channel C Duty Control */
+#define                          PWM_SEG  0xffc03720   /* PWM Crossover and Output Enable */
+#define                       PWM_SYNCWT  0xffc03724   /* PWM Sync Pluse Width Control */
+#define                         PWM_CHAL  0xffc03728   /* PWM Channel AL Duty Control (SR mode only) */
+#define                         PWM_CHBL  0xffc0372c   /* PWM Channel BL Duty Control (SR mode only) */
+#define                         PWM_CHCL  0xffc03730   /* PWM Channel CL Duty Control (SR mode only) */
+#define                          PWM_LSI  0xffc03734   /* PWM Low Side Invert (SR mode only) */
+#define                        PWM_STAT2  0xffc03738   /* PWM Status Register 2 */
+
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
+#define                  HOST_CNTR_nHOST_EN  0x0
+#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
+#define                 HOST_CNTR_nHOST_END  0x0
+#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
+#define                HOST_CNTR_nDATA_SIZE  0x0
+#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
+#define                 HOST_CNTR_nHOST_RST  0x0
+#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
+#define                 HOST_CNTR_nHRDY_OVR  0x0
+#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
+#define                 HOST_CNTR_nINT_MODE  0x0
+#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
+#define                   HOST_CNTR_ nBT_EN  0x0
+#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
+#define                      HOST_CNTR_nEHW  0x0
+#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
+#define                      HOST_CNTR_nEHR  0x0
+#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
+#define                      HOST_CNTR_nBDR  0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define                     HOST_STAT_READY  0x1        /* DMA Ready */
+#define                    HOST_STAT_nREADY  0x0
+#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
+#define                 HOST_STAT_nFIFOFULL  0x0
+#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
+#define                HOST_STAT_nFIFOEMPTY  0x0
+#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
+#define                 HOST_STAT_nCOMPLETE  0x0
+#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
+#define                     HOST_STAT_nHSHK  0x0
+#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
+#define                  HOST_STAT_nTIMEOUT  0x0
+#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
+#define                     HOST_STAT_nHIRQ  0x0
+#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               HOST_STAT_nALLOW_CNFG  0x0
+#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
+#define                  HOST_STAT_nDMA_DIR  0x0
+#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
+#define                      HOST_STAT_nBTE  0x0
+#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              HOST_STAT_nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0
+#define                   SECSTAT  0xe0       /* Secure Status */
 
 #endif /* _DEF_BF512_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
deleted file mode 100644
index 5f84913dcd91..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ /dev/null
@@ -1,1495 +0,0 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF51X_H
-#define _DEF_BF51X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF51x    */
-/* ************************************************************** */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register                           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID                          0xFFC00014      /* Device ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                                */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                                */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register                      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                              */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                              */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                              */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                              */
-#define SIC_ISR0                        0xFFC00120      /* Interrupt Status Register                                    */
-#define SIC_IWR0                        0xFFC00124      /* Interrupt Wakeup Register                                    */
-
-/* SIC Additions to ADSP-BF51x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-/* SPI0 Controller                      (0xFFC00500 - 0xFFC005FF)                                                       */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI0_CTL                        0xFFC00500      /* SPI Control Register                                         */
-#define SPI0_FLG                        0xFFC00504      /* SPI Flag register                                            */
-#define SPI0_STAT                       0xFFC00508      /* SPI Status register                                          */
-#define SPI0_TDBR                       0xFFC0050C      /* SPI Transmit Data Buffer Register                            */
-#define SPI0_RDBR                       0xFFC00510      /* SPI Receive Data Buffer Register                             */
-#define SPI0_BAUD                       0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI0_SHADOW                     0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-/* SPI1 Controller                      (0xFFC03400 - 0xFFC034FF)                                                       */
-#define SPI1_REGBASE                    0xFFC03400
-#define SPI1_CTL                        0xFFC03400      /* SPI Control Register                                         */
-#define SPI1_FLG                        0xFFC03404      /* SPI Flag register                                            */
-#define SPI1_STAT                       0xFFC03408      /* SPI Status register                                          */
-#define SPI1_TDBR                       0xFFC0340C      /* SPI Transmit Data Buffer Register                            */
-#define SPI1_RDBR                       0xFFC03410      /* SPI Receive Data Buffer Register                             */
-#define SPI1_BAUD                       0xFFC03414      /* SPI Baud rate Register                                       */
-#define SPI1_SHADOW                     0xFFC03418      /* SPI_RDBR Shadow Register                                     */
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Motor Control PWM Registers */
-
-#define                         PWM_CTRL  0xffc03700   /* PWM Control Register */
-#define                         PWM_STAT  0xffc03704   /* PWM Status Register */
-#define                           PWM_TM  0xffc03708   /* PWM Period Register */
-#define                           PWM_DT  0xffc0370c   /* PWM Dead Time Register */
-#define                         PWM_GATE  0xffc03710   /* PWM Chopping Control */
-#define                          PWM_CHA  0xffc03714   /* PWM Channel A Duty Control */
-#define                          PWM_CHB  0xffc03718   /* PWM Channel B Duty Control */
-#define                          PWM_CHC  0xffc0371c   /* PWM Channel C Duty Control */
-#define                          PWM_SEG  0xffc03720   /* PWM Crossover and Output Enable */
-#define                       PWM_SYNCWT  0xffc03724   /* PWM Sync Pluse Width Control */
-#define                         PWM_CHAL  0xffc03728   /* PWM Channel AL Duty Control (SR mode only) */
-#define                         PWM_CHBL  0xffc0372c   /* PWM Channel BL Duty Control (SR mode only) */
-#define                         PWM_CHCL  0xffc03730   /* PWM Channel CL Duty Control (SR mode only) */
-#define                          PWM_LSI  0xffc03734   /* PWM Low Side Invert (SR mode only) */
-#define                        PWM_STAT2  0xffc03738   /* PWM Status Register 2 */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-
-
-#endif /* _DEF_BF51X_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/gpio.h b/arch/blackfin/mach-bf518/include/mach/gpio.h
index 9af6ce0f6321..b480705bfc2e 100644
--- a/arch/blackfin/mach-bf518/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf518/include/mach/gpio.h
@@ -55,4 +55,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf518/include/mach/pll.h b/arch/blackfin/mach-bf518/include/mach/pll.h
index d5502988896b..94cca674d835 100644
--- a/arch/blackfin/mach-bf518/include/mach/pll.h
+++ b/arch/blackfin/mach-bf518/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index 52295fff5577..ccab4c689dc3 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -67,6 +67,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -419,7 +420,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -474,7 +475,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -627,9 +628,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -661,9 +662,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 50533edc3994..c9d6dc88f0e6 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -104,6 +104,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -614,7 +615,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -669,7 +670,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -801,9 +802,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -835,9 +836,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index d06177b5fe22..b7101aa6e3aa 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -68,6 +68,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -499,7 +500,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -554,7 +555,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -681,9 +682,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -715,9 +716,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 35a88a5a5013..2cd2ff6f3043 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -108,6 +108,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -708,7 +709,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -763,7 +764,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -962,6 +963,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
                 I2C_BOARD_INFO("ad5252", 0x2f),
         },
 #endif
+#if defined(CONFIG_SND_SOC_ADAU1373) || defined(CONFIG_SND_SOC_ADAU1373_MODULE)
+        {
+                I2C_BOARD_INFO("adau1373", 0x1A),
+        },
+#endif
 };
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
@@ -984,9 +990,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -1018,9 +1024,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c
index 130861bd2589..18d303dd5627 100644
--- a/arch/blackfin/mach-bf527/boards/tll6527m.c
+++ b/arch/blackfin/mach-bf527/boards/tll6527m.c
@@ -193,7 +193,7 @@ static unsigned gpio_addr_inputs[] = {
         GPIO_PG1, GPIO_PH9, GPIO_PH10
 };
 
-static struct gpio_decoder_platfrom_data spi_decoded_cs = {
+static struct gpio_decoder_platform_data spi_decoded_cs = {
         .base           = EXP_GPIO_SPISEL_BASE,
         .input_addrs    = gpio_addr_inputs,
         .nr_input_addrs = ARRAY_SIZE(gpio_addr_inputs),
@@ -586,7 +586,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -642,7 +642,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -799,9 +799,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -834,9 +834,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf527/dma.c b/arch/blackfin/mach-bf527/dma.c
index 7bc7577d6c4f..1fabdefea73a 100644
--- a/arch/blackfin/mach-bf527/dma.c
+++ b/arch/blackfin/mach-bf527/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index c1d55b878b45..960e08919def 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        int status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long uart_base_addr;
         int uart_irq;
@@ -146,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/blackfin.h b/arch/blackfin/mach-bf527/include/mach/blackfin.h
index f714c5de3073..e1d279274487 100644
--- a/arch/blackfin/mach-bf527/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf527/include/mach/blackfin.h
@@ -1,49 +1,37 @@
 /*
- * Copyright 2007-2009 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
 #define _MACH_BLACKFIN_H_
 
 #include "bf527.h"
-#include "defBF522.h"
 #include "anomaly.h"
 
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "defBF527.h"
+#include <asm/def_LPBlackfin.h>
+#if defined(CONFIG_BF523) || defined(CONFIG_BF522)
+# include "defBF522.h"
 #endif
-
 #if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "defBF525.h"
+# include "defBF525.h"
 #endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF522.h"
-
 #if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "cdefBF527.h"
+# include "defBF527.h"
 #endif
 
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "cdefBF525.h"
-#endif
+#if !defined(__ASSEMBLY__)
+# include <asm/cdef_LPBlackfin.h>
+# if defined(CONFIG_BF523) || defined(CONFIG_BF522)
+#  include "cdefBF522.h"
+# endif
+# if defined(CONFIG_BF525) || defined(CONFIG_BF524)
+#  include "cdefBF525.h"
+# endif
+# if defined(CONFIG_BF527) || defined(CONFIG_BF526)
+#  include "cdefBF527.h"
+# endif
 #endif
 
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 1079af8c7aef..618dfcdfa91a 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1,21 +1,1095 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF522_H
 #define _CDEF_BF522_H
 
-/* include all Core registers and bit definitions */
-#include "defBF522.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
+#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
+#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
+#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
+#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
+#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
+#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
 
-/* include core specific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                       bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
+#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
 
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
+#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
+#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
+#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
+#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
+#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
+
+#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
+#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
+#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
+#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
+
+#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
+#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
+#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
+#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
+
+#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
+#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
+#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
+#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+
+#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
+#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
+#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
+#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
+#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
+#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
+#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
+#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
+#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
+#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
+#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
+#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
+#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
+#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
+#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
+#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
+#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
+#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
+#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
+#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
+#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
+#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
+#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
+#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
+#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
+#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
+#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
+#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
+#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
+#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
+#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
+#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
+#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
+
+
+/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
+#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
+#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
+#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
+#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
+#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
+#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
+#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
+#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
+#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
+#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
+
+#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
+#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
+#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
+#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
+
+#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
+#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
+#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
+#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
+
+#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
+#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
+#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
+#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
+
+#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
+#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
+#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
+#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
+
+#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
+#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
+#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
+#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
+
+#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
+#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
+#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
+#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
+
+#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
+#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
+#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
+#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
+
+#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
+#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
+#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
+#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
+#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
+#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
+#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
+#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
+#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
+#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
+#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
+#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
+#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
+#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
+#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
+#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
+#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
+#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
+#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
+#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
+#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
+#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
+#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
+#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
+#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
+#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
+#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
+#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
+#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
+#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
+#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
+#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
+#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
+#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
+#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
+#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
+#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
+#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
+#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
+#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define bfin_read_DMAC_TC_PER()                 bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)             bfin_write16(DMAC_TC_PER, val)
+#define bfin_read_DMAC_TC_CNT()                 bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)             bfin_write16(DMAC_TC_CNT, val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
+#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
+#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
+#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
+#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
+#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
+#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
+#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
+#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
+#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
+#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
+#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
+#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
+#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
+#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
+#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
+#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
+#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
+#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
+#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
+#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
+#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
+#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
+#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
+#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
+#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
+#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
+#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
+#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
+#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
+#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
+#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
+#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
+#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
+#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
+#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
+#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
+#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
+#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
+#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
+#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
+#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
+#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
+#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
+#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
+#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
+#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
+#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
+#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
+#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
+#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
+#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
+#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
+#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
+#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
+#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
+#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
+#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
+#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
+#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
+#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
+#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
+#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
+#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
+#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
+#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
+#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
+#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
+#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
+#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
+#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
+#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
+#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
+#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
+#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
+#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
+#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
+#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
+#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
+#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
+#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
+#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
+#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
+#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
+#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
+#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
+#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
+#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
+#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
+#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
+#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
+#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
+#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
+#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
+#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
+#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
+#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
+#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
+#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
+#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
+#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
+#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
+#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
+#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
+#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
+#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
+#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
+#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
+#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
+#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
+#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
+
+#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
+#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
+#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
+#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
+#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
+#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
+#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
+#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
+#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
+#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
+#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+
+#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
+#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
+#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
+#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
+#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
+#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
+#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
+#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
+#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
+#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
+#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
+#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
+#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
+#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
+#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
+#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
+#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
+#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
+#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
+#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
+#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
+#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
+#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
+#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
+#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
+#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
+#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
+#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
+#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
+#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
+#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
+#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
+#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
+#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
+#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
+#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
+#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
+#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
+#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
+#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
+#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
+
+#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
+#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
+#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
+#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
+#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
+#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
+
+#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
+#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
+#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
+#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
+#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
+#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
+#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
+#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
+#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
+#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
+#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
+#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
+#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
+#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
+#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
+#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
+#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
+#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
+#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
+#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
+#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
+#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
+#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
+
+/* Counter Registers */
+
+#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
+#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
+#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
+#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
+#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
+#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
+#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
+#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
+#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
+#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
+#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
+#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
+#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
+#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
+#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
+#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
+
+/* Security Registers */
+
+#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
+#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
+#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
+#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
+#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
+#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
+
+/* NFC Registers */
+
+#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
+#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
+#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
+#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
+#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
+#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
+#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
+#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
+#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
+#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
+#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
+#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
+#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
+#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
+#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
+#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
+#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
+#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
+#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
+#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
+#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
+#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
+#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
+#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
+#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
+#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
+#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
+#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
+#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
+#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
+#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
+#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
 
 #endif /* _CDEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
index d7e2751c6bcc..d90a85b6b6b9 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF525.h
@@ -1,15 +1,12 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF525_H
 #define _CDEF_BF525_H
 
-/* include all Core registers and bit definitions */
-#include "defBF525.h"
-
 /* BF525 is BF522 + USB */
 #include "cdefBF522.h"
 
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
index c7ba544d50b6..eb22f5866105 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF527.h
@@ -1,15 +1,12 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF527_H
 #define _CDEF_BF527_H
 
-/* include all Core registers and bit definitions */
-#include "defBF527.h"
-
 /* BF527 is BF525 + EMAC */
 #include "cdefBF525.h"
 
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
deleted file mode 100644
index 3048b52bf46a..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF52x_base.h
+++ /dev/null
@@ -1,1113 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF52x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_clear_PPI_STATUS()                 bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
-#endif /* _CDEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index cb139a254810..89f5420ee6cd 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,12 +7,1393 @@
 #ifndef _DEF_BF522_H
 #define _DEF_BF522_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
+/* ************************************************************** */
+/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
+/* ************************************************************** */
 
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+/* ==== begin from defBF534.h ==== */
 
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID        0xFFC00014  /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
+
+#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
+#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
+#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
+#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
+#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
+#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
+#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
+#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+
+/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI0_REGBASE                    0xFFC00500
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI0_REGBASE                    0xFFC01400
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
+#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
+#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+
+/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX               0xFFC03210      /* Port F mux control */
+#define PORTG_MUX               0xFFC03214      /* Port G mux control */
+#define PORTH_MUX               0xFFC03218      /* Port H mux control */
+#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
+#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
+#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
+#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
+#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
+#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
+#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
+#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
+#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
+
+#if 0
+#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
+
+#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
+#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
+#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
+#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
+#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
+
+#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
+#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
+#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
+#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
+#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
+#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
+#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
+#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
+
+#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
+#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
+#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
+#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
+#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
+#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
+#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
+#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
+#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
+#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
+
+#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
+#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
+#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
+#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
+#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
+#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
+#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
+#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
+#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
+#endif
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
+
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
+#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
+#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
+#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
+#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
+#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
+#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
+
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002          /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
+#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
+#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
+#define DLENGTH                 0x3800          /* PPI Data Length  */
+#define POLC                    0x4000          /* PPI Clock Polarity                           */
+#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400          /* Field Indicator                                      */
+#define FT_ERR                  0x0800          /* Frame Track Error                            */
+#define OVR                             0x1000          /* FIFO Overflow Error                          */
+#define UNDR                    0x2000          /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
+#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTL Masks                                                                                                                  */
+#define SEN                     0x0001          /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTL Masks                                                                                                 */
+#define MEN                     0x0001          /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002          /* Master Address Length                                        */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010          /* Issue Stop Condition                                         */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000          /* Serial Data Override                                         */
+#define SCLOVR          0x8000          /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001          /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004          /* Address Not Acknowledged                                             */
+#define DNAK            0x0008          /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
+#define SDASEN          0x0040          /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001          /* Slave Transfer Initiated     */
+#define SCOMP           0x0002          /* Slave Transfer Complete      */
+#define SERR            0x0004          /* Slave Transfer Error         */
+#define SOVF            0x0008          /* Slave Overflow                       */
+#define MCOMP           0x0010          /* Master Transfer Complete     */
+#define MERR            0x0020          /* Master Transfer Error        */
+#define XMTSERV         0x0040          /* Transmit FIFO Service        */
+#define RCVSERV         0x0080          /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
+
+
+/* Omit CAN masks from defBF534.h */
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
+#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
+#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010                  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART   PFDE_UART
+#define PGDE_DMA    PFDE_DMA
+#define CKELOW          SCKELOW
+
+/* ==== end from defBF534.h ==== */
+
+/* HOST Port Registers */
+
+#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
+#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
+#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
+#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
+#define                       CNT_STATUS  0xffc03508   /* Status Register */
+#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
+#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
+#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
+#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
+#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
+#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
+#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
+#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
+#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
+#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* NFC Registers */
+
+#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
+#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
+#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
+#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
+#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
+#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
+#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
+#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
+#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
+#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
+#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
+#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
+#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
+#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
+#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
+#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
+
+/* ********************************************************** */
+/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
+/*     and MULTI BIT READ MACROS                              */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
+#define                  HOST_CNTR_nHOST_EN  0x0
+#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
+#define                 HOST_CNTR_nHOST_END  0x0
+#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
+#define                HOST_CNTR_nDATA_SIZE  0x0
+#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
+#define                 HOST_CNTR_nHOST_RST  0x0
+#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
+#define                 HOST_CNTR_nHRDY_OVR  0x0
+#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
+#define                 HOST_CNTR_nINT_MODE  0x0
+#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
+#define                   HOST_CNTR_ nBT_EN  0x0
+#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
+#define                      HOST_CNTR_nEHW  0x0
+#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
+#define                      HOST_CNTR_nEHR  0x0
+#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
+#define                      HOST_CNTR_nBDR  0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define                     HOST_STAT_READY  0x1        /* DMA Ready */
+#define                    HOST_STAT_nREADY  0x0
+#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
+#define                 HOST_STAT_nFIFOFULL  0x0
+#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
+#define                HOST_STAT_nFIFOEMPTY  0x0
+#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
+#define                 HOST_STAT_nCOMPLETE  0x0
+#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
+#define                     HOST_STAT_nHSHK  0x0
+#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
+#define                  HOST_STAT_nTIMEOUT  0x0
+#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
+#define                     HOST_STAT_nHIRQ  0x0
+#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
+#define               HOST_STAT_nALLOW_CNFG  0x0
+#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
+#define                  HOST_STAT_nDMA_DIR  0x0
+#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
+#define                      HOST_STAT_nBTE  0x0
+#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
+#define              HOST_STAT_nHOSTRD_DONE  0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define                   EMUDABL  0x1        /* Emulation Disable. */
+#define                  nEMUDABL  0x0
+#define                   RSTDABL  0x2        /* Reset Disable */
+#define                  nRSTDABL  0x0
+#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
+#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
+#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
+#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
+#define                  nDMA0OVR  0x0
+#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
+#define                  nDMA1OVR  0x0
+#define                    EMUOVR  0x4000     /* Emulation Override */
+#define                   nEMUOVR  0x0
+#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
+#define                   nOTPSEN  0x0
+#define                    L2DABL  0x70000    /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define                   SECURE0  0x1        /* SECURE 0 */
+#define                  nSECURE0  0x0
+#define                   SECURE1  0x2        /* SECURE 1 */
+#define                  nSECURE1  0x0
+#define                   SECURE2  0x4        /* SECURE 2 */
+#define                  nSECURE2  0x0
+#define                   SECURE3  0x8        /* SECURE 3 */
+#define                  nSECURE3  0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define                   SECMODE  0x3        /* Secured Mode Control State */
+#define                       NMI  0x4        /* Non Maskable Interrupt */
+#define                      nNMI  0x0
+#define                   AFVALID  0x8        /* Authentication Firmware Valid */
+#define                  nAFVALID  0x0
+#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
+#define                   nAFEXIT  0x0
+#define                   SECSTAT  0xe0       /* Secure Status */
 
 #endif /* _DEF_BF522_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index c136f7032962..cc383adfdffa 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF527.h b/arch/blackfin/mach-bf527/include/mach/defBF527.h
index 4dd58fb33156..05369a92fbc8 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF527.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF527.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
deleted file mode 100644
index 09475034c6a1..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ /dev/null
@@ -1,1506 +0,0 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the ADI BSD license or the GPL-2 (or later)
- */
-
-#ifndef _DEF_BF52X_H
-#define _DEF_BF52X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI0_CONTROL                    0xFFC01404      /* TWI Control Register                                         */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI0_MASTER_CTL         0xFFC01414      /* Master Mode Control Register                         */
-#define TWI0_MASTER_STAT                0xFFC01418      /* Master Mode Status Register                          */
-#define TWI0_MASTER_ADDR                0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register                                        */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTL Masks                                                                                                                  */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTL Masks                                                                                                 */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000
-#define _BOOTROM_FINAL_INIT 0xEF000002
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-#endif /* _DEF_BF52X_H */
diff --git a/arch/blackfin/mach-bf527/include/mach/gpio.h b/arch/blackfin/mach-bf527/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf527/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf527/include/mach/gpio.h
@@ -62,4 +62,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf527/include/mach/pll.h b/arch/blackfin/mach-bf527/include/mach/pll.h
index 24f1d7c02325..94cca674d835 100644
--- a/arch/blackfin/mach-bf527/include/mach/pll.h
+++ b/arch/blackfin/mach-bf527/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf533/boards/H8606.c b/arch/blackfin/mach-bf533/boards/H8606.c
index 2ce7b16faee1..d4bfcea56828 100644
--- a/arch/blackfin/mach-bf533/boards/H8606.c
+++ b/arch/blackfin/mach-bf533/boards/H8606.c
@@ -286,7 +286,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 20c102285bef..87b5af3693c1 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -25,7 +25,6 @@
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -225,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -290,9 +289,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -324,9 +323,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -476,10 +475,16 @@ static int __init blackstamp_init(void)
                 return ret;
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-        /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
-        bfin_write_FIO_FLAG_S(PF0);
-        SSYNC();
+        /*
+         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
+         * the bfin-async-map driver takes care of flipping between
+         * flash and ethernet when necessary.
+         */
+        ret = gpio_request(GPIO_PF0, "enet_cpld");
+        if (!ret) {
+                gpio_direction_output(GPIO_PF0, 1);
+                gpio_free(GPIO_PF0);
+        }
 #endif
 
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index adbe62a81e25..4d5604eaa7c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -271,7 +271,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -336,9 +336,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -370,9 +370,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index a1cb8e7c1010..b67b91d82242 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -349,7 +349,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index 5ba4b02a12eb..f869a3711480 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -22,7 +22,6 @@
 #include <asm/dma.h>
 #include <asm/bfin5xx_spi.h>
 #include <asm/portmux.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -174,7 +173,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -295,15 +294,7 @@ static int __init ip0x_init(void)
         printk(KERN_INFO "%s(): registering device resources\n", __func__);
         platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
 
-#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
-        for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
-                int j = 1 << bfin_spi_board_info[i].chip_select;
-                /* set spi cs to 1 */
-                bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
-                bfin_write_FIO_FLAG_S(j);
-        }
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
-#endif
 
         return 0;
 }
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index b3b1cdea2703..43224ef00b8c 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -24,7 +24,6 @@
 #include <asm/reboot.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
-#include <mach/fio_flag.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -354,7 +353,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -419,9 +418,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +452,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -674,10 +673,16 @@ static int __init stamp_init(void)
                 return ret;
 
 #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
-        /* setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC */
-        bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
-        bfin_write_FIO_FLAG_S(PF0);
-        SSYNC();
+        /*
+         * setup BF533_STAMP CPLD to route AMS3 to Ethernet MAC.
+         * the bfin-async-map driver takes care of flipping between
+         * flash and ethernet when necessary.
+         */
+        ret = gpio_request(GPIO_PF0, "enet_cpld");
+        if (!ret) {
+                gpio_direction_output(GPIO_PF0, 1);
+                gpio_free(GPIO_PF0);
+        }
 #endif
 
         spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
@@ -713,7 +718,6 @@ void __init native_machine_early_platform_add_devices(void)
 void native_machine_restart(char *cmd)
 {
         /* workaround pull up on cpld / flash pin not being strong enough */
-        bfin_write_FIO_INEN(~PF0);
-        bfin_write_FIO_DIR(PF0);
-        bfin_write_FIO_FLAG_C(PF0);
+        gpio_request(GPIO_PF0, "flash_cpld");
+        gpio_direction_output(GPIO_PF0, 0);
 }
diff --git a/arch/blackfin/mach-bf533/dma.c b/arch/blackfin/mach-bf533/dma.c
index 4a14a46a9a68..1f5988d43139 100644
--- a/arch/blackfin/mach-bf533/dma.c
+++ b/arch/blackfin/mach-bf533/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      1
+
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index 9e1f3defb6bc..45dcaa4f3e41 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000363
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/blackfin.h b/arch/blackfin/mach-bf533/include/mach/blackfin.h
index f4bd6df5d968..e366207fbf12 100644
--- a/arch/blackfin/mach-bf533/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf533/include/mach/blackfin.h
@@ -1,7 +1,7 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
@@ -10,26 +10,14 @@
 #define BF533_FAMILY
 
 #include "bf533.h"
-#include "defBF532.h"
 #include "anomaly.h"
 
-#if !defined(__ASSEMBLY__)
-#include "cdefBF532.h"
-#endif
-
-#define BFIN_UART_NR_PORTS      1
+#include <asm/def_LPBlackfin.h>
+#include "defBF532.h"
 
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# include "cdefBF532.h"
+#endif
 
-#endif                          /* _MACH_BLACKFIN_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
index 401e524f5321..fd0cbe4df21a 100644
--- a/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/cdefBF532.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -7,9 +7,6 @@
 #ifndef _CDEF_BF532_H
 #define _CDEF_BF532_H
 
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
 #define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
@@ -66,16 +63,10 @@
 #define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
 
 /* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
+#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)
+#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)
 
 /* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
 #define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
@@ -105,6 +96,47 @@
 #define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
 #define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
 
+#if ANOMALY_05000311
+/* Keep at the CPP expansion to avoid circular header dependency loops */
+#define BFIN_WRITE_FIO_FLAG(name, val) \
+        do { \
+                unsigned long __flags; \
+                __flags = hard_local_irq_save(); \
+                bfin_write16(FIO_FLAG_##name, val); \
+                bfin_read_CHIPID(); \
+                hard_local_irq_restore(__flags); \
+        } while (0)
+#define bfin_write_FIO_FLAG_D(val)           BFIN_WRITE_FIO_FLAG(D, val)
+#define bfin_write_FIO_FLAG_C(val)           BFIN_WRITE_FIO_FLAG(C, val)
+#define bfin_write_FIO_FLAG_S(val)           BFIN_WRITE_FIO_FLAG(S, val)
+#define bfin_write_FIO_FLAG_T(val)           BFIN_WRITE_FIO_FLAG(T, val)
+
+#define BFIN_READ_FIO_FLAG(name) \
+        ({ \
+                unsigned long __flags; \
+                u16 __ret; \
+                __flags = hard_local_irq_save(); \
+                __ret = bfin_read16(FIO_FLAG_##name); \
+                bfin_read_CHIPID(); \
+                hard_local_irq_restore(__flags); \
+                __ret; \
+        })
+#define bfin_read_FIO_FLAG_D()               BFIN_READ_FIO_FLAG(D)
+#define bfin_read_FIO_FLAG_C()               BFIN_READ_FIO_FLAG(C)
+#define bfin_read_FIO_FLAG_S()               BFIN_READ_FIO_FLAG(S)
+#define bfin_read_FIO_FLAG_T()               BFIN_READ_FIO_FLAG(T)
+
+#else
+#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
+#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
+#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
+#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
+#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
+#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
+#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
+#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
+#endif
+
 /* DMA Controller */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
 #define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
@@ -647,7 +679,4 @@
 #define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
 #define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF532_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 3adb0b44e597..2376d5393511 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -1,7 +1,7 @@
 /*
  * System & MMR bit and Address definitions for ADSP-BF532
  *
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -9,9 +9,6 @@
 #ifndef _DEF_BF532_H
 #define _DEF_BF532_H
 
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
@@ -182,12 +179,8 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
 
 /* DMA Traffic controls */
-#define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
-#define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
-#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
+#define DMAC_TC_PER 0xFFC00B0C  /* Traffic Control Periods Register */
+#define DMAC_TC_CNT 0xFFC00B10  /* Traffic Control Current Counts Register */
 
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
 #define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
@@ -432,83 +425,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
@@ -643,44 +559,6 @@
 #define ERR_TYP_P0              0x0E
 #define ERR_TYP_P1              0x0F
 
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
 
 /* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf533/include/mach/fio_flag.h b/arch/blackfin/mach-bf533/include/mach/fio_flag.h
deleted file mode 100644
index d0bfba0b083b..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/fio_flag.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_FIO_FLAG_H
-#define _MACH_FIO_FLAG_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static inline void bfin_write_FIO_FLAG_##name(unsigned short val) \
-{ \
-        unsigned long flags; \
-        flags = hard_local_irq_save(); \
-        bfin_write16(FIO_FLAG_##name, val); \
-        bfin_read_CHIPID(); \
-        hard_local_irq_restore(flags); \
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static inline u16 bfin_read_FIO_FLAG_##name(void) \
-{ \
-        unsigned long flags; \
-        u16 ret; \
-        flags = hard_local_irq_save(); \
-        ret = bfin_read16(FIO_FLAG_##name); \
-        bfin_read_CHIPID(); \
-        hard_local_irq_restore(flags); \
-        return ret; \
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D, val)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C, val)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S, val)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#endif
-
-#endif /* _MACH_FIO_FLAG_H */
diff --git a/arch/blackfin/mach-bf533/include/mach/gpio.h b/arch/blackfin/mach-bf533/include/mach/gpio.h
index e02416db4b00..cce4f8fb3785 100644
--- a/arch/blackfin/mach-bf533/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf533/include/mach/gpio.h
@@ -28,4 +28,6 @@
 
 #define PORT_F GPIO_PF0
 
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf533/include/mach/pll.h b/arch/blackfin/mach-bf533/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf533/include/mach/pll.h
+++ b/arch/blackfin/mach-bf533/include/mach/pll.h
@@ -1,57 +1 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 44132fda63be..a44bf3a1816e 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -39,4 +39,10 @@ config CAMSIG_MINOTAUR
         help
           Board supply package for CSP Minotaur
 
+config DNP5370
+        bool "SSV Dil/NetPC DNP/5370"
+        depends on (BF537)
+        help
+          Board supply package for DNP/5370 DIL64 module
+
 endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7e6aa4e5b205..fe42258fe1f4 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_BFIN537_BLUETECHNIX_CM_U) += cm_bf537u.o
 obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM)  += tcm_bf537.o
 obj-$(CONFIG_PNAV10)                   += pnav10.o
 obj-$(CONFIG_CAMSIG_MINOTAUR)          += minotaur.o
+obj-$(CONFIG_DNP5370)                  += dnp5370.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 836698c4ee54..2c776e188a94 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -373,7 +373,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -434,7 +434,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -545,9 +545,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -579,9 +579,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 2a85670273cb..085661175ec7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -510,9 +510,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -544,9 +544,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
new file mode 100644
index 000000000000..e1e9ea02ad89
--- /dev/null
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -0,0 +1,418 @@
+/*
+ * This is the configuration for SSV Dil/NetPC DNP/5370 board.
+ *
+ * DIL module:         http://www.dilnetpc.com/dnp0086.htm
+ * SK28 (starter kit): http://www.dilnetpc.com/dnp0088.htm
+ *
+ * Copyright 2010 3ality Digital Systems
+ * Copyright 2005 National ICT Australia (NICTA)
+ * Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/spi/mmc_spi.h>
+#include <linux/phy.h>
+#include <asm/dma.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/reboot.h>
+#include <asm/portmux.h>
+#include <asm/dpmc.h>
+
+/*
+ * Name the Board for the /proc/cpuinfo
+ */
+const char bfin_board_name[] = "DNP/5370";
+#define FLASH_MAC               0x202f0000
+#define CONFIG_MTD_PHYSMAP_LEN  0x300000
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+static struct platform_device rtc_device = {
+        .name = "rtc-bfin",
+        .id   = -1,
+};
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+#include <linux/bfin_mac.h>
+static const unsigned short bfin_mac_peripherals[] = P_RMII0;
+
+static struct bfin_phydev_platform_data bfin_phydev_data[] = {
+        {
+                .addr = 1,
+                .irq = PHY_POLL, /* IRQ_MAC_PHYINT */
+        },
+};
+
+static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
+        .phydev_number   = 1,
+        .phydev_data     = bfin_phydev_data,
+        .phy_mode        = PHY_INTERFACE_MODE_RMII,
+        .mac_peripherals = bfin_mac_peripherals,
+};
+
+static struct platform_device bfin_mii_bus = {
+        .name = "bfin_mii_bus",
+        .dev = {
+                .platform_data = &bfin_mii_bus_data,
+        }
+};
+
+static struct platform_device bfin_mac_device = {
+        .name = "bfin_mac",
+        .dev = {
+                .platform_data = &bfin_mii_bus,
+        }
+};
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition asmb_flash_partitions[] = {
+        {
+                .name       = "bootloader(nor)",
+                .size       = 0x30000,
+                .offset     = 0,
+        }, {
+                .name       = "linux kernel and rootfs(nor)",
+                .size       = 0x300000 - 0x30000 - 0x10000,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "MAC address(nor)",
+                .size       = 0x10000,
+                .offset     = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        }
+};
+
+static struct physmap_flash_data asmb_flash_data = {
+        .width      = 1,
+        .parts      = asmb_flash_partitions,
+        .nr_parts   = ARRAY_SIZE(asmb_flash_partitions),
+};
+
+static struct resource asmb_flash_resource = {
+        .start = 0x20000000,
+        .end   = 0x202fffff,
+        .flags = IORESOURCE_MEM,
+};
+
+/* 4 MB NOR flash attached to async memory banks 0-2,
+ * therefore only 3 MB visible.
+ */
+static struct platform_device asmb_flash_device = {
+        .name     = "physmap-flash",
+        .id       = 0,
+        .dev = {
+                .platform_data = &asmb_flash_data,
+        },
+        .num_resources = 1,
+        .resource      = &asmb_flash_resource,
+};
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+
+#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
+
+static int bfin_mmc_spi_init(struct device *dev,
+        irqreturn_t (*detect_int)(int, void *), void *data)
+{
+        return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
+                IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
+}
+
+static void bfin_mmc_spi_exit(struct device *dev, void *data)
+{
+        free_irq(MMC_SPI_CARD_DETECT_INT, data);
+}
+
+static struct bfin5xx_spi_chip mmc_spi_chip_info = {
+        .enable_dma    = 0,      /* use no dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+
+static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
+        .init = bfin_mmc_spi_init,
+        .exit = bfin_mmc_spi_exit,
+        .detect_delay = 100, /* msecs */
+};
+#endif
+
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+/* This mapping is for at45db642 it has 1056 page size,
+ * partition size and offset should be page aligned
+ */
+static struct mtd_partition bfin_spi_dataflash_partitions[] = {
+        {
+                .name   = "JFFS2 dataflash(nor)",
+#ifdef CONFIG_MTD_PAGESIZE_1024
+                .offset = 0x40000,
+                .size   = 0x7C0000,
+#else
+                .offset = 0x0,
+                .size   = 0x840000,
+#endif
+        }
+};
+
+static struct flash_platform_data bfin_spi_dataflash_data = {
+        .name     = "mtd_dataflash",
+        .parts    = bfin_spi_dataflash_partitions,
+        .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
+        .type     = "mtd_dataflash",
+};
+
+static struct bfin5xx_spi_chip spi_dataflash_chip_info = {
+        .enable_dma    = 0,      /* use no dma transfer with this chip*/
+        .bits_per_word = 8,
+};
+#endif
+
+static struct spi_board_info bfin_spi_board_info[] __initdata = {
+/* SD/MMC card reader at SPI bus */
+#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
+        {
+                .modalias        = "mmc_spi",
+                .max_speed_hz    = 20000000,
+                .bus_num         = 0,
+                .chip_select     = 1,
+                .platform_data   = &bfin_mmc_spi_pdata,
+                .controller_data = &mmc_spi_chip_info,
+                .mode            = SPI_MODE_3,
+        },
+#endif
+
+/* 8 Megabyte Atmel NOR flash chip at SPI bus */
+#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
+        {
+        .modalias        = "mtd_dataflash",
+        .max_speed_hz    = 16700000,
+        .bus_num         = 0,
+        .chip_select     = 2,
+        .platform_data   = &bfin_spi_dataflash_data,
+        .controller_data = &spi_dataflash_chip_info,
+        .mode            = SPI_MODE_3, /* SPI_CPHA and SPI_CPOL */
+        },
+#endif
+};
+
+/* SPI controller data */
+/* SPI (0) */
+static struct resource bfin_spi0_resource[] = {
+        [0] = {
+                .start = SPI0_REGBASE,
+                .end   = SPI0_REGBASE + 0xFF,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = CH_SPI,
+                .end   = CH_SPI,
+                .flags = IORESOURCE_DMA,
+        },
+        [2] = {
+                .start = IRQ_SPI,
+                .end   = IRQ_SPI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct bfin5xx_spi_master spi_bfin_master_info = {
+        .num_chipselect = 8,
+        .enable_dma     = 1,  /* master has the ability to do dma transfer */
+        .pin_req        = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
+};
+
+static struct platform_device spi_bfin_master_device = {
+        .name          = "bfin-spi",
+        .id            = 0, /* Bus number */
+        .num_resources = ARRAY_SIZE(bfin_spi0_resource),
+        .resource      = bfin_spi0_resource,
+        .dev           = {
+                .platform_data = &spi_bfin_master_info, /* Passed to driver */
+        },
+};
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+static struct resource bfin_uart0_resources[] = {
+        {
+                .start = UART0_THR,
+                .end = UART0_GCTL+2,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART0_RX,
+                .end = IRQ_UART0_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART0_ERROR,
+                .end = IRQ_UART0_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART0_TX,
+                .end = CH_UART0_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART0_RX,
+                .end = CH_UART0_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static unsigned short bfin_uart0_peripherals[] = {
+        P_UART0_TX, P_UART0_RX, 0
+};
+
+static struct platform_device bfin_uart0_device = {
+        .name = "bfin-uart",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_uart0_resources),
+        .resource = bfin_uart0_resources,
+        .dev = {
+                .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
+        },
+};
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_UART1
+static struct resource bfin_uart1_resources[] = {
+        {
+                .start = UART1_THR,
+                .end   = UART1_GCTL+2,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_UART1_RX,
+                .end   = IRQ_UART1_RX+1,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = IRQ_UART1_ERROR,
+                .end   = IRQ_UART1_ERROR,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_UART1_TX,
+                .end   = CH_UART1_TX,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = CH_UART1_RX,
+                .end   = CH_UART1_RX,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static unsigned short bfin_uart1_peripherals[] = {
+        P_UART1_TX, P_UART1_RX, 0
+};
+
+static struct platform_device bfin_uart1_device = {
+        .name          = "bfin-uart",
+        .id            = 1,
+        .num_resources = ARRAY_SIZE(bfin_uart1_resources),
+        .resource      = bfin_uart1_resources,
+        .dev = {
+                .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
+        },
+};
+#endif
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+static struct resource bfin_twi0_resource[] = {
+        [0] = {
+                .start = TWI0_REGBASE,
+                .end   = TWI0_REGBASE + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_TWI,
+                .end   = IRQ_TWI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device i2c_bfin_twi_device = {
+        .name          = "i2c-bfin-twi",
+        .id            = 0,
+        .num_resources = ARRAY_SIZE(bfin_twi0_resource),
+        .resource      = bfin_twi0_resource,
+};
+#endif
+
+static struct platform_device *dnp5370_devices[] __initdata = {
+
+#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        &bfin_uart0_device,
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        &bfin_uart1_device,
+#endif
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        &asmb_flash_device,
+#endif
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+        &bfin_mii_bus,
+        &bfin_mac_device,
+#endif
+
+#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
+        &spi_bfin_master_device,
+#endif
+
+#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
+        &i2c_bfin_twi_device,
+#endif
+
+#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
+        &rtc_device,
+#endif
+
+};
+
+static int __init dnp5370_init(void)
+{
+        printk(KERN_INFO "DNP/5370: registering device resources\n");
+        platform_add_devices(dnp5370_devices, ARRAY_SIZE(dnp5370_devices));
+        printk(KERN_INFO "DNP/5370: registering %zu SPI slave devices\n",
+               ARRAY_SIZE(bfin_spi_board_info));
+        spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
+        printk(KERN_INFO "DNP/5370: MAC %pM\n", (void *)FLASH_MAC);
+        return 0;
+}
+arch_initcall(dnp5370_init);
+
+/*
+ * Currently the MAC address is saved in Flash by U-Boot
+ */
+void bfin_get_ether_addr(char *addr)
+{
+        *(u32 *)(&(addr[0])) = bfin_read32(FLASH_MAC);
+        *(u16 *)(&(addr[4])) = bfin_read16(FLASH_MAC + 4);
+}
+EXPORT_SYMBOL(bfin_get_ether_addr);
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index 49800518412c..bfb3671a78da 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -263,7 +263,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -306,7 +306,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -419,9 +419,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -453,9 +453,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index b95807894e25..9389f03e3b0a 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -367,7 +367,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -410,7 +410,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3aa344ce8e52..2c69785a7bbe 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -289,7 +289,7 @@ static struct platform_device isp1362_hcd_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
@@ -693,7 +693,7 @@ static struct bfin5xx_spi_chip ad2s90_spi_chip_info = {
 #endif
 
 #if defined(CONFIG_AD2S120X) || defined(CONFIG_AD2S120X_MODULE)
-unsigned short ad2s120x_platform_data[] = {
+static unsigned short ad2s120x_platform_data[] = {
         /* used as SAMPLE and RDVEL */
         GPIO_PF5, GPIO_PF6, 0
 };
@@ -705,7 +705,7 @@ static struct bfin5xx_spi_chip ad2s120x_spi_chip_info = {
 #endif
 
 #if defined(CONFIG_AD2S1210) || defined(CONFIG_AD2S1210_MODULE)
-unsigned short ad2s1210_platform_data[] = {
+static unsigned short ad2s1210_platform_data[] = {
         /* use as SAMPLE, A0, A1 */
         GPIO_PF7, GPIO_PF8, GPIO_PF9,
 # if defined(CONFIG_AD2S1210_GPIO_INPUT) || defined(CONFIG_AD2S1210_GPIO_OUTPUT)
@@ -1717,7 +1717,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -1760,7 +1760,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -2447,9 +2447,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -2481,9 +2481,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 31498add1a42..0761b201abca 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -356,7 +356,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -399,7 +399,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -512,9 +512,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -546,9 +546,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
diff --git a/arch/blackfin/mach-bf537/dma.c b/arch/blackfin/mach-bf537/dma.c
index 5c8c4ed517bb..5c62e99c9fac 100644
--- a/arch/blackfin/mach-bf537/dma.c
+++ b/arch/blackfin/mach-bf537/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..00c603fe8218
--- /dev/null
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      2
+
+#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index 635c91c526a3..3e955dba8951 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,49 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -145,3 +75,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/blackfin.h b/arch/blackfin/mach-bf537/include/mach/blackfin.h
index a12d4b6a221d..baa096fc724a 100644
--- a/arch/blackfin/mach-bf537/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf537/include/mach/blackfin.h
@@ -1,7 +1,7 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
- * Licensed under the GPL-2 or later
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _MACH_BLACKFIN_H_
@@ -10,34 +10,24 @@
 #define BF537_FAMILY
 
 #include "bf537.h"
-#include "defBF534.h"
 #include "anomaly.h"
 
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF534
+# include "defBF534.h"
+#endif
 #if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "defBF537.h"
+# include "defBF537.h"
 #endif
 
 #if !defined(__ASSEMBLY__)
-#include "cdefBF534.h"
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "cdefBF537.h"
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF534
+#  include "cdefBF534.h"
+# endif
+# if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+#  include "cdefBF537.h"
+# endif
 #endif
-#endif
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
 
 #endif
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
index fbeb35e14135..563ede907336 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF534.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF534_H
 #define _CDEF_BF534_H
 
-#include <asm/blackfin.h>
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF534.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/cdef_LPBlackfin.h>
-
 /* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
 #define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
 #define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
@@ -355,16 +347,10 @@
 #define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+#define bfin_read_DMAC_TC_PER()              bfin_read16(DMAC_TC_PER)
+#define bfin_write_DMAC_TC_PER(val)          bfin_write16(DMAC_TC_PER,val)
+#define bfin_read_DMAC_TC_CNT()              bfin_read16(DMAC_TC_CNT)
+#define bfin_write_DMAC_TC_CNT(val)          bfin_write16(DMAC_TC_CNT,val)
 
 /* DMA Controller                                                                                                                                       */
 #define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
@@ -1747,7 +1733,4 @@
 #define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
 #define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF534_H */
diff --git a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
index 9363c3990421..19ec21ea150a 100644
--- a/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/cdefBF537.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later
  */
@@ -10,9 +10,6 @@
 /* Include MMRs Common to BF534                                                                 */
 #include "cdefBF534.h"
 
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF537.h"
-
 /* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
 /* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
 #define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 0323e6bacdae..32529a03b266 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _DEF_BF534_H
 #define _DEF_BF534_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
 /************************************************************************************
 ** System MMR Register Map
 *************************************************************************************/
@@ -193,12 +190,8 @@
 #define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
 
 /* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+#define DMAC_TC_PER                     0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMAC_TC_CNT                     0xFFC00B10      /* Traffic Control Current Counts Register      */
 
 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
 #define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
@@ -1029,48 +1022,6 @@
 #define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
 #define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
 
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
-#define STB                     0x04    /* Stop Bits                    */
-#define PEN                     0x08    /* Parity Enable                */
-#define EPS                     0x10    /* Even Parity Select   */
-#define STP                     0x20    /* Stick Parity                 */
-#define SB                      0x40    /* Set Break                    */
-#define DLAB            0x80    /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
-#define LOOP_ENA_P      0x04
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04    /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01    /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01    /* Enable UARTx Clocks                          */
-#define IREN            0x02    /* Enable IrDA Mode                                     */
-#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
-#define FPE                     0x10    /* Force Parity Error On Transmit       */
-#define FFE                     0x20    /* Force Framing Error On Transmit      */
-
 /*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
 /* TIMER_ENABLE Masks                                                                                                   */
 #define TIMEN0                  0x0001  /* Enable Timer 0                                       */
@@ -1141,62 +1092,6 @@
 #define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
 #define ERR_TYP                 0xC000  /* Error Type                                                   */
 
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF537.h b/arch/blackfin/mach-bf537/include/mach/defBF537.h
index 8cb5d5cf0c94..3d471d752684 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF537.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF537.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2008 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,9 +7,6 @@
 #ifndef _DEF_BF537_H
 #define _DEF_BF537_H
 
-/* Include all Core registers and bit definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /* Include all MMR and bit defines common to BF534 */
 #include "defBF534.h"
 
diff --git a/arch/blackfin/mach-bf537/include/mach/gpio.h b/arch/blackfin/mach-bf537/include/mach/gpio.h
index f80c2995efdb..fba606b699c3 100644
--- a/arch/blackfin/mach-bf537/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf537/include/mach/gpio.h
@@ -62,4 +62,8 @@
 #define PORT_G GPIO_PG0
 #define PORT_H GPIO_PH0
 
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf537/include/mach/pll.h b/arch/blackfin/mach-bf537/include/mach/pll.h
index 169c106d0edb..94cca674d835 100644
--- a/arch/blackfin/mach-bf537/include/mach/pll.h
+++ b/arch/blackfin/mach-bf537/include/mach/pll.h
@@ -1,57 +1 @@
-/*
- * Copyright 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index c6fb0a52f849..e61424ef35eb 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -82,7 +82,7 @@ static struct resource bfin_uart0_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -125,7 +125,7 @@ static struct resource bfin_uart1_resources[] = {
         },
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX, 0
 };
 
@@ -168,7 +168,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -282,9 +282,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -316,9 +316,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -350,7 +350,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -384,7 +384,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -402,7 +402,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf538/dma.c b/arch/blackfin/mach-bf538/dma.c
index 5dc022589214..cce8ef5a5cec 100644
--- a/arch/blackfin/mach-bf538/dma.c
+++ b/arch/blackfin/mach-bf538/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
@@ -32,14 +32,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA17_NEXT_DESC_PTR,
         (struct dma_register *) DMA18_NEXT_DESC_PTR,
         (struct dma_register *) DMA19_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA0_S1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
 };
 EXPORT_SYMBOL(dma_io_base_addr);
 
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..c66e2760aad3
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      3
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 5c148142f041..beb502e9cb33 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
@@ -54,50 +27,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -160,3 +89,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/blackfin.h b/arch/blackfin/mach-bf538/include/mach/blackfin.h
index 08b5eabb1ed5..791d08400cf0 100644
--- a/arch/blackfin/mach-bf538/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf538/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,31 +10,24 @@
 #define BF538_FAMILY
 
 #include "bf538.h"
-#include "defBF539.h"
 #include "anomaly.h"
 
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF538.h"
-
-#if defined(CONFIG_BF539)
-#include "cdefBF539.h"
+#include <asm/def_LPBlackfin.h>
+#ifdef CONFIG_BF538
+# include "defBF538.h"
 #endif
+#ifdef CONFIG_BF539
+# include "defBF539.h"
 #endif
 
-#define BFIN_UART_NR_PORTS      3
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF538
+#  include "cdefBF538.h"
+# endif
+# ifdef CONFIG_BF539
+#  include "cdefBF539.h"
+# endif
+#endif
 
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
index 085b06b8c0a5..f6a56792180b 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF538.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF538_H
 #define _CDEF_BF538_H
 
-#include <asm/blackfin.h>
-
-/*include all Core registers and bit definitions*/
-#include "defBF539.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 #define bfin_writePTR(addr, val) bfin_write32(addr, val)
 
 #define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
@@ -487,10 +479,10 @@
 #define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
 #define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
 #define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_TC_PER()        bfin_read16(DMA0_TC_PER)
-#define bfin_write_DMA0_TC_PER(val)    bfin_write16(DMA0_TC_PER, val)
-#define bfin_read_DMA0_TC_CNT()        bfin_read16(DMA0_TC_CNT)
-#define bfin_write_DMA0_TC_CNT(val)    bfin_write16(DMA0_TC_CNT, val)
+#define bfin_read_DMAC0_TC_PER()       bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val)   bfin_write16(DMAC0_TC_PER, val)
+#define bfin_read_DMAC0_TC_CNT()       bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val)   bfin_write16(DMAC0_TC_CNT, val)
 #define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
 #define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
 #define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
@@ -699,10 +691,10 @@
 #define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
 #define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
 #define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_TC_PER()        bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)    bfin_write16(DMA1_TC_PER, val)
-#define bfin_read_DMA1_TC_CNT()        bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)    bfin_write16(DMA1_TC_CNT, val)
+#define bfin_read_DMAC1_TC_PER()       bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val)   bfin_write16(DMAC1_TC_PER, val)
+#define bfin_read_DMAC1_TC_CNT()       bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val)   bfin_write16(DMAC1_TC_CNT, val)
 #define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
 #define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
 #define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
@@ -1015,273 +1007,214 @@
 #define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
 #define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
 #define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_START_ADDR() bfin_readPTR(MDMA0_D0_START_ADDR)
-#define bfin_write_MDMA0_D0_START_ADDR(val) bfin_writePTR(MDMA0_D0_START_ADDR, val)
-#define bfin_read_MDMA0_D0_CONFIG()    bfin_read16(MDMA0_D0_CONFIG)
-#define bfin_write_MDMA0_D0_CONFIG(val) bfin_write16(MDMA0_D0_CONFIG, val)
-#define bfin_read_MDMA0_D0_X_COUNT()   bfin_read16(MDMA0_D0_X_COUNT)
-#define bfin_write_MDMA0_D0_X_COUNT(val) bfin_write16(MDMA0_D0_X_COUNT, val)
-#define bfin_read_MDMA0_D0_X_MODIFY()  bfin_read16(MDMA0_D0_X_MODIFY)
-#define bfin_write_MDMA0_D0_X_MODIFY(val) bfin_write16(MDMA0_D0_X_MODIFY, val)
-#define bfin_read_MDMA0_D0_Y_COUNT()   bfin_read16(MDMA0_D0_Y_COUNT)
-#define bfin_write_MDMA0_D0_Y_COUNT(val) bfin_write16(MDMA0_D0_Y_COUNT, val)
-#define bfin_read_MDMA0_D0_Y_MODIFY()  bfin_read16(MDMA0_D0_Y_MODIFY)
-#define bfin_write_MDMA0_D0_Y_MODIFY(val) bfin_write16(MDMA0_D0_Y_MODIFY, val)
-#define bfin_read_MDMA0_D0_CURR_DESC_PTR() bfin_readPTR(MDMA0_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D0_CURR_ADDR() bfin_readPTR(MDMA0_D0_CURR_ADDR)
-#define bfin_write_MDMA0_D0_CURR_ADDR(val) bfin_writePTR(MDMA0_D0_CURR_ADDR, val)
-#define bfin_read_MDMA0_D0_IRQ_STATUS() bfin_read16(MDMA0_D0_IRQ_STATUS)
-#define bfin_write_MDMA0_D0_IRQ_STATUS(val) bfin_write16(MDMA0_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D0_PERIPHERAL_MAP() bfin_read16(MDMA0_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D0_CURR_X_COUNT() bfin_read16(MDMA0_D0_CURR_X_COUNT)
-#define bfin_write_MDMA0_D0_CURR_X_COUNT(val) bfin_write16(MDMA0_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D0_CURR_Y_COUNT() bfin_read16(MDMA0_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D0_CURR_Y_COUNT(val) bfin_write16(MDMA0_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_START_ADDR() bfin_readPTR(MDMA0_S0_START_ADDR)
-#define bfin_write_MDMA0_S0_START_ADDR(val) bfin_writePTR(MDMA0_S0_START_ADDR, val)
-#define bfin_read_MDMA0_S0_CONFIG()    bfin_read16(MDMA0_S0_CONFIG)
-#define bfin_write_MDMA0_S0_CONFIG(val) bfin_write16(MDMA0_S0_CONFIG, val)
-#define bfin_read_MDMA0_S0_X_COUNT()   bfin_read16(MDMA0_S0_X_COUNT)
-#define bfin_write_MDMA0_S0_X_COUNT(val) bfin_write16(MDMA0_S0_X_COUNT, val)
-#define bfin_read_MDMA0_S0_X_MODIFY()  bfin_read16(MDMA0_S0_X_MODIFY)
-#define bfin_write_MDMA0_S0_X_MODIFY(val) bfin_write16(MDMA0_S0_X_MODIFY, val)
-#define bfin_read_MDMA0_S0_Y_COUNT()   bfin_read16(MDMA0_S0_Y_COUNT)
-#define bfin_write_MDMA0_S0_Y_COUNT(val) bfin_write16(MDMA0_S0_Y_COUNT, val)
-#define bfin_read_MDMA0_S0_Y_MODIFY()  bfin_read16(MDMA0_S0_Y_MODIFY)
-#define bfin_write_MDMA0_S0_Y_MODIFY(val) bfin_write16(MDMA0_S0_Y_MODIFY, val)
-#define bfin_read_MDMA0_S0_CURR_DESC_PTR() bfin_readPTR(MDMA0_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S0_CURR_ADDR() bfin_readPTR(MDMA0_S0_CURR_ADDR)
-#define bfin_write_MDMA0_S0_CURR_ADDR(val) bfin_writePTR(MDMA0_S0_CURR_ADDR, val)
-#define bfin_read_MDMA0_S0_IRQ_STATUS() bfin_read16(MDMA0_S0_IRQ_STATUS)
-#define bfin_write_MDMA0_S0_IRQ_STATUS(val) bfin_write16(MDMA0_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S0_PERIPHERAL_MAP() bfin_read16(MDMA0_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S0_CURR_X_COUNT() bfin_read16(MDMA0_S0_CURR_X_COUNT)
-#define bfin_write_MDMA0_S0_CURR_X_COUNT(val) bfin_write16(MDMA0_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S0_CURR_Y_COUNT() bfin_read16(MDMA0_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S0_CURR_Y_COUNT(val) bfin_write16(MDMA0_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_START_ADDR() bfin_readPTR(MDMA0_D1_START_ADDR)
-#define bfin_write_MDMA0_D1_START_ADDR(val) bfin_writePTR(MDMA0_D1_START_ADDR, val)
-#define bfin_read_MDMA0_D1_CONFIG()    bfin_read16(MDMA0_D1_CONFIG)
-#define bfin_write_MDMA0_D1_CONFIG(val) bfin_write16(MDMA0_D1_CONFIG, val)
-#define bfin_read_MDMA0_D1_X_COUNT()   bfin_read16(MDMA0_D1_X_COUNT)
-#define bfin_write_MDMA0_D1_X_COUNT(val) bfin_write16(MDMA0_D1_X_COUNT, val)
-#define bfin_read_MDMA0_D1_X_MODIFY()  bfin_read16(MDMA0_D1_X_MODIFY)
-#define bfin_write_MDMA0_D1_X_MODIFY(val) bfin_write16(MDMA0_D1_X_MODIFY, val)
-#define bfin_read_MDMA0_D1_Y_COUNT()   bfin_read16(MDMA0_D1_Y_COUNT)
-#define bfin_write_MDMA0_D1_Y_COUNT(val) bfin_write16(MDMA0_D1_Y_COUNT, val)
-#define bfin_read_MDMA0_D1_Y_MODIFY()  bfin_read16(MDMA0_D1_Y_MODIFY)
-#define bfin_write_MDMA0_D1_Y_MODIFY(val) bfin_write16(MDMA0_D1_Y_MODIFY, val)
-#define bfin_read_MDMA0_D1_CURR_DESC_PTR() bfin_readPTR(MDMA0_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_D1_CURR_ADDR() bfin_readPTR(MDMA0_D1_CURR_ADDR)
-#define bfin_write_MDMA0_D1_CURR_ADDR(val) bfin_writePTR(MDMA0_D1_CURR_ADDR, val)
-#define bfin_read_MDMA0_D1_IRQ_STATUS() bfin_read16(MDMA0_D1_IRQ_STATUS)
-#define bfin_write_MDMA0_D1_IRQ_STATUS(val) bfin_write16(MDMA0_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_D1_PERIPHERAL_MAP() bfin_read16(MDMA0_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_D1_CURR_X_COUNT() bfin_read16(MDMA0_D1_CURR_X_COUNT)
-#define bfin_write_MDMA0_D1_CURR_X_COUNT(val) bfin_write16(MDMA0_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_D1_CURR_Y_COUNT() bfin_read16(MDMA0_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_D1_CURR_Y_COUNT(val) bfin_write16(MDMA0_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA0_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA0_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA0_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_START_ADDR() bfin_readPTR(MDMA0_S1_START_ADDR)
-#define bfin_write_MDMA0_S1_START_ADDR(val) bfin_writePTR(MDMA0_S1_START_ADDR, val)
-#define bfin_read_MDMA0_S1_CONFIG()    bfin_read16(MDMA0_S1_CONFIG)
-#define bfin_write_MDMA0_S1_CONFIG(val) bfin_write16(MDMA0_S1_CONFIG, val)
-#define bfin_read_MDMA0_S1_X_COUNT()   bfin_read16(MDMA0_S1_X_COUNT)
-#define bfin_write_MDMA0_S1_X_COUNT(val) bfin_write16(MDMA0_S1_X_COUNT, val)
-#define bfin_read_MDMA0_S1_X_MODIFY()  bfin_read16(MDMA0_S1_X_MODIFY)
-#define bfin_write_MDMA0_S1_X_MODIFY(val) bfin_write16(MDMA0_S1_X_MODIFY, val)
-#define bfin_read_MDMA0_S1_Y_COUNT()   bfin_read16(MDMA0_S1_Y_COUNT)
-#define bfin_write_MDMA0_S1_Y_COUNT(val) bfin_write16(MDMA0_S1_Y_COUNT, val)
-#define bfin_read_MDMA0_S1_Y_MODIFY()  bfin_read16(MDMA0_S1_Y_MODIFY)
-#define bfin_write_MDMA0_S1_Y_MODIFY(val) bfin_write16(MDMA0_S1_Y_MODIFY, val)
-#define bfin_read_MDMA0_S1_CURR_DESC_PTR() bfin_readPTR(MDMA0_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA0_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA0_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA0_S1_CURR_ADDR() bfin_readPTR(MDMA0_S1_CURR_ADDR)
-#define bfin_write_MDMA0_S1_CURR_ADDR(val) bfin_writePTR(MDMA0_S1_CURR_ADDR, val)
-#define bfin_read_MDMA0_S1_IRQ_STATUS() bfin_read16(MDMA0_S1_IRQ_STATUS)
-#define bfin_write_MDMA0_S1_IRQ_STATUS(val) bfin_write16(MDMA0_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA0_S1_PERIPHERAL_MAP() bfin_read16(MDMA0_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA0_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA0_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA0_S1_CURR_X_COUNT() bfin_read16(MDMA0_S1_CURR_X_COUNT)
-#define bfin_write_MDMA0_S1_CURR_X_COUNT(val) bfin_write16(MDMA0_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA0_S1_CURR_Y_COUNT() bfin_read16(MDMA0_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA0_S1_CURR_Y_COUNT(val) bfin_write16(MDMA0_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_START_ADDR() bfin_readPTR(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val) bfin_writePTR(MDMA1_D0_START_ADDR, val)
-#define bfin_read_MDMA1_D0_CONFIG()    bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val) bfin_write16(MDMA1_D0_CONFIG, val)
-#define bfin_read_MDMA1_D0_X_COUNT()   bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val) bfin_write16(MDMA1_D0_X_COUNT, val)
-#define bfin_read_MDMA1_D0_X_MODIFY()  bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val) bfin_write16(MDMA1_D0_X_MODIFY, val)
-#define bfin_read_MDMA1_D0_Y_COUNT()   bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val) bfin_write16(MDMA1_D0_Y_COUNT, val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()  bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val) bfin_write16(MDMA1_D0_Y_MODIFY, val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR() bfin_readPTR(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D0_CURR_ADDR() bfin_readPTR(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val) bfin_writePTR(MDMA1_D0_CURR_ADDR, val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS() bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val) bfin_write16(MDMA1_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP() bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT() bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT() bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_START_ADDR() bfin_readPTR(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val) bfin_writePTR(MDMA1_S0_START_ADDR, val)
-#define bfin_read_MDMA1_S0_CONFIG()    bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val) bfin_write16(MDMA1_S0_CONFIG, val)
-#define bfin_read_MDMA1_S0_X_COUNT()   bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val) bfin_write16(MDMA1_S0_X_COUNT, val)
-#define bfin_read_MDMA1_S0_X_MODIFY()  bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val) bfin_write16(MDMA1_S0_X_MODIFY, val)
-#define bfin_read_MDMA1_S0_Y_COUNT()   bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val) bfin_write16(MDMA1_S0_Y_COUNT, val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()  bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val) bfin_write16(MDMA1_S0_Y_MODIFY, val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR() bfin_readPTR(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S0_CURR_ADDR() bfin_readPTR(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val) bfin_writePTR(MDMA1_S0_CURR_ADDR, val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS() bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val) bfin_write16(MDMA1_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP() bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT() bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT() bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_START_ADDR() bfin_readPTR(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val) bfin_writePTR(MDMA1_D1_START_ADDR, val)
-#define bfin_read_MDMA1_D1_CONFIG()    bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val) bfin_write16(MDMA1_D1_CONFIG, val)
-#define bfin_read_MDMA1_D1_X_COUNT()   bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val) bfin_write16(MDMA1_D1_X_COUNT, val)
-#define bfin_read_MDMA1_D1_X_MODIFY()  bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val) bfin_write16(MDMA1_D1_X_MODIFY, val)
-#define bfin_read_MDMA1_D1_Y_COUNT()   bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val) bfin_write16(MDMA1_D1_Y_COUNT, val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()  bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val) bfin_write16(MDMA1_D1_Y_MODIFY, val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR() bfin_readPTR(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_D1_CURR_ADDR() bfin_readPTR(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val) bfin_writePTR(MDMA1_D1_CURR_ADDR, val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS() bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val) bfin_write16(MDMA1_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP() bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT() bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT() bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA1_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_START_ADDR() bfin_readPTR(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val) bfin_writePTR(MDMA1_S1_START_ADDR, val)
-#define bfin_read_MDMA1_S1_CONFIG()    bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val) bfin_write16(MDMA1_S1_CONFIG, val)
-#define bfin_read_MDMA1_S1_X_COUNT()   bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val) bfin_write16(MDMA1_S1_X_COUNT, val)
-#define bfin_read_MDMA1_S1_X_MODIFY()  bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val) bfin_write16(MDMA1_S1_X_MODIFY, val)
-#define bfin_read_MDMA1_S1_Y_COUNT()   bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val) bfin_write16(MDMA1_S1_Y_COUNT, val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()  bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val) bfin_write16(MDMA1_S1_Y_MODIFY, val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR() bfin_readPTR(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA1_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA1_S1_CURR_ADDR() bfin_readPTR(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val) bfin_writePTR(MDMA1_S1_CURR_ADDR, val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS() bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val) bfin_write16(MDMA1_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP() bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT() bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT() bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT, val)
-
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA0_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA0_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA0_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA0_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA0_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA0_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA0_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA0_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA0_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA0_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA0_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA0_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA0_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA0_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA0_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA0_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA0_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA0_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA0_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA0_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA0_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA0_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA0_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA0_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA0_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA0_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA0_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA0_D0_START_ADDR(val)
-
-#define bfin_read_MDMA_S1_CONFIG()  bfin_read_MDMA0_S1_CONFIG()
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA0_S1_CONFIG(val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()  bfin_read_MDMA0_S1_IRQ_STATUS()
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA0_S1_IRQ_STATUS(val)
-#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read_MDMA0_S1_X_MODIFY()
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA0_S1_X_MODIFY(val)
-#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read_MDMA0_S1_Y_MODIFY()
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA0_S1_Y_MODIFY(val)
-#define bfin_read_MDMA_S1_X_COUNT()  bfin_read_MDMA0_S1_X_COUNT()
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA0_S1_X_COUNT(val)
-#define bfin_read_MDMA_S1_Y_COUNT()  bfin_read_MDMA0_S1_Y_COUNT()
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA0_S1_Y_COUNT(val)
-#define bfin_read_MDMA_S1_START_ADDR()  bfin_read_MDMA0_S1_START_ADDR()
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA0_S1_START_ADDR(val)
-#define bfin_read_MDMA_D1_CONFIG()  bfin_read_MDMA0_D1_CONFIG()
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA0_D1_CONFIG(val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()  bfin_read_MDMA0_D1_IRQ_STATUS()
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA0_D1_IRQ_STATUS(val)
-#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read_MDMA0_D1_X_MODIFY()
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA0_D1_X_MODIFY(val)
-#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read_MDMA0_D1_Y_MODIFY()
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA0_D1_Y_MODIFY(val)
-#define bfin_read_MDMA_D1_X_COUNT()  bfin_read_MDMA0_D1_X_COUNT()
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA0_D1_X_COUNT(val)
-#define bfin_read_MDMA_D1_Y_COUNT()  bfin_read_MDMA0_D1_Y_COUNT()
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA0_D1_Y_COUNT(val)
-#define bfin_read_MDMA_D1_START_ADDR()  bfin_read_MDMA0_D1_START_ADDR()
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA0_D1_START_ADDR(val)
-
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
+#define bfin_read_MDMA_D0_CONFIG()    bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
+#define bfin_read_MDMA_D0_X_COUNT()   bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
+#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
+#define bfin_read_MDMA_D0_Y_COUNT()   bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
+#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
+#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
+#define bfin_read_MDMA_S0_CONFIG()    bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
+#define bfin_read_MDMA_S0_X_COUNT()   bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
+#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
+#define bfin_read_MDMA_S0_Y_COUNT()   bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
+#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
+#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
+#define bfin_read_MDMA_D1_CONFIG()    bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
+#define bfin_read_MDMA_D1_X_COUNT()   bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
+#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
+#define bfin_read_MDMA_D1_Y_COUNT()   bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
+#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
+#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
+#define bfin_read_MDMA_S1_CONFIG()    bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
+#define bfin_read_MDMA_S1_X_COUNT()   bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
+#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
+#define bfin_read_MDMA_S1_Y_COUNT()   bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
+#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
+#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
+#define bfin_read_MDMA_D2_CONFIG()    bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
+#define bfin_read_MDMA_D2_X_COUNT()   bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
+#define bfin_read_MDMA_D2_X_MODIFY()  bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
+#define bfin_read_MDMA_D2_Y_COUNT()   bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
+#define bfin_read_MDMA_D2_Y_MODIFY()  bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
+#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D2_CURR_ADDR() bfin_readPTR(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
+#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
+#define bfin_read_MDMA_S2_CONFIG()    bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
+#define bfin_read_MDMA_S2_X_COUNT()   bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
+#define bfin_read_MDMA_S2_X_MODIFY()  bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
+#define bfin_read_MDMA_S2_Y_COUNT()   bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
+#define bfin_read_MDMA_S2_Y_MODIFY()  bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
+#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S2_CURR_ADDR() bfin_readPTR(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
+#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
+#define bfin_read_MDMA_D3_CONFIG()    bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
+#define bfin_read_MDMA_D3_X_COUNT()   bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
+#define bfin_read_MDMA_D3_X_MODIFY()  bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
+#define bfin_read_MDMA_D3_Y_COUNT()   bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
+#define bfin_read_MDMA_D3_Y_MODIFY()  bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
+#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_D3_CURR_ADDR() bfin_readPTR(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
+#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
+#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
+#define bfin_read_MDMA_S3_CONFIG()    bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
+#define bfin_read_MDMA_S3_X_COUNT()   bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
+#define bfin_read_MDMA_S3_X_MODIFY()  bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
+#define bfin_read_MDMA_S3_Y_COUNT()   bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
+#define bfin_read_MDMA_S3_Y_MODIFY()  bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
+#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
+#define bfin_read_MDMA_S3_CURR_ADDR() bfin_readPTR(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
+#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
+#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
+#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
 #define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
 #define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
 #define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
@@ -2024,7 +1957,4 @@
 #define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
 #define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
 
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
index 198c4bbc8e5d..acc15f3aba38 100644
--- a/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/cdefBF539.h
@@ -1,6 +1,7 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
+/*
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
  */
 
 #ifndef _CDEF_BF539_H
@@ -9,7 +10,6 @@
 /* Include MMRs Common to BF538                                                                 */
 #include "cdefBF538.h"
 
-
 #define bfin_read_MXVR_CONFIG()        bfin_read16(MXVR_CONFIG)
 #define bfin_write_MXVR_CONFIG(val)    bfin_write16(MXVR_CONFIG, val)
 #define bfin_read_MXVR_PLL_CTL_0()     bfin_read32(MXVR_PLL_CTL_0)
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF538.h b/arch/blackfin/mach-bf538/include/mach/defBF538.h
new file mode 100644
index 000000000000..d27f81d6c4b1
--- /dev/null
+++ b/arch/blackfin/mach-bf538/include/mach/defBF538.h
@@ -0,0 +1,1825 @@
+/*
+ * Copyright 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
+ */
+
+#ifndef _DEF_BF538_H
+#define _DEF_BF538_H
+
+/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
+#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
+#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock     Count register (16-bit) */
+#define CHIPID                  0xFFC00014      /* Chip ID Register */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
+#define SYSCR                   0xFFC00104  /* System Configuration registe */
+#define SIC_RVECT               0xFFC00108
+#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register */
+#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3 */
+#define SIC_ISR0                        0xFFC00120  /* Interrupt Status Register */
+#define SIC_IWR0                        0xFFC00124  /* Interrupt Wakeup Register */
+#define SIC_IMASK1                      0xFFC00128      /* Interrupt Mask Register 1 */
+#define SIC_ISR1                        0xFFC0012C      /* Interrupt Status Register 1 */
+#define SIC_IWR1                        0xFFC00130      /* Interrupt Wakeup Register 1 */
+#define SIC_IAR4                        0xFFC00134      /* Interrupt Assignment Register 4 */
+#define SIC_IAR5                        0xFFC00138      /* Interrupt Assignment Register 5 */
+#define SIC_IAR6                        0xFFC0013C      /* Interrupt Assignment Register 6 */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
+#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
+#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT        0xFFC00300  /* RTC Status Register */
+#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
+#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
+#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
+#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
+#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
+#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR             0xFFC00400  /* Transmit Holding register */
+#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
+#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
+#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
+#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
+#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
+#define UART0_LCR             0xFFC0040C  /* Line Control Register */
+#define UART0_MCR                        0xFFC00410  /* Modem Control Register */
+#define UART0_LSR             0xFFC00414  /* Line Status Register */
+#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
+#define UART0_GCTL                   0xFFC00424  /* Global Control Register */
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
+
+#define SPI0_CTL                        0xFFC00500  /* SPI0 Control Register */
+#define SPI0_FLG                        0xFFC00504  /* SPI0 Flag register */
+#define SPI0_STAT                       0xFFC00508  /* SPI0 Status register */
+#define SPI0_TDBR                       0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR                       0xFFC00510  /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD                       0xFFC00514  /* SPI0 Baud rate Register */
+#define SPI0_SHADOW                     0xFFC00518  /* SPI0_RDBR Shadow Register */
+#define SPI0_REGBASE                    SPI0_CTL
+
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
+#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
+#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
+#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
+#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
+
+#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
+#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
+#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
+#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
+
+#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
+#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
+#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
+
+
+/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
+#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
+#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
+#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
+#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
+#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
+#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
+#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
+#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+/* Asynchronous Memory Controller  */
+#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller */
+#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
+
+
+
+/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+
+#define DMAC0_TC_PER                    0xFFC00B0C      /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TC_CNT                    0xFFC00B10      /* DMA Controller 0 Traffic Control Current Counts Register */
+
+
+
+/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)                                                    */
+
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR              0xFFC00E04      /* MemDMA0 Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG                  0xFFC00E08      /* MemDMA0 Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT         0xFFC00E10      /* MemDMA0 Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY                0xFFC00E14      /* MemDMA0 Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT         0xFFC00E18      /* MemDMA0 Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY                0xFFC00E1C      /* MemDMA0 Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR               0xFFC00E24      /* MemDMA0 Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS              0xFFC00E28      /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA0 Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA0 Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA0 Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR              0xFFC00E44      /* MemDMA0 Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG                  0xFFC00E48      /* MemDMA0 Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT         0xFFC00E50      /* MemDMA0 Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY                0xFFC00E54      /* MemDMA0 Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT         0xFFC00E58      /* MemDMA0 Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY                0xFFC00E5C      /* MemDMA0 Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR               0xFFC00E64      /* MemDMA0 Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS              0xFFC00E68      /* MemDMA0 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA0 Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA0 Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA0 Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR              0xFFC00E84      /* MemDMA0 Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG                  0xFFC00E88      /* MemDMA0 Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT         0xFFC00E90      /* MemDMA0 Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY                0xFFC00E94      /* MemDMA0 Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT         0xFFC00E98      /* MemDMA0 Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY                0xFFC00E9C      /* MemDMA0 Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR               0xFFC00EA4      /* MemDMA0 Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS              0xFFC00EA8      /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA0 Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA0 Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA0 Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR              0xFFC00EC4      /* MemDMA0 Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG                  0xFFC00EC8      /* MemDMA0 Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT         0xFFC00ED0      /* MemDMA0 Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY                0xFFC00ED4      /* MemDMA0 Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT         0xFFC00ED8      /* MemDMA0 Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY                0xFFC00EDC      /* MemDMA0 Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR               0xFFC00EE4      /* MemDMA0 Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS              0xFFC00EE8      /* MemDMA0 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA0 Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA0 Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA0 Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF)                        */
+#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
+#define TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
+#define TWI0_MASTER_CTL 0xFFC01414      /* Master Mode Control Register */
+#define TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
+#define TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
+#define TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
+#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register */
+#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
+#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register */
+
+#define TWI0_REGBASE            TWI0_CLKDIV
+
+/* the following are for backwards compatibility */
+#define TWI0_PRESCALE    TWI0_CONTROL
+#define TWI0_INT_SRC     TWI0_INT_STAT
+#define TWI0_INT_ENABLE  TWI0_INT_MASK
+
+
+/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
+
+/* GPIO Port C Register Names */
+#define PORTCIO_FER                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
+#define PORTCIO                         0xFFC01510      /* GPIO Pin Port C Data Register */
+#define PORTCIO_CLEAR                   0xFFC01520      /* Clear GPIO Pin Port C Register */
+#define PORTCIO_SET                     0xFFC01530      /* Set GPIO Pin Port C Register */
+#define PORTCIO_TOGGLE                  0xFFC01540      /* Toggle GPIO Pin Port C Register */
+#define PORTCIO_DIR                     0xFFC01550      /* GPIO Pin Port C Direction Register */
+#define PORTCIO_INEN                    0xFFC01560      /* GPIO Pin Port C Input Enable Register */
+
+/* GPIO Port D Register Names */
+#define PORTDIO_FER                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
+#define PORTDIO                         0xFFC01514      /* GPIO Pin Port D Data Register */
+#define PORTDIO_CLEAR                   0xFFC01524      /* Clear GPIO Pin Port D Register */
+#define PORTDIO_SET                     0xFFC01534      /* Set GPIO Pin Port D Register */
+#define PORTDIO_TOGGLE                  0xFFC01544      /* Toggle GPIO Pin Port D Register */
+#define PORTDIO_DIR                     0xFFC01554      /* GPIO Pin Port D Direction Register */
+#define PORTDIO_INEN                    0xFFC01564      /* GPIO Pin Port D Input Enable Register */
+
+/* GPIO Port E Register Names */
+#define PORTEIO_FER                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
+#define PORTEIO                         0xFFC01518      /* GPIO Pin Port E Data Register */
+#define PORTEIO_CLEAR                   0xFFC01528      /* Clear GPIO Pin Port E Register */
+#define PORTEIO_SET                     0xFFC01538      /* Set GPIO Pin Port E Register */
+#define PORTEIO_TOGGLE                  0xFFC01548      /* Toggle GPIO Pin Port E Register */
+#define PORTEIO_DIR                     0xFFC01558      /* GPIO Pin Port E Direction Register */
+#define PORTEIO_INEN                    0xFFC01568      /* GPIO Pin Port E Input Enable Register */
+
+/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
+
+#define DMAC1_TC_PER                    0xFFC01B0C      /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TC_CNT                    0xFFC01B10      /* DMA Controller 1 Traffic Control Current Counts Register */
+
+
+
+/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)                                                    */
+#define DMA8_NEXT_DESC_PTR              0xFFC01C00      /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR                 0xFFC01C04      /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG                             0xFFC01C08      /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT                    0xFFC01C10      /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY                   0xFFC01C14      /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT                    0xFFC01C18      /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY                   0xFFC01C1C      /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR              0xFFC01C20      /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR                  0xFFC01C24      /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS                 0xFFC01C28      /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP             0xFFC01C2C      /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT               0xFFC01C30      /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT               0xFFC01C38      /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC01C40      /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR                 0xFFC01C44      /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG                             0xFFC01C48      /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT                    0xFFC01C50      /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY                   0xFFC01C54      /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT                    0xFFC01C58      /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY                   0xFFC01C5C      /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR              0xFFC01C60      /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR                  0xFFC01C64      /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS                 0xFFC01C68      /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP             0xFFC01C6C      /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT               0xFFC01C70      /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT               0xFFC01C78      /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC01C80      /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR                0xFFC01C84      /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG                    0xFFC01C88      /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT                   0xFFC01C90      /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY                  0xFFC01C94      /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT                   0xFFC01C98      /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY                  0xFFC01C9C      /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR             0xFFC01CA0      /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR                 0xFFC01CA4      /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS                0xFFC01CA8      /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP    0xFFC01CAC      /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT              0xFFC01CB0      /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT              0xFFC01CB8      /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC01CC0      /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR                0xFFC01CC4      /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG                    0xFFC01CC8      /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT                   0xFFC01CD0      /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY                  0xFFC01CD4      /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT                   0xFFC01CD8      /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY                  0xFFC01CDC      /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR             0xFFC01CE0      /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR                 0xFFC01CE4      /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS                0xFFC01CE8      /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP    0xFFC01CEC      /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT              0xFFC01CF0      /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT              0xFFC01CF8      /* DMA Channel 11 Current Y Count Register */
+
+#define DMA12_NEXT_DESC_PTR             0xFFC01D00      /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR                0xFFC01D04      /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG                    0xFFC01D08      /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT                   0xFFC01D10      /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY                  0xFFC01D14      /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT                   0xFFC01D18      /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY                  0xFFC01D1C      /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR             0xFFC01D20      /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR                 0xFFC01D24      /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS                0xFFC01D28      /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP    0xFFC01D2C      /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT              0xFFC01D30      /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT              0xFFC01D38      /* DMA Channel 12 Current Y Count Register */
+
+#define DMA13_NEXT_DESC_PTR             0xFFC01D40      /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR                0xFFC01D44      /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG                    0xFFC01D48      /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT                   0xFFC01D50      /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY                  0xFFC01D54      /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT                   0xFFC01D58      /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY                  0xFFC01D5C      /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR             0xFFC01D60      /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR                 0xFFC01D64      /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS                0xFFC01D68      /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP    0xFFC01D6C      /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT              0xFFC01D70      /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT              0xFFC01D78      /* DMA Channel 13 Current Y Count Register */
+
+#define DMA14_NEXT_DESC_PTR             0xFFC01D80      /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR                0xFFC01D84      /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG                    0xFFC01D88      /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT                   0xFFC01D90      /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY                  0xFFC01D94      /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT                   0xFFC01D98      /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY                  0xFFC01D9C      /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR             0xFFC01DA0      /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR                 0xFFC01DA4      /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS                0xFFC01DA8      /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP    0xFFC01DAC      /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT              0xFFC01DB0      /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT              0xFFC01DB8      /* DMA Channel 14 Current Y Count Register */
+
+#define DMA15_NEXT_DESC_PTR             0xFFC01DC0      /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR                0xFFC01DC4      /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG                    0xFFC01DC8      /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT                   0xFFC01DD0      /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY                  0xFFC01DD4      /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT                   0xFFC01DD8      /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY                  0xFFC01DDC      /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR             0xFFC01DE0      /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR                 0xFFC01DE4      /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS                0xFFC01DE8      /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP    0xFFC01DEC      /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT              0xFFC01DF0      /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT              0xFFC01DF8      /* DMA Channel 15 Current Y Count Register */
+
+#define DMA16_NEXT_DESC_PTR             0xFFC01E00      /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR                0xFFC01E04      /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG                    0xFFC01E08      /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT                   0xFFC01E10      /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY                  0xFFC01E14      /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT                   0xFFC01E18      /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY                  0xFFC01E1C      /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR             0xFFC01E20      /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR                 0xFFC01E24      /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS                0xFFC01E28      /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP    0xFFC01E2C      /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT              0xFFC01E30      /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT              0xFFC01E38      /* DMA Channel 16 Current Y Count Register */
+
+#define DMA17_NEXT_DESC_PTR             0xFFC01E40      /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR                0xFFC01E44      /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG                    0xFFC01E48      /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT                   0xFFC01E50      /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY                  0xFFC01E54      /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT                   0xFFC01E58      /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY                  0xFFC01E5C      /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR             0xFFC01E60      /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR                 0xFFC01E64      /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS                0xFFC01E68      /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP    0xFFC01E6C      /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT              0xFFC01E70      /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT              0xFFC01E78      /* DMA Channel 17 Current Y Count Register */
+
+#define DMA18_NEXT_DESC_PTR             0xFFC01E80      /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR                0xFFC01E84      /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG                    0xFFC01E88      /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT                   0xFFC01E90      /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY                  0xFFC01E94      /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT                   0xFFC01E98      /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY                  0xFFC01E9C      /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR             0xFFC01EA0      /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR                 0xFFC01EA4      /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS                0xFFC01EA8      /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP    0xFFC01EAC      /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT              0xFFC01EB0      /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT              0xFFC01EB8      /* DMA Channel 18 Current Y Count Register */
+
+#define DMA19_NEXT_DESC_PTR             0xFFC01EC0      /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR                0xFFC01EC4      /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG                    0xFFC01EC8      /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT                   0xFFC01ED0      /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY                  0xFFC01ED4      /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT                   0xFFC01ED8      /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY                  0xFFC01EDC      /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR             0xFFC01EE0      /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR                 0xFFC01EE4      /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS                0xFFC01EE8      /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP    0xFFC01EEC      /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT              0xFFC01EF0      /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT              0xFFC01EF8      /* DMA Channel 19 Current Y Count Register */
+
+#define MDMA_D2_NEXT_DESC_PTR   0xFFC01F00      /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR              0xFFC01F04      /* MemDMA1 Stream 0 Destination Start Address Register */
+#define MDMA_D2_CONFIG                  0xFFC01F08      /* MemDMA1 Stream 0 Destination Configuration Register */
+#define MDMA_D2_X_COUNT         0xFFC01F10      /* MemDMA1 Stream 0 Destination X Count Register */
+#define MDMA_D2_X_MODIFY                0xFFC01F14      /* MemDMA1 Stream 0 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT         0xFFC01F18      /* MemDMA1 Stream 0 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY                0xFFC01F1C      /* MemDMA1 Stream 0 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR   0xFFC01F20      /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR               0xFFC01F24      /* MemDMA1 Stream 0 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS              0xFFC01F28      /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP  0xFFC01F2C      /* MemDMA1 Stream 0 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT    0xFFC01F30      /* MemDMA1 Stream 0 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT    0xFFC01F38      /* MemDMA1 Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S2_NEXT_DESC_PTR   0xFFC01F40      /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR              0xFFC01F44      /* MemDMA1 Stream 0 Source Start Address Register */
+#define MDMA_S2_CONFIG                  0xFFC01F48      /* MemDMA1 Stream 0 Source Configuration Register */
+#define MDMA_S2_X_COUNT         0xFFC01F50      /* MemDMA1 Stream 0 Source X Count Register */
+#define MDMA_S2_X_MODIFY                0xFFC01F54      /* MemDMA1 Stream 0 Source X Modify Register */
+#define MDMA_S2_Y_COUNT         0xFFC01F58      /* MemDMA1 Stream 0 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY                0xFFC01F5C      /* MemDMA1 Stream 0 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR   0xFFC01F60      /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR               0xFFC01F64      /* MemDMA1 Stream 0 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS              0xFFC01F68      /* MemDMA1 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP  0xFFC01F6C      /* MemDMA1 Stream 0 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT    0xFFC01F70      /* MemDMA1 Stream 0 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT    0xFFC01F78      /* MemDMA1 Stream 0 Source Current Y Count Register */
+
+#define MDMA_D3_NEXT_DESC_PTR   0xFFC01F80      /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR              0xFFC01F84      /* MemDMA1 Stream 1 Destination Start Address Register */
+#define MDMA_D3_CONFIG                  0xFFC01F88      /* MemDMA1 Stream 1 Destination Configuration Register */
+#define MDMA_D3_X_COUNT         0xFFC01F90      /* MemDMA1 Stream 1 Destination X Count Register */
+#define MDMA_D3_X_MODIFY                0xFFC01F94      /* MemDMA1 Stream 1 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT         0xFFC01F98      /* MemDMA1 Stream 1 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY                0xFFC01F9C      /* MemDMA1 Stream 1 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR   0xFFC01FA0      /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR               0xFFC01FA4      /* MemDMA1 Stream 1 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS              0xFFC01FA8      /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP  0xFFC01FAC      /* MemDMA1 Stream 1 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT    0xFFC01FB0      /* MemDMA1 Stream 1 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT    0xFFC01FB8      /* MemDMA1 Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S3_NEXT_DESC_PTR   0xFFC01FC0      /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR              0xFFC01FC4      /* MemDMA1 Stream 1 Source Start Address Register */
+#define MDMA_S3_CONFIG                  0xFFC01FC8      /* MemDMA1 Stream 1 Source Configuration Register */
+#define MDMA_S3_X_COUNT         0xFFC01FD0      /* MemDMA1 Stream 1 Source X Count Register */
+#define MDMA_S3_X_MODIFY                0xFFC01FD4      /* MemDMA1 Stream 1 Source X Modify Register */
+#define MDMA_S3_Y_COUNT         0xFFC01FD8      /* MemDMA1 Stream 1 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY                0xFFC01FDC      /* MemDMA1 Stream 1 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR   0xFFC01FE0      /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR               0xFFC01FE4      /* MemDMA1 Stream 1 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS              0xFFC01FE8      /* MemDMA1 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP  0xFFC01FEC      /* MemDMA1 Stream 1 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT    0xFFC01FF0      /* MemDMA1 Stream 1 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT    0xFFC01FF8      /* MemDMA1 Stream 1 Source Current Y Count Register */
+
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)        */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte) */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte) */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register */
+
+
+/* UART2 Controller             (0xFFC02100 - 0xFFC021FF)        */
+#define UART2_THR                       0xFFC02100      /* Transmit Holding register */
+#define UART2_RBR                       0xFFC02100      /* Receive Buffer register */
+#define UART2_DLL                       0xFFC02100      /* Divisor Latch (Low-Byte) */
+#define UART2_IER                       0xFFC02104      /* Interrupt Enable Register */
+#define UART2_DLH                       0xFFC02104      /* Divisor Latch (High-Byte) */
+#define UART2_IIR                       0xFFC02108      /* Interrupt Identification Register */
+#define UART2_LCR                       0xFFC0210C      /* Line Control Register */
+#define UART2_MCR                       0xFFC02110      /* Modem Control Register */
+#define UART2_LSR                       0xFFC02114      /* Line Status Register */
+#define UART2_SCR                       0xFFC0211C      /* SCR Scratch Register */
+#define UART2_GCTL                      0xFFC02124      /* Global Control Register */
+
+
+/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF)                        */
+#define TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
+#define TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTL          0xFFC02208      /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xFFC02214      /* Master Mode Control Register */
+#define TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
+#define TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTL           0xFFC02228      /* FIFO Control Register */
+#define TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
+#define TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8          0xFFC02288      /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16         0xFFC0228C      /* FIFO Receive Data Double Byte Register */
+#define TWI1_REGBASE            TWI1_CLKDIV
+
+
+/* the following are for backwards compatibility */
+#define TWI1_PRESCALE     TWI1_CONTROL
+#define TWI1_INT_SRC      TWI1_INT_STAT
+#define TWI1_INT_ENABLE   TWI1_INT_MASK
+
+
+/* SPI1 Controller              (0xFFC02300 - 0xFFC023FF)        */
+#define SPI1_CTL                        0xFFC02300  /* SPI1 Control Register */
+#define SPI1_FLG                        0xFFC02304  /* SPI1 Flag register */
+#define SPI1_STAT                       0xFFC02308  /* SPI1 Status register */
+#define SPI1_TDBR                       0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR                       0xFFC02310  /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD                       0xFFC02314  /* SPI1 Baud rate Register */
+#define SPI1_SHADOW                     0xFFC02318  /* SPI1_RDBR Shadow Register */
+#define SPI1_REGBASE                    SPI1_CTL
+
+/* SPI2 Controller              (0xFFC02400 - 0xFFC024FF)        */
+#define SPI2_CTL                        0xFFC02400  /* SPI2 Control Register */
+#define SPI2_FLG                        0xFFC02404  /* SPI2 Flag register */
+#define SPI2_STAT                       0xFFC02408  /* SPI2 Status register */
+#define SPI2_TDBR                       0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR                       0xFFC02410  /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD                       0xFFC02414  /* SPI2 Baud rate Register */
+#define SPI2_SHADOW                     0xFFC02418  /* SPI2_RDBR Shadow Register */
+#define SPI2_REGBASE                    SPI2_CTL
+
+/* SPORT2 Controller            (0xFFC02500 - 0xFFC025FF)                        */
+#define SPORT2_TCR1                     0xFFC02500      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2                     0xFFC02504      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV          0xFFC02508      /* SPORT2 Transmit Clock Divider */
+#define SPORT2_TFSDIV           0xFFC0250C      /* SPORT2 Transmit Frame Sync Divider */
+#define SPORT2_TX                       0xFFC02510      /* SPORT2 TX Data Register */
+#define SPORT2_RX                       0xFFC02518      /* SPORT2 RX Data Register */
+#define SPORT2_RCR1                     0xFFC02520      /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_RCR2                     0xFFC02524      /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_RCLKDIV          0xFFC02528      /* SPORT2 Receive Clock Divider */
+#define SPORT2_RFSDIV           0xFFC0252C      /* SPORT2 Receive Frame Sync Divider */
+#define SPORT2_STAT                     0xFFC02530      /* SPORT2 Status Register */
+#define SPORT2_CHNL                     0xFFC02534      /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1            0xFFC02538      /* SPORT2 Multi-Channel Configuration Register 1 */
+#define SPORT2_MCMC2            0xFFC0253C      /* SPORT2 Multi-Channel Configuration Register 2 */
+#define SPORT2_MTCS0            0xFFC02540      /* SPORT2 Multi-Channel Transmit Select Register 0 */
+#define SPORT2_MTCS1            0xFFC02544      /* SPORT2 Multi-Channel Transmit Select Register 1 */
+#define SPORT2_MTCS2            0xFFC02548      /* SPORT2 Multi-Channel Transmit Select Register 2 */
+#define SPORT2_MTCS3            0xFFC0254C      /* SPORT2 Multi-Channel Transmit Select Register 3 */
+#define SPORT2_MRCS0            0xFFC02550      /* SPORT2 Multi-Channel Receive Select Register 0 */
+#define SPORT2_MRCS1            0xFFC02554      /* SPORT2 Multi-Channel Receive Select Register 1 */
+#define SPORT2_MRCS2            0xFFC02558      /* SPORT2 Multi-Channel Receive Select Register 2 */
+#define SPORT2_MRCS3            0xFFC0255C      /* SPORT2 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT3 Controller            (0xFFC02600 - 0xFFC026FF)                        */
+#define SPORT3_TCR1                     0xFFC02600      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2                     0xFFC02604      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV          0xFFC02608      /* SPORT3 Transmit Clock Divider */
+#define SPORT3_TFSDIV           0xFFC0260C      /* SPORT3 Transmit Frame Sync Divider */
+#define SPORT3_TX                       0xFFC02610      /* SPORT3 TX Data Register */
+#define SPORT3_RX                       0xFFC02618      /* SPORT3 RX Data Register */
+#define SPORT3_RCR1                     0xFFC02620      /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_RCR2                     0xFFC02624      /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_RCLKDIV          0xFFC02628      /* SPORT3 Receive Clock Divider */
+#define SPORT3_RFSDIV           0xFFC0262C      /* SPORT3 Receive Frame Sync Divider */
+#define SPORT3_STAT                     0xFFC02630      /* SPORT3 Status Register */
+#define SPORT3_CHNL                     0xFFC02634      /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1            0xFFC02638      /* SPORT3 Multi-Channel Configuration Register 1 */
+#define SPORT3_MCMC2            0xFFC0263C      /* SPORT3 Multi-Channel Configuration Register 2 */
+#define SPORT3_MTCS0            0xFFC02640      /* SPORT3 Multi-Channel Transmit Select Register 0 */
+#define SPORT3_MTCS1            0xFFC02644      /* SPORT3 Multi-Channel Transmit Select Register 1 */
+#define SPORT3_MTCS2            0xFFC02648      /* SPORT3 Multi-Channel Transmit Select Register 2 */
+#define SPORT3_MTCS3            0xFFC0264C      /* SPORT3 Multi-Channel Transmit Select Register 3 */
+#define SPORT3_MRCS0            0xFFC02650      /* SPORT3 Multi-Channel Receive Select Register 0 */
+#define SPORT3_MRCS1            0xFFC02654      /* SPORT3 Multi-Channel Receive Select Register 1 */
+#define SPORT3_MRCS2            0xFFC02658      /* SPORT3 Multi-Channel Receive Select Register 2 */
+#define SPORT3_MRCS3            0xFFC0265C      /* SPORT3 Multi-Channel Receive Select Register 3 */
+
+
+/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                */
+/* For Mailboxes 0-15                                                                                    */
+#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1  */
+#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1 */
+#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1 */
+#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1 */
+#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1 */
+#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1 */
+#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1 */
+#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmission reg 1 */
+
+/* For Mailboxes 16-31                                                                                   */
+#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2  */
+#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2 */
+#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2 */
+#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2 */
+#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2 */
+#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2 */
+#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2 */
+#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmission reg 2 */
+
+#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0 */
+#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1 */
+
+#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                */
+/* the following is for backwards compatibility */
+#define CAN_CNF          CAN_DEBUG
+
+#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register */
+#define CAN_CEC                         0xFFC02A90      /* Error Counter Register */
+#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register */
+#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register */
+#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register */
+#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register */
+#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register */
+#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature */
+#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level */
+#define CAN_ESR                         0xFFC02AB4      /* Error Status Register */
+#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter     */
+#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Reload/Capture Register */
+#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks                                      */
+#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x)                     (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x)                     (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers                                                                     */
+#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits and Macros */
+/******************************************************************************* */
+
+/* SWRST Mask */
+#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
+#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks                                                                                                   */
+#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
+#define PLL_WAKEUP_IRQ          0x00000001      /* PLL Wakeup Interrupt Request */
+#define DMAC0_ERR_IRQ           0x00000002      /* DMA Controller 0 Error Interrupt Request */
+#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
+#define SPORT0_ERR_IRQ          0x00000008      /* SPORT0 Error Interrupt Request */
+#define SPORT1_ERR_IRQ          0x00000010      /* SPORT1 Error Interrupt Request */
+#define SPI0_ERR_IRQ            0x00000020      /* SPI0 Error Interrupt Request */
+#define UART0_ERR_IRQ           0x00000040      /* UART0 Error Interrupt Request */
+#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
+#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
+#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
+#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
+#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
+#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
+#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
+#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
+#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
+#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
+#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
+#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
+#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
+#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
+#define MDMA0_0_IRQ             0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
+#define MDMA0_1_IRQ             0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
+#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
+#define DMAC1_ERR_IRQ           0x01000000      /* DMA Controller 1 Error Interrupt Request */
+#define SPORT2_ERR_IRQ          0x02000000      /* SPORT2 Error Interrupt Request */
+#define SPORT3_ERR_IRQ          0x04000000      /* SPORT3 Error Interrupt Request */
+#define MXVR_SD_IRQ             0x08000000      /* MXVR Synchronous Data Interrupt Request */
+#define SPI1_ERR_IRQ            0x10000000      /* SPI1 Error Interrupt Request */
+#define SPI2_ERR_IRQ            0x20000000      /* SPI2 Error Interrupt Request */
+#define UART1_ERR_IRQ           0x40000000      /* UART1 Error Interrupt Request */
+#define UART2_ERR_IRQ           0x80000000      /* UART2 Error Interrupt Request */
+
+/* the following are for backwards compatibility */
+#define DMA0_ERR_IRQ            DMAC0_ERR_IRQ
+#define DMA1_ERR_IRQ            DMAC1_ERR_IRQ
+
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1   */
+#define CAN_ERR_IRQ                     0x00000001      /* CAN Error Interrupt Request */
+#define DMA8_IRQ                        0x00000002      /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
+#define DMA9_IRQ                        0x00000004      /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
+#define DMA10_IRQ                       0x00000008      /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
+#define DMA11_IRQ                       0x00000010      /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
+#define DMA12_IRQ                       0x00000020      /* DMA Channel 12 Interrupt Request */
+#define DMA13_IRQ                       0x00000040      /* DMA Channel 13 Interrupt Request */
+#define DMA14_IRQ                       0x00000080      /* DMA Channel 14 (SPI1) Interrupt Request */
+#define DMA15_IRQ                       0x00000100      /* DMA Channel 15 (SPI2) Interrupt Request */
+#define DMA16_IRQ                       0x00000200      /* DMA Channel 16 (UART1 RX) Interrupt Request */
+#define DMA17_IRQ                       0x00000400      /* DMA Channel 17 (UART1 TX) Interrupt Request */
+#define DMA18_IRQ                       0x00000800      /* DMA Channel 18 (UART2 RX) Interrupt Request */
+#define DMA19_IRQ                       0x00001000      /* DMA Channel 19 (UART2 TX) Interrupt Request */
+#define TWI0_IRQ                        0x00002000      /* TWI0 Interrupt Request */
+#define TWI1_IRQ                        0x00004000      /* TWI1 Interrupt Request */
+#define CAN_RX_IRQ                      0x00008000      /* CAN Receive Interrupt Request */
+#define CAN_TX_IRQ                      0x00010000      /* CAN Transmit Interrupt Request */
+#define MDMA1_0_IRQ                     0x00020000      /* MemDMA1 Stream 0 Interrupt Request */
+#define MDMA1_1_IRQ                     0x00040000      /* MemDMA1 Stream 1 Interrupt Request */
+#define MXVR_STAT_IRQ                   0x00080000      /* MXVR Status Interrupt Request */
+#define MXVR_CM_IRQ                     0x00100000      /* MXVR Control Message Interrupt Request */
+#define MXVR_AP_IRQ                     0x00200000      /* MXVR Asynchronous Packet Interrupt */
+
+/* the following are for backwards compatibility */
+#define MDMA0_IRQ               MDMA1_0_IRQ
+#define MDMA1_IRQ               MDMA1_1_IRQ
+
+#ifdef _MISRA_RULES
+#define _MF15 0xFu
+#define _MF7 7u
+#else
+#define _MF15 0xF
+#define _MF7 7
+#endif /* _MISRA_RULES */
+
+/* SIC_IMASKx Masks                                                                                      */
+#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts */
+#ifdef _MISRA_RULES
+#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt */
+#else
+#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt */
+#endif /* _MISRA_RULES */
+
+/* SIC_IWRx Masks                                                                                        */
+#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals */
+#ifdef _MISRA_RULES
+#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x */
+#else
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x */
+#endif /* _MISRA_RULES */
+
+/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
+/*  PPI_CONTROL Masks         */
+#define PORT_EN         0x0001  /* PPI Port Enable  */
+#define PORT_DIR        0x0002  /* PPI Port Direction       */
+#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
+#define PORT_CFG        0x0030  /* PPI Port Configuration */
+#define FLD_SEL         0x0040  /* PPI Active Field Select */
+#define PACK_EN         0x0080  /* PPI Packing Mode */
+/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
+#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
+#define DLENGTH         0x3800  /* PPI Data Length  */
+#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
+#define DLEN_10         0x0800          /* Data Length = 10 Bits */
+#define DLEN_11         0x1000          /* Data Length = 11 Bits */
+#define DLEN_12         0x1800          /* Data Length = 12 Bits */
+#define DLEN_13         0x2000          /* Data Length = 13 Bits */
+#define DLEN_14         0x2800          /* Data Length = 14 Bits */
+#define DLEN_15         0x3000          /* Data Length = 15 Bits */
+#define DLEN_16         0x3800          /* Data Length = 16 Bits */
+#ifdef _MISRA_RULES
+#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#else
+#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#endif /* _MISRA_RULES */
+#define POL                     0xC000  /* PPI Signal Polarities       */
+#define POLC            0x4000          /* PPI Clock Polarity */
+#define POLS            0x8000          /* PPI Frame Sync Polarity */
+
+
+/* PPI_STATUS Masks                                          */
+#define FLD                     0x0400  /* Field Indicator   */
+#define FT_ERR          0x0800  /* Frame Track Error */
+#define OVR                     0x1000  /* FIFO Overflow Error */
+#define UNDR            0x2000  /* FIFO Underrun Error */
+#define ERR_DET         0x4000  /* Error Detected Indicator */
+#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
+
+
+/* **********  DMA CONTROLLER MASKS  ***********************/
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
+#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
+#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
+#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
+#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
+#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
+#define PMAP                    0xF000  /* DMA Peripheral Map Field */
+
+/* PMAP Encodings For DMA Controller 0 */
+#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI0               0x5000  /* PMAP SPI DMA */
+#define PMAP_UART0RX            0x6000  /* PMAP UART Receive DMA */
+#define PMAP_UART0TX            0x7000  /* PMAP UART Transmit DMA */
+
+/* PMAP Encodings For DMA Controller 1 */
+#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
+#define PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
+#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
+#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
+#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
+#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
+#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
+#define PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
+#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
+#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
+
+
+/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
+/* PWM Timer bit definitions */
+/* TIMER_ENABLE Register */
+#define TIMEN0                  0x0001  /* Enable Timer 0 */
+#define TIMEN1                  0x0002  /* Enable Timer 1 */
+#define TIMEN2                  0x0004  /* Enable Timer 2 */
+
+#define TIMEN0_P                0x00
+#define TIMEN1_P                0x01
+#define TIMEN2_P                0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0                 0x0001  /* Disable Timer 0 */
+#define TIMDIS1                 0x0002  /* Disable Timer 1 */
+#define TIMDIS2                 0x0004  /* Disable Timer 2 */
+
+#define TIMDIS0_P               0x00
+#define TIMDIS1_P               0x01
+#define TIMDIS2_P               0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0                  0x0001  /* Timer 0 Interrupt */
+#define TIMIL1                  0x0002  /* Timer 1 Interrupt */
+#define TIMIL2                  0x0004  /* Timer 2 Interrupt */
+#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow */
+#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow */
+#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow */
+#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status */
+#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status */
+#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status */
+
+#define TIMIL0_P                0x00
+#define TIMIL1_P                0x01
+#define TIMIL2_P                0x02
+#define TOVF_ERR0_P             0x04
+#define TOVF_ERR1_P             0x05
+#define TOVF_ERR2_P             0x06
+#define TRUN0_P                 0x0C
+#define TRUN1_P                 0x0D
+#define TRUN2_P                 0x0E
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0               TOVF_ERR0
+#define TOVL_ERR1               TOVF_ERR1
+#define TOVL_ERR2               TOVF_ERR2
+#define TOVL_ERR0_P             TOVF_ERR0_P
+#define TOVL_ERR1_P     TOVF_ERR1_P
+#define TOVL_ERR2_P     TOVF_ERR2_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT                 0x0001
+#define WDTH_CAP                0x0002
+#define EXT_CLK                 0x0003
+#define PULSE_HI                0x0004
+#define PERIOD_CNT              0x0008
+#define IRQ_ENA                 0x0010
+#define TIN_SEL                 0x0020
+#define OUT_DIS                 0x0040
+#define CLK_SEL                 0x0080
+#define TOGGLE_HI               0x0100
+#define EMU_RUN                 0x0200
+#ifdef _MISRA_RULES
+#define ERR_TYP(x)              (((x) & 0x03u) << 14)
+#else
+#define ERR_TYP(x)              (((x) & 0x03) << 14)
+#endif /* _MISRA_RULES */
+
+#define TMODE_P0                0x00
+#define TMODE_P1                0x01
+#define PULSE_HI_P              0x02
+#define PERIOD_CNT_P    0x03
+#define IRQ_ENA_P               0x04
+#define TIN_SEL_P               0x05
+#define OUT_DIS_P               0x06
+#define CLK_SEL_P               0x07
+#define TOGGLE_HI_P             0x08
+#define EMU_RUN_P               0x09
+#define ERR_TYP_P0              0x0E
+#define ERR_TYP_P1              0x0F
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN          0x0001  /* Enable CLKOUT */
+#define AMBEN_NONE      0x0000  /* All Banks Disabled */
+#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO          0x0100  /* DMA has priority over core for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P                0x0000  /* Enable CLKOUT */
+#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+/* EBIU_SDGCTL Masks */
+#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE                             0x00000010 /* Enable SDRAM prefetch */
+#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD                   0x00200000 /*Power-up start delay */
+#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE                   0x02000000 /* Enable external buffering timing */
+#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
+#define EMREN                   0x10000000 /* Extended mode register enable */
+#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE                             0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16                 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32                 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64                 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
+#define EBSZ_256                0x00000008 /* SDRAM External Bank Size = 256MB */
+#define EBSZ_512                0x0000000A /* SDRAM External Bank Size = 512MB */
+#define EBCAW_8                 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9                 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                    0x00000001 /* SDRAM controller is idle */
+#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA                   0x00000004 /* SDRAM power up active  */
+#define SDRS                    0x00000008 /* SDRAM is in reset state */
+#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                  0x00000020 /* Bus granted */
+
+
+/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
+/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
+#ifdef _MISRA_RULES
+#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
+#else
+#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
+#endif /* _MISRA_RULES */
+
+/* TWIx_PRESCALE Masks                                                           */
+#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA         0x0080          /* TWI Enable            */
+#define SCCB            0x0200          /* SCCB Compatibility Enable */
+
+/* TWIx_SLAVE_CTRL Masks                                                                 */
+#define SEN                     0x0001          /* Slave Enable          */
+#define SADD_LEN        0x0002          /* Slave Address Length */
+#define STDVAL          0x0004          /* Slave Transmit Data Valid */
+#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
+
+/* TWIx_SLAVE_STAT Masks                                                                 */
+#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002          /* General Call Indicator */
+
+/* TWIx_MASTER_CTRL Masks                                                */
+#define MEN                     0x0001          /* Master Mode Enable */
+#define MADD_LEN        0x0002          /* Master Address Length */
+#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
+#define FAST            0x0008          /* Use Fast Mode Timing Specs */
+#define STOP            0x0010          /* Issue Stop Condition */
+#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT            0x3FC0          /* Data Bytes To Transfer */
+#define SDAOVR          0x4000          /* Serial Data Override */
+#define SCLOVR          0x8000          /* Serial Clock Override */
+
+/* TWIx_MASTER_STAT Masks                                                        */
+#define MPROG           0x0001          /* Master Transfer In Progress */
+#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK            0x0004          /* Address Not Acknowledged */
+#define DNAK            0x0008          /* Data Not Acknowledged */
+#define BUFRDERR        0x0010          /* Buffer Read Error */
+#define BUFWRERR        0x0020          /* Buffer Write Error */
+#define SDASEN          0x0040          /* Serial Data Sense */
+#define SCLSEN          0x0080          /* Serial Clock Sense */
+#define BUSBUSY         0x0100          /* Bus Busy Indicator */
+
+/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
+#define SINIT           0x0001          /* Slave Transfer Initiated */
+#define SCOMP           0x0002          /* Slave Transfer Complete */
+#define SERR            0x0004          /* Slave Transfer Error */
+#define SOVF            0x0008          /* Slave Overflow */
+#define MCOMP           0x0010          /* Master Transfer Complete */
+#define MERR            0x0020          /* Master Transfer Error */
+#define XMTSERV         0x0040          /* Transmit FIFO Service */
+#define RCVSERV         0x0080          /* Receive FIFO Service */
+
+/* TWIx_FIFO_CTL Masks                                   */
+#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
+#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
+#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
+
+/* TWIx_FIFO_STAT Masks                                                          */
+#define XMTSTAT         0x0003          /* Transmit FIFO Status */
+#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
+#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT         0x000C          /* Receive FIFO Status */
+#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
+#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
+
+#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index 7a8ac5f44204..8100bcd01a0d 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1,859 +1,13 @@
 /*
- * Copyright 2008-2009 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF538/9 */
-
 #ifndef _DEF_BF539_H
 #define _DEF_BF539_H
 
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
-#define PLL_CTL                 0xFFC00000      /* PLL Control register (16-bit) */
-#define PLL_DIV                 0xFFC00004      /* PLL Divide Register (16-bit) */
-#define VR_CTL                  0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                0xFFC0000C      /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT             0xFFC00010      /* PLL Lock     Count register (16-bit) */
-#define CHIPID                  0xFFC00014      /* Chip ID Register */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR                   0xFFC00104  /* System Configuration registe */
-#define SIC_RVECT               0xFFC00108
-#define SIC_IMASK0              0xFFC0010C  /* Interrupt Mask Register */
-#define SIC_IAR0                0xFFC00110  /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                0xFFC00114  /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                0xFFC00118  /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                        0xFFC00120  /* Interrupt Status Register */
-#define SIC_IWR0                        0xFFC00124  /* Interrupt Wakeup Register */
-#define SIC_IMASK1                      0xFFC00128      /* Interrupt Mask Register 1 */
-#define SIC_ISR1                        0xFFC0012C      /* Interrupt Status Register 1 */
-#define SIC_IWR1                        0xFFC00130      /* Interrupt Wakeup Register 1 */
-#define SIC_IAR4                        0xFFC00134      /* Interrupt Assignment Register 4 */
-#define SIC_IAR5                        0xFFC00138      /* Interrupt Assignment Register 5 */
-#define SIC_IAR6                        0xFFC0013C      /* Interrupt Assignment Register 6 */
-
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL        0xFFC00200  /* Watchdog Control Register */
-#define WDOG_CNT        0xFFC00204  /* Watchdog Count Register */
-#define WDOG_STAT       0xFFC00208  /* Watchdog Status Register */
-
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT        0xFFC00300  /* RTC Status Register */
-#define RTC_ICTL        0xFFC00304  /* RTC Interrupt Control Register */
-#define RTC_ISTAT       0xFFC00308  /* RTC Interrupt Status Register */
-#define RTC_SWCNT       0xFFC0030C  /* RTC Stopwatch Count Register */
-#define RTC_ALARM       0xFFC00310  /* RTC Alarm Time Register */
-#define RTC_FAST        0xFFC00314  /* RTC Prescaler Enable Register */
-#define RTC_PREN                0xFFC00314  /* RTC Prescaler Enable Register (alternate macro) */
-
-
-/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART0_THR             0xFFC00400  /* Transmit Holding register */
-#define UART0_RBR             0xFFC00400  /* Receive Buffer register */
-#define UART0_DLL             0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define UART0_IER             0xFFC00404  /* Interrupt Enable Register */
-#define UART0_DLH             0xFFC00404  /* Divisor Latch (High-Byte) */
-#define UART0_IIR             0xFFC00408  /* Interrupt Identification Register */
-#define UART0_LCR             0xFFC0040C  /* Line Control Register */
-#define UART0_MCR                        0xFFC00410  /* Modem Control Register */
-#define UART0_LSR             0xFFC00414  /* Line Status Register */
-#define UART0_SCR             0xFFC0041C  /* SCR Scratch Register */
-#define UART0_GCTL                   0xFFC00424  /* Global Control Register */
-
-
-/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
-
-#define SPI0_CTL                        0xFFC00500  /* SPI0 Control Register */
-#define SPI0_FLG                        0xFFC00504  /* SPI0 Flag register */
-#define SPI0_STAT                       0xFFC00508  /* SPI0 Status register */
-#define SPI0_TDBR                       0xFFC0050C  /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                       0xFFC00510  /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                       0xFFC00514  /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                     0xFFC00518  /* SPI0_RDBR Shadow Register */
-#define SPI0_REGBASE                    SPI0_CTL
-
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-#define TIMER0_CONFIG                   0xFFC00600     /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                          0xFFC00604     /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                   0xFFC00608     /* Timer 0 Period Register */
-#define TIMER0_WIDTH                    0xFFC0060C     /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE                            0xFFC00640      /* Timer Enable Register */
-#define TIMER_DISABLE                           0xFFC00644      /* Timer Disable Register */
-#define TIMER_STATUS                            0xFFC00648      /* Timer Status Register */
-
-
-/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
-#define FIO_FLAG_D                              0xFFC00700  /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C                      0xFFC00704  /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S                      0xFFC00708  /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T                                      0xFFC0070C  /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D                     0xFFC00710  /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C                     0xFFC00714  /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S                     0xFFC00718  /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T                     0xFFC0071C  /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D                     0xFFC00720  /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C                     0xFFC00724  /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S                     0xFFC00728  /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T                     0xFFC0072C  /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                         0xFFC00730  /* Peripheral Flag Direction Register */
-#define FIO_POLAR                       0xFFC00734  /* Flag Source Polarity Register */
-#define FIO_EDGE                        0xFFC00738  /* Flag Source Sensitivity Register */
-#define FIO_BOTH                        0xFFC0073C  /* Flag Set on BOTH Edges Register */
-#define FIO_INEN                                        0xFFC00740  /* Flag Input Enable Register  */
-
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                             0xFFC00800  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                             0xFFC00804  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808  /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C  /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810  /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818  /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                             0xFFC00820  /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                             0xFFC00824  /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828  /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C  /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830  /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834  /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838  /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C  /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840  /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844  /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848  /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C  /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850  /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854  /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858  /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C  /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                             0xFFC00900  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                             0xFFC00904  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908  /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C  /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910  /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918  /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                             0xFFC00920  /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                             0xFFC00924  /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928  /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C  /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930  /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934  /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938  /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C  /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940  /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944  /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948  /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C  /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950  /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954  /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958  /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C  /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-/* Asynchronous Memory Controller  */
-#define EBIU_AMGCTL                     0xFFC00A00  /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0            0xFFC00A04  /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1            0xFFC00A08  /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller */
-#define EBIU_SDGCTL                     0xFFC00A10  /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                     0xFFC00A14  /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                      0xFFC00A18  /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                     0xFFC00A1C  /* SDRAM Status Register */
-
-
-
-/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
-
-#define DMAC0_TC_PER                    0xFFC00B0C      /* DMA Controller 0 Traffic Control Periods Register */
-#define DMAC0_TC_CNT                    0xFFC00B10      /* DMA Controller 0 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA0_TCPER                      DMAC0_TC_PER
-#define DMA0_TCCNT                      DMAC0_TC_CNT
-
-
-/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF)                                                    */
-
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
-
-#define MDMA0_D0_NEXT_DESC_PTR  0xFFC00E00      /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA0_D0_START_ADDR             0xFFC00E04      /* MemDMA0 Stream 0 Destination Start Address Register */
-#define MDMA0_D0_CONFIG                 0xFFC00E08      /* MemDMA0 Stream 0 Destination Configuration Register */
-#define MDMA0_D0_X_COUNT                0xFFC00E10      /* MemDMA0 Stream 0 Destination X Count Register */
-#define MDMA0_D0_X_MODIFY               0xFFC00E14      /* MemDMA0 Stream 0 Destination X Modify Register */
-#define MDMA0_D0_Y_COUNT                0xFFC00E18      /* MemDMA0 Stream 0 Destination Y Count Register */
-#define MDMA0_D0_Y_MODIFY               0xFFC00E1C      /* MemDMA0 Stream 0 Destination Y Modify Register */
-#define MDMA0_D0_CURR_DESC_PTR  0xFFC00E20      /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA0_D0_CURR_ADDR              0xFFC00E24      /* MemDMA0 Stream 0 Destination Current Address Register */
-#define MDMA0_D0_IRQ_STATUS             0xFFC00E28      /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
-#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C      /* MemDMA0 Stream 0 Destination Peripheral Map Register */
-#define MDMA0_D0_CURR_X_COUNT   0xFFC00E30      /* MemDMA0 Stream 0 Destination Current X Count Register */
-#define MDMA0_D0_CURR_Y_COUNT   0xFFC00E38      /* MemDMA0 Stream 0 Destination Current Y Count Register */
-
-#define MDMA0_S0_NEXT_DESC_PTR  0xFFC00E40      /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA0_S0_START_ADDR             0xFFC00E44      /* MemDMA0 Stream 0 Source Start Address Register */
-#define MDMA0_S0_CONFIG                 0xFFC00E48      /* MemDMA0 Stream 0 Source Configuration Register */
-#define MDMA0_S0_X_COUNT                0xFFC00E50      /* MemDMA0 Stream 0 Source X Count Register */
-#define MDMA0_S0_X_MODIFY               0xFFC00E54      /* MemDMA0 Stream 0 Source X Modify Register */
-#define MDMA0_S0_Y_COUNT                0xFFC00E58      /* MemDMA0 Stream 0 Source Y Count Register */
-#define MDMA0_S0_Y_MODIFY               0xFFC00E5C      /* MemDMA0 Stream 0 Source Y Modify Register */
-#define MDMA0_S0_CURR_DESC_PTR  0xFFC00E60      /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA0_S0_CURR_ADDR              0xFFC00E64      /* MemDMA0 Stream 0 Source Current Address Register */
-#define MDMA0_S0_IRQ_STATUS             0xFFC00E68      /* MemDMA0 Stream 0 Source Interrupt/Status Register */
-#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C      /* MemDMA0 Stream 0 Source Peripheral Map Register */
-#define MDMA0_S0_CURR_X_COUNT   0xFFC00E70      /* MemDMA0 Stream 0 Source Current X Count Register */
-#define MDMA0_S0_CURR_Y_COUNT   0xFFC00E78      /* MemDMA0 Stream 0 Source Current Y Count Register */
-
-#define MDMA0_D1_NEXT_DESC_PTR  0xFFC00E80      /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA0_D1_START_ADDR             0xFFC00E84      /* MemDMA0 Stream 1 Destination Start Address Register */
-#define MDMA0_D1_CONFIG                 0xFFC00E88      /* MemDMA0 Stream 1 Destination Configuration Register */
-#define MDMA0_D1_X_COUNT                0xFFC00E90      /* MemDMA0 Stream 1 Destination X Count Register */
-#define MDMA0_D1_X_MODIFY               0xFFC00E94      /* MemDMA0 Stream 1 Destination X Modify Register */
-#define MDMA0_D1_Y_COUNT                0xFFC00E98      /* MemDMA0 Stream 1 Destination Y Count Register */
-#define MDMA0_D1_Y_MODIFY               0xFFC00E9C      /* MemDMA0 Stream 1 Destination Y Modify Register */
-#define MDMA0_D1_CURR_DESC_PTR  0xFFC00EA0      /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA0_D1_CURR_ADDR              0xFFC00EA4      /* MemDMA0 Stream 1 Destination Current Address Register */
-#define MDMA0_D1_IRQ_STATUS             0xFFC00EA8      /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
-#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC      /* MemDMA0 Stream 1 Destination Peripheral Map Register */
-#define MDMA0_D1_CURR_X_COUNT   0xFFC00EB0      /* MemDMA0 Stream 1 Destination Current X Count Register */
-#define MDMA0_D1_CURR_Y_COUNT   0xFFC00EB8      /* MemDMA0 Stream 1 Destination Current Y Count Register */
-
-#define MDMA0_S1_NEXT_DESC_PTR  0xFFC00EC0      /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA0_S1_START_ADDR             0xFFC00EC4      /* MemDMA0 Stream 1 Source Start Address Register */
-#define MDMA0_S1_CONFIG                 0xFFC00EC8      /* MemDMA0 Stream 1 Source Configuration Register */
-#define MDMA0_S1_X_COUNT                0xFFC00ED0      /* MemDMA0 Stream 1 Source X Count Register */
-#define MDMA0_S1_X_MODIFY               0xFFC00ED4      /* MemDMA0 Stream 1 Source X Modify Register */
-#define MDMA0_S1_Y_COUNT                0xFFC00ED8      /* MemDMA0 Stream 1 Source Y Count Register */
-#define MDMA0_S1_Y_MODIFY               0xFFC00EDC      /* MemDMA0 Stream 1 Source Y Modify Register */
-#define MDMA0_S1_CURR_DESC_PTR  0xFFC00EE0      /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA0_S1_CURR_ADDR              0xFFC00EE4      /* MemDMA0 Stream 1 Source Current Address Register */
-#define MDMA0_S1_IRQ_STATUS             0xFFC00EE8      /* MemDMA0 Stream 1 Source Interrupt/Status Register */
-#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC      /* MemDMA0 Stream 1 Source Peripheral Map Register */
-#define MDMA0_S1_CURR_X_COUNT   0xFFC00EF0      /* MemDMA0 Stream 1 Source Current X Count Register */
-#define MDMA0_S1_CURR_Y_COUNT   0xFFC00EF8      /* MemDMA0 Stream 1 Source Current Y Count Register */
-
-#define MDMA_D0_NEXT_DESC_PTR MDMA0_D0_NEXT_DESC_PTR
-#define MDMA_D0_START_ADDR MDMA0_D0_START_ADDR
-#define MDMA_D0_CONFIG MDMA0_D0_CONFIG
-#define MDMA_D0_X_COUNT MDMA0_D0_X_COUNT
-#define MDMA_D0_X_MODIFY MDMA0_D0_X_MODIFY
-#define MDMA_D0_Y_COUNT MDMA0_D0_Y_COUNT
-#define MDMA_D0_Y_MODIFY MDMA0_D0_Y_MODIFY
-#define MDMA_D0_CURR_DESC_PTR MDMA0_D0_CURR_DESC_PTR
-#define MDMA_D0_CURR_ADDR MDMA0_D0_CURR_ADDR
-#define MDMA_D0_IRQ_STATUS MDMA0_D0_IRQ_STATUS
-#define MDMA_D0_PERIPHERAL_MAP MDMA0_D0_PERIPHERAL_MAP
-#define MDMA_D0_CURR_X_COUNT MDMA0_D0_CURR_X_COUNT
-#define MDMA_D0_CURR_Y_COUNT MDMA0_D0_CURR_Y_COUNT
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA0_S0_NEXT_DESC_PTR
-#define MDMA_S0_START_ADDR MDMA0_S0_START_ADDR
-#define MDMA_S0_CONFIG MDMA0_S0_CONFIG
-#define MDMA_S0_X_COUNT MDMA0_S0_X_COUNT
-#define MDMA_S0_X_MODIFY MDMA0_S0_X_MODIFY
-#define MDMA_S0_Y_COUNT MDMA0_S0_Y_COUNT
-#define MDMA_S0_Y_MODIFY MDMA0_S0_Y_MODIFY
-#define MDMA_S0_CURR_DESC_PTR MDMA0_S0_CURR_DESC_PTR
-#define MDMA_S0_CURR_ADDR MDMA0_S0_CURR_ADDR
-#define MDMA_S0_IRQ_STATUS MDMA0_S0_IRQ_STATUS
-#define MDMA_S0_PERIPHERAL_MAP MDMA0_S0_PERIPHERAL_MAP
-#define MDMA_S0_CURR_X_COUNT MDMA0_S0_CURR_X_COUNT
-#define MDMA_S0_CURR_Y_COUNT MDMA0_S0_CURR_Y_COUNT
-
-#define MDMA_D1_NEXT_DESC_PTR MDMA0_D1_NEXT_DESC_PTR
-#define MDMA_D1_START_ADDR MDMA0_D1_START_ADDR
-#define MDMA_D1_CONFIG MDMA0_D1_CONFIG
-#define MDMA_D1_X_COUNT MDMA0_D1_X_COUNT
-#define MDMA_D1_X_MODIFY MDMA0_D1_X_MODIFY
-#define MDMA_D1_Y_COUNT MDMA0_D1_Y_COUNT
-#define MDMA_D1_Y_MODIFY MDMA0_D1_Y_MODIFY
-#define MDMA_D1_CURR_DESC_PTR MDMA0_D1_CURR_DESC_PTR
-#define MDMA_D1_CURR_ADDR MDMA0_D1_CURR_ADDR
-#define MDMA_D1_IRQ_STATUS MDMA0_D1_IRQ_STATUS
-#define MDMA_D1_PERIPHERAL_MAP MDMA0_D1_PERIPHERAL_MAP
-#define MDMA_D1_CURR_X_COUNT MDMA0_D1_CURR_X_COUNT
-#define MDMA_D1_CURR_Y_COUNT MDMA0_D1_CURR_Y_COUNT
-
-#define MDMA_S1_NEXT_DESC_PTR MDMA0_S1_NEXT_DESC_PTR
-#define MDMA_S1_START_ADDR MDMA0_S1_START_ADDR
-#define MDMA_S1_CONFIG MDMA0_S1_CONFIG
-#define MDMA_S1_X_COUNT MDMA0_S1_X_COUNT
-#define MDMA_S1_X_MODIFY MDMA0_S1_X_MODIFY
-#define MDMA_S1_Y_COUNT MDMA0_S1_Y_COUNT
-#define MDMA_S1_Y_MODIFY MDMA0_S1_Y_MODIFY
-#define MDMA_S1_CURR_DESC_PTR MDMA0_S1_CURR_DESC_PTR
-#define MDMA_S1_CURR_ADDR MDMA0_S1_CURR_ADDR
-#define MDMA_S1_IRQ_STATUS MDMA0_S1_IRQ_STATUS
-#define MDMA_S1_PERIPHERAL_MAP MDMA0_S1_PERIPHERAL_MAP
-#define MDMA_S1_CURR_X_COUNT MDMA0_S1_CURR_X_COUNT
-#define MDMA_S1_CURR_Y_COUNT MDMA0_S1_CURR_Y_COUNT
-
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
-
-
-/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF)                        */
-#define TWI0_CLKDIV                     0xFFC01400      /* Serial Clock Divider Register */
-#define TWI0_CONTROL            0xFFC01404      /* TWI0 Master Internal Time Reference Register */
-#define TWI0_SLAVE_CTL          0xFFC01408      /* Slave Mode Control Register */
-#define TWI0_SLAVE_STAT         0xFFC0140C      /* Slave Mode Status Register */
-#define TWI0_SLAVE_ADDR         0xFFC01410      /* Slave Mode Address Register */
-#define TWI0_MASTER_CTL 0xFFC01414      /* Master Mode Control Register */
-#define TWI0_MASTER_STAT        0xFFC01418      /* Master Mode Status Register */
-#define TWI0_MASTER_ADDR        0xFFC0141C      /* Master Mode Address Register */
-#define TWI0_INT_STAT           0xFFC01420      /* TWI0 Master Interrupt Register */
-#define TWI0_INT_MASK           0xFFC01424      /* TWI0 Master Interrupt Mask Register */
-#define TWI0_FIFO_CTL           0xFFC01428      /* FIFO Control Register */
-#define TWI0_FIFO_STAT          0xFFC0142C      /* FIFO Status Register */
-#define TWI0_XMT_DATA8          0xFFC01480      /* FIFO Transmit Data Single Byte Register */
-#define TWI0_XMT_DATA16         0xFFC01484      /* FIFO Transmit Data Double Byte Register */
-#define TWI0_RCV_DATA8          0xFFC01488      /* FIFO Receive Data Single Byte Register */
-#define TWI0_RCV_DATA16         0xFFC0148C      /* FIFO Receive Data Double Byte Register */
-
-#define TWI0_REGBASE            TWI0_CLKDIV
-
-/* the following are for backwards compatibility */
-#define TWI0_PRESCALE    TWI0_CONTROL
-#define TWI0_INT_SRC     TWI0_INT_STAT
-#define TWI0_INT_ENABLE  TWI0_INT_MASK
-
-
-/* General-Purpose Ports  (0xFFC01500 - 0xFFC015FF)      */
-
-/* GPIO Port C Register Names */
-#define PORTCIO_FER                     0xFFC01500      /* GPIO Pin Port C Configuration Register */
-#define PORTCIO                         0xFFC01510      /* GPIO Pin Port C Data Register */
-#define PORTCIO_CLEAR                   0xFFC01520      /* Clear GPIO Pin Port C Register */
-#define PORTCIO_SET                     0xFFC01530      /* Set GPIO Pin Port C Register */
-#define PORTCIO_TOGGLE                  0xFFC01540      /* Toggle GPIO Pin Port C Register */
-#define PORTCIO_DIR                     0xFFC01550      /* GPIO Pin Port C Direction Register */
-#define PORTCIO_INEN                    0xFFC01560      /* GPIO Pin Port C Input Enable Register */
-
-/* GPIO Port D Register Names */
-#define PORTDIO_FER                     0xFFC01504      /* GPIO Pin Port D Configuration Register */
-#define PORTDIO                         0xFFC01514      /* GPIO Pin Port D Data Register */
-#define PORTDIO_CLEAR                   0xFFC01524      /* Clear GPIO Pin Port D Register */
-#define PORTDIO_SET                     0xFFC01534      /* Set GPIO Pin Port D Register */
-#define PORTDIO_TOGGLE                  0xFFC01544      /* Toggle GPIO Pin Port D Register */
-#define PORTDIO_DIR                     0xFFC01554      /* GPIO Pin Port D Direction Register */
-#define PORTDIO_INEN                    0xFFC01564      /* GPIO Pin Port D Input Enable Register */
-
-/* GPIO Port E Register Names */
-#define PORTEIO_FER                     0xFFC01508      /* GPIO Pin Port E Configuration Register */
-#define PORTEIO                         0xFFC01518      /* GPIO Pin Port E Data Register */
-#define PORTEIO_CLEAR                   0xFFC01528      /* Clear GPIO Pin Port E Register */
-#define PORTEIO_SET                     0xFFC01538      /* Set GPIO Pin Port E Register */
-#define PORTEIO_TOGGLE                  0xFFC01548      /* Toggle GPIO Pin Port E Register */
-#define PORTEIO_DIR                     0xFFC01558      /* GPIO Pin Port E Direction Register */
-#define PORTEIO_INEN                    0xFFC01568      /* GPIO Pin Port E Input Enable Register */
-
-/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
-
-#define DMAC1_TC_PER                    0xFFC01B0C      /* DMA Controller 1 Traffic Control Periods Register */
-#define DMAC1_TC_CNT                    0xFFC01B10      /* DMA Controller 1 Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA1_TCPER                      DMAC1_TC_PER
-#define DMA1_TCCNT                      DMAC1_TC_CNT
-
-
-/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF)                                                    */
-#define DMA8_NEXT_DESC_PTR              0xFFC01C00      /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                 0xFFC01C04      /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                             0xFFC01C08      /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                    0xFFC01C10      /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                   0xFFC01C14      /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                    0xFFC01C18      /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                   0xFFC01C1C      /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR              0xFFC01C20      /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                  0xFFC01C24      /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                 0xFFC01C28      /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP             0xFFC01C2C      /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT               0xFFC01C30      /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT               0xFFC01C38      /* DMA Channel 8 Current Y Count Register */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC01C40      /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                 0xFFC01C44      /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                             0xFFC01C48      /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                    0xFFC01C50      /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                   0xFFC01C54      /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                    0xFFC01C58      /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                   0xFFC01C5C      /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR              0xFFC01C60      /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                  0xFFC01C64      /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                 0xFFC01C68      /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP             0xFFC01C6C      /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT               0xFFC01C70      /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT               0xFFC01C78      /* DMA Channel 9 Current Y Count Register */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC01C80      /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR                0xFFC01C84      /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                    0xFFC01C88      /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                   0xFFC01C90      /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                  0xFFC01C94      /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                   0xFFC01C98      /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                  0xFFC01C9C      /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR             0xFFC01CA0      /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                 0xFFC01CA4      /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS                0xFFC01CA8      /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP    0xFFC01CAC      /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT              0xFFC01CB0      /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT              0xFFC01CB8      /* DMA Channel 10 Current Y Count Register */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC01CC0      /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR                0xFFC01CC4      /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                    0xFFC01CC8      /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                   0xFFC01CD0      /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                  0xFFC01CD4      /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                   0xFFC01CD8      /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                  0xFFC01CDC      /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR             0xFFC01CE0      /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                 0xFFC01CE4      /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS                0xFFC01CE8      /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP    0xFFC01CEC      /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT              0xFFC01CF0      /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT              0xFFC01CF8      /* DMA Channel 11 Current Y Count Register */
-
-#define DMA12_NEXT_DESC_PTR             0xFFC01D00      /* DMA Channel 12 Next Descriptor Pointer Register */
-#define DMA12_START_ADDR                0xFFC01D04      /* DMA Channel 12 Start Address Register */
-#define DMA12_CONFIG                    0xFFC01D08      /* DMA Channel 12 Configuration Register */
-#define DMA12_X_COUNT                   0xFFC01D10      /* DMA Channel 12 X Count Register */
-#define DMA12_X_MODIFY                  0xFFC01D14      /* DMA Channel 12 X Modify Register */
-#define DMA12_Y_COUNT                   0xFFC01D18      /* DMA Channel 12 Y Count Register */
-#define DMA12_Y_MODIFY                  0xFFC01D1C      /* DMA Channel 12 Y Modify Register */
-#define DMA12_CURR_DESC_PTR             0xFFC01D20      /* DMA Channel 12 Current Descriptor Pointer Register */
-#define DMA12_CURR_ADDR                 0xFFC01D24      /* DMA Channel 12 Current Address Register */
-#define DMA12_IRQ_STATUS                0xFFC01D28      /* DMA Channel 12 Interrupt/Status Register */
-#define DMA12_PERIPHERAL_MAP    0xFFC01D2C      /* DMA Channel 12 Peripheral Map Register */
-#define DMA12_CURR_X_COUNT              0xFFC01D30      /* DMA Channel 12 Current X Count Register */
-#define DMA12_CURR_Y_COUNT              0xFFC01D38      /* DMA Channel 12 Current Y Count Register */
-
-#define DMA13_NEXT_DESC_PTR             0xFFC01D40      /* DMA Channel 13 Next Descriptor Pointer Register */
-#define DMA13_START_ADDR                0xFFC01D44      /* DMA Channel 13 Start Address Register */
-#define DMA13_CONFIG                    0xFFC01D48      /* DMA Channel 13 Configuration Register */
-#define DMA13_X_COUNT                   0xFFC01D50      /* DMA Channel 13 X Count Register */
-#define DMA13_X_MODIFY                  0xFFC01D54      /* DMA Channel 13 X Modify Register */
-#define DMA13_Y_COUNT                   0xFFC01D58      /* DMA Channel 13 Y Count Register */
-#define DMA13_Y_MODIFY                  0xFFC01D5C      /* DMA Channel 13 Y Modify Register */
-#define DMA13_CURR_DESC_PTR             0xFFC01D60      /* DMA Channel 13 Current Descriptor Pointer Register */
-#define DMA13_CURR_ADDR                 0xFFC01D64      /* DMA Channel 13 Current Address Register */
-#define DMA13_IRQ_STATUS                0xFFC01D68      /* DMA Channel 13 Interrupt/Status Register */
-#define DMA13_PERIPHERAL_MAP    0xFFC01D6C      /* DMA Channel 13 Peripheral Map Register */
-#define DMA13_CURR_X_COUNT              0xFFC01D70      /* DMA Channel 13 Current X Count Register */
-#define DMA13_CURR_Y_COUNT              0xFFC01D78      /* DMA Channel 13 Current Y Count Register */
-
-#define DMA14_NEXT_DESC_PTR             0xFFC01D80      /* DMA Channel 14 Next Descriptor Pointer Register */
-#define DMA14_START_ADDR                0xFFC01D84      /* DMA Channel 14 Start Address Register */
-#define DMA14_CONFIG                    0xFFC01D88      /* DMA Channel 14 Configuration Register */
-#define DMA14_X_COUNT                   0xFFC01D90      /* DMA Channel 14 X Count Register */
-#define DMA14_X_MODIFY                  0xFFC01D94      /* DMA Channel 14 X Modify Register */
-#define DMA14_Y_COUNT                   0xFFC01D98      /* DMA Channel 14 Y Count Register */
-#define DMA14_Y_MODIFY                  0xFFC01D9C      /* DMA Channel 14 Y Modify Register */
-#define DMA14_CURR_DESC_PTR             0xFFC01DA0      /* DMA Channel 14 Current Descriptor Pointer Register */
-#define DMA14_CURR_ADDR                 0xFFC01DA4      /* DMA Channel 14 Current Address Register */
-#define DMA14_IRQ_STATUS                0xFFC01DA8      /* DMA Channel 14 Interrupt/Status Register */
-#define DMA14_PERIPHERAL_MAP    0xFFC01DAC      /* DMA Channel 14 Peripheral Map Register */
-#define DMA14_CURR_X_COUNT              0xFFC01DB0      /* DMA Channel 14 Current X Count Register */
-#define DMA14_CURR_Y_COUNT              0xFFC01DB8      /* DMA Channel 14 Current Y Count Register */
-
-#define DMA15_NEXT_DESC_PTR             0xFFC01DC0      /* DMA Channel 15 Next Descriptor Pointer Register */
-#define DMA15_START_ADDR                0xFFC01DC4      /* DMA Channel 15 Start Address Register */
-#define DMA15_CONFIG                    0xFFC01DC8      /* DMA Channel 15 Configuration Register */
-#define DMA15_X_COUNT                   0xFFC01DD0      /* DMA Channel 15 X Count Register */
-#define DMA15_X_MODIFY                  0xFFC01DD4      /* DMA Channel 15 X Modify Register */
-#define DMA15_Y_COUNT                   0xFFC01DD8      /* DMA Channel 15 Y Count Register */
-#define DMA15_Y_MODIFY                  0xFFC01DDC      /* DMA Channel 15 Y Modify Register */
-#define DMA15_CURR_DESC_PTR             0xFFC01DE0      /* DMA Channel 15 Current Descriptor Pointer Register */
-#define DMA15_CURR_ADDR                 0xFFC01DE4      /* DMA Channel 15 Current Address Register */
-#define DMA15_IRQ_STATUS                0xFFC01DE8      /* DMA Channel 15 Interrupt/Status Register */
-#define DMA15_PERIPHERAL_MAP    0xFFC01DEC      /* DMA Channel 15 Peripheral Map Register */
-#define DMA15_CURR_X_COUNT              0xFFC01DF0      /* DMA Channel 15 Current X Count Register */
-#define DMA15_CURR_Y_COUNT              0xFFC01DF8      /* DMA Channel 15 Current Y Count Register */
-
-#define DMA16_NEXT_DESC_PTR             0xFFC01E00      /* DMA Channel 16 Next Descriptor Pointer Register */
-#define DMA16_START_ADDR                0xFFC01E04      /* DMA Channel 16 Start Address Register */
-#define DMA16_CONFIG                    0xFFC01E08      /* DMA Channel 16 Configuration Register */
-#define DMA16_X_COUNT                   0xFFC01E10      /* DMA Channel 16 X Count Register */
-#define DMA16_X_MODIFY                  0xFFC01E14      /* DMA Channel 16 X Modify Register */
-#define DMA16_Y_COUNT                   0xFFC01E18      /* DMA Channel 16 Y Count Register */
-#define DMA16_Y_MODIFY                  0xFFC01E1C      /* DMA Channel 16 Y Modify Register */
-#define DMA16_CURR_DESC_PTR             0xFFC01E20      /* DMA Channel 16 Current Descriptor Pointer Register */
-#define DMA16_CURR_ADDR                 0xFFC01E24      /* DMA Channel 16 Current Address Register */
-#define DMA16_IRQ_STATUS                0xFFC01E28      /* DMA Channel 16 Interrupt/Status Register */
-#define DMA16_PERIPHERAL_MAP    0xFFC01E2C      /* DMA Channel 16 Peripheral Map Register */
-#define DMA16_CURR_X_COUNT              0xFFC01E30      /* DMA Channel 16 Current X Count Register */
-#define DMA16_CURR_Y_COUNT              0xFFC01E38      /* DMA Channel 16 Current Y Count Register */
-
-#define DMA17_NEXT_DESC_PTR             0xFFC01E40      /* DMA Channel 17 Next Descriptor Pointer Register */
-#define DMA17_START_ADDR                0xFFC01E44      /* DMA Channel 17 Start Address Register */
-#define DMA17_CONFIG                    0xFFC01E48      /* DMA Channel 17 Configuration Register */
-#define DMA17_X_COUNT                   0xFFC01E50      /* DMA Channel 17 X Count Register */
-#define DMA17_X_MODIFY                  0xFFC01E54      /* DMA Channel 17 X Modify Register */
-#define DMA17_Y_COUNT                   0xFFC01E58      /* DMA Channel 17 Y Count Register */
-#define DMA17_Y_MODIFY                  0xFFC01E5C      /* DMA Channel 17 Y Modify Register */
-#define DMA17_CURR_DESC_PTR             0xFFC01E60      /* DMA Channel 17 Current Descriptor Pointer Register */
-#define DMA17_CURR_ADDR                 0xFFC01E64      /* DMA Channel 17 Current Address Register */
-#define DMA17_IRQ_STATUS                0xFFC01E68      /* DMA Channel 17 Interrupt/Status Register */
-#define DMA17_PERIPHERAL_MAP    0xFFC01E6C      /* DMA Channel 17 Peripheral Map Register */
-#define DMA17_CURR_X_COUNT              0xFFC01E70      /* DMA Channel 17 Current X Count Register */
-#define DMA17_CURR_Y_COUNT              0xFFC01E78      /* DMA Channel 17 Current Y Count Register */
-
-#define DMA18_NEXT_DESC_PTR             0xFFC01E80      /* DMA Channel 18 Next Descriptor Pointer Register */
-#define DMA18_START_ADDR                0xFFC01E84      /* DMA Channel 18 Start Address Register */
-#define DMA18_CONFIG                    0xFFC01E88      /* DMA Channel 18 Configuration Register */
-#define DMA18_X_COUNT                   0xFFC01E90      /* DMA Channel 18 X Count Register */
-#define DMA18_X_MODIFY                  0xFFC01E94      /* DMA Channel 18 X Modify Register */
-#define DMA18_Y_COUNT                   0xFFC01E98      /* DMA Channel 18 Y Count Register */
-#define DMA18_Y_MODIFY                  0xFFC01E9C      /* DMA Channel 18 Y Modify Register */
-#define DMA18_CURR_DESC_PTR             0xFFC01EA0      /* DMA Channel 18 Current Descriptor Pointer Register */
-#define DMA18_CURR_ADDR                 0xFFC01EA4      /* DMA Channel 18 Current Address Register */
-#define DMA18_IRQ_STATUS                0xFFC01EA8      /* DMA Channel 18 Interrupt/Status Register */
-#define DMA18_PERIPHERAL_MAP    0xFFC01EAC      /* DMA Channel 18 Peripheral Map Register */
-#define DMA18_CURR_X_COUNT              0xFFC01EB0      /* DMA Channel 18 Current X Count Register */
-#define DMA18_CURR_Y_COUNT              0xFFC01EB8      /* DMA Channel 18 Current Y Count Register */
-
-#define DMA19_NEXT_DESC_PTR             0xFFC01EC0      /* DMA Channel 19 Next Descriptor Pointer Register */
-#define DMA19_START_ADDR                0xFFC01EC4      /* DMA Channel 19 Start Address Register */
-#define DMA19_CONFIG                    0xFFC01EC8      /* DMA Channel 19 Configuration Register */
-#define DMA19_X_COUNT                   0xFFC01ED0      /* DMA Channel 19 X Count Register */
-#define DMA19_X_MODIFY                  0xFFC01ED4      /* DMA Channel 19 X Modify Register */
-#define DMA19_Y_COUNT                   0xFFC01ED8      /* DMA Channel 19 Y Count Register */
-#define DMA19_Y_MODIFY                  0xFFC01EDC      /* DMA Channel 19 Y Modify Register */
-#define DMA19_CURR_DESC_PTR             0xFFC01EE0      /* DMA Channel 19 Current Descriptor Pointer Register */
-#define DMA19_CURR_ADDR                 0xFFC01EE4      /* DMA Channel 19 Current Address Register */
-#define DMA19_IRQ_STATUS                0xFFC01EE8      /* DMA Channel 19 Interrupt/Status Register */
-#define DMA19_PERIPHERAL_MAP    0xFFC01EEC      /* DMA Channel 19 Peripheral Map Register */
-#define DMA19_CURR_X_COUNT              0xFFC01EF0      /* DMA Channel 19 Current X Count Register */
-#define DMA19_CURR_Y_COUNT              0xFFC01EF8      /* DMA Channel 19 Current Y Count Register */
-
-#define MDMA1_D0_NEXT_DESC_PTR  0xFFC01F00      /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA1_D0_START_ADDR             0xFFC01F04      /* MemDMA1 Stream 0 Destination Start Address Register */
-#define MDMA1_D0_CONFIG                 0xFFC01F08      /* MemDMA1 Stream 0 Destination Configuration Register */
-#define MDMA1_D0_X_COUNT                0xFFC01F10      /* MemDMA1 Stream 0 Destination X Count Register */
-#define MDMA1_D0_X_MODIFY               0xFFC01F14      /* MemDMA1 Stream 0 Destination X Modify Register */
-#define MDMA1_D0_Y_COUNT                0xFFC01F18      /* MemDMA1 Stream 0 Destination Y Count Register */
-#define MDMA1_D0_Y_MODIFY               0xFFC01F1C      /* MemDMA1 Stream 0 Destination Y Modify Register */
-#define MDMA1_D0_CURR_DESC_PTR  0xFFC01F20      /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA1_D0_CURR_ADDR              0xFFC01F24      /* MemDMA1 Stream 0 Destination Current Address Register */
-#define MDMA1_D0_IRQ_STATUS             0xFFC01F28      /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /* MemDMA1 Stream 0 Destination Peripheral Map Register */
-#define MDMA1_D0_CURR_X_COUNT   0xFFC01F30      /* MemDMA1 Stream 0 Destination Current X Count Register */
-#define MDMA1_D0_CURR_Y_COUNT   0xFFC01F38      /* MemDMA1 Stream 0 Destination Current Y Count Register */
-
-#define MDMA1_S0_NEXT_DESC_PTR  0xFFC01F40      /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA1_S0_START_ADDR             0xFFC01F44      /* MemDMA1 Stream 0 Source Start Address Register */
-#define MDMA1_S0_CONFIG                 0xFFC01F48      /* MemDMA1 Stream 0 Source Configuration Register */
-#define MDMA1_S0_X_COUNT                0xFFC01F50      /* MemDMA1 Stream 0 Source X Count Register */
-#define MDMA1_S0_X_MODIFY               0xFFC01F54      /* MemDMA1 Stream 0 Source X Modify Register */
-#define MDMA1_S0_Y_COUNT                0xFFC01F58      /* MemDMA1 Stream 0 Source Y Count Register */
-#define MDMA1_S0_Y_MODIFY               0xFFC01F5C      /* MemDMA1 Stream 0 Source Y Modify Register */
-#define MDMA1_S0_CURR_DESC_PTR  0xFFC01F60      /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA1_S0_CURR_ADDR              0xFFC01F64      /* MemDMA1 Stream 0 Source Current Address Register */
-#define MDMA1_S0_IRQ_STATUS             0xFFC01F68      /* MemDMA1 Stream 0 Source Interrupt/Status Register */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /* MemDMA1 Stream 0 Source Peripheral Map Register */
-#define MDMA1_S0_CURR_X_COUNT   0xFFC01F70      /* MemDMA1 Stream 0 Source Current X Count Register */
-#define MDMA1_S0_CURR_Y_COUNT   0xFFC01F78      /* MemDMA1 Stream 0 Source Current Y Count Register */
-
-#define MDMA1_D1_NEXT_DESC_PTR  0xFFC01F80      /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA1_D1_START_ADDR             0xFFC01F84      /* MemDMA1 Stream 1 Destination Start Address Register */
-#define MDMA1_D1_CONFIG                 0xFFC01F88      /* MemDMA1 Stream 1 Destination Configuration Register */
-#define MDMA1_D1_X_COUNT                0xFFC01F90      /* MemDMA1 Stream 1 Destination X Count Register */
-#define MDMA1_D1_X_MODIFY               0xFFC01F94      /* MemDMA1 Stream 1 Destination X Modify Register */
-#define MDMA1_D1_Y_COUNT                0xFFC01F98      /* MemDMA1 Stream 1 Destination Y Count Register */
-#define MDMA1_D1_Y_MODIFY               0xFFC01F9C      /* MemDMA1 Stream 1 Destination Y Modify Register */
-#define MDMA1_D1_CURR_DESC_PTR  0xFFC01FA0      /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA1_D1_CURR_ADDR              0xFFC01FA4      /* MemDMA1 Stream 1 Destination Current Address Register */
-#define MDMA1_D1_IRQ_STATUS             0xFFC01FA8      /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /* MemDMA1 Stream 1 Destination Peripheral Map Register */
-#define MDMA1_D1_CURR_X_COUNT   0xFFC01FB0      /* MemDMA1 Stream 1 Destination Current X Count Register */
-#define MDMA1_D1_CURR_Y_COUNT   0xFFC01FB8      /* MemDMA1 Stream 1 Destination Current Y Count Register */
-
-#define MDMA1_S1_NEXT_DESC_PTR  0xFFC01FC0      /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA1_S1_START_ADDR             0xFFC01FC4      /* MemDMA1 Stream 1 Source Start Address Register */
-#define MDMA1_S1_CONFIG                 0xFFC01FC8      /* MemDMA1 Stream 1 Source Configuration Register */
-#define MDMA1_S1_X_COUNT                0xFFC01FD0      /* MemDMA1 Stream 1 Source X Count Register */
-#define MDMA1_S1_X_MODIFY               0xFFC01FD4      /* MemDMA1 Stream 1 Source X Modify Register */
-#define MDMA1_S1_Y_COUNT                0xFFC01FD8      /* MemDMA1 Stream 1 Source Y Count Register */
-#define MDMA1_S1_Y_MODIFY               0xFFC01FDC      /* MemDMA1 Stream 1 Source Y Modify Register */
-#define MDMA1_S1_CURR_DESC_PTR  0xFFC01FE0      /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA1_S1_CURR_ADDR              0xFFC01FE4      /* MemDMA1 Stream 1 Source Current Address Register */
-#define MDMA1_S1_IRQ_STATUS             0xFFC01FE8      /* MemDMA1 Stream 1 Source Interrupt/Status Register */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /* MemDMA1 Stream 1 Source Peripheral Map Register */
-#define MDMA1_S1_CURR_X_COUNT   0xFFC01FF0      /* MemDMA1 Stream 1 Source Current X Count Register */
-#define MDMA1_S1_CURR_Y_COUNT   0xFFC01FF8      /* MemDMA1 Stream 1 Source Current Y Count Register */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)        */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte) */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte) */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register */
-
-
-/* UART2 Controller             (0xFFC02100 - 0xFFC021FF)        */
-#define UART2_THR                       0xFFC02100      /* Transmit Holding register */
-#define UART2_RBR                       0xFFC02100      /* Receive Buffer register */
-#define UART2_DLL                       0xFFC02100      /* Divisor Latch (Low-Byte) */
-#define UART2_IER                       0xFFC02104      /* Interrupt Enable Register */
-#define UART2_DLH                       0xFFC02104      /* Divisor Latch (High-Byte) */
-#define UART2_IIR                       0xFFC02108      /* Interrupt Identification Register */
-#define UART2_LCR                       0xFFC0210C      /* Line Control Register */
-#define UART2_MCR                       0xFFC02110      /* Modem Control Register */
-#define UART2_LSR                       0xFFC02114      /* Line Status Register */
-#define UART2_SCR                       0xFFC0211C      /* SCR Scratch Register */
-#define UART2_GCTL                      0xFFC02124      /* Global Control Register */
-
-
-/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF)                        */
-#define TWI1_CLKDIV                     0xFFC02200      /* Serial Clock Divider Register */
-#define TWI1_CONTROL            0xFFC02204      /* TWI1 Master Internal Time Reference Register */
-#define TWI1_SLAVE_CTL          0xFFC02208      /* Slave Mode Control Register */
-#define TWI1_SLAVE_STAT         0xFFC0220C      /* Slave Mode Status Register */
-#define TWI1_SLAVE_ADDR         0xFFC02210      /* Slave Mode Address Register */
-#define TWI1_MASTER_CTL 0xFFC02214      /* Master Mode Control Register */
-#define TWI1_MASTER_STAT        0xFFC02218      /* Master Mode Status Register */
-#define TWI1_MASTER_ADDR        0xFFC0221C      /* Master Mode Address Register */
-#define TWI1_INT_STAT           0xFFC02220      /* TWI1 Master Interrupt Register */
-#define TWI1_INT_MASK           0xFFC02224      /* TWI1 Master Interrupt Mask Register */
-#define TWI1_FIFO_CTL           0xFFC02228      /* FIFO Control Register */
-#define TWI1_FIFO_STAT          0xFFC0222C      /* FIFO Status Register */
-#define TWI1_XMT_DATA8          0xFFC02280      /* FIFO Transmit Data Single Byte Register */
-#define TWI1_XMT_DATA16         0xFFC02284      /* FIFO Transmit Data Double Byte Register */
-#define TWI1_RCV_DATA8          0xFFC02288      /* FIFO Receive Data Single Byte Register */
-#define TWI1_RCV_DATA16         0xFFC0228C      /* FIFO Receive Data Double Byte Register */
-#define TWI1_REGBASE            TWI1_CLKDIV
-
-
-/* the following are for backwards compatibility */
-#define TWI1_PRESCALE     TWI1_CONTROL
-#define TWI1_INT_SRC      TWI1_INT_STAT
-#define TWI1_INT_ENABLE   TWI1_INT_MASK
-
-
-/* SPI1 Controller              (0xFFC02300 - 0xFFC023FF)        */
-#define SPI1_CTL                        0xFFC02300  /* SPI1 Control Register */
-#define SPI1_FLG                        0xFFC02304  /* SPI1 Flag register */
-#define SPI1_STAT                       0xFFC02308  /* SPI1 Status register */
-#define SPI1_TDBR                       0xFFC0230C  /* SPI1 Transmit Data Buffer Register */
-#define SPI1_RDBR                       0xFFC02310  /* SPI1 Receive Data Buffer Register */
-#define SPI1_BAUD                       0xFFC02314  /* SPI1 Baud rate Register */
-#define SPI1_SHADOW                     0xFFC02318  /* SPI1_RDBR Shadow Register */
-#define SPI1_REGBASE                    SPI1_CTL
-
-/* SPI2 Controller              (0xFFC02400 - 0xFFC024FF)        */
-#define SPI2_CTL                        0xFFC02400  /* SPI2 Control Register */
-#define SPI2_FLG                        0xFFC02404  /* SPI2 Flag register */
-#define SPI2_STAT                       0xFFC02408  /* SPI2 Status register */
-#define SPI2_TDBR                       0xFFC0240C  /* SPI2 Transmit Data Buffer Register */
-#define SPI2_RDBR                       0xFFC02410  /* SPI2 Receive Data Buffer Register */
-#define SPI2_BAUD                       0xFFC02414  /* SPI2 Baud rate Register */
-#define SPI2_SHADOW                     0xFFC02418  /* SPI2_RDBR Shadow Register */
-#define SPI2_REGBASE                    SPI2_CTL
-
-/* SPORT2 Controller            (0xFFC02500 - 0xFFC025FF)                        */
-#define SPORT2_TCR1                     0xFFC02500      /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_TCR2                     0xFFC02504      /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_TCLKDIV          0xFFC02508      /* SPORT2 Transmit Clock Divider */
-#define SPORT2_TFSDIV           0xFFC0250C      /* SPORT2 Transmit Frame Sync Divider */
-#define SPORT2_TX                       0xFFC02510      /* SPORT2 TX Data Register */
-#define SPORT2_RX                       0xFFC02518      /* SPORT2 RX Data Register */
-#define SPORT2_RCR1                     0xFFC02520      /* SPORT2 Transmit Configuration 1 Register */
-#define SPORT2_RCR2                     0xFFC02524      /* SPORT2 Transmit Configuration 2 Register */
-#define SPORT2_RCLKDIV          0xFFC02528      /* SPORT2 Receive Clock Divider */
-#define SPORT2_RFSDIV           0xFFC0252C      /* SPORT2 Receive Frame Sync Divider */
-#define SPORT2_STAT                     0xFFC02530      /* SPORT2 Status Register */
-#define SPORT2_CHNL                     0xFFC02534      /* SPORT2 Current Channel Register */
-#define SPORT2_MCMC1            0xFFC02538      /* SPORT2 Multi-Channel Configuration Register 1 */
-#define SPORT2_MCMC2            0xFFC0253C      /* SPORT2 Multi-Channel Configuration Register 2 */
-#define SPORT2_MTCS0            0xFFC02540      /* SPORT2 Multi-Channel Transmit Select Register 0 */
-#define SPORT2_MTCS1            0xFFC02544      /* SPORT2 Multi-Channel Transmit Select Register 1 */
-#define SPORT2_MTCS2            0xFFC02548      /* SPORT2 Multi-Channel Transmit Select Register 2 */
-#define SPORT2_MTCS3            0xFFC0254C      /* SPORT2 Multi-Channel Transmit Select Register 3 */
-#define SPORT2_MRCS0            0xFFC02550      /* SPORT2 Multi-Channel Receive Select Register 0 */
-#define SPORT2_MRCS1            0xFFC02554      /* SPORT2 Multi-Channel Receive Select Register 1 */
-#define SPORT2_MRCS2            0xFFC02558      /* SPORT2 Multi-Channel Receive Select Register 2 */
-#define SPORT2_MRCS3            0xFFC0255C      /* SPORT2 Multi-Channel Receive Select Register 3 */
-
-
-/* SPORT3 Controller            (0xFFC02600 - 0xFFC026FF)                        */
-#define SPORT3_TCR1                     0xFFC02600      /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_TCR2                     0xFFC02604      /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_TCLKDIV          0xFFC02608      /* SPORT3 Transmit Clock Divider */
-#define SPORT3_TFSDIV           0xFFC0260C      /* SPORT3 Transmit Frame Sync Divider */
-#define SPORT3_TX                       0xFFC02610      /* SPORT3 TX Data Register */
-#define SPORT3_RX                       0xFFC02618      /* SPORT3 RX Data Register */
-#define SPORT3_RCR1                     0xFFC02620      /* SPORT3 Transmit Configuration 1 Register */
-#define SPORT3_RCR2                     0xFFC02624      /* SPORT3 Transmit Configuration 2 Register */
-#define SPORT3_RCLKDIV          0xFFC02628      /* SPORT3 Receive Clock Divider */
-#define SPORT3_RFSDIV           0xFFC0262C      /* SPORT3 Receive Frame Sync Divider */
-#define SPORT3_STAT                     0xFFC02630      /* SPORT3 Status Register */
-#define SPORT3_CHNL                     0xFFC02634      /* SPORT3 Current Channel Register */
-#define SPORT3_MCMC1            0xFFC02638      /* SPORT3 Multi-Channel Configuration Register 1 */
-#define SPORT3_MCMC2            0xFFC0263C      /* SPORT3 Multi-Channel Configuration Register 2 */
-#define SPORT3_MTCS0            0xFFC02640      /* SPORT3 Multi-Channel Transmit Select Register 0 */
-#define SPORT3_MTCS1            0xFFC02644      /* SPORT3 Multi-Channel Transmit Select Register 1 */
-#define SPORT3_MTCS2            0xFFC02648      /* SPORT3 Multi-Channel Transmit Select Register 2 */
-#define SPORT3_MTCS3            0xFFC0264C      /* SPORT3 Multi-Channel Transmit Select Register 3 */
-#define SPORT3_MRCS0            0xFFC02650      /* SPORT3 Multi-Channel Receive Select Register 0 */
-#define SPORT3_MRCS1            0xFFC02654      /* SPORT3 Multi-Channel Receive Select Register 1 */
-#define SPORT3_MRCS2            0xFFC02658      /* SPORT3 Multi-Channel Receive Select Register 2 */
-#define SPORT3_MRCS3            0xFFC0265C      /* SPORT3 Multi-Channel Receive Select Register 3 */
-
+#include "defBF538.h"
 
 /* Media Transceiver (MXVR)   (0xFFC02700 - 0xFFC028FF) */
 
@@ -995,1249 +149,4 @@
 #define MXVR_BLOCK_CNT        0xFFC028C0  /* MXVR Block Counter */
 #define MXVR_PLL_CTL_2        0xFFC028C4  /* MXVR Phase Lock Loop Control Register 2 */
 
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                */
-/* For Mailboxes 0-15                                                                                    */
-#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1  */
-#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1 */
-#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1 */
-#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1 */
-#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1 */
-#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1 */
-#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1 */
-#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1 */
-#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1 */
-#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1 */
-#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1 */
-#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1 */
-#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmission reg 1 */
-
-/* For Mailboxes 16-31                                                                                   */
-#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2  */
-#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2 */
-#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2 */
-#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2 */
-#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2 */
-#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2 */
-#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2 */
-#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2 */
-#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2 */
-#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2 */
-#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2 */
-#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2 */
-#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmission reg 2 */
-
-#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0 */
-#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1 */
-
-#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                */
-/* the following is for backwards compatibility */
-#define CAN_CNF          CAN_DEBUG
-
-#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register */
-#define CAN_CEC                         0xFFC02A90      /* Error Counter Register */
-#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register */
-#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register */
-#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register */
-#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register */
-#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register */
-#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature */
-#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level */
-#define CAN_ESR                         0xFFC02AB4      /* Error Status Register */
-#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter     */
-#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Reload/Capture Register */
-#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register */
-
-/* Mailbox Acceptance Masks                                      */
-#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask */
-#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask */
-#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask */
-#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask */
-#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask */
-#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask */
-#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask */
-#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask */
-#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask */
-#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask */
-#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask */
-#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask */
-#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask */
-#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask */
-#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask */
-#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask */
-#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask */
-#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask */
-#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask */
-#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask */
-#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask */
-#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask */
-#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask */
-#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask */
-#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask */
-#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask */
-#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask */
-#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask */
-#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask */
-#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask */
-#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask */
-#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask */
-
-#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask */
-#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask */
-#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask */
-#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask */
-#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask */
-#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask */
-#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask */
-#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask */
-#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask */
-#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask */
-#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask */
-#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask */
-#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask */
-#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask */
-#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask */
-#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask */
-#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask */
-#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask */
-#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask */
-#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask */
-#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask */
-#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask */
-#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask */
-#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask */
-#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask */
-#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask */
-#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask */
-#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask */
-#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask */
-#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask */
-#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask */
-#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask */
-
-/* CAN Acceptance Mask Macros */
-#define CAN_AM_L(x)                     (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)                     (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers                                                                     */
-#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register */
-#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register */
-#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register */
-#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register */
-#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register */
-#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register */
-#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register */
-#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register */
-
-#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register */
-#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register */
-#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register */
-#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register */
-#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register */
-#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register */
-#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register */
-#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register */
-
-#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register */
-#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register */
-#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register */
-#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register */
-#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register */
-#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register */
-#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register */
-#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register */
-
-#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register */
-#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register */
-#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register */
-#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register */
-#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register */
-#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register */
-#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register */
-#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register */
-
-#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register */
-#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register */
-#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register */
-#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register */
-#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register */
-#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register */
-#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register */
-#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register */
-
-#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register */
-#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register */
-#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register */
-#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register */
-#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register */
-#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register */
-#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register */
-#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register */
-
-#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register */
-#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register */
-#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register */
-#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register */
-#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register */
-#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register */
-#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register */
-#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register */
-
-#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register */
-#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register */
-#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register */
-#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register */
-#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register */
-#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register */
-#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register */
-#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register */
-
-#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register */
-#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register */
-#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register */
-#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register */
-#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register */
-#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register */
-#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register */
-#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register */
-
-#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register */
-#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register */
-#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register */
-#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register */
-#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register */
-#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register */
-#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register */
-#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register */
-
-#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register */
-#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register */
-#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register */
-#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register */
-#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register */
-#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register */
-#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register */
-#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register */
-
-#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register */
-#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register */
-#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register */
-#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register */
-#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register */
-#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register */
-#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register */
-#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register */
-
-#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register */
-#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register */
-#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register */
-#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register */
-#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register */
-#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register */
-#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register */
-#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register */
-
-#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register */
-#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register */
-#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register */
-#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register */
-#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register */
-#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register */
-#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register */
-#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register */
-
-#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register */
-#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register */
-#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register */
-#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register */
-#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register */
-#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register */
-#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register */
-#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register */
-
-#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register */
-#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register */
-#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register */
-#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register */
-#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register */
-#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register */
-#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register */
-#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register */
-
-#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register */
-#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register */
-#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register */
-#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register */
-#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register */
-#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register */
-#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register */
-#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register */
-
-#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register */
-#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register */
-#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register */
-#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register */
-#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register */
-#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register */
-#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register */
-#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register */
-
-#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register */
-#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register */
-#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register */
-#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register */
-#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register */
-#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register */
-#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register */
-#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register */
-
-#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register */
-#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register */
-#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register */
-#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register */
-#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register */
-#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register */
-#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register */
-#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register */
-
-#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register */
-#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register */
-#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register */
-#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register */
-#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register */
-#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register */
-#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register */
-#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register */
-
-#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register */
-#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register */
-#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register */
-#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register */
-#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register */
-#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register */
-#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register */
-#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register */
-
-#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register */
-#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register */
-#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register */
-#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register */
-#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register */
-#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register */
-#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register */
-#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register */
-
-#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register */
-#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register */
-#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register */
-#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register */
-#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register */
-#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register */
-#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register */
-#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register */
-
-#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register */
-#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register */
-#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register */
-#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register */
-#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register */
-#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register */
-#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register */
-#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register */
-
-#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register */
-#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register */
-#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register */
-#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register */
-#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register */
-#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register */
-#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register */
-#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register */
-
-#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register */
-#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register */
-#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register */
-#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register */
-#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register */
-#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register */
-#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register */
-#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register */
-
-#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register */
-#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register */
-#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register */
-#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register */
-#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register */
-#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register */
-#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register */
-#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register */
-
-#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register */
-#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register */
-#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register */
-#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register */
-#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register */
-#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register */
-#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register */
-#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register */
-
-#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register */
-#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register */
-#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register */
-#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register */
-#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register */
-#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register */
-#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register */
-#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register */
-
-#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register */
-#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register */
-#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register */
-#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register */
-#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register */
-#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register */
-#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register */
-#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register */
-
-#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register */
-#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register */
-#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register */
-#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register */
-#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register */
-#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register */
-#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register */
-#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register */
-
-/* CAN Mailbox Area Macros */
-#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
-
-
-/*********************************************************************************** */
-/* System MMR Register Bits and Macros */
-/******************************************************************************* */
-
-/* SWRST Mask */
-#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset */
-#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset */
-#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault */
-#define RESET_WDOG              0x4000  /* SW Reset Generated By Watchdog Timer */
-#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* SYSCR Masks                                                                                                   */
-#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins */
-#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
-#define PLL_WAKEUP_IRQ          0x00000001      /* PLL Wakeup Interrupt Request */
-#define DMAC0_ERR_IRQ           0x00000002      /* DMA Controller 0 Error Interrupt Request */
-#define PPI_ERR_IRQ             0x00000004      /* PPI Error Interrupt Request */
-#define SPORT0_ERR_IRQ          0x00000008      /* SPORT0 Error Interrupt Request */
-#define SPORT1_ERR_IRQ          0x00000010      /* SPORT1 Error Interrupt Request */
-#define SPI0_ERR_IRQ            0x00000020      /* SPI0 Error Interrupt Request */
-#define UART0_ERR_IRQ           0x00000040      /* UART0 Error Interrupt Request */
-#define RTC_IRQ                 0x00000080      /* Real-Time Clock Interrupt Request */
-#define DMA0_IRQ                0x00000100      /* DMA Channel 0 (PPI) Interrupt Request */
-#define DMA1_IRQ                0x00000200      /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
-#define DMA2_IRQ                0x00000400      /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
-#define DMA3_IRQ                0x00000800      /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
-#define DMA4_IRQ                0x00001000      /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
-#define DMA5_IRQ                0x00002000      /* DMA Channel 5 (SPI) Interrupt Request */
-#define DMA6_IRQ                0x00004000      /* DMA Channel 6 (UART RX) Interrupt Request */
-#define DMA7_IRQ                0x00008000      /* DMA Channel 7 (UART TX) Interrupt Request */
-#define TIMER0_IRQ              0x00010000      /* Timer 0 Interrupt Request */
-#define TIMER1_IRQ              0x00020000      /* Timer 1 Interrupt Request */
-#define TIMER2_IRQ              0x00040000      /* Timer 2 Interrupt Request */
-#define PFA_IRQ                 0x00080000      /* Programmable Flag Interrupt Request A */
-#define PFB_IRQ                 0x00100000      /* Programmable Flag Interrupt Request B */
-#define MDMA0_0_IRQ             0x00200000      /* MemDMA0 Stream 0 Interrupt Request */
-#define MDMA0_1_IRQ             0x00400000      /* MemDMA0 Stream 1 Interrupt Request */
-#define WDOG_IRQ                0x00800000      /* Software Watchdog Timer Interrupt Request */
-#define DMAC1_ERR_IRQ           0x01000000      /* DMA Controller 1 Error Interrupt Request */
-#define SPORT2_ERR_IRQ          0x02000000      /* SPORT2 Error Interrupt Request */
-#define SPORT3_ERR_IRQ          0x04000000      /* SPORT3 Error Interrupt Request */
-#define MXVR_SD_IRQ             0x08000000      /* MXVR Synchronous Data Interrupt Request */
-#define SPI1_ERR_IRQ            0x10000000      /* SPI1 Error Interrupt Request */
-#define SPI2_ERR_IRQ            0x20000000      /* SPI2 Error Interrupt Request */
-#define UART1_ERR_IRQ           0x40000000      /* UART1 Error Interrupt Request */
-#define UART2_ERR_IRQ           0x80000000      /* UART2 Error Interrupt Request */
-
-/* the following are for backwards compatibility */
-#define DMA0_ERR_IRQ            DMAC0_ERR_IRQ
-#define DMA1_ERR_IRQ            DMAC1_ERR_IRQ
-
-
-/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1   */
-#define CAN_ERR_IRQ                     0x00000001      /* CAN Error Interrupt Request */
-#define DMA8_IRQ                        0x00000002      /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
-#define DMA9_IRQ                        0x00000004      /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
-#define DMA10_IRQ                       0x00000008      /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
-#define DMA11_IRQ                       0x00000010      /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
-#define DMA12_IRQ                       0x00000020      /* DMA Channel 12 Interrupt Request */
-#define DMA13_IRQ                       0x00000040      /* DMA Channel 13 Interrupt Request */
-#define DMA14_IRQ                       0x00000080      /* DMA Channel 14 (SPI1) Interrupt Request */
-#define DMA15_IRQ                       0x00000100      /* DMA Channel 15 (SPI2) Interrupt Request */
-#define DMA16_IRQ                       0x00000200      /* DMA Channel 16 (UART1 RX) Interrupt Request */
-#define DMA17_IRQ                       0x00000400      /* DMA Channel 17 (UART1 TX) Interrupt Request */
-#define DMA18_IRQ                       0x00000800      /* DMA Channel 18 (UART2 RX) Interrupt Request */
-#define DMA19_IRQ                       0x00001000      /* DMA Channel 19 (UART2 TX) Interrupt Request */
-#define TWI0_IRQ                        0x00002000      /* TWI0 Interrupt Request */
-#define TWI1_IRQ                        0x00004000      /* TWI1 Interrupt Request */
-#define CAN_RX_IRQ                      0x00008000      /* CAN Receive Interrupt Request */
-#define CAN_TX_IRQ                      0x00010000      /* CAN Transmit Interrupt Request */
-#define MDMA1_0_IRQ                     0x00020000      /* MemDMA1 Stream 0 Interrupt Request */
-#define MDMA1_1_IRQ                     0x00040000      /* MemDMA1 Stream 1 Interrupt Request */
-#define MXVR_STAT_IRQ                   0x00080000      /* MXVR Status Interrupt Request */
-#define MXVR_CM_IRQ                     0x00100000      /* MXVR Control Message Interrupt Request */
-#define MXVR_AP_IRQ                     0x00200000      /* MXVR Asynchronous Packet Interrupt */
-
-/* the following are for backwards compatibility */
-#define MDMA0_IRQ               MDMA1_0_IRQ
-#define MDMA1_IRQ               MDMA1_1_IRQ
-
-#ifdef _MISRA_RULES
-#define _MF15 0xFu
-#define _MF7 7u
-#else
-#define _MF15 0xF
-#define _MF7 7
-#endif /* _MISRA_RULES */
-
-/* SIC_IMASKx Masks                                                                                      */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts */
-#ifdef _MISRA_RULES
-#define SIC_MASK(x)             (1 << ((x)&0x1Fu))                                      /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x)   (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Unmask Peripheral #x interrupt */
-#else
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt */
-#endif /* _MISRA_RULES */
-
-/* SIC_IWRx Masks                                                                                        */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals */
-#ifdef _MISRA_RULES
-#define IWR_ENABLE(x)   (1 << ((x)&0x1Fu))                                      /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x)  (0xFFFFFFFFu ^ (1 << ((x)&0x1Fu)))      /* Wakeup Disable Peripheral #x */
-#else
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x */
-#endif /* _MISRA_RULES */
-
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-/* UARTx_LCR Register */
-#ifdef _MISRA_RULES
-#define WLS(x)          (((x)-5u) & 0x03u)      /* Word Length Select */
-#else
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#endif /* _MISRA_RULES */
-#define STB                     0x04                            /* Stop Bits */
-#define PEN                     0x08                            /* Parity Enable */
-#define EPS                     0x10                            /* Even Parity Select */
-#define STP                     0x20                            /* Stick Parity */
-#define SB                      0x40                            /* Set Break */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-#define DLAB_P          0x07
-#define SB_P            0x06
-#define STP_P           0x05
-#define EPS_P           0x04
-#define PEN_P           0x03
-#define STB_P           0x02
-#define WLS_P1          0x01
-#define WLS_P0          0x00
-
-/* UARTx_MCR Register */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-/* Deprecated UARTx_MCR Mask                     */
-
-/* UARTx_LSR Register */
-#define DR                      0x01    /* Data Ready */
-#define OE                      0x02    /* Overrun Error */
-#define PE                      0x04    /* Parity Error */
-#define FE                      0x08    /* Framing Error */
-#define BI                      0x10    /* Break Interrupt */
-#define THRE            0x20    /* THR Empty */
-#define TEMT            0x40    /* TSR and UART_THR Empty */
-
-#define TEMP_P          0x06
-#define THRE_P          0x05
-#define BI_P            0x04
-#define FE_P            0x03
-#define PE_P            0x02
-#define OE_P            0x01
-#define DR_P            0x00
-
-/* UARTx_IER Register */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt */
-#define ELSI            0x04            /* Enable RX Status Interrupt */
-
-#define ELSI_P          0x02
-#define ETBEI_P         0x01
-#define ERBFI_P         0x00
-
-/* UARTx_IIR Register */
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-
-/* UARTx_GCTL Register */
-#define UCEN            0x01            /* Enable UARTx Clocks */
-#define IREN            0x02            /* Enable IrDA Mode */
-#define TPOLC           0x04            /* IrDA TX Polarity Change */
-#define RPOLC           0x08            /* IrDA RX Polarity Change */
-#define FPE                     0x10            /* Force Parity Error On Transmit */
-#define FFE                     0x20            /* Force Framing Error On Transmit */
-
-#define FFE_P           0x05
-#define FPE_P           0x04
-#define RPOLC_P         0x03
-#define TPOLC_P         0x02
-#define IREN_P          0x01
-#define UCEN_P          0x00
-
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-/*  PPI_CONTROL Masks         */
-#define PORT_EN         0x0001  /* PPI Port Enable  */
-#define PORT_DIR        0x0002  /* PPI Port Direction       */
-#define XFR_TYPE        0x000C  /* PPI Transfer Type  */
-#define PORT_CFG        0x0030  /* PPI Port Configuration */
-#define FLD_SEL         0x0040  /* PPI Active Field Select */
-#define PACK_EN         0x0080  /* PPI Packing Mode */
-/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
-#define SKIP_EN         0x0200  /* PPI Skip Element Enable */
-#define SKIP_EO         0x0400  /* PPI Skip Even/Odd Elements */
-#define DLENGTH         0x3800  /* PPI Data Length  */
-#define DLEN_8          0x0          /* PPI Data Length mask for DLEN=8 */
-#define DLEN_10         0x0800          /* Data Length = 10 Bits */
-#define DLEN_11         0x1000          /* Data Length = 11 Bits */
-#define DLEN_12         0x1800          /* Data Length = 12 Bits */
-#define DLEN_13         0x2000          /* Data Length = 13 Bits */
-#define DLEN_14         0x2800          /* Data Length = 14 Bits */
-#define DLEN_15         0x3000          /* Data Length = 15 Bits */
-#define DLEN_16         0x3800          /* Data Length = 16 Bits */
-#ifdef _MISRA_RULES
-#define DLEN(x)         ((((x)-9u) & 0x07u) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#else
-#define DLEN(x)         ((((x)-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#endif /* _MISRA_RULES */
-#define POL                     0xC000  /* PPI Signal Polarities       */
-#define POLC            0x4000          /* PPI Clock Polarity */
-#define POLS            0x8000          /* PPI Frame Sync Polarity */
-
-
-/* PPI_STATUS Masks                                          */
-#define FLD                     0x0400  /* Field Indicator   */
-#define FT_ERR          0x0800  /* Frame Track Error */
-#define OVR                     0x1000  /* FIFO Overflow Error */
-#define UNDR            0x2000  /* FIFO Underrun Error */
-#define ERR_DET         0x4000  /* Error Detected Indicator */
-#define ERR_NCOR        0x8000  /* Error Not Corrected Indicator */
-
-
-/* **********  DMA CONTROLLER MASKS  ***********************/
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator */
-#define CTYPE_P                 0x6             /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8                   0x0080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16                  0x0100  /* DMA 16-bit Operation Indicator */
-#define PCAP32                  0x0200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR                  0x0400  /* DMA Write Operation Indicator */
-#define PCAPRD                  0x0800  /* DMA Read Operation Indicator */
-#define PMAP                    0xF000  /* DMA Peripheral Map Field */
-
-/* PMAP Encodings For DMA Controller 0 */
-#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX   0x1000  /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX   0x2000  /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX   0x3000  /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX   0x4000  /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI0               0x5000  /* PMAP SPI DMA */
-#define PMAP_UART0RX            0x6000  /* PMAP UART Receive DMA */
-#define PMAP_UART0TX            0x7000  /* PMAP UART Transmit DMA */
-
-/* PMAP Encodings For DMA Controller 1 */
-#define PMAP_SPORT2RX       0x0000  /* PMAP SPORT2 Receive DMA */
-#define PMAP_SPORT2TX       0x1000  /* PMAP SPORT2 Transmit DMA */
-#define PMAP_SPORT3RX       0x2000  /* PMAP SPORT3 Receive DMA */
-#define PMAP_SPORT3TX       0x3000  /* PMAP SPORT3 Transmit DMA */
-#define PMAP_SPI1           0x6000  /* PMAP SPI1 DMA */
-#define PMAP_SPI2           0x7000  /* PMAP SPI2 DMA */
-#define PMAP_UART1RX        0x8000  /* PMAP UART1 Receive DMA */
-#define PMAP_UART1TX        0x9000  /* PMAP UART1 Transmit DMA */
-#define PMAP_UART2RX        0xA000  /* PMAP UART2 Receive DMA */
-#define PMAP_UART2TX        0xB000  /* PMAP UART2 Transmit DMA */
-
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-/* PWM Timer bit definitions */
-/* TIMER_ENABLE Register */
-#define TIMEN0                  0x0001  /* Enable Timer 0 */
-#define TIMEN1                  0x0002  /* Enable Timer 1 */
-#define TIMEN2                  0x0004  /* Enable Timer 2 */
-
-#define TIMEN0_P                0x00
-#define TIMEN1_P                0x01
-#define TIMEN2_P                0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0                 0x0001  /* Disable Timer 0 */
-#define TIMDIS1                 0x0002  /* Disable Timer 1 */
-#define TIMDIS2                 0x0004  /* Disable Timer 2 */
-
-#define TIMDIS0_P               0x00
-#define TIMDIS1_P               0x01
-#define TIMDIS2_P               0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0                  0x0001  /* Timer 0 Interrupt */
-#define TIMIL1                  0x0002  /* Timer 1 Interrupt */
-#define TIMIL2                  0x0004  /* Timer 2 Interrupt */
-#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow */
-#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow */
-#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow */
-#define TRUN0                   0x1000  /* Timer 0 Slave Enable Status */
-#define TRUN1                   0x2000  /* Timer 1 Slave Enable Status */
-#define TRUN2                   0x4000  /* Timer 2 Slave Enable Status */
-
-#define TIMIL0_P                0x00
-#define TIMIL1_P                0x01
-#define TIMIL2_P                0x02
-#define TOVF_ERR0_P             0x04
-#define TOVF_ERR1_P             0x05
-#define TOVF_ERR2_P             0x06
-#define TRUN0_P                 0x0C
-#define TRUN1_P                 0x0D
-#define TRUN2_P                 0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0               TOVF_ERR0
-#define TOVL_ERR1               TOVF_ERR1
-#define TOVL_ERR2               TOVF_ERR2
-#define TOVL_ERR0_P             TOVF_ERR0_P
-#define TOVL_ERR1_P     TOVF_ERR1_P
-#define TOVL_ERR2_P     TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT                 0x0001
-#define WDTH_CAP                0x0002
-#define EXT_CLK                 0x0003
-#define PULSE_HI                0x0004
-#define PERIOD_CNT              0x0008
-#define IRQ_ENA                 0x0010
-#define TIN_SEL                 0x0020
-#define OUT_DIS                 0x0040
-#define CLK_SEL                 0x0080
-#define TOGGLE_HI               0x0100
-#define EMU_RUN                 0x0200
-#ifdef _MISRA_RULES
-#define ERR_TYP(x)              (((x) & 0x03u) << 14)
-#else
-#define ERR_TYP(x)              (((x) & 0x03) << 14)
-#endif /* _MISRA_RULES */
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P    0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-
-/*/ ******************   GENERAL-PURPOSE I/O  ********************* */
-/*  Flag I/O (FIO_) Masks */
-#define PF0                     0x0001
-#define PF1                     0x0002
-#define PF2                     0x0004
-#define PF3                     0x0008
-#define PF4                     0x0010
-#define PF5                     0x0020
-#define PF6                     0x0040
-#define PF7                     0x0080
-#define PF8                     0x0100
-#define PF9                     0x0200
-#define PF10            0x0400
-#define PF11            0x0800
-#define PF12            0x1000
-#define PF13            0x2000
-#define PF14            0x4000
-#define PF15            0x8000
-
-/*  PORT F BIT POSITIONS */
-#define PF0_P           0x0
-#define PF1_P           0x1
-#define PF2_P           0x2
-#define PF3_P           0x3
-#define PF4_P           0x4
-#define PF5_P           0x5
-#define PF6_P           0x6
-#define PF7_P           0x7
-#define PF8_P           0x8
-#define PF9_P           0x9
-#define PF10_P          0xA
-#define PF11_P          0xB
-#define PF12_P          0xC
-#define PF13_P          0xD
-#define PF14_P          0xE
-#define PF15_P          0xF
-
-
-/*******************   GPIO MASKS  *********************/
-/* Port C Masks */
-#define PC0             0x0001
-#define PC1             0x0002
-#define PC4             0x0010
-#define PC5             0x0020
-#define PC6             0x0040
-#define PC7             0x0080
-#define PC8             0x0100
-#define PC9             0x0200
-/* Port C Bit Positions */
-#define PC0_P   0x0
-#define PC1_P   0x1
-#define PC4_P   0x4
-#define PC5_P   0x5
-#define PC6_P   0x6
-#define PC7_P   0x7
-#define PC8_P   0x8
-#define PC9_P   0x9
-
-/* Port D */
-#define PD0             0x0001
-#define PD1             0x0002
-#define PD2             0x0004
-#define PD3             0x0008
-#define PD4             0x0010
-#define PD5             0x0020
-#define PD6             0x0040
-#define PD7             0x0080
-#define PD8             0x0100
-#define PD9             0x0200
-#define PD10    0x0400
-#define PD11    0x0800
-#define PD12    0x1000
-#define PD13    0x2000
-#define PD14    0x4000
-#define PD15    0x8000
-/* Port D Bit Positions */
-#define PD0_P   0x0
-#define PD1_P   0x1
-#define PD2_P   0x2
-#define PD3_P   0x3
-#define PD4_P   0x4
-#define PD5_P   0x5
-#define PD6_P   0x6
-#define PD7_P   0x7
-#define PD8_P   0x8
-#define PD9_P   0x9
-#define PD10_P  0xA
-#define PD11_P  0xB
-#define PD12_P  0xC
-#define PD13_P  0xD
-#define PD14_P  0xE
-#define PD15_P  0xF
-
-/* Port E */
-#define PE0             0x0001
-#define PE1             0x0002
-#define PE2             0x0004
-#define PE3             0x0008
-#define PE4             0x0010
-#define PE5             0x0020
-#define PE6             0x0040
-#define PE7             0x0080
-#define PE8             0x0100
-#define PE9             0x0200
-#define PE10    0x0400
-#define PE11    0x0800
-#define PE12    0x1000
-#define PE13    0x2000
-#define PE14    0x4000
-#define PE15    0x8000
-/* Port E Bit Positions */
-#define PE0_P   0x0
-#define PE1_P   0x1
-#define PE2_P   0x2
-#define PE3_P   0x3
-#define PE4_P   0x4
-#define PE5_P   0x5
-#define PE6_P   0x6
-#define PE7_P   0x7
-#define PE8_P   0x8
-#define PE9_P   0x9
-#define PE10_P  0xA
-#define PE11_P  0xB
-#define PE12_P  0xC
-#define PE13_P  0xD
-#define PE14_P  0xE
-#define PE15_P  0xF
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-/* EBIU_AMGCTL Masks */
-#define AMCKEN          0x0001  /* Enable CLKOUT */
-#define AMBEN_NONE      0x0000  /* All Banks Disabled */
-#define AMBEN_B0        0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1     0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL       0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define CDPRIO          0x0100  /* DMA has priority over core for external accesses */
-
-/* EBIU_AMGCTL Bit Positions */
-#define AMCKEN_P                0x0000  /* Enable CLKOUT */
-#define AMBEN_P0                0x0001  /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x0002  /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x0003  /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* EBIU_AMBCTL0 Masks */
-#define B0RDYEN                 0x00000001  /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL                0x00000002  /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1                  0x00000004  /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2                  0x00000008  /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3                  0x0000000C  /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4                  0x00000000  /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1                  0x00000010  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2                  0x00000020  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3                  0x00000030  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4                  0x00000000  /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1                  0x00000040  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2                  0x00000080  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3                  0x000000C0  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0                  0x00000000  /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100  /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200  /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300  /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400  /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500  /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600  /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700  /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800  /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900  /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00  /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00  /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00  /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00  /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00  /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00  /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000  /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000  /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000  /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000  /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000  /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000  /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000  /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000  /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000  /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000  /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000  /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000  /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000  /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000  /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000  /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000  /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000  /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000  /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000  /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000  /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000  /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000  /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000  /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000  /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000  /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000  /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000  /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000  /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000  /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000  /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000  /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000  /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000  /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000  /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000  /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000  /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000  /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000  /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000  /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000  /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000  /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000  /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000  /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000  /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000  /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000  /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000  /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000  /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000  /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000  /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000  /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000  /* Bank 1 Write Access Time = 15 cycles */
-
-/* EBIU_AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001  /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002  /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004  /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008  /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C  /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000  /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000  /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000  /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100  /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200  /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300  /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400  /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500  /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600  /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700  /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800  /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900  /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00  /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00  /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00  /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00  /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00  /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00  /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000  /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000  /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000  /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000  /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000  /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000  /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000  /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000  /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000  /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000  /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000  /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000  /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000  /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000  /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000  /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000  /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000  /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000  /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000  /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000  /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000  /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000  /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000  /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000  /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000  /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000  /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000  /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000  /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000  /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000  /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000  /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000  /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000  /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000  /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000  /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000  /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000  /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000  /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000  /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000  /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000  /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000  /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000  /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000  /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000  /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000  /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000  /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000  /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000  /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000  /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000  /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-/* EBIU_SDGCTL Masks */
-#define SCTLE                   0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008 /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C /* SDRAM CAS latency = 3 cycles */
-#define PFE                             0x00000010 /* Enable SDRAM prefetch */
-#define PFP                             0x00000020 /* Prefetch has priority over AMC requests */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
-#define TRAS_1                  0x00000040 /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080 /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0 /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100 /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140 /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180 /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0 /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200 /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240 /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280 /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0 /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300 /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340 /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380 /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0 /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800 /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000 /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800 /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000 /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800 /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000 /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800 /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000 /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000 /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000 /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000 /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000 /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000 /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000 /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000 /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000 /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000 /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000 /*Power-up start delay */
-#define PSM                             0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000 /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000 /* Enable external buffering timing */
-#define FBBRW                   0x04000000 /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000 /* Extended mode register enable */
-#define TCSR                    0x20000000 /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000 /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE                             0x00000001 /* Enable SDRAM external bank */
-#define EBSZ_16                 0x00000000 /* SDRAM external bank size = 16MB */
-#define EBSZ_32                 0x00000002 /* SDRAM external bank size = 32MB */
-#define EBSZ_64                 0x00000004 /* SDRAM external bank size = 64MB */
-#define EBSZ_128                0x00000006 /* SDRAM external bank size = 128MB */
-#define EBSZ_256                0x00000008 /* SDRAM External Bank Size = 256MB */
-#define EBSZ_512                0x0000000A /* SDRAM External Bank Size = 512MB */
-#define EBCAW_8                 0x00000000 /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9                 0x00000010 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10                0x00000020 /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11                0x00000030 /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001 /* SDRAM controller is idle */
-#define SDSRA                   0x00000002 /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004 /* SDRAM power up active  */
-#define SDRS                    0x00000008 /* SDRAM is in reset state */
-#define SDEASE                  0x00000010 /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020 /* Bus granted */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWIx) MASKS  ***********************/
-/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y);  ) */
-#ifdef _MISRA_RULES
-#define CLKLOW(x)       ((x) & 0xFFu)           /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFFu)<<0x8)      /* Periods Before New Clock Low */
-#else
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low */
-#endif /* _MISRA_RULES */
-
-/* TWIx_PRESCALE Masks                                                           */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz) */
-#define TWI_ENA         0x0080          /* TWI Enable            */
-#define SCCB            0x0200          /* SCCB Compatibility Enable */
-
-/* TWIx_SLAVE_CTRL Masks                                                                 */
-#define SEN                     0x0001          /* Slave Enable          */
-#define SADD_LEN        0x0002          /* Slave Address Length */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled */
-
-/* TWIx_SLAVE_STAT Masks                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator */
-
-/* TWIx_MASTER_CTRL Masks                                                */
-#define MEN                     0x0001          /* Master Mode Enable */
-#define MADD_LEN        0x0002          /* Master Address Length */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*) */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs */
-#define STOP            0x0010          /* Issue Stop Condition */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer */
-#define SDAOVR          0x4000          /* Serial Data Override */
-#define SCLOVR          0x8000          /* Serial Clock Override */
-
-/* TWIx_MASTER_STAT Masks                                                        */
-#define MPROG           0x0001          /* Master Transfer In Progress */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted) */
-#define ANAK            0x0004          /* Address Not Acknowledged */
-#define DNAK            0x0008          /* Data Not Acknowledged */
-#define BUFRDERR        0x0010          /* Buffer Read Error */
-#define BUFWRERR        0x0020          /* Buffer Write Error */
-#define SDASEN          0x0040          /* Serial Data Sense */
-#define SCLSEN          0x0080          /* Serial Clock Sense */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator */
-
-/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
-#define SINIT           0x0001          /* Slave Transfer Initiated */
-#define SCOMP           0x0002          /* Slave Transfer Complete */
-#define SERR            0x0004          /* Slave Transfer Error */
-#define SOVF            0x0008          /* Slave Overflow */
-#define MCOMP           0x0010          /* Master Transfer Complete */
-#define MERR            0x0020          /* Master Transfer Error */
-#define XMTSERV         0x0040          /* Transmit FIFO Service */
-#define RCVSERV         0x0080          /* Receive FIFO Service */
-
-/* TWIx_FIFO_CTL Masks                                   */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length */
-
-/* TWIx_FIFO_STAT Masks                                                          */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write) */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read) */
-
 #endif /* _DEF_BF539_H */
diff --git a/arch/blackfin/mach-bf538/include/mach/gpio.h b/arch/blackfin/mach-bf538/include/mach/gpio.h
index bd9adb7183da..8a5beeece996 100644
--- a/arch/blackfin/mach-bf538/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf538/include/mach/gpio.h
@@ -70,4 +70,9 @@
 #define PORT_D GPIO_PD0
 #define PORT_E GPIO_PE0
 
+#include <mach-common/ports-c.h>
+#include <mach-common/ports-d.h>
+#include <mach-common/ports-e.h>
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf538/include/mach/pll.h b/arch/blackfin/mach-bf538/include/mach/pll.h
index b30bbcd412a7..94cca674d835 100644
--- a/arch/blackfin/mach-bf538/include/mach/pll.h
+++ b/arch/blackfin/mach-bf538/include/mach/pll.h
@@ -1,63 +1 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index 4c2ee6789099..d11502ac5623 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -156,7 +156,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -211,7 +211,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX,
 #ifdef CONFIG_BFIN_UART1_CTSRTS
         P_UART1_RTS, P_UART1_CTS,
@@ -258,7 +258,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -313,7 +313,7 @@ static struct resource bfin_uart3_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart3_peripherals[] = {
+static unsigned short bfin_uart3_peripherals[] = {
         P_UART3_TX, P_UART3_RX,
 #ifdef CONFIG_BFIN_UART3_CTSRTS
         P_UART3_RTS, P_UART3_CTS,
@@ -504,6 +504,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -552,9 +553,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -586,9 +587,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -620,7 +621,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -654,7 +655,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -756,7 +757,7 @@ static struct platform_device bf54x_sdh_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 4f03fbc4c9be..ce5a2bb147dc 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -261,7 +261,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
@@ -316,7 +316,7 @@ static struct resource bfin_uart1_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart1_peripherals[] = {
+static unsigned short bfin_uart1_peripherals[] = {
         P_UART1_TX, P_UART1_RX,
 #ifdef CONFIG_BFIN_UART1_CTSRTS
         P_UART1_RTS, P_UART1_CTS,
@@ -363,7 +363,7 @@ static struct resource bfin_uart2_resources[] = {
         },
 };
 
-unsigned short bfin_uart2_peripherals[] = {
+static unsigned short bfin_uart2_peripherals[] = {
         P_UART2_TX, P_UART2_RX, 0
 };
 
@@ -418,7 +418,7 @@ static struct resource bfin_uart3_resources[] = {
 #endif
 };
 
-unsigned short bfin_uart3_peripherals[] = {
+static unsigned short bfin_uart3_peripherals[] = {
         P_UART3_TX, P_UART3_RX,
 #ifdef CONFIG_BFIN_UART3_CTSRTS
         P_UART3_RTS, P_UART3_CTS,
@@ -609,6 +609,7 @@ static struct musb_hdrc_config musb_config = {
          * if it is the case.
          */
         .gpio_vrsel_active      = 1,
+        .clkin          = 24,           /* musb CLKIN in MHZ */
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
@@ -657,9 +658,9 @@ static struct resource bfin_sport0_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport0_peripherals[] = {
+static unsigned short bfin_sport0_peripherals[] = {
         P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
-        P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
+        P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
 };
 
 static struct platform_device bfin_sport0_uart_device = {
@@ -691,9 +692,9 @@ static struct resource bfin_sport1_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport1_peripherals[] = {
+static unsigned short bfin_sport1_peripherals[] = {
         P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
-        P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_DRSEC, P_SPORT1_DTSEC, 0
+        P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
 };
 
 static struct platform_device bfin_sport1_uart_device = {
@@ -725,7 +726,7 @@ static struct resource bfin_sport2_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport2_peripherals[] = {
+static unsigned short bfin_sport2_peripherals[] = {
         P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
         P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
 };
@@ -759,7 +760,7 @@ static struct resource bfin_sport3_uart_resources[] = {
         },
 };
 
-unsigned short bfin_sport3_peripherals[] = {
+static unsigned short bfin_sport3_peripherals[] = {
         P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
         P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
 };
@@ -777,7 +778,7 @@ static struct platform_device bfin_sport3_uart_device = {
 #endif
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
-unsigned short bfin_can_peripherals[] = {
+static unsigned short bfin_can_peripherals[] = {
         P_CAN0_RX, P_CAN0_TX, 0
 };
 
diff --git a/arch/blackfin/mach-bf548/dma.c b/arch/blackfin/mach-bf548/dma.c
index 888b9cc0b822..69ead33cbf91 100644
--- a/arch/blackfin/mach-bf548/dma.c
+++ b/arch/blackfin/mach-bf548/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..a77109f99720
--- /dev/null
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial.h
@@ -0,0 +1,16 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      4
+
+#define BFIN_UART_BF54X_STYLE
+
+#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index dd44aa75fe72..0d94edaaaa2e 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -4,72 +4,14 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-#define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
-#define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
-#define UART_CLEAR_IER(uart,v)  bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-#define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
-#define UART_CLEAR_SCTS(uart)   bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
-
-#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
-#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
-
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
-#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
         defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
 # define CONFIG_SERIAL_BFIN_HARD_CTSRTS
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        int                     scts;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -148,3 +90,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/blackfin.h b/arch/blackfin/mach-bf548/include/mach/blackfin.h
index 5684030ccc21..72da721a77f5 100644
--- a/arch/blackfin/mach-bf548/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf548/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2009 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,58 +10,40 @@
 #include "bf548.h"
 #include "anomaly.h"
 
+#include <asm/def_LPBlackfin.h>
 #ifdef CONFIG_BF542
-#include "defBF542.h"
+# include "defBF542.h"
 #endif
-
 #ifdef CONFIG_BF544
-#include "defBF544.h"
+# include "defBF544.h"
 #endif
-
 #ifdef CONFIG_BF547
-#include "defBF547.h"
+# include "defBF547.h"
 #endif
-
 #ifdef CONFIG_BF548
-#include "defBF548.h"
+# include "defBF548.h"
 #endif
-
 #ifdef CONFIG_BF549
-#include "defBF549.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#ifdef CONFIG_BF542
-#include "cdefBF542.h"
+# include "defBF549.h"
+#endif
+
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# ifdef CONFIG_BF542
+#  include "cdefBF542.h"
+# endif
+# ifdef CONFIG_BF544
+#  include "cdefBF544.h"
+# endif
+# ifdef CONFIG_BF547
+#  include "cdefBF547.h"
+# endif
+# ifdef CONFIG_BF548
+#  include "cdefBF548.h"
+# endif
+# ifdef CONFIG_BF549
+#  include "cdefBF549.h"
+# endif
 #endif
-#ifdef CONFIG_BF544
-#include "cdefBF544.h"
-#endif
-#ifdef CONFIG_BF547
-#include "cdefBF547.h"
-#endif
-#ifdef CONFIG_BF548
-#include "cdefBF548.h"
-#endif
-#ifdef CONFIG_BF549
-#include "cdefBF549.h"
-#endif
-
-#endif
-
-#define BFIN_UART_NR_PORTS      4
-
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_GCTL             0x08    /* Global Control Register              */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
-#define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
-#define OFFSET_THR              0x28    /* Transmit Holding register            */
-#define OFFSET_RBR              0x2C    /* Receive Buffer register              */
 
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
index 42f4a9469549..d09c19cd1b7b 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF542.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF542_H
 #define _CDEF_BF542_H
 
-/* include all Core registers and bit definitions */
-#include "defBF542.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
index 2207799575ff..33ec8102ceda 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF544.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF544_H
 #define _CDEF_BF544_H
 
-/* include all Core registers and bit definitions */
-#include "defBF544.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
index bc650e6ea482..bcb9726dea54 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF547.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF547_H
 #define _CDEF_BF547_H
 
-/* include all Core registers and bit definitions */
-#include "defBF547.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
index 3523e08f7968..bae67a65633e 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF548.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF548_H
 #define _CDEF_BF548_H
 
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
index 80201ed41f80..002136ad5a44 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF549.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF549_H
 #define _CDEF_BF549_H
 
-/* include all Core registers and bit definitions */
-#include "defBF549.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
 /* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
 #include "cdefBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
index deaf5d6542d5..50c89c8052f3 100644
--- a/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,10 +7,6 @@
 #ifndef _CDEF_BF54X_H
 #define _CDEF_BF54X_H
 
-#include <asm/blackfin.h>
-
-#include "defBF54x_base.h"
-
 /* ************************************************************** */
 /* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
 /* ************************************************************** */
@@ -2633,22 +2629,5 @@
 
 /* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
 
-/* legacy definitions */
-#define bfin_read_EBIU_AMCBCTL0         bfin_read_EBIU_AMBCTL0
-#define bfin_write_EBIU_AMCBCTL0        bfin_write_EBIU_AMBCTL0
-#define bfin_read_EBIU_AMCBCTL1         bfin_read_EBIU_AMBCTL1
-#define bfin_write_EBIU_AMCBCTL1        bfin_write_EBIU_AMBCTL1
-#define bfin_read_PINT0_IRQ             bfin_read_PINT0_REQUEST
-#define bfin_write_PINT0_IRQ            bfin_write_PINT0_REQUEST
-#define bfin_read_PINT1_IRQ             bfin_read_PINT1_REQUEST
-#define bfin_write_PINT1_IRQ            bfin_write_PINT1_REQUEST
-#define bfin_read_PINT2_IRQ             bfin_read_PINT2_REQUEST
-#define bfin_write_PINT2_IRQ            bfin_write_PINT2_REQUEST
-#define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
-#define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif /* _CDEF_BF54X_H */
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF542.h b/arch/blackfin/mach-bf548/include/mach/defBF542.h
index abf5f750dd8b..629bf216e2b5 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF542.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF542.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF542_H
 #define _DEF_BF542_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index e2771094de02..642468c1bcb1 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF544_H
 #define _DEF_BF544_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index be21ba5b3aa8..2f3337cd311e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Analog Devices Inc.
+ * Copyright 2008-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF547_H
 #define _DEF_BF547_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF548.h b/arch/blackfin/mach-bf548/include/mach/defBF548.h
index 3fb33b040ab7..3c7f1b69349e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF548.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF548.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF548_H
 #define _DEF_BF548_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF549.h b/arch/blackfin/mach-bf548/include/mach/defBF549.h
index 5a04e6d4017e..9a45cb6b30da 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF549.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF549.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -7,11 +7,6 @@
 #ifndef _DEF_BF549_H
 #define _DEF_BF549_H
 
-/* Include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
 #include "defBF54x_base.h"
 
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 78f91103f175..0867c2bedb43 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2007-2008 Analog Devices Inc.
+ * Copyright 2007-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
@@ -1615,14 +1615,14 @@
 #define                     CTYPE  0x40       /* DMA Channel Type */
 #define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
 
-/* Bit masks for DMACx_TCPER */
+/* Bit masks for DMACx_TC_PER */
 
 #define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
 #define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
 #define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
 #define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
 
-/* Bit masks for DMACx_TCCNT */
+/* Bit masks for DMACx_TC_CNT */
 
 #define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
 #define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
@@ -2172,68 +2172,6 @@
 
 #define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
 
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                       PEN  0x8        /* Parity Enable */
-#define                       EPS  0x10       /* Even Parity Select */
-#define                       STP  0x20       /* Sticky Parity */
-#define                        SB  0x40       /* Set Break */
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                        OE  0x2        /* Overrun Error */
-#define                        PE  0x4        /* Parity Error */
-#define                        FE  0x8        /* Framing Error */
-#define                        BI  0x10       /* Break Interrupt */
-#define                      THRE  0x20       /* THR Empty */
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                       CTS  0x10       /* Clear To Send */
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-
-/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
-
-#define                   ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                   ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                   EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                  EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                    ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                   ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                       FPE  0x10       /* Force Parity Error */
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-
-
 /* ******************************************* */
 /*     MULTI BIT MACRO ENUMERATIONS            */
 /* ******************************************* */
@@ -2251,13 +2189,6 @@
 #define WDTH_CAP 0x0002
 #define EXT_CLK  0x0003
 
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
 /* PINTx Register Bit Definitions */
 
 #define PIQ0 0x00000001
@@ -2300,240 +2231,6 @@
 #define PIQ30 0x40000000
 #define PIQ31 0x80000000
 
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR,
-PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
-PORTA_FER registers
-*/
-
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR,
-PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
-PORTB_FER registers
-*/
-
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-
-
-/* PORT C Bit Definitions for the registers
-PORTC, PORTC_SET, PORTC_CLEAR,
-PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
-PORTC_FER registers
-*/
-
-
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR,
-PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
-PORTD_FER registers
-*/
-
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR,
-PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
-PORTE_FER registers
-*/
-
-
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR,
-PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
-PORTF_FER registers
-*/
-
-
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR,
-PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
-PORTG_FER registers
-*/
-
-
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR,
-PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
-PORTH_FER registers
-*/
-
-
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR,
-PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
-PORTI_FER registers
-*/
-
-
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR,
-PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
-PORTJ_FER registers
-*/
-
-
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-
-
 /* Port Muxing Bit Fields for PORTx_MUX Registers */
 
 #define MUX0 0x00000003
@@ -2703,16 +2400,4 @@ PORTJ_FER registers
 #define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
 #define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
 
-
-/* for legacy compatibility */
-
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#define W1LMAX_MAX W1LMAX_MIN
-#define EBIU_AMCBCTL0 EBIU_AMBCTL0
-#define EBIU_AMCBCTL1 EBIU_AMBCTL1
-#define PINT0_IRQ PINT0_REQUEST
-#define PINT1_IRQ PINT1_REQUEST
-#define PINT2_IRQ PINT2_REQUEST
-#define PINT3_IRQ PINT3_REQUEST
-
 #endif /* _DEF_BF54X_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 28037e331964..7db433514e3f 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -200,4 +200,15 @@ struct gpio_port_s {
 
 #endif
 
+#include <mach-common/ports-a.h>
+#include <mach-common/ports-b.h>
+#include <mach-common/ports-c.h>
+#include <mach-common/ports-d.h>
+#include <mach-common/ports-e.h>
+#include <mach-common/ports-f.h>
+#include <mach-common/ports-g.h>
+#include <mach-common/ports-h.h>
+#include <mach-common/ports-i.h>
+#include <mach-common/ports-j.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 1f99b51a3d56..99fd1b2c53d8 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -474,4 +474,26 @@ Events         (highest priority)  EMU         0
 #define IRQ_PINT2_POS           24
 #define IRQ_PINT3_POS           28
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+
+/*
+ * bfin pint registers layout
+ */
+struct bfin_pint_regs {
+        u32 mask_set;
+        u32 mask_clear;
+        u32 irq;
+        u32 assign;
+        u32 edge_set;
+        u32 edge_clear;
+        u32 invert_set;
+        u32 invert_clear;
+        u32 pinstate;
+        u32 latch;
+        u32 __pad0[2];
+};
+
+#endif
+
 #endif /* _BF548_IRQ_H_ */
diff --git a/arch/blackfin/mach-bf548/include/mach/pll.h b/arch/blackfin/mach-bf548/include/mach/pll.h
index 7865a090d333..94cca674d835 100644
--- a/arch/blackfin/mach-bf548/include/mach/pll.h
+++ b/arch/blackfin/mach-bf548/include/mach/pll.h
@@ -1,69 +1 @@
-/*
- * Copyright 2007-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _MACH_PLL_H
-#define _MACH_PLL_H
-
-#include <asm/blackfin.h>
-#include <asm/irqflags.h>
-
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        hard_local_irq_restore(flags);
-}
-
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        hard_local_irq_restore(flags);
-}
-
-#endif /* _MACH_PLL_H */
+#include <mach-common/pll.h>
diff --git a/arch/blackfin/mach-bf561/atomic.S b/arch/blackfin/mach-bf561/atomic.S
index f99f174b129f..52d6f73fcced 100644
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -49,6 +49,7 @@ ENTRY(_get_core_lock)
         jump .Lretry_corelock
 .Ldone_corelock:
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
         CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
@@ -685,6 +686,8 @@ ENTRY(___raw_atomic_test_asm)
         r1 = -L1_CACHE_BYTES;
         r1 = r0 & r1;
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
+        CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
         r0 = [p1];
@@ -907,6 +910,8 @@ ENTRY(___raw_uncached_fetch_asm)
         r1 = -L1_CACHE_BYTES;
         r1 = r0 & r1;
         p0 = r1;
+        /* flush core internal write buffer before invalidate dcache */
+        CSYNC(r2);
         flushinv[p0];
         SSYNC(r2);
         r0 = [p1];
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 0b1c20f14fe0..3926cd909b66 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -224,7 +224,7 @@ static struct resource bfin_uart0_resources[] = {
          },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 087b6b05cc73..3b67929d4c0a 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -334,7 +334,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index ab7a487975fd..f667e7704197 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -190,7 +190,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/boards/tepla.c b/arch/blackfin/mach-bf561/boards/tepla.c
index d3017e53686b..bb056e60f6ed 100644
--- a/arch/blackfin/mach-bf561/boards/tepla.c
+++ b/arch/blackfin/mach-bf561/boards/tepla.c
@@ -72,7 +72,7 @@ static struct resource bfin_uart0_resources[] = {
         },
 };
 
-unsigned short bfin_uart0_peripherals[] = {
+static unsigned short bfin_uart0_peripherals[] = {
         P_UART0_TX, P_UART0_RX, 0
 };
 
diff --git a/arch/blackfin/mach-bf561/dma.c b/arch/blackfin/mach-bf561/dma.c
index c938c3c7355d..8ffdd6b4a242 100644
--- a/arch/blackfin/mach-bf561/dma.c
+++ b/arch/blackfin/mach-bf561/dma.c
@@ -11,7 +11,7 @@
 #include <asm/blackfin.h>
 #include <asm/dma.h>
 
-struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
+struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA1_0_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_1_NEXT_DESC_PTR,
         (struct dma_register *) DMA1_2_NEXT_DESC_PTR,
@@ -36,14 +36,14 @@ struct dma_register *dma_io_base_addr[MAX_DMA_CHANNELS] = {
         (struct dma_register *) DMA2_9_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_10_NEXT_DESC_PTR,
         (struct dma_register *) DMA2_11_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA1_S1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S0_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_D1_NEXT_DESC_PTR,
-        (struct dma_register *) MDMA2_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S0_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S1_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S2_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_D3_NEXT_DESC_PTR,
+        (struct dma_register *) MDMA_S3_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_D0_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_S0_NEXT_DESC_PTR,
         (struct dma_register *) IMDMA_D1_NEXT_DESC_PTR,
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index c95169b612dc..4cd3b28cd046 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -6,7 +6,9 @@
  */
 
 #include <asm/blackfin.h>
+#include <asm/irq.h>
 #include <asm/smp.h>
+
 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
 
 int hotplug_coreb;
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 4c108c99cb6e..6a3499b02097 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -181,7 +181,11 @@
 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
 #define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
 /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Tempoary work around for kgdb bug 6333 in SMP kernel. It looks coreb hangs in exception
+ * without handling anomaly 05000257 properly on bf561 v0.5. This work around may change
+ * after the behavior and the root cause are confirmed with hardware team.
+ */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5 || (__SILICON_REVISION__ == 5 && CONFIG_SMP))
 /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
 #define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
 /* ICPLB_STATUS MMR Register May Be Corrupted */
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
new file mode 100644
index 000000000000..08072c86d5dc
--- /dev/null
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial.h
@@ -0,0 +1,14 @@
+/*
+ * mach/bfin_serial.h - Blackfin UART/Serial definitions
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef __BFIN_MACH_SERIAL_H__
+#define __BFIN_MACH_SERIAL_H__
+
+#define BFIN_UART_NR_PORTS      1
+
+#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index e33e158bc16d..3a6947456cf1 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -4,36 +4,9 @@
  * Licensed under the GPL-2 or later.
  */
 
-#include <linux/serial.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
 
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_DISABLE_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_ENABLE_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
@@ -44,51 +17,6 @@
 # endif
 #endif
 
-#define BFIN_UART_TX_FIFO_SIZE  2
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        int                     status_irq;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000363
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
 struct bfin_serial_res {
         unsigned long   uart_base_addr;
         int             uart_irq;
@@ -120,3 +48,5 @@ struct bfin_serial_res bfin_serial_resource[] = {
 };
 
 #define DRIVER_NAME "bfin-uart"
+
+#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/blackfin.h b/arch/blackfin/mach-bf561/include/mach/blackfin.h
index 6c7dc58c018c..dc470534c085 100644
--- a/arch/blackfin/mach-bf561/include/mach/blackfin.h
+++ b/arch/blackfin/mach-bf561/include/mach/blackfin.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -10,11 +10,14 @@
 #define BF561_FAMILY
 
 #include "bf561.h"
-#include "defBF561.h"
 #include "anomaly.h"
 
-#if !defined(__ASSEMBLY__)
-#include "cdefBF561.h"
+#include <asm/def_LPBlackfin.h>
+#include "defBF561.h"
+
+#ifndef __ASSEMBLY__
+# include <asm/cdef_LPBlackfin.h>
+# include "cdefBF561.h"
 #endif
 
 #define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
@@ -35,19 +38,4 @@
 #define bfin_read_SICB_ISR(x)           bfin_read32(__SIC_MUX(SICB_ISR0, x))
 #define bfin_write_SICB_ISR(x, val)     bfin_write32(__SIC_MUX(SICB_ISR0, x), val)
 
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
 #endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
index 2bab99152495..753331597207 100644
--- a/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/cdefBF561.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,14 +7,6 @@
 #ifndef _CDEF_BF561_H
 #define _CDEF_BF561_H
 
-#include <asm/blackfin.h>
-
-/* include all Core registers and bit definitions */
-#include "defBF561.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/cdef_LPBlackfin.h>
-
 /*********************************************************************************** */
 /* System MMR Register Map */
 /*********************************************************************************** */
@@ -523,14 +515,14 @@
 #define bfin_read_PPI1_FRAME()               bfin_read16(PPI1_FRAME)
 #define bfin_write_PPI1_FRAME(val)           bfin_write16(PPI1_FRAME,val)
 /*DMA traffic control registers */
-#define bfin_read_DMA1_TC_PER()              bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)          bfin_write16(DMA1_TC_PER,val)
-#define bfin_read_DMA1_TC_CNT()              bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)          bfin_write16(DMA1_TC_CNT,val)
-#define bfin_read_DMA2_TC_PER()              bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val)          bfin_write16(DMA2_TC_PER,val)
-#define bfin_read_DMA2_TC_CNT()              bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val)          bfin_write16(DMA2_TC_CNT,val)
+#define bfin_read_DMAC0_TC_PER()             bfin_read16(DMAC0_TC_PER)
+#define bfin_write_DMAC0_TC_PER(val)         bfin_write16(DMAC0_TC_PER,val)
+#define bfin_read_DMAC0_TC_CNT()             bfin_read16(DMAC0_TC_CNT)
+#define bfin_write_DMAC0_TC_CNT(val)         bfin_write16(DMAC0_TC_CNT,val)
+#define bfin_read_DMAC1_TC_PER()             bfin_read16(DMAC1_TC_PER)
+#define bfin_write_DMAC1_TC_PER(val)         bfin_write16(DMAC1_TC_PER,val)
+#define bfin_read_DMAC1_TC_CNT()             bfin_read16(DMAC1_TC_CNT)
+#define bfin_write_DMAC1_TC_CNT(val)         bfin_write16(DMAC1_TC_CNT,val)
 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
 #define bfin_read_DMA1_0_CONFIG()            bfin_read16(DMA1_0_CONFIG)
 #define bfin_write_DMA1_0_CONFIG(val)        bfin_write16(DMA1_0_CONFIG,val)
@@ -845,110 +837,110 @@
 #define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
 #define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA1_D0_CONFIG()          bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val)      bfin_write16(MDMA1_D0_CONFIG,val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_START_ADDR()      bfin_read32(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val)  bfin_write32(MDMA1_D0_START_ADDR,val)
-#define bfin_read_MDMA1_D0_X_COUNT()         bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val)     bfin_write16(MDMA1_D0_X_COUNT,val)
-#define bfin_read_MDMA1_D0_Y_COUNT()         bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val)     bfin_write16(MDMA1_D0_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_X_MODIFY()        bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val)    bfin_write16(MDMA1_D0_X_MODIFY,val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()        bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val)    bfin_write16(MDMA1_D0_Y_MODIFY,val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_read32(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_CURR_ADDR()       bfin_read32(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_write32(MDMA1_D0_CURR_ADDR,val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT()    bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT()    bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS()      bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val)  bfin_write16(MDMA1_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()  bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S0_CONFIG()          bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val)      bfin_write16(MDMA1_S0_CONFIG,val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_START_ADDR()      bfin_read32(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val)  bfin_write32(MDMA1_S0_START_ADDR,val)
-#define bfin_read_MDMA1_S0_X_COUNT()         bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val)     bfin_write16(MDMA1_S0_X_COUNT,val)
-#define bfin_read_MDMA1_S0_Y_COUNT()         bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val)     bfin_write16(MDMA1_S0_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_X_MODIFY()        bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val)    bfin_write16(MDMA1_S0_X_MODIFY,val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()        bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val)    bfin_write16(MDMA1_S0_Y_MODIFY,val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_read32(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_CURR_ADDR()       bfin_read32(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_write32(MDMA1_S0_CURR_ADDR,val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT()    bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT()    bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS()      bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val)  bfin_write16(MDMA1_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()  bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_D1_CONFIG()          bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val)      bfin_write16(MDMA1_D1_CONFIG,val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_START_ADDR()      bfin_read32(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val)  bfin_write32(MDMA1_D1_START_ADDR,val)
-#define bfin_read_MDMA1_D1_X_COUNT()         bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val)     bfin_write16(MDMA1_D1_X_COUNT,val)
-#define bfin_read_MDMA1_D1_Y_COUNT()         bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val)     bfin_write16(MDMA1_D1_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_X_MODIFY()        bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val)    bfin_write16(MDMA1_D1_X_MODIFY,val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()        bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val)    bfin_write16(MDMA1_D1_Y_MODIFY,val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_read32(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_CURR_ADDR()       bfin_read32(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_write32(MDMA1_D1_CURR_ADDR,val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT()    bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT()    bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS()      bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val)  bfin_write16(MDMA1_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()  bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S1_CONFIG()          bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val)      bfin_write16(MDMA1_S1_CONFIG,val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_START_ADDR()      bfin_read32(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val)  bfin_write32(MDMA1_S1_START_ADDR,val)
-#define bfin_read_MDMA1_S1_X_COUNT()         bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val)     bfin_write16(MDMA1_S1_X_COUNT,val)
-#define bfin_read_MDMA1_S1_Y_COUNT()         bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val)     bfin_write16(MDMA1_S1_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_X_MODIFY()        bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val)    bfin_write16(MDMA1_S1_X_MODIFY,val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()        bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val)    bfin_write16(MDMA1_S1_Y_MODIFY,val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_read32(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_CURR_ADDR()       bfin_read32(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_write32(MDMA1_S1_CURR_ADDR,val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT()    bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT()    bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS()      bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val)  bfin_write16(MDMA1_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()  bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D2_CONFIG()          bfin_read16(MDMA_D2_CONFIG)
+#define bfin_write_MDMA_D2_CONFIG(val)      bfin_write16(MDMA_D2_CONFIG,val)
+#define bfin_read_MDMA_D2_NEXT_DESC_PTR()   bfin_read32(MDMA_D2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D2_START_ADDR()      bfin_read32(MDMA_D2_START_ADDR)
+#define bfin_write_MDMA_D2_START_ADDR(val)  bfin_write32(MDMA_D2_START_ADDR,val)
+#define bfin_read_MDMA_D2_X_COUNT()         bfin_read16(MDMA_D2_X_COUNT)
+#define bfin_write_MDMA_D2_X_COUNT(val)     bfin_write16(MDMA_D2_X_COUNT,val)
+#define bfin_read_MDMA_D2_Y_COUNT()         bfin_read16(MDMA_D2_Y_COUNT)
+#define bfin_write_MDMA_D2_Y_COUNT(val)     bfin_write16(MDMA_D2_Y_COUNT,val)
+#define bfin_read_MDMA_D2_X_MODIFY()        bfin_read16(MDMA_D2_X_MODIFY)
+#define bfin_write_MDMA_D2_X_MODIFY(val)    bfin_write16(MDMA_D2_X_MODIFY,val)
+#define bfin_read_MDMA_D2_Y_MODIFY()        bfin_read16(MDMA_D2_Y_MODIFY)
+#define bfin_write_MDMA_D2_Y_MODIFY(val)    bfin_write16(MDMA_D2_Y_MODIFY,val)
+#define bfin_read_MDMA_D2_CURR_DESC_PTR()   bfin_read32(MDMA_D2_CURR_DESC_PTR)
+#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D2_CURR_ADDR()       bfin_read32(MDMA_D2_CURR_ADDR)
+#define bfin_write_MDMA_D2_CURR_ADDR(val)   bfin_write32(MDMA_D2_CURR_ADDR,val)
+#define bfin_read_MDMA_D2_CURR_X_COUNT()    bfin_read16(MDMA_D2_CURR_X_COUNT)
+#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D2_CURR_Y_COUNT()    bfin_read16(MDMA_D2_CURR_Y_COUNT)
+#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D2_IRQ_STATUS()      bfin_read16(MDMA_D2_IRQ_STATUS)
+#define bfin_write_MDMA_D2_IRQ_STATUS(val)  bfin_write16(MDMA_D2_IRQ_STATUS,val)
+#define bfin_read_MDMA_D2_PERIPHERAL_MAP()  bfin_read16(MDMA_D2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S2_CONFIG()          bfin_read16(MDMA_S2_CONFIG)
+#define bfin_write_MDMA_S2_CONFIG(val)      bfin_write16(MDMA_S2_CONFIG,val)
+#define bfin_read_MDMA_S2_NEXT_DESC_PTR()   bfin_read32(MDMA_S2_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S2_START_ADDR()      bfin_read32(MDMA_S2_START_ADDR)
+#define bfin_write_MDMA_S2_START_ADDR(val)  bfin_write32(MDMA_S2_START_ADDR,val)
+#define bfin_read_MDMA_S2_X_COUNT()         bfin_read16(MDMA_S2_X_COUNT)
+#define bfin_write_MDMA_S2_X_COUNT(val)     bfin_write16(MDMA_S2_X_COUNT,val)
+#define bfin_read_MDMA_S2_Y_COUNT()         bfin_read16(MDMA_S2_Y_COUNT)
+#define bfin_write_MDMA_S2_Y_COUNT(val)     bfin_write16(MDMA_S2_Y_COUNT,val)
+#define bfin_read_MDMA_S2_X_MODIFY()        bfin_read16(MDMA_S2_X_MODIFY)
+#define bfin_write_MDMA_S2_X_MODIFY(val)    bfin_write16(MDMA_S2_X_MODIFY,val)
+#define bfin_read_MDMA_S2_Y_MODIFY()        bfin_read16(MDMA_S2_Y_MODIFY)
+#define bfin_write_MDMA_S2_Y_MODIFY(val)    bfin_write16(MDMA_S2_Y_MODIFY,val)
+#define bfin_read_MDMA_S2_CURR_DESC_PTR()   bfin_read32(MDMA_S2_CURR_DESC_PTR)
+#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S2_CURR_ADDR()       bfin_read32(MDMA_S2_CURR_ADDR)
+#define bfin_write_MDMA_S2_CURR_ADDR(val)   bfin_write32(MDMA_S2_CURR_ADDR,val)
+#define bfin_read_MDMA_S2_CURR_X_COUNT()    bfin_read16(MDMA_S2_CURR_X_COUNT)
+#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S2_CURR_Y_COUNT()    bfin_read16(MDMA_S2_CURR_Y_COUNT)
+#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S2_IRQ_STATUS()      bfin_read16(MDMA_S2_IRQ_STATUS)
+#define bfin_write_MDMA_S2_IRQ_STATUS(val)  bfin_write16(MDMA_S2_IRQ_STATUS,val)
+#define bfin_read_MDMA_S2_PERIPHERAL_MAP()  bfin_read16(MDMA_S2_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D3_CONFIG()          bfin_read16(MDMA_D3_CONFIG)
+#define bfin_write_MDMA_D3_CONFIG(val)      bfin_write16(MDMA_D3_CONFIG,val)
+#define bfin_read_MDMA_D3_NEXT_DESC_PTR()   bfin_read32(MDMA_D3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D3_START_ADDR()      bfin_read32(MDMA_D3_START_ADDR)
+#define bfin_write_MDMA_D3_START_ADDR(val)  bfin_write32(MDMA_D3_START_ADDR,val)
+#define bfin_read_MDMA_D3_X_COUNT()         bfin_read16(MDMA_D3_X_COUNT)
+#define bfin_write_MDMA_D3_X_COUNT(val)     bfin_write16(MDMA_D3_X_COUNT,val)
+#define bfin_read_MDMA_D3_Y_COUNT()         bfin_read16(MDMA_D3_Y_COUNT)
+#define bfin_write_MDMA_D3_Y_COUNT(val)     bfin_write16(MDMA_D3_Y_COUNT,val)
+#define bfin_read_MDMA_D3_X_MODIFY()        bfin_read16(MDMA_D3_X_MODIFY)
+#define bfin_write_MDMA_D3_X_MODIFY(val)    bfin_write16(MDMA_D3_X_MODIFY,val)
+#define bfin_read_MDMA_D3_Y_MODIFY()        bfin_read16(MDMA_D3_Y_MODIFY)
+#define bfin_write_MDMA_D3_Y_MODIFY(val)    bfin_write16(MDMA_D3_Y_MODIFY,val)
+#define bfin_read_MDMA_D3_CURR_DESC_PTR()   bfin_read32(MDMA_D3_CURR_DESC_PTR)
+#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D3_CURR_ADDR()       bfin_read32(MDMA_D3_CURR_ADDR)
+#define bfin_write_MDMA_D3_CURR_ADDR(val)   bfin_write32(MDMA_D3_CURR_ADDR,val)
+#define bfin_read_MDMA_D3_CURR_X_COUNT()    bfin_read16(MDMA_D3_CURR_X_COUNT)
+#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D3_CURR_Y_COUNT()    bfin_read16(MDMA_D3_CURR_Y_COUNT)
+#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D3_IRQ_STATUS()      bfin_read16(MDMA_D3_IRQ_STATUS)
+#define bfin_write_MDMA_D3_IRQ_STATUS(val)  bfin_write16(MDMA_D3_IRQ_STATUS,val)
+#define bfin_read_MDMA_D3_PERIPHERAL_MAP()  bfin_read16(MDMA_D3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S3_CONFIG()          bfin_read16(MDMA_S3_CONFIG)
+#define bfin_write_MDMA_S3_CONFIG(val)      bfin_write16(MDMA_S3_CONFIG,val)
+#define bfin_read_MDMA_S3_NEXT_DESC_PTR()   bfin_read32(MDMA_S3_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S3_START_ADDR()      bfin_read32(MDMA_S3_START_ADDR)
+#define bfin_write_MDMA_S3_START_ADDR(val)  bfin_write32(MDMA_S3_START_ADDR,val)
+#define bfin_read_MDMA_S3_X_COUNT()         bfin_read16(MDMA_S3_X_COUNT)
+#define bfin_write_MDMA_S3_X_COUNT(val)     bfin_write16(MDMA_S3_X_COUNT,val)
+#define bfin_read_MDMA_S3_Y_COUNT()         bfin_read16(MDMA_S3_Y_COUNT)
+#define bfin_write_MDMA_S3_Y_COUNT(val)     bfin_write16(MDMA_S3_Y_COUNT,val)
+#define bfin_read_MDMA_S3_X_MODIFY()        bfin_read16(MDMA_S3_X_MODIFY)
+#define bfin_write_MDMA_S3_X_MODIFY(val)    bfin_write16(MDMA_S3_X_MODIFY,val)
+#define bfin_read_MDMA_S3_Y_MODIFY()        bfin_read16(MDMA_S3_Y_MODIFY)
+#define bfin_write_MDMA_S3_Y_MODIFY(val)    bfin_write16(MDMA_S3_Y_MODIFY,val)
+#define bfin_read_MDMA_S3_CURR_DESC_PTR()   bfin_read32(MDMA_S3_CURR_DESC_PTR)
+#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S3_CURR_ADDR()       bfin_read32(MDMA_S3_CURR_ADDR)
+#define bfin_write_MDMA_S3_CURR_ADDR(val)   bfin_write32(MDMA_S3_CURR_ADDR,val)
+#define bfin_read_MDMA_S3_CURR_X_COUNT()    bfin_read16(MDMA_S3_CURR_X_COUNT)
+#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S3_CURR_Y_COUNT()    bfin_read16(MDMA_S3_CURR_Y_COUNT)
+#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S3_IRQ_STATUS()      bfin_read16(MDMA_S3_IRQ_STATUS)
+#define bfin_write_MDMA_S3_IRQ_STATUS(val)  bfin_write16(MDMA_S3_IRQ_STATUS,val)
+#define bfin_read_MDMA_S3_PERIPHERAL_MAP()  bfin_read16(MDMA_S3_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP,val)
 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
 #define bfin_read_DMA2_0_CONFIG()            bfin_read16(DMA2_0_CONFIG)
 #define bfin_write_DMA2_0_CONFIG(val)        bfin_write16(DMA2_0_CONFIG,val)
@@ -1263,110 +1255,110 @@
 #define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
 #define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA2_D0_CONFIG()          bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val)      bfin_write16(MDMA2_D0_CONFIG,val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_START_ADDR()      bfin_read32(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val)  bfin_write32(MDMA2_D0_START_ADDR,val)
-#define bfin_read_MDMA2_D0_X_COUNT()         bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val)     bfin_write16(MDMA2_D0_X_COUNT,val)
-#define bfin_read_MDMA2_D0_Y_COUNT()         bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val)     bfin_write16(MDMA2_D0_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_X_MODIFY()        bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val)    bfin_write16(MDMA2_D0_X_MODIFY,val)
-#define bfin_read_MDMA2_D0_Y_MODIFY()        bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val)    bfin_write16(MDMA2_D0_Y_MODIFY,val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_read32(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_CURR_ADDR()       bfin_read32(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_write32(MDMA2_D0_CURR_ADDR,val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT()    bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT()    bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS()      bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val)  bfin_write16(MDMA2_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()  bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S0_CONFIG()          bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val)      bfin_write16(MDMA2_S0_CONFIG,val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_START_ADDR()      bfin_read32(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val)  bfin_write32(MDMA2_S0_START_ADDR,val)
-#define bfin_read_MDMA2_S0_X_COUNT()         bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val)     bfin_write16(MDMA2_S0_X_COUNT,val)
-#define bfin_read_MDMA2_S0_Y_COUNT()         bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val)     bfin_write16(MDMA2_S0_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_X_MODIFY()        bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val)    bfin_write16(MDMA2_S0_X_MODIFY,val)
-#define bfin_read_MDMA2_S0_Y_MODIFY()        bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val)    bfin_write16(MDMA2_S0_Y_MODIFY,val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_read32(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_CURR_ADDR()       bfin_read32(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_write32(MDMA2_S0_CURR_ADDR,val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT()    bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT()    bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS()      bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val)  bfin_write16(MDMA2_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()  bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_D1_CONFIG()          bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val)      bfin_write16(MDMA2_D1_CONFIG,val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_START_ADDR()      bfin_read32(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val)  bfin_write32(MDMA2_D1_START_ADDR,val)
-#define bfin_read_MDMA2_D1_X_COUNT()         bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val)     bfin_write16(MDMA2_D1_X_COUNT,val)
-#define bfin_read_MDMA2_D1_Y_COUNT()         bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val)     bfin_write16(MDMA2_D1_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_X_MODIFY()        bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val)    bfin_write16(MDMA2_D1_X_MODIFY,val)
-#define bfin_read_MDMA2_D1_Y_MODIFY()        bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val)    bfin_write16(MDMA2_D1_Y_MODIFY,val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_read32(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_CURR_ADDR()       bfin_read32(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_write32(MDMA2_D1_CURR_ADDR,val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT()    bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT()    bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS()      bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val)  bfin_write16(MDMA2_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()  bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S1_CONFIG()          bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val)      bfin_write16(MDMA2_S1_CONFIG,val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_START_ADDR()      bfin_read32(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val)  bfin_write32(MDMA2_S1_START_ADDR,val)
-#define bfin_read_MDMA2_S1_X_COUNT()         bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val)     bfin_write16(MDMA2_S1_X_COUNT,val)
-#define bfin_read_MDMA2_S1_Y_COUNT()         bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val)     bfin_write16(MDMA2_S1_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_X_MODIFY()        bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val)    bfin_write16(MDMA2_S1_X_MODIFY,val)
-#define bfin_read_MDMA2_S1_Y_MODIFY()        bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val)    bfin_write16(MDMA2_S1_Y_MODIFY,val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_read32(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_CURR_ADDR()       bfin_read32(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_write32(MDMA2_S1_CURR_ADDR,val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT()    bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT()    bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS()      bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val)  bfin_write16(MDMA2_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()  bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D0_CONFIG()          bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)      bfin_write16(MDMA_D0_CONFIG,val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()   bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D0_START_ADDR()      bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)  bfin_write32(MDMA_D0_START_ADDR,val)
+#define bfin_read_MDMA_D0_X_COUNT()         bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)     bfin_write16(MDMA_D0_X_COUNT,val)
+#define bfin_read_MDMA_D0_Y_COUNT()         bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)     bfin_write16(MDMA_D0_Y_COUNT,val)
+#define bfin_read_MDMA_D0_X_MODIFY()        bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)    bfin_write16(MDMA_D0_X_MODIFY,val)
+#define bfin_read_MDMA_D0_Y_MODIFY()        bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)    bfin_write16(MDMA_D0_Y_MODIFY,val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()   bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D0_CURR_ADDR()       bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)   bfin_write32(MDMA_D0_CURR_ADDR,val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()    bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()    bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()      bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)  bfin_write16(MDMA_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()  bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S0_CONFIG()          bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)      bfin_write16(MDMA_S0_CONFIG,val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()   bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S0_START_ADDR()      bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)  bfin_write32(MDMA_S0_START_ADDR,val)
+#define bfin_read_MDMA_S0_X_COUNT()         bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)     bfin_write16(MDMA_S0_X_COUNT,val)
+#define bfin_read_MDMA_S0_Y_COUNT()         bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)     bfin_write16(MDMA_S0_Y_COUNT,val)
+#define bfin_read_MDMA_S0_X_MODIFY()        bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)    bfin_write16(MDMA_S0_X_MODIFY,val)
+#define bfin_read_MDMA_S0_Y_MODIFY()        bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)    bfin_write16(MDMA_S0_Y_MODIFY,val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()   bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S0_CURR_ADDR()       bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)   bfin_write32(MDMA_S0_CURR_ADDR,val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()    bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()    bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()      bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)  bfin_write16(MDMA_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()  bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_D1_CONFIG()          bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)      bfin_write16(MDMA_D1_CONFIG,val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()   bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D1_START_ADDR()      bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)  bfin_write32(MDMA_D1_START_ADDR,val)
+#define bfin_read_MDMA_D1_X_COUNT()         bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)     bfin_write16(MDMA_D1_X_COUNT,val)
+#define bfin_read_MDMA_D1_Y_COUNT()         bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)     bfin_write16(MDMA_D1_Y_COUNT,val)
+#define bfin_read_MDMA_D1_X_MODIFY()        bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)    bfin_write16(MDMA_D1_X_MODIFY,val)
+#define bfin_read_MDMA_D1_Y_MODIFY()        bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)    bfin_write16(MDMA_D1_Y_MODIFY,val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()   bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D1_CURR_ADDR()       bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)   bfin_write32(MDMA_D1_CURR_ADDR,val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()    bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()    bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()      bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)  bfin_write16(MDMA_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()  bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA_S1_CONFIG()          bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)      bfin_write16(MDMA_S1_CONFIG,val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()   bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S1_START_ADDR()      bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)  bfin_write32(MDMA_S1_START_ADDR,val)
+#define bfin_read_MDMA_S1_X_COUNT()         bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)     bfin_write16(MDMA_S1_X_COUNT,val)
+#define bfin_read_MDMA_S1_Y_COUNT()         bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)     bfin_write16(MDMA_S1_Y_COUNT,val)
+#define bfin_read_MDMA_S1_X_MODIFY()        bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)    bfin_write16(MDMA_S1_X_MODIFY,val)
+#define bfin_read_MDMA_S1_Y_MODIFY()        bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)    bfin_write16(MDMA_S1_Y_MODIFY,val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()   bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S1_CURR_ADDR()       bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)   bfin_write32(MDMA_S1_CURR_ADDR,val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()    bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()    bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()      bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)  bfin_write16(MDMA_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()  bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
 #define bfin_read_IMDMA_D0_CONFIG()          bfin_read16(IMDMA_D0_CONFIG)
 #define bfin_write_IMDMA_D0_CONFIG(val)      bfin_write16(IMDMA_D0_CONFIG,val)
@@ -1465,65 +1457,4 @@
 #define bfin_read_IMDMA_S1_IRQ_STATUS()      bfin_read16(IMDMA_S1_IRQ_STATUS)
 #define bfin_write_IMDMA_S1_IRQ_STATUS(val)  bfin_write16(IMDMA_S1_IRQ_STATUS,val)
 
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA1_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA1_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA1_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA1_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA1_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA1_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA1_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA1_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA1_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA1_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA1_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA1_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA1_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
-
-#define bfin_read_MDMA_S1_CONFIG()  bfin_read_MDMA1_S1_CONFIG()
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write_MDMA1_S1_CONFIG(val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()  bfin_read_MDMA1_S1_IRQ_STATUS()
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write_MDMA1_S1_IRQ_STATUS(val)
-#define bfin_read_MDMA_S1_X_MODIFY()  bfin_read_MDMA1_S1_X_MODIFY()
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write_MDMA1_S1_X_MODIFY(val)
-#define bfin_read_MDMA_S1_Y_MODIFY()  bfin_read_MDMA1_S1_Y_MODIFY()
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write_MDMA1_S1_Y_MODIFY(val)
-#define bfin_read_MDMA_S1_X_COUNT()  bfin_read_MDMA1_S1_X_COUNT()
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write_MDMA1_S1_X_COUNT(val)
-#define bfin_read_MDMA_S1_Y_COUNT()  bfin_read_MDMA1_S1_Y_COUNT()
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write_MDMA1_S1_Y_COUNT(val)
-#define bfin_read_MDMA_S1_START_ADDR()  bfin_read_MDMA1_S1_START_ADDR()
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write_MDMA1_S1_START_ADDR(val)
-#define bfin_read_MDMA_D1_CONFIG()  bfin_read_MDMA1_D1_CONFIG()
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write_MDMA1_D1_CONFIG(val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()  bfin_read_MDMA1_D1_IRQ_STATUS()
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write_MDMA1_D1_IRQ_STATUS(val)
-#define bfin_read_MDMA_D1_X_MODIFY()  bfin_read_MDMA1_D1_X_MODIFY()
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write_MDMA1_D1_X_MODIFY(val)
-#define bfin_read_MDMA_D1_Y_MODIFY()  bfin_read_MDMA1_D1_Y_MODIFY()
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write_MDMA1_D1_Y_MODIFY(val)
-#define bfin_read_MDMA_D1_X_COUNT()  bfin_read_MDMA1_D1_X_COUNT()
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write_MDMA1_D1_X_COUNT(val)
-#define bfin_read_MDMA_D1_Y_COUNT()  bfin_read_MDMA1_D1_Y_COUNT()
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write_MDMA1_D1_Y_COUNT(val)
-#define bfin_read_MDMA_D1_START_ADDR()  bfin_read_MDMA1_D1_START_ADDR()
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write_MDMA1_D1_START_ADDR(val)
-
-/* These need to be last due to the cdef/linux inter-dependencies */
-#include <asm/irq.h>
-
 #endif                          /* _CDEF_BF561_H */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 79e048d452e0..71e805ea74e5 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1,18 +1,11 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _DEF_BF561_H
 #define _DEF_BF561_H
-/*
-#if !defined(__ADSPBF561__)
-#warning defBF561.h should only be included for BF561 chip.
-#endif
-*/
-/* include all Core registers and bit definitions */
-#include <asm/def_LPBlackfin.h>
 
 /*********************************************************************************** */
 /* System MMR Register Map */
@@ -311,10 +304,10 @@
 #define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
 
 /*DMA traffic control registers */
-#define DMA1_TC_PER  0xFFC01B0C /* Traffic control periods */
-#define DMA1_TC_CNT  0xFFC01B10 /* Traffic control current counts */
-#define DMA2_TC_PER  0xFFC00B0C /* Traffic control periods */
-#define DMA2_TC_CNT  0xFFC00B10 /* Traffic control current counts        */
+#define DMAC0_TC_PER  0xFFC00B0C        /* Traffic control periods */
+#define DMAC0_TC_CNT  0xFFC00B10        /* Traffic control current counts        */
+#define DMAC1_TC_PER  0xFFC01B0C        /* Traffic control periods */
+#define DMAC1_TC_CNT  0xFFC01B10        /* Traffic control current counts */
 
 /* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
 #define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
@@ -486,61 +479,61 @@
 #define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
 
 /* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA1_D0_CONFIG 0xFFC01F08      /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00       /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D0_START_ADDR 0xFFC01F04  /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA1_D0_X_COUNT 0xFFC01F10     /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA1_D0_Y_COUNT 0xFFC01F18     /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA1_D0_X_MODIFY 0xFFC01F14    /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C    /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20       /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24   /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30        /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38        /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28  /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA1_S0_CONFIG 0xFFC01F48      /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40       /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA1_S0_START_ADDR 0xFFC01F44  /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA1_S0_X_COUNT 0xFFC01F50     /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA1_S0_Y_COUNT 0xFFC01F58     /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA1_S0_X_MODIFY 0xFFC01F54    /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C    /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60       /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64   /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70        /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78        /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68  /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA1_D1_CONFIG 0xFFC01F88      /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80       /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D1_START_ADDR 0xFFC01F84  /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA1_D1_X_COUNT 0xFFC01F90     /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA1_D1_Y_COUNT 0xFFC01F98     /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA1_D1_X_MODIFY 0xFFC01F94    /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C    /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0       /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4   /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0        /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8        /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8  /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA1_S1_CONFIG 0xFFC01FC8      /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0       /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA1_S1_START_ADDR 0xFFC01FC4  /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA1_S1_X_COUNT 0xFFC01FD0     /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8     /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4    /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC    /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0       /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4   /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0        /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8        /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8  /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /*MemDMA1 Stream 1 Source Peripheral Map */
+#define MDMA_D2_CONFIG 0xFFC01F08       /*MemDMA1 Stream 0 Destination Configuration */
+#define MDMA_D2_NEXT_DESC_PTR 0xFFC01F00        /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D2_START_ADDR 0xFFC01F04   /*MemDMA1 Stream 0 Destination Start Address */
+#define MDMA_D2_X_COUNT 0xFFC01F10      /*MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA_D2_Y_COUNT 0xFFC01F18      /*MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA_D2_X_MODIFY 0xFFC01F14     /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D2_Y_MODIFY 0xFFC01F1C     /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D2_CURR_DESC_PTR 0xFFC01F20        /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D2_CURR_ADDR 0xFFC01F24    /*MemDMA1 Stream 0 Destination Current Address */
+#define MDMA_D2_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA_D2_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA_D2_IRQ_STATUS 0xFFC01F28   /*MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA_D2_PERIPHERAL_MAP 0xFFC01F2C       /*MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA_S2_CONFIG 0xFFC01F48       /*MemDMA1 Stream 0 Source Configuration */
+#define MDMA_S2_NEXT_DESC_PTR 0xFFC01F40        /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S2_START_ADDR 0xFFC01F44   /*MemDMA1 Stream 0 Source Start Address */
+#define MDMA_S2_X_COUNT 0xFFC01F50      /*MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA_S2_Y_COUNT 0xFFC01F58      /*MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA_S2_X_MODIFY 0xFFC01F54     /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA_S2_Y_MODIFY 0xFFC01F5C     /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA_S2_CURR_DESC_PTR 0xFFC01F60        /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S2_CURR_ADDR 0xFFC01F64    /*MemDMA1 Stream 0 Source Current Address */
+#define MDMA_S2_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA_S2_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA_S2_IRQ_STATUS 0xFFC01F68   /*MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA_S2_PERIPHERAL_MAP 0xFFC01F6C       /*MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA_D3_CONFIG 0xFFC01F88       /*MemDMA1 Stream 1 Destination Configuration */
+#define MDMA_D3_NEXT_DESC_PTR 0xFFC01F80        /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D3_START_ADDR 0xFFC01F84   /*MemDMA1 Stream 1 Destination Start Address */
+#define MDMA_D3_X_COUNT 0xFFC01F90      /*MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA_D3_Y_COUNT 0xFFC01F98      /*MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA_D3_X_MODIFY 0xFFC01F94     /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D3_Y_MODIFY 0xFFC01F9C     /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D3_CURR_DESC_PTR 0xFFC01FA0        /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA_D3_CURR_ADDR 0xFFC01FA4    /*MemDMA1 Stream 1 Dest Current Address */
+#define MDMA_D3_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA_D3_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA_D3_IRQ_STATUS 0xFFC01FA8   /*MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA_D3_PERIPHERAL_MAP 0xFFC01FAC       /*MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA_S3_CONFIG 0xFFC01FC8       /*MemDMA1 Stream 1 Source Configuration */
+#define MDMA_S3_NEXT_DESC_PTR 0xFFC01FC0        /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S3_START_ADDR 0xFFC01FC4   /*MemDMA1 Stream 1 Source Start Address */
+#define MDMA_S3_X_COUNT 0xFFC01FD0      /*MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA_S3_Y_COUNT 0xFFC01FD8      /*MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA_S3_X_MODIFY 0xFFC01FD4     /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA_S3_Y_MODIFY 0xFFC01FDC     /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S3_CURR_DESC_PTR 0xFFC01FE0        /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S3_CURR_ADDR 0xFFC01FE4    /*MemDMA1 Stream 1 Source Current Address */
+#define MDMA_S3_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S3_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S3_IRQ_STATUS 0xFFC01FE8   /*MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA_S3_PERIPHERAL_MAP 0xFFC01FEC       /*MemDMA1 Stream 1 Source Peripheral Map */
 
 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
 #define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
@@ -712,117 +705,61 @@
 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
 
 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA2_D0_CONFIG 0xFFC00F08      /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00       /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D0_START_ADDR 0xFFC00F04  /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA2_D0_X_COUNT 0xFFC00F10     /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA2_D0_Y_COUNT 0xFFC00F18     /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA2_D0_X_MODIFY 0xFFC00F14    /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C    /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20       /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24   /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30        /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38        /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28  /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C      /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA2_S0_CONFIG 0xFFC00F48      /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40       /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA2_S0_START_ADDR 0xFFC00F44  /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA2_S0_X_COUNT 0xFFC00F50     /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA2_S0_Y_COUNT 0xFFC00F58     /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA2_S0_X_MODIFY 0xFFC00F54    /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C    /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60       /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64   /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70        /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78        /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68  /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C      /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA2_D1_CONFIG 0xFFC00F88      /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80       /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D1_START_ADDR 0xFFC00F84  /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA2_D1_X_COUNT 0xFFC00F90     /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA2_D1_Y_COUNT 0xFFC00F98     /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA2_D1_X_MODIFY 0xFFC00F94    /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C    /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0       /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4   /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0        /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8        /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8  /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC      /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA2_S1_CONFIG 0xFFC00FC8      /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0       /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA2_S1_START_ADDR 0xFFC00FC4  /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA2_S1_X_COUNT 0xFFC00FD0     /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8     /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4    /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC    /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0       /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4   /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0        /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8        /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8  /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC      /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-#define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
-#define MDMA_D0_START_ADDR MDMA1_D0_START_ADDR
-#define MDMA_D0_CONFIG MDMA1_D0_CONFIG
-#define MDMA_D0_X_COUNT MDMA1_D0_X_COUNT
-#define MDMA_D0_X_MODIFY MDMA1_D0_X_MODIFY
-#define MDMA_D0_Y_COUNT MDMA1_D0_Y_COUNT
-#define MDMA_D0_Y_MODIFY MDMA1_D0_Y_MODIFY
-#define MDMA_D0_CURR_DESC_PTR MDMA1_D0_CURR_DESC_PTR
-#define MDMA_D0_CURR_ADDR MDMA1_D0_CURR_ADDR
-#define MDMA_D0_IRQ_STATUS MDMA1_D0_IRQ_STATUS
-#define MDMA_D0_PERIPHERAL_MAP MDMA1_D0_PERIPHERAL_MAP
-#define MDMA_D0_CURR_X_COUNT MDMA1_D0_CURR_X_COUNT
-#define MDMA_D0_CURR_Y_COUNT MDMA1_D0_CURR_Y_COUNT
-
-#define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
-#define MDMA_S0_START_ADDR MDMA1_S0_START_ADDR
-#define MDMA_S0_CONFIG MDMA1_S0_CONFIG
-#define MDMA_S0_X_COUNT MDMA1_S0_X_COUNT
-#define MDMA_S0_X_MODIFY MDMA1_S0_X_MODIFY
-#define MDMA_S0_Y_COUNT MDMA1_S0_Y_COUNT
-#define MDMA_S0_Y_MODIFY MDMA1_S0_Y_MODIFY
-#define MDMA_S0_CURR_DESC_PTR MDMA1_S0_CURR_DESC_PTR
-#define MDMA_S0_CURR_ADDR MDMA1_S0_CURR_ADDR
-#define MDMA_S0_IRQ_STATUS MDMA1_S0_IRQ_STATUS
-#define MDMA_S0_PERIPHERAL_MAP MDMA1_S0_PERIPHERAL_MAP
-#define MDMA_S0_CURR_X_COUNT MDMA1_S0_CURR_X_COUNT
-#define MDMA_S0_CURR_Y_COUNT MDMA1_S0_CURR_Y_COUNT
-
-#define MDMA_D1_NEXT_DESC_PTR MDMA1_D1_NEXT_DESC_PTR
-#define MDMA_D1_START_ADDR MDMA1_D1_START_ADDR
-#define MDMA_D1_CONFIG MDMA1_D1_CONFIG
-#define MDMA_D1_X_COUNT MDMA1_D1_X_COUNT
-#define MDMA_D1_X_MODIFY MDMA1_D1_X_MODIFY
-#define MDMA_D1_Y_COUNT MDMA1_D1_Y_COUNT
-#define MDMA_D1_Y_MODIFY MDMA1_D1_Y_MODIFY
-#define MDMA_D1_CURR_DESC_PTR MDMA1_D1_CURR_DESC_PTR
-#define MDMA_D1_CURR_ADDR MDMA1_D1_CURR_ADDR
-#define MDMA_D1_IRQ_STATUS MDMA1_D1_IRQ_STATUS
-#define MDMA_D1_PERIPHERAL_MAP MDMA1_D1_PERIPHERAL_MAP
-#define MDMA_D1_CURR_X_COUNT MDMA1_D1_CURR_X_COUNT
-#define MDMA_D1_CURR_Y_COUNT MDMA1_D1_CURR_Y_COUNT
-
-#define MDMA_S1_NEXT_DESC_PTR MDMA1_S1_NEXT_DESC_PTR
-#define MDMA_S1_START_ADDR MDMA1_S1_START_ADDR
-#define MDMA_S1_CONFIG MDMA1_S1_CONFIG
-#define MDMA_S1_X_COUNT MDMA1_S1_X_COUNT
-#define MDMA_S1_X_MODIFY MDMA1_S1_X_MODIFY
-#define MDMA_S1_Y_COUNT MDMA1_S1_Y_COUNT
-#define MDMA_S1_Y_MODIFY MDMA1_S1_Y_MODIFY
-#define MDMA_S1_CURR_DESC_PTR MDMA1_S1_CURR_DESC_PTR
-#define MDMA_S1_CURR_ADDR MDMA1_S1_CURR_ADDR
-#define MDMA_S1_IRQ_STATUS MDMA1_S1_IRQ_STATUS
-#define MDMA_S1_PERIPHERAL_MAP MDMA1_S1_PERIPHERAL_MAP
-#define MDMA_S1_CURR_X_COUNT MDMA1_S1_CURR_X_COUNT
-#define MDMA_S1_CURR_Y_COUNT MDMA1_S1_CURR_Y_COUNT
+#define MDMA_D0_CONFIG 0xFFC00F08       /*MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00        /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA_D0_START_ADDR 0xFFC00F04   /*MemDMA2 Stream 0 Destination Start Address */
+#define MDMA_D0_X_COUNT 0xFFC00F10      /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18      /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14     /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C     /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20        /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24    /*MemDMA2 Stream 0 Destination Current Address */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28   /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C       /*MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA_S0_CONFIG 0xFFC00F48       /*MemDMA2 Stream 0 Source Configuration register */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40        /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA_S0_START_ADDR 0xFFC00F44   /*MemDMA2 Stream 0 Source Start Address */
+#define MDMA_S0_X_COUNT 0xFFC00F50      /*MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58      /*MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54     /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C     /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60        /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64    /*MemDMA2 Stream 0 Source Current Address */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68   /*MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C       /*MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA_D1_CONFIG 0xFFC00F88       /*MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80        /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA_D1_START_ADDR 0xFFC00F84   /*MemDMA2 Stream 1 Destination Start Address */
+#define MDMA_D1_X_COUNT 0xFFC00F90      /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98      /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94     /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C     /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0        /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4    /*MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8   /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC       /*MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA_S1_CONFIG 0xFFC00FC8       /*MemDMA2 Stream 1 Source Configuration register */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0        /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA_S1_START_ADDR 0xFFC00FC4   /*MemDMA2 Stream 1 Source Start Address */
+#define MDMA_S1_X_COUNT 0xFFC00FD0      /*MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8      /*MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4     /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC     /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0        /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4    /*MemDMA2 Stream 1 Source Current Address */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8   /*MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC       /*MemDMA2 Stream 1 Source Peripheral Map register */
 
 /* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
 #define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
@@ -927,83 +864,6 @@
 #define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
 
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
@@ -1230,44 +1090,6 @@
 #define ERR_TYP_P0              0x0E
 #define ERR_TYP_P1              0x0F
 
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
 
 /* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf561/include/mach/gpio.h b/arch/blackfin/mach-bf561/include/mach/gpio.h
index 4f8aa5d08802..57d5eab59faf 100644
--- a/arch/blackfin/mach-bf561/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf561/include/mach/gpio.h
@@ -62,4 +62,6 @@
 #define PORT_FIO1 GPIO_16
 #define PORT_FIO2 GPIO_32
 
+#include <mach-common/ports-f.h>
+
 #endif /* _MACH_GPIO_H_ */
diff --git a/arch/blackfin/mach-bf561/include/mach/mem_map.h b/arch/blackfin/mach-bf561/include/mach/mem_map.h
index 5b96ea549a04..4cc91995f781 100644
--- a/arch/blackfin/mach-bf561/include/mach/mem_map.h
+++ b/arch/blackfin/mach-bf561/include/mach/mem_map.h
@@ -106,7 +106,7 @@
 #define COREA_L1_SCRATCH_START  0xFFB00000
 #define COREB_L1_SCRATCH_START  0xFF700000
 
-#ifdef __ASSEMBLY__
+#ifdef CONFIG_SMP
 
 /*
  * The following macros both return the address of the PDA for the
@@ -121,8 +121,7 @@
  * is allowed to use the specified Dreg for determining the PDA
  * address to be returned into Preg.
  */
-#ifdef CONFIG_SMP
-#define GET_PDA_SAFE(preg)              \
+# define GET_PDA_SAFE(preg)             \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         preg = [preg];                  \
@@ -158,7 +157,7 @@
         preg = [preg];                  \
 4:
 
-#define GET_PDA(preg, dreg)             \
+# define GET_PDA(preg, dreg)            \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         dreg = [preg];                  \
@@ -169,13 +168,17 @@
         preg = [preg];                  \
 1:                                      \
 
-#define GET_CPUID(preg, dreg)           \
+# define GET_CPUID(preg, dreg)          \
         preg.l = lo(DSPID);             \
         preg.h = hi(DSPID);             \
         dreg = [preg];                  \
         dreg = ROT dreg BY -1;          \
         dreg = CC;
 
+# ifndef __ASSEMBLY__
+
+#  include <asm/processor.h>
+
 static inline unsigned long get_l1_scratch_start_cpu(int cpu)
 {
         return cpu ? COREB_L1_SCRATCH_START : COREA_L1_SCRATCH_START;
@@ -210,8 +213,7 @@ static inline unsigned long get_l1_data_b_start(void)
         return get_l1_data_b_start_cpu(blackfin_core_id());
 }
 
+# endif /* __ASSEMBLY__ */
 #endif /* CONFIG_SMP */
 
-#endif /* __ASSEMBLY__ */
-
 #endif
diff --git a/arch/blackfin/mach-bf561/include/mach/pll.h b/arch/blackfin/mach-bf561/include/mach/pll.h
index f2b1fbdb8e72..7977db2f1c12 100644
--- a/arch/blackfin/mach-bf561/include/mach/pll.h
+++ b/arch/blackfin/mach-bf561/include/mach/pll.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2005-2009 Analog Devices Inc.
+ * Copyright 2005-2010 Analog Devices Inc.
  *
  * Licensed under the GPL-2 or later.
  */
@@ -7,57 +7,48 @@
 #ifndef _MACH_PLL_H
 #define _MACH_PLL_H
 
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SMP
+
 #include <asm/blackfin.h>
 #include <asm/irqflags.h>
+#include <mach/irq.h>
+
+#define SUPPLE_0_WAKEUP ((IRQ_SUPPLE_0 - (IRQ_CORETMR + 1)) % 32)
 
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+static inline void
+bfin_iwr_restore(unsigned long iwr0, unsigned long iwr1, unsigned long iwr2)
 {
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        hard_local_irq_restore(flags);
+        unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
+
+        bfin_write32(SIC_IWR0 + SICA_SICB_OFF, iwr0);
+        bfin_write32(SIC_IWR1 + SICA_SICB_OFF, iwr1);
 }
+#define bfin_iwr_restore bfin_iwr_restore
 
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
+static inline void
+bfin_iwr_save(unsigned long niwr0, unsigned long niwr1, unsigned long niwr2,
+              unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
 {
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        flags = hard_local_irq_save();
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        hard_local_irq_restore(flags);
+        unsigned long SICA_SICB_OFF = ((bfin_read_DSPID() & 0xff) ? 0x1000 : 0);
+
+        *iwr0 = bfin_read32(SIC_IWR0 + SICA_SICB_OFF);
+        *iwr1 = bfin_read32(SIC_IWR1 + SICA_SICB_OFF);
+        bfin_iwr_restore(niwr0, niwr1, niwr2);
 }
+#define bfin_iwr_save bfin_iwr_save
+
+static inline void
+bfin_iwr_set_sup0(unsigned long *iwr0, unsigned long *iwr1, unsigned long *iwr2)
+{
+        bfin_iwr_save(0, IWR_ENABLE(SUPPLE_0_WAKEUP), 0, iwr0, iwr1, iwr2);
+}
+
+#endif
+
+#endif
+
+#include <mach-common/pll.h>
 
-#endif /* _MACH_PLL_H */
+#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/smp.h b/arch/blackfin/mach-bf561/include/mach/smp.h
index 2c8c514dd386..346c60589be6 100644
--- a/arch/blackfin/mach-bf561/include/mach/smp.h
+++ b/arch/blackfin/mach-bf561/include/mach/smp.h
@@ -7,6 +7,8 @@
 #ifndef _MACH_BF561_SMP
 #define _MACH_BF561_SMP
 
+/* This header has to stand alone to avoid circular deps */
+
 struct task_struct;
 
 void platform_init_cpus(void);
@@ -17,13 +19,13 @@ int platform_boot_secondary(unsigned int cpu, struct task_struct *idle);
 
 void platform_secondary_init(unsigned int cpu);
 
-void platform_request_ipi(int (*handler)(int, void *));
+void platform_request_ipi(int irq, /*irq_handler_t*/ void *handler);
 
-void platform_send_ipi(cpumask_t callmap);
+void platform_send_ipi(cpumask_t callmap, int irq);
 
-void platform_send_ipi_cpu(unsigned int cpu);
+void platform_send_ipi_cpu(unsigned int cpu, int irq);
 
-void platform_clear_ipi(unsigned int cpu);
+void platform_clear_ipi(unsigned int cpu, int irq);
 
 void bfin_local_timer_setup(void);
 
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index f540ed1257d6..1074a7ef81c7 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -86,12 +86,12 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
 
         spin_lock(&boot_lock);
 
-        if ((bfin_read_SIC_SYSCR() & COREB_SRAM_INIT) == 0) {
+        if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
                 /* CoreB already running, sending ipi to wakeup it */
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
         } else {
                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
-                bfin_write_SIC_SYSCR(bfin_read_SIC_SYSCR() & ~COREB_SRAM_INIT);
+                bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
                 SSYNC();
         }
 
@@ -111,41 +111,46 @@ int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle
                 panic("CPU%u: processor failed to boot\n", cpu);
 }
 
-void __init platform_request_ipi(irq_handler_t handler)
+static const char supple0[] = "IRQ_SUPPLE_0";
+static const char supple1[] = "IRQ_SUPPLE_1";
+void __init platform_request_ipi(int irq, void *handler)
 {
         int ret;
+        const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
 
-        ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
-                          "Supplemental Interrupt0", handler);
+        ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
         if (ret)
-                panic("Cannot request supplemental interrupt 0 for IPI service");
+                panic("Cannot request %s for IPI service", name);
 }
 
-void platform_send_ipi(cpumask_t callmap)
+void platform_send_ipi(cpumask_t callmap, int irq)
 {
         unsigned int cpu;
+        int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 
         for_each_cpu_mask(cpu, callmap) {
                 BUG_ON(cpu >= 2);
                 SSYNC();
-                bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+                bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
                 SSYNC();
         }
 }
 
-void platform_send_ipi_cpu(unsigned int cpu)
+void platform_send_ipi_cpu(unsigned int cpu, int irq)
 {
+        int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
         BUG_ON(cpu >= 2);
         SSYNC();
-        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
         SSYNC();
 }
 
-void platform_clear_ipi(unsigned int cpu)
+void platform_clear_ipi(unsigned int cpu, int irq)
 {
+        int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
         BUG_ON(cpu >= 2);
         SSYNC();
-        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
+        bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
         SSYNC();
 }
 
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 2ca915ee181f..bc08c98d008d 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -615,7 +615,7 @@ ENTRY(_system_call)
 #ifdef CONFIG_IPIPE
         r0 = sp;
         SP += -12;
-        call ___ipipe_syscall_root;
+        pseudo_long_call ___ipipe_syscall_root, p0;
         SP += 12;
         cc = r0 == 1;
         if cc jump .Lsyscall_really_exit;
@@ -692,7 +692,7 @@ ENTRY(_system_call)
         [--sp] = reti;
         SP += 4; /* don't merge with next insn to keep the pattern obvious */
         SP += -12;
-        call ___ipipe_sync_root;
+        pseudo_long_call ___ipipe_sync_root, p4;
         SP += 12;
         jump .Lresume_userspace_1;
 .Lsyscall_no_irqsync:
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index da7e3c63746b..a604f19d8dc3 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -866,7 +866,6 @@ static void bfin_gpio_unmask_irq(unsigned int irq)
         u32 pintbit = PINT_BIT(pint_val);
         u32 bank = PINT_2_BANK(pint_val);
 
-        pint[bank]->request = pintbit;
         pint[bank]->mask_set = pintbit;
 }
 
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 80884b136a0c..42fa87e8375c 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -23,9 +23,6 @@
 
 void bfin_pm_suspend_standby_enter(void)
 {
-        unsigned long flags;
-
-        flags = hard_local_irq_save();
         bfin_pm_standby_setup();
 
 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
@@ -55,8 +52,6 @@ void bfin_pm_suspend_standby_enter(void)
 #else
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
-
-        hard_local_irq_restore(flags);
 }
 
 int bf53x_suspend_l1_mem(unsigned char *memptr)
@@ -127,7 +122,6 @@ static void flushinv_all_dcache(void)
 
 int bfin_pm_suspend_mem_enter(void)
 {
-        unsigned long flags;
         int wakeup, ret;
 
         unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
@@ -149,12 +143,9 @@ int bfin_pm_suspend_mem_enter(void)
         wakeup |= GPWE;
 #endif
 
-        flags = hard_local_irq_save();
-
         ret = blackfin_dma_suspend();
 
         if (ret) {
-                hard_local_irq_restore(flags);
                 kfree(memptr);
                 return ret;
         }
@@ -178,7 +169,6 @@ int bfin_pm_suspend_mem_enter(void)
         bfin_gpio_pm_hibernate_restore();
         blackfin_dma_resume();
 
-        hard_local_irq_restore(flags);
         kfree(memptr);
 
         return 0;
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index a17107a700d5..9f251406a76a 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -19,6 +19,7 @@
 #include <linux/mm.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
+#include <linux/cpumask.h>
 #include <linux/seq_file.h>
 #include <linux/irq.h>
 #include <linux/slab.h>
@@ -43,12 +44,6 @@ void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
         *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
         *init_saved_dcplb_fault_addr_coreb;
 
-cpumask_t cpu_possible_map;
-EXPORT_SYMBOL(cpu_possible_map);
-
-cpumask_t cpu_online_map;
-EXPORT_SYMBOL(cpu_online_map);
-
 #define BFIN_IPI_RESCHEDULE   0
 #define BFIN_IPI_CALL_FUNC    1
 #define BFIN_IPI_CPU_STOP     2
@@ -65,8 +60,7 @@ struct smp_call_struct {
         void (*func)(void *info);
         void *info;
         int wait;
-        cpumask_t pending;
-        cpumask_t waitmask;
+        cpumask_t *waitmask;
 };
 
 static struct blackfin_flush_data smp_flush_data;
@@ -74,15 +68,19 @@ static struct blackfin_flush_data smp_flush_data;
 static DEFINE_SPINLOCK(stop_lock);
 
 struct ipi_message {
-        struct list_head list;
         unsigned long type;
         struct smp_call_struct call_struct;
 };
 
+/* A magic number - stress test shows this is safe for common cases */
+#define BFIN_IPI_MSGQ_LEN 5
+
+/* Simple FIFO buffer, overflow leads to panic */
 struct ipi_message_queue {
-        struct list_head head;
         spinlock_t lock;
         unsigned long count;
+        unsigned long head; /* head of the queue */
+        struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
 };
 
 static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
@@ -121,7 +119,6 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
         func = msg->call_struct.func;
         info = msg->call_struct.info;
         wait = msg->call_struct.wait;
-        cpu_clear(cpu, msg->call_struct.pending);
         func(info);
         if (wait) {
 #ifdef __ARCH_SYNC_CORE_DCACHE
@@ -132,51 +129,57 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
                  */
                 resync_core_dcache();
 #endif
-                cpu_clear(cpu, msg->call_struct.waitmask);
-        } else
-                kfree(msg);
+                cpu_clear(cpu, *msg->call_struct.waitmask);
+        }
+}
+
+/* Use IRQ_SUPPLE_0 to request reschedule.
+ * When returning from interrupt to user space,
+ * there is chance to reschedule */
+static irqreturn_t ipi_handler_int0(int irq, void *dev_instance)
+{
+        unsigned int cpu = smp_processor_id();
+
+        platform_clear_ipi(cpu, IRQ_SUPPLE_0);
+        return IRQ_HANDLED;
 }
 
-static irqreturn_t ipi_handler(int irq, void *dev_instance)
+static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 {
         struct ipi_message *msg;
         struct ipi_message_queue *msg_queue;
         unsigned int cpu = smp_processor_id();
+        unsigned long flags;
 
-        platform_clear_ipi(cpu);
+        platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 
         msg_queue = &__get_cpu_var(ipi_msg_queue);
-        msg_queue->count++;
 
-        spin_lock(&msg_queue->lock);
-        while (!list_empty(&msg_queue->head)) {
-                msg = list_entry(msg_queue->head.next, typeof(*msg), list);
-                list_del(&msg->list);
+        spin_lock_irqsave(&msg_queue->lock, flags);
+
+        while (msg_queue->count) {
+                msg = &msg_queue->ipi_message[msg_queue->head];
                 switch (msg->type) {
-                case BFIN_IPI_RESCHEDULE:
-                        /* That's the easiest one; leave it to
-                         * return_from_int. */
-                        kfree(msg);
-                        break;
                 case BFIN_IPI_CALL_FUNC:
-                        spin_unlock(&msg_queue->lock);
+                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_call_function(cpu, msg);
-                        spin_lock(&msg_queue->lock);
+                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 case BFIN_IPI_CPU_STOP:
-                        spin_unlock(&msg_queue->lock);
+                        spin_unlock_irqrestore(&msg_queue->lock, flags);
                         ipi_cpu_stop(cpu);
-                        spin_lock(&msg_queue->lock);
-                        kfree(msg);
+                        spin_lock_irqsave(&msg_queue->lock, flags);
                         break;
                 default:
                         printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
                                cpu, msg->type);
-                        kfree(msg);
                         break;
                 }
+                msg_queue->head++;
+                msg_queue->head %= BFIN_IPI_MSGQ_LEN;
+                msg_queue->count--;
         }
-        spin_unlock(&msg_queue->lock);
+        spin_unlock_irqrestore(&msg_queue->lock, flags);
         return IRQ_HANDLED;
 }
 
@@ -186,48 +189,47 @@ static void ipi_queue_init(void)
         struct ipi_message_queue *msg_queue;
         for_each_possible_cpu(cpu) {
                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                INIT_LIST_HEAD(&msg_queue->head);
                 spin_lock_init(&msg_queue->lock);
                 msg_queue->count = 0;
+                msg_queue->head = 0;
         }
 }
 
-int smp_call_function(void (*func)(void *info), void *info, int wait)
+static inline void smp_send_message(cpumask_t callmap, unsigned long type,
+                                        void (*func) (void *info), void *info, int wait)
 {
         unsigned int cpu;
-        cpumask_t callmap;
-        unsigned long flags;
         struct ipi_message_queue *msg_queue;
         struct ipi_message *msg;
-
-        callmap = cpu_online_map;
-        cpu_clear(smp_processor_id(), callmap);
-        if (cpus_empty(callmap))
-                return 0;
-
-        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return -ENOMEM;
-        INIT_LIST_HEAD(&msg->list);
-        msg->call_struct.func = func;
-        msg->call_struct.info = info;
-        msg->call_struct.wait = wait;
-        msg->call_struct.pending = callmap;
-        msg->call_struct.waitmask = callmap;
-        msg->type = BFIN_IPI_CALL_FUNC;
+        unsigned long flags, next_msg;
+        cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
 
         for_each_cpu_mask(cpu, callmap) {
                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
                 spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add_tail(&msg->list, &msg_queue->head);
+                if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
+                        next_msg = (msg_queue->head + msg_queue->count)
+                                        % BFIN_IPI_MSGQ_LEN;
+                        msg = &msg_queue->ipi_message[next_msg];
+                        msg->type = type;
+                        if (type == BFIN_IPI_CALL_FUNC) {
+                                msg->call_struct.func = func;
+                                msg->call_struct.info = info;
+                                msg->call_struct.wait = wait;
+                                msg->call_struct.waitmask = &waitmask;
+                        }
+                        msg_queue->count++;
+                } else
+                        panic("IPI message queue overflow\n");
                 spin_unlock_irqrestore(&msg_queue->lock, flags);
-                platform_send_ipi_cpu(cpu);
+                platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
         }
+
         if (wait) {
-                while (!cpus_empty(msg->call_struct.waitmask))
+                while (!cpus_empty(waitmask))
                         blackfin_dcache_invalidate_range(
-                                (unsigned long)(&msg->call_struct.waitmask),
-                                (unsigned long)(&msg->call_struct.waitmask));
+                                (unsigned long)(&waitmask),
+                                (unsigned long)(&waitmask));
 #ifdef __ARCH_SYNC_CORE_DCACHE
                 /*
                  * Invalidate D cache in case shared data was changed by
@@ -235,8 +237,20 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
                  */
                 resync_core_dcache();
 #endif
-                kfree(msg);
         }
+}
+
+int smp_call_function(void (*func)(void *info), void *info, int wait)
+{
+        cpumask_t callmap;
+
+        callmap = cpu_online_map;
+        cpu_clear(smp_processor_id(), callmap);
+        if (cpus_empty(callmap))
+                return 0;
+
+        smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
+
         return 0;
 }
 EXPORT_SYMBOL_GPL(smp_call_function);
@@ -246,100 +260,39 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 {
         unsigned int cpu = cpuid;
         cpumask_t callmap;
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
 
         if (cpu_is_offline(cpu))
                 return 0;
         cpus_clear(callmap);
         cpu_set(cpu, callmap);
 
-        msg = kmalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return -ENOMEM;
-        INIT_LIST_HEAD(&msg->list);
-        msg->call_struct.func = func;
-        msg->call_struct.info = info;
-        msg->call_struct.wait = wait;
-        msg->call_struct.pending = callmap;
-        msg->call_struct.waitmask = callmap;
-        msg->type = BFIN_IPI_CALL_FUNC;
-
-        msg_queue = &per_cpu(ipi_msg_queue, cpu);
-        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add_tail(&msg->list, &msg_queue->head);
-        spin_unlock_irqrestore(&msg_queue->lock, flags);
-        platform_send_ipi_cpu(cpu);
+        smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 
-        if (wait) {
-                while (!cpus_empty(msg->call_struct.waitmask))
-                        blackfin_dcache_invalidate_range(
-                                (unsigned long)(&msg->call_struct.waitmask),
-                                (unsigned long)(&msg->call_struct.waitmask));
-#ifdef __ARCH_SYNC_CORE_DCACHE
-                /*
-                 * Invalidate D cache in case shared data was changed by
-                 * other processors to ensure cache coherence.
-                 */
-                resync_core_dcache();
-#endif
-                kfree(msg);
-        }
         return 0;
 }
 EXPORT_SYMBOL_GPL(smp_call_function_single);
 
 void smp_send_reschedule(int cpu)
 {
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
-
+        /* simply trigger an ipi */
         if (cpu_is_offline(cpu))
                 return;
-
-        msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return;
-        INIT_LIST_HEAD(&msg->list);
-        msg->type = BFIN_IPI_RESCHEDULE;
-
-        msg_queue = &per_cpu(ipi_msg_queue, cpu);
-        spin_lock_irqsave(&msg_queue->lock, flags);
-        list_add_tail(&msg->list, &msg_queue->head);
-        spin_unlock_irqrestore(&msg_queue->lock, flags);
-        platform_send_ipi_cpu(cpu);
+        platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 
         return;
 }
 
 void smp_send_stop(void)
 {
-        unsigned int cpu;
         cpumask_t callmap;
-        unsigned long flags;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
 
         callmap = cpu_online_map;
         cpu_clear(smp_processor_id(), callmap);
         if (cpus_empty(callmap))
                 return;
 
-        msg = kzalloc(sizeof(*msg), GFP_ATOMIC);
-        if (!msg)
-                return;
-        INIT_LIST_HEAD(&msg->list);
-        msg->type = BFIN_IPI_CPU_STOP;
+        smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 
-        for_each_cpu_mask(cpu, callmap) {
-                msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                spin_lock_irqsave(&msg_queue->lock, flags);
-                list_add_tail(&msg->list, &msg_queue->head);
-                spin_unlock_irqrestore(&msg_queue->lock, flags);
-                platform_send_ipi_cpu(cpu);
-        }
         return;
 }
 
@@ -446,7 +399,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         platform_prepare_cpus(max_cpus);
         ipi_queue_init();
-        platform_request_ipi(&ipi_handler);
+        platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
+        platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 }
 
 void __init smp_cpus_done(unsigned int max_cpus)
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index 627e04b5ba9a..dfd304a4a3ea 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -704,18 +704,18 @@ int sram_free_with_lsl(const void *addr)
 {
         struct sram_list_struct *lsl, **tmp;
         struct mm_struct *mm = current->mm;
+        int ret = -1;
 
         for (tmp = &mm->context.sram_list; *tmp; tmp = &(*tmp)->next)
-                if ((*tmp)->addr == addr)
-                        goto found;
-        return -1;
-found:
-        lsl = *tmp;
-        sram_free(addr);
-        *tmp = lsl->next;
-        kfree(lsl);
+                if ((*tmp)->addr == addr) {
+                        lsl = *tmp;
+                        ret = sram_free(addr);
+                        *tmp = lsl->next;
+                        kfree(lsl);
+                        break;
+                }
 
-        return 0;
+        return ret;
 }
 EXPORT_SYMBOL(sram_free_with_lsl);
 
diff --git a/drivers/net/irda/bfin_sir.h b/drivers/net/irda/bfin_sir.h
index b54a6f08db45..e3b285a67734 100644
--- a/drivers/net/irda/bfin_sir.h
+++ b/drivers/net/irda/bfin_sir.h
@@ -26,6 +26,8 @@
 #include <asm/cacheflush.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
+#include <mach/bfin_serial_5xx.h>
+#undef DRIVER_NAME
 
 #ifdef CONFIG_SIR_BFIN_DMA
 struct dma_rx_buf {
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 188aff6d263f..c1df7676a73d 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -776,24 +776,7 @@ config BFIN_UART0_CTSRTS
         bool "Enable UART0 hardware flow control"
         depends on SERIAL_BFIN_UART0
         help
-          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
-          signal.
-
-config UART0_CTS_PIN
-        int "UART0 CTS pin"
-        depends on BFIN_UART0_CTSRTS && !BF548
-        default 23
-        help
-          The default pin is GPIO_GP7.
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
-
-config UART0_RTS_PIN
-        int "UART0 RTS pin"
-        depends on BFIN_UART0_CTSRTS && !BF548
-        default 22
-        help
-          The default pin is GPIO_GP6.
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
+          Enable hardware flow control in the driver.
 
 config SERIAL_BFIN_UART1
         bool "Enable UART1"
@@ -805,22 +788,7 @@ config BFIN_UART1_CTSRTS
         bool "Enable UART1 hardware flow control"
         depends on SERIAL_BFIN_UART1
         help
-          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
-          signal.
-
-config UART1_CTS_PIN
-        int "UART1 CTS pin"
-        depends on BFIN_UART1_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
-
-config UART1_RTS_PIN
-        int "UART1 RTS pin"
-        depends on BFIN_UART1_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
+          Enable hardware flow control in the driver.
 
 config SERIAL_BFIN_UART2
         bool "Enable UART2"
@@ -832,22 +800,7 @@ config BFIN_UART2_CTSRTS
         bool "Enable UART2 hardware flow control"
         depends on SERIAL_BFIN_UART2
         help
-          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
-          signal.
-
-config UART2_CTS_PIN
-        int "UART2 CTS pin"
-        depends on BFIN_UART2_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
-
-config UART2_RTS_PIN
-        int "UART2 RTS pin"
-        depends on BFIN_UART2_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
+          Enable hardware flow control in the driver.
 
 config SERIAL_BFIN_UART3
         bool "Enable UART3"
@@ -859,22 +812,7 @@ config BFIN_UART3_CTSRTS
         bool "Enable UART3 hardware flow control"
         depends on SERIAL_BFIN_UART3
         help
-          Enable hardware flow control in the driver. Using GPIO emulate the CTS/RTS
-          signal.
-
-config UART3_CTS_PIN
-        int "UART3 CTS pin"
-        depends on BFIN_UART3_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
-
-config UART3_RTS_PIN
-        int "UART3 RTS pin"
-        depends on BFIN_UART3_CTSRTS && !BF548
-        default -1
-        help
-          Refer to arch/blackfin/mach-*/include/mach/gpio.h to see the GPIO map.
+          Enable hardware flow control in the driver.
 
 config SERIAL_IMX
         bool "IMX serial port support"
diff --git a/drivers/serial/bfin_5xx.c b/drivers/serial/bfin_5xx.c
index 19cac9f610fd..e381b895b04d 100644
--- a/drivers/serial/bfin_5xx.c
+++ b/drivers/serial/bfin_5xx.c
@@ -1,7 +1,7 @@
 /*
  * Blackfin On-Chip Serial Driver
  *
- * Copyright 2006-2008 Analog Devices Inc.
+ * Copyright 2006-2010 Analog Devices Inc.
  *
  * Enter bugs at http://blackfin.uclinux.org/
  *
@@ -12,6 +12,9 @@
 #define SUPPORT_SYSRQ
 #endif
 
+#define DRIVER_NAME "bfin-uart"
+#define pr_fmt(fmt) DRIVER_NAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/ioport.h>
 #include <linux/gfp.h>
@@ -23,21 +26,20 @@
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/serial_core.h>
-#include <linux/dma-mapping.h>
-
-#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
-        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+#include <linux/gpio.h>
+#include <linux/irq.h>
 #include <linux/kgdb.h>
-#include <asm/irq_regs.h>
-#endif
-
-#include <asm/gpio.h>
-#include <mach/bfin_serial_5xx.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
 
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/irq.h>
+#include <asm/portmux.h>
 #include <asm/cacheflush.h>
+#include <asm/dma.h>
+
+#define port_membase(uart)     (((struct bfin_serial_port *)(uart))->port.membase)
+#define get_lsr_cache(uart)    (((struct bfin_serial_port *)(uart))->lsr)
+#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
+#include <asm/bfin_serial.h>
 
 #ifdef CONFIG_SERIAL_BFIN_MODULE
 # undef CONFIG_EARLY_PRINTK
@@ -48,12 +50,11 @@
 #endif
 
 /* UART name and device definitions */
-#define BFIN_SERIAL_NAME        "ttyBF"
+#define BFIN_SERIAL_DEV_NAME    "ttyBF"
 #define BFIN_SERIAL_MAJOR       204
 #define BFIN_SERIAL_MINOR       64
 
-static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
+static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
 
 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
         defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
@@ -743,14 +744,14 @@ static int bfin_serial_startup(struct uart_port *port)
                 }
         }
         if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
                 gpio_direction_output(uart->rts_pin, 0);
         }
 #endif
 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        if (request_irq(uart->status_irq,
+        if (uart->cts_pin >= 0 && request_irq(uart->status_irq,
                 bfin_serial_mctrl_cts_int,
                 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
+                uart->cts_pin = -1;
                 pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n");
         }
 
@@ -796,11 +797,9 @@ static void bfin_serial_shutdown(struct uart_port *port)
 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
         if (uart->cts_pin >= 0)
                 free_irq(gpio_to_irq(uart->cts_pin), uart);
-        if (uart->rts_pin >= 0)
-                gpio_free(uart->rts_pin);
 #endif
 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        if (UART_GET_IER(uart) & EDSSI)
+        if (uart->cts_pin >= 0)
                 free_irq(uart->status_irq, uart);
 #endif
 }
@@ -962,33 +961,33 @@ bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  */
 static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
 {
-        int line = port->line;
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
         unsigned short val;
 
         switch (ld) {
         case N_IRDA:
-                val = UART_GET_GCTL(&bfin_serial_ports[line]);
+                val = UART_GET_GCTL(uart);
                 val |= (IREN | RPOLC);
-                UART_PUT_GCTL(&bfin_serial_ports[line], val);
+                UART_PUT_GCTL(uart, val);
                 break;
         default:
-                val = UART_GET_GCTL(&bfin_serial_ports[line]);
+                val = UART_GET_GCTL(uart);
                 val &= ~(IREN | RPOLC);
-                UART_PUT_GCTL(&bfin_serial_ports[line], val);
+                UART_PUT_GCTL(uart, val);
         }
 }
 
 static void bfin_serial_reset_irda(struct uart_port *port)
 {
-        int line = port->line;
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
         unsigned short val;
 
-        val = UART_GET_GCTL(&bfin_serial_ports[line]);
+        val = UART_GET_GCTL(uart);
         val &= ~(IREN | RPOLC);
-        UART_PUT_GCTL(&bfin_serial_ports[line], val);
+        UART_PUT_GCTL(uart, val);
         SSYNC();
         val |= (IREN | RPOLC);
-        UART_PUT_GCTL(&bfin_serial_ports[line], val);
+        UART_PUT_GCTL(uart, val);
         SSYNC();
 }
 
@@ -1070,85 +1069,6 @@ static struct uart_ops bfin_serial_pops = {
 #endif
 };
 
-static void __init bfin_serial_hw_init(void)
-{
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-
-# if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
-        peripheral_request(P_UART1_RTS, DRIVER_NAME);
-        peripheral_request(P_UART1_CTS, DRIVER_NAME);
-# endif
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        peripheral_request(P_UART2_TX, DRIVER_NAME);
-        peripheral_request(P_UART2_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        peripheral_request(P_UART3_TX, DRIVER_NAME);
-        peripheral_request(P_UART3_RX, DRIVER_NAME);
-
-# if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
-        peripheral_request(P_UART3_RTS, DRIVER_NAME);
-        peripheral_request(P_UART3_CTS, DRIVER_NAME);
-# endif
-#endif
-}
-
-static void __init bfin_serial_init_ports(void)
-{
-        static int first = 1;
-        int i;
-
-        if (!first)
-                return;
-        first = 0;
-
-        bfin_serial_hw_init();
-
-        for (i = 0; i < nr_active_ports; i++) {
-                spin_lock_init(&bfin_serial_ports[i].port.lock);
-                bfin_serial_ports[i].port.uartclk   = get_sclk();
-                bfin_serial_ports[i].port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
-                bfin_serial_ports[i].port.ops       = &bfin_serial_pops;
-                bfin_serial_ports[i].port.line      = i;
-                bfin_serial_ports[i].port.iotype    = UPIO_MEM;
-                bfin_serial_ports[i].port.membase   =
-                        (void __iomem *)bfin_serial_resource[i].uart_base_addr;
-                bfin_serial_ports[i].port.mapbase   =
-                        bfin_serial_resource[i].uart_base_addr;
-                bfin_serial_ports[i].port.irq       =
-                        bfin_serial_resource[i].uart_irq;
-                bfin_serial_ports[i].status_irq     =
-                        bfin_serial_resource[i].uart_status_irq;
-                bfin_serial_ports[i].port.flags     = UPF_BOOT_AUTOCONF;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-                bfin_serial_ports[i].tx_done        = 1;
-                bfin_serial_ports[i].tx_count       = 0;
-                bfin_serial_ports[i].tx_dma_channel =
-                        bfin_serial_resource[i].uart_tx_dma_channel;
-                bfin_serial_ports[i].rx_dma_channel =
-                        bfin_serial_resource[i].uart_rx_dma_channel;
-                init_timer(&(bfin_serial_ports[i].rx_dma_timer));
-#endif
-#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
-        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
-                bfin_serial_ports[i].cts_pin        =
-                        bfin_serial_resource[i].uart_cts_pin;
-                bfin_serial_ports[i].rts_pin        =
-                        bfin_serial_resource[i].uart_rts_pin;
-#endif
-        }
-}
-
 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
 /*
  * If the port was already initialised (eg, by a boot loader),
@@ -1196,6 +1116,34 @@ bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
 
 static struct uart_driver bfin_serial_reg;
 
+static void bfin_serial_console_putchar(struct uart_port *port, int ch)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        while (!(UART_GET_LSR(uart) & THRE))
+                barrier();
+        UART_PUT_CHAR(uart, ch);
+}
+
+#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
+                 defined (CONFIG_EARLY_PRINTK) */
+
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+#define CLASS_BFIN_CONSOLE      "bfin-console"
+/*
+ * Interrupts are disabled on entering
+ */
+static void
+bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
+{
+        struct bfin_serial_port *uart = bfin_serial_ports[co->index];
+        unsigned long flags;
+
+        spin_lock_irqsave(&uart->port.lock, flags);
+        uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
+        spin_unlock_irqrestore(&uart->port.lock, flags);
+
+}
+
 static int __init
 bfin_serial_console_setup(struct console *co, char *options)
 {
@@ -1215,9 +1163,12 @@ bfin_serial_console_setup(struct console *co, char *options)
          * if so, search for the first available port that does have
          * console support.
          */
-        if (co->index == -1 || co->index >= nr_active_ports)
-                co->index = 0;
-        uart = &bfin_serial_ports[co->index];
+        if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
+                return -ENODEV;
+
+        uart = bfin_serial_ports[co->index];
+        if (!uart)
+                return -ENODEV;
 
         if (options)
                 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -1226,36 +1177,9 @@ bfin_serial_console_setup(struct console *co, char *options)
 
         return uart_set_options(&uart->port, co, baud, parity, bits, flow);
 }
-#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
-                                 defined (CONFIG_EARLY_PRINTK) */
-
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
-static void bfin_serial_console_putchar(struct uart_port *port, int ch)
-{
-        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-        while (!(UART_GET_LSR(uart) & THRE))
-                barrier();
-        UART_PUT_CHAR(uart, ch);
-        SSYNC();
-}
-
-/*
- * Interrupts are disabled on entering
- */
-static void
-bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
-{
-        struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
-        unsigned long flags;
-
-        spin_lock_irqsave(&uart->port.lock, flags);
-        uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
-        spin_unlock_irqrestore(&uart->port.lock, flags);
-
-}
 
 static struct console bfin_serial_console = {
-        .name           = BFIN_SERIAL_NAME,
+        .name           = BFIN_SERIAL_DEV_NAME,
         .write          = bfin_serial_console_write,
         .device         = uart_console_device,
         .setup          = bfin_serial_console_setup,
@@ -1263,44 +1187,30 @@ static struct console bfin_serial_console = {
         .index          = -1,
         .data           = &bfin_serial_reg,
 };
-
-static int __init bfin_serial_rs_console_init(void)
-{
-        bfin_serial_init_ports();
-        register_console(&bfin_serial_console);
-
-        return 0;
-}
-console_initcall(bfin_serial_rs_console_init);
-
 #define BFIN_SERIAL_CONSOLE     &bfin_serial_console
 #else
 #define BFIN_SERIAL_CONSOLE     NULL
 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
 
+#ifdef  CONFIG_EARLY_PRINTK
+static struct bfin_serial_port bfin_earlyprintk_port;
+#define CLASS_BFIN_EARLYPRINTK  "bfin-earlyprintk"
 
-#ifdef CONFIG_EARLY_PRINTK
-static __init void early_serial_putc(struct uart_port *port, int ch)
+/*
+ * Interrupts are disabled on entering
+ */
+static void
+bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
 {
-        unsigned timeout = 0xffff;
-        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
-
-        while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
-                cpu_relax();
-        UART_PUT_CHAR(uart, ch);
-}
+        unsigned long flags;
 
-static __init void early_serial_write(struct console *con, const char *s,
-                                        unsigned int n)
-{
-        struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
-        unsigned int i;
+        if (bfin_earlyprintk_port.port.line != co->index)
+                return;
 
-        for (i = 0; i < n; i++, s++) {
-                if (*s == '\n')
-                        early_serial_putc(&uart->port, '\r');
-                early_serial_putc(&uart->port, *s);
-        }
+        spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
+        uart_console_write(&bfin_earlyprintk_port.port, s, count,
+                bfin_serial_console_putchar);
+        spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
 }
 
 /*
@@ -1311,113 +1221,204 @@ static __init void early_serial_write(struct console *con, const char *s,
  */
 static struct __initdata console bfin_early_serial_console = {
         .name = "early_BFuart",
-        .write = early_serial_write,
+        .write = bfin_earlyprintk_console_write,
         .device = uart_console_device,
         .flags = CON_PRINTBUFFER,
         .index = -1,
         .data  = &bfin_serial_reg,
 };
-
-struct console __init *bfin_earlyserial_init(unsigned int port,
-                                                unsigned int cflag)
-{
-        struct bfin_serial_port *uart;
-        struct ktermios t;
-
-#ifdef CONFIG_SERIAL_BFIN_CONSOLE
-        /*
-         * If we are using early serial, don't let the normal console rewind
-         * log buffer, since that causes things to be printed multiple times
-         */
-        bfin_serial_console.flags &= ~CON_PRINTBUFFER;
 #endif
 
-        if (port == -1 || port >= nr_active_ports)
-                port = 0;
-        bfin_serial_init_ports();
-        bfin_early_serial_console.index = port;
-        uart = &bfin_serial_ports[port];
-        t.c_cflag = cflag;
-        t.c_iflag = 0;
-        t.c_oflag = 0;
-        t.c_lflag = ICANON;
-        t.c_line = port;
-        bfin_serial_set_termios(&uart->port, &t, &t);
-        return &bfin_early_serial_console;
-}
-
-#endif /* CONFIG_EARLY_PRINTK */
-
 static struct uart_driver bfin_serial_reg = {
         .owner                  = THIS_MODULE,
-        .driver_name            = "bfin-uart",
-        .dev_name               = BFIN_SERIAL_NAME,
+        .driver_name            = DRIVER_NAME,
+        .dev_name               = BFIN_SERIAL_DEV_NAME,
         .major                  = BFIN_SERIAL_MAJOR,
         .minor                  = BFIN_SERIAL_MINOR,
         .nr                     = BFIN_UART_NR_PORTS,
         .cons                   = BFIN_SERIAL_CONSOLE,
 };
 
-static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
+static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
 {
-        int i;
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
 
-        for (i = 0; i < nr_active_ports; i++) {
-                if (bfin_serial_ports[i].port.dev != &dev->dev)
-                        continue;
-                uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
-        }
+        return uart_suspend_port(&bfin_serial_reg, &uart->port);
+}
 
-        return 0;
+static int bfin_serial_resume(struct platform_device *pdev)
+{
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
+
+        return uart_resume_port(&bfin_serial_reg, &uart->port);
 }
 
-static int bfin_serial_resume(struct platform_device *dev)
+static int bfin_serial_probe(struct platform_device *pdev)
 {
-        int i;
+        struct resource *res;
+        struct bfin_serial_port *uart = NULL;
+        int ret = 0;
 
-        for (i = 0; i < nr_active_ports; i++) {
-                if (bfin_serial_ports[i].port.dev != &dev->dev)
-                        continue;
-                uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
+        if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
+                dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
+                return -ENOENT;
         }
 
-        return 0;
-}
+        if (bfin_serial_ports[pdev->id] == NULL) {
 
-static int bfin_serial_probe(struct platform_device *dev)
-{
-        struct resource *res = dev->resource;
-        int i;
+                uart = kzalloc(sizeof(*uart), GFP_KERNEL);
+                if (!uart) {
+                        dev_err(&pdev->dev,
+                                "fail to malloc bfin_serial_port\n");
+                        return -ENOMEM;
+                }
+                bfin_serial_ports[pdev->id] = uart;
 
-        for (i = 0; i < dev->num_resources; i++, res++)
-                if (res->flags & IORESOURCE_MEM)
-                        break;
+#ifdef CONFIG_EARLY_PRINTK
+                if (!(bfin_earlyprintk_port.port.membase
+                        && bfin_earlyprintk_port.port.line == pdev->id)) {
+                        /*
+                         * If the peripheral PINs of current port is allocated
+                         * in earlyprintk probe stage, don't do it again.
+                         */
+#endif
+                ret = peripheral_request_list(
+                        (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "fail to request bfin serial peripherals\n");
+                        goto out_error_free_mem;
+                }
+#ifdef CONFIG_EARLY_PRINTK
+                }
+#endif
+
+                spin_lock_init(&uart->port.lock);
+                uart->port.uartclk   = get_sclk();
+                uart->port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
+                uart->port.ops       = &bfin_serial_pops;
+                uart->port.line      = pdev->id;
+                uart->port.iotype    = UPIO_MEM;
+                uart->port.flags     = UPF_BOOT_AUTOCONF;
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+                        ret = -ENOENT;
+                        goto out_error_free_peripherals;
+                }
+
+                uart->port.membase = ioremap(res->start,
+                        res->end - res->start);
+                if (!uart->port.membase) {
+                        dev_err(&pdev->dev, "Cannot map uart IO\n");
+                        ret = -ENXIO;
+                        goto out_error_free_peripherals;
+                }
+                uart->port.mapbase = res->start;
 
-        if (i < dev->num_resources) {
-                for (i = 0; i < nr_active_ports; i++, res++) {
-                        if (bfin_serial_ports[i].port.mapbase != res->start)
-                                continue;
-                        bfin_serial_ports[i].port.dev = &dev->dev;
-                        uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
+                uart->port.irq = platform_get_irq(pdev, 0);
+                if (uart->port.irq < 0) {
+                        dev_err(&pdev->dev, "No uart RX/TX IRQ specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
                 }
+
+                uart->status_irq = platform_get_irq(pdev, 1);
+                if (uart->status_irq < 0) {
+                        dev_err(&pdev->dev, "No uart status IRQ specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+                uart->tx_done       = 1;
+                uart->tx_count      = 0;
+
+                res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+                uart->tx_dma_channel = res->start;
+
+                res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+                uart->rx_dma_channel = res->start;
+
+                init_timer(&(uart->rx_dma_timer));
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+                res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+                if (res == NULL)
+                        uart->cts_pin = -1;
+                else
+                        uart->cts_pin = res->start;
+
+                res = platform_get_resource(pdev, IORESOURCE_IO, 1);
+                if (res == NULL)
+                        uart->rts_pin = -1;
+                else
+                        uart->rts_pin = res->start;
+# if defined(CONFIG_SERIAL_BFIN_CTSRTS)
+                if (uart->rts_pin >= 0)
+                        gpio_request(uart->rts_pin, DRIVER_NAME);
+# endif
+#endif
         }
 
-        return 0;
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        if (!is_early_platform_device(pdev)) {
+#endif
+                uart = bfin_serial_ports[pdev->id];
+                uart->port.dev = &pdev->dev;
+                dev_set_drvdata(&pdev->dev, uart);
+                ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        }
+#endif
+
+        if (!ret)
+                return 0;
+
+        if (uart) {
+out_error_unmap:
+                iounmap(uart->port.membase);
+out_error_free_peripherals:
+                peripheral_free_list(
+                        (unsigned short *)pdev->dev.platform_data);
+out_error_free_mem:
+                kfree(uart);
+                bfin_serial_ports[pdev->id] = NULL;
+        }
+
+        return ret;
 }
 
-static int bfin_serial_remove(struct platform_device *dev)
+static int __devexit bfin_serial_remove(struct platform_device *pdev)
 {
-        int i;
-
-        for (i = 0; i < nr_active_ports; i++) {
-                if (bfin_serial_ports[i].port.dev != &dev->dev)
-                        continue;
-                uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
-                bfin_serial_ports[i].port.dev = NULL;
-#if defined(CONFIG_SERIAL_BFIN_CTSRTS)
-                gpio_free(bfin_serial_ports[i].cts_pin);
-                gpio_free(bfin_serial_ports[i].rts_pin);
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
+
+        dev_set_drvdata(&pdev->dev, NULL);
+
+        if (uart) {
+                uart_remove_one_port(&bfin_serial_reg, &uart->port);
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+                if (uart->rts_pin >= 0)
+                        gpio_free(uart->rts_pin);
 #endif
+                iounmap(uart->port.membase);
+                peripheral_free_list(
+                        (unsigned short *)pdev->dev.platform_data);
+                kfree(uart);
+                bfin_serial_ports[pdev->id] = NULL;
         }
 
         return 0;
@@ -1425,31 +1426,160 @@ static int bfin_serial_remove(struct platform_device *dev)
 
 static struct platform_driver bfin_serial_driver = {
         .probe          = bfin_serial_probe,
-        .remove         = bfin_serial_remove,
+        .remove         = __devexit_p(bfin_serial_remove),
         .suspend        = bfin_serial_suspend,
         .resume         = bfin_serial_resume,
         .driver         = {
-                .name   = "bfin-uart",
+                .name   = DRIVER_NAME,
                 .owner  = THIS_MODULE,
         },
 };
 
-static int __init bfin_serial_init(void)
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE)
+static __initdata struct early_platform_driver early_bfin_serial_driver = {
+        .class_str = CLASS_BFIN_CONSOLE,
+        .pdrv = &bfin_serial_driver,
+        .requested_id = EARLY_PLATFORM_ID_UNSET,
+};
+
+static int __init bfin_serial_rs_console_init(void)
+{
+        early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
+
+        early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
+
+        register_console(&bfin_serial_console);
+
+        return 0;
+}
+console_initcall(bfin_serial_rs_console_init);
+#endif
+
+#ifdef CONFIG_EARLY_PRINTK
+/*
+ * Memory can't be allocated dynamically during earlyprink init stage.
+ * So, do individual probe for earlyprink with a static uart port variable.
+ */
+static int bfin_earlyprintk_probe(struct platform_device *pdev)
 {
+        struct resource *res;
         int ret;
 
-        pr_info("Serial: Blackfin serial driver\n");
+        if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
+                dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
+                return -ENOENT;
+        }
+
+        ret = peripheral_request_list(
+                (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
+        if (ret) {
+                dev_err(&pdev->dev,
+                                "fail to request bfin serial peripherals\n");
+                        return ret;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+                ret = -ENOENT;
+                goto out_error_free_peripherals;
+        }
+
+        bfin_earlyprintk_port.port.membase = ioremap(res->start,
+                        res->end - res->start);
+        if (!bfin_earlyprintk_port.port.membase) {
+                dev_err(&pdev->dev, "Cannot map uart IO\n");
+                ret = -ENXIO;
+                goto out_error_free_peripherals;
+        }
+        bfin_earlyprintk_port.port.mapbase = res->start;
+        bfin_earlyprintk_port.port.line = pdev->id;
+        bfin_earlyprintk_port.port.uartclk = get_sclk();
+        bfin_earlyprintk_port.port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
+        spin_lock_init(&bfin_earlyprintk_port.port.lock);
+
+        return 0;
+
+out_error_free_peripherals:
+        peripheral_free_list(
+                (unsigned short *)pdev->dev.platform_data);
+
+        return ret;
+}
+
+static struct platform_driver bfin_earlyprintk_driver = {
+        .probe          = bfin_earlyprintk_probe,
+        .driver         = {
+                .name   = DRIVER_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static __initdata struct early_platform_driver early_bfin_earlyprintk_driver = {
+        .class_str = CLASS_BFIN_EARLYPRINTK,
+        .pdrv = &bfin_earlyprintk_driver,
+        .requested_id = EARLY_PLATFORM_ID_UNSET,
+};
+
+struct console __init *bfin_earlyserial_init(unsigned int port,
+                                                unsigned int cflag)
+{
+        struct ktermios t;
+        char port_name[20];
 
-        bfin_serial_init_ports();
+        if (port < 0 || port >= BFIN_UART_NR_PORTS)
+                return NULL;
+
+        /*
+         * Only probe resource of the given port in earlyprintk boot arg.
+         * The expected port id should be indicated in port name string.
+         */
+        snprintf(port_name, 20, DRIVER_NAME ".%d", port);
+        early_platform_driver_register(&early_bfin_earlyprintk_driver,
+                port_name);
+        early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
+
+        if (!bfin_earlyprintk_port.port.membase)
+                return NULL;
+
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        /*
+         * If we are using early serial, don't let the normal console rewind
+         * log buffer, since that causes things to be printed multiple times
+         */
+        bfin_serial_console.flags &= ~CON_PRINTBUFFER;
+#endif
+
+        bfin_early_serial_console.index = port;
+        t.c_cflag = cflag;
+        t.c_iflag = 0;
+        t.c_oflag = 0;
+        t.c_lflag = ICANON;
+        t.c_line = port;
+        bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
+
+        return &bfin_early_serial_console;
+}
+#endif /* CONFIG_EARLY_PRINTK */
+
+static int __init bfin_serial_init(void)
+{
+        int ret;
+
+        pr_info("Blackfin serial driver\n");
 
         ret = uart_register_driver(&bfin_serial_reg);
-        if (ret == 0) {
-                ret = platform_driver_register(&bfin_serial_driver);
-                if (ret) {
-                        pr_debug("uart register failed\n");
-                        uart_unregister_driver(&bfin_serial_reg);
-                }
+        if (ret) {
+                pr_err("failed to register %s:%d\n",
+                        bfin_serial_reg.driver_name, ret);
+        }
+
+        ret = platform_driver_register(&bfin_serial_driver);
+        if (ret) {
+                pr_err("fail to register bfin uart\n");
+                uart_unregister_driver(&bfin_serial_reg);
         }
+
         return ret;
 }
 
@@ -1463,7 +1593,7 @@ static void __exit bfin_serial_exit(void)
 module_init(bfin_serial_init);
 module_exit(bfin_serial_exit);
 
-MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
+MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
 MODULE_DESCRIPTION("Blackfin generic serial port driver");
 MODULE_LICENSE("GPL");
 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h
index 3577ca11a0be..4644c9a7f724 100644
--- a/include/asm-generic/io.h
+++ b/include/asm-generic/io.h
@@ -211,6 +211,36 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
 }
 #endif
 
+static inline void readsl(const void __iomem *addr, void *buf, int len)
+{
+        insl((unsigned long)addr, buf, len);
+}
+
+static inline void readsw(const void __iomem *addr, void *buf, int len)
+{
+        insw((unsigned long)addr, buf, len);
+}
+
+static inline void readsb(const void __iomem *addr, void *buf, int len)
+{
+        insb((unsigned long)addr, buf, len);
+}
+
+static inline void writesl(const void __iomem *addr, const void *buf, int len)
+{
+        outsl((unsigned long)addr, buf, len);
+}
+
+static inline void writesw(const void __iomem *addr, const void *buf, int len)
+{
+        outsw((unsigned long)addr, buf, len);
+}
+
+static inline void writesb(const void __iomem *addr, const void *buf, int len)
+{
+        outsb((unsigned long)addr, buf, len);
+}
+
 #ifndef CONFIG_GENERIC_IOMAP
 #define ioread8(addr)           readb(addr)
 #define ioread16(addr)          readw(addr)