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authorJiang Liu <jiang.liu@huawei.com>2012-07-24 05:20:25 -0400
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 12:11:14 -0400
commit08bd108096b6bc7d830b62e0b468179e5e3d0b89 (patch)
tree60df2fe0cf0a8d28c28d17cfce801b20aa53c66f
parenteb0ff56366c38b87c048a624407bc699bf06d43f (diff)
ath9k: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify ath9k driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c21
1 files changed, 6 insertions, 15 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 87b89d55e637..f7fe104df372 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -112,41 +112,32 @@ static void ath_pci_aspm_init(struct ath_common *common)
112 struct ath_hw *ah = sc->sc_ah; 112 struct ath_hw *ah = sc->sc_ah;
113 struct pci_dev *pdev = to_pci_dev(sc->dev); 113 struct pci_dev *pdev = to_pci_dev(sc->dev);
114 struct pci_dev *parent; 114 struct pci_dev *parent;
115 int pos; 115 u16 aspm;
116 u8 aspm;
117 116
118 if (!ah->is_pciexpress) 117 if (!ah->is_pciexpress)
119 return; 118 return;
120 119
121 pos = pci_pcie_cap(pdev);
122 if (!pos)
123 return;
124
125 parent = pdev->bus->self; 120 parent = pdev->bus->self;
126 if (!parent) 121 if (!parent)
127 return; 122 return;
128 123
129 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) { 124 if (ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) {
130 /* Bluetooth coexistance requires disabling ASPM. */ 125 /* Bluetooth coexistance requires disabling ASPM. */
131 pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &aspm); 126 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
132 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 127 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
133 pci_write_config_byte(pdev, pos + PCI_EXP_LNKCTL, aspm);
134 128
135 /* 129 /*
136 * Both upstream and downstream PCIe components should 130 * Both upstream and downstream PCIe components should
137 * have the same ASPM settings. 131 * have the same ASPM settings.
138 */ 132 */
139 pos = pci_pcie_cap(parent); 133 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
140 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm); 134 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
141 aspm &= ~(PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
142 pci_write_config_byte(parent, pos + PCI_EXP_LNKCTL, aspm);
143 135
144 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 136 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
145 return; 137 return;
146 } 138 }
147 139
148 pos = pci_pcie_cap(parent); 140 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
149 pci_read_config_byte(parent, pos + PCI_EXP_LNKCTL, &aspm);
150 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 141 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
151 ah->aspm_enabled = true; 142 ah->aspm_enabled = true;
152 /* Initialize PCIe PM and SERDES registers. */ 143 /* Initialize PCIe PM and SERDES registers. */