diff options
| author | Mike Frysinger <vapier@gentoo.org> | 2011-05-26 18:05:15 -0400 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-05-28 17:02:56 -0400 |
| commit | fcb243918f9e8414bf5ad6fb0361447ac3d3fddb (patch) | |
| tree | 72ee1b97b061e1de09ff91853ea10b0f602781a2 | |
| parent | 61aa818f7bfdb5dd0aef4687513566c75c0e4c21 (diff) | |
Blackfin: bf51x: fix up RSI_PID# MMR defines
Looks like the copying of MMR defines from the SDH block missed updating
the addresses of the RSI_PID# registers. So tweak them to reflect the
actual hardware.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF514.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h index 98a51c479290..cfab428e577c 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h | |||
| @@ -36,13 +36,13 @@ | |||
| 36 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ | 36 | #define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ |
| 37 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ | 37 | #define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ |
| 38 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ | 38 | #define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ |
| 39 | #define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ | 39 | #define RSI_PID0 0xFFC038D0 /* RSI Peripheral ID Register 0 */ |
| 40 | #define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ | 40 | #define RSI_PID1 0xFFC038D4 /* RSI Peripheral ID Register 1 */ |
| 41 | #define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ | 41 | #define RSI_PID2 0xFFC038D8 /* RSI Peripheral ID Register 2 */ |
| 42 | #define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ | 42 | #define RSI_PID3 0xFFC038DC /* RSI Peripheral ID Register 3 */ |
| 43 | #define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ | 43 | #define RSI_PID4 0xFFC038E0 /* RSI Peripheral ID Register 0 */ |
| 44 | #define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ | 44 | #define RSI_PID5 0xFFC038E4 /* RSI Peripheral ID Register 1 */ |
| 45 | #define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ | 45 | #define RSI_PID6 0xFFC038E8 /* RSI Peripheral ID Register 2 */ |
| 46 | #define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ | 46 | #define RSI_PID7 0xFFC038EC /* RSI Peripheral ID Register 3 */ |
| 47 | 47 | ||
| 48 | #endif /* _DEF_BF514_H */ | 48 | #endif /* _DEF_BF514_H */ |