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authorMichael Ellerman <michael@ellerman.id.au>2006-11-07 02:21:21 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2006-12-01 17:36:56 -0500
commite65e5fb5ceb02aaea7b65bf8b3b0d0c9057718b6 (patch)
tree0a77bfb7da117da88bd021691a8afde10671a007
parent009af1ff78bfc30b9a27807dd0207fc32848218a (diff)
PCI: Make some MSI-X #defines generic
Move some MSI-X #defines into pci_regs.h so they can be used outside of drivers/pci. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/pci/msi.h8
-rw-r--r--include/linux/pci_regs.h6
2 files changed, 6 insertions, 8 deletions
diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h
index f0cca1772f9c..3898f5237144 100644
--- a/drivers/pci/msi.h
+++ b/drivers/pci/msi.h
@@ -6,14 +6,6 @@
6#ifndef MSI_H 6#ifndef MSI_H
7#define MSI_H 7#define MSI_H
8 8
9/*
10 * MSI-X Address Register
11 */
12#define PCI_MSIX_FLAGS_QSIZE 0x7FF
13#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
14#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
15#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
16
17#define PCI_MSIX_ENTRY_SIZE 16 9#define PCI_MSIX_ENTRY_SIZE 16
18#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0 10#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
19#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4 11#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c321316f1bc7..064b1dc71c22 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -292,6 +292,12 @@
292#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 292#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
293#define PCI_MSI_MASK_BIT 16 /* Mask bits register */ 293#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
294 294
295/* MSI-X registers (these are at offset PCI_MSI_FLAGS) */
296#define PCI_MSIX_FLAGS_QSIZE 0x7FF
297#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
298#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
299#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
300
295/* CompactPCI Hotswap Register */ 301/* CompactPCI Hotswap Register */
296 302
297#define PCI_CHSWP_CSR 2 /* Control and Status Register */ 303#define PCI_CHSWP_CSR 2 /* Control and Status Register */