aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRuss Anderson <rja@sgi.com>2008-02-29 18:14:44 -0500
committerTony Luck <tony.luck@intel.com>2008-04-09 16:05:54 -0400
commitc19b2930df0621500913c005c06978bd8933110b (patch)
treee59a2498214ff65a6630722430a0c80941377ff9
parent273988fa4dffd1b1e6deb3de18b979a44e9d8732 (diff)
[IA64] Itanium Spec updates
Updates based on the "IntelĀ® ItaniumĀ® Architecture Software Developer's Manual Specification Update October 2007". http://download.intel.com/design/itanium/specupdt/24869911.pdf Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--include/asm-ia64/pal.h72
1 files changed, 63 insertions, 9 deletions
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 8a695d3407d2..67b02901ead4 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -13,6 +13,7 @@
13 * Copyright (C) 1999 VA Linux Systems 13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> 14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> 15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
16 * 17 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters. 18 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. 19 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
@@ -73,6 +74,8 @@
73#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ 74#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
74#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */ 75#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
75#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */ 76#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
77#define PAL_VP_INFO 50 /* Information about virtual processor features */
78#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
76 79
77#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ 80#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
78#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ 81#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
@@ -504,7 +507,8 @@ typedef struct pal_cache_check_info_s {
504 wiv : 1, /* Way field valid */ 507 wiv : 1, /* Way field valid */
505 reserved2 : 1, 508 reserved2 : 1,
506 dp : 1, /* Data poisoned on MBE */ 509 dp : 1, /* Data poisoned on MBE */
507 reserved3 : 8, 510 reserved3 : 6,
511 hlth : 2, /* Health indicator */
508 512
509 index : 20, /* Cache line index */ 513 index : 20, /* Cache line index */
510 reserved4 : 2, 514 reserved4 : 2,
@@ -542,7 +546,9 @@ typedef struct pal_tlb_check_info_s {
542 dtc : 1, /* Fail in data TC */ 546 dtc : 1, /* Fail in data TC */
543 itc : 1, /* Fail in inst. TC */ 547 itc : 1, /* Fail in inst. TC */
544 op : 4, /* Cache operation */ 548 op : 4, /* Cache operation */
545 reserved3 : 30, 549 reserved3 : 6,
550 hlth : 2, /* Health indicator */
551 reserved4 : 22,
546 552
547 is : 1, /* instruction set (1 == ia32) */ 553 is : 1, /* instruction set (1 == ia32) */
548 iv : 1, /* instruction set field valid */ 554 iv : 1, /* instruction set field valid */
@@ -633,7 +639,8 @@ typedef struct pal_uarch_check_info_s {
633 way : 6, /* Way of structure */ 639 way : 6, /* Way of structure */
634 wv : 1, /* way valid */ 640 wv : 1, /* way valid */
635 xv : 1, /* index valid */ 641 xv : 1, /* index valid */
636 reserved1 : 8, 642 reserved1 : 6,
643 hlth : 2, /* Health indicator */
637 index : 8, /* Index or set of the uarch 644 index : 8, /* Index or set of the uarch
638 * structure that failed. 645 * structure that failed.
639 */ 646 */
@@ -1213,14 +1220,12 @@ ia64_pal_mc_drain (void)
1213 1220
1214/* Return the machine check dynamic processor state */ 1221/* Return the machine check dynamic processor state */
1215static inline s64 1222static inline s64
1216ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds) 1223ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
1217{ 1224{
1218 struct ia64_pal_retval iprv; 1225 struct ia64_pal_retval iprv;
1219 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0); 1226 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
1220 if (size) 1227 if (size)
1221 *size = iprv.v0; 1228 *size = iprv.v0;
1222 if (pds)
1223 *pds = iprv.v1;
1224 return iprv.status; 1229 return iprv.status;
1225} 1230}
1226 1231
@@ -1281,15 +1286,41 @@ ia64_pal_mc_expected (u64 expected, u64 *previous)
1281 return iprv.status; 1286 return iprv.status;
1282} 1287}
1283 1288
1289typedef union pal_hw_tracking_u {
1290 u64 pht_data;
1291 struct {
1292 u64 itc :4, /* Instruction cache tracking */
1293 dct :4, /* Date cache tracking */
1294 itt :4, /* Instruction TLB tracking */
1295 ddt :4, /* Data TLB tracking */
1296 reserved:48;
1297 } pal_hw_tracking_s;
1298} pal_hw_tracking_u_t;
1299
1300/*
1301 * Hardware tracking status.
1302 */
1303static inline s64
1304ia64_pal_mc_hw_tracking (u64 *status)
1305{
1306 struct ia64_pal_retval iprv;
1307 PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
1308 if (status)
1309 *status = iprv.v0;
1310 return iprv.status;
1311}
1312
1284/* Register a platform dependent location with PAL to which it can save 1313/* Register a platform dependent location with PAL to which it can save
1285 * minimal processor state in the event of a machine check or initialization 1314 * minimal processor state in the event of a machine check or initialization
1286 * event. 1315 * event.
1287 */ 1316 */
1288static inline s64 1317static inline s64
1289ia64_pal_mc_register_mem (u64 physical_addr) 1318ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
1290{ 1319{
1291 struct ia64_pal_retval iprv; 1320 struct ia64_pal_retval iprv;
1292 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0); 1321 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
1322 if (req_size)
1323 *req_size = iprv.v0;
1293 return iprv.status; 1324 return iprv.status;
1294} 1325}
1295 1326
@@ -1631,6 +1662,29 @@ ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1631 return iprv.status; 1662 return iprv.status;
1632} 1663}
1633 1664
1665typedef union pal_vp_info_u {
1666 u64 pvi_val;
1667 struct {
1668 u64 index: 48, /* virtual feature set info */
1669 vmm_id: 16; /* feature set id */
1670 } pal_vp_info_s;
1671} pal_vp_info_u_t;
1672
1673/*
1674 * Returns infomation about virtual processor features
1675 */
1676static inline s64
1677ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
1678{
1679 struct ia64_pal_retval iprv;
1680 PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
1681 if (vp_info)
1682 *vp_info = iprv.v0;
1683 if (vmm_id)
1684 *vmm_id = iprv.v1;
1685 return iprv.status;
1686}
1687
1634typedef union pal_itr_valid_u { 1688typedef union pal_itr_valid_u {
1635 u64 piv_val; 1689 u64 piv_val;
1636 struct { 1690 struct {