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authorSylvain Munaut <tnt@246tNt.com>2007-09-16 06:53:26 -0400
committerGrant Likely <grant.likely@secretlab.ca>2007-10-16 19:09:27 -0400
commit07e6e93136ca61f071c819c69e1ec5bff9fda46f (patch)
treef5dd88f6cc7842d40b9abbd7e8f7f3ac323e9b98
parent1088a20998a1091b22b42cf3dc2f5f1be4faaead (diff)
[POWERPC] mpc52xx: Update mpc52xx_psc structure with B revision changes
On the mpc5200b the ccr register is 32 bits wide while on the mpc5200 it's only 16 bits. It's up to the driver to use the correct format depending on the chip it's running on. The 5200b also offers some more registers & status in AC97 mode. Again, if not running on a 5200b the driver should not use those. Signed-off-by: Sylvain Munaut <tnt@246tNt.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
-rw-r--r--include/asm-ppc/mpc52xx_psc.h10
1 files changed, 8 insertions, 2 deletions
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h
index 9d850b2b20b8..c82b8d49a7da 100644
--- a/include/asm-ppc/mpc52xx_psc.h
+++ b/include/asm-ppc/mpc52xx_psc.h
@@ -28,6 +28,10 @@
28#define MPC52xx_PSC_MAXNUM 6 28#define MPC52xx_PSC_MAXNUM 6
29 29
30/* Programmable Serial Controller (PSC) status register bits */ 30/* Programmable Serial Controller (PSC) status register bits */
31#define MPC52xx_PSC_SR_UNEX_RX 0x0001
32#define MPC52xx_PSC_SR_DATA_VAL 0x0002
33#define MPC52xx_PSC_SR_DATA_OVR 0x0004
34#define MPC52xx_PSC_SR_CMDSEND 0x0008
31#define MPC52xx_PSC_SR_CDE 0x0080 35#define MPC52xx_PSC_SR_CDE 0x0080
32#define MPC52xx_PSC_SR_RXRDY 0x0100 36#define MPC52xx_PSC_SR_RXRDY 0x0100
33#define MPC52xx_PSC_SR_RXFULL 0x0200 37#define MPC52xx_PSC_SR_RXFULL 0x0200
@@ -132,8 +136,10 @@ struct mpc52xx_psc {
132 u8 reserved5[3]; 136 u8 reserved5[3];
133 u8 ctlr; /* PSC + 0x1c */ 137 u8 ctlr; /* PSC + 0x1c */
134 u8 reserved6[3]; 138 u8 reserved6[3];
135 u16 ccr; /* PSC + 0x20 */ 139 u32 ccr; /* PSC + 0x20 */
136 u8 reserved7[14]; 140 u32 ac97_slots; /* PSC + 0x24 */
141 u32 ac97_cmd; /* PSC + 0x28 */
142 u32 ac97_data; /* PSC + 0x2c */
137 u8 ivr; /* PSC + 0x30 */ 143 u8 ivr; /* PSC + 0x30 */
138 u8 reserved8[3]; 144 u8 reserved8[3];
139 u8 ip; /* PSC + 0x34 */ 145 u8 ip; /* PSC + 0x34 */