diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2010-07-28 17:00:54 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-07-29 09:04:36 -0400 |
commit | e936771a76a7b61ca55a5142a3de835c2e196871 (patch) | |
tree | 3ec67935283bbd150bbaa2c9847dec525a0eb031 | |
parent | 661f10f6b6ce55c737e88c4803453eba4ba3a61c (diff) |
ARM: 6271/1: Introduce *_relaxed() I/O accessors
This patch introduces readl*_relaxed()/write*_relaxed() as the main I/O
accessors (when __mem_pci is defined). The standard read*()/write*()
macros are now based on the relaxed accessors.
This patch is in preparation for a subsequent patch which adds barriers
to the I/O accessors.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r-- | arch/arm/include/asm/io.h | 29 |
1 files changed, 17 insertions, 12 deletions
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index c980156f3263..9db072df2b3d 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h | |||
@@ -179,25 +179,30 @@ extern void _memset_io(volatile void __iomem *, int, size_t); | |||
179 | * IO port primitives for more information. | 179 | * IO port primitives for more information. |
180 | */ | 180 | */ |
181 | #ifdef __mem_pci | 181 | #ifdef __mem_pci |
182 | #define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; }) | 182 | #define readb_relaxed(c) ({ u8 __v = __raw_readb(__mem_pci(c)); __v; }) |
183 | #define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \ | 183 | #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \ |
184 | __raw_readw(__mem_pci(c))); __v; }) | 184 | __raw_readw(__mem_pci(c))); __v; }) |
185 | #define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \ | 185 | #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \ |
186 | __raw_readl(__mem_pci(c))); __v; }) | 186 | __raw_readl(__mem_pci(c))); __v; }) |
187 | #define readb_relaxed(addr) readb(addr) | 187 | |
188 | #define readw_relaxed(addr) readw(addr) | 188 | #define writeb_relaxed(v,c) ((void)__raw_writeb(v,__mem_pci(c))) |
189 | #define readl_relaxed(addr) readl(addr) | 189 | #define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \ |
190 | cpu_to_le16(v),__mem_pci(c))) | ||
191 | #define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \ | ||
192 | cpu_to_le32(v),__mem_pci(c))) | ||
193 | |||
194 | #define readb(c) readb_relaxed(c) | ||
195 | #define readw(c) readw_relaxed(c) | ||
196 | #define readl(c) readl_relaxed(c) | ||
197 | |||
198 | #define writeb(v,c) writeb_relaxed(v,c) | ||
199 | #define writew(v,c) writew_relaxed(v,c) | ||
200 | #define writel(v,c) writel_relaxed(v,c) | ||
190 | 201 | ||
191 | #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) | 202 | #define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l) |
192 | #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) | 203 | #define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l) |
193 | #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) | 204 | #define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l) |
194 | 205 | ||
195 | #define writeb(v,c) __raw_writeb(v,__mem_pci(c)) | ||
196 | #define writew(v,c) __raw_writew((__force __u16) \ | ||
197 | cpu_to_le16(v),__mem_pci(c)) | ||
198 | #define writel(v,c) __raw_writel((__force __u32) \ | ||
199 | cpu_to_le32(v),__mem_pci(c)) | ||
200 | |||
201 | #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) | 206 | #define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l) |
202 | #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) | 207 | #define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l) |
203 | #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) | 208 | #define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l) |