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authorBen Dooks <ben-linux@fluff.org>2006-08-31 10:26:37 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-08-31 10:26:37 -0400
commitf105a7dfc5e81c28dd23ebf2328e42972e2cf240 (patch)
treece38e1802bef52e03f9f16acc5344322d2ddc4f6
parent851fb304b510fc1e5dc5852cda25361219c1c4b1 (diff)
[ARM] 3764/1: S3C24XX: change type naming to kernel style
Patch from Ben Dooks The type naming in the s3c24xx dma code is riddled with typedefs creating _t types, from the code import from 2.4 which is contrary to the current Kernel coding style. This patch cleans this up, removing the typedefs and and fixing up the resultant code changes. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/mach-s3c2410/dma.c88
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h80
2 files changed, 80 insertions, 88 deletions
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 25855452fe8c..cc92a7b2db88 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -60,7 +60,7 @@ static void __iomem *dma_base;
60static kmem_cache_t *dma_kmem; 60static kmem_cache_t *dma_kmem;
61 61
62/* dma channel state information */ 62/* dma channel state information */
63s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS]; 63struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
64 64
65/* debugging functions */ 65/* debugging functions */
66 66
@@ -74,7 +74,7 @@ s3c2410_dma_chan_t s3c2410_chans[S3C2410_DMA_CHANNELS];
74#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg)) 74#define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
75#else 75#else
76static inline void 76static inline void
77dma_wrreg(s3c2410_dma_chan_t *chan, int reg, unsigned long val) 77dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
78{ 78{
79 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg); 79 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
80 writel(val, dma_regaddr(chan, reg)); 80 writel(val, dma_regaddr(chan, reg));
@@ -102,7 +102,7 @@ struct s3c2410_dma_regstate {
102*/ 102*/
103 103
104static void 104static void
105dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs) 105dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
106{ 106{
107 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC); 107 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
108 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC); 108 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
@@ -112,7 +112,7 @@ dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs)
112} 112}
113 113
114static void 114static void
115dmadbg_dumpregs(const char *fname, int line, s3c2410_dma_chan_t *chan, 115dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
116 struct s3c2410_dma_regstate *regs) 116 struct s3c2410_dma_regstate *regs)
117{ 117{
118 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", 118 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
@@ -122,7 +122,7 @@ dmadbg_dumpregs(const char *fname, int line, s3c2410_dma_chan_t *chan,
122} 122}
123 123
124static void 124static void
125dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan) 125dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
126{ 126{
127 struct s3c2410_dma_regstate state; 127 struct s3c2410_dma_regstate state;
128 128
@@ -136,7 +136,7 @@ dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan)
136} 136}
137 137
138static void 138static void
139dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan) 139dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
140{ 140{
141 struct s3c2410_dma_regstate state; 141 struct s3c2410_dma_regstate state;
142 142
@@ -164,7 +164,7 @@ dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan)
164*/ 164*/
165 165
166static void 166static void
167s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val) 167s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
168{ 168{
169 if (stats == NULL) 169 if (stats == NULL)
170 return; 170 return;
@@ -183,7 +183,7 @@ s3c2410_dma_stats_timeout(s3c2410_dma_stats_t *stats, int val)
183*/ 183*/
184 184
185static int 185static int
186s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line) 186s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
187{ 187{
188 int timeout = chan->load_timeout; 188 int timeout = chan->load_timeout;
189 int took; 189 int took;
@@ -230,8 +230,8 @@ s3c2410_dma_waitforload(s3c2410_dma_chan_t *chan, int line)
230*/ 230*/
231 231
232static inline int 232static inline int
233s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan, 233s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
234 s3c2410_dma_buf_t *buf) 234 struct s3c2410_dma_buf *buf)
235{ 235{
236 unsigned long reload; 236 unsigned long reload;
237 237
@@ -304,7 +304,7 @@ s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan,
304*/ 304*/
305 305
306static void 306static void
307s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op) 307s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
308{ 308{
309 if (chan->op_fn != NULL) { 309 if (chan->op_fn != NULL) {
310 (chan->op_fn)(chan, op); 310 (chan->op_fn)(chan, op);
@@ -318,8 +318,8 @@ s3c2410_dma_call_op(s3c2410_dma_chan_t *chan, s3c2410_chan_op_t op)
318*/ 318*/
319 319
320static inline void 320static inline void
321s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf, 321s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
322 s3c2410_dma_buffresult_t result) 322 enum s3c2410_dma_buffresult result)
323{ 323{
324 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n", 324 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
325 chan->callback_fn, buf, buf->id, buf->size, result); 325 chan->callback_fn, buf, buf->id, buf->size, result);
@@ -334,7 +334,7 @@ s3c2410_dma_buffdone(s3c2410_dma_chan_t *chan, s3c2410_dma_buf_t *buf,
334 * start a dma channel going 334 * start a dma channel going
335*/ 335*/
336 336
337static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) 337static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
338{ 338{
339 unsigned long tmp; 339 unsigned long tmp;
340 unsigned long flags; 340 unsigned long flags;
@@ -430,7 +430,7 @@ static int s3c2410_dma_start(s3c2410_dma_chan_t *chan)
430*/ 430*/
431 431
432static int 432static int
433s3c2410_dma_canload(s3c2410_dma_chan_t *chan) 433s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
434{ 434{
435 if (chan->load_state == S3C2410_DMALOAD_NONE || 435 if (chan->load_state == S3C2410_DMALOAD_NONE ||
436 chan->load_state == S3C2410_DMALOAD_1RUNNING) 436 chan->load_state == S3C2410_DMALOAD_1RUNNING)
@@ -460,8 +460,8 @@ s3c2410_dma_canload(s3c2410_dma_chan_t *chan)
460int s3c2410_dma_enqueue(unsigned int channel, void *id, 460int s3c2410_dma_enqueue(unsigned int channel, void *id,
461 dma_addr_t data, int size) 461 dma_addr_t data, int size)
462{ 462{
463 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 463 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
464 s3c2410_dma_buf_t *buf; 464 struct s3c2410_dma_buf *buf;
465 unsigned long flags; 465 unsigned long flags;
466 466
467 check_channel(channel); 467 check_channel(channel);
@@ -540,7 +540,7 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id,
540EXPORT_SYMBOL(s3c2410_dma_enqueue); 540EXPORT_SYMBOL(s3c2410_dma_enqueue);
541 541
542static inline void 542static inline void
543s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf) 543s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
544{ 544{
545 int magicok = (buf->magic == BUF_MAGIC); 545 int magicok = (buf->magic == BUF_MAGIC);
546 546
@@ -560,7 +560,7 @@ s3c2410_dma_freebuf(s3c2410_dma_buf_t *buf)
560*/ 560*/
561 561
562static inline void 562static inline void
563s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan) 563s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
564{ 564{
565 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n", 565 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
566 chan->number, chan->load_state); 566 chan->number, chan->load_state);
@@ -601,8 +601,8 @@ s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan)
601static irqreturn_t 601static irqreturn_t
602s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) 602s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
603{ 603{
604 s3c2410_dma_chan_t *chan = (s3c2410_dma_chan_t *)devpw; 604 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
605 s3c2410_dma_buf_t *buf; 605 struct s3c2410_dma_buf *buf;
606 606
607 buf = chan->curr; 607 buf = chan->curr;
608 608
@@ -731,10 +731,10 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs)
731 * get control of an dma channel 731 * get control of an dma channel
732*/ 732*/
733 733
734int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, 734int s3c2410_dma_request(unsigned int channel, struct s3c2410_dma_client *client,
735 void *dev) 735 void *dev)
736{ 736{
737 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 737 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
738 unsigned long flags; 738 unsigned long flags;
739 int err; 739 int err;
740 740
@@ -807,9 +807,9 @@ EXPORT_SYMBOL(s3c2410_dma_request);
807 * allowed to go through. 807 * allowed to go through.
808*/ 808*/
809 809
810int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client) 810int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
811{ 811{
812 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 812 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
813 unsigned long flags; 813 unsigned long flags;
814 814
815 check_channel(channel); 815 check_channel(channel);
@@ -846,7 +846,7 @@ int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
846 846
847EXPORT_SYMBOL(s3c2410_dma_free); 847EXPORT_SYMBOL(s3c2410_dma_free);
848 848
849static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) 849static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
850{ 850{
851 unsigned long tmp; 851 unsigned long tmp;
852 unsigned long flags; 852 unsigned long flags;
@@ -880,7 +880,7 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan)
880 return 0; 880 return 0;
881} 881}
882 882
883void s3c2410_dma_waitforstop(s3c2410_dma_chan_t *chan) 883void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
884{ 884{
885 unsigned long tmp; 885 unsigned long tmp;
886 unsigned int timeout = 0x10000; 886 unsigned int timeout = 0x10000;
@@ -901,9 +901,9 @@ void s3c2410_dma_waitforstop(s3c2410_dma_chan_t *chan)
901 * stop the channel, and remove all current and pending transfers 901 * stop the channel, and remove all current and pending transfers
902*/ 902*/
903 903
904static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) 904static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
905{ 905{
906 s3c2410_dma_buf_t *buf, *next; 906 struct s3c2410_dma_buf *buf, *next;
907 unsigned long flags; 907 unsigned long flags;
908 908
909 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); 909 pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
@@ -958,7 +958,7 @@ static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan)
958} 958}
959 959
960int 960int
961s3c2410_dma_started(s3c2410_dma_chan_t *chan) 961s3c2410_dma_started(struct s3c2410_dma_chan *chan)
962{ 962{
963 unsigned long flags; 963 unsigned long flags;
964 964
@@ -995,9 +995,9 @@ s3c2410_dma_started(s3c2410_dma_chan_t *chan)
995} 995}
996 996
997int 997int
998s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) 998s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
999{ 999{
1000 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1000 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1001 1001
1002 check_channel(channel); 1002 check_channel(channel);
1003 1003
@@ -1046,7 +1046,7 @@ int s3c2410_dma_config(dmach_t channel,
1046 int xferunit, 1046 int xferunit,
1047 int dcon) 1047 int dcon)
1048{ 1048{
1049 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1049 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1050 1050
1051 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n", 1051 pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1052 __FUNCTION__, channel, xferunit, dcon); 1052 __FUNCTION__, channel, xferunit, dcon);
@@ -1086,7 +1086,7 @@ EXPORT_SYMBOL(s3c2410_dma_config);
1086 1086
1087int s3c2410_dma_setflags(dmach_t channel, unsigned int flags) 1087int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1088{ 1088{
1089 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1089 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1090 1090
1091 check_channel(channel); 1091 check_channel(channel);
1092 1092
@@ -1106,7 +1106,7 @@ EXPORT_SYMBOL(s3c2410_dma_setflags);
1106 1106
1107int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn) 1107int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1108{ 1108{
1109 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1109 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1110 1110
1111 check_channel(channel); 1111 check_channel(channel);
1112 1112
@@ -1121,7 +1121,7 @@ EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1121 1121
1122int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn) 1122int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1123{ 1123{
1124 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1124 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1125 1125
1126 check_channel(channel); 1126 check_channel(channel);
1127 1127
@@ -1149,11 +1149,11 @@ EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1149*/ 1149*/
1150 1150
1151int s3c2410_dma_devconfig(int channel, 1151int s3c2410_dma_devconfig(int channel,
1152 s3c2410_dmasrc_t source, 1152 enum s3c2410_dmasrc source,
1153 int hwcfg, 1153 int hwcfg,
1154 unsigned long devaddr) 1154 unsigned long devaddr)
1155{ 1155{
1156 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1156 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1157 1157
1158 check_channel(channel); 1158 check_channel(channel);
1159 1159
@@ -1200,7 +1200,7 @@ EXPORT_SYMBOL(s3c2410_dma_devconfig);
1200 1200
1201int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst) 1201int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1202{ 1202{
1203 s3c2410_dma_chan_t *chan = &s3c2410_chans[channel]; 1203 struct s3c2410_dma_chan *chan = &s3c2410_chans[channel];
1204 1204
1205 check_channel(channel); 1205 check_channel(channel);
1206 1206
@@ -1222,7 +1222,7 @@ EXPORT_SYMBOL(s3c2410_dma_getposition);
1222 1222
1223static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) 1223static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1224{ 1224{
1225 s3c2410_dma_chan_t *cp = container_of(dev, s3c2410_dma_chan_t, dev); 1225 struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev);
1226 1226
1227 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number); 1227 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1228 1228
@@ -1262,7 +1262,7 @@ static struct sysdev_class dma_sysclass = {
1262 1262
1263static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f) 1263static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f)
1264{ 1264{
1265 memset(p, 0, sizeof(s3c2410_dma_buf_t)); 1265 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1266} 1266}
1267 1267
1268 1268
@@ -1270,7 +1270,7 @@ static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f)
1270 1270
1271static int __init s3c2410_init_dma(void) 1271static int __init s3c2410_init_dma(void)
1272{ 1272{
1273 s3c2410_dma_chan_t *cp; 1273 struct s3c2410_dma_chan *cp;
1274 int channel; 1274 int channel;
1275 int ret; 1275 int ret;
1276 1276
@@ -1288,7 +1288,7 @@ static int __init s3c2410_init_dma(void)
1288 goto err; 1288 goto err;
1289 } 1289 }
1290 1290
1291 dma_kmem = kmem_cache_create("dma_desc", sizeof(s3c2410_dma_buf_t), 0, 1291 dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
1292 SLAB_HWCACHE_ALIGN, 1292 SLAB_HWCACHE_ALIGN,
1293 s3c2410_dma_cache_ctor, NULL); 1293 s3c2410_dma_cache_ctor, NULL);
1294 1294
@@ -1301,7 +1301,7 @@ static int __init s3c2410_init_dma(void)
1301 for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) { 1301 for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
1302 cp = &s3c2410_chans[channel]; 1302 cp = &s3c2410_chans[channel];
1303 1303
1304 memset(cp, 0, sizeof(s3c2410_dma_chan_t)); 1304 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1305 1305
1306 /* dma channel irqs are in order.. */ 1306 /* dma channel irqs are in order.. */
1307 cp->number = channel; 1307 cp->number = channel;
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 7463fd5252ce..46e65409fcc5 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -35,14 +35,14 @@
35 35
36/* types */ 36/* types */
37 37
38typedef enum { 38enum s3c2410_dma_state {
39 S3C2410_DMA_IDLE, 39 S3C2410_DMA_IDLE,
40 S3C2410_DMA_RUNNING, 40 S3C2410_DMA_RUNNING,
41 S3C2410_DMA_PAUSED 41 S3C2410_DMA_PAUSED
42} s3c2410_dma_state_t; 42};
43 43
44 44
45/* s3c2410_dma_loadst_t 45/* enum s3c2410_dma_loadst
46 * 46 *
47 * This represents the state of the DMA engine, wrt to the loaded / running 47 * This represents the state of the DMA engine, wrt to the loaded / running
48 * transfers. Since we don't have any way of knowing exactly the state of 48 * transfers. Since we don't have any way of knowing exactly the state of
@@ -70,34 +70,32 @@ typedef enum {
70 * currently running. 70 * currently running.
71*/ 71*/
72 72
73typedef enum { 73enum s3c2410_dma_loadst {
74 S3C2410_DMALOAD_NONE, 74 S3C2410_DMALOAD_NONE,
75 S3C2410_DMALOAD_1LOADED, 75 S3C2410_DMALOAD_1LOADED,
76 S3C2410_DMALOAD_1RUNNING, 76 S3C2410_DMALOAD_1RUNNING,
77 S3C2410_DMALOAD_1LOADED_1RUNNING, 77 S3C2410_DMALOAD_1LOADED_1RUNNING,
78} s3c2410_dma_loadst_t; 78};
79 79
80typedef enum { 80enum s3c2410_dma_buffresult {
81 S3C2410_RES_OK, 81 S3C2410_RES_OK,
82 S3C2410_RES_ERR, 82 S3C2410_RES_ERR,
83 S3C2410_RES_ABORT 83 S3C2410_RES_ABORT
84} s3c2410_dma_buffresult_t; 84};
85
86 85
87typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
88 86
89enum s3c2410_dmasrc_e { 87enum s3c2410_dmasrc {
90 S3C2410_DMASRC_HW, /* source is memory */ 88 S3C2410_DMASRC_HW, /* source is memory */
91 S3C2410_DMASRC_MEM /* source is hardware */ 89 S3C2410_DMASRC_MEM /* source is hardware */
92}; 90};
93 91
94/* enum s3c2410_chan_op_e 92/* enum s3c2410_chan_op
95 * 93 *
96 * operation codes passed to the DMA code by the user, and also used 94 * operation codes passed to the DMA code by the user, and also used
97 * to inform the current channel owner of any changes to the system state 95 * to inform the current channel owner of any changes to the system state
98*/ 96*/
99 97
100enum s3c2410_chan_op_e { 98enum s3c2410_chan_op {
101 S3C2410_DMAOP_START, 99 S3C2410_DMAOP_START,
102 S3C2410_DMAOP_STOP, 100 S3C2410_DMAOP_STOP,
103 S3C2410_DMAOP_PAUSE, 101 S3C2410_DMAOP_PAUSE,
@@ -107,8 +105,6 @@ enum s3c2410_chan_op_e {
107 S3C2410_DMAOP_STARTED, /* indicate channel started */ 105 S3C2410_DMAOP_STARTED, /* indicate channel started */
108}; 106};
109 107
110typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
111
112/* flags */ 108/* flags */
113 109
114#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about 110#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
@@ -117,22 +113,19 @@ typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
117 113
118/* dma buffer */ 114/* dma buffer */
119 115
120typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
121
122struct s3c2410_dma_client { 116struct s3c2410_dma_client {
123 char *name; 117 char *name;
124}; 118};
125 119
126typedef struct s3c2410_dma_client s3c2410_dma_client_t;
127
128/* s3c2410_dma_buf_s 120/* s3c2410_dma_buf_s
129 * 121 *
130 * internally used buffer structure to describe a queued or running 122 * internally used buffer structure to describe a queued or running
131 * buffer. 123 * buffer.
132*/ 124*/
133 125
134struct s3c2410_dma_buf_s { 126struct s3c2410_dma_buf;
135 s3c2410_dma_buf_t *next; 127struct s3c2410_dma_buf {
128 struct s3c2410_dma_buf *next;
136 int magic; /* magic */ 129 int magic; /* magic */
137 int size; /* buffer size in bytes */ 130 int size; /* buffer size in bytes */
138 dma_addr_t data; /* start of DMA data */ 131 dma_addr_t data; /* start of DMA data */
@@ -142,20 +135,21 @@ struct s3c2410_dma_buf_s {
142 135
143/* [1] is this updated for both recv/send modes? */ 136/* [1] is this updated for both recv/send modes? */
144 137
145typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; 138struct s3c2410_dma_chan;
146 139
147/* s3c2410_dma_cbfn_t 140/* s3c2410_dma_cbfn_t
148 * 141 *
149 * buffer callback routine type 142 * buffer callback routine type
150*/ 143*/
151 144
152typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, 145typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
153 s3c2410_dma_buffresult_t result); 146 void *buf, int size,
147 enum s3c2410_dma_buffresult result);
154 148
155typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, 149typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
156 s3c2410_chan_op_t ); 150 enum s3c2410_chan_op );
157 151
158struct s3c2410_dma_stats_s { 152struct s3c2410_dma_stats {
159 unsigned long loads; 153 unsigned long loads;
160 unsigned long timeout_longest; 154 unsigned long timeout_longest;
161 unsigned long timeout_shortest; 155 unsigned long timeout_shortest;
@@ -163,14 +157,12 @@ struct s3c2410_dma_stats_s {
163 unsigned long timeout_failed; 157 unsigned long timeout_failed;
164}; 158};
165 159
166typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; 160/* struct s3c2410_dma_chan
167
168/* struct s3c2410_dma_chan_s
169 * 161 *
170 * full state information for each DMA channel 162 * full state information for each DMA channel
171*/ 163*/
172 164
173struct s3c2410_dma_chan_s { 165struct s3c2410_dma_chan {
174 /* channel state flags and information */ 166 /* channel state flags and information */
175 unsigned char number; /* number of this dma channel */ 167 unsigned char number; /* number of this dma channel */
176 unsigned char in_use; /* channel allocated */ 168 unsigned char in_use; /* channel allocated */
@@ -180,12 +172,12 @@ struct s3c2410_dma_chan_s {
180 172
181 /* channel state */ 173 /* channel state */
182 174
183 s3c2410_dma_state_t state; 175 enum s3c2410_dma_state state;
184 s3c2410_dma_loadst_t load_state; 176 enum s3c2410_dma_loadst load_state;
185 s3c2410_dma_client_t *client; 177 struct s3c2410_dma_client *client;
186 178
187 /* channel configuration */ 179 /* channel configuration */
188 s3c2410_dmasrc_t source; 180 enum s3c2410_dmasrc source;
189 unsigned long dev_addr; 181 unsigned long dev_addr;
190 unsigned long load_timeout; 182 unsigned long load_timeout;
191 unsigned int flags; /* channel flags */ 183 unsigned int flags; /* channel flags */
@@ -201,20 +193,20 @@ struct s3c2410_dma_chan_s {
201 s3c2410_dma_opfn_t op_fn; /* channel operation callback */ 193 s3c2410_dma_opfn_t op_fn; /* channel operation callback */
202 194
203 /* stats gathering */ 195 /* stats gathering */
204 s3c2410_dma_stats_t *stats; 196 struct s3c2410_dma_stats *stats;
205 s3c2410_dma_stats_t stats_store; 197 struct s3c2410_dma_stats stats_store;
206 198
207 /* buffer list and information */ 199 /* buffer list and information */
208 s3c2410_dma_buf_t *curr; /* current dma buffer */ 200 struct s3c2410_dma_buf *curr; /* current dma buffer */
209 s3c2410_dma_buf_t *next; /* next buffer to load */ 201 struct s3c2410_dma_buf *next; /* next buffer to load */
210 s3c2410_dma_buf_t *end; /* end of queue */ 202 struct s3c2410_dma_buf *end; /* end of queue */
211 203
212 /* system device */ 204 /* system device */
213 struct sys_device dev; 205 struct sys_device dev;
214}; 206};
215 207
216/* the currently allocated channel information */ 208/* the currently allocated channel information */
217extern s3c2410_dma_chan_t s3c2410_chans[]; 209extern struct s3c2410_dma_chan s3c2410_chans[];
218 210
219/* note, we don't really use dma_device_t at the moment */ 211/* note, we don't really use dma_device_t at the moment */
220typedef unsigned long dma_device_t; 212typedef unsigned long dma_device_t;
@@ -227,7 +219,7 @@ typedef unsigned long dma_device_t;
227*/ 219*/
228 220
229extern int s3c2410_dma_request(dmach_t channel, 221extern int s3c2410_dma_request(dmach_t channel,
230 s3c2410_dma_client_t *, void *dev); 222 struct s3c2410_dma_client *, void *dev);
231 223
232 224
233/* s3c2410_dma_ctrl 225/* s3c2410_dma_ctrl
@@ -235,7 +227,7 @@ extern int s3c2410_dma_request(dmach_t channel,
235 * change the state of the dma channel 227 * change the state of the dma channel
236*/ 228*/
237 229
238extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); 230extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
239 231
240/* s3c2410_dma_setflags 232/* s3c2410_dma_setflags
241 * 233 *
@@ -250,7 +242,7 @@ extern int s3c2410_dma_setflags(dmach_t channel,
250 * free the dma channel (will also abort any outstanding operations) 242 * free the dma channel (will also abort any outstanding operations)
251*/ 243*/
252 244
253extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); 245extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
254 246
255/* s3c2410_dma_enqueue 247/* s3c2410_dma_enqueue
256 * 248 *
@@ -274,7 +266,7 @@ extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
274 * configure the device we're talking to 266 * configure the device we're talking to
275*/ 267*/
276 268
277extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, 269extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
278 int hwcfg, unsigned long devaddr); 270 int hwcfg, unsigned long devaddr);
279 271
280/* s3c2410_dma_getposition 272/* s3c2410_dma_getposition