drm: Add the basic check for the detailed timing in EDID

Sometimes we will get the incorrect display modeline when parsing the detailed
timing in EDID. For example:
   >hsync/vsync width is zero
   >sync is beyond the blank.

So add the basic check for the detailed timing in EDID to avoid the incorrect
display modeline.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index 3c0d2b3aed76..cea665d86dd3 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -626,6 +626,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
                 return NULL;
         }
 
+        /* it is incorrect if hsync/vsync width is zero */
+        if (!hsync_pulse_width || !vsync_pulse_width) {
+                DRM_DEBUG_KMS("Incorrect Detailed timing. "
+                                "Wrong Hsync/Vsync pulse width\n");
+                return NULL;
+        }
         mode = drm_mode_create(dev);
         if (!mode)
                 return NULL;
@@ -647,6 +653,15 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
         mode->vsync_end = mode->vsync_start + vsync_pulse_width;
         mode->vtotal = mode->vdisplay + vblank;
 
+        /* perform the basic check for the detailed timing */
+        if (mode->hsync_end > mode->htotal ||
+                mode->vsync_end > mode->vtotal) {
+                drm_mode_destroy(dev, mode);
+                DRM_DEBUG_KMS("Incorrect detailed timing. "
+                                "Sync is beyond the blank.\n");
+                return NULL;
+        }
+
         drm_mode_set_name(mode);
 
         if (pt->misc & DRM_EDID_PT_INTERLACED)