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authorRussell King <rmk+kernel@arm.linux.org.uk>2009-10-24 17:36:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-10-29 15:13:09 -0400
commitdf71dfd4ca01130f98d9dbfab76c440d72a177c6 (patch)
tree5050d23a67be5fc5fabd4e6d96ac89786fb2a9c9
parent657e12fd388899502d47f9f6f9d276ec9ced8add (diff)
ARM: Fix errata 411920 workarounds
Errata 411920 indicates that any "invalidate entire instruction cache" operation can fail if the right conditions are present. This is not limited just to those operations in flush.c, but elsewhere. Place the workaround in the already existing __flush_icache_all() function instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/include/asm/cacheflush.h5
-rw-r--r--arch/arm/mm/context.c5
-rw-r--r--arch/arm/mm/flush.c31
3 files changed, 12 insertions, 29 deletions
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index fd03fb63a332..3d0cdd21b882 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -414,9 +414,14 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
414 414
415static inline void __flush_icache_all(void) 415static inline void __flush_icache_all(void)
416{ 416{
417#ifdef CONFIG_ARM_ERRATA_411920
418 extern void v6_icache_inval_all(void);
419 v6_icache_inval_all();
420#else
417 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 421 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
418 : 422 :
419 : "r" (0)); 423 : "r" (0));
424#endif
420} 425}
421 426
422#define ARCH_HAS_FLUSH_ANON_PAGE 427#define ARCH_HAS_FLUSH_ANON_PAGE
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 6bda76a43199..a9e22e31eaa1 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -50,10 +50,7 @@ void __new_context(struct mm_struct *mm)
50 isb(); 50 isb();
51 flush_tlb_all(); 51 flush_tlb_all();
52 if (icache_is_vivt_asid_tagged()) { 52 if (icache_is_vivt_asid_tagged()) {
53 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 53 __flush_icache_all();
54 "mcr p15, 0, %0, c7, c5, 6 @ flush BTAC/BTB\n"
55 :
56 : "r" (0));
57 dsb(); 54 dsb();
58 } 55 }
59 } 56 }
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index b27942909b23..7f294f307c83 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -18,10 +18,6 @@
18 18
19#include "mm.h" 19#include "mm.h"
20 20
21#ifdef CONFIG_ARM_ERRATA_411920
22extern void v6_icache_inval_all(void);
23#endif
24
25#ifdef CONFIG_CPU_CACHE_VIPT 21#ifdef CONFIG_CPU_CACHE_VIPT
26 22
27#define ALIAS_FLUSH_START 0xffff4000 23#define ALIAS_FLUSH_START 0xffff4000
@@ -35,16 +31,11 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
35 flush_tlb_kernel_page(to); 31 flush_tlb_kernel_page(to);
36 32
37 asm( "mcrr p15, 0, %1, %0, c14\n" 33 asm( "mcrr p15, 0, %1, %0, c14\n"
38 " mcr p15, 0, %2, c7, c10, 4\n" 34 " mcr p15, 0, %2, c7, c10, 4"
39#ifndef CONFIG_ARM_ERRATA_411920
40 " mcr p15, 0, %2, c7, c5, 0\n"
41#endif
42 : 35 :
43 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) 36 : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
44 : "cc"); 37 : "cc");
45#ifdef CONFIG_ARM_ERRATA_411920 38 __flush_icache_all();
46 v6_icache_inval_all();
47#endif
48} 39}
49 40
50void flush_cache_mm(struct mm_struct *mm) 41void flush_cache_mm(struct mm_struct *mm)
@@ -57,16 +48,11 @@ void flush_cache_mm(struct mm_struct *mm)
57 48
58 if (cache_is_vipt_aliasing()) { 49 if (cache_is_vipt_aliasing()) {
59 asm( "mcr p15, 0, %0, c7, c14, 0\n" 50 asm( "mcr p15, 0, %0, c7, c14, 0\n"
60 " mcr p15, 0, %0, c7, c10, 4\n" 51 " mcr p15, 0, %0, c7, c10, 4"
61#ifndef CONFIG_ARM_ERRATA_411920
62 " mcr p15, 0, %0, c7, c5, 0\n"
63#endif
64 : 52 :
65 : "r" (0) 53 : "r" (0)
66 : "cc"); 54 : "cc");
67#ifdef CONFIG_ARM_ERRATA_411920 55 __flush_icache_all();
68 v6_icache_inval_all();
69#endif
70 } 56 }
71} 57}
72 58
@@ -81,16 +67,11 @@ void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
81 67
82 if (cache_is_vipt_aliasing()) { 68 if (cache_is_vipt_aliasing()) {
83 asm( "mcr p15, 0, %0, c7, c14, 0\n" 69 asm( "mcr p15, 0, %0, c7, c14, 0\n"
84 " mcr p15, 0, %0, c7, c10, 4\n" 70 " mcr p15, 0, %0, c7, c10, 4"
85#ifndef CONFIG_ARM_ERRATA_411920
86 " mcr p15, 0, %0, c7, c5, 0\n"
87#endif
88 : 71 :
89 : "r" (0) 72 : "r" (0)
90 : "cc"); 73 : "cc");
91#ifdef CONFIG_ARM_ERRATA_411920 74 __flush_icache_all();
92 v6_icache_inval_all();
93#endif
94 } 75 }
95} 76}
96 77